]> git.proxmox.com Git - mirror_qemu.git/blame - target/ppc/translate/vmx-impl.inc.c
projects / mirror_qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
spapr: Add forgotten capability to migration stream
[mirror_qemu.git] / target / ppc / translate / vmx-impl.inc.c
CommitLineData
0304af89
BH		 1/*
2 * translate/vmx-impl.c
3 *
4 * Altivec/VMX translation
5 */
6
7/*** Altivec vector extension ***/
8/* Altivec registers moves */
9
10static inline TCGv_ptr gen_avr_ptr(int reg)
11{
12 TCGv_ptr r = tcg_temp_new_ptr();
c82a8a85 13 tcg_gen_addi_ptr(r, cpu_env, avr_full_offset(reg));
0304af89
BH		 14 return r;
15}
16
17#define GEN_VR_LDX(name, opc2, opc3) \
32553866 18static void glue(gen_, name)(DisasContext *ctx) \
0304af89
BH		 19{ \
20 TCGv EA; \
c4a18dbf 21 TCGv_i64 avr; \
0304af89
BH		 22 if (unlikely(!ctx->altivec_enabled)) { \
23 gen_exception(ctx, POWERPC_EXCP_VPU); \
24 return; \
25 } \
26 gen_set_access_type(ctx, ACCESS_INT); \
c4a18dbf 27 avr = tcg_temp_new_i64(); \
0304af89
BH		 28 EA = tcg_temp_new(); \
29 gen_addr_reg_index(ctx, EA); \
30 tcg_gen_andi_tl(EA, EA, ~0xf); \
32553866
DG		 31 /* \
32 * We only need to swap high and low halves. gen_qemu_ld64_i64 \
33 * does necessary 64-bit byteswap already. \
34 */ \
0304af89 35 if (ctx->le_mode) { \
c4a18dbf
MCA		 36 gen_qemu_ld64_i64(ctx, avr, EA); \
37 set_avr64(rD(ctx->opcode), avr, false); \
0304af89 38 tcg_gen_addi_tl(EA, EA, 8); \
c4a18dbf
MCA		 39 gen_qemu_ld64_i64(ctx, avr, EA); \
40 set_avr64(rD(ctx->opcode), avr, true); \
0304af89 41 } else { \
c4a18dbf
MCA		 42 gen_qemu_ld64_i64(ctx, avr, EA); \
43 set_avr64(rD(ctx->opcode), avr, true); \
0304af89 44 tcg_gen_addi_tl(EA, EA, 8); \
c4a18dbf
MCA		 45 gen_qemu_ld64_i64(ctx, avr, EA); \
46 set_avr64(rD(ctx->opcode), avr, false); \
0304af89
BH		 47 } \
48 tcg_temp_free(EA); \
c4a18dbf 49 tcg_temp_free_i64(avr); \
0304af89
BH		 50}
51
52#define GEN_VR_STX(name, opc2, opc3) \
53static void gen_st##name(DisasContext *ctx) \
54{ \
55 TCGv EA; \
c4a18dbf 56 TCGv_i64 avr; \
0304af89
BH		 57 if (unlikely(!ctx->altivec_enabled)) { \
58 gen_exception(ctx, POWERPC_EXCP_VPU); \
59 return; \
60 } \
61 gen_set_access_type(ctx, ACCESS_INT); \
c4a18dbf 62 avr = tcg_temp_new_i64(); \
0304af89
BH		 63 EA = tcg_temp_new(); \
64 gen_addr_reg_index(ctx, EA); \
65 tcg_gen_andi_tl(EA, EA, ~0xf); \
32553866
DG		 66 /* \
67 * We only need to swap high and low halves. gen_qemu_st64_i64 \
68 * does necessary 64-bit byteswap already. \
69 */ \
0304af89 70 if (ctx->le_mode) { \
c4a18dbf
MCA		 71 get_avr64(avr, rD(ctx->opcode), false); \
72 gen_qemu_st64_i64(ctx, avr, EA); \
0304af89 73 tcg_gen_addi_tl(EA, EA, 8); \
c4a18dbf
MCA		 74 get_avr64(avr, rD(ctx->opcode), true); \
75 gen_qemu_st64_i64(ctx, avr, EA); \
0304af89 76 } else { \
c4a18dbf
MCA		 77 get_avr64(avr, rD(ctx->opcode), true); \
78 gen_qemu_st64_i64(ctx, avr, EA); \
0304af89 79 tcg_gen_addi_tl(EA, EA, 8); \
c4a18dbf
MCA		 80 get_avr64(avr, rD(ctx->opcode), false); \
81 gen_qemu_st64_i64(ctx, avr, EA); \
0304af89
BH		 82 } \
83 tcg_temp_free(EA); \
c4a18dbf 84 tcg_temp_free_i64(avr); \
0304af89
BH		 85}
86
87#define GEN_VR_LVE(name, opc2, opc3, size) \
88static void gen_lve##name(DisasContext *ctx) \
89 { \
90 TCGv EA; \
91 TCGv_ptr rs; \
92 if (unlikely(!ctx->altivec_enabled)) { \
93 gen_exception(ctx, POWERPC_EXCP_VPU); \
94 return; \
95 } \
96 gen_set_access_type(ctx, ACCESS_INT); \
97 EA = tcg_temp_new(); \
98 gen_addr_reg_index(ctx, EA); \
99 if (size > 1) { \
100 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
101 } \
102 rs = gen_avr_ptr(rS(ctx->opcode)); \
103 gen_helper_lve##name(cpu_env, rs, EA); \
104 tcg_temp_free(EA); \
105 tcg_temp_free_ptr(rs); \
106 }
107
108#define GEN_VR_STVE(name, opc2, opc3, size) \
109static void gen_stve##name(DisasContext *ctx) \
110 { \
111 TCGv EA; \
112 TCGv_ptr rs; \
113 if (unlikely(!ctx->altivec_enabled)) { \
114 gen_exception(ctx, POWERPC_EXCP_VPU); \
115 return; \
116 } \
117 gen_set_access_type(ctx, ACCESS_INT); \
118 EA = tcg_temp_new(); \
119 gen_addr_reg_index(ctx, EA); \
120 if (size > 1) { \
121 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
122 } \
123 rs = gen_avr_ptr(rS(ctx->opcode)); \
124 gen_helper_stve##name(cpu_env, rs, EA); \
125 tcg_temp_free(EA); \
126 tcg_temp_free_ptr(rs); \
127 }
128
129GEN_VR_LDX(lvx, 0x07, 0x03);
130/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
131GEN_VR_LDX(lvxl, 0x07, 0x0B);
132
133GEN_VR_LVE(bx, 0x07, 0x00, 1);
134GEN_VR_LVE(hx, 0x07, 0x01, 2);
135GEN_VR_LVE(wx, 0x07, 0x02, 4);
136
137GEN_VR_STX(svx, 0x07, 0x07);
138/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
139GEN_VR_STX(svxl, 0x07, 0x0F);
140
141GEN_VR_STVE(bx, 0x07, 0x04, 1);
142GEN_VR_STVE(hx, 0x07, 0x05, 2);
143GEN_VR_STVE(wx, 0x07, 0x06, 4);
144
145static void gen_lvsl(DisasContext *ctx)
146{
147 TCGv_ptr rd;
148 TCGv EA;
149 if (unlikely(!ctx->altivec_enabled)) {
150 gen_exception(ctx, POWERPC_EXCP_VPU);
151 return;
152 }
153 EA = tcg_temp_new();
154 gen_addr_reg_index(ctx, EA);
155 rd = gen_avr_ptr(rD(ctx->opcode));
156 gen_helper_lvsl(rd, EA);
157 tcg_temp_free(EA);
158 tcg_temp_free_ptr(rd);
159}
160
161static void gen_lvsr(DisasContext *ctx)
162{
163 TCGv_ptr rd;
164 TCGv EA;
165 if (unlikely(!ctx->altivec_enabled)) {
166 gen_exception(ctx, POWERPC_EXCP_VPU);
167 return;
168 }
169 EA = tcg_temp_new();
170 gen_addr_reg_index(ctx, EA);
171 rd = gen_avr_ptr(rD(ctx->opcode));
172 gen_helper_lvsr(rd, EA);
173 tcg_temp_free(EA);
174 tcg_temp_free_ptr(rd);
175}
176
177static void gen_mfvscr(DisasContext *ctx)
178{
179 TCGv_i32 t;
c4a18dbf 180 TCGv_i64 avr;
0304af89
BH		 181 if (unlikely(!ctx->altivec_enabled)) {
182 gen_exception(ctx, POWERPC_EXCP_VPU);
183 return;
184 }
c4a18dbf
MCA		 185 avr = tcg_temp_new_i64();
186 tcg_gen_movi_i64(avr, 0);
187 set_avr64(rD(ctx->opcode), avr, true);
0304af89 188 t = tcg_temp_new_i32();
cc2b90d7 189 gen_helper_mfvscr(t, cpu_env);
c4a18dbf
MCA		 190 tcg_gen_extu_i32_i64(avr, t);
191 set_avr64(rD(ctx->opcode), avr, false);
0304af89 192 tcg_temp_free_i32(t);
c4a18dbf 193 tcg_temp_free_i64(avr);
0304af89
BH		 194}
195
196static void gen_mtvscr(DisasContext *ctx)
197{
dedfaac7
RH		 198 TCGv_i32 val;
199 int bofs;
200
0304af89
BH		 201 if (unlikely(!ctx->altivec_enabled)) {
202 gen_exception(ctx, POWERPC_EXCP_VPU);
203 return;
204 }
dedfaac7
RH		 205
206 val = tcg_temp_new_i32();
c82a8a85 207 bofs = avr_full_offset(rB(ctx->opcode));
dedfaac7
RH		 208#ifdef HOST_WORDS_BIGENDIAN
209 bofs += 3 * 4;
210#endif
211
212 tcg_gen_ld_i32(val, cpu_env, bofs);
213 gen_helper_mtvscr(cpu_env, val);
214 tcg_temp_free_i32(val);
0304af89
BH		 215}
216
37ad52ba
VH		 217#define GEN_VX_VMUL10(name, add_cin, ret_carry) \
218static void glue(gen_, name)(DisasContext *ctx) \
219{ \
c4a18dbf
MCA		 220 TCGv_i64 t0; \
221 TCGv_i64 t1; \
222 TCGv_i64 t2; \
223 TCGv_i64 avr; \
37ad52ba
VH		 224 TCGv_i64 ten, z; \
225 \
226 if (unlikely(!ctx->altivec_enabled)) { \
227 gen_exception(ctx, POWERPC_EXCP_VPU); \
228 return; \
229 } \
230 \
c4a18dbf
MCA		 231 t0 = tcg_temp_new_i64(); \
232 t1 = tcg_temp_new_i64(); \
233 t2 = tcg_temp_new_i64(); \
234 avr = tcg_temp_new_i64(); \
37ad52ba
VH		 235 ten = tcg_const_i64(10); \
236 z = tcg_const_i64(0); \
237 \
238 if (add_cin) { \
c4a18dbf
MCA		 239 get_avr64(avr, rA(ctx->opcode), false); \
240 tcg_gen_mulu2_i64(t0, t1, avr, ten); \
241 get_avr64(avr, rB(ctx->opcode), false); \
242 tcg_gen_andi_i64(t2, avr, 0xF); \
243 tcg_gen_add2_i64(avr, t2, t0, t1, t2, z); \
244 set_avr64(rD(ctx->opcode), avr, false); \
37ad52ba 245 } else { \
c4a18dbf
MCA		 246 get_avr64(avr, rA(ctx->opcode), false); \
247 tcg_gen_mulu2_i64(avr, t2, avr, ten); \
248 set_avr64(rD(ctx->opcode), avr, false); \
37ad52ba
VH		 249 } \
250 \
251 if (ret_carry) { \
c4a18dbf
MCA		 252 get_avr64(avr, rA(ctx->opcode), true); \
253 tcg_gen_mulu2_i64(t0, t1, avr, ten); \
254 tcg_gen_add2_i64(t0, avr, t0, t1, t2, z); \
255 set_avr64(rD(ctx->opcode), avr, false); \
256 set_avr64(rD(ctx->opcode), z, true); \
37ad52ba 257 } else { \
c4a18dbf
MCA		 258 get_avr64(avr, rA(ctx->opcode), true); \
259 tcg_gen_mul_i64(t0, avr, ten); \
260 tcg_gen_add_i64(avr, t0, t2); \
261 set_avr64(rD(ctx->opcode), avr, true); \
37ad52ba
VH		 262 } \
263 \
264 tcg_temp_free_i64(t0); \
265 tcg_temp_free_i64(t1); \
266 tcg_temp_free_i64(t2); \
c4a18dbf 267 tcg_temp_free_i64(avr); \
37ad52ba
VH		 268 tcg_temp_free_i64(ten); \
269 tcg_temp_free_i64(z); \
270} \
271
272GEN_VX_VMUL10(vmul10uq, 0, 0);
273GEN_VX_VMUL10(vmul10euq, 1, 0);
274GEN_VX_VMUL10(vmul10cuq, 0, 1);
275GEN_VX_VMUL10(vmul10ecuq, 1, 1);
276
50d24aed
MCA		 277#define GEN_VXFORM_V(name, vece, tcg_op, opc2, opc3) \
278static void glue(gen_, name)(DisasContext *ctx) \
0304af89
BH		 279{ \
280 if (unlikely(!ctx->altivec_enabled)) { \
281 gen_exception(ctx, POWERPC_EXCP_VPU); \
282 return; \
283 } \
c4a18dbf 284 \
50d24aed 285 tcg_op(vece, \
c82a8a85
MCA		 286 avr_full_offset(rD(ctx->opcode)), \
287 avr_full_offset(rA(ctx->opcode)), \
288 avr_full_offset(rB(ctx->opcode)), \
50d24aed 289 16, 16); \
0304af89
BH		 290}
291
50d24aed
MCA		 292/* Logical operations */
293GEN_VXFORM_V(vand, MO_64, tcg_gen_gvec_and, 2, 16);
294GEN_VXFORM_V(vandc, MO_64, tcg_gen_gvec_andc, 2, 17);
295GEN_VXFORM_V(vor, MO_64, tcg_gen_gvec_or, 2, 18);
296GEN_VXFORM_V(vxor, MO_64, tcg_gen_gvec_xor, 2, 19);
297GEN_VXFORM_V(vnor, MO_64, tcg_gen_gvec_nor, 2, 20);
298GEN_VXFORM_V(veqv, MO_64, tcg_gen_gvec_eqv, 2, 26);
299GEN_VXFORM_V(vnand, MO_64, tcg_gen_gvec_nand, 2, 22);
300GEN_VXFORM_V(vorc, MO_64, tcg_gen_gvec_orc, 2, 21);
0304af89
BH		 301
302#define GEN_VXFORM(name, opc2, opc3) \
32553866 303static void glue(gen_, name)(DisasContext *ctx) \
0304af89
BH		 304{ \
305 TCGv_ptr ra, rb, rd; \
306 if (unlikely(!ctx->altivec_enabled)) { \
307 gen_exception(ctx, POWERPC_EXCP_VPU); \
308 return; \
309 } \
310 ra = gen_avr_ptr(rA(ctx->opcode)); \
311 rb = gen_avr_ptr(rB(ctx->opcode)); \
312 rd = gen_avr_ptr(rD(ctx->opcode)); \
32553866 313 gen_helper_##name(rd, ra, rb); \
0304af89
BH		 314 tcg_temp_free_ptr(ra); \
315 tcg_temp_free_ptr(rb); \
316 tcg_temp_free_ptr(rd); \
317}
318
319#define GEN_VXFORM_ENV(name, opc2, opc3) \
320static void glue(gen_, name)(DisasContext *ctx) \
321{ \
322 TCGv_ptr ra, rb, rd; \
323 if (unlikely(!ctx->altivec_enabled)) { \
324 gen_exception(ctx, POWERPC_EXCP_VPU); \
325 return; \
326 } \
327 ra = gen_avr_ptr(rA(ctx->opcode)); \
328 rb = gen_avr_ptr(rB(ctx->opcode)); \
329 rd = gen_avr_ptr(rD(ctx->opcode)); \
330 gen_helper_##name(cpu_env, rd, ra, rb); \
331 tcg_temp_free_ptr(ra); \
332 tcg_temp_free_ptr(rb); \
333 tcg_temp_free_ptr(rd); \
334}
335
336#define GEN_VXFORM3(name, opc2, opc3) \
337static void glue(gen_, name)(DisasContext *ctx) \
338{ \
339 TCGv_ptr ra, rb, rc, rd; \
340 if (unlikely(!ctx->altivec_enabled)) { \
341 gen_exception(ctx, POWERPC_EXCP_VPU); \
342 return; \
343 } \
344 ra = gen_avr_ptr(rA(ctx->opcode)); \
345 rb = gen_avr_ptr(rB(ctx->opcode)); \
346 rc = gen_avr_ptr(rC(ctx->opcode)); \
347 rd = gen_avr_ptr(rD(ctx->opcode)); \
348 gen_helper_##name(rd, ra, rb, rc); \
349 tcg_temp_free_ptr(ra); \
350 tcg_temp_free_ptr(rb); \
351 tcg_temp_free_ptr(rc); \
352 tcg_temp_free_ptr(rd); \
353}
354
355/*
356 * Support for Altivec instruction pairs that use bit 31 (Rc) as
357 * an opcode bit. In general, these pairs come from different
358 * versions of the ISA, so we must also support a pair of flags for
359 * each instruction.
360 */
361#define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
362static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
363{ \
364 if ((Rc(ctx->opcode) == 0) && \
365 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
366 gen_##name0(ctx); \
367 } else if ((Rc(ctx->opcode) == 1) && \
368 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
369 gen_##name1(ctx); \
370 } else { \
371 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
372 } \
373}
374
37ad52ba
VH		 375/* Adds support to provide invalid mask */
376#define GEN_VXFORM_DUAL_EXT(name0, flg0, flg2_0, inval0, \
377 name1, flg1, flg2_1, inval1) \
378static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
379{ \
380 if ((Rc(ctx->opcode) == 0) && \
381 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0)) && \
382 !(ctx->opcode & inval0)) { \
383 gen_##name0(ctx); \
384 } else if ((Rc(ctx->opcode) == 1) && \
385 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1)) && \
386 !(ctx->opcode & inval1)) { \
387 gen_##name1(ctx); \
388 } else { \
389 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
390 } \
391}
392
60caf221
AK		 393#define GEN_VXFORM_HETRO(name, opc2, opc3) \
394static void glue(gen_, name)(DisasContext *ctx) \
395{ \
396 TCGv_ptr rb; \
397 if (unlikely(!ctx->altivec_enabled)) { \
398 gen_exception(ctx, POWERPC_EXCP_VPU); \
399 return; \
400 } \
401 rb = gen_avr_ptr(rB(ctx->opcode)); \
402 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], rb); \
403 tcg_temp_free_ptr(rb); \
404}
405
3e942a1a 406GEN_VXFORM_V(vaddubm, MO_8, tcg_gen_gvec_add, 0, 0);
37ad52ba
VH		 407GEN_VXFORM_DUAL_EXT(vaddubm, PPC_ALTIVEC, PPC_NONE, 0, \
408 vmul10cuq, PPC_NONE, PPC2_ISA300, 0x0000F800)
3e942a1a 409GEN_VXFORM_V(vadduhm, MO_16, tcg_gen_gvec_add, 0, 1);
37ad52ba
VH		 410GEN_VXFORM_DUAL(vadduhm, PPC_ALTIVEC, PPC_NONE, \
411 vmul10ecuq, PPC_NONE, PPC2_ISA300)
3e942a1a
MCA		 412GEN_VXFORM_V(vadduwm, MO_32, tcg_gen_gvec_add, 0, 2);
413GEN_VXFORM_V(vaddudm, MO_64, tcg_gen_gvec_add, 0, 3);
414GEN_VXFORM_V(vsububm, MO_8, tcg_gen_gvec_sub, 0, 16);
415GEN_VXFORM_V(vsubuhm, MO_16, tcg_gen_gvec_sub, 0, 17);
416GEN_VXFORM_V(vsubuwm, MO_32, tcg_gen_gvec_sub, 0, 18);
417GEN_VXFORM_V(vsubudm, MO_64, tcg_gen_gvec_sub, 0, 19);
73e14c6a
RH		 418GEN_VXFORM_V(vmaxub, MO_8, tcg_gen_gvec_umax, 1, 0);
419GEN_VXFORM_V(vmaxuh, MO_16, tcg_gen_gvec_umax, 1, 1);
420GEN_VXFORM_V(vmaxuw, MO_32, tcg_gen_gvec_umax, 1, 2);
421GEN_VXFORM_V(vmaxud, MO_64, tcg_gen_gvec_umax, 1, 3);
422GEN_VXFORM_V(vmaxsb, MO_8, tcg_gen_gvec_smax, 1, 4);
423GEN_VXFORM_V(vmaxsh, MO_16, tcg_gen_gvec_smax, 1, 5);
424GEN_VXFORM_V(vmaxsw, MO_32, tcg_gen_gvec_smax, 1, 6);
425GEN_VXFORM_V(vmaxsd, MO_64, tcg_gen_gvec_smax, 1, 7);
426GEN_VXFORM_V(vminub, MO_8, tcg_gen_gvec_umin, 1, 8);
427GEN_VXFORM_V(vminuh, MO_16, tcg_gen_gvec_umin, 1, 9);
428GEN_VXFORM_V(vminuw, MO_32, tcg_gen_gvec_umin, 1, 10);
429GEN_VXFORM_V(vminud, MO_64, tcg_gen_gvec_umin, 1, 11);
430GEN_VXFORM_V(vminsb, MO_8, tcg_gen_gvec_smin, 1, 12);
431GEN_VXFORM_V(vminsh, MO_16, tcg_gen_gvec_smin, 1, 13);
432GEN_VXFORM_V(vminsw, MO_32, tcg_gen_gvec_smin, 1, 14);
433GEN_VXFORM_V(vminsd, MO_64, tcg_gen_gvec_smin, 1, 15);
0304af89 434GEN_VXFORM(vavgub, 1, 16);
37707059
SD		 435GEN_VXFORM(vabsdub, 1, 16);
436GEN_VXFORM_DUAL(vavgub, PPC_ALTIVEC, PPC_NONE, \
437 vabsdub, PPC_NONE, PPC2_ISA300)
0304af89 438GEN_VXFORM(vavguh, 1, 17);
37707059
SD		 439GEN_VXFORM(vabsduh, 1, 17);
440GEN_VXFORM_DUAL(vavguh, PPC_ALTIVEC, PPC_NONE, \
441 vabsduh, PPC_NONE, PPC2_ISA300)
0304af89 442GEN_VXFORM(vavguw, 1, 18);
37707059
SD		 443GEN_VXFORM(vabsduw, 1, 18);
444GEN_VXFORM_DUAL(vavguw, PPC_ALTIVEC, PPC_NONE, \
445 vabsduw, PPC_NONE, PPC2_ISA300)
0304af89
BH		 446GEN_VXFORM(vavgsb, 1, 20);
447GEN_VXFORM(vavgsh, 1, 21);
448GEN_VXFORM(vavgsw, 1, 22);
449GEN_VXFORM(vmrghb, 6, 0);
450GEN_VXFORM(vmrghh, 6, 1);
451GEN_VXFORM(vmrghw, 6, 2);
452GEN_VXFORM(vmrglb, 6, 4);
453GEN_VXFORM(vmrglh, 6, 5);
454GEN_VXFORM(vmrglw, 6, 6);
455
456static void gen_vmrgew(DisasContext *ctx)
457{
458 TCGv_i64 tmp;
c4a18dbf 459 TCGv_i64 avr;
0304af89
BH		 460 int VT, VA, VB;
461 if (unlikely(!ctx->altivec_enabled)) {
462 gen_exception(ctx, POWERPC_EXCP_VPU);
463 return;
464 }
465 VT = rD(ctx->opcode);
466 VA = rA(ctx->opcode);
467 VB = rB(ctx->opcode);
468 tmp = tcg_temp_new_i64();
c4a18dbf
MCA		 469 avr = tcg_temp_new_i64();
470
471 get_avr64(avr, VB, true);
472 tcg_gen_shri_i64(tmp, avr, 32);
473 get_avr64(avr, VA, true);
474 tcg_gen_deposit_i64(avr, avr, tmp, 0, 32);
475 set_avr64(VT, avr, true);
476
477 get_avr64(avr, VB, false);
478 tcg_gen_shri_i64(tmp, avr, 32);
479 get_avr64(avr, VA, false);
480 tcg_gen_deposit_i64(avr, avr, tmp, 0, 32);
481 set_avr64(VT, avr, false);
482
0304af89 483 tcg_temp_free_i64(tmp);
c4a18dbf 484 tcg_temp_free_i64(avr);
0304af89
BH		 485}
486
487static void gen_vmrgow(DisasContext *ctx)
488{
c4a18dbf
MCA		 489 TCGv_i64 t0, t1;
490 TCGv_i64 avr;
0304af89
BH		 491 int VT, VA, VB;
492 if (unlikely(!ctx->altivec_enabled)) {
493 gen_exception(ctx, POWERPC_EXCP_VPU);
494 return;
495 }
496 VT = rD(ctx->opcode);
497 VA = rA(ctx->opcode);
498 VB = rB(ctx->opcode);
c4a18dbf
MCA		 499 t0 = tcg_temp_new_i64();
500 t1 = tcg_temp_new_i64();
501 avr = tcg_temp_new_i64();
502
503 get_avr64(t0, VB, true);
504 get_avr64(t1, VA, true);
505 tcg_gen_deposit_i64(avr, t0, t1, 32, 32);
506 set_avr64(VT, avr, true);
507
508 get_avr64(t0, VB, false);
509 get_avr64(t1, VA, false);
510 tcg_gen_deposit_i64(avr, t0, t1, 32, 32);
511 set_avr64(VT, avr, false);
512
513 tcg_temp_free_i64(t0);
514 tcg_temp_free_i64(t1);
515 tcg_temp_free_i64(avr);
0304af89
BH		 516}
517
518GEN_VXFORM(vmuloub, 4, 0);
519GEN_VXFORM(vmulouh, 4, 1);
520GEN_VXFORM(vmulouw, 4, 2);
521GEN_VXFORM(vmuluwm, 4, 2);
522GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
523 vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
524GEN_VXFORM(vmulosb, 4, 4);
525GEN_VXFORM(vmulosh, 4, 5);
526GEN_VXFORM(vmulosw, 4, 6);
527GEN_VXFORM(vmuleub, 4, 8);
528GEN_VXFORM(vmuleuh, 4, 9);
529GEN_VXFORM(vmuleuw, 4, 10);
530GEN_VXFORM(vmulesb, 4, 12);
531GEN_VXFORM(vmulesh, 4, 13);
532GEN_VXFORM(vmulesw, 4, 14);
533GEN_VXFORM(vslb, 2, 4);
534GEN_VXFORM(vslh, 2, 5);
535GEN_VXFORM(vslw, 2, 6);
09a245e1
BR		 536GEN_VXFORM(vrlwnm, 2, 6);
537GEN_VXFORM_DUAL(vslw, PPC_ALTIVEC, PPC_NONE, \
538 vrlwnm, PPC_NONE, PPC2_ISA300)
0304af89
BH		 539GEN_VXFORM(vsld, 2, 23);
540GEN_VXFORM(vsrb, 2, 8);
541GEN_VXFORM(vsrh, 2, 9);
542GEN_VXFORM(vsrw, 2, 10);
543GEN_VXFORM(vsrd, 2, 27);
544GEN_VXFORM(vsrab, 2, 12);
545GEN_VXFORM(vsrah, 2, 13);
546GEN_VXFORM(vsraw, 2, 14);
547GEN_VXFORM(vsrad, 2, 15);
4004c1db 548GEN_VXFORM(vsrv, 2, 28);
5644a175 549GEN_VXFORM(vslv, 2, 29);
0304af89
BH		 550GEN_VXFORM(vslo, 6, 16);
551GEN_VXFORM(vsro, 6, 17);
552GEN_VXFORM(vaddcuw, 0, 6);
553GEN_VXFORM(vsubcuw, 0, 22);
fb11ae7d
RH		 554
555#define GEN_VXFORM_SAT(NAME, VECE, NORM, SAT, OPC2, OPC3) \
556static void glue(glue(gen_, NAME), _vec)(unsigned vece, TCGv_vec t, \
557 TCGv_vec sat, TCGv_vec a, \
558 TCGv_vec b) \
559{ \
560 TCGv_vec x = tcg_temp_new_vec_matching(t); \
561 glue(glue(tcg_gen_, NORM), _vec)(VECE, x, a, b); \
562 glue(glue(tcg_gen_, SAT), _vec)(VECE, t, a, b); \
563 tcg_gen_cmp_vec(TCG_COND_NE, VECE, x, x, t); \
564 tcg_gen_or_vec(VECE, sat, sat, x); \
565 tcg_temp_free_vec(x); \
566} \
567static void glue(gen_, NAME)(DisasContext *ctx) \
568{ \
53229a77
RH		 569 static const TCGOpcode vecop_list[] = { \
570 glue(glue(INDEX_op_, NORM), _vec), \
571 glue(glue(INDEX_op_, SAT), _vec), \
572 INDEX_op_cmp_vec, 0 \
573 }; \
fb11ae7d
RH		 574 static const GVecGen4 g = { \
575 .fniv = glue(glue(gen_, NAME), _vec), \
576 .fno = glue(gen_helper_, NAME), \
53229a77 577 .opt_opc = vecop_list, \
fb11ae7d
RH		 578 .write_aofs = true, \
579 .vece = VECE, \
580 }; \
581 if (unlikely(!ctx->altivec_enabled)) { \
582 gen_exception(ctx, POWERPC_EXCP_VPU); \
583 return; \
584 } \
c82a8a85 585 tcg_gen_gvec_4(avr_full_offset(rD(ctx->opcode)), \
fb11ae7d 586 offsetof(CPUPPCState, vscr_sat), \
c82a8a85
MCA		 587 avr_full_offset(rA(ctx->opcode)), \
588 avr_full_offset(rB(ctx->opcode)), \
fb11ae7d
RH		 589 16, 16, &g); \
590}
591
592GEN_VXFORM_SAT(vaddubs, MO_8, add, usadd, 0, 8);
37ad52ba
VH		 593GEN_VXFORM_DUAL_EXT(vaddubs, PPC_ALTIVEC, PPC_NONE, 0, \
594 vmul10uq, PPC_NONE, PPC2_ISA300, 0x0000F800)
fb11ae7d 595GEN_VXFORM_SAT(vadduhs, MO_16, add, usadd, 0, 9);
37ad52ba
VH		 596GEN_VXFORM_DUAL(vadduhs, PPC_ALTIVEC, PPC_NONE, \
597 vmul10euq, PPC_NONE, PPC2_ISA300)
fb11ae7d
RH		 598GEN_VXFORM_SAT(vadduws, MO_32, add, usadd, 0, 10);
599GEN_VXFORM_SAT(vaddsbs, MO_8, add, ssadd, 0, 12);
600GEN_VXFORM_SAT(vaddshs, MO_16, add, ssadd, 0, 13);
601GEN_VXFORM_SAT(vaddsws, MO_32, add, ssadd, 0, 14);
602GEN_VXFORM_SAT(vsububs, MO_8, sub, ussub, 0, 24);
603GEN_VXFORM_SAT(vsubuhs, MO_16, sub, ussub, 0, 25);
604GEN_VXFORM_SAT(vsubuws, MO_32, sub, ussub, 0, 26);
605GEN_VXFORM_SAT(vsubsbs, MO_8, sub, sssub, 0, 28);
606GEN_VXFORM_SAT(vsubshs, MO_16, sub, sssub, 0, 29);
607GEN_VXFORM_SAT(vsubsws, MO_32, sub, sssub, 0, 30);
0304af89
BH		 608GEN_VXFORM(vadduqm, 0, 4);
609GEN_VXFORM(vaddcuq, 0, 5);
610GEN_VXFORM3(vaddeuqm, 30, 0);
611GEN_VXFORM3(vaddecuq, 30, 0);
612GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
613 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
614GEN_VXFORM(vsubuqm, 0, 20);
615GEN_VXFORM(vsubcuq, 0, 21);
616GEN_VXFORM3(vsubeuqm, 31, 0);
617GEN_VXFORM3(vsubecuq, 31, 0);
618GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
619 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
620GEN_VXFORM(vrlb, 2, 0);
621GEN_VXFORM(vrlh, 2, 1);
622GEN_VXFORM(vrlw, 2, 2);
3e00884f
GS		 623GEN_VXFORM(vrlwmi, 2, 2);
624GEN_VXFORM_DUAL(vrlw, PPC_ALTIVEC, PPC_NONE, \
625 vrlwmi, PPC_NONE, PPC2_ISA300)
0304af89 626GEN_VXFORM(vrld, 2, 3);
3e00884f
GS		 627GEN_VXFORM(vrldmi, 2, 3);
628GEN_VXFORM_DUAL(vrld, PPC_NONE, PPC2_ALTIVEC_207, \
629 vrldmi, PPC_NONE, PPC2_ISA300)
0304af89 630GEN_VXFORM(vsl, 2, 7);
09a245e1
BR		 631GEN_VXFORM(vrldnm, 2, 7);
632GEN_VXFORM_DUAL(vsl, PPC_ALTIVEC, PPC_NONE, \
633 vrldnm, PPC_NONE, PPC2_ISA300)
0304af89
BH		 634GEN_VXFORM(vsr, 2, 11);
635GEN_VXFORM_ENV(vpkuhum, 7, 0);
636GEN_VXFORM_ENV(vpkuwum, 7, 1);
637GEN_VXFORM_ENV(vpkudum, 7, 17);
638GEN_VXFORM_ENV(vpkuhus, 7, 2);
639GEN_VXFORM_ENV(vpkuwus, 7, 3);
640GEN_VXFORM_ENV(vpkudus, 7, 19);
641GEN_VXFORM_ENV(vpkshus, 7, 4);
642GEN_VXFORM_ENV(vpkswus, 7, 5);
643GEN_VXFORM_ENV(vpksdus, 7, 21);
644GEN_VXFORM_ENV(vpkshss, 7, 6);
645GEN_VXFORM_ENV(vpkswss, 7, 7);
646GEN_VXFORM_ENV(vpksdss, 7, 23);
647GEN_VXFORM(vpkpx, 7, 12);
648GEN_VXFORM_ENV(vsum4ubs, 4, 24);
649GEN_VXFORM_ENV(vsum4sbs, 4, 28);
650GEN_VXFORM_ENV(vsum4shs, 4, 25);
651GEN_VXFORM_ENV(vsum2sws, 4, 26);
652GEN_VXFORM_ENV(vsumsws, 4, 30);
653GEN_VXFORM_ENV(vaddfp, 5, 0);
654GEN_VXFORM_ENV(vsubfp, 5, 1);
655GEN_VXFORM_ENV(vmaxfp, 5, 16);
656GEN_VXFORM_ENV(vminfp, 5, 17);
60caf221
AK		 657GEN_VXFORM_HETRO(vextublx, 6, 24)
658GEN_VXFORM_HETRO(vextuhlx, 6, 25)
659GEN_VXFORM_HETRO(vextuwlx, 6, 26)
660GEN_VXFORM_DUAL(vmrgow, PPC_NONE, PPC2_ALTIVEC_207,
661 vextuwlx, PPC_NONE, PPC2_ISA300)
662GEN_VXFORM_HETRO(vextubrx, 6, 28)
663GEN_VXFORM_HETRO(vextuhrx, 6, 29)
664GEN_VXFORM_HETRO(vextuwrx, 6, 30)
665GEN_VXFORM_DUAL(vmrgew, PPC_NONE, PPC2_ALTIVEC_207, \
666 vextuwrx, PPC_NONE, PPC2_ISA300)
0304af89
BH		 667
668#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
669static void glue(gen_, name)(DisasContext *ctx) \
670 { \
671 TCGv_ptr ra, rb, rd; \
672 if (unlikely(!ctx->altivec_enabled)) { \
673 gen_exception(ctx, POWERPC_EXCP_VPU); \
674 return; \
675 } \
676 ra = gen_avr_ptr(rA(ctx->opcode)); \
677 rb = gen_avr_ptr(rB(ctx->opcode)); \
678 rd = gen_avr_ptr(rD(ctx->opcode)); \
679 gen_helper_##opname(cpu_env, rd, ra, rb); \
680 tcg_temp_free_ptr(ra); \
681 tcg_temp_free_ptr(rb); \
682 tcg_temp_free_ptr(rd); \
683 }
684
685#define GEN_VXRFORM(name, opc2, opc3) \
686 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
687 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
688
689/*
690 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
691 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
692 * come from different versions of the ISA, so we must also support a
693 * pair of flags for each instruction.
694 */
695#define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
696static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
697{ \
698 if ((Rc(ctx->opcode) == 0) && \
699 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
700 if (Rc21(ctx->opcode) == 0) { \
701 gen_##name0(ctx); \
702 } else { \
703 gen_##name0##_(ctx); \
704 } \
705 } else if ((Rc(ctx->opcode) == 1) && \
706 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
707 if (Rc21(ctx->opcode) == 0) { \
708 gen_##name1(ctx); \
709 } else { \
710 gen_##name1##_(ctx); \
711 } \
712 } else { \
713 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
714 } \
715}
716
717GEN_VXRFORM(vcmpequb, 3, 0)
718GEN_VXRFORM(vcmpequh, 3, 1)
719GEN_VXRFORM(vcmpequw, 3, 2)
720GEN_VXRFORM(vcmpequd, 3, 3)
f7cc8466
SB		 721GEN_VXRFORM(vcmpnezb, 3, 4)
722GEN_VXRFORM(vcmpnezh, 3, 5)
723GEN_VXRFORM(vcmpnezw, 3, 6)
0304af89
BH		 724GEN_VXRFORM(vcmpgtsb, 3, 12)
725GEN_VXRFORM(vcmpgtsh, 3, 13)
726GEN_VXRFORM(vcmpgtsw, 3, 14)
727GEN_VXRFORM(vcmpgtsd, 3, 15)
728GEN_VXRFORM(vcmpgtub, 3, 8)
729GEN_VXRFORM(vcmpgtuh, 3, 9)
730GEN_VXRFORM(vcmpgtuw, 3, 10)
731GEN_VXRFORM(vcmpgtud, 3, 11)
732GEN_VXRFORM(vcmpeqfp, 3, 3)
733GEN_VXRFORM(vcmpgefp, 3, 7)
734GEN_VXRFORM(vcmpgtfp, 3, 11)
735GEN_VXRFORM(vcmpbfp, 3, 15)
0fa59364
RS		 736GEN_VXRFORM(vcmpneb, 3, 0)
737GEN_VXRFORM(vcmpneh, 3, 1)
738GEN_VXRFORM(vcmpnew, 3, 2)
0304af89 739
2020b67d 740GEN_VXRFORM_DUAL(vcmpequb, PPC_ALTIVEC, PPC_NONE, \
0fa59364 741 vcmpneb, PPC_NONE, PPC2_ISA300)
2020b67d 742GEN_VXRFORM_DUAL(vcmpequh, PPC_ALTIVEC, PPC_NONE, \
0fa59364 743 vcmpneh, PPC_NONE, PPC2_ISA300)
2020b67d 744GEN_VXRFORM_DUAL(vcmpequw, PPC_ALTIVEC, PPC_NONE, \
0fa59364 745 vcmpnew, PPC_NONE, PPC2_ISA300)
0304af89
BH		 746GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
747 vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
748GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
749 vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
750GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
751 vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
752
471ff3d0 753#define GEN_VXFORM_DUPI(name, tcg_op, opc2, opc3) \
0304af89
BH		 754static void glue(gen_, name)(DisasContext *ctx) \
755 { \
471ff3d0 756 int simm; \
0304af89
BH		 757 if (unlikely(!ctx->altivec_enabled)) { \
758 gen_exception(ctx, POWERPC_EXCP_VPU); \
759 return; \
760 } \
471ff3d0 761 simm = SIMM5(ctx->opcode); \
c82a8a85 762 tcg_op(avr_full_offset(rD(ctx->opcode)), 16, 16, simm); \
0304af89
BH		 763 }
764
471ff3d0
RH		 765GEN_VXFORM_DUPI(vspltisb, tcg_gen_gvec_dup8i, 6, 12);
766GEN_VXFORM_DUPI(vspltish, tcg_gen_gvec_dup16i, 6, 13);
767GEN_VXFORM_DUPI(vspltisw, tcg_gen_gvec_dup32i, 6, 14);
0304af89
BH		 768
769#define GEN_VXFORM_NOA(name, opc2, opc3) \
32553866 770static void glue(gen_, name)(DisasContext *ctx) \
0304af89
BH		 771 { \
772 TCGv_ptr rb, rd; \
773 if (unlikely(!ctx->altivec_enabled)) { \
774 gen_exception(ctx, POWERPC_EXCP_VPU); \
775 return; \
776 } \
777 rb = gen_avr_ptr(rB(ctx->opcode)); \
778 rd = gen_avr_ptr(rD(ctx->opcode)); \
32553866 779 gen_helper_##name(rd, rb); \
0304af89 780 tcg_temp_free_ptr(rb); \
32553866 781 tcg_temp_free_ptr(rd); \
0304af89
BH		 782 }
783
784#define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
785static void glue(gen_, name)(DisasContext *ctx) \
786 { \
787 TCGv_ptr rb, rd; \
788 \
789 if (unlikely(!ctx->altivec_enabled)) { \
790 gen_exception(ctx, POWERPC_EXCP_VPU); \
791 return; \
792 } \
793 rb = gen_avr_ptr(rB(ctx->opcode)); \
794 rd = gen_avr_ptr(rD(ctx->opcode)); \
795 gen_helper_##name(cpu_env, rd, rb); \
796 tcg_temp_free_ptr(rb); \
797 tcg_temp_free_ptr(rd); \
798 }
799
a5ad8fbf
RS		 800#define GEN_VXFORM_NOA_2(name, opc2, opc3, opc4) \
801static void glue(gen_, name)(DisasContext *ctx) \
802 { \
803 TCGv_ptr rb, rd; \
804 if (unlikely(!ctx->altivec_enabled)) { \
805 gen_exception(ctx, POWERPC_EXCP_VPU); \
806 return; \
807 } \
808 rb = gen_avr_ptr(rB(ctx->opcode)); \
809 rd = gen_avr_ptr(rD(ctx->opcode)); \
810 gen_helper_##name(rd, rb); \
811 tcg_temp_free_ptr(rb); \
812 tcg_temp_free_ptr(rd); \
813 }
814
4879538c
RS		 815#define GEN_VXFORM_NOA_3(name, opc2, opc3, opc4) \
816static void glue(gen_, name)(DisasContext *ctx) \
817 { \
818 TCGv_ptr rb; \
819 if (unlikely(!ctx->altivec_enabled)) { \
820 gen_exception(ctx, POWERPC_EXCP_VPU); \
821 return; \
822 } \
823 rb = gen_avr_ptr(rB(ctx->opcode)); \
824 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], rb); \
825 tcg_temp_free_ptr(rb); \
826 }
0304af89
BH		 827GEN_VXFORM_NOA(vupkhsb, 7, 8);
828GEN_VXFORM_NOA(vupkhsh, 7, 9);
829GEN_VXFORM_NOA(vupkhsw, 7, 25);
830GEN_VXFORM_NOA(vupklsb, 7, 10);
831GEN_VXFORM_NOA(vupklsh, 7, 11);
832GEN_VXFORM_NOA(vupklsw, 7, 27);
833GEN_VXFORM_NOA(vupkhpx, 7, 13);
834GEN_VXFORM_NOA(vupklpx, 7, 15);
835GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
836GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
837GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
838GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
839GEN_VXFORM_NOA_ENV(vrfim, 5, 11);
840GEN_VXFORM_NOA_ENV(vrfin, 5, 8);
841GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
842GEN_VXFORM_NOA_ENV(vrfiz, 5, 9);
5c69452c
AK		 843GEN_VXFORM_NOA(vprtybw, 1, 24);
844GEN_VXFORM_NOA(vprtybd, 1, 24);
845GEN_VXFORM_NOA(vprtybq, 1, 24);
0304af89 846
0f6a6d5d
RH		 847static void gen_vsplt(DisasContext *ctx, int vece)
848{
849 int uimm, dofs, bofs;
850
851 if (unlikely(!ctx->altivec_enabled)) {
852 gen_exception(ctx, POWERPC_EXCP_VPU);
853 return;
0304af89
BH		 854 }
855
0f6a6d5d 856 uimm = UIMM5(ctx->opcode);
c82a8a85
MCA		 857 bofs = avr_full_offset(rB(ctx->opcode));
858 dofs = avr_full_offset(rD(ctx->opcode));
0f6a6d5d
RH		 859
860 /* Experimental testing shows that hardware masks the immediate. */
861 bofs += (uimm << vece) & 15;
862#ifndef HOST_WORDS_BIGENDIAN
863 bofs ^= 15;
864 bofs &= ~((1 << vece) - 1);
865#endif
866
867 tcg_gen_gvec_dup_mem(vece, dofs, bofs, 16, 16);
868}
869
870#define GEN_VXFORM_VSPLT(name, vece, opc2, opc3) \
871static void glue(gen_, name)(DisasContext *ctx) { gen_vsplt(ctx, vece); }
872
0304af89
BH		 873#define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
874static void glue(gen_, name)(DisasContext *ctx) \
875 { \
876 TCGv_ptr rb, rd; \
877 TCGv_i32 uimm; \
878 \
879 if (unlikely(!ctx->altivec_enabled)) { \
880 gen_exception(ctx, POWERPC_EXCP_VPU); \
881 return; \
882 } \
883 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
884 rb = gen_avr_ptr(rB(ctx->opcode)); \
885 rd = gen_avr_ptr(rD(ctx->opcode)); \
886 gen_helper_##name(cpu_env, rd, rb, uimm); \
887 tcg_temp_free_i32(uimm); \
888 tcg_temp_free_ptr(rb); \
889 tcg_temp_free_ptr(rd); \
890 }
891
e7b1e06f
RS		 892#define GEN_VXFORM_UIMM_SPLAT(name, opc2, opc3, splat_max) \
893static void glue(gen_, name)(DisasContext *ctx) \
894 { \
895 TCGv_ptr rb, rd; \
896 uint8_t uimm = UIMM4(ctx->opcode); \
c4a18dbf 897 TCGv_i32 t0; \
e7b1e06f
RS		 898 if (unlikely(!ctx->altivec_enabled)) { \
899 gen_exception(ctx, POWERPC_EXCP_VPU); \
900 return; \
901 } \
902 if (uimm > splat_max) { \
903 uimm = 0; \
904 } \
c4a18dbf 905 t0 = tcg_temp_new_i32(); \
e7b1e06f
RS		 906 tcg_gen_movi_i32(t0, uimm); \
907 rb = gen_avr_ptr(rB(ctx->opcode)); \
908 rd = gen_avr_ptr(rD(ctx->opcode)); \
909 gen_helper_##name(rd, rb, t0); \
910 tcg_temp_free_i32(t0); \
911 tcg_temp_free_ptr(rb); \
912 tcg_temp_free_ptr(rd); \
913 }
914
0f6a6d5d
RH		 915GEN_VXFORM_VSPLT(vspltb, MO_8, 6, 8);
916GEN_VXFORM_VSPLT(vsplth, MO_16, 6, 9);
917GEN_VXFORM_VSPLT(vspltw, MO_32, 6, 10);
b5d569a1
RS		 918GEN_VXFORM_UIMM_SPLAT(vextractub, 6, 8, 15);
919GEN_VXFORM_UIMM_SPLAT(vextractuh, 6, 9, 14);
920GEN_VXFORM_UIMM_SPLAT(vextractuw, 6, 10, 12);
921GEN_VXFORM_UIMM_SPLAT(vextractd, 6, 11, 8);
e7b1e06f
RS		 922GEN_VXFORM_UIMM_SPLAT(vinsertb, 6, 12, 15);
923GEN_VXFORM_UIMM_SPLAT(vinserth, 6, 13, 14);
924GEN_VXFORM_UIMM_SPLAT(vinsertw, 6, 14, 12);
925GEN_VXFORM_UIMM_SPLAT(vinsertd, 6, 15, 8);
0304af89
BH		 926GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
927GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
928GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
929GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
2020b67d
ND		 930GEN_VXFORM_DUAL(vspltb, PPC_ALTIVEC, PPC_NONE,
931 vextractub, PPC_NONE, PPC2_ISA300);
932GEN_VXFORM_DUAL(vsplth, PPC_ALTIVEC, PPC_NONE,
933 vextractuh, PPC_NONE, PPC2_ISA300);
934GEN_VXFORM_DUAL(vspltw, PPC_ALTIVEC, PPC_NONE,
935 vextractuw, PPC_NONE, PPC2_ISA300);
936GEN_VXFORM_DUAL(vspltisb, PPC_ALTIVEC, PPC_NONE,
937 vinsertb, PPC_NONE, PPC2_ISA300);
938GEN_VXFORM_DUAL(vspltish, PPC_ALTIVEC, PPC_NONE,
939 vinserth, PPC_NONE, PPC2_ISA300);
940GEN_VXFORM_DUAL(vspltisw, PPC_ALTIVEC, PPC_NONE,
941 vinsertw, PPC_NONE, PPC2_ISA300);
0304af89
BH		 942
943static void gen_vsldoi(DisasContext *ctx)
944{
945 TCGv_ptr ra, rb, rd;
946 TCGv_i32 sh;
947 if (unlikely(!ctx->altivec_enabled)) {
948 gen_exception(ctx, POWERPC_EXCP_VPU);
949 return;
950 }
951 ra = gen_avr_ptr(rA(ctx->opcode));
952 rb = gen_avr_ptr(rB(ctx->opcode));
953 rd = gen_avr_ptr(rD(ctx->opcode));
954 sh = tcg_const_i32(VSH(ctx->opcode));
32553866 955 gen_helper_vsldoi(rd, ra, rb, sh);
0304af89
BH		 956 tcg_temp_free_ptr(ra);
957 tcg_temp_free_ptr(rb);
958 tcg_temp_free_ptr(rd);
959 tcg_temp_free_i32(sh);
960}
961
962#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
963static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
964 { \
965 TCGv_ptr ra, rb, rc, rd; \
966 if (unlikely(!ctx->altivec_enabled)) { \
967 gen_exception(ctx, POWERPC_EXCP_VPU); \
968 return; \
969 } \
970 ra = gen_avr_ptr(rA(ctx->opcode)); \
971 rb = gen_avr_ptr(rB(ctx->opcode)); \
972 rc = gen_avr_ptr(rC(ctx->opcode)); \
973 rd = gen_avr_ptr(rD(ctx->opcode)); \
974 if (Rc(ctx->opcode)) { \
975 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
976 } else { \
977 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
978 } \
979 tcg_temp_free_ptr(ra); \
980 tcg_temp_free_ptr(rb); \
981 tcg_temp_free_ptr(rc); \
982 tcg_temp_free_ptr(rd); \
983 }
984
985GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
986
987static void gen_vmladduhm(DisasContext *ctx)
988{
989 TCGv_ptr ra, rb, rc, rd;
990 if (unlikely(!ctx->altivec_enabled)) {
991 gen_exception(ctx, POWERPC_EXCP_VPU);
992 return;
993 }
994 ra = gen_avr_ptr(rA(ctx->opcode));
995 rb = gen_avr_ptr(rB(ctx->opcode));
996 rc = gen_avr_ptr(rC(ctx->opcode));
997 rd = gen_avr_ptr(rD(ctx->opcode));
998 gen_helper_vmladduhm(rd, ra, rb, rc);
999 tcg_temp_free_ptr(ra);
1000 tcg_temp_free_ptr(rb);
1001 tcg_temp_free_ptr(rc);
1002 tcg_temp_free_ptr(rd);
1003}
1004
ab045436
RS		 1005static void gen_vpermr(DisasContext *ctx)
1006{
1007 TCGv_ptr ra, rb, rc, rd;
1008 if (unlikely(!ctx->altivec_enabled)) {
1009 gen_exception(ctx, POWERPC_EXCP_VPU);
1010 return;
1011 }
1012 ra = gen_avr_ptr(rA(ctx->opcode));
1013 rb = gen_avr_ptr(rB(ctx->opcode));
1014 rc = gen_avr_ptr(rC(ctx->opcode));
1015 rd = gen_avr_ptr(rD(ctx->opcode));
1016 gen_helper_vpermr(cpu_env, rd, ra, rb, rc);
1017 tcg_temp_free_ptr(ra);
1018 tcg_temp_free_ptr(rb);
1019 tcg_temp_free_ptr(rc);
1020 tcg_temp_free_ptr(rd);
1021}
1022
0304af89
BH		 1023GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
1024GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
1025GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
1026GEN_VAFORM_PAIRED(vsel, vperm, 21)
1027GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
1028
1029GEN_VXFORM_NOA(vclzb, 1, 28)
1030GEN_VXFORM_NOA(vclzh, 1, 29)
1031GEN_VXFORM_NOA(vclzw, 1, 30)
1032GEN_VXFORM_NOA(vclzd, 1, 31)
cc8b6e76
ND		 1033GEN_VXFORM_NOA_2(vnegw, 1, 24, 6)
1034GEN_VXFORM_NOA_2(vnegd, 1, 24, 7)
125a9b23
ND		 1035GEN_VXFORM_NOA_2(vextsb2w, 1, 24, 16)
1036GEN_VXFORM_NOA_2(vextsh2w, 1, 24, 17)
1037GEN_VXFORM_NOA_2(vextsb2d, 1, 24, 24)
1038GEN_VXFORM_NOA_2(vextsh2d, 1, 24, 25)
1039GEN_VXFORM_NOA_2(vextsw2d, 1, 24, 26)
a5ad8fbf
RS		 1040GEN_VXFORM_NOA_2(vctzb, 1, 24, 28)
1041GEN_VXFORM_NOA_2(vctzh, 1, 24, 29)
1042GEN_VXFORM_NOA_2(vctzw, 1, 24, 30)
1043GEN_VXFORM_NOA_2(vctzd, 1, 24, 31)
4879538c
RS		 1044GEN_VXFORM_NOA_3(vclzlsbb, 1, 24, 0)
1045GEN_VXFORM_NOA_3(vctzlsbb, 1, 24, 1)
0304af89
BH		 1046GEN_VXFORM_NOA(vpopcntb, 1, 28)
1047GEN_VXFORM_NOA(vpopcnth, 1, 29)
1048GEN_VXFORM_NOA(vpopcntw, 1, 30)
1049GEN_VXFORM_NOA(vpopcntd, 1, 31)
1050GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
1051 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
1052GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
1053 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
1054GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
1055 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
1056GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
1057 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
01fe9a47 1058GEN_VXFORM(vbpermd, 6, 23);
0304af89
BH		 1059GEN_VXFORM(vbpermq, 6, 21);
1060GEN_VXFORM_NOA(vgbbd, 6, 20);
1061GEN_VXFORM(vpmsumb, 4, 16)
1062GEN_VXFORM(vpmsumh, 4, 17)
1063GEN_VXFORM(vpmsumw, 4, 18)
1064GEN_VXFORM(vpmsumd, 4, 19)
1065
1066#define GEN_BCD(op) \
1067static void gen_##op(DisasContext *ctx) \
1068{ \
1069 TCGv_ptr ra, rb, rd; \
1070 TCGv_i32 ps; \
1071 \
1072 if (unlikely(!ctx->altivec_enabled)) { \
1073 gen_exception(ctx, POWERPC_EXCP_VPU); \
1074 return; \
1075 } \
1076 \
1077 ra = gen_avr_ptr(rA(ctx->opcode)); \
1078 rb = gen_avr_ptr(rB(ctx->opcode)); \
1079 rd = gen_avr_ptr(rD(ctx->opcode)); \
1080 \
1081 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
1082 \
1083 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
1084 \
1085 tcg_temp_free_ptr(ra); \
1086 tcg_temp_free_ptr(rb); \
1087 tcg_temp_free_ptr(rd); \
1088 tcg_temp_free_i32(ps); \
1089}
1090
b8155872
JRZ		 1091#define GEN_BCD2(op) \
1092static void gen_##op(DisasContext *ctx) \
1093{ \
1094 TCGv_ptr rd, rb; \
1095 TCGv_i32 ps; \
1096 \
1097 if (unlikely(!ctx->altivec_enabled)) { \
1098 gen_exception(ctx, POWERPC_EXCP_VPU); \
1099 return; \
1100 } \
1101 \
1102 rb = gen_avr_ptr(rB(ctx->opcode)); \
1103 rd = gen_avr_ptr(rD(ctx->opcode)); \
1104 \
1105 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
1106 \
1107 gen_helper_##op(cpu_crf[6], rd, rb, ps); \
1108 \
1109 tcg_temp_free_ptr(rb); \
1110 tcg_temp_free_ptr(rd); \
1111 tcg_temp_free_i32(ps); \
1112}
1113
0304af89
BH		 1114GEN_BCD(bcdadd)
1115GEN_BCD(bcdsub)
b8155872 1116GEN_BCD2(bcdcfn)
e2106d73 1117GEN_BCD2(bcdctn)
38f4cb04 1118GEN_BCD2(bcdcfz)
0a890b31 1119GEN_BCD2(bcdctz)
a406c058 1120GEN_BCD2(bcdcfsq)
c85bc7dd 1121GEN_BCD2(bcdctsq)
466a3f9c 1122GEN_BCD2(bcdsetsgn)
c3025c3b 1123GEN_BCD(bcdcpsgn);
e04797f7 1124GEN_BCD(bcds);
a49a95e9 1125GEN_BCD(bcdus);
a54238ad 1126GEN_BCD(bcdsr);
31bc4d11 1127GEN_BCD(bcdtrunc);
5c32e2e4 1128GEN_BCD(bcdutrunc);
b8155872
JRZ		 1129
1130static void gen_xpnd04_1(DisasContext *ctx)
1131{
1132 switch (opc4(ctx->opcode)) {
c85bc7dd
JRZ		 1133 case 0:
1134 gen_bcdctsq(ctx);
1135 break;
a406c058
JRZ		 1136 case 2:
1137 gen_bcdcfsq(ctx);
1138 break;
0a890b31
JRZ		 1139 case 4:
1140 gen_bcdctz(ctx);
1141 break;
e2106d73
JRZ		 1142 case 5:
1143 gen_bcdctn(ctx);
1144 break;
38f4cb04
JRZ		 1145 case 6:
1146 gen_bcdcfz(ctx);
1147 break;
b8155872
JRZ		 1148 case 7:
1149 gen_bcdcfn(ctx);
1150 break;
466a3f9c
JRZ		 1151 case 31:
1152 gen_bcdsetsgn(ctx);
1153 break;
b8155872
JRZ		 1154 default:
1155 gen_invalid(ctx);
1156 break;
1157 }
1158}
1159
1160static void gen_xpnd04_2(DisasContext *ctx)
1161{
1162 switch (opc4(ctx->opcode)) {
c85bc7dd
JRZ		 1163 case 0:
1164 gen_bcdctsq(ctx);
1165 break;
a406c058
JRZ		 1166 case 2:
1167 gen_bcdcfsq(ctx);
1168 break;
0a890b31
JRZ		 1169 case 4:
1170 gen_bcdctz(ctx);
1171 break;
38f4cb04
JRZ		 1172 case 6:
1173 gen_bcdcfz(ctx);
1174 break;
b8155872
JRZ		 1175 case 7:
1176 gen_bcdcfn(ctx);
1177 break;
466a3f9c
JRZ		 1178 case 31:
1179 gen_bcdsetsgn(ctx);
1180 break;
b8155872
JRZ		 1181 default:
1182 gen_invalid(ctx);
1183 break;
1184 }
1185}
1186
466a3f9c 1187
b8155872
JRZ		 1188GEN_VXFORM_DUAL(vsubcuw, PPC_ALTIVEC, PPC_NONE, \
1189 xpnd04_1, PPC_NONE, PPC2_ISA300)
1190GEN_VXFORM_DUAL(vsubsws, PPC_ALTIVEC, PPC_NONE, \
1191 xpnd04_2, PPC_NONE, PPC2_ISA300)
0304af89
BH		 1192
1193GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
1194 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
1195GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
1196 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
1197GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
1198 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
1199GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
1200 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
c3025c3b
JRZ		 1201GEN_VXFORM_DUAL(vaddshs, PPC_ALTIVEC, PPC_NONE, \
1202 bcdcpsgn, PPC_NONE, PPC2_ISA300)
e04797f7
JRZ		 1203GEN_VXFORM_DUAL(vsubudm, PPC2_ALTIVEC_207, PPC_NONE, \
1204 bcds, PPC_NONE, PPC2_ISA300)
a49a95e9
JRZ		 1205GEN_VXFORM_DUAL(vsubuwm, PPC_ALTIVEC, PPC_NONE, \
1206 bcdus, PPC_NONE, PPC2_ISA300)
31bc4d11
JRZ		 1207GEN_VXFORM_DUAL(vsubsbs, PPC_ALTIVEC, PPC_NONE, \
1208 bcdtrunc, PPC_NONE, PPC2_ISA300)
1209GEN_VXFORM_DUAL(vsubuqm, PPC2_ALTIVEC_207, PPC_NONE, \
1210 bcdtrunc, PPC_NONE, PPC2_ISA300)
5c32e2e4
JRZ		 1211GEN_VXFORM_DUAL(vsubcuq, PPC2_ALTIVEC_207, PPC_NONE, \
1212 bcdutrunc, PPC_NONE, PPC2_ISA300)
1213
0304af89
BH		 1214
1215static void gen_vsbox(DisasContext *ctx)
1216{
1217 TCGv_ptr ra, rd;
1218 if (unlikely(!ctx->altivec_enabled)) {
1219 gen_exception(ctx, POWERPC_EXCP_VPU);
1220 return;
1221 }
1222 ra = gen_avr_ptr(rA(ctx->opcode));
1223 rd = gen_avr_ptr(rD(ctx->opcode));
1224 gen_helper_vsbox(rd, ra);
1225 tcg_temp_free_ptr(ra);
1226 tcg_temp_free_ptr(rd);
1227}
1228
1229GEN_VXFORM(vcipher, 4, 20)
1230GEN_VXFORM(vcipherlast, 4, 20)
1231GEN_VXFORM(vncipher, 4, 21)
1232GEN_VXFORM(vncipherlast, 4, 21)
1233
1234GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
1235 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
1236GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
1237 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
1238
1239#define VSHASIGMA(op) \
1240static void gen_##op(DisasContext *ctx) \
1241{ \
1242 TCGv_ptr ra, rd; \
1243 TCGv_i32 st_six; \
1244 if (unlikely(!ctx->altivec_enabled)) { \
1245 gen_exception(ctx, POWERPC_EXCP_VPU); \
1246 return; \
1247 } \
1248 ra = gen_avr_ptr(rA(ctx->opcode)); \
1249 rd = gen_avr_ptr(rD(ctx->opcode)); \
1250 st_six = tcg_const_i32(rB(ctx->opcode)); \
1251 gen_helper_##op(rd, ra, st_six); \
1252 tcg_temp_free_ptr(ra); \
1253 tcg_temp_free_ptr(rd); \
1254 tcg_temp_free_i32(st_six); \
1255}
1256
1257VSHASIGMA(vshasigmaw)
1258VSHASIGMA(vshasigmad)
1259
1260GEN_VXFORM3(vpermxor, 22, 0xFF)
1261GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
1262 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
1263
1264#undef GEN_VR_LDX
1265#undef GEN_VR_STX
1266#undef GEN_VR_LVE
1267#undef GEN_VR_STVE
1268
1269#undef GEN_VX_LOGICAL
1270#undef GEN_VX_LOGICAL_207
1271#undef GEN_VXFORM
1272#undef GEN_VXFORM_207
1273#undef GEN_VXFORM_DUAL
1274#undef GEN_VXRFORM_DUAL
1275#undef GEN_VXRFORM1
1276#undef GEN_VXRFORM
471ff3d0 1277#undef GEN_VXFORM_DUPI
0304af89
BH		 1278#undef GEN_VXFORM_NOA
1279#undef GEN_VXFORM_UIMM
1280#undef GEN_VAFORM_PAIRED
b8155872
JRZ		 1281
1282#undef GEN_BCD2
QEMU mirror