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0304af89 BH |
1 | /* |
2 | * translate/vmx-impl.c | |
3 | * | |
4 | * Altivec/VMX translation | |
5 | */ | |
6 | ||
7 | /*** Altivec vector extension ***/ | |
8 | /* Altivec registers moves */ | |
9 | ||
10 | static inline TCGv_ptr gen_avr_ptr(int reg) | |
11 | { | |
12 | TCGv_ptr r = tcg_temp_new_ptr(); | |
13 | tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg])); | |
14 | return r; | |
15 | } | |
16 | ||
17 | #define GEN_VR_LDX(name, opc2, opc3) \ | |
18 | static void glue(gen_, name)(DisasContext *ctx) \ | |
19 | { \ | |
20 | TCGv EA; \ | |
21 | if (unlikely(!ctx->altivec_enabled)) { \ | |
22 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
23 | return; \ | |
24 | } \ | |
25 | gen_set_access_type(ctx, ACCESS_INT); \ | |
26 | EA = tcg_temp_new(); \ | |
27 | gen_addr_reg_index(ctx, EA); \ | |
28 | tcg_gen_andi_tl(EA, EA, ~0xf); \ | |
4f364fe7 ND |
29 | /* We only need to swap high and low halves. gen_qemu_ld64_i64 does \ |
30 | necessary 64-bit byteswap already. */ \ | |
0304af89 | 31 | if (ctx->le_mode) { \ |
4f364fe7 | 32 | gen_qemu_ld64_i64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
0304af89 | 33 | tcg_gen_addi_tl(EA, EA, 8); \ |
4f364fe7 | 34 | gen_qemu_ld64_i64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
0304af89 | 35 | } else { \ |
4f364fe7 | 36 | gen_qemu_ld64_i64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
0304af89 | 37 | tcg_gen_addi_tl(EA, EA, 8); \ |
4f364fe7 | 38 | gen_qemu_ld64_i64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
0304af89 BH |
39 | } \ |
40 | tcg_temp_free(EA); \ | |
41 | } | |
42 | ||
43 | #define GEN_VR_STX(name, opc2, opc3) \ | |
44 | static void gen_st##name(DisasContext *ctx) \ | |
45 | { \ | |
46 | TCGv EA; \ | |
47 | if (unlikely(!ctx->altivec_enabled)) { \ | |
48 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
49 | return; \ | |
50 | } \ | |
51 | gen_set_access_type(ctx, ACCESS_INT); \ | |
52 | EA = tcg_temp_new(); \ | |
53 | gen_addr_reg_index(ctx, EA); \ | |
54 | tcg_gen_andi_tl(EA, EA, ~0xf); \ | |
2468f23d ND |
55 | /* We only need to swap high and low halves. gen_qemu_st64_i64 does \ |
56 | necessary 64-bit byteswap already. */ \ | |
0304af89 | 57 | if (ctx->le_mode) { \ |
2468f23d | 58 | gen_qemu_st64_i64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
0304af89 | 59 | tcg_gen_addi_tl(EA, EA, 8); \ |
2468f23d | 60 | gen_qemu_st64_i64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
0304af89 | 61 | } else { \ |
2468f23d | 62 | gen_qemu_st64_i64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
0304af89 | 63 | tcg_gen_addi_tl(EA, EA, 8); \ |
2468f23d | 64 | gen_qemu_st64_i64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
0304af89 BH |
65 | } \ |
66 | tcg_temp_free(EA); \ | |
67 | } | |
68 | ||
69 | #define GEN_VR_LVE(name, opc2, opc3, size) \ | |
70 | static void gen_lve##name(DisasContext *ctx) \ | |
71 | { \ | |
72 | TCGv EA; \ | |
73 | TCGv_ptr rs; \ | |
74 | if (unlikely(!ctx->altivec_enabled)) { \ | |
75 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
76 | return; \ | |
77 | } \ | |
78 | gen_set_access_type(ctx, ACCESS_INT); \ | |
79 | EA = tcg_temp_new(); \ | |
80 | gen_addr_reg_index(ctx, EA); \ | |
81 | if (size > 1) { \ | |
82 | tcg_gen_andi_tl(EA, EA, ~(size - 1)); \ | |
83 | } \ | |
84 | rs = gen_avr_ptr(rS(ctx->opcode)); \ | |
85 | gen_helper_lve##name(cpu_env, rs, EA); \ | |
86 | tcg_temp_free(EA); \ | |
87 | tcg_temp_free_ptr(rs); \ | |
88 | } | |
89 | ||
90 | #define GEN_VR_STVE(name, opc2, opc3, size) \ | |
91 | static void gen_stve##name(DisasContext *ctx) \ | |
92 | { \ | |
93 | TCGv EA; \ | |
94 | TCGv_ptr rs; \ | |
95 | if (unlikely(!ctx->altivec_enabled)) { \ | |
96 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
97 | return; \ | |
98 | } \ | |
99 | gen_set_access_type(ctx, ACCESS_INT); \ | |
100 | EA = tcg_temp_new(); \ | |
101 | gen_addr_reg_index(ctx, EA); \ | |
102 | if (size > 1) { \ | |
103 | tcg_gen_andi_tl(EA, EA, ~(size - 1)); \ | |
104 | } \ | |
105 | rs = gen_avr_ptr(rS(ctx->opcode)); \ | |
106 | gen_helper_stve##name(cpu_env, rs, EA); \ | |
107 | tcg_temp_free(EA); \ | |
108 | tcg_temp_free_ptr(rs); \ | |
109 | } | |
110 | ||
111 | GEN_VR_LDX(lvx, 0x07, 0x03); | |
112 | /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */ | |
113 | GEN_VR_LDX(lvxl, 0x07, 0x0B); | |
114 | ||
115 | GEN_VR_LVE(bx, 0x07, 0x00, 1); | |
116 | GEN_VR_LVE(hx, 0x07, 0x01, 2); | |
117 | GEN_VR_LVE(wx, 0x07, 0x02, 4); | |
118 | ||
119 | GEN_VR_STX(svx, 0x07, 0x07); | |
120 | /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */ | |
121 | GEN_VR_STX(svxl, 0x07, 0x0F); | |
122 | ||
123 | GEN_VR_STVE(bx, 0x07, 0x04, 1); | |
124 | GEN_VR_STVE(hx, 0x07, 0x05, 2); | |
125 | GEN_VR_STVE(wx, 0x07, 0x06, 4); | |
126 | ||
127 | static void gen_lvsl(DisasContext *ctx) | |
128 | { | |
129 | TCGv_ptr rd; | |
130 | TCGv EA; | |
131 | if (unlikely(!ctx->altivec_enabled)) { | |
132 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
133 | return; | |
134 | } | |
135 | EA = tcg_temp_new(); | |
136 | gen_addr_reg_index(ctx, EA); | |
137 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
138 | gen_helper_lvsl(rd, EA); | |
139 | tcg_temp_free(EA); | |
140 | tcg_temp_free_ptr(rd); | |
141 | } | |
142 | ||
143 | static void gen_lvsr(DisasContext *ctx) | |
144 | { | |
145 | TCGv_ptr rd; | |
146 | TCGv EA; | |
147 | if (unlikely(!ctx->altivec_enabled)) { | |
148 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
149 | return; | |
150 | } | |
151 | EA = tcg_temp_new(); | |
152 | gen_addr_reg_index(ctx, EA); | |
153 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
154 | gen_helper_lvsr(rd, EA); | |
155 | tcg_temp_free(EA); | |
156 | tcg_temp_free_ptr(rd); | |
157 | } | |
158 | ||
159 | static void gen_mfvscr(DisasContext *ctx) | |
160 | { | |
161 | TCGv_i32 t; | |
162 | if (unlikely(!ctx->altivec_enabled)) { | |
163 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
164 | return; | |
165 | } | |
166 | tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0); | |
167 | t = tcg_temp_new_i32(); | |
168 | tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr)); | |
169 | tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t); | |
170 | tcg_temp_free_i32(t); | |
171 | } | |
172 | ||
173 | static void gen_mtvscr(DisasContext *ctx) | |
174 | { | |
175 | TCGv_ptr p; | |
176 | if (unlikely(!ctx->altivec_enabled)) { | |
177 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
178 | return; | |
179 | } | |
180 | p = gen_avr_ptr(rB(ctx->opcode)); | |
181 | gen_helper_mtvscr(cpu_env, p); | |
182 | tcg_temp_free_ptr(p); | |
183 | } | |
184 | ||
37ad52ba VH |
185 | #define GEN_VX_VMUL10(name, add_cin, ret_carry) \ |
186 | static void glue(gen_, name)(DisasContext *ctx) \ | |
187 | { \ | |
188 | TCGv_i64 t0 = tcg_temp_new_i64(); \ | |
189 | TCGv_i64 t1 = tcg_temp_new_i64(); \ | |
190 | TCGv_i64 t2 = tcg_temp_new_i64(); \ | |
191 | TCGv_i64 ten, z; \ | |
192 | \ | |
193 | if (unlikely(!ctx->altivec_enabled)) { \ | |
194 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
195 | return; \ | |
196 | } \ | |
197 | \ | |
198 | ten = tcg_const_i64(10); \ | |
199 | z = tcg_const_i64(0); \ | |
200 | \ | |
201 | if (add_cin) { \ | |
202 | tcg_gen_mulu2_i64(t0, t1, cpu_avrl[rA(ctx->opcode)], ten); \ | |
203 | tcg_gen_andi_i64(t2, cpu_avrl[rB(ctx->opcode)], 0xF); \ | |
204 | tcg_gen_add2_i64(cpu_avrl[rD(ctx->opcode)], t2, t0, t1, t2, z); \ | |
205 | } else { \ | |
206 | tcg_gen_mulu2_i64(cpu_avrl[rD(ctx->opcode)], t2, \ | |
207 | cpu_avrl[rA(ctx->opcode)], ten); \ | |
208 | } \ | |
209 | \ | |
210 | if (ret_carry) { \ | |
211 | tcg_gen_mulu2_i64(t0, t1, cpu_avrh[rA(ctx->opcode)], ten); \ | |
212 | tcg_gen_add2_i64(t0, cpu_avrl[rD(ctx->opcode)], t0, t1, t2, z); \ | |
213 | tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0); \ | |
214 | } else { \ | |
215 | tcg_gen_mul_i64(t0, cpu_avrh[rA(ctx->opcode)], ten); \ | |
216 | tcg_gen_add_i64(cpu_avrh[rD(ctx->opcode)], t0, t2); \ | |
217 | } \ | |
218 | \ | |
219 | tcg_temp_free_i64(t0); \ | |
220 | tcg_temp_free_i64(t1); \ | |
221 | tcg_temp_free_i64(t2); \ | |
222 | tcg_temp_free_i64(ten); \ | |
223 | tcg_temp_free_i64(z); \ | |
224 | } \ | |
225 | ||
226 | GEN_VX_VMUL10(vmul10uq, 0, 0); | |
227 | GEN_VX_VMUL10(vmul10euq, 1, 0); | |
228 | GEN_VX_VMUL10(vmul10cuq, 0, 1); | |
229 | GEN_VX_VMUL10(vmul10ecuq, 1, 1); | |
230 | ||
0304af89 BH |
231 | /* Logical operations */ |
232 | #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \ | |
233 | static void glue(gen_, name)(DisasContext *ctx) \ | |
234 | { \ | |
235 | if (unlikely(!ctx->altivec_enabled)) { \ | |
236 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
237 | return; \ | |
238 | } \ | |
239 | tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \ | |
240 | tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \ | |
241 | } | |
242 | ||
243 | GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16); | |
244 | GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17); | |
245 | GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18); | |
246 | GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19); | |
247 | GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20); | |
248 | GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26); | |
249 | GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22); | |
250 | GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21); | |
251 | ||
252 | #define GEN_VXFORM(name, opc2, opc3) \ | |
253 | static void glue(gen_, name)(DisasContext *ctx) \ | |
254 | { \ | |
255 | TCGv_ptr ra, rb, rd; \ | |
256 | if (unlikely(!ctx->altivec_enabled)) { \ | |
257 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
258 | return; \ | |
259 | } \ | |
260 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
261 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
262 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
263 | gen_helper_##name (rd, ra, rb); \ | |
264 | tcg_temp_free_ptr(ra); \ | |
265 | tcg_temp_free_ptr(rb); \ | |
266 | tcg_temp_free_ptr(rd); \ | |
267 | } | |
268 | ||
269 | #define GEN_VXFORM_ENV(name, opc2, opc3) \ | |
270 | static void glue(gen_, name)(DisasContext *ctx) \ | |
271 | { \ | |
272 | TCGv_ptr ra, rb, rd; \ | |
273 | if (unlikely(!ctx->altivec_enabled)) { \ | |
274 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
275 | return; \ | |
276 | } \ | |
277 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
278 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
279 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
280 | gen_helper_##name(cpu_env, rd, ra, rb); \ | |
281 | tcg_temp_free_ptr(ra); \ | |
282 | tcg_temp_free_ptr(rb); \ | |
283 | tcg_temp_free_ptr(rd); \ | |
284 | } | |
285 | ||
286 | #define GEN_VXFORM3(name, opc2, opc3) \ | |
287 | static void glue(gen_, name)(DisasContext *ctx) \ | |
288 | { \ | |
289 | TCGv_ptr ra, rb, rc, rd; \ | |
290 | if (unlikely(!ctx->altivec_enabled)) { \ | |
291 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
292 | return; \ | |
293 | } \ | |
294 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
295 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
296 | rc = gen_avr_ptr(rC(ctx->opcode)); \ | |
297 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
298 | gen_helper_##name(rd, ra, rb, rc); \ | |
299 | tcg_temp_free_ptr(ra); \ | |
300 | tcg_temp_free_ptr(rb); \ | |
301 | tcg_temp_free_ptr(rc); \ | |
302 | tcg_temp_free_ptr(rd); \ | |
303 | } | |
304 | ||
305 | /* | |
306 | * Support for Altivec instruction pairs that use bit 31 (Rc) as | |
307 | * an opcode bit. In general, these pairs come from different | |
308 | * versions of the ISA, so we must also support a pair of flags for | |
309 | * each instruction. | |
310 | */ | |
311 | #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \ | |
312 | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ | |
313 | { \ | |
314 | if ((Rc(ctx->opcode) == 0) && \ | |
315 | ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \ | |
316 | gen_##name0(ctx); \ | |
317 | } else if ((Rc(ctx->opcode) == 1) && \ | |
318 | ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \ | |
319 | gen_##name1(ctx); \ | |
320 | } else { \ | |
321 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ | |
322 | } \ | |
323 | } | |
324 | ||
37ad52ba VH |
325 | /* Adds support to provide invalid mask */ |
326 | #define GEN_VXFORM_DUAL_EXT(name0, flg0, flg2_0, inval0, \ | |
327 | name1, flg1, flg2_1, inval1) \ | |
328 | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ | |
329 | { \ | |
330 | if ((Rc(ctx->opcode) == 0) && \ | |
331 | ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0)) && \ | |
332 | !(ctx->opcode & inval0)) { \ | |
333 | gen_##name0(ctx); \ | |
334 | } else if ((Rc(ctx->opcode) == 1) && \ | |
335 | ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1)) && \ | |
336 | !(ctx->opcode & inval1)) { \ | |
337 | gen_##name1(ctx); \ | |
338 | } else { \ | |
339 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ | |
340 | } \ | |
341 | } | |
342 | ||
0304af89 | 343 | GEN_VXFORM(vaddubm, 0, 0); |
37ad52ba VH |
344 | GEN_VXFORM_DUAL_EXT(vaddubm, PPC_ALTIVEC, PPC_NONE, 0, \ |
345 | vmul10cuq, PPC_NONE, PPC2_ISA300, 0x0000F800) | |
0304af89 | 346 | GEN_VXFORM(vadduhm, 0, 1); |
37ad52ba VH |
347 | GEN_VXFORM_DUAL(vadduhm, PPC_ALTIVEC, PPC_NONE, \ |
348 | vmul10ecuq, PPC_NONE, PPC2_ISA300) | |
0304af89 BH |
349 | GEN_VXFORM(vadduwm, 0, 2); |
350 | GEN_VXFORM(vaddudm, 0, 3); | |
351 | GEN_VXFORM(vsububm, 0, 16); | |
352 | GEN_VXFORM(vsubuhm, 0, 17); | |
353 | GEN_VXFORM(vsubuwm, 0, 18); | |
354 | GEN_VXFORM(vsubudm, 0, 19); | |
355 | GEN_VXFORM(vmaxub, 1, 0); | |
356 | GEN_VXFORM(vmaxuh, 1, 1); | |
357 | GEN_VXFORM(vmaxuw, 1, 2); | |
358 | GEN_VXFORM(vmaxud, 1, 3); | |
359 | GEN_VXFORM(vmaxsb, 1, 4); | |
360 | GEN_VXFORM(vmaxsh, 1, 5); | |
361 | GEN_VXFORM(vmaxsw, 1, 6); | |
362 | GEN_VXFORM(vmaxsd, 1, 7); | |
363 | GEN_VXFORM(vminub, 1, 8); | |
364 | GEN_VXFORM(vminuh, 1, 9); | |
365 | GEN_VXFORM(vminuw, 1, 10); | |
366 | GEN_VXFORM(vminud, 1, 11); | |
367 | GEN_VXFORM(vminsb, 1, 12); | |
368 | GEN_VXFORM(vminsh, 1, 13); | |
369 | GEN_VXFORM(vminsw, 1, 14); | |
370 | GEN_VXFORM(vminsd, 1, 15); | |
371 | GEN_VXFORM(vavgub, 1, 16); | |
37707059 SD |
372 | GEN_VXFORM(vabsdub, 1, 16); |
373 | GEN_VXFORM_DUAL(vavgub, PPC_ALTIVEC, PPC_NONE, \ | |
374 | vabsdub, PPC_NONE, PPC2_ISA300) | |
0304af89 | 375 | GEN_VXFORM(vavguh, 1, 17); |
37707059 SD |
376 | GEN_VXFORM(vabsduh, 1, 17); |
377 | GEN_VXFORM_DUAL(vavguh, PPC_ALTIVEC, PPC_NONE, \ | |
378 | vabsduh, PPC_NONE, PPC2_ISA300) | |
0304af89 | 379 | GEN_VXFORM(vavguw, 1, 18); |
37707059 SD |
380 | GEN_VXFORM(vabsduw, 1, 18); |
381 | GEN_VXFORM_DUAL(vavguw, PPC_ALTIVEC, PPC_NONE, \ | |
382 | vabsduw, PPC_NONE, PPC2_ISA300) | |
0304af89 BH |
383 | GEN_VXFORM(vavgsb, 1, 20); |
384 | GEN_VXFORM(vavgsh, 1, 21); | |
385 | GEN_VXFORM(vavgsw, 1, 22); | |
386 | GEN_VXFORM(vmrghb, 6, 0); | |
387 | GEN_VXFORM(vmrghh, 6, 1); | |
388 | GEN_VXFORM(vmrghw, 6, 2); | |
389 | GEN_VXFORM(vmrglb, 6, 4); | |
390 | GEN_VXFORM(vmrglh, 6, 5); | |
391 | GEN_VXFORM(vmrglw, 6, 6); | |
392 | ||
393 | static void gen_vmrgew(DisasContext *ctx) | |
394 | { | |
395 | TCGv_i64 tmp; | |
396 | int VT, VA, VB; | |
397 | if (unlikely(!ctx->altivec_enabled)) { | |
398 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
399 | return; | |
400 | } | |
401 | VT = rD(ctx->opcode); | |
402 | VA = rA(ctx->opcode); | |
403 | VB = rB(ctx->opcode); | |
404 | tmp = tcg_temp_new_i64(); | |
405 | tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32); | |
406 | tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32); | |
407 | tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32); | |
408 | tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32); | |
409 | tcg_temp_free_i64(tmp); | |
410 | } | |
411 | ||
412 | static void gen_vmrgow(DisasContext *ctx) | |
413 | { | |
414 | int VT, VA, VB; | |
415 | if (unlikely(!ctx->altivec_enabled)) { | |
416 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
417 | return; | |
418 | } | |
419 | VT = rD(ctx->opcode); | |
420 | VA = rA(ctx->opcode); | |
421 | VB = rB(ctx->opcode); | |
422 | ||
423 | tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32); | |
424 | tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32); | |
425 | } | |
426 | ||
427 | GEN_VXFORM(vmuloub, 4, 0); | |
428 | GEN_VXFORM(vmulouh, 4, 1); | |
429 | GEN_VXFORM(vmulouw, 4, 2); | |
430 | GEN_VXFORM(vmuluwm, 4, 2); | |
431 | GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE, | |
432 | vmuluwm, PPC_NONE, PPC2_ALTIVEC_207) | |
433 | GEN_VXFORM(vmulosb, 4, 4); | |
434 | GEN_VXFORM(vmulosh, 4, 5); | |
435 | GEN_VXFORM(vmulosw, 4, 6); | |
436 | GEN_VXFORM(vmuleub, 4, 8); | |
437 | GEN_VXFORM(vmuleuh, 4, 9); | |
438 | GEN_VXFORM(vmuleuw, 4, 10); | |
439 | GEN_VXFORM(vmulesb, 4, 12); | |
440 | GEN_VXFORM(vmulesh, 4, 13); | |
441 | GEN_VXFORM(vmulesw, 4, 14); | |
442 | GEN_VXFORM(vslb, 2, 4); | |
443 | GEN_VXFORM(vslh, 2, 5); | |
444 | GEN_VXFORM(vslw, 2, 6); | |
09a245e1 BR |
445 | GEN_VXFORM(vrlwnm, 2, 6); |
446 | GEN_VXFORM_DUAL(vslw, PPC_ALTIVEC, PPC_NONE, \ | |
447 | vrlwnm, PPC_NONE, PPC2_ISA300) | |
0304af89 BH |
448 | GEN_VXFORM(vsld, 2, 23); |
449 | GEN_VXFORM(vsrb, 2, 8); | |
450 | GEN_VXFORM(vsrh, 2, 9); | |
451 | GEN_VXFORM(vsrw, 2, 10); | |
452 | GEN_VXFORM(vsrd, 2, 27); | |
453 | GEN_VXFORM(vsrab, 2, 12); | |
454 | GEN_VXFORM(vsrah, 2, 13); | |
455 | GEN_VXFORM(vsraw, 2, 14); | |
456 | GEN_VXFORM(vsrad, 2, 15); | |
4004c1db | 457 | GEN_VXFORM(vsrv, 2, 28); |
5644a175 | 458 | GEN_VXFORM(vslv, 2, 29); |
0304af89 BH |
459 | GEN_VXFORM(vslo, 6, 16); |
460 | GEN_VXFORM(vsro, 6, 17); | |
461 | GEN_VXFORM(vaddcuw, 0, 6); | |
462 | GEN_VXFORM(vsubcuw, 0, 22); | |
463 | GEN_VXFORM_ENV(vaddubs, 0, 8); | |
37ad52ba VH |
464 | GEN_VXFORM_DUAL_EXT(vaddubs, PPC_ALTIVEC, PPC_NONE, 0, \ |
465 | vmul10uq, PPC_NONE, PPC2_ISA300, 0x0000F800) | |
0304af89 | 466 | GEN_VXFORM_ENV(vadduhs, 0, 9); |
37ad52ba VH |
467 | GEN_VXFORM_DUAL(vadduhs, PPC_ALTIVEC, PPC_NONE, \ |
468 | vmul10euq, PPC_NONE, PPC2_ISA300) | |
0304af89 BH |
469 | GEN_VXFORM_ENV(vadduws, 0, 10); |
470 | GEN_VXFORM_ENV(vaddsbs, 0, 12); | |
471 | GEN_VXFORM_ENV(vaddshs, 0, 13); | |
472 | GEN_VXFORM_ENV(vaddsws, 0, 14); | |
473 | GEN_VXFORM_ENV(vsububs, 0, 24); | |
474 | GEN_VXFORM_ENV(vsubuhs, 0, 25); | |
475 | GEN_VXFORM_ENV(vsubuws, 0, 26); | |
476 | GEN_VXFORM_ENV(vsubsbs, 0, 28); | |
477 | GEN_VXFORM_ENV(vsubshs, 0, 29); | |
478 | GEN_VXFORM_ENV(vsubsws, 0, 30); | |
479 | GEN_VXFORM(vadduqm, 0, 4); | |
480 | GEN_VXFORM(vaddcuq, 0, 5); | |
481 | GEN_VXFORM3(vaddeuqm, 30, 0); | |
482 | GEN_VXFORM3(vaddecuq, 30, 0); | |
483 | GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \ | |
484 | vaddecuq, PPC_NONE, PPC2_ALTIVEC_207) | |
485 | GEN_VXFORM(vsubuqm, 0, 20); | |
486 | GEN_VXFORM(vsubcuq, 0, 21); | |
487 | GEN_VXFORM3(vsubeuqm, 31, 0); | |
488 | GEN_VXFORM3(vsubecuq, 31, 0); | |
489 | GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \ | |
490 | vsubecuq, PPC_NONE, PPC2_ALTIVEC_207) | |
491 | GEN_VXFORM(vrlb, 2, 0); | |
492 | GEN_VXFORM(vrlh, 2, 1); | |
493 | GEN_VXFORM(vrlw, 2, 2); | |
3e00884f GS |
494 | GEN_VXFORM(vrlwmi, 2, 2); |
495 | GEN_VXFORM_DUAL(vrlw, PPC_ALTIVEC, PPC_NONE, \ | |
496 | vrlwmi, PPC_NONE, PPC2_ISA300) | |
0304af89 | 497 | GEN_VXFORM(vrld, 2, 3); |
3e00884f GS |
498 | GEN_VXFORM(vrldmi, 2, 3); |
499 | GEN_VXFORM_DUAL(vrld, PPC_NONE, PPC2_ALTIVEC_207, \ | |
500 | vrldmi, PPC_NONE, PPC2_ISA300) | |
0304af89 | 501 | GEN_VXFORM(vsl, 2, 7); |
09a245e1 BR |
502 | GEN_VXFORM(vrldnm, 2, 7); |
503 | GEN_VXFORM_DUAL(vsl, PPC_ALTIVEC, PPC_NONE, \ | |
504 | vrldnm, PPC_NONE, PPC2_ISA300) | |
0304af89 BH |
505 | GEN_VXFORM(vsr, 2, 11); |
506 | GEN_VXFORM_ENV(vpkuhum, 7, 0); | |
507 | GEN_VXFORM_ENV(vpkuwum, 7, 1); | |
508 | GEN_VXFORM_ENV(vpkudum, 7, 17); | |
509 | GEN_VXFORM_ENV(vpkuhus, 7, 2); | |
510 | GEN_VXFORM_ENV(vpkuwus, 7, 3); | |
511 | GEN_VXFORM_ENV(vpkudus, 7, 19); | |
512 | GEN_VXFORM_ENV(vpkshus, 7, 4); | |
513 | GEN_VXFORM_ENV(vpkswus, 7, 5); | |
514 | GEN_VXFORM_ENV(vpksdus, 7, 21); | |
515 | GEN_VXFORM_ENV(vpkshss, 7, 6); | |
516 | GEN_VXFORM_ENV(vpkswss, 7, 7); | |
517 | GEN_VXFORM_ENV(vpksdss, 7, 23); | |
518 | GEN_VXFORM(vpkpx, 7, 12); | |
519 | GEN_VXFORM_ENV(vsum4ubs, 4, 24); | |
520 | GEN_VXFORM_ENV(vsum4sbs, 4, 28); | |
521 | GEN_VXFORM_ENV(vsum4shs, 4, 25); | |
522 | GEN_VXFORM_ENV(vsum2sws, 4, 26); | |
523 | GEN_VXFORM_ENV(vsumsws, 4, 30); | |
524 | GEN_VXFORM_ENV(vaddfp, 5, 0); | |
525 | GEN_VXFORM_ENV(vsubfp, 5, 1); | |
526 | GEN_VXFORM_ENV(vmaxfp, 5, 16); | |
527 | GEN_VXFORM_ENV(vminfp, 5, 17); | |
528 | ||
529 | #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \ | |
530 | static void glue(gen_, name)(DisasContext *ctx) \ | |
531 | { \ | |
532 | TCGv_ptr ra, rb, rd; \ | |
533 | if (unlikely(!ctx->altivec_enabled)) { \ | |
534 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
535 | return; \ | |
536 | } \ | |
537 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
538 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
539 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
540 | gen_helper_##opname(cpu_env, rd, ra, rb); \ | |
541 | tcg_temp_free_ptr(ra); \ | |
542 | tcg_temp_free_ptr(rb); \ | |
543 | tcg_temp_free_ptr(rd); \ | |
544 | } | |
545 | ||
546 | #define GEN_VXRFORM(name, opc2, opc3) \ | |
547 | GEN_VXRFORM1(name, name, #name, opc2, opc3) \ | |
548 | GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) | |
549 | ||
550 | /* | |
551 | * Support for Altivec instructions that use bit 31 (Rc) as an opcode | |
552 | * bit but also use bit 21 as an actual Rc bit. In general, thse pairs | |
553 | * come from different versions of the ISA, so we must also support a | |
554 | * pair of flags for each instruction. | |
555 | */ | |
556 | #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \ | |
557 | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ | |
558 | { \ | |
559 | if ((Rc(ctx->opcode) == 0) && \ | |
560 | ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \ | |
561 | if (Rc21(ctx->opcode) == 0) { \ | |
562 | gen_##name0(ctx); \ | |
563 | } else { \ | |
564 | gen_##name0##_(ctx); \ | |
565 | } \ | |
566 | } else if ((Rc(ctx->opcode) == 1) && \ | |
567 | ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \ | |
568 | if (Rc21(ctx->opcode) == 0) { \ | |
569 | gen_##name1(ctx); \ | |
570 | } else { \ | |
571 | gen_##name1##_(ctx); \ | |
572 | } \ | |
573 | } else { \ | |
574 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ | |
575 | } \ | |
576 | } | |
577 | ||
578 | GEN_VXRFORM(vcmpequb, 3, 0) | |
579 | GEN_VXRFORM(vcmpequh, 3, 1) | |
580 | GEN_VXRFORM(vcmpequw, 3, 2) | |
581 | GEN_VXRFORM(vcmpequd, 3, 3) | |
f7cc8466 SB |
582 | GEN_VXRFORM(vcmpnezb, 3, 4) |
583 | GEN_VXRFORM(vcmpnezh, 3, 5) | |
584 | GEN_VXRFORM(vcmpnezw, 3, 6) | |
0304af89 BH |
585 | GEN_VXRFORM(vcmpgtsb, 3, 12) |
586 | GEN_VXRFORM(vcmpgtsh, 3, 13) | |
587 | GEN_VXRFORM(vcmpgtsw, 3, 14) | |
588 | GEN_VXRFORM(vcmpgtsd, 3, 15) | |
589 | GEN_VXRFORM(vcmpgtub, 3, 8) | |
590 | GEN_VXRFORM(vcmpgtuh, 3, 9) | |
591 | GEN_VXRFORM(vcmpgtuw, 3, 10) | |
592 | GEN_VXRFORM(vcmpgtud, 3, 11) | |
593 | GEN_VXRFORM(vcmpeqfp, 3, 3) | |
594 | GEN_VXRFORM(vcmpgefp, 3, 7) | |
595 | GEN_VXRFORM(vcmpgtfp, 3, 11) | |
596 | GEN_VXRFORM(vcmpbfp, 3, 15) | |
0fa59364 RS |
597 | GEN_VXRFORM(vcmpneb, 3, 0) |
598 | GEN_VXRFORM(vcmpneh, 3, 1) | |
599 | GEN_VXRFORM(vcmpnew, 3, 2) | |
0304af89 | 600 | |
2020b67d | 601 | GEN_VXRFORM_DUAL(vcmpequb, PPC_ALTIVEC, PPC_NONE, \ |
0fa59364 | 602 | vcmpneb, PPC_NONE, PPC2_ISA300) |
2020b67d | 603 | GEN_VXRFORM_DUAL(vcmpequh, PPC_ALTIVEC, PPC_NONE, \ |
0fa59364 | 604 | vcmpneh, PPC_NONE, PPC2_ISA300) |
2020b67d | 605 | GEN_VXRFORM_DUAL(vcmpequw, PPC_ALTIVEC, PPC_NONE, \ |
0fa59364 | 606 | vcmpnew, PPC_NONE, PPC2_ISA300) |
0304af89 BH |
607 | GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \ |
608 | vcmpequd, PPC_NONE, PPC2_ALTIVEC_207) | |
609 | GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \ | |
610 | vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207) | |
611 | GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \ | |
612 | vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207) | |
613 | ||
614 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \ | |
615 | static void glue(gen_, name)(DisasContext *ctx) \ | |
616 | { \ | |
617 | TCGv_ptr rd; \ | |
618 | TCGv_i32 simm; \ | |
619 | if (unlikely(!ctx->altivec_enabled)) { \ | |
620 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
621 | return; \ | |
622 | } \ | |
623 | simm = tcg_const_i32(SIMM5(ctx->opcode)); \ | |
624 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
625 | gen_helper_##name (rd, simm); \ | |
626 | tcg_temp_free_i32(simm); \ | |
627 | tcg_temp_free_ptr(rd); \ | |
628 | } | |
629 | ||
630 | GEN_VXFORM_SIMM(vspltisb, 6, 12); | |
631 | GEN_VXFORM_SIMM(vspltish, 6, 13); | |
632 | GEN_VXFORM_SIMM(vspltisw, 6, 14); | |
633 | ||
634 | #define GEN_VXFORM_NOA(name, opc2, opc3) \ | |
635 | static void glue(gen_, name)(DisasContext *ctx) \ | |
636 | { \ | |
637 | TCGv_ptr rb, rd; \ | |
638 | if (unlikely(!ctx->altivec_enabled)) { \ | |
639 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
640 | return; \ | |
641 | } \ | |
642 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
643 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
644 | gen_helper_##name (rd, rb); \ | |
645 | tcg_temp_free_ptr(rb); \ | |
646 | tcg_temp_free_ptr(rd); \ | |
647 | } | |
648 | ||
649 | #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \ | |
650 | static void glue(gen_, name)(DisasContext *ctx) \ | |
651 | { \ | |
652 | TCGv_ptr rb, rd; \ | |
653 | \ | |
654 | if (unlikely(!ctx->altivec_enabled)) { \ | |
655 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
656 | return; \ | |
657 | } \ | |
658 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
659 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
660 | gen_helper_##name(cpu_env, rd, rb); \ | |
661 | tcg_temp_free_ptr(rb); \ | |
662 | tcg_temp_free_ptr(rd); \ | |
663 | } | |
664 | ||
a5ad8fbf RS |
665 | #define GEN_VXFORM_NOA_2(name, opc2, opc3, opc4) \ |
666 | static void glue(gen_, name)(DisasContext *ctx) \ | |
667 | { \ | |
668 | TCGv_ptr rb, rd; \ | |
669 | if (unlikely(!ctx->altivec_enabled)) { \ | |
670 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
671 | return; \ | |
672 | } \ | |
673 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
674 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
675 | gen_helper_##name(rd, rb); \ | |
676 | tcg_temp_free_ptr(rb); \ | |
677 | tcg_temp_free_ptr(rd); \ | |
678 | } | |
679 | ||
4879538c RS |
680 | #define GEN_VXFORM_NOA_3(name, opc2, opc3, opc4) \ |
681 | static void glue(gen_, name)(DisasContext *ctx) \ | |
682 | { \ | |
683 | TCGv_ptr rb; \ | |
684 | if (unlikely(!ctx->altivec_enabled)) { \ | |
685 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
686 | return; \ | |
687 | } \ | |
688 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
689 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], rb); \ | |
690 | tcg_temp_free_ptr(rb); \ | |
691 | } | |
0304af89 BH |
692 | GEN_VXFORM_NOA(vupkhsb, 7, 8); |
693 | GEN_VXFORM_NOA(vupkhsh, 7, 9); | |
694 | GEN_VXFORM_NOA(vupkhsw, 7, 25); | |
695 | GEN_VXFORM_NOA(vupklsb, 7, 10); | |
696 | GEN_VXFORM_NOA(vupklsh, 7, 11); | |
697 | GEN_VXFORM_NOA(vupklsw, 7, 27); | |
698 | GEN_VXFORM_NOA(vupkhpx, 7, 13); | |
699 | GEN_VXFORM_NOA(vupklpx, 7, 15); | |
700 | GEN_VXFORM_NOA_ENV(vrefp, 5, 4); | |
701 | GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5); | |
702 | GEN_VXFORM_NOA_ENV(vexptefp, 5, 6); | |
703 | GEN_VXFORM_NOA_ENV(vlogefp, 5, 7); | |
704 | GEN_VXFORM_NOA_ENV(vrfim, 5, 11); | |
705 | GEN_VXFORM_NOA_ENV(vrfin, 5, 8); | |
706 | GEN_VXFORM_NOA_ENV(vrfip, 5, 10); | |
707 | GEN_VXFORM_NOA_ENV(vrfiz, 5, 9); | |
5c69452c AK |
708 | GEN_VXFORM_NOA(vprtybw, 1, 24); |
709 | GEN_VXFORM_NOA(vprtybd, 1, 24); | |
710 | GEN_VXFORM_NOA(vprtybq, 1, 24); | |
0304af89 BH |
711 | |
712 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \ | |
713 | static void glue(gen_, name)(DisasContext *ctx) \ | |
714 | { \ | |
715 | TCGv_ptr rd; \ | |
716 | TCGv_i32 simm; \ | |
717 | if (unlikely(!ctx->altivec_enabled)) { \ | |
718 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
719 | return; \ | |
720 | } \ | |
721 | simm = tcg_const_i32(SIMM5(ctx->opcode)); \ | |
722 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
723 | gen_helper_##name (rd, simm); \ | |
724 | tcg_temp_free_i32(simm); \ | |
725 | tcg_temp_free_ptr(rd); \ | |
726 | } | |
727 | ||
728 | #define GEN_VXFORM_UIMM(name, opc2, opc3) \ | |
729 | static void glue(gen_, name)(DisasContext *ctx) \ | |
730 | { \ | |
731 | TCGv_ptr rb, rd; \ | |
732 | TCGv_i32 uimm; \ | |
733 | if (unlikely(!ctx->altivec_enabled)) { \ | |
734 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
735 | return; \ | |
736 | } \ | |
737 | uimm = tcg_const_i32(UIMM5(ctx->opcode)); \ | |
738 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
739 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
740 | gen_helper_##name (rd, rb, uimm); \ | |
741 | tcg_temp_free_i32(uimm); \ | |
742 | tcg_temp_free_ptr(rb); \ | |
743 | tcg_temp_free_ptr(rd); \ | |
744 | } | |
745 | ||
746 | #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \ | |
747 | static void glue(gen_, name)(DisasContext *ctx) \ | |
748 | { \ | |
749 | TCGv_ptr rb, rd; \ | |
750 | TCGv_i32 uimm; \ | |
751 | \ | |
752 | if (unlikely(!ctx->altivec_enabled)) { \ | |
753 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
754 | return; \ | |
755 | } \ | |
756 | uimm = tcg_const_i32(UIMM5(ctx->opcode)); \ | |
757 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
758 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
759 | gen_helper_##name(cpu_env, rd, rb, uimm); \ | |
760 | tcg_temp_free_i32(uimm); \ | |
761 | tcg_temp_free_ptr(rb); \ | |
762 | tcg_temp_free_ptr(rd); \ | |
763 | } | |
764 | ||
e7b1e06f RS |
765 | #define GEN_VXFORM_UIMM_SPLAT(name, opc2, opc3, splat_max) \ |
766 | static void glue(gen_, name)(DisasContext *ctx) \ | |
767 | { \ | |
768 | TCGv_ptr rb, rd; \ | |
769 | uint8_t uimm = UIMM4(ctx->opcode); \ | |
770 | TCGv_i32 t0 = tcg_temp_new_i32(); \ | |
771 | if (unlikely(!ctx->altivec_enabled)) { \ | |
772 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
773 | return; \ | |
774 | } \ | |
775 | if (uimm > splat_max) { \ | |
776 | uimm = 0; \ | |
777 | } \ | |
778 | tcg_gen_movi_i32(t0, uimm); \ | |
779 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
780 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
781 | gen_helper_##name(rd, rb, t0); \ | |
782 | tcg_temp_free_i32(t0); \ | |
783 | tcg_temp_free_ptr(rb); \ | |
784 | tcg_temp_free_ptr(rd); \ | |
785 | } | |
786 | ||
0304af89 BH |
787 | GEN_VXFORM_UIMM(vspltb, 6, 8); |
788 | GEN_VXFORM_UIMM(vsplth, 6, 9); | |
789 | GEN_VXFORM_UIMM(vspltw, 6, 10); | |
b5d569a1 RS |
790 | GEN_VXFORM_UIMM_SPLAT(vextractub, 6, 8, 15); |
791 | GEN_VXFORM_UIMM_SPLAT(vextractuh, 6, 9, 14); | |
792 | GEN_VXFORM_UIMM_SPLAT(vextractuw, 6, 10, 12); | |
793 | GEN_VXFORM_UIMM_SPLAT(vextractd, 6, 11, 8); | |
e7b1e06f RS |
794 | GEN_VXFORM_UIMM_SPLAT(vinsertb, 6, 12, 15); |
795 | GEN_VXFORM_UIMM_SPLAT(vinserth, 6, 13, 14); | |
796 | GEN_VXFORM_UIMM_SPLAT(vinsertw, 6, 14, 12); | |
797 | GEN_VXFORM_UIMM_SPLAT(vinsertd, 6, 15, 8); | |
0304af89 BH |
798 | GEN_VXFORM_UIMM_ENV(vcfux, 5, 12); |
799 | GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13); | |
800 | GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14); | |
801 | GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15); | |
2020b67d ND |
802 | GEN_VXFORM_DUAL(vspltb, PPC_ALTIVEC, PPC_NONE, |
803 | vextractub, PPC_NONE, PPC2_ISA300); | |
804 | GEN_VXFORM_DUAL(vsplth, PPC_ALTIVEC, PPC_NONE, | |
805 | vextractuh, PPC_NONE, PPC2_ISA300); | |
806 | GEN_VXFORM_DUAL(vspltw, PPC_ALTIVEC, PPC_NONE, | |
807 | vextractuw, PPC_NONE, PPC2_ISA300); | |
808 | GEN_VXFORM_DUAL(vspltisb, PPC_ALTIVEC, PPC_NONE, | |
809 | vinsertb, PPC_NONE, PPC2_ISA300); | |
810 | GEN_VXFORM_DUAL(vspltish, PPC_ALTIVEC, PPC_NONE, | |
811 | vinserth, PPC_NONE, PPC2_ISA300); | |
812 | GEN_VXFORM_DUAL(vspltisw, PPC_ALTIVEC, PPC_NONE, | |
813 | vinsertw, PPC_NONE, PPC2_ISA300); | |
0304af89 BH |
814 | |
815 | static void gen_vsldoi(DisasContext *ctx) | |
816 | { | |
817 | TCGv_ptr ra, rb, rd; | |
818 | TCGv_i32 sh; | |
819 | if (unlikely(!ctx->altivec_enabled)) { | |
820 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
821 | return; | |
822 | } | |
823 | ra = gen_avr_ptr(rA(ctx->opcode)); | |
824 | rb = gen_avr_ptr(rB(ctx->opcode)); | |
825 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
826 | sh = tcg_const_i32(VSH(ctx->opcode)); | |
827 | gen_helper_vsldoi (rd, ra, rb, sh); | |
828 | tcg_temp_free_ptr(ra); | |
829 | tcg_temp_free_ptr(rb); | |
830 | tcg_temp_free_ptr(rd); | |
831 | tcg_temp_free_i32(sh); | |
832 | } | |
833 | ||
834 | #define GEN_VAFORM_PAIRED(name0, name1, opc2) \ | |
835 | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ | |
836 | { \ | |
837 | TCGv_ptr ra, rb, rc, rd; \ | |
838 | if (unlikely(!ctx->altivec_enabled)) { \ | |
839 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
840 | return; \ | |
841 | } \ | |
842 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
843 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
844 | rc = gen_avr_ptr(rC(ctx->opcode)); \ | |
845 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
846 | if (Rc(ctx->opcode)) { \ | |
847 | gen_helper_##name1(cpu_env, rd, ra, rb, rc); \ | |
848 | } else { \ | |
849 | gen_helper_##name0(cpu_env, rd, ra, rb, rc); \ | |
850 | } \ | |
851 | tcg_temp_free_ptr(ra); \ | |
852 | tcg_temp_free_ptr(rb); \ | |
853 | tcg_temp_free_ptr(rc); \ | |
854 | tcg_temp_free_ptr(rd); \ | |
855 | } | |
856 | ||
857 | GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16) | |
858 | ||
859 | static void gen_vmladduhm(DisasContext *ctx) | |
860 | { | |
861 | TCGv_ptr ra, rb, rc, rd; | |
862 | if (unlikely(!ctx->altivec_enabled)) { | |
863 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
864 | return; | |
865 | } | |
866 | ra = gen_avr_ptr(rA(ctx->opcode)); | |
867 | rb = gen_avr_ptr(rB(ctx->opcode)); | |
868 | rc = gen_avr_ptr(rC(ctx->opcode)); | |
869 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
870 | gen_helper_vmladduhm(rd, ra, rb, rc); | |
871 | tcg_temp_free_ptr(ra); | |
872 | tcg_temp_free_ptr(rb); | |
873 | tcg_temp_free_ptr(rc); | |
874 | tcg_temp_free_ptr(rd); | |
875 | } | |
876 | ||
ab045436 RS |
877 | static void gen_vpermr(DisasContext *ctx) |
878 | { | |
879 | TCGv_ptr ra, rb, rc, rd; | |
880 | if (unlikely(!ctx->altivec_enabled)) { | |
881 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
882 | return; | |
883 | } | |
884 | ra = gen_avr_ptr(rA(ctx->opcode)); | |
885 | rb = gen_avr_ptr(rB(ctx->opcode)); | |
886 | rc = gen_avr_ptr(rC(ctx->opcode)); | |
887 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
888 | gen_helper_vpermr(cpu_env, rd, ra, rb, rc); | |
889 | tcg_temp_free_ptr(ra); | |
890 | tcg_temp_free_ptr(rb); | |
891 | tcg_temp_free_ptr(rc); | |
892 | tcg_temp_free_ptr(rd); | |
893 | } | |
894 | ||
0304af89 BH |
895 | GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18) |
896 | GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19) | |
897 | GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20) | |
898 | GEN_VAFORM_PAIRED(vsel, vperm, 21) | |
899 | GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23) | |
900 | ||
901 | GEN_VXFORM_NOA(vclzb, 1, 28) | |
902 | GEN_VXFORM_NOA(vclzh, 1, 29) | |
903 | GEN_VXFORM_NOA(vclzw, 1, 30) | |
904 | GEN_VXFORM_NOA(vclzd, 1, 31) | |
cc8b6e76 ND |
905 | GEN_VXFORM_NOA_2(vnegw, 1, 24, 6) |
906 | GEN_VXFORM_NOA_2(vnegd, 1, 24, 7) | |
125a9b23 ND |
907 | GEN_VXFORM_NOA_2(vextsb2w, 1, 24, 16) |
908 | GEN_VXFORM_NOA_2(vextsh2w, 1, 24, 17) | |
909 | GEN_VXFORM_NOA_2(vextsb2d, 1, 24, 24) | |
910 | GEN_VXFORM_NOA_2(vextsh2d, 1, 24, 25) | |
911 | GEN_VXFORM_NOA_2(vextsw2d, 1, 24, 26) | |
a5ad8fbf RS |
912 | GEN_VXFORM_NOA_2(vctzb, 1, 24, 28) |
913 | GEN_VXFORM_NOA_2(vctzh, 1, 24, 29) | |
914 | GEN_VXFORM_NOA_2(vctzw, 1, 24, 30) | |
915 | GEN_VXFORM_NOA_2(vctzd, 1, 24, 31) | |
4879538c RS |
916 | GEN_VXFORM_NOA_3(vclzlsbb, 1, 24, 0) |
917 | GEN_VXFORM_NOA_3(vctzlsbb, 1, 24, 1) | |
0304af89 BH |
918 | GEN_VXFORM_NOA(vpopcntb, 1, 28) |
919 | GEN_VXFORM_NOA(vpopcnth, 1, 29) | |
920 | GEN_VXFORM_NOA(vpopcntw, 1, 30) | |
921 | GEN_VXFORM_NOA(vpopcntd, 1, 31) | |
922 | GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \ | |
923 | vpopcntb, PPC_NONE, PPC2_ALTIVEC_207) | |
924 | GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \ | |
925 | vpopcnth, PPC_NONE, PPC2_ALTIVEC_207) | |
926 | GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \ | |
927 | vpopcntw, PPC_NONE, PPC2_ALTIVEC_207) | |
928 | GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \ | |
929 | vpopcntd, PPC_NONE, PPC2_ALTIVEC_207) | |
01fe9a47 | 930 | GEN_VXFORM(vbpermd, 6, 23); |
0304af89 BH |
931 | GEN_VXFORM(vbpermq, 6, 21); |
932 | GEN_VXFORM_NOA(vgbbd, 6, 20); | |
933 | GEN_VXFORM(vpmsumb, 4, 16) | |
934 | GEN_VXFORM(vpmsumh, 4, 17) | |
935 | GEN_VXFORM(vpmsumw, 4, 18) | |
936 | GEN_VXFORM(vpmsumd, 4, 19) | |
937 | ||
938 | #define GEN_BCD(op) \ | |
939 | static void gen_##op(DisasContext *ctx) \ | |
940 | { \ | |
941 | TCGv_ptr ra, rb, rd; \ | |
942 | TCGv_i32 ps; \ | |
943 | \ | |
944 | if (unlikely(!ctx->altivec_enabled)) { \ | |
945 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
946 | return; \ | |
947 | } \ | |
948 | \ | |
949 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
950 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
951 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
952 | \ | |
953 | ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \ | |
954 | \ | |
955 | gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \ | |
956 | \ | |
957 | tcg_temp_free_ptr(ra); \ | |
958 | tcg_temp_free_ptr(rb); \ | |
959 | tcg_temp_free_ptr(rd); \ | |
960 | tcg_temp_free_i32(ps); \ | |
961 | } | |
962 | ||
b8155872 JRZ |
963 | #define GEN_BCD2(op) \ |
964 | static void gen_##op(DisasContext *ctx) \ | |
965 | { \ | |
966 | TCGv_ptr rd, rb; \ | |
967 | TCGv_i32 ps; \ | |
968 | \ | |
969 | if (unlikely(!ctx->altivec_enabled)) { \ | |
970 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
971 | return; \ | |
972 | } \ | |
973 | \ | |
974 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
975 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
976 | \ | |
977 | ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \ | |
978 | \ | |
979 | gen_helper_##op(cpu_crf[6], rd, rb, ps); \ | |
980 | \ | |
981 | tcg_temp_free_ptr(rb); \ | |
982 | tcg_temp_free_ptr(rd); \ | |
983 | tcg_temp_free_i32(ps); \ | |
984 | } | |
985 | ||
0304af89 BH |
986 | GEN_BCD(bcdadd) |
987 | GEN_BCD(bcdsub) | |
b8155872 | 988 | GEN_BCD2(bcdcfn) |
e2106d73 | 989 | GEN_BCD2(bcdctn) |
38f4cb04 | 990 | GEN_BCD2(bcdcfz) |
0a890b31 | 991 | GEN_BCD2(bcdctz) |
a406c058 | 992 | GEN_BCD2(bcdcfsq) |
c85bc7dd | 993 | GEN_BCD2(bcdctsq) |
b8155872 JRZ |
994 | |
995 | static void gen_xpnd04_1(DisasContext *ctx) | |
996 | { | |
997 | switch (opc4(ctx->opcode)) { | |
c85bc7dd JRZ |
998 | case 0: |
999 | gen_bcdctsq(ctx); | |
1000 | break; | |
a406c058 JRZ |
1001 | case 2: |
1002 | gen_bcdcfsq(ctx); | |
1003 | break; | |
0a890b31 JRZ |
1004 | case 4: |
1005 | gen_bcdctz(ctx); | |
1006 | break; | |
e2106d73 JRZ |
1007 | case 5: |
1008 | gen_bcdctn(ctx); | |
1009 | break; | |
38f4cb04 JRZ |
1010 | case 6: |
1011 | gen_bcdcfz(ctx); | |
1012 | break; | |
b8155872 JRZ |
1013 | case 7: |
1014 | gen_bcdcfn(ctx); | |
1015 | break; | |
1016 | default: | |
1017 | gen_invalid(ctx); | |
1018 | break; | |
1019 | } | |
1020 | } | |
1021 | ||
1022 | static void gen_xpnd04_2(DisasContext *ctx) | |
1023 | { | |
1024 | switch (opc4(ctx->opcode)) { | |
c85bc7dd JRZ |
1025 | case 0: |
1026 | gen_bcdctsq(ctx); | |
1027 | break; | |
a406c058 JRZ |
1028 | case 2: |
1029 | gen_bcdcfsq(ctx); | |
1030 | break; | |
0a890b31 JRZ |
1031 | case 4: |
1032 | gen_bcdctz(ctx); | |
1033 | break; | |
38f4cb04 JRZ |
1034 | case 6: |
1035 | gen_bcdcfz(ctx); | |
1036 | break; | |
b8155872 JRZ |
1037 | case 7: |
1038 | gen_bcdcfn(ctx); | |
1039 | break; | |
1040 | default: | |
1041 | gen_invalid(ctx); | |
1042 | break; | |
1043 | } | |
1044 | } | |
1045 | ||
1046 | GEN_VXFORM_DUAL(vsubcuw, PPC_ALTIVEC, PPC_NONE, \ | |
1047 | xpnd04_1, PPC_NONE, PPC2_ISA300) | |
1048 | GEN_VXFORM_DUAL(vsubsws, PPC_ALTIVEC, PPC_NONE, \ | |
1049 | xpnd04_2, PPC_NONE, PPC2_ISA300) | |
0304af89 BH |
1050 | |
1051 | GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \ | |
1052 | bcdadd, PPC_NONE, PPC2_ALTIVEC_207) | |
1053 | GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \ | |
1054 | bcdadd, PPC_NONE, PPC2_ALTIVEC_207) | |
1055 | GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \ | |
1056 | bcdsub, PPC_NONE, PPC2_ALTIVEC_207) | |
1057 | GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \ | |
1058 | bcdsub, PPC_NONE, PPC2_ALTIVEC_207) | |
1059 | ||
1060 | static void gen_vsbox(DisasContext *ctx) | |
1061 | { | |
1062 | TCGv_ptr ra, rd; | |
1063 | if (unlikely(!ctx->altivec_enabled)) { | |
1064 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
1065 | return; | |
1066 | } | |
1067 | ra = gen_avr_ptr(rA(ctx->opcode)); | |
1068 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
1069 | gen_helper_vsbox(rd, ra); | |
1070 | tcg_temp_free_ptr(ra); | |
1071 | tcg_temp_free_ptr(rd); | |
1072 | } | |
1073 | ||
1074 | GEN_VXFORM(vcipher, 4, 20) | |
1075 | GEN_VXFORM(vcipherlast, 4, 20) | |
1076 | GEN_VXFORM(vncipher, 4, 21) | |
1077 | GEN_VXFORM(vncipherlast, 4, 21) | |
1078 | ||
1079 | GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207, | |
1080 | vcipherlast, PPC_NONE, PPC2_ALTIVEC_207) | |
1081 | GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207, | |
1082 | vncipherlast, PPC_NONE, PPC2_ALTIVEC_207) | |
1083 | ||
1084 | #define VSHASIGMA(op) \ | |
1085 | static void gen_##op(DisasContext *ctx) \ | |
1086 | { \ | |
1087 | TCGv_ptr ra, rd; \ | |
1088 | TCGv_i32 st_six; \ | |
1089 | if (unlikely(!ctx->altivec_enabled)) { \ | |
1090 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
1091 | return; \ | |
1092 | } \ | |
1093 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
1094 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
1095 | st_six = tcg_const_i32(rB(ctx->opcode)); \ | |
1096 | gen_helper_##op(rd, ra, st_six); \ | |
1097 | tcg_temp_free_ptr(ra); \ | |
1098 | tcg_temp_free_ptr(rd); \ | |
1099 | tcg_temp_free_i32(st_six); \ | |
1100 | } | |
1101 | ||
1102 | VSHASIGMA(vshasigmaw) | |
1103 | VSHASIGMA(vshasigmad) | |
1104 | ||
1105 | GEN_VXFORM3(vpermxor, 22, 0xFF) | |
1106 | GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE, | |
1107 | vpermxor, PPC_NONE, PPC2_ALTIVEC_207) | |
1108 | ||
1109 | #undef GEN_VR_LDX | |
1110 | #undef GEN_VR_STX | |
1111 | #undef GEN_VR_LVE | |
1112 | #undef GEN_VR_STVE | |
1113 | ||
1114 | #undef GEN_VX_LOGICAL | |
1115 | #undef GEN_VX_LOGICAL_207 | |
1116 | #undef GEN_VXFORM | |
1117 | #undef GEN_VXFORM_207 | |
1118 | #undef GEN_VXFORM_DUAL | |
1119 | #undef GEN_VXRFORM_DUAL | |
1120 | #undef GEN_VXRFORM1 | |
1121 | #undef GEN_VXRFORM | |
1122 | #undef GEN_VXFORM_SIMM | |
1123 | #undef GEN_VXFORM_NOA | |
1124 | #undef GEN_VXFORM_UIMM | |
1125 | #undef GEN_VAFORM_PAIRED | |
b8155872 JRZ |
1126 | |
1127 | #undef GEN_BCD2 |