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target/ppc: move Vsr* macros from internal.h to cpu.h
[mirror_qemu.git] / target / ppc / translate / vmx-impl.inc.c
CommitLineData
0304af89
BH		 1/*
2 * translate/vmx-impl.c
3 *
4 * Altivec/VMX translation
5 */
6
7/*** Altivec vector extension ***/
8/* Altivec registers moves */
9
10static inline TCGv_ptr gen_avr_ptr(int reg)
11{
12 TCGv_ptr r = tcg_temp_new_ptr();
ef96e3ae 13 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, vsr[32 + reg].u64[0]));
0304af89
BH		 14 return r;
15}
16
ef96e3ae
MCA		 17static inline long avr64_offset(int reg, bool high)
18{
19 return offsetof(CPUPPCState, vsr[32 + reg].u64[(high ? 0 : 1)]);
20}
21
0304af89
BH		 22#define GEN_VR_LDX(name, opc2, opc3) \
23static void glue(gen_, name)(DisasContext *ctx) \
24{ \
25 TCGv EA; \
c4a18dbf 26 TCGv_i64 avr; \
0304af89
BH		 27 if (unlikely(!ctx->altivec_enabled)) { \
28 gen_exception(ctx, POWERPC_EXCP_VPU); \
29 return; \
30 } \
31 gen_set_access_type(ctx, ACCESS_INT); \
c4a18dbf 32 avr = tcg_temp_new_i64(); \
0304af89
BH		 33 EA = tcg_temp_new(); \
34 gen_addr_reg_index(ctx, EA); \
35 tcg_gen_andi_tl(EA, EA, ~0xf); \
4f364fe7
ND		 36 /* We only need to swap high and low halves. gen_qemu_ld64_i64 does \
37 necessary 64-bit byteswap already. */ \
0304af89 38 if (ctx->le_mode) { \
c4a18dbf
MCA		 39 gen_qemu_ld64_i64(ctx, avr, EA); \
40 set_avr64(rD(ctx->opcode), avr, false); \
0304af89 41 tcg_gen_addi_tl(EA, EA, 8); \
c4a18dbf
MCA		 42 gen_qemu_ld64_i64(ctx, avr, EA); \
43 set_avr64(rD(ctx->opcode), avr, true); \
0304af89 44 } else { \
c4a18dbf
MCA		 45 gen_qemu_ld64_i64(ctx, avr, EA); \
46 set_avr64(rD(ctx->opcode), avr, true); \
0304af89 47 tcg_gen_addi_tl(EA, EA, 8); \
c4a18dbf
MCA		 48 gen_qemu_ld64_i64(ctx, avr, EA); \
49 set_avr64(rD(ctx->opcode), avr, false); \
0304af89
BH		 50 } \
51 tcg_temp_free(EA); \
c4a18dbf 52 tcg_temp_free_i64(avr); \
0304af89
BH		 53}
54
55#define GEN_VR_STX(name, opc2, opc3) \
56static void gen_st##name(DisasContext *ctx) \
57{ \
58 TCGv EA; \
c4a18dbf 59 TCGv_i64 avr; \
0304af89
BH		 60 if (unlikely(!ctx->altivec_enabled)) { \
61 gen_exception(ctx, POWERPC_EXCP_VPU); \
62 return; \
63 } \
64 gen_set_access_type(ctx, ACCESS_INT); \
c4a18dbf 65 avr = tcg_temp_new_i64(); \
0304af89
BH		 66 EA = tcg_temp_new(); \
67 gen_addr_reg_index(ctx, EA); \
68 tcg_gen_andi_tl(EA, EA, ~0xf); \
2468f23d
ND		 69 /* We only need to swap high and low halves. gen_qemu_st64_i64 does \
70 necessary 64-bit byteswap already. */ \
0304af89 71 if (ctx->le_mode) { \
c4a18dbf
MCA		 72 get_avr64(avr, rD(ctx->opcode), false); \
73 gen_qemu_st64_i64(ctx, avr, EA); \
0304af89 74 tcg_gen_addi_tl(EA, EA, 8); \
c4a18dbf
MCA		 75 get_avr64(avr, rD(ctx->opcode), true); \
76 gen_qemu_st64_i64(ctx, avr, EA); \
0304af89 77 } else { \
c4a18dbf
MCA		 78 get_avr64(avr, rD(ctx->opcode), true); \
79 gen_qemu_st64_i64(ctx, avr, EA); \
0304af89 80 tcg_gen_addi_tl(EA, EA, 8); \
c4a18dbf
MCA		 81 get_avr64(avr, rD(ctx->opcode), false); \
82 gen_qemu_st64_i64(ctx, avr, EA); \
0304af89
BH		 83 } \
84 tcg_temp_free(EA); \
c4a18dbf 85 tcg_temp_free_i64(avr); \
0304af89
BH		 86}
87
88#define GEN_VR_LVE(name, opc2, opc3, size) \
89static void gen_lve##name(DisasContext *ctx) \
90 { \
91 TCGv EA; \
92 TCGv_ptr rs; \
93 if (unlikely(!ctx->altivec_enabled)) { \
94 gen_exception(ctx, POWERPC_EXCP_VPU); \
95 return; \
96 } \
97 gen_set_access_type(ctx, ACCESS_INT); \
98 EA = tcg_temp_new(); \
99 gen_addr_reg_index(ctx, EA); \
100 if (size > 1) { \
101 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
102 } \
103 rs = gen_avr_ptr(rS(ctx->opcode)); \
104 gen_helper_lve##name(cpu_env, rs, EA); \
105 tcg_temp_free(EA); \
106 tcg_temp_free_ptr(rs); \
107 }
108
109#define GEN_VR_STVE(name, opc2, opc3, size) \
110static void gen_stve##name(DisasContext *ctx) \
111 { \
112 TCGv EA; \
113 TCGv_ptr rs; \
114 if (unlikely(!ctx->altivec_enabled)) { \
115 gen_exception(ctx, POWERPC_EXCP_VPU); \
116 return; \
117 } \
118 gen_set_access_type(ctx, ACCESS_INT); \
119 EA = tcg_temp_new(); \
120 gen_addr_reg_index(ctx, EA); \
121 if (size > 1) { \
122 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
123 } \
124 rs = gen_avr_ptr(rS(ctx->opcode)); \
125 gen_helper_stve##name(cpu_env, rs, EA); \
126 tcg_temp_free(EA); \
127 tcg_temp_free_ptr(rs); \
128 }
129
130GEN_VR_LDX(lvx, 0x07, 0x03);
131/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
132GEN_VR_LDX(lvxl, 0x07, 0x0B);
133
134GEN_VR_LVE(bx, 0x07, 0x00, 1);
135GEN_VR_LVE(hx, 0x07, 0x01, 2);
136GEN_VR_LVE(wx, 0x07, 0x02, 4);
137
138GEN_VR_STX(svx, 0x07, 0x07);
139/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
140GEN_VR_STX(svxl, 0x07, 0x0F);
141
142GEN_VR_STVE(bx, 0x07, 0x04, 1);
143GEN_VR_STVE(hx, 0x07, 0x05, 2);
144GEN_VR_STVE(wx, 0x07, 0x06, 4);
145
146static void gen_lvsl(DisasContext *ctx)
147{
148 TCGv_ptr rd;
149 TCGv EA;
150 if (unlikely(!ctx->altivec_enabled)) {
151 gen_exception(ctx, POWERPC_EXCP_VPU);
152 return;
153 }
154 EA = tcg_temp_new();
155 gen_addr_reg_index(ctx, EA);
156 rd = gen_avr_ptr(rD(ctx->opcode));
157 gen_helper_lvsl(rd, EA);
158 tcg_temp_free(EA);
159 tcg_temp_free_ptr(rd);
160}
161
162static void gen_lvsr(DisasContext *ctx)
163{
164 TCGv_ptr rd;
165 TCGv EA;
166 if (unlikely(!ctx->altivec_enabled)) {
167 gen_exception(ctx, POWERPC_EXCP_VPU);
168 return;
169 }
170 EA = tcg_temp_new();
171 gen_addr_reg_index(ctx, EA);
172 rd = gen_avr_ptr(rD(ctx->opcode));
173 gen_helper_lvsr(rd, EA);
174 tcg_temp_free(EA);
175 tcg_temp_free_ptr(rd);
176}
177
178static void gen_mfvscr(DisasContext *ctx)
179{
180 TCGv_i32 t;
c4a18dbf 181 TCGv_i64 avr;
0304af89
BH		 182 if (unlikely(!ctx->altivec_enabled)) {
183 gen_exception(ctx, POWERPC_EXCP_VPU);
184 return;
185 }
c4a18dbf
MCA		 186 avr = tcg_temp_new_i64();
187 tcg_gen_movi_i64(avr, 0);
188 set_avr64(rD(ctx->opcode), avr, true);
0304af89 189 t = tcg_temp_new_i32();
cc2b90d7 190 gen_helper_mfvscr(t, cpu_env);
c4a18dbf
MCA		 191 tcg_gen_extu_i32_i64(avr, t);
192 set_avr64(rD(ctx->opcode), avr, false);
0304af89 193 tcg_temp_free_i32(t);
c4a18dbf 194 tcg_temp_free_i64(avr);
0304af89
BH		 195}
196
197static void gen_mtvscr(DisasContext *ctx)
198{
dedfaac7
RH		 199 TCGv_i32 val;
200 int bofs;
201
0304af89
BH		 202 if (unlikely(!ctx->altivec_enabled)) {
203 gen_exception(ctx, POWERPC_EXCP_VPU);
204 return;
205 }
dedfaac7
RH		 206
207 val = tcg_temp_new_i32();
208 bofs = avr64_offset(rB(ctx->opcode), true);
209#ifdef HOST_WORDS_BIGENDIAN
210 bofs += 3 * 4;
211#endif
212
213 tcg_gen_ld_i32(val, cpu_env, bofs);
214 gen_helper_mtvscr(cpu_env, val);
215 tcg_temp_free_i32(val);
0304af89
BH		 216}
217
37ad52ba
VH		 218#define GEN_VX_VMUL10(name, add_cin, ret_carry) \
219static void glue(gen_, name)(DisasContext *ctx) \
220{ \
c4a18dbf
MCA		 221 TCGv_i64 t0; \
222 TCGv_i64 t1; \
223 TCGv_i64 t2; \
224 TCGv_i64 avr; \
37ad52ba
VH		 225 TCGv_i64 ten, z; \
226 \
227 if (unlikely(!ctx->altivec_enabled)) { \
228 gen_exception(ctx, POWERPC_EXCP_VPU); \
229 return; \
230 } \
231 \
c4a18dbf
MCA		 232 t0 = tcg_temp_new_i64(); \
233 t1 = tcg_temp_new_i64(); \
234 t2 = tcg_temp_new_i64(); \
235 avr = tcg_temp_new_i64(); \
37ad52ba
VH		 236 ten = tcg_const_i64(10); \
237 z = tcg_const_i64(0); \
238 \
239 if (add_cin) { \
c4a18dbf
MCA		 240 get_avr64(avr, rA(ctx->opcode), false); \
241 tcg_gen_mulu2_i64(t0, t1, avr, ten); \
242 get_avr64(avr, rB(ctx->opcode), false); \
243 tcg_gen_andi_i64(t2, avr, 0xF); \
244 tcg_gen_add2_i64(avr, t2, t0, t1, t2, z); \
245 set_avr64(rD(ctx->opcode), avr, false); \
37ad52ba 246 } else { \
c4a18dbf
MCA		 247 get_avr64(avr, rA(ctx->opcode), false); \
248 tcg_gen_mulu2_i64(avr, t2, avr, ten); \
249 set_avr64(rD(ctx->opcode), avr, false); \
37ad52ba
VH		 250 } \
251 \
252 if (ret_carry) { \
c4a18dbf
MCA		 253 get_avr64(avr, rA(ctx->opcode), true); \
254 tcg_gen_mulu2_i64(t0, t1, avr, ten); \
255 tcg_gen_add2_i64(t0, avr, t0, t1, t2, z); \
256 set_avr64(rD(ctx->opcode), avr, false); \
257 set_avr64(rD(ctx->opcode), z, true); \
37ad52ba 258 } else { \
c4a18dbf
MCA		 259 get_avr64(avr, rA(ctx->opcode), true); \
260 tcg_gen_mul_i64(t0, avr, ten); \
261 tcg_gen_add_i64(avr, t0, t2); \
262 set_avr64(rD(ctx->opcode), avr, true); \
37ad52ba
VH		 263 } \
264 \
265 tcg_temp_free_i64(t0); \
266 tcg_temp_free_i64(t1); \
267 tcg_temp_free_i64(t2); \
c4a18dbf 268 tcg_temp_free_i64(avr); \
37ad52ba
VH		 269 tcg_temp_free_i64(ten); \
270 tcg_temp_free_i64(z); \
271} \
272
273GEN_VX_VMUL10(vmul10uq, 0, 0);
274GEN_VX_VMUL10(vmul10euq, 1, 0);
275GEN_VX_VMUL10(vmul10cuq, 0, 1);
276GEN_VX_VMUL10(vmul10ecuq, 1, 1);
277
50d24aed
MCA		 278#define GEN_VXFORM_V(name, vece, tcg_op, opc2, opc3) \
279static void glue(gen_, name)(DisasContext *ctx) \
0304af89
BH		 280{ \
281 if (unlikely(!ctx->altivec_enabled)) { \
282 gen_exception(ctx, POWERPC_EXCP_VPU); \
283 return; \
284 } \
c4a18dbf 285 \
50d24aed
MCA		 286 tcg_op(vece, \
287 avr64_offset(rD(ctx->opcode), true), \
288 avr64_offset(rA(ctx->opcode), true), \
289 avr64_offset(rB(ctx->opcode), true), \
290 16, 16); \
0304af89
BH		 291}
292
50d24aed
MCA		 293/* Logical operations */
294GEN_VXFORM_V(vand, MO_64, tcg_gen_gvec_and, 2, 16);
295GEN_VXFORM_V(vandc, MO_64, tcg_gen_gvec_andc, 2, 17);
296GEN_VXFORM_V(vor, MO_64, tcg_gen_gvec_or, 2, 18);
297GEN_VXFORM_V(vxor, MO_64, tcg_gen_gvec_xor, 2, 19);
298GEN_VXFORM_V(vnor, MO_64, tcg_gen_gvec_nor, 2, 20);
299GEN_VXFORM_V(veqv, MO_64, tcg_gen_gvec_eqv, 2, 26);
300GEN_VXFORM_V(vnand, MO_64, tcg_gen_gvec_nand, 2, 22);
301GEN_VXFORM_V(vorc, MO_64, tcg_gen_gvec_orc, 2, 21);
0304af89
BH		 302
303#define GEN_VXFORM(name, opc2, opc3) \
304static void glue(gen_, name)(DisasContext *ctx) \
305{ \
306 TCGv_ptr ra, rb, rd; \
307 if (unlikely(!ctx->altivec_enabled)) { \
308 gen_exception(ctx, POWERPC_EXCP_VPU); \
309 return; \
310 } \
311 ra = gen_avr_ptr(rA(ctx->opcode)); \
312 rb = gen_avr_ptr(rB(ctx->opcode)); \
313 rd = gen_avr_ptr(rD(ctx->opcode)); \
314 gen_helper_##name (rd, ra, rb); \
315 tcg_temp_free_ptr(ra); \
316 tcg_temp_free_ptr(rb); \
317 tcg_temp_free_ptr(rd); \
318}
319
320#define GEN_VXFORM_ENV(name, opc2, opc3) \
321static void glue(gen_, name)(DisasContext *ctx) \
322{ \
323 TCGv_ptr ra, rb, rd; \
324 if (unlikely(!ctx->altivec_enabled)) { \
325 gen_exception(ctx, POWERPC_EXCP_VPU); \
326 return; \
327 } \
328 ra = gen_avr_ptr(rA(ctx->opcode)); \
329 rb = gen_avr_ptr(rB(ctx->opcode)); \
330 rd = gen_avr_ptr(rD(ctx->opcode)); \
331 gen_helper_##name(cpu_env, rd, ra, rb); \
332 tcg_temp_free_ptr(ra); \
333 tcg_temp_free_ptr(rb); \
334 tcg_temp_free_ptr(rd); \
335}
336
337#define GEN_VXFORM3(name, opc2, opc3) \
338static void glue(gen_, name)(DisasContext *ctx) \
339{ \
340 TCGv_ptr ra, rb, rc, rd; \
341 if (unlikely(!ctx->altivec_enabled)) { \
342 gen_exception(ctx, POWERPC_EXCP_VPU); \
343 return; \
344 } \
345 ra = gen_avr_ptr(rA(ctx->opcode)); \
346 rb = gen_avr_ptr(rB(ctx->opcode)); \
347 rc = gen_avr_ptr(rC(ctx->opcode)); \
348 rd = gen_avr_ptr(rD(ctx->opcode)); \
349 gen_helper_##name(rd, ra, rb, rc); \
350 tcg_temp_free_ptr(ra); \
351 tcg_temp_free_ptr(rb); \
352 tcg_temp_free_ptr(rc); \
353 tcg_temp_free_ptr(rd); \
354}
355
356/*
357 * Support for Altivec instruction pairs that use bit 31 (Rc) as
358 * an opcode bit. In general, these pairs come from different
359 * versions of the ISA, so we must also support a pair of flags for
360 * each instruction.
361 */
362#define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
363static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
364{ \
365 if ((Rc(ctx->opcode) == 0) && \
366 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
367 gen_##name0(ctx); \
368 } else if ((Rc(ctx->opcode) == 1) && \
369 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
370 gen_##name1(ctx); \
371 } else { \
372 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
373 } \
374}
375
37ad52ba
VH		 376/* Adds support to provide invalid mask */
377#define GEN_VXFORM_DUAL_EXT(name0, flg0, flg2_0, inval0, \
378 name1, flg1, flg2_1, inval1) \
379static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
380{ \
381 if ((Rc(ctx->opcode) == 0) && \
382 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0)) && \
383 !(ctx->opcode & inval0)) { \
384 gen_##name0(ctx); \
385 } else if ((Rc(ctx->opcode) == 1) && \
386 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1)) && \
387 !(ctx->opcode & inval1)) { \
388 gen_##name1(ctx); \
389 } else { \
390 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
391 } \
392}
393
60caf221
AK		 394#define GEN_VXFORM_HETRO(name, opc2, opc3) \
395static void glue(gen_, name)(DisasContext *ctx) \
396{ \
397 TCGv_ptr rb; \
398 if (unlikely(!ctx->altivec_enabled)) { \
399 gen_exception(ctx, POWERPC_EXCP_VPU); \
400 return; \
401 } \
402 rb = gen_avr_ptr(rB(ctx->opcode)); \
403 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], rb); \
404 tcg_temp_free_ptr(rb); \
405}
406
3e942a1a 407GEN_VXFORM_V(vaddubm, MO_8, tcg_gen_gvec_add, 0, 0);
37ad52ba
VH		 408GEN_VXFORM_DUAL_EXT(vaddubm, PPC_ALTIVEC, PPC_NONE, 0, \
409 vmul10cuq, PPC_NONE, PPC2_ISA300, 0x0000F800)
3e942a1a 410GEN_VXFORM_V(vadduhm, MO_16, tcg_gen_gvec_add, 0, 1);
37ad52ba
VH		 411GEN_VXFORM_DUAL(vadduhm, PPC_ALTIVEC, PPC_NONE, \
412 vmul10ecuq, PPC_NONE, PPC2_ISA300)
3e942a1a
MCA		 413GEN_VXFORM_V(vadduwm, MO_32, tcg_gen_gvec_add, 0, 2);
414GEN_VXFORM_V(vaddudm, MO_64, tcg_gen_gvec_add, 0, 3);
415GEN_VXFORM_V(vsububm, MO_8, tcg_gen_gvec_sub, 0, 16);
416GEN_VXFORM_V(vsubuhm, MO_16, tcg_gen_gvec_sub, 0, 17);
417GEN_VXFORM_V(vsubuwm, MO_32, tcg_gen_gvec_sub, 0, 18);
418GEN_VXFORM_V(vsubudm, MO_64, tcg_gen_gvec_sub, 0, 19);
73e14c6a
RH		 419GEN_VXFORM_V(vmaxub, MO_8, tcg_gen_gvec_umax, 1, 0);
420GEN_VXFORM_V(vmaxuh, MO_16, tcg_gen_gvec_umax, 1, 1);
421GEN_VXFORM_V(vmaxuw, MO_32, tcg_gen_gvec_umax, 1, 2);
422GEN_VXFORM_V(vmaxud, MO_64, tcg_gen_gvec_umax, 1, 3);
423GEN_VXFORM_V(vmaxsb, MO_8, tcg_gen_gvec_smax, 1, 4);
424GEN_VXFORM_V(vmaxsh, MO_16, tcg_gen_gvec_smax, 1, 5);
425GEN_VXFORM_V(vmaxsw, MO_32, tcg_gen_gvec_smax, 1, 6);
426GEN_VXFORM_V(vmaxsd, MO_64, tcg_gen_gvec_smax, 1, 7);
427GEN_VXFORM_V(vminub, MO_8, tcg_gen_gvec_umin, 1, 8);
428GEN_VXFORM_V(vminuh, MO_16, tcg_gen_gvec_umin, 1, 9);
429GEN_VXFORM_V(vminuw, MO_32, tcg_gen_gvec_umin, 1, 10);
430GEN_VXFORM_V(vminud, MO_64, tcg_gen_gvec_umin, 1, 11);
431GEN_VXFORM_V(vminsb, MO_8, tcg_gen_gvec_smin, 1, 12);
432GEN_VXFORM_V(vminsh, MO_16, tcg_gen_gvec_smin, 1, 13);
433GEN_VXFORM_V(vminsw, MO_32, tcg_gen_gvec_smin, 1, 14);
434GEN_VXFORM_V(vminsd, MO_64, tcg_gen_gvec_smin, 1, 15);
0304af89 435GEN_VXFORM(vavgub, 1, 16);
37707059
SD		 436GEN_VXFORM(vabsdub, 1, 16);
437GEN_VXFORM_DUAL(vavgub, PPC_ALTIVEC, PPC_NONE, \
438 vabsdub, PPC_NONE, PPC2_ISA300)
0304af89 439GEN_VXFORM(vavguh, 1, 17);
37707059
SD		 440GEN_VXFORM(vabsduh, 1, 17);
441GEN_VXFORM_DUAL(vavguh, PPC_ALTIVEC, PPC_NONE, \
442 vabsduh, PPC_NONE, PPC2_ISA300)
0304af89 443GEN_VXFORM(vavguw, 1, 18);
37707059
SD		 444GEN_VXFORM(vabsduw, 1, 18);
445GEN_VXFORM_DUAL(vavguw, PPC_ALTIVEC, PPC_NONE, \
446 vabsduw, PPC_NONE, PPC2_ISA300)
0304af89
BH		 447GEN_VXFORM(vavgsb, 1, 20);
448GEN_VXFORM(vavgsh, 1, 21);
449GEN_VXFORM(vavgsw, 1, 22);
450GEN_VXFORM(vmrghb, 6, 0);
451GEN_VXFORM(vmrghh, 6, 1);
452GEN_VXFORM(vmrghw, 6, 2);
453GEN_VXFORM(vmrglb, 6, 4);
454GEN_VXFORM(vmrglh, 6, 5);
455GEN_VXFORM(vmrglw, 6, 6);
456
457static void gen_vmrgew(DisasContext *ctx)
458{
459 TCGv_i64 tmp;
c4a18dbf 460 TCGv_i64 avr;
0304af89
BH		 461 int VT, VA, VB;
462 if (unlikely(!ctx->altivec_enabled)) {
463 gen_exception(ctx, POWERPC_EXCP_VPU);
464 return;
465 }
466 VT = rD(ctx->opcode);
467 VA = rA(ctx->opcode);
468 VB = rB(ctx->opcode);
469 tmp = tcg_temp_new_i64();
c4a18dbf
MCA		 470 avr = tcg_temp_new_i64();
471
472 get_avr64(avr, VB, true);
473 tcg_gen_shri_i64(tmp, avr, 32);
474 get_avr64(avr, VA, true);
475 tcg_gen_deposit_i64(avr, avr, tmp, 0, 32);
476 set_avr64(VT, avr, true);
477
478 get_avr64(avr, VB, false);
479 tcg_gen_shri_i64(tmp, avr, 32);
480 get_avr64(avr, VA, false);
481 tcg_gen_deposit_i64(avr, avr, tmp, 0, 32);
482 set_avr64(VT, avr, false);
483
0304af89 484 tcg_temp_free_i64(tmp);
c4a18dbf 485 tcg_temp_free_i64(avr);
0304af89
BH		 486}
487
488static void gen_vmrgow(DisasContext *ctx)
489{
c4a18dbf
MCA		 490 TCGv_i64 t0, t1;
491 TCGv_i64 avr;
0304af89
BH		 492 int VT, VA, VB;
493 if (unlikely(!ctx->altivec_enabled)) {
494 gen_exception(ctx, POWERPC_EXCP_VPU);
495 return;
496 }
497 VT = rD(ctx->opcode);
498 VA = rA(ctx->opcode);
499 VB = rB(ctx->opcode);
c4a18dbf
MCA		 500 t0 = tcg_temp_new_i64();
501 t1 = tcg_temp_new_i64();
502 avr = tcg_temp_new_i64();
503
504 get_avr64(t0, VB, true);
505 get_avr64(t1, VA, true);
506 tcg_gen_deposit_i64(avr, t0, t1, 32, 32);
507 set_avr64(VT, avr, true);
508
509 get_avr64(t0, VB, false);
510 get_avr64(t1, VA, false);
511 tcg_gen_deposit_i64(avr, t0, t1, 32, 32);
512 set_avr64(VT, avr, false);
513
514 tcg_temp_free_i64(t0);
515 tcg_temp_free_i64(t1);
516 tcg_temp_free_i64(avr);
0304af89
BH		 517}
518
519GEN_VXFORM(vmuloub, 4, 0);
520GEN_VXFORM(vmulouh, 4, 1);
521GEN_VXFORM(vmulouw, 4, 2);
522GEN_VXFORM(vmuluwm, 4, 2);
523GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
524 vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
525GEN_VXFORM(vmulosb, 4, 4);
526GEN_VXFORM(vmulosh, 4, 5);
527GEN_VXFORM(vmulosw, 4, 6);
528GEN_VXFORM(vmuleub, 4, 8);
529GEN_VXFORM(vmuleuh, 4, 9);
530GEN_VXFORM(vmuleuw, 4, 10);
531GEN_VXFORM(vmulesb, 4, 12);
532GEN_VXFORM(vmulesh, 4, 13);
533GEN_VXFORM(vmulesw, 4, 14);
534GEN_VXFORM(vslb, 2, 4);
535GEN_VXFORM(vslh, 2, 5);
536GEN_VXFORM(vslw, 2, 6);
09a245e1
BR		 537GEN_VXFORM(vrlwnm, 2, 6);
538GEN_VXFORM_DUAL(vslw, PPC_ALTIVEC, PPC_NONE, \
539 vrlwnm, PPC_NONE, PPC2_ISA300)
0304af89
BH		 540GEN_VXFORM(vsld, 2, 23);
541GEN_VXFORM(vsrb, 2, 8);
542GEN_VXFORM(vsrh, 2, 9);
543GEN_VXFORM(vsrw, 2, 10);
544GEN_VXFORM(vsrd, 2, 27);
545GEN_VXFORM(vsrab, 2, 12);
546GEN_VXFORM(vsrah, 2, 13);
547GEN_VXFORM(vsraw, 2, 14);
548GEN_VXFORM(vsrad, 2, 15);
4004c1db 549GEN_VXFORM(vsrv, 2, 28);
5644a175 550GEN_VXFORM(vslv, 2, 29);
0304af89
BH		 551GEN_VXFORM(vslo, 6, 16);
552GEN_VXFORM(vsro, 6, 17);
553GEN_VXFORM(vaddcuw, 0, 6);
554GEN_VXFORM(vsubcuw, 0, 22);
fb11ae7d
RH		 555
556#define GEN_VXFORM_SAT(NAME, VECE, NORM, SAT, OPC2, OPC3) \
557static void glue(glue(gen_, NAME), _vec)(unsigned vece, TCGv_vec t, \
558 TCGv_vec sat, TCGv_vec a, \
559 TCGv_vec b) \
560{ \
561 TCGv_vec x = tcg_temp_new_vec_matching(t); \
562 glue(glue(tcg_gen_, NORM), _vec)(VECE, x, a, b); \
563 glue(glue(tcg_gen_, SAT), _vec)(VECE, t, a, b); \
564 tcg_gen_cmp_vec(TCG_COND_NE, VECE, x, x, t); \
565 tcg_gen_or_vec(VECE, sat, sat, x); \
566 tcg_temp_free_vec(x); \
567} \
568static void glue(gen_, NAME)(DisasContext *ctx) \
569{ \
570 static const GVecGen4 g = { \
571 .fniv = glue(glue(gen_, NAME), _vec), \
572 .fno = glue(gen_helper_, NAME), \
573 .opc = glue(glue(INDEX_op_, SAT), _vec), \
574 .write_aofs = true, \
575 .vece = VECE, \
576 }; \
577 if (unlikely(!ctx->altivec_enabled)) { \
578 gen_exception(ctx, POWERPC_EXCP_VPU); \
579 return; \
580 } \
581 tcg_gen_gvec_4(avr64_offset(rD(ctx->opcode), true), \
582 offsetof(CPUPPCState, vscr_sat), \
583 avr64_offset(rA(ctx->opcode), true), \
584 avr64_offset(rB(ctx->opcode), true), \
585 16, 16, &g); \
586}
587
588GEN_VXFORM_SAT(vaddubs, MO_8, add, usadd, 0, 8);
37ad52ba
VH		 589GEN_VXFORM_DUAL_EXT(vaddubs, PPC_ALTIVEC, PPC_NONE, 0, \
590 vmul10uq, PPC_NONE, PPC2_ISA300, 0x0000F800)
fb11ae7d 591GEN_VXFORM_SAT(vadduhs, MO_16, add, usadd, 0, 9);
37ad52ba
VH		 592GEN_VXFORM_DUAL(vadduhs, PPC_ALTIVEC, PPC_NONE, \
593 vmul10euq, PPC_NONE, PPC2_ISA300)
fb11ae7d
RH		 594GEN_VXFORM_SAT(vadduws, MO_32, add, usadd, 0, 10);
595GEN_VXFORM_SAT(vaddsbs, MO_8, add, ssadd, 0, 12);
596GEN_VXFORM_SAT(vaddshs, MO_16, add, ssadd, 0, 13);
597GEN_VXFORM_SAT(vaddsws, MO_32, add, ssadd, 0, 14);
598GEN_VXFORM_SAT(vsububs, MO_8, sub, ussub, 0, 24);
599GEN_VXFORM_SAT(vsubuhs, MO_16, sub, ussub, 0, 25);
600GEN_VXFORM_SAT(vsubuws, MO_32, sub, ussub, 0, 26);
601GEN_VXFORM_SAT(vsubsbs, MO_8, sub, sssub, 0, 28);
602GEN_VXFORM_SAT(vsubshs, MO_16, sub, sssub, 0, 29);
603GEN_VXFORM_SAT(vsubsws, MO_32, sub, sssub, 0, 30);
0304af89
BH		 604GEN_VXFORM(vadduqm, 0, 4);
605GEN_VXFORM(vaddcuq, 0, 5);
606GEN_VXFORM3(vaddeuqm, 30, 0);
607GEN_VXFORM3(vaddecuq, 30, 0);
608GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
609 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
610GEN_VXFORM(vsubuqm, 0, 20);
611GEN_VXFORM(vsubcuq, 0, 21);
612GEN_VXFORM3(vsubeuqm, 31, 0);
613GEN_VXFORM3(vsubecuq, 31, 0);
614GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
615 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
616GEN_VXFORM(vrlb, 2, 0);
617GEN_VXFORM(vrlh, 2, 1);
618GEN_VXFORM(vrlw, 2, 2);
3e00884f
GS		 619GEN_VXFORM(vrlwmi, 2, 2);
620GEN_VXFORM_DUAL(vrlw, PPC_ALTIVEC, PPC_NONE, \
621 vrlwmi, PPC_NONE, PPC2_ISA300)
0304af89 622GEN_VXFORM(vrld, 2, 3);
3e00884f
GS		 623GEN_VXFORM(vrldmi, 2, 3);
624GEN_VXFORM_DUAL(vrld, PPC_NONE, PPC2_ALTIVEC_207, \
625 vrldmi, PPC_NONE, PPC2_ISA300)
0304af89 626GEN_VXFORM(vsl, 2, 7);
09a245e1
BR		 627GEN_VXFORM(vrldnm, 2, 7);
628GEN_VXFORM_DUAL(vsl, PPC_ALTIVEC, PPC_NONE, \
629 vrldnm, PPC_NONE, PPC2_ISA300)
0304af89
BH		 630GEN_VXFORM(vsr, 2, 11);
631GEN_VXFORM_ENV(vpkuhum, 7, 0);
632GEN_VXFORM_ENV(vpkuwum, 7, 1);
633GEN_VXFORM_ENV(vpkudum, 7, 17);
634GEN_VXFORM_ENV(vpkuhus, 7, 2);
635GEN_VXFORM_ENV(vpkuwus, 7, 3);
636GEN_VXFORM_ENV(vpkudus, 7, 19);
637GEN_VXFORM_ENV(vpkshus, 7, 4);
638GEN_VXFORM_ENV(vpkswus, 7, 5);
639GEN_VXFORM_ENV(vpksdus, 7, 21);
640GEN_VXFORM_ENV(vpkshss, 7, 6);
641GEN_VXFORM_ENV(vpkswss, 7, 7);
642GEN_VXFORM_ENV(vpksdss, 7, 23);
643GEN_VXFORM(vpkpx, 7, 12);
644GEN_VXFORM_ENV(vsum4ubs, 4, 24);
645GEN_VXFORM_ENV(vsum4sbs, 4, 28);
646GEN_VXFORM_ENV(vsum4shs, 4, 25);
647GEN_VXFORM_ENV(vsum2sws, 4, 26);
648GEN_VXFORM_ENV(vsumsws, 4, 30);
649GEN_VXFORM_ENV(vaddfp, 5, 0);
650GEN_VXFORM_ENV(vsubfp, 5, 1);
651GEN_VXFORM_ENV(vmaxfp, 5, 16);
652GEN_VXFORM_ENV(vminfp, 5, 17);
60caf221
AK		 653GEN_VXFORM_HETRO(vextublx, 6, 24)
654GEN_VXFORM_HETRO(vextuhlx, 6, 25)
655GEN_VXFORM_HETRO(vextuwlx, 6, 26)
656GEN_VXFORM_DUAL(vmrgow, PPC_NONE, PPC2_ALTIVEC_207,
657 vextuwlx, PPC_NONE, PPC2_ISA300)
658GEN_VXFORM_HETRO(vextubrx, 6, 28)
659GEN_VXFORM_HETRO(vextuhrx, 6, 29)
660GEN_VXFORM_HETRO(vextuwrx, 6, 30)
661GEN_VXFORM_DUAL(vmrgew, PPC_NONE, PPC2_ALTIVEC_207, \
662 vextuwrx, PPC_NONE, PPC2_ISA300)
0304af89
BH		 663
664#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
665static void glue(gen_, name)(DisasContext *ctx) \
666 { \
667 TCGv_ptr ra, rb, rd; \
668 if (unlikely(!ctx->altivec_enabled)) { \
669 gen_exception(ctx, POWERPC_EXCP_VPU); \
670 return; \
671 } \
672 ra = gen_avr_ptr(rA(ctx->opcode)); \
673 rb = gen_avr_ptr(rB(ctx->opcode)); \
674 rd = gen_avr_ptr(rD(ctx->opcode)); \
675 gen_helper_##opname(cpu_env, rd, ra, rb); \
676 tcg_temp_free_ptr(ra); \
677 tcg_temp_free_ptr(rb); \
678 tcg_temp_free_ptr(rd); \
679 }
680
681#define GEN_VXRFORM(name, opc2, opc3) \
682 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
683 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
684
685/*
686 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
687 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
688 * come from different versions of the ISA, so we must also support a
689 * pair of flags for each instruction.
690 */
691#define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
692static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
693{ \
694 if ((Rc(ctx->opcode) == 0) && \
695 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
696 if (Rc21(ctx->opcode) == 0) { \
697 gen_##name0(ctx); \
698 } else { \
699 gen_##name0##_(ctx); \
700 } \
701 } else if ((Rc(ctx->opcode) == 1) && \
702 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
703 if (Rc21(ctx->opcode) == 0) { \
704 gen_##name1(ctx); \
705 } else { \
706 gen_##name1##_(ctx); \
707 } \
708 } else { \
709 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
710 } \
711}
712
713GEN_VXRFORM(vcmpequb, 3, 0)
714GEN_VXRFORM(vcmpequh, 3, 1)
715GEN_VXRFORM(vcmpequw, 3, 2)
716GEN_VXRFORM(vcmpequd, 3, 3)
f7cc8466
SB		 717GEN_VXRFORM(vcmpnezb, 3, 4)
718GEN_VXRFORM(vcmpnezh, 3, 5)
719GEN_VXRFORM(vcmpnezw, 3, 6)
0304af89
BH		 720GEN_VXRFORM(vcmpgtsb, 3, 12)
721GEN_VXRFORM(vcmpgtsh, 3, 13)
722GEN_VXRFORM(vcmpgtsw, 3, 14)
723GEN_VXRFORM(vcmpgtsd, 3, 15)
724GEN_VXRFORM(vcmpgtub, 3, 8)
725GEN_VXRFORM(vcmpgtuh, 3, 9)
726GEN_VXRFORM(vcmpgtuw, 3, 10)
727GEN_VXRFORM(vcmpgtud, 3, 11)
728GEN_VXRFORM(vcmpeqfp, 3, 3)
729GEN_VXRFORM(vcmpgefp, 3, 7)
730GEN_VXRFORM(vcmpgtfp, 3, 11)
731GEN_VXRFORM(vcmpbfp, 3, 15)
0fa59364
RS		 732GEN_VXRFORM(vcmpneb, 3, 0)
733GEN_VXRFORM(vcmpneh, 3, 1)
734GEN_VXRFORM(vcmpnew, 3, 2)
0304af89 735
2020b67d 736GEN_VXRFORM_DUAL(vcmpequb, PPC_ALTIVEC, PPC_NONE, \
0fa59364 737 vcmpneb, PPC_NONE, PPC2_ISA300)
2020b67d 738GEN_VXRFORM_DUAL(vcmpequh, PPC_ALTIVEC, PPC_NONE, \
0fa59364 739 vcmpneh, PPC_NONE, PPC2_ISA300)
2020b67d 740GEN_VXRFORM_DUAL(vcmpequw, PPC_ALTIVEC, PPC_NONE, \
0fa59364 741 vcmpnew, PPC_NONE, PPC2_ISA300)
0304af89
BH		 742GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
743 vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
744GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
745 vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
746GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
747 vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
748
471ff3d0 749#define GEN_VXFORM_DUPI(name, tcg_op, opc2, opc3) \
0304af89
BH		 750static void glue(gen_, name)(DisasContext *ctx) \
751 { \
471ff3d0 752 int simm; \
0304af89
BH		 753 if (unlikely(!ctx->altivec_enabled)) { \
754 gen_exception(ctx, POWERPC_EXCP_VPU); \
755 return; \
756 } \
471ff3d0
RH		 757 simm = SIMM5(ctx->opcode); \
758 tcg_op(avr64_offset(rD(ctx->opcode), true), 16, 16, simm); \
0304af89
BH		 759 }
760
471ff3d0
RH		 761GEN_VXFORM_DUPI(vspltisb, tcg_gen_gvec_dup8i, 6, 12);
762GEN_VXFORM_DUPI(vspltish, tcg_gen_gvec_dup16i, 6, 13);
763GEN_VXFORM_DUPI(vspltisw, tcg_gen_gvec_dup32i, 6, 14);
0304af89
BH		 764
765#define GEN_VXFORM_NOA(name, opc2, opc3) \
766static void glue(gen_, name)(DisasContext *ctx) \
767 { \
768 TCGv_ptr rb, rd; \
769 if (unlikely(!ctx->altivec_enabled)) { \
770 gen_exception(ctx, POWERPC_EXCP_VPU); \
771 return; \
772 } \
773 rb = gen_avr_ptr(rB(ctx->opcode)); \
774 rd = gen_avr_ptr(rD(ctx->opcode)); \
775 gen_helper_##name (rd, rb); \
776 tcg_temp_free_ptr(rb); \
777 tcg_temp_free_ptr(rd); \
778 }
779
780#define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
781static void glue(gen_, name)(DisasContext *ctx) \
782 { \
783 TCGv_ptr rb, rd; \
784 \
785 if (unlikely(!ctx->altivec_enabled)) { \
786 gen_exception(ctx, POWERPC_EXCP_VPU); \
787 return; \
788 } \
789 rb = gen_avr_ptr(rB(ctx->opcode)); \
790 rd = gen_avr_ptr(rD(ctx->opcode)); \
791 gen_helper_##name(cpu_env, rd, rb); \
792 tcg_temp_free_ptr(rb); \
793 tcg_temp_free_ptr(rd); \
794 }
795
a5ad8fbf
RS		 796#define GEN_VXFORM_NOA_2(name, opc2, opc3, opc4) \
797static void glue(gen_, name)(DisasContext *ctx) \
798 { \
799 TCGv_ptr rb, rd; \
800 if (unlikely(!ctx->altivec_enabled)) { \
801 gen_exception(ctx, POWERPC_EXCP_VPU); \
802 return; \
803 } \
804 rb = gen_avr_ptr(rB(ctx->opcode)); \
805 rd = gen_avr_ptr(rD(ctx->opcode)); \
806 gen_helper_##name(rd, rb); \
807 tcg_temp_free_ptr(rb); \
808 tcg_temp_free_ptr(rd); \
809 }
810
4879538c
RS		 811#define GEN_VXFORM_NOA_3(name, opc2, opc3, opc4) \
812static void glue(gen_, name)(DisasContext *ctx) \
813 { \
814 TCGv_ptr rb; \
815 if (unlikely(!ctx->altivec_enabled)) { \
816 gen_exception(ctx, POWERPC_EXCP_VPU); \
817 return; \
818 } \
819 rb = gen_avr_ptr(rB(ctx->opcode)); \
820 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], rb); \
821 tcg_temp_free_ptr(rb); \
822 }
0304af89
BH		 823GEN_VXFORM_NOA(vupkhsb, 7, 8);
824GEN_VXFORM_NOA(vupkhsh, 7, 9);
825GEN_VXFORM_NOA(vupkhsw, 7, 25);
826GEN_VXFORM_NOA(vupklsb, 7, 10);
827GEN_VXFORM_NOA(vupklsh, 7, 11);
828GEN_VXFORM_NOA(vupklsw, 7, 27);
829GEN_VXFORM_NOA(vupkhpx, 7, 13);
830GEN_VXFORM_NOA(vupklpx, 7, 15);
831GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
832GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
833GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
834GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
835GEN_VXFORM_NOA_ENV(vrfim, 5, 11);
836GEN_VXFORM_NOA_ENV(vrfin, 5, 8);
837GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
838GEN_VXFORM_NOA_ENV(vrfiz, 5, 9);
5c69452c
AK		 839GEN_VXFORM_NOA(vprtybw, 1, 24);
840GEN_VXFORM_NOA(vprtybd, 1, 24);
841GEN_VXFORM_NOA(vprtybq, 1, 24);
0304af89 842
0f6a6d5d
RH		 843static void gen_vsplt(DisasContext *ctx, int vece)
844{
845 int uimm, dofs, bofs;
846
847 if (unlikely(!ctx->altivec_enabled)) {
848 gen_exception(ctx, POWERPC_EXCP_VPU);
849 return;
0304af89
BH		 850 }
851
0f6a6d5d
RH		 852 uimm = UIMM5(ctx->opcode);
853 bofs = avr64_offset(rB(ctx->opcode), true);
854 dofs = avr64_offset(rD(ctx->opcode), true);
855
856 /* Experimental testing shows that hardware masks the immediate. */
857 bofs += (uimm << vece) & 15;
858#ifndef HOST_WORDS_BIGENDIAN
859 bofs ^= 15;
860 bofs &= ~((1 << vece) - 1);
861#endif
862
863 tcg_gen_gvec_dup_mem(vece, dofs, bofs, 16, 16);
864}
865
866#define GEN_VXFORM_VSPLT(name, vece, opc2, opc3) \
867static void glue(gen_, name)(DisasContext *ctx) { gen_vsplt(ctx, vece); }
868
0304af89
BH		 869#define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
870static void glue(gen_, name)(DisasContext *ctx) \
871 { \
872 TCGv_ptr rb, rd; \
873 TCGv_i32 uimm; \
874 \
875 if (unlikely(!ctx->altivec_enabled)) { \
876 gen_exception(ctx, POWERPC_EXCP_VPU); \
877 return; \
878 } \
879 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
880 rb = gen_avr_ptr(rB(ctx->opcode)); \
881 rd = gen_avr_ptr(rD(ctx->opcode)); \
882 gen_helper_##name(cpu_env, rd, rb, uimm); \
883 tcg_temp_free_i32(uimm); \
884 tcg_temp_free_ptr(rb); \
885 tcg_temp_free_ptr(rd); \
886 }
887
e7b1e06f
RS		 888#define GEN_VXFORM_UIMM_SPLAT(name, opc2, opc3, splat_max) \
889static void glue(gen_, name)(DisasContext *ctx) \
890 { \
891 TCGv_ptr rb, rd; \
892 uint8_t uimm = UIMM4(ctx->opcode); \
c4a18dbf 893 TCGv_i32 t0; \
e7b1e06f
RS		 894 if (unlikely(!ctx->altivec_enabled)) { \
895 gen_exception(ctx, POWERPC_EXCP_VPU); \
896 return; \
897 } \
898 if (uimm > splat_max) { \
899 uimm = 0; \
900 } \
c4a18dbf 901 t0 = tcg_temp_new_i32(); \
e7b1e06f
RS		 902 tcg_gen_movi_i32(t0, uimm); \
903 rb = gen_avr_ptr(rB(ctx->opcode)); \
904 rd = gen_avr_ptr(rD(ctx->opcode)); \
905 gen_helper_##name(rd, rb, t0); \
906 tcg_temp_free_i32(t0); \
907 tcg_temp_free_ptr(rb); \
908 tcg_temp_free_ptr(rd); \
909 }
910
0f6a6d5d
RH		 911GEN_VXFORM_VSPLT(vspltb, MO_8, 6, 8);
912GEN_VXFORM_VSPLT(vsplth, MO_16, 6, 9);
913GEN_VXFORM_VSPLT(vspltw, MO_32, 6, 10);
b5d569a1
RS		 914GEN_VXFORM_UIMM_SPLAT(vextractub, 6, 8, 15);
915GEN_VXFORM_UIMM_SPLAT(vextractuh, 6, 9, 14);
916GEN_VXFORM_UIMM_SPLAT(vextractuw, 6, 10, 12);
917GEN_VXFORM_UIMM_SPLAT(vextractd, 6, 11, 8);
e7b1e06f
RS		 918GEN_VXFORM_UIMM_SPLAT(vinsertb, 6, 12, 15);
919GEN_VXFORM_UIMM_SPLAT(vinserth, 6, 13, 14);
920GEN_VXFORM_UIMM_SPLAT(vinsertw, 6, 14, 12);
921GEN_VXFORM_UIMM_SPLAT(vinsertd, 6, 15, 8);
0304af89
BH		 922GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
923GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
924GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
925GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
2020b67d
ND		 926GEN_VXFORM_DUAL(vspltb, PPC_ALTIVEC, PPC_NONE,
927 vextractub, PPC_NONE, PPC2_ISA300);
928GEN_VXFORM_DUAL(vsplth, PPC_ALTIVEC, PPC_NONE,
929 vextractuh, PPC_NONE, PPC2_ISA300);
930GEN_VXFORM_DUAL(vspltw, PPC_ALTIVEC, PPC_NONE,
931 vextractuw, PPC_NONE, PPC2_ISA300);
932GEN_VXFORM_DUAL(vspltisb, PPC_ALTIVEC, PPC_NONE,
933 vinsertb, PPC_NONE, PPC2_ISA300);
934GEN_VXFORM_DUAL(vspltish, PPC_ALTIVEC, PPC_NONE,
935 vinserth, PPC_NONE, PPC2_ISA300);
936GEN_VXFORM_DUAL(vspltisw, PPC_ALTIVEC, PPC_NONE,
937 vinsertw, PPC_NONE, PPC2_ISA300);
0304af89
BH		 938
939static void gen_vsldoi(DisasContext *ctx)
940{
941 TCGv_ptr ra, rb, rd;
942 TCGv_i32 sh;
943 if (unlikely(!ctx->altivec_enabled)) {
944 gen_exception(ctx, POWERPC_EXCP_VPU);
945 return;
946 }
947 ra = gen_avr_ptr(rA(ctx->opcode));
948 rb = gen_avr_ptr(rB(ctx->opcode));
949 rd = gen_avr_ptr(rD(ctx->opcode));
950 sh = tcg_const_i32(VSH(ctx->opcode));
951 gen_helper_vsldoi (rd, ra, rb, sh);
952 tcg_temp_free_ptr(ra);
953 tcg_temp_free_ptr(rb);
954 tcg_temp_free_ptr(rd);
955 tcg_temp_free_i32(sh);
956}
957
958#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
959static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
960 { \
961 TCGv_ptr ra, rb, rc, rd; \
962 if (unlikely(!ctx->altivec_enabled)) { \
963 gen_exception(ctx, POWERPC_EXCP_VPU); \
964 return; \
965 } \
966 ra = gen_avr_ptr(rA(ctx->opcode)); \
967 rb = gen_avr_ptr(rB(ctx->opcode)); \
968 rc = gen_avr_ptr(rC(ctx->opcode)); \
969 rd = gen_avr_ptr(rD(ctx->opcode)); \
970 if (Rc(ctx->opcode)) { \
971 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
972 } else { \
973 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
974 } \
975 tcg_temp_free_ptr(ra); \
976 tcg_temp_free_ptr(rb); \
977 tcg_temp_free_ptr(rc); \
978 tcg_temp_free_ptr(rd); \
979 }
980
981GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
982
983static void gen_vmladduhm(DisasContext *ctx)
984{
985 TCGv_ptr ra, rb, rc, rd;
986 if (unlikely(!ctx->altivec_enabled)) {
987 gen_exception(ctx, POWERPC_EXCP_VPU);
988 return;
989 }
990 ra = gen_avr_ptr(rA(ctx->opcode));
991 rb = gen_avr_ptr(rB(ctx->opcode));
992 rc = gen_avr_ptr(rC(ctx->opcode));
993 rd = gen_avr_ptr(rD(ctx->opcode));
994 gen_helper_vmladduhm(rd, ra, rb, rc);
995 tcg_temp_free_ptr(ra);
996 tcg_temp_free_ptr(rb);
997 tcg_temp_free_ptr(rc);
998 tcg_temp_free_ptr(rd);
999}
1000
ab045436
RS		 1001static void gen_vpermr(DisasContext *ctx)
1002{
1003 TCGv_ptr ra, rb, rc, rd;
1004 if (unlikely(!ctx->altivec_enabled)) {
1005 gen_exception(ctx, POWERPC_EXCP_VPU);
1006 return;
1007 }
1008 ra = gen_avr_ptr(rA(ctx->opcode));
1009 rb = gen_avr_ptr(rB(ctx->opcode));
1010 rc = gen_avr_ptr(rC(ctx->opcode));
1011 rd = gen_avr_ptr(rD(ctx->opcode));
1012 gen_helper_vpermr(cpu_env, rd, ra, rb, rc);
1013 tcg_temp_free_ptr(ra);
1014 tcg_temp_free_ptr(rb);
1015 tcg_temp_free_ptr(rc);
1016 tcg_temp_free_ptr(rd);
1017}
1018
0304af89
BH		 1019GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
1020GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
1021GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
1022GEN_VAFORM_PAIRED(vsel, vperm, 21)
1023GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
1024
1025GEN_VXFORM_NOA(vclzb, 1, 28)
1026GEN_VXFORM_NOA(vclzh, 1, 29)
1027GEN_VXFORM_NOA(vclzw, 1, 30)
1028GEN_VXFORM_NOA(vclzd, 1, 31)
cc8b6e76
ND		 1029GEN_VXFORM_NOA_2(vnegw, 1, 24, 6)
1030GEN_VXFORM_NOA_2(vnegd, 1, 24, 7)
125a9b23
ND		 1031GEN_VXFORM_NOA_2(vextsb2w, 1, 24, 16)
1032GEN_VXFORM_NOA_2(vextsh2w, 1, 24, 17)
1033GEN_VXFORM_NOA_2(vextsb2d, 1, 24, 24)
1034GEN_VXFORM_NOA_2(vextsh2d, 1, 24, 25)
1035GEN_VXFORM_NOA_2(vextsw2d, 1, 24, 26)
a5ad8fbf
RS		 1036GEN_VXFORM_NOA_2(vctzb, 1, 24, 28)
1037GEN_VXFORM_NOA_2(vctzh, 1, 24, 29)
1038GEN_VXFORM_NOA_2(vctzw, 1, 24, 30)
1039GEN_VXFORM_NOA_2(vctzd, 1, 24, 31)
4879538c
RS		 1040GEN_VXFORM_NOA_3(vclzlsbb, 1, 24, 0)
1041GEN_VXFORM_NOA_3(vctzlsbb, 1, 24, 1)
0304af89
BH		 1042GEN_VXFORM_NOA(vpopcntb, 1, 28)
1043GEN_VXFORM_NOA(vpopcnth, 1, 29)
1044GEN_VXFORM_NOA(vpopcntw, 1, 30)
1045GEN_VXFORM_NOA(vpopcntd, 1, 31)
1046GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
1047 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
1048GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
1049 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
1050GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
1051 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
1052GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
1053 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
01fe9a47 1054GEN_VXFORM(vbpermd, 6, 23);
0304af89
BH		 1055GEN_VXFORM(vbpermq, 6, 21);
1056GEN_VXFORM_NOA(vgbbd, 6, 20);
1057GEN_VXFORM(vpmsumb, 4, 16)
1058GEN_VXFORM(vpmsumh, 4, 17)
1059GEN_VXFORM(vpmsumw, 4, 18)
1060GEN_VXFORM(vpmsumd, 4, 19)
1061
1062#define GEN_BCD(op) \
1063static void gen_##op(DisasContext *ctx) \
1064{ \
1065 TCGv_ptr ra, rb, rd; \
1066 TCGv_i32 ps; \
1067 \
1068 if (unlikely(!ctx->altivec_enabled)) { \
1069 gen_exception(ctx, POWERPC_EXCP_VPU); \
1070 return; \
1071 } \
1072 \
1073 ra = gen_avr_ptr(rA(ctx->opcode)); \
1074 rb = gen_avr_ptr(rB(ctx->opcode)); \
1075 rd = gen_avr_ptr(rD(ctx->opcode)); \
1076 \
1077 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
1078 \
1079 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
1080 \
1081 tcg_temp_free_ptr(ra); \
1082 tcg_temp_free_ptr(rb); \
1083 tcg_temp_free_ptr(rd); \
1084 tcg_temp_free_i32(ps); \
1085}
1086
b8155872
JRZ		 1087#define GEN_BCD2(op) \
1088static void gen_##op(DisasContext *ctx) \
1089{ \
1090 TCGv_ptr rd, rb; \
1091 TCGv_i32 ps; \
1092 \
1093 if (unlikely(!ctx->altivec_enabled)) { \
1094 gen_exception(ctx, POWERPC_EXCP_VPU); \
1095 return; \
1096 } \
1097 \
1098 rb = gen_avr_ptr(rB(ctx->opcode)); \
1099 rd = gen_avr_ptr(rD(ctx->opcode)); \
1100 \
1101 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
1102 \
1103 gen_helper_##op(cpu_crf[6], rd, rb, ps); \
1104 \
1105 tcg_temp_free_ptr(rb); \
1106 tcg_temp_free_ptr(rd); \
1107 tcg_temp_free_i32(ps); \
1108}
1109
0304af89
BH		 1110GEN_BCD(bcdadd)
1111GEN_BCD(bcdsub)
b8155872 1112GEN_BCD2(bcdcfn)
e2106d73 1113GEN_BCD2(bcdctn)
38f4cb04 1114GEN_BCD2(bcdcfz)
0a890b31 1115GEN_BCD2(bcdctz)
a406c058 1116GEN_BCD2(bcdcfsq)
c85bc7dd 1117GEN_BCD2(bcdctsq)
466a3f9c 1118GEN_BCD2(bcdsetsgn)
c3025c3b 1119GEN_BCD(bcdcpsgn);
e04797f7 1120GEN_BCD(bcds);
a49a95e9 1121GEN_BCD(bcdus);
a54238ad 1122GEN_BCD(bcdsr);
31bc4d11 1123GEN_BCD(bcdtrunc);
5c32e2e4 1124GEN_BCD(bcdutrunc);
b8155872
JRZ		 1125
1126static void gen_xpnd04_1(DisasContext *ctx)
1127{
1128 switch (opc4(ctx->opcode)) {
c85bc7dd
JRZ		 1129 case 0:
1130 gen_bcdctsq(ctx);
1131 break;
a406c058
JRZ		 1132 case 2:
1133 gen_bcdcfsq(ctx);
1134 break;
0a890b31
JRZ		 1135 case 4:
1136 gen_bcdctz(ctx);
1137 break;
e2106d73
JRZ		 1138 case 5:
1139 gen_bcdctn(ctx);
1140 break;
38f4cb04
JRZ		 1141 case 6:
1142 gen_bcdcfz(ctx);
1143 break;
b8155872
JRZ		 1144 case 7:
1145 gen_bcdcfn(ctx);
1146 break;
466a3f9c
JRZ		 1147 case 31:
1148 gen_bcdsetsgn(ctx);
1149 break;
b8155872
JRZ		 1150 default:
1151 gen_invalid(ctx);
1152 break;
1153 }
1154}
1155
1156static void gen_xpnd04_2(DisasContext *ctx)
1157{
1158 switch (opc4(ctx->opcode)) {
c85bc7dd
JRZ		 1159 case 0:
1160 gen_bcdctsq(ctx);
1161 break;
a406c058
JRZ		 1162 case 2:
1163 gen_bcdcfsq(ctx);
1164 break;
0a890b31
JRZ		 1165 case 4:
1166 gen_bcdctz(ctx);
1167 break;
38f4cb04
JRZ		 1168 case 6:
1169 gen_bcdcfz(ctx);
1170 break;
b8155872
JRZ		 1171 case 7:
1172 gen_bcdcfn(ctx);
1173 break;
466a3f9c
JRZ		 1174 case 31:
1175 gen_bcdsetsgn(ctx);
1176 break;
b8155872
JRZ		 1177 default:
1178 gen_invalid(ctx);
1179 break;
1180 }
1181}
1182
466a3f9c 1183
b8155872
JRZ		 1184GEN_VXFORM_DUAL(vsubcuw, PPC_ALTIVEC, PPC_NONE, \
1185 xpnd04_1, PPC_NONE, PPC2_ISA300)
1186GEN_VXFORM_DUAL(vsubsws, PPC_ALTIVEC, PPC_NONE, \
1187 xpnd04_2, PPC_NONE, PPC2_ISA300)
0304af89
BH		 1188
1189GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
1190 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
1191GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
1192 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
1193GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
1194 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
1195GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
1196 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
c3025c3b
JRZ		 1197GEN_VXFORM_DUAL(vaddshs, PPC_ALTIVEC, PPC_NONE, \
1198 bcdcpsgn, PPC_NONE, PPC2_ISA300)
e04797f7
JRZ		 1199GEN_VXFORM_DUAL(vsubudm, PPC2_ALTIVEC_207, PPC_NONE, \
1200 bcds, PPC_NONE, PPC2_ISA300)
a49a95e9
JRZ		 1201GEN_VXFORM_DUAL(vsubuwm, PPC_ALTIVEC, PPC_NONE, \
1202 bcdus, PPC_NONE, PPC2_ISA300)
31bc4d11
JRZ		 1203GEN_VXFORM_DUAL(vsubsbs, PPC_ALTIVEC, PPC_NONE, \
1204 bcdtrunc, PPC_NONE, PPC2_ISA300)
1205GEN_VXFORM_DUAL(vsubuqm, PPC2_ALTIVEC_207, PPC_NONE, \
1206 bcdtrunc, PPC_NONE, PPC2_ISA300)
5c32e2e4
JRZ		 1207GEN_VXFORM_DUAL(vsubcuq, PPC2_ALTIVEC_207, PPC_NONE, \
1208 bcdutrunc, PPC_NONE, PPC2_ISA300)
1209
0304af89
BH		 1210
1211static void gen_vsbox(DisasContext *ctx)
1212{
1213 TCGv_ptr ra, rd;
1214 if (unlikely(!ctx->altivec_enabled)) {
1215 gen_exception(ctx, POWERPC_EXCP_VPU);
1216 return;
1217 }
1218 ra = gen_avr_ptr(rA(ctx->opcode));
1219 rd = gen_avr_ptr(rD(ctx->opcode));
1220 gen_helper_vsbox(rd, ra);
1221 tcg_temp_free_ptr(ra);
1222 tcg_temp_free_ptr(rd);
1223}
1224
1225GEN_VXFORM(vcipher, 4, 20)
1226GEN_VXFORM(vcipherlast, 4, 20)
1227GEN_VXFORM(vncipher, 4, 21)
1228GEN_VXFORM(vncipherlast, 4, 21)
1229
1230GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
1231 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
1232GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
1233 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
1234
1235#define VSHASIGMA(op) \
1236static void gen_##op(DisasContext *ctx) \
1237{ \
1238 TCGv_ptr ra, rd; \
1239 TCGv_i32 st_six; \
1240 if (unlikely(!ctx->altivec_enabled)) { \
1241 gen_exception(ctx, POWERPC_EXCP_VPU); \
1242 return; \
1243 } \
1244 ra = gen_avr_ptr(rA(ctx->opcode)); \
1245 rd = gen_avr_ptr(rD(ctx->opcode)); \
1246 st_six = tcg_const_i32(rB(ctx->opcode)); \
1247 gen_helper_##op(rd, ra, st_six); \
1248 tcg_temp_free_ptr(ra); \
1249 tcg_temp_free_ptr(rd); \
1250 tcg_temp_free_i32(st_six); \
1251}
1252
1253VSHASIGMA(vshasigmaw)
1254VSHASIGMA(vshasigmad)
1255
1256GEN_VXFORM3(vpermxor, 22, 0xFF)
1257GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
1258 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
1259
1260#undef GEN_VR_LDX
1261#undef GEN_VR_STX
1262#undef GEN_VR_LVE
1263#undef GEN_VR_STVE
1264
1265#undef GEN_VX_LOGICAL
1266#undef GEN_VX_LOGICAL_207
1267#undef GEN_VXFORM
1268#undef GEN_VXFORM_207
1269#undef GEN_VXFORM_DUAL
1270#undef GEN_VXRFORM_DUAL
1271#undef GEN_VXRFORM1
1272#undef GEN_VXRFORM
471ff3d0 1273#undef GEN_VXFORM_DUPI
0304af89
BH		 1274#undef GEN_VXFORM_NOA
1275#undef GEN_VXFORM_UIMM
1276#undef GEN_VAFORM_PAIRED
b8155872
JRZ		 1277
1278#undef GEN_BCD2
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