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Commit | Line | Data |
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79aceca5 | 1 | /* |
3fc6c082 | 2 | * PowerPC emulation for qemu: main translation routines. |
5fafdf24 | 3 | * |
76a66253 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
90dc8812 | 5 | * Copyright (C) 2011 Freescale Semiconductor, Inc. |
79aceca5 FB |
6 | * |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
6bd039cd | 10 | * version 2.1 of the License, or (at your option) any later version. |
79aceca5 FB |
11 | * |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
79aceca5 | 19 | */ |
c6a1c22b | 20 | |
0d75590d | 21 | #include "qemu/osdep.h" |
79aceca5 | 22 | #include "cpu.h" |
3e00884f | 23 | #include "internal.h" |
76cad711 | 24 | #include "disas/disas.h" |
63c91552 | 25 | #include "exec/exec-all.h" |
dcb32f1d PMD |
26 | #include "tcg/tcg-op.h" |
27 | #include "tcg/tcg-op-gvec.h" | |
1de7afc9 | 28 | #include "qemu/host-utils.h" |
db725815 | 29 | #include "qemu/main-loop.h" |
f08b6170 | 30 | #include "exec/cpu_ldst.h" |
79aceca5 | 31 | |
2ef6175a RH |
32 | #include "exec/helper-proto.h" |
33 | #include "exec/helper-gen.h" | |
a7812ae4 | 34 | |
b6bac4bc | 35 | #include "exec/translator.h" |
508127e2 | 36 | #include "exec/log.h" |
f34ec0f6 | 37 | #include "qemu/atomic128.h" |
99e964ef | 38 | #include "spr_common.h" |
eeaaefe9 | 39 | #include "power8-pmu.h" |
a7e30d84 | 40 | |
3e770bf7 BL |
41 | #include "qemu/qemu-print.h" |
42 | #include "qapi/error.h" | |
a7e30d84 | 43 | |
d53106c9 RH |
44 | #define HELPER_H "helper.h" |
45 | #include "exec/helper-info.c.inc" | |
46 | #undef HELPER_H | |
47 | ||
8cbcb4fa AJ |
48 | #define CPU_SINGLE_STEP 0x1 |
49 | #define CPU_BRANCH_STEP 0x2 | |
8cbcb4fa | 50 | |
a750fc0b | 51 | /* Include definitions for instructions classes and implementations flags */ |
efe843d8 | 52 | /* #define PPC_DEBUG_DISAS */ |
79aceca5 | 53 | |
d12d51d5 | 54 | #ifdef PPC_DEBUG_DISAS |
93fcfe39 | 55 | # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) |
d12d51d5 AL |
56 | #else |
57 | # define LOG_DISAS(...) do { } while (0) | |
58 | #endif | |
a750fc0b JM |
59 | /*****************************************************************************/ |
60 | /* Code translation helpers */ | |
c53be334 | 61 | |
f78fb44e | 62 | /* global register indexes */ |
efe843d8 DG |
63 | static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ |
64 | + 10 * 4 + 22 * 5 /* SPE GPRh */ | |
65 | + 8 * 5 /* CRF */]; | |
f78fb44e | 66 | static TCGv cpu_gpr[32]; |
f78fb44e | 67 | static TCGv cpu_gprh[32]; |
a7812ae4 | 68 | static TCGv_i32 cpu_crf[8]; |
bd568f18 | 69 | static TCGv cpu_nip; |
6527f6ea | 70 | static TCGv cpu_msr; |
cfdcd37a AJ |
71 | static TCGv cpu_ctr; |
72 | static TCGv cpu_lr; | |
697ab892 DG |
73 | #if defined(TARGET_PPC64) |
74 | static TCGv cpu_cfar; | |
75 | #endif | |
dd09c361 | 76 | static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; |
cf360a32 | 77 | static TCGv cpu_reserve; |
392d328a | 78 | static TCGv cpu_reserve_length; |
253ce7b2 | 79 | static TCGv cpu_reserve_val; |
894448ae | 80 | static TCGv cpu_reserve_val2; |
30304420 | 81 | static TCGv cpu_fpscr; |
a7859e89 | 82 | static TCGv_i32 cpu_access_type; |
f78fb44e | 83 | |
2e70f6ef PB |
84 | void ppc_translate_init(void) |
85 | { | |
f78fb44e | 86 | int i; |
efe843d8 | 87 | char *p; |
2dc766da | 88 | size_t cpu_reg_names_size; |
f78fb44e | 89 | |
f78fb44e | 90 | p = cpu_reg_names; |
2dc766da | 91 | cpu_reg_names_size = sizeof(cpu_reg_names); |
47e4661c AJ |
92 | |
93 | for (i = 0; i < 8; i++) { | |
2dc766da | 94 | snprintf(p, cpu_reg_names_size, "crf%d", i); |
e1ccc054 | 95 | cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, |
1328c2bf | 96 | offsetof(CPUPPCState, crf[i]), p); |
47e4661c | 97 | p += 5; |
2dc766da | 98 | cpu_reg_names_size -= 5; |
47e4661c AJ |
99 | } |
100 | ||
f78fb44e | 101 | for (i = 0; i < 32; i++) { |
2dc766da | 102 | snprintf(p, cpu_reg_names_size, "r%d", i); |
e1ccc054 | 103 | cpu_gpr[i] = tcg_global_mem_new(cpu_env, |
1328c2bf | 104 | offsetof(CPUPPCState, gpr[i]), p); |
f78fb44e | 105 | p += (i < 10) ? 3 : 4; |
2dc766da | 106 | cpu_reg_names_size -= (i < 10) ? 3 : 4; |
2dc766da | 107 | snprintf(p, cpu_reg_names_size, "r%dH", i); |
e1ccc054 | 108 | cpu_gprh[i] = tcg_global_mem_new(cpu_env, |
13b6a455 | 109 | offsetof(CPUPPCState, gprh[i]), p); |
f78fb44e | 110 | p += (i < 10) ? 4 : 5; |
2dc766da | 111 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
f78fb44e | 112 | } |
f10dc08e | 113 | |
e1ccc054 | 114 | cpu_nip = tcg_global_mem_new(cpu_env, |
1328c2bf | 115 | offsetof(CPUPPCState, nip), "nip"); |
bd568f18 | 116 | |
e1ccc054 | 117 | cpu_msr = tcg_global_mem_new(cpu_env, |
1328c2bf | 118 | offsetof(CPUPPCState, msr), "msr"); |
6527f6ea | 119 | |
e1ccc054 | 120 | cpu_ctr = tcg_global_mem_new(cpu_env, |
1328c2bf | 121 | offsetof(CPUPPCState, ctr), "ctr"); |
cfdcd37a | 122 | |
e1ccc054 | 123 | cpu_lr = tcg_global_mem_new(cpu_env, |
1328c2bf | 124 | offsetof(CPUPPCState, lr), "lr"); |
cfdcd37a | 125 | |
697ab892 | 126 | #if defined(TARGET_PPC64) |
e1ccc054 | 127 | cpu_cfar = tcg_global_mem_new(cpu_env, |
1328c2bf | 128 | offsetof(CPUPPCState, cfar), "cfar"); |
697ab892 DG |
129 | #endif |
130 | ||
e1ccc054 | 131 | cpu_xer = tcg_global_mem_new(cpu_env, |
1328c2bf | 132 | offsetof(CPUPPCState, xer), "xer"); |
e1ccc054 | 133 | cpu_so = tcg_global_mem_new(cpu_env, |
da91a00f | 134 | offsetof(CPUPPCState, so), "SO"); |
e1ccc054 | 135 | cpu_ov = tcg_global_mem_new(cpu_env, |
da91a00f | 136 | offsetof(CPUPPCState, ov), "OV"); |
e1ccc054 | 137 | cpu_ca = tcg_global_mem_new(cpu_env, |
da91a00f | 138 | offsetof(CPUPPCState, ca), "CA"); |
dd09c361 ND |
139 | cpu_ov32 = tcg_global_mem_new(cpu_env, |
140 | offsetof(CPUPPCState, ov32), "OV32"); | |
141 | cpu_ca32 = tcg_global_mem_new(cpu_env, | |
142 | offsetof(CPUPPCState, ca32), "CA32"); | |
3d7b417e | 143 | |
e1ccc054 | 144 | cpu_reserve = tcg_global_mem_new(cpu_env, |
1328c2bf | 145 | offsetof(CPUPPCState, reserve_addr), |
18b21a2f | 146 | "reserve_addr"); |
392d328a NP |
147 | cpu_reserve_length = tcg_global_mem_new(cpu_env, |
148 | offsetof(CPUPPCState, | |
149 | reserve_length), | |
150 | "reserve_length"); | |
253ce7b2 | 151 | cpu_reserve_val = tcg_global_mem_new(cpu_env, |
894448ae RH |
152 | offsetof(CPUPPCState, reserve_val), |
153 | "reserve_val"); | |
154 | cpu_reserve_val2 = tcg_global_mem_new(cpu_env, | |
155 | offsetof(CPUPPCState, reserve_val2), | |
156 | "reserve_val2"); | |
cf360a32 | 157 | |
e1ccc054 | 158 | cpu_fpscr = tcg_global_mem_new(cpu_env, |
30304420 | 159 | offsetof(CPUPPCState, fpscr), "fpscr"); |
e1571908 | 160 | |
e1ccc054 | 161 | cpu_access_type = tcg_global_mem_new_i32(cpu_env, |
efe843d8 DG |
162 | offsetof(CPUPPCState, access_type), |
163 | "access_type"); | |
2e70f6ef PB |
164 | } |
165 | ||
79aceca5 | 166 | /* internal defines */ |
69b058c8 | 167 | struct DisasContext { |
b6bac4bc | 168 | DisasContextBase base; |
2c2bcb1b | 169 | target_ulong cia; /* current instruction address */ |
79aceca5 | 170 | uint32_t opcode; |
3cc62370 | 171 | /* Routine used to access memory */ |
5c3ae929 | 172 | bool pr, hv, dr, le_mode; |
c5a8d8f3 | 173 | bool lazy_tlb_flush; |
5f2a6254 | 174 | bool need_access_type; |
3cc62370 | 175 | int mem_idx; |
76db3ba4 | 176 | int access_type; |
3cc62370 | 177 | /* Translation flags */ |
14776ab5 | 178 | MemOp default_tcg_memop_mask; |
d9bce9d9 | 179 | #if defined(TARGET_PPC64) |
5c3ae929 BH |
180 | bool sf_mode; |
181 | bool has_cfar; | |
9a64fbe4 | 182 | #endif |
5c3ae929 BH |
183 | bool fpu_enabled; |
184 | bool altivec_enabled; | |
185 | bool vsx_enabled; | |
186 | bool spe_enabled; | |
187 | bool tm_enabled; | |
c6fd28fd | 188 | bool gtse; |
1db3632a | 189 | bool hr; |
f7460df2 DHB |
190 | bool mmcr0_pmcc0; |
191 | bool mmcr0_pmcc1; | |
8b3d1c49 LL |
192 | bool mmcr0_pmcjce; |
193 | bool pmc_other; | |
46d396bd | 194 | bool pmu_insn_cnt; |
c227f099 | 195 | ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ |
ea4e754f | 196 | int singlestep_enabled; |
0e3bf489 | 197 | uint32_t flags; |
7d08d856 AJ |
198 | uint64_t insns_flags; |
199 | uint64_t insns_flags2; | |
69b058c8 | 200 | }; |
79aceca5 | 201 | |
a9b5b3d0 RH |
202 | #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */ |
203 | #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */ | |
204 | #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ | |
205 | #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ | |
206 | ||
e22c357b DK |
207 | /* Return true iff byteswap is needed in a scalar memop */ |
208 | static inline bool need_byteswap(const DisasContext *ctx) | |
209 | { | |
ee3eb3a7 | 210 | #if TARGET_BIG_ENDIAN |
e22c357b DK |
211 | return ctx->le_mode; |
212 | #else | |
213 | return !ctx->le_mode; | |
214 | #endif | |
215 | } | |
216 | ||
79482e5a RH |
217 | /* True when active word size < size of target_long. */ |
218 | #ifdef TARGET_PPC64 | |
219 | # define NARROW_MODE(C) (!(C)->sf_mode) | |
220 | #else | |
221 | # define NARROW_MODE(C) 0 | |
222 | #endif | |
223 | ||
c227f099 | 224 | struct opc_handler_t { |
70560da7 FC |
225 | /* invalid bits for instruction 1 (Rc(opcode) == 0) */ |
226 | uint32_t inval1; | |
227 | /* invalid bits for instruction 2 (Rc(opcode) == 1) */ | |
228 | uint32_t inval2; | |
9a64fbe4 | 229 | /* instruction type */ |
0487d6a8 | 230 | uint64_t type; |
a5858d7a AG |
231 | /* extended instruction type */ |
232 | uint64_t type2; | |
79aceca5 FB |
233 | /* handler */ |
234 | void (*handler)(DisasContext *ctx); | |
3fc6c082 | 235 | }; |
79aceca5 | 236 | |
0e3bf489 RK |
237 | /* SPR load/store helpers */ |
238 | static inline void gen_load_spr(TCGv t, int reg) | |
239 | { | |
240 | tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); | |
241 | } | |
242 | ||
243 | static inline void gen_store_spr(int reg, TCGv t) | |
244 | { | |
245 | tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); | |
246 | } | |
247 | ||
636aa200 | 248 | static inline void gen_set_access_type(DisasContext *ctx, int access_type) |
a7859e89 | 249 | { |
5f2a6254 | 250 | if (ctx->need_access_type && ctx->access_type != access_type) { |
76db3ba4 AJ |
251 | tcg_gen_movi_i32(cpu_access_type, access_type); |
252 | ctx->access_type = access_type; | |
253 | } | |
a7859e89 AJ |
254 | } |
255 | ||
636aa200 | 256 | static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) |
d9bce9d9 | 257 | { |
e0c8f9ce RH |
258 | if (NARROW_MODE(ctx)) { |
259 | nip = (uint32_t)nip; | |
260 | } | |
261 | tcg_gen_movi_tl(cpu_nip, nip); | |
d9bce9d9 JM |
262 | } |
263 | ||
b9971cc5 | 264 | static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) |
e06fcd75 AJ |
265 | { |
266 | TCGv_i32 t0, t1; | |
bd6fefe7 | 267 | |
efe843d8 DG |
268 | /* |
269 | * These are all synchronous exceptions, we set the PC back to the | |
270 | * faulting instruction | |
bd6fefe7 | 271 | */ |
7a3fe174 | 272 | gen_update_nip(ctx, ctx->cia); |
7058ff52 RH |
273 | t0 = tcg_constant_i32(excp); |
274 | t1 = tcg_constant_i32(error); | |
e5f17ac6 | 275 | gen_helper_raise_exception_err(cpu_env, t0, t1); |
3d8a5b69 | 276 | ctx->base.is_jmp = DISAS_NORETURN; |
e06fcd75 | 277 | } |
e1833e1f | 278 | |
b9971cc5 | 279 | static void gen_exception(DisasContext *ctx, uint32_t excp) |
e06fcd75 AJ |
280 | { |
281 | TCGv_i32 t0; | |
bd6fefe7 | 282 | |
efe843d8 DG |
283 | /* |
284 | * These are all synchronous exceptions, we set the PC back to the | |
285 | * faulting instruction | |
bd6fefe7 | 286 | */ |
7a3fe174 | 287 | gen_update_nip(ctx, ctx->cia); |
7058ff52 | 288 | t0 = tcg_constant_i32(excp); |
e5f17ac6 | 289 | gen_helper_raise_exception(cpu_env, t0); |
3d8a5b69 | 290 | ctx->base.is_jmp = DISAS_NORETURN; |
e06fcd75 | 291 | } |
e1833e1f | 292 | |
bd6fefe7 BH |
293 | static void gen_exception_nip(DisasContext *ctx, uint32_t excp, |
294 | target_ulong nip) | |
295 | { | |
296 | TCGv_i32 t0; | |
297 | ||
298 | gen_update_nip(ctx, nip); | |
7058ff52 | 299 | t0 = tcg_constant_i32(excp); |
bd6fefe7 | 300 | gen_helper_raise_exception(cpu_env, t0); |
3d8a5b69 | 301 | ctx->base.is_jmp = DISAS_NORETURN; |
bd6fefe7 BH |
302 | } |
303 | ||
2fdedcbc MF |
304 | #if !defined(CONFIG_USER_ONLY) |
305 | static void gen_ppc_maybe_interrupt(DisasContext *ctx) | |
306 | { | |
283a9177 | 307 | translator_io_start(&ctx->base); |
2fdedcbc MF |
308 | gen_helper_ppc_maybe_interrupt(cpu_env); |
309 | } | |
310 | #endif | |
311 | ||
e150ac89 RK |
312 | /* |
313 | * Tells the caller what is the appropriate exception to generate and prepares | |
314 | * SPR registers for this exception. | |
315 | * | |
316 | * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or | |
317 | * POWERPC_EXCP_DEBUG (on BookE). | |
0e3bf489 | 318 | */ |
e150ac89 | 319 | static uint32_t gen_prep_dbgex(DisasContext *ctx) |
0e3bf489 | 320 | { |
0e3bf489 RK |
321 | if (ctx->flags & POWERPC_FLAG_DE) { |
322 | target_ulong dbsr = 0; | |
e150ac89 | 323 | if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { |
0e3bf489 | 324 | dbsr = DBCR0_ICMP; |
e150ac89 RK |
325 | } else { |
326 | /* Must have been branch */ | |
0e3bf489 | 327 | dbsr = DBCR0_BRT; |
0e3bf489 RK |
328 | } |
329 | TCGv t0 = tcg_temp_new(); | |
330 | gen_load_spr(t0, SPR_BOOKE_DBSR); | |
331 | tcg_gen_ori_tl(t0, t0, dbsr); | |
332 | gen_store_spr(SPR_BOOKE_DBSR, t0); | |
0e3bf489 RK |
333 | return POWERPC_EXCP_DEBUG; |
334 | } else { | |
e150ac89 | 335 | return POWERPC_EXCP_TRACE; |
0e3bf489 RK |
336 | } |
337 | } | |
338 | ||
b9971cc5 | 339 | static void gen_debug_exception(DisasContext *ctx) |
e06fcd75 | 340 | { |
9498d103 | 341 | gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx))); |
3d8a5b69 | 342 | ctx->base.is_jmp = DISAS_NORETURN; |
e06fcd75 | 343 | } |
9a64fbe4 | 344 | |
636aa200 | 345 | static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) |
e06fcd75 | 346 | { |
9b2fadda BH |
347 | /* Will be converted to program check if needed */ |
348 | gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); | |
349 | } | |
350 | ||
351 | static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) | |
352 | { | |
353 | gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); | |
354 | } | |
355 | ||
356 | static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) | |
357 | { | |
358 | /* Will be converted to program check if needed */ | |
359 | gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); | |
e06fcd75 | 360 | } |
a9d9eb8f | 361 | |
37f219c8 BL |
362 | /*****************************************************************************/ |
363 | /* SPR READ/WRITE CALLBACKS */ | |
364 | ||
a829cec3 | 365 | void spr_noaccess(DisasContext *ctx, int gprn, int sprn) |
37f219c8 BL |
366 | { |
367 | #if 0 | |
368 | sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); | |
369 | printf("ERROR: try to access SPR %d !\n", sprn); | |
370 | #endif | |
371 | } | |
37f219c8 BL |
372 | |
373 | /* #define PPC_DUMP_SPR_ACCESSES */ | |
374 | ||
375 | /* | |
376 | * Generic callbacks: | |
377 | * do nothing but store/retrieve spr value | |
378 | */ | |
379 | static void spr_load_dump_spr(int sprn) | |
380 | { | |
381 | #ifdef PPC_DUMP_SPR_ACCESSES | |
7058ff52 | 382 | TCGv_i32 t0 = tcg_constant_i32(sprn); |
37f219c8 | 383 | gen_helper_load_dump_spr(cpu_env, t0); |
37f219c8 BL |
384 | #endif |
385 | } | |
386 | ||
a829cec3 | 387 | void spr_read_generic(DisasContext *ctx, int gprn, int sprn) |
37f219c8 BL |
388 | { |
389 | gen_load_spr(cpu_gpr[gprn], sprn); | |
390 | spr_load_dump_spr(sprn); | |
391 | } | |
392 | ||
393 | static void spr_store_dump_spr(int sprn) | |
394 | { | |
395 | #ifdef PPC_DUMP_SPR_ACCESSES | |
7058ff52 | 396 | TCGv_i32 t0 = tcg_constant_i32(sprn); |
37f219c8 | 397 | gen_helper_store_dump_spr(cpu_env, t0); |
37f219c8 BL |
398 | #endif |
399 | } | |
400 | ||
a829cec3 | 401 | void spr_write_generic(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
402 | { |
403 | gen_store_spr(sprn, cpu_gpr[gprn]); | |
404 | spr_store_dump_spr(sprn); | |
405 | } | |
406 | ||
a829cec3 | 407 | void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
408 | { |
409 | #ifdef TARGET_PPC64 | |
410 | TCGv t0 = tcg_temp_new(); | |
411 | tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); | |
412 | gen_store_spr(sprn, t0); | |
37f219c8 BL |
413 | spr_store_dump_spr(sprn); |
414 | #else | |
415 | spr_write_generic(ctx, sprn, gprn); | |
416 | #endif | |
417 | } | |
418 | ||
fbda88f7 NP |
419 | void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) |
420 | { | |
421 | spr_write_generic32(ctx, sprn, gprn); | |
422 | ||
423 | /* | |
424 | * SPR_CTRL writes must force a new translation block, | |
425 | * allowing the PMU to calculate the run latch events with | |
426 | * more accuracy. | |
427 | */ | |
428 | ctx->base.is_jmp = DISAS_EXIT_UPDATE; | |
429 | } | |
430 | ||
431 | #if !defined(CONFIG_USER_ONLY) | |
a829cec3 | 432 | void spr_write_clear(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
433 | { |
434 | TCGv t0 = tcg_temp_new(); | |
435 | TCGv t1 = tcg_temp_new(); | |
436 | gen_load_spr(t0, sprn); | |
437 | tcg_gen_neg_tl(t1, cpu_gpr[gprn]); | |
438 | tcg_gen_and_tl(t0, t0, t1); | |
439 | gen_store_spr(sprn, t0); | |
37f219c8 BL |
440 | } |
441 | ||
a829cec3 | 442 | void spr_access_nop(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
443 | { |
444 | } | |
445 | ||
446 | #endif | |
447 | ||
448 | /* SPR common to all PowerPC */ | |
449 | /* XER */ | |
a829cec3 | 450 | void spr_read_xer(DisasContext *ctx, int gprn, int sprn) |
37f219c8 BL |
451 | { |
452 | TCGv dst = cpu_gpr[gprn]; | |
453 | TCGv t0 = tcg_temp_new(); | |
454 | TCGv t1 = tcg_temp_new(); | |
455 | TCGv t2 = tcg_temp_new(); | |
456 | tcg_gen_mov_tl(dst, cpu_xer); | |
457 | tcg_gen_shli_tl(t0, cpu_so, XER_SO); | |
458 | tcg_gen_shli_tl(t1, cpu_ov, XER_OV); | |
459 | tcg_gen_shli_tl(t2, cpu_ca, XER_CA); | |
460 | tcg_gen_or_tl(t0, t0, t1); | |
461 | tcg_gen_or_tl(dst, dst, t2); | |
462 | tcg_gen_or_tl(dst, dst, t0); | |
463 | if (is_isa300(ctx)) { | |
464 | tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); | |
465 | tcg_gen_or_tl(dst, dst, t0); | |
466 | tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); | |
467 | tcg_gen_or_tl(dst, dst, t0); | |
468 | } | |
37f219c8 BL |
469 | } |
470 | ||
a829cec3 | 471 | void spr_write_xer(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
472 | { |
473 | TCGv src = cpu_gpr[gprn]; | |
474 | /* Write all flags, while reading back check for isa300 */ | |
475 | tcg_gen_andi_tl(cpu_xer, src, | |
476 | ~((1u << XER_SO) | | |
477 | (1u << XER_OV) | (1u << XER_OV32) | | |
478 | (1u << XER_CA) | (1u << XER_CA32))); | |
479 | tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); | |
480 | tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); | |
481 | tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); | |
482 | tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); | |
483 | tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); | |
484 | } | |
485 | ||
486 | /* LR */ | |
a829cec3 | 487 | void spr_read_lr(DisasContext *ctx, int gprn, int sprn) |
37f219c8 BL |
488 | { |
489 | tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); | |
490 | } | |
491 | ||
a829cec3 | 492 | void spr_write_lr(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
493 | { |
494 | tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); | |
495 | } | |
496 | ||
497 | /* CFAR */ | |
498 | #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) | |
a829cec3 | 499 | void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) |
37f219c8 BL |
500 | { |
501 | tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); | |
502 | } | |
503 | ||
a829cec3 | 504 | void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
505 | { |
506 | tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); | |
507 | } | |
508 | #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ | |
509 | ||
510 | /* CTR */ | |
a829cec3 | 511 | void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) |
37f219c8 BL |
512 | { |
513 | tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); | |
514 | } | |
515 | ||
a829cec3 | 516 | void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
517 | { |
518 | tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); | |
519 | } | |
520 | ||
521 | /* User read access to SPR */ | |
522 | /* USPRx */ | |
523 | /* UMMCRx */ | |
524 | /* UPMCx */ | |
525 | /* USIA */ | |
526 | /* UDECR */ | |
a829cec3 | 527 | void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) |
37f219c8 BL |
528 | { |
529 | gen_load_spr(cpu_gpr[gprn], sprn + 0x10); | |
530 | } | |
531 | ||
532 | #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) | |
a829cec3 | 533 | void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
534 | { |
535 | gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); | |
536 | } | |
537 | #endif | |
538 | ||
539 | /* SPR common to all non-embedded PowerPC */ | |
540 | /* DECR */ | |
541 | #if !defined(CONFIG_USER_ONLY) | |
a829cec3 | 542 | void spr_read_decr(DisasContext *ctx, int gprn, int sprn) |
37f219c8 | 543 | { |
283a9177 | 544 | translator_io_start(&ctx->base); |
37f219c8 | 545 | gen_helper_load_decr(cpu_gpr[gprn], cpu_env); |
37f219c8 BL |
546 | } |
547 | ||
a829cec3 | 548 | void spr_write_decr(DisasContext *ctx, int sprn, int gprn) |
37f219c8 | 549 | { |
283a9177 | 550 | translator_io_start(&ctx->base); |
37f219c8 | 551 | gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); |
37f219c8 BL |
552 | } |
553 | #endif | |
554 | ||
555 | /* SPR common to all non-embedded PowerPC, except 601 */ | |
556 | /* Time base */ | |
a829cec3 | 557 | void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) |
37f219c8 | 558 | { |
283a9177 | 559 | translator_io_start(&ctx->base); |
37f219c8 | 560 | gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); |
37f219c8 BL |
561 | } |
562 | ||
a829cec3 | 563 | void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) |
37f219c8 | 564 | { |
283a9177 | 565 | translator_io_start(&ctx->base); |
37f219c8 | 566 | gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); |
37f219c8 BL |
567 | } |
568 | ||
a829cec3 | 569 | void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) |
37f219c8 BL |
570 | { |
571 | gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); | |
572 | } | |
573 | ||
a829cec3 | 574 | void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) |
37f219c8 BL |
575 | { |
576 | gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); | |
577 | } | |
578 | ||
579 | #if !defined(CONFIG_USER_ONLY) | |
a829cec3 | 580 | void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) |
37f219c8 | 581 | { |
283a9177 | 582 | translator_io_start(&ctx->base); |
37f219c8 | 583 | gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); |
37f219c8 BL |
584 | } |
585 | ||
a829cec3 | 586 | void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) |
37f219c8 | 587 | { |
283a9177 | 588 | translator_io_start(&ctx->base); |
37f219c8 | 589 | gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); |
37f219c8 BL |
590 | } |
591 | ||
a829cec3 | 592 | void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
593 | { |
594 | gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); | |
595 | } | |
596 | ||
a829cec3 | 597 | void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
598 | { |
599 | gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); | |
600 | } | |
601 | ||
602 | #if defined(TARGET_PPC64) | |
a829cec3 | 603 | void spr_read_purr(DisasContext *ctx, int gprn, int sprn) |
37f219c8 | 604 | { |
283a9177 | 605 | translator_io_start(&ctx->base); |
37f219c8 | 606 | gen_helper_load_purr(cpu_gpr[gprn], cpu_env); |
37f219c8 BL |
607 | } |
608 | ||
a829cec3 | 609 | void spr_write_purr(DisasContext *ctx, int sprn, int gprn) |
37f219c8 | 610 | { |
283a9177 | 611 | translator_io_start(&ctx->base); |
37f219c8 | 612 | gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); |
37f219c8 BL |
613 | } |
614 | ||
615 | /* HDECR */ | |
a829cec3 | 616 | void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) |
37f219c8 | 617 | { |
283a9177 | 618 | translator_io_start(&ctx->base); |
37f219c8 | 619 | gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); |
37f219c8 BL |
620 | } |
621 | ||
a829cec3 | 622 | void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) |
37f219c8 | 623 | { |
283a9177 | 624 | translator_io_start(&ctx->base); |
37f219c8 | 625 | gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); |
37f219c8 BL |
626 | } |
627 | ||
a829cec3 | 628 | void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) |
37f219c8 | 629 | { |
283a9177 | 630 | translator_io_start(&ctx->base); |
37f219c8 | 631 | gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); |
37f219c8 BL |
632 | } |
633 | ||
a829cec3 | 634 | void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) |
37f219c8 | 635 | { |
283a9177 | 636 | translator_io_start(&ctx->base); |
37f219c8 | 637 | gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); |
37f219c8 BL |
638 | } |
639 | ||
a829cec3 | 640 | void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) |
37f219c8 | 641 | { |
283a9177 | 642 | translator_io_start(&ctx->base); |
37f219c8 | 643 | gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); |
37f219c8 BL |
644 | } |
645 | ||
646 | #endif | |
647 | #endif | |
648 | ||
649 | #if !defined(CONFIG_USER_ONLY) | |
650 | /* IBAT0U...IBAT0U */ | |
651 | /* IBAT0L...IBAT7L */ | |
a829cec3 | 652 | void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) |
37f219c8 BL |
653 | { |
654 | tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, | |
655 | offsetof(CPUPPCState, | |
656 | IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); | |
657 | } | |
658 | ||
a829cec3 | 659 | void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) |
37f219c8 BL |
660 | { |
661 | tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, | |
662 | offsetof(CPUPPCState, | |
663 | IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); | |
664 | } | |
665 | ||
a829cec3 | 666 | void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) |
37f219c8 | 667 | { |
7058ff52 | 668 | TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0U) / 2); |
37f219c8 | 669 | gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); |
37f219c8 BL |
670 | } |
671 | ||
a829cec3 | 672 | void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) |
37f219c8 | 673 | { |
7058ff52 | 674 | TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4U) / 2) + 4); |
37f219c8 | 675 | gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); |
37f219c8 BL |
676 | } |
677 | ||
a829cec3 | 678 | void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) |
37f219c8 | 679 | { |
7058ff52 | 680 | TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0L) / 2); |
37f219c8 | 681 | gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); |
37f219c8 BL |
682 | } |
683 | ||
a829cec3 | 684 | void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) |
37f219c8 | 685 | { |
7058ff52 | 686 | TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4L) / 2) + 4); |
37f219c8 | 687 | gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); |
37f219c8 BL |
688 | } |
689 | ||
690 | /* DBAT0U...DBAT7U */ | |
691 | /* DBAT0L...DBAT7L */ | |
a829cec3 | 692 | void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) |
37f219c8 BL |
693 | { |
694 | tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, | |
695 | offsetof(CPUPPCState, | |
696 | DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); | |
697 | } | |
698 | ||
a829cec3 | 699 | void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) |
37f219c8 BL |
700 | { |
701 | tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, | |
702 | offsetof(CPUPPCState, | |
703 | DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); | |
704 | } | |
705 | ||
a829cec3 | 706 | void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) |
37f219c8 | 707 | { |
7058ff52 | 708 | TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0U) / 2); |
37f219c8 | 709 | gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); |
37f219c8 BL |
710 | } |
711 | ||
a829cec3 | 712 | void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) |
37f219c8 | 713 | { |
7058ff52 | 714 | TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4U) / 2) + 4); |
37f219c8 | 715 | gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); |
37f219c8 BL |
716 | } |
717 | ||
a829cec3 | 718 | void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) |
37f219c8 | 719 | { |
7058ff52 | 720 | TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0L) / 2); |
37f219c8 | 721 | gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); |
37f219c8 BL |
722 | } |
723 | ||
a829cec3 | 724 | void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) |
37f219c8 | 725 | { |
7058ff52 | 726 | TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4L) / 2) + 4); |
37f219c8 | 727 | gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); |
37f219c8 BL |
728 | } |
729 | ||
730 | /* SDR1 */ | |
a829cec3 | 731 | void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
732 | { |
733 | gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); | |
734 | } | |
735 | ||
736 | #if defined(TARGET_PPC64) | |
737 | /* 64 bits PowerPC specific SPRs */ | |
738 | /* PIDR */ | |
a829cec3 | 739 | void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
740 | { |
741 | gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); | |
742 | } | |
743 | ||
a829cec3 | 744 | void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
745 | { |
746 | gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); | |
747 | } | |
748 | ||
a829cec3 | 749 | void spr_read_hior(DisasContext *ctx, int gprn, int sprn) |
37f219c8 BL |
750 | { |
751 | tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); | |
752 | } | |
753 | ||
a829cec3 | 754 | void spr_write_hior(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
755 | { |
756 | TCGv t0 = tcg_temp_new(); | |
757 | tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); | |
758 | tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); | |
37f219c8 | 759 | } |
a829cec3 | 760 | void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
761 | { |
762 | gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); | |
763 | } | |
764 | ||
a829cec3 | 765 | void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
766 | { |
767 | gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); | |
768 | } | |
769 | ||
770 | /* DPDES */ | |
a829cec3 | 771 | void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) |
37f219c8 BL |
772 | { |
773 | gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); | |
774 | } | |
775 | ||
a829cec3 | 776 | void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
777 | { |
778 | gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); | |
779 | } | |
780 | #endif | |
781 | #endif | |
782 | ||
37f219c8 BL |
783 | /* PowerPC 40x specific registers */ |
784 | #if !defined(CONFIG_USER_ONLY) | |
a829cec3 | 785 | void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) |
37f219c8 | 786 | { |
283a9177 | 787 | translator_io_start(&ctx->base); |
37f219c8 | 788 | gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); |
37f219c8 BL |
789 | } |
790 | ||
a829cec3 | 791 | void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) |
37f219c8 | 792 | { |
283a9177 | 793 | translator_io_start(&ctx->base); |
37f219c8 | 794 | gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); |
37f219c8 BL |
795 | } |
796 | ||
a829cec3 | 797 | void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) |
37f219c8 | 798 | { |
283a9177 | 799 | translator_io_start(&ctx->base); |
37f219c8 BL |
800 | gen_store_spr(sprn, cpu_gpr[gprn]); |
801 | gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); | |
802 | /* We must stop translation as we may have rebooted */ | |
d736de8f | 803 | ctx->base.is_jmp = DISAS_EXIT_UPDATE; |
37f219c8 BL |
804 | } |
805 | ||
a829cec3 | 806 | void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) |
37f219c8 | 807 | { |
283a9177 | 808 | translator_io_start(&ctx->base); |
37f219c8 | 809 | gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); |
37f219c8 BL |
810 | } |
811 | ||
cbd8f17d CLG |
812 | void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn) |
813 | { | |
283a9177 | 814 | translator_io_start(&ctx->base); |
cbd8f17d CLG |
815 | gen_helper_store_40x_tcr(cpu_env, cpu_gpr[gprn]); |
816 | } | |
817 | ||
818 | void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn) | |
819 | { | |
283a9177 | 820 | translator_io_start(&ctx->base); |
cbd8f17d CLG |
821 | gen_helper_store_40x_tsr(cpu_env, cpu_gpr[gprn]); |
822 | } | |
823 | ||
dd69d140 CLG |
824 | void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn) |
825 | { | |
826 | TCGv t0 = tcg_temp_new(); | |
827 | tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF); | |
47822486 | 828 | gen_helper_store_40x_pid(cpu_env, t0); |
dd69d140 CLG |
829 | } |
830 | ||
a829cec3 | 831 | void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) |
37f219c8 | 832 | { |
283a9177 | 833 | translator_io_start(&ctx->base); |
37f219c8 | 834 | gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); |
37f219c8 BL |
835 | } |
836 | ||
a829cec3 | 837 | void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) |
37f219c8 | 838 | { |
283a9177 | 839 | translator_io_start(&ctx->base); |
37f219c8 | 840 | gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); |
37f219c8 BL |
841 | } |
842 | #endif | |
843 | ||
328c95fc | 844 | /* PIR */ |
37f219c8 | 845 | #if !defined(CONFIG_USER_ONLY) |
a829cec3 | 846 | void spr_write_pir(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
847 | { |
848 | TCGv t0 = tcg_temp_new(); | |
849 | tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); | |
850 | gen_store_spr(SPR_PIR, t0); | |
37f219c8 BL |
851 | } |
852 | #endif | |
853 | ||
854 | /* SPE specific registers */ | |
a829cec3 | 855 | void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) |
37f219c8 BL |
856 | { |
857 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
858 | tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); | |
859 | tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); | |
37f219c8 BL |
860 | } |
861 | ||
a829cec3 | 862 | void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
863 | { |
864 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
865 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); | |
866 | tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); | |
37f219c8 BL |
867 | } |
868 | ||
869 | #if !defined(CONFIG_USER_ONLY) | |
870 | /* Callback used to write the exception vector base */ | |
a829cec3 | 871 | void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
872 | { |
873 | TCGv t0 = tcg_temp_new(); | |
874 | tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); | |
875 | tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); | |
876 | tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); | |
877 | gen_store_spr(sprn, t0); | |
37f219c8 BL |
878 | } |
879 | ||
a829cec3 | 880 | void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
881 | { |
882 | int sprn_offs; | |
883 | ||
884 | if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { | |
885 | sprn_offs = sprn - SPR_BOOKE_IVOR0; | |
886 | } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { | |
887 | sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; | |
888 | } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { | |
889 | sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; | |
890 | } else { | |
8e1fedf8 MF |
891 | qemu_log_mask(LOG_GUEST_ERROR, "Trying to write an unknown exception" |
892 | " vector 0x%03x\n", sprn); | |
893 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
37f219c8 BL |
894 | return; |
895 | } | |
896 | ||
897 | TCGv t0 = tcg_temp_new(); | |
898 | tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); | |
899 | tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); | |
900 | tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); | |
901 | gen_store_spr(sprn, t0); | |
37f219c8 BL |
902 | } |
903 | #endif | |
904 | ||
905 | #ifdef TARGET_PPC64 | |
906 | #ifndef CONFIG_USER_ONLY | |
a829cec3 | 907 | void spr_write_amr(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
908 | { |
909 | TCGv t0 = tcg_temp_new(); | |
910 | TCGv t1 = tcg_temp_new(); | |
911 | TCGv t2 = tcg_temp_new(); | |
912 | ||
913 | /* | |
914 | * Note, the HV=1 PR=0 case is handled earlier by simply using | |
915 | * spr_write_generic for HV mode in the SPR table | |
916 | */ | |
917 | ||
918 | /* Build insertion mask into t1 based on context */ | |
919 | if (ctx->pr) { | |
920 | gen_load_spr(t1, SPR_UAMOR); | |
921 | } else { | |
922 | gen_load_spr(t1, SPR_AMOR); | |
923 | } | |
924 | ||
925 | /* Mask new bits into t2 */ | |
926 | tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); | |
927 | ||
928 | /* Load AMR and clear new bits in t0 */ | |
929 | gen_load_spr(t0, SPR_AMR); | |
930 | tcg_gen_andc_tl(t0, t0, t1); | |
931 | ||
932 | /* Or'in new bits and write it out */ | |
933 | tcg_gen_or_tl(t0, t0, t2); | |
934 | gen_store_spr(SPR_AMR, t0); | |
935 | spr_store_dump_spr(SPR_AMR); | |
37f219c8 BL |
936 | } |
937 | ||
a829cec3 | 938 | void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
939 | { |
940 | TCGv t0 = tcg_temp_new(); | |
941 | TCGv t1 = tcg_temp_new(); | |
942 | TCGv t2 = tcg_temp_new(); | |
943 | ||
944 | /* | |
945 | * Note, the HV=1 case is handled earlier by simply using | |
946 | * spr_write_generic for HV mode in the SPR table | |
947 | */ | |
948 | ||
949 | /* Build insertion mask into t1 based on context */ | |
950 | gen_load_spr(t1, SPR_AMOR); | |
951 | ||
952 | /* Mask new bits into t2 */ | |
953 | tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); | |
954 | ||
955 | /* Load AMR and clear new bits in t0 */ | |
956 | gen_load_spr(t0, SPR_UAMOR); | |
957 | tcg_gen_andc_tl(t0, t0, t1); | |
958 | ||
959 | /* Or'in new bits and write it out */ | |
960 | tcg_gen_or_tl(t0, t0, t2); | |
961 | gen_store_spr(SPR_UAMOR, t0); | |
962 | spr_store_dump_spr(SPR_UAMOR); | |
37f219c8 BL |
963 | } |
964 | ||
a829cec3 | 965 | void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
966 | { |
967 | TCGv t0 = tcg_temp_new(); | |
968 | TCGv t1 = tcg_temp_new(); | |
969 | TCGv t2 = tcg_temp_new(); | |
970 | ||
971 | /* | |
972 | * Note, the HV=1 case is handled earlier by simply using | |
973 | * spr_write_generic for HV mode in the SPR table | |
974 | */ | |
975 | ||
976 | /* Build insertion mask into t1 based on context */ | |
977 | gen_load_spr(t1, SPR_AMOR); | |
978 | ||
979 | /* Mask new bits into t2 */ | |
980 | tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); | |
981 | ||
982 | /* Load AMR and clear new bits in t0 */ | |
983 | gen_load_spr(t0, SPR_IAMR); | |
984 | tcg_gen_andc_tl(t0, t0, t1); | |
985 | ||
986 | /* Or'in new bits and write it out */ | |
987 | tcg_gen_or_tl(t0, t0, t2); | |
988 | gen_store_spr(SPR_IAMR, t0); | |
989 | spr_store_dump_spr(SPR_IAMR); | |
37f219c8 BL |
990 | } |
991 | #endif | |
992 | #endif | |
993 | ||
994 | #ifndef CONFIG_USER_ONLY | |
a829cec3 | 995 | void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) |
37f219c8 BL |
996 | { |
997 | gen_helper_fixup_thrm(cpu_env); | |
998 | gen_load_spr(cpu_gpr[gprn], sprn); | |
999 | spr_load_dump_spr(sprn); | |
1000 | } | |
1001 | #endif /* !CONFIG_USER_ONLY */ | |
1002 | ||
1003 | #if !defined(CONFIG_USER_ONLY) | |
a829cec3 | 1004 | void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
1005 | { |
1006 | TCGv t0 = tcg_temp_new(); | |
1007 | ||
1008 | tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); | |
1009 | gen_store_spr(sprn, t0); | |
37f219c8 BL |
1010 | } |
1011 | ||
a829cec3 | 1012 | void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
1013 | { |
1014 | TCGv t0 = tcg_temp_new(); | |
1015 | ||
1016 | tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); | |
1017 | gen_store_spr(sprn, t0); | |
37f219c8 BL |
1018 | } |
1019 | ||
a829cec3 | 1020 | void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
1021 | { |
1022 | TCGv t0 = tcg_temp_new(); | |
1023 | ||
1024 | tcg_gen_andi_tl(t0, cpu_gpr[gprn], | |
1025 | ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); | |
1026 | gen_store_spr(sprn, t0); | |
37f219c8 BL |
1027 | } |
1028 | ||
a829cec3 | 1029 | void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
1030 | { |
1031 | gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); | |
1032 | } | |
1033 | ||
a829cec3 | 1034 | void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) |
37f219c8 | 1035 | { |
7058ff52 | 1036 | TCGv_i32 t0 = tcg_constant_i32(sprn); |
37f219c8 | 1037 | gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); |
37f219c8 | 1038 | } |
7058ff52 | 1039 | |
a829cec3 | 1040 | void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
1041 | { |
1042 | gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); | |
1043 | } | |
7058ff52 | 1044 | |
a829cec3 | 1045 | void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
1046 | { |
1047 | gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); | |
1048 | } | |
1049 | ||
1050 | #endif | |
1051 | ||
1052 | #if !defined(CONFIG_USER_ONLY) | |
a829cec3 | 1053 | void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
1054 | { |
1055 | TCGv val = tcg_temp_new(); | |
1056 | tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); | |
1057 | gen_store_spr(SPR_BOOKE_MAS3, val); | |
1058 | tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); | |
1059 | gen_store_spr(SPR_BOOKE_MAS7, val); | |
37f219c8 BL |
1060 | } |
1061 | ||
a829cec3 | 1062 | void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) |
37f219c8 BL |
1063 | { |
1064 | TCGv mas7 = tcg_temp_new(); | |
1065 | TCGv mas3 = tcg_temp_new(); | |
1066 | gen_load_spr(mas7, SPR_BOOKE_MAS7); | |
1067 | tcg_gen_shli_tl(mas7, mas7, 32); | |
1068 | gen_load_spr(mas3, SPR_BOOKE_MAS3); | |
1069 | tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); | |
37f219c8 BL |
1070 | } |
1071 | ||
1072 | #endif | |
1073 | ||
1074 | #ifdef TARGET_PPC64 | |
1075 | static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, | |
1076 | int bit, int sprn, int cause) | |
1077 | { | |
7058ff52 RH |
1078 | TCGv_i32 t1 = tcg_constant_i32(bit); |
1079 | TCGv_i32 t2 = tcg_constant_i32(sprn); | |
1080 | TCGv_i32 t3 = tcg_constant_i32(cause); | |
37f219c8 BL |
1081 | |
1082 | gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); | |
37f219c8 BL |
1083 | } |
1084 | ||
1085 | static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, | |
1086 | int bit, int sprn, int cause) | |
1087 | { | |
7058ff52 RH |
1088 | TCGv_i32 t1 = tcg_constant_i32(bit); |
1089 | TCGv_i32 t2 = tcg_constant_i32(sprn); | |
1090 | TCGv_i32 t3 = tcg_constant_i32(cause); | |
37f219c8 BL |
1091 | |
1092 | gen_helper_msr_facility_check(cpu_env, t1, t2, t3); | |
37f219c8 BL |
1093 | } |
1094 | ||
a829cec3 | 1095 | void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) |
37f219c8 BL |
1096 | { |
1097 | TCGv spr_up = tcg_temp_new(); | |
1098 | TCGv spr = tcg_temp_new(); | |
1099 | ||
1100 | gen_load_spr(spr, sprn - 1); | |
1101 | tcg_gen_shri_tl(spr_up, spr, 32); | |
1102 | tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); | |
37f219c8 BL |
1103 | } |
1104 | ||
a829cec3 | 1105 | void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
1106 | { |
1107 | TCGv spr = tcg_temp_new(); | |
1108 | ||
1109 | gen_load_spr(spr, sprn - 1); | |
1110 | tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); | |
1111 | gen_store_spr(sprn - 1, spr); | |
37f219c8 BL |
1112 | } |
1113 | ||
1114 | #if !defined(CONFIG_USER_ONLY) | |
a829cec3 | 1115 | void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
1116 | { |
1117 | TCGv hmer = tcg_temp_new(); | |
1118 | ||
1119 | gen_load_spr(hmer, sprn); | |
1120 | tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); | |
1121 | gen_store_spr(sprn, hmer); | |
1122 | spr_store_dump_spr(sprn); | |
37f219c8 BL |
1123 | } |
1124 | ||
a829cec3 | 1125 | void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
1126 | { |
1127 | gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); | |
1128 | } | |
1129 | #endif /* !defined(CONFIG_USER_ONLY) */ | |
1130 | ||
a829cec3 | 1131 | void spr_read_tar(DisasContext *ctx, int gprn, int sprn) |
37f219c8 BL |
1132 | { |
1133 | gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); | |
1134 | spr_read_generic(ctx, gprn, sprn); | |
1135 | } | |
1136 | ||
a829cec3 | 1137 | void spr_write_tar(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
1138 | { |
1139 | gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); | |
1140 | spr_write_generic(ctx, sprn, gprn); | |
1141 | } | |
1142 | ||
a829cec3 | 1143 | void spr_read_tm(DisasContext *ctx, int gprn, int sprn) |
37f219c8 BL |
1144 | { |
1145 | gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); | |
1146 | spr_read_generic(ctx, gprn, sprn); | |
1147 | } | |
1148 | ||
a829cec3 | 1149 | void spr_write_tm(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
1150 | { |
1151 | gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); | |
1152 | spr_write_generic(ctx, sprn, gprn); | |
1153 | } | |
1154 | ||
a829cec3 | 1155 | void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) |
37f219c8 BL |
1156 | { |
1157 | gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); | |
1158 | spr_read_prev_upper32(ctx, gprn, sprn); | |
1159 | } | |
1160 | ||
a829cec3 | 1161 | void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
1162 | { |
1163 | gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); | |
1164 | spr_write_prev_upper32(ctx, sprn, gprn); | |
1165 | } | |
1166 | ||
a829cec3 | 1167 | void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) |
37f219c8 BL |
1168 | { |
1169 | gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); | |
1170 | spr_read_generic(ctx, gprn, sprn); | |
1171 | } | |
1172 | ||
a829cec3 | 1173 | void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
1174 | { |
1175 | gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); | |
1176 | spr_write_generic(ctx, sprn, gprn); | |
1177 | } | |
1178 | ||
a829cec3 | 1179 | void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) |
37f219c8 BL |
1180 | { |
1181 | gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); | |
1182 | spr_read_prev_upper32(ctx, gprn, sprn); | |
1183 | } | |
1184 | ||
a829cec3 | 1185 | void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) |
37f219c8 BL |
1186 | { |
1187 | gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); | |
1188 | spr_write_prev_upper32(ctx, sprn, gprn); | |
1189 | } | |
395b5d5b NM |
1190 | |
1191 | void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn) | |
1192 | { | |
1193 | TCGv t0 = tcg_temp_new(); | |
1194 | ||
1195 | /* | |
1196 | * Access to the (H)DEXCR in problem state is done using separated | |
1197 | * SPR indexes which are 16 below the SPR indexes which have full | |
1198 | * access to the (H)DEXCR in privileged state. Problem state can | |
1199 | * only read bits 32:63, bits 0:31 return 0. | |
1200 | * | |
1201 | * See section 9.3.1-9.3.2 of PowerISA v3.1B | |
1202 | */ | |
1203 | ||
1204 | gen_load_spr(t0, sprn + 16); | |
1205 | tcg_gen_ext32u_tl(cpu_gpr[gprn], t0); | |
395b5d5b | 1206 | } |
37f219c8 BL |
1207 | #endif |
1208 | ||
79aceca5 | 1209 | #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ |
a5858d7a AG |
1210 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) |
1211 | ||
1212 | #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ | |
1213 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) | |
79aceca5 | 1214 | |
c7697e1f | 1215 | #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ |
a5858d7a AG |
1216 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) |
1217 | ||
1218 | #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ | |
1219 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) | |
c7697e1f | 1220 | |
323ad19b ND |
1221 | #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ |
1222 | GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) | |
1223 | ||
14fd8ab2 ND |
1224 | #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ |
1225 | GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) | |
1226 | ||
c227f099 | 1227 | typedef struct opcode_t { |
323ad19b | 1228 | unsigned char opc1, opc2, opc3, opc4; |
1235fc06 | 1229 | #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ |
323ad19b | 1230 | unsigned char pad[4]; |
18fba28c | 1231 | #endif |
c227f099 | 1232 | opc_handler_t handler; |
b55266b5 | 1233 | const char *oname; |
c227f099 | 1234 | } opcode_t; |
79aceca5 | 1235 | |
9f0cf041 MF |
1236 | static void gen_priv_opc(DisasContext *ctx) |
1237 | { | |
1238 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
1239 | } | |
1240 | ||
9b2fadda | 1241 | /* Helpers for priv. check */ |
9f0cf041 MF |
1242 | #define GEN_PRIV(CTX) \ |
1243 | do { \ | |
1244 | gen_priv_opc(CTX); return; \ | |
9b2fadda BH |
1245 | } while (0) |
1246 | ||
1247 | #if defined(CONFIG_USER_ONLY) | |
9f0cf041 MF |
1248 | #define CHK_HV(CTX) GEN_PRIV(CTX) |
1249 | #define CHK_SV(CTX) GEN_PRIV(CTX) | |
1250 | #define CHK_HVRM(CTX) GEN_PRIV(CTX) | |
9b2fadda | 1251 | #else |
9f0cf041 MF |
1252 | #define CHK_HV(CTX) \ |
1253 | do { \ | |
1254 | if (unlikely(ctx->pr || !ctx->hv)) {\ | |
1255 | GEN_PRIV(CTX); \ | |
1256 | } \ | |
9b2fadda | 1257 | } while (0) |
9f0cf041 | 1258 | #define CHK_SV(CTX) \ |
9b2fadda BH |
1259 | do { \ |
1260 | if (unlikely(ctx->pr)) { \ | |
9f0cf041 | 1261 | GEN_PRIV(CTX); \ |
9b2fadda BH |
1262 | } \ |
1263 | } while (0) | |
9f0cf041 MF |
1264 | #define CHK_HVRM(CTX) \ |
1265 | do { \ | |
1266 | if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ | |
1267 | GEN_PRIV(CTX); \ | |
1268 | } \ | |
b7815375 | 1269 | } while (0) |
9b2fadda BH |
1270 | #endif |
1271 | ||
9f0cf041 | 1272 | #define CHK_NONE(CTX) |
9b2fadda | 1273 | |
a750fc0b | 1274 | /*****************************************************************************/ |
a750fc0b | 1275 | /* PowerPC instructions table */ |
933dc6eb | 1276 | |
a5858d7a | 1277 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 1278 | { \ |
79aceca5 FB |
1279 | .opc1 = op1, \ |
1280 | .opc2 = op2, \ | |
1281 | .opc3 = op3, \ | |
323ad19b | 1282 | .opc4 = 0xff, \ |
79aceca5 | 1283 | .handler = { \ |
70560da7 FC |
1284 | .inval1 = invl, \ |
1285 | .type = _typ, \ | |
1286 | .type2 = _typ2, \ | |
1287 | .handler = &gen_##name, \ | |
70560da7 FC |
1288 | }, \ |
1289 | .oname = stringify(name), \ | |
1290 | } | |
1291 | #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ | |
1292 | { \ | |
1293 | .opc1 = op1, \ | |
1294 | .opc2 = op2, \ | |
1295 | .opc3 = op3, \ | |
323ad19b | 1296 | .opc4 = 0xff, \ |
70560da7 FC |
1297 | .handler = { \ |
1298 | .inval1 = invl1, \ | |
1299 | .inval2 = invl2, \ | |
9a64fbe4 | 1300 | .type = _typ, \ |
a5858d7a | 1301 | .type2 = _typ2, \ |
79aceca5 FB |
1302 | .handler = &gen_##name, \ |
1303 | }, \ | |
3fc6c082 | 1304 | .oname = stringify(name), \ |
79aceca5 | 1305 | } |
a5858d7a | 1306 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 1307 | { \ |
c7697e1f JM |
1308 | .opc1 = op1, \ |
1309 | .opc2 = op2, \ | |
1310 | .opc3 = op3, \ | |
323ad19b | 1311 | .opc4 = 0xff, \ |
c7697e1f | 1312 | .handler = { \ |
70560da7 | 1313 | .inval1 = invl, \ |
c7697e1f | 1314 | .type = _typ, \ |
a5858d7a | 1315 | .type2 = _typ2, \ |
c7697e1f | 1316 | .handler = &gen_##name, \ |
c7697e1f JM |
1317 | }, \ |
1318 | .oname = onam, \ | |
1319 | } | |
323ad19b ND |
1320 | #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ |
1321 | { \ | |
1322 | .opc1 = op1, \ | |
1323 | .opc2 = op2, \ | |
1324 | .opc3 = op3, \ | |
1325 | .opc4 = op4, \ | |
1326 | .handler = { \ | |
1327 | .inval1 = invl, \ | |
1328 | .type = _typ, \ | |
1329 | .type2 = _typ2, \ | |
1330 | .handler = &gen_##name, \ | |
323ad19b ND |
1331 | }, \ |
1332 | .oname = stringify(name), \ | |
1333 | } | |
14fd8ab2 ND |
1334 | #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ |
1335 | { \ | |
1336 | .opc1 = op1, \ | |
1337 | .opc2 = op2, \ | |
1338 | .opc3 = op3, \ | |
1339 | .opc4 = op4, \ | |
1340 | .handler = { \ | |
1341 | .inval1 = invl, \ | |
1342 | .type = _typ, \ | |
1343 | .type2 = _typ2, \ | |
1344 | .handler = &gen_##name, \ | |
14fd8ab2 ND |
1345 | }, \ |
1346 | .oname = onam, \ | |
1347 | } | |
2e610050 | 1348 | |
54623277 | 1349 | /* Invalid instruction */ |
99e300ef | 1350 | static void gen_invalid(DisasContext *ctx) |
9a64fbe4 | 1351 | { |
e06fcd75 | 1352 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
9a64fbe4 FB |
1353 | } |
1354 | ||
c227f099 | 1355 | static opc_handler_t invalid_handler = { |
70560da7 FC |
1356 | .inval1 = 0xFFFFFFFF, |
1357 | .inval2 = 0xFFFFFFFF, | |
9a64fbe4 | 1358 | .type = PPC_NONE, |
a5858d7a | 1359 | .type2 = PPC_NONE, |
79aceca5 FB |
1360 | .handler = gen_invalid, |
1361 | }; | |
1362 | ||
e1571908 AJ |
1363 | /*** Integer comparison ***/ |
1364 | ||
636aa200 | 1365 | static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) |
e1571908 | 1366 | { |
2fdcb629 | 1367 | TCGv t0 = tcg_temp_new(); |
b62b3686 PB |
1368 | TCGv t1 = tcg_temp_new(); |
1369 | TCGv_i32 t = tcg_temp_new_i32(); | |
e1571908 | 1370 | |
b62b3686 PB |
1371 | tcg_gen_movi_tl(t0, CRF_EQ); |
1372 | tcg_gen_movi_tl(t1, CRF_LT); | |
efe843d8 DG |
1373 | tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), |
1374 | t0, arg0, arg1, t1, t0); | |
b62b3686 | 1375 | tcg_gen_movi_tl(t1, CRF_GT); |
efe843d8 DG |
1376 | tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), |
1377 | t0, arg0, arg1, t1, t0); | |
2fdcb629 | 1378 | |
b62b3686 PB |
1379 | tcg_gen_trunc_tl_i32(t, t0); |
1380 | tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); | |
1381 | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); | |
e1571908 AJ |
1382 | } |
1383 | ||
636aa200 | 1384 | static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) |
e1571908 | 1385 | { |
7058ff52 | 1386 | TCGv t0 = tcg_constant_tl(arg1); |
ea363694 | 1387 | gen_op_cmp(arg0, t0, s, crf); |
e1571908 AJ |
1388 | } |
1389 | ||
636aa200 | 1390 | static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) |
e1571908 | 1391 | { |
ea363694 | 1392 | TCGv t0, t1; |
2fdcb629 RH |
1393 | t0 = tcg_temp_new(); |
1394 | t1 = tcg_temp_new(); | |
e1571908 | 1395 | if (s) { |
ea363694 AJ |
1396 | tcg_gen_ext32s_tl(t0, arg0); |
1397 | tcg_gen_ext32s_tl(t1, arg1); | |
e1571908 | 1398 | } else { |
ea363694 AJ |
1399 | tcg_gen_ext32u_tl(t0, arg0); |
1400 | tcg_gen_ext32u_tl(t1, arg1); | |
e1571908 | 1401 | } |
ea363694 | 1402 | gen_op_cmp(t0, t1, s, crf); |
e1571908 AJ |
1403 | } |
1404 | ||
636aa200 | 1405 | static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) |
e1571908 | 1406 | { |
7058ff52 | 1407 | TCGv t0 = tcg_constant_tl(arg1); |
ea363694 | 1408 | gen_op_cmp32(arg0, t0, s, crf); |
e1571908 | 1409 | } |
e1571908 | 1410 | |
636aa200 | 1411 | static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) |
e1571908 | 1412 | { |
02765534 | 1413 | if (NARROW_MODE(ctx)) { |
e1571908 | 1414 | gen_op_cmpi32(reg, 0, 1, 0); |
02765534 | 1415 | } else { |
e1571908 | 1416 | gen_op_cmpi(reg, 0, 1, 0); |
02765534 | 1417 | } |
e1571908 AJ |
1418 | } |
1419 | ||
f2442ef9 ND |
1420 | /* cmprb - range comparison: isupper, isaplha, islower*/ |
1421 | static void gen_cmprb(DisasContext *ctx) | |
1422 | { | |
1423 | TCGv_i32 src1 = tcg_temp_new_i32(); | |
1424 | TCGv_i32 src2 = tcg_temp_new_i32(); | |
1425 | TCGv_i32 src2lo = tcg_temp_new_i32(); | |
1426 | TCGv_i32 src2hi = tcg_temp_new_i32(); | |
1427 | TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; | |
1428 | ||
1429 | tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); | |
1430 | tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); | |
1431 | ||
1432 | tcg_gen_andi_i32(src1, src1, 0xFF); | |
1433 | tcg_gen_ext8u_i32(src2lo, src2); | |
1434 | tcg_gen_shri_i32(src2, src2, 8); | |
1435 | tcg_gen_ext8u_i32(src2hi, src2); | |
1436 | ||
1437 | tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); | |
1438 | tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); | |
1439 | tcg_gen_and_i32(crf, src2lo, src2hi); | |
1440 | ||
1441 | if (ctx->opcode & 0x00200000) { | |
1442 | tcg_gen_shri_i32(src2, src2, 8); | |
1443 | tcg_gen_ext8u_i32(src2lo, src2); | |
1444 | tcg_gen_shri_i32(src2, src2, 8); | |
1445 | tcg_gen_ext8u_i32(src2hi, src2); | |
1446 | tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); | |
1447 | tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); | |
1448 | tcg_gen_and_i32(src2lo, src2lo, src2hi); | |
1449 | tcg_gen_or_i32(crf, crf, src2lo); | |
1450 | } | |
efa73196 | 1451 | tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); |
f2442ef9 ND |
1452 | } |
1453 | ||
082ce330 ND |
1454 | #if defined(TARGET_PPC64) |
1455 | /* cmpeqb */ | |
1456 | static void gen_cmpeqb(DisasContext *ctx) | |
1457 | { | |
1458 | gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
1459 | cpu_gpr[rB(ctx->opcode)]); | |
1460 | } | |
1461 | #endif | |
1462 | ||
e1571908 | 1463 | /* isel (PowerPC 2.03 specification) */ |
99e300ef | 1464 | static void gen_isel(DisasContext *ctx) |
e1571908 | 1465 | { |
e1571908 | 1466 | uint32_t bi = rC(ctx->opcode); |
24f9cd95 RH |
1467 | uint32_t mask = 0x08 >> (bi & 0x03); |
1468 | TCGv t0 = tcg_temp_new(); | |
1469 | TCGv zr; | |
e1571908 | 1470 | |
24f9cd95 RH |
1471 | tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); |
1472 | tcg_gen_andi_tl(t0, t0, mask); | |
1473 | ||
7058ff52 | 1474 | zr = tcg_constant_tl(0); |
24f9cd95 RH |
1475 | tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, |
1476 | rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, | |
1477 | cpu_gpr[rB(ctx->opcode)]); | |
e1571908 AJ |
1478 | } |
1479 | ||
fcfda20f AJ |
1480 | /* cmpb: PowerPC 2.05 specification */ |
1481 | static void gen_cmpb(DisasContext *ctx) | |
1482 | { | |
1483 | gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], | |
1484 | cpu_gpr[rB(ctx->opcode)]); | |
1485 | } | |
1486 | ||
79aceca5 | 1487 | /*** Integer arithmetic ***/ |
79aceca5 | 1488 | |
636aa200 BS |
1489 | static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, |
1490 | TCGv arg1, TCGv arg2, int sub) | |
74637406 | 1491 | { |
ffe30937 | 1492 | TCGv t0 = tcg_temp_new(); |
79aceca5 | 1493 | |
8e7a6db9 | 1494 | tcg_gen_xor_tl(cpu_ov, arg0, arg2); |
74637406 | 1495 | tcg_gen_xor_tl(t0, arg1, arg2); |
ffe30937 RH |
1496 | if (sub) { |
1497 | tcg_gen_and_tl(cpu_ov, cpu_ov, t0); | |
1498 | } else { | |
1499 | tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); | |
1500 | } | |
02765534 | 1501 | if (NARROW_MODE(ctx)) { |
dc0ad844 ND |
1502 | tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); |
1503 | if (is_isa300(ctx)) { | |
1504 | tcg_gen_mov_tl(cpu_ov32, cpu_ov); | |
1505 | } | |
1506 | } else { | |
1507 | if (is_isa300(ctx)) { | |
1508 | tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); | |
1509 | } | |
38a61d34 | 1510 | tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); |
ffe30937 | 1511 | } |
ffe30937 | 1512 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); |
79aceca5 FB |
1513 | } |
1514 | ||
6b10d008 ND |
1515 | static inline void gen_op_arith_compute_ca32(DisasContext *ctx, |
1516 | TCGv res, TCGv arg0, TCGv arg1, | |
4c5920af | 1517 | TCGv ca32, int sub) |
6b10d008 ND |
1518 | { |
1519 | TCGv t0; | |
1520 | ||
1521 | if (!is_isa300(ctx)) { | |
1522 | return; | |
1523 | } | |
1524 | ||
1525 | t0 = tcg_temp_new(); | |
33903d0a ND |
1526 | if (sub) { |
1527 | tcg_gen_eqv_tl(t0, arg0, arg1); | |
1528 | } else { | |
1529 | tcg_gen_xor_tl(t0, arg0, arg1); | |
1530 | } | |
6b10d008 | 1531 | tcg_gen_xor_tl(t0, t0, res); |
4c5920af | 1532 | tcg_gen_extract_tl(ca32, t0, 32, 1); |
6b10d008 ND |
1533 | } |
1534 | ||
74637406 | 1535 | /* Common add function */ |
636aa200 | 1536 | static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
4c5920af SJS |
1537 | TCGv arg2, TCGv ca, TCGv ca32, |
1538 | bool add_ca, bool compute_ca, | |
b5a73f8d | 1539 | bool compute_ov, bool compute_rc0) |
74637406 | 1540 | { |
b5a73f8d | 1541 | TCGv t0 = ret; |
d9bce9d9 | 1542 | |
752d634e | 1543 | if (compute_ca || compute_ov) { |
146de60d | 1544 | t0 = tcg_temp_new(); |
74637406 | 1545 | } |
79aceca5 | 1546 | |
da91a00f | 1547 | if (compute_ca) { |
79482e5a | 1548 | if (NARROW_MODE(ctx)) { |
efe843d8 DG |
1549 | /* |
1550 | * Caution: a non-obvious corner case of the spec is that | |
1551 | * we must produce the *entire* 64-bit addition, but | |
1552 | * produce the carry into bit 32. | |
1553 | */ | |
79482e5a | 1554 | TCGv t1 = tcg_temp_new(); |
752d634e RH |
1555 | tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ |
1556 | tcg_gen_add_tl(t0, arg1, arg2); | |
79482e5a | 1557 | if (add_ca) { |
4c5920af | 1558 | tcg_gen_add_tl(t0, t0, ca); |
79482e5a | 1559 | } |
4c5920af | 1560 | tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ |
4c5920af | 1561 | tcg_gen_extract_tl(ca, ca, 32, 1); |
6b10d008 | 1562 | if (is_isa300(ctx)) { |
4c5920af | 1563 | tcg_gen_mov_tl(ca32, ca); |
6b10d008 | 1564 | } |
b5a73f8d | 1565 | } else { |
7058ff52 | 1566 | TCGv zero = tcg_constant_tl(0); |
79482e5a | 1567 | if (add_ca) { |
4c5920af SJS |
1568 | tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); |
1569 | tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); | |
79482e5a | 1570 | } else { |
4c5920af | 1571 | tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); |
79482e5a | 1572 | } |
4c5920af | 1573 | gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); |
b5a73f8d | 1574 | } |
b5a73f8d RH |
1575 | } else { |
1576 | tcg_gen_add_tl(t0, arg1, arg2); | |
1577 | if (add_ca) { | |
4c5920af | 1578 | tcg_gen_add_tl(t0, t0, ca); |
b5a73f8d | 1579 | } |
da91a00f | 1580 | } |
79aceca5 | 1581 | |
74637406 AJ |
1582 | if (compute_ov) { |
1583 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); | |
1584 | } | |
b5a73f8d | 1585 | if (unlikely(compute_rc0)) { |
74637406 | 1586 | gen_set_Rc0(ctx, t0); |
b5a73f8d | 1587 | } |
74637406 | 1588 | |
11f4e8f8 | 1589 | if (t0 != ret) { |
74637406 | 1590 | tcg_gen_mov_tl(ret, t0); |
74637406 | 1591 | } |
39dd32ee | 1592 | } |
74637406 | 1593 | /* Add functions with two operands */ |
4c5920af | 1594 | #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ |
b5a73f8d | 1595 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
1596 | { \ |
1597 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1598 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
4c5920af | 1599 | ca, glue(ca, 32), \ |
b5a73f8d | 1600 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
1601 | } |
1602 | /* Add functions with one operand and one immediate */ | |
4c5920af | 1603 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ |
74637406 | 1604 | add_ca, compute_ca, compute_ov) \ |
b5a73f8d | 1605 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 1606 | { \ |
7058ff52 | 1607 | TCGv t0 = tcg_constant_tl(const_val); \ |
74637406 AJ |
1608 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1609 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
4c5920af | 1610 | ca, glue(ca, 32), \ |
b5a73f8d | 1611 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
1612 | } |
1613 | ||
1614 | /* add add. addo addo. */ | |
4c5920af SJS |
1615 | GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) |
1616 | GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) | |
74637406 | 1617 | /* addc addc. addco addco. */ |
4c5920af SJS |
1618 | GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) |
1619 | GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) | |
74637406 | 1620 | /* adde adde. addeo addeo. */ |
4c5920af SJS |
1621 | GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) |
1622 | GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) | |
74637406 | 1623 | /* addme addme. addmeo addmeo. */ |
4c5920af SJS |
1624 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) |
1625 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) | |
1626 | /* addex */ | |
1627 | GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); | |
74637406 | 1628 | /* addze addze. addzeo addzeo.*/ |
4c5920af SJS |
1629 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) |
1630 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) | |
74637406 | 1631 | /* addic addic.*/ |
b5a73f8d | 1632 | static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) |
d9bce9d9 | 1633 | { |
7058ff52 | 1634 | TCGv c = tcg_constant_tl(SIMM(ctx->opcode)); |
b5a73f8d | 1635 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
4c5920af | 1636 | c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); |
d9bce9d9 | 1637 | } |
99e300ef BS |
1638 | |
1639 | static void gen_addic(DisasContext *ctx) | |
d9bce9d9 | 1640 | { |
b5a73f8d | 1641 | gen_op_addic(ctx, 0); |
d9bce9d9 | 1642 | } |
e8eaa2c0 BS |
1643 | |
1644 | static void gen_addic_(DisasContext *ctx) | |
d9bce9d9 | 1645 | { |
b5a73f8d | 1646 | gen_op_addic(ctx, 1); |
d9bce9d9 | 1647 | } |
99e300ef | 1648 | |
636aa200 BS |
1649 | static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, |
1650 | TCGv arg2, int sign, int compute_ov) | |
d9bce9d9 | 1651 | { |
b07c32dc ND |
1652 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1653 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
1654 | TCGv_i32 t2 = tcg_temp_new_i32(); | |
1655 | TCGv_i32 t3 = tcg_temp_new_i32(); | |
74637406 | 1656 | |
2ef1b120 AJ |
1657 | tcg_gen_trunc_tl_i32(t0, arg1); |
1658 | tcg_gen_trunc_tl_i32(t1, arg2); | |
74637406 | 1659 | if (sign) { |
b07c32dc ND |
1660 | tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); |
1661 | tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); | |
1662 | tcg_gen_and_i32(t2, t2, t3); | |
1663 | tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); | |
1664 | tcg_gen_or_i32(t2, t2, t3); | |
1665 | tcg_gen_movi_i32(t3, 0); | |
1666 | tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1667 | tcg_gen_div_i32(t3, t0, t1); | |
1668 | tcg_gen_extu_i32_tl(ret, t3); | |
74637406 | 1669 | } else { |
b07c32dc ND |
1670 | tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); |
1671 | tcg_gen_movi_i32(t3, 0); | |
1672 | tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1673 | tcg_gen_divu_i32(t3, t0, t1); | |
1674 | tcg_gen_extu_i32_tl(ret, t3); | |
74637406 AJ |
1675 | } |
1676 | if (compute_ov) { | |
b07c32dc | 1677 | tcg_gen_extu_i32_tl(cpu_ov, t2); |
c44027ff ND |
1678 | if (is_isa300(ctx)) { |
1679 | tcg_gen_extu_i32_tl(cpu_ov32, t2); | |
1680 | } | |
b07c32dc | 1681 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); |
74637406 | 1682 | } |
b07c32dc | 1683 | |
efe843d8 | 1684 | if (unlikely(Rc(ctx->opcode) != 0)) { |
74637406 | 1685 | gen_set_Rc0(ctx, ret); |
efe843d8 | 1686 | } |
d9bce9d9 | 1687 | } |
74637406 AJ |
1688 | /* Div functions */ |
1689 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ | |
efe843d8 | 1690 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
1691 | { \ |
1692 | gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1693 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1694 | sign, compute_ov); \ | |
1695 | } | |
1696 | /* divwu divwu. divwuo divwuo. */ | |
1697 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); | |
1698 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); | |
1699 | /* divw divw. divwo divwo. */ | |
1700 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); | |
1701 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); | |
98d1eb27 TM |
1702 | |
1703 | /* div[wd]eu[o][.] */ | |
1704 | #define GEN_DIVE(name, hlpr, compute_ov) \ | |
1705 | static void gen_##name(DisasContext *ctx) \ | |
1706 | { \ | |
7058ff52 | 1707 | TCGv_i32 t0 = tcg_constant_i32(compute_ov); \ |
98d1eb27 TM |
1708 | gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ |
1709 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ | |
98d1eb27 TM |
1710 | if (unlikely(Rc(ctx->opcode) != 0)) { \ |
1711 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ | |
1712 | } \ | |
1713 | } | |
1714 | ||
6a4fda33 TM |
1715 | GEN_DIVE(divweu, divweu, 0); |
1716 | GEN_DIVE(divweuo, divweu, 1); | |
a98eb9e9 TM |
1717 | GEN_DIVE(divwe, divwe, 0); |
1718 | GEN_DIVE(divweo, divwe, 1); | |
6a4fda33 | 1719 | |
d9bce9d9 | 1720 | #if defined(TARGET_PPC64) |
636aa200 BS |
1721 | static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, |
1722 | TCGv arg2, int sign, int compute_ov) | |
d9bce9d9 | 1723 | { |
4110b586 ND |
1724 | TCGv_i64 t0 = tcg_temp_new_i64(); |
1725 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1726 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1727 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
74637406 | 1728 | |
4110b586 ND |
1729 | tcg_gen_mov_i64(t0, arg1); |
1730 | tcg_gen_mov_i64(t1, arg2); | |
74637406 | 1731 | if (sign) { |
4110b586 ND |
1732 | tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); |
1733 | tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); | |
1734 | tcg_gen_and_i64(t2, t2, t3); | |
1735 | tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); | |
1736 | tcg_gen_or_i64(t2, t2, t3); | |
1737 | tcg_gen_movi_i64(t3, 0); | |
1738 | tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1739 | tcg_gen_div_i64(ret, t0, t1); | |
74637406 | 1740 | } else { |
4110b586 ND |
1741 | tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); |
1742 | tcg_gen_movi_i64(t3, 0); | |
1743 | tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1744 | tcg_gen_divu_i64(ret, t0, t1); | |
74637406 AJ |
1745 | } |
1746 | if (compute_ov) { | |
4110b586 | 1747 | tcg_gen_mov_tl(cpu_ov, t2); |
c44027ff ND |
1748 | if (is_isa300(ctx)) { |
1749 | tcg_gen_mov_tl(cpu_ov32, t2); | |
1750 | } | |
4110b586 | 1751 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); |
74637406 | 1752 | } |
4110b586 | 1753 | |
efe843d8 | 1754 | if (unlikely(Rc(ctx->opcode) != 0)) { |
74637406 | 1755 | gen_set_Rc0(ctx, ret); |
efe843d8 | 1756 | } |
d9bce9d9 | 1757 | } |
4110b586 | 1758 | |
74637406 | 1759 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ |
efe843d8 | 1760 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 1761 | { \ |
2ef1b120 AJ |
1762 | gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1763 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1764 | sign, compute_ov); \ | |
74637406 | 1765 | } |
c44027ff | 1766 | /* divdu divdu. divduo divduo. */ |
74637406 AJ |
1767 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); |
1768 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); | |
c44027ff | 1769 | /* divd divd. divdo divdo. */ |
74637406 AJ |
1770 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); |
1771 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); | |
98d1eb27 TM |
1772 | |
1773 | GEN_DIVE(divdeu, divdeu, 0); | |
1774 | GEN_DIVE(divdeuo, divdeu, 1); | |
e44259b6 TM |
1775 | GEN_DIVE(divde, divde, 0); |
1776 | GEN_DIVE(divdeo, divde, 1); | |
d9bce9d9 | 1777 | #endif |
74637406 | 1778 | |
af2c6620 ND |
1779 | static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, |
1780 | TCGv arg2, int sign) | |
1781 | { | |
1782 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
1783 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
1784 | ||
1785 | tcg_gen_trunc_tl_i32(t0, arg1); | |
1786 | tcg_gen_trunc_tl_i32(t1, arg2); | |
1787 | if (sign) { | |
1788 | TCGv_i32 t2 = tcg_temp_new_i32(); | |
1789 | TCGv_i32 t3 = tcg_temp_new_i32(); | |
1790 | tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); | |
1791 | tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); | |
1792 | tcg_gen_and_i32(t2, t2, t3); | |
1793 | tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); | |
1794 | tcg_gen_or_i32(t2, t2, t3); | |
1795 | tcg_gen_movi_i32(t3, 0); | |
1796 | tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1797 | tcg_gen_rem_i32(t3, t0, t1); | |
1798 | tcg_gen_ext_i32_tl(ret, t3); | |
af2c6620 | 1799 | } else { |
7058ff52 RH |
1800 | TCGv_i32 t2 = tcg_constant_i32(1); |
1801 | TCGv_i32 t3 = tcg_constant_i32(0); | |
af2c6620 | 1802 | tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); |
a253231f RH |
1803 | tcg_gen_remu_i32(t0, t0, t1); |
1804 | tcg_gen_extu_i32_tl(ret, t0); | |
af2c6620 | 1805 | } |
af2c6620 ND |
1806 | } |
1807 | ||
1808 | #define GEN_INT_ARITH_MODW(name, opc3, sign) \ | |
1809 | static void glue(gen_, name)(DisasContext *ctx) \ | |
1810 | { \ | |
1811 | gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1812 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1813 | sign); \ | |
1814 | } | |
1815 | ||
1816 | GEN_INT_ARITH_MODW(moduw, 0x08, 0); | |
1817 | GEN_INT_ARITH_MODW(modsw, 0x18, 1); | |
1818 | ||
063cf14f ND |
1819 | #if defined(TARGET_PPC64) |
1820 | static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, | |
1821 | TCGv arg2, int sign) | |
1822 | { | |
1823 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
1824 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1825 | ||
1826 | tcg_gen_mov_i64(t0, arg1); | |
1827 | tcg_gen_mov_i64(t1, arg2); | |
1828 | if (sign) { | |
1829 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1830 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
1831 | tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); | |
1832 | tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); | |
1833 | tcg_gen_and_i64(t2, t2, t3); | |
1834 | tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); | |
1835 | tcg_gen_or_i64(t2, t2, t3); | |
1836 | tcg_gen_movi_i64(t3, 0); | |
1837 | tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1838 | tcg_gen_rem_i64(ret, t0, t1); | |
063cf14f | 1839 | } else { |
7058ff52 RH |
1840 | TCGv_i64 t2 = tcg_constant_i64(1); |
1841 | TCGv_i64 t3 = tcg_constant_i64(0); | |
063cf14f ND |
1842 | tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); |
1843 | tcg_gen_remu_i64(ret, t0, t1); | |
063cf14f | 1844 | } |
063cf14f ND |
1845 | } |
1846 | ||
1847 | #define GEN_INT_ARITH_MODD(name, opc3, sign) \ | |
1848 | static void glue(gen_, name)(DisasContext *ctx) \ | |
1849 | { \ | |
1850 | gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1851 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1852 | sign); \ | |
1853 | } | |
1854 | ||
1855 | GEN_INT_ARITH_MODD(modud, 0x08, 0); | |
1856 | GEN_INT_ARITH_MODD(modsd, 0x18, 1); | |
1857 | #endif | |
1858 | ||
74637406 | 1859 | /* mulhw mulhw. */ |
99e300ef | 1860 | static void gen_mulhw(DisasContext *ctx) |
d9bce9d9 | 1861 | { |
23ad1d5d RH |
1862 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1863 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1864 | |
23ad1d5d RH |
1865 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1866 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1867 | tcg_gen_muls2_i32(t0, t1, t0, t1); | |
1868 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
efe843d8 | 1869 | if (unlikely(Rc(ctx->opcode) != 0)) { |
74637406 | 1870 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
efe843d8 | 1871 | } |
d9bce9d9 | 1872 | } |
99e300ef | 1873 | |
54623277 | 1874 | /* mulhwu mulhwu. */ |
99e300ef | 1875 | static void gen_mulhwu(DisasContext *ctx) |
d9bce9d9 | 1876 | { |
23ad1d5d RH |
1877 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1878 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1879 | |
23ad1d5d RH |
1880 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1881 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1882 | tcg_gen_mulu2_i32(t0, t1, t0, t1); | |
1883 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
efe843d8 | 1884 | if (unlikely(Rc(ctx->opcode) != 0)) { |
74637406 | 1885 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
efe843d8 | 1886 | } |
d9bce9d9 | 1887 | } |
99e300ef | 1888 | |
54623277 | 1889 | /* mullw mullw. */ |
99e300ef | 1890 | static void gen_mullw(DisasContext *ctx) |
d9bce9d9 | 1891 | { |
1fa74845 TM |
1892 | #if defined(TARGET_PPC64) |
1893 | TCGv_i64 t0, t1; | |
1894 | t0 = tcg_temp_new_i64(); | |
1895 | t1 = tcg_temp_new_i64(); | |
1896 | tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); | |
1897 | tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); | |
1898 | tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
1fa74845 | 1899 | #else |
03039e5e TM |
1900 | tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1901 | cpu_gpr[rB(ctx->opcode)]); | |
1fa74845 | 1902 | #endif |
efe843d8 | 1903 | if (unlikely(Rc(ctx->opcode) != 0)) { |
74637406 | 1904 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
efe843d8 | 1905 | } |
d9bce9d9 | 1906 | } |
99e300ef | 1907 | |
54623277 | 1908 | /* mullwo mullwo. */ |
99e300ef | 1909 | static void gen_mullwo(DisasContext *ctx) |
d9bce9d9 | 1910 | { |
e4a2c846 RH |
1911 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1912 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1913 | |
e4a2c846 RH |
1914 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1915 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1916 | tcg_gen_muls2_i32(t0, t1, t0, t1); | |
f11ebbf8 | 1917 | #if defined(TARGET_PPC64) |
26977876 TM |
1918 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); |
1919 | #else | |
1920 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); | |
f11ebbf8 | 1921 | #endif |
e4a2c846 RH |
1922 | |
1923 | tcg_gen_sari_i32(t0, t0, 31); | |
1924 | tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); | |
1925 | tcg_gen_extu_i32_tl(cpu_ov, t0); | |
61aa9a69 ND |
1926 | if (is_isa300(ctx)) { |
1927 | tcg_gen_mov_tl(cpu_ov32, cpu_ov); | |
1928 | } | |
e4a2c846 RH |
1929 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); |
1930 | ||
efe843d8 | 1931 | if (unlikely(Rc(ctx->opcode) != 0)) { |
74637406 | 1932 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
efe843d8 | 1933 | } |
d9bce9d9 | 1934 | } |
99e300ef | 1935 | |
54623277 | 1936 | /* mulli */ |
99e300ef | 1937 | static void gen_mulli(DisasContext *ctx) |
d9bce9d9 | 1938 | { |
74637406 AJ |
1939 | tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1940 | SIMM(ctx->opcode)); | |
d9bce9d9 | 1941 | } |
23ad1d5d | 1942 | |
d9bce9d9 | 1943 | #if defined(TARGET_PPC64) |
74637406 | 1944 | /* mulhd mulhd. */ |
23ad1d5d RH |
1945 | static void gen_mulhd(DisasContext *ctx) |
1946 | { | |
1947 | TCGv lo = tcg_temp_new(); | |
1948 | tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], | |
1949 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
23ad1d5d RH |
1950 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1951 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1952 | } | |
1953 | } | |
1954 | ||
74637406 | 1955 | /* mulhdu mulhdu. */ |
23ad1d5d RH |
1956 | static void gen_mulhdu(DisasContext *ctx) |
1957 | { | |
1958 | TCGv lo = tcg_temp_new(); | |
1959 | tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], | |
1960 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
23ad1d5d RH |
1961 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1962 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1963 | } | |
1964 | } | |
99e300ef | 1965 | |
54623277 | 1966 | /* mulld mulld. */ |
99e300ef | 1967 | static void gen_mulld(DisasContext *ctx) |
d9bce9d9 | 1968 | { |
74637406 AJ |
1969 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1970 | cpu_gpr[rB(ctx->opcode)]); | |
efe843d8 | 1971 | if (unlikely(Rc(ctx->opcode) != 0)) { |
74637406 | 1972 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
efe843d8 | 1973 | } |
d9bce9d9 | 1974 | } |
d15f74fb | 1975 | |
74637406 | 1976 | /* mulldo mulldo. */ |
d15f74fb BS |
1977 | static void gen_mulldo(DisasContext *ctx) |
1978 | { | |
22ffad31 TM |
1979 | TCGv_i64 t0 = tcg_temp_new_i64(); |
1980 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1981 | ||
1982 | tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], | |
1983 | cpu_gpr[rB(ctx->opcode)]); | |
1984 | tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); | |
1985 | ||
1986 | tcg_gen_sari_i64(t0, t0, 63); | |
1987 | tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); | |
61aa9a69 ND |
1988 | if (is_isa300(ctx)) { |
1989 | tcg_gen_mov_tl(cpu_ov32, cpu_ov); | |
1990 | } | |
22ffad31 TM |
1991 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); |
1992 | ||
d15f74fb BS |
1993 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1994 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1995 | } | |
1996 | } | |
d9bce9d9 | 1997 | #endif |
74637406 | 1998 | |
74637406 | 1999 | /* Common subf function */ |
636aa200 | 2000 | static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, |
b5a73f8d RH |
2001 | TCGv arg2, bool add_ca, bool compute_ca, |
2002 | bool compute_ov, bool compute_rc0) | |
79aceca5 | 2003 | { |
b5a73f8d | 2004 | TCGv t0 = ret; |
79aceca5 | 2005 | |
752d634e | 2006 | if (compute_ca || compute_ov) { |
b5a73f8d | 2007 | t0 = tcg_temp_new(); |
da91a00f | 2008 | } |
74637406 | 2009 | |
79482e5a RH |
2010 | if (compute_ca) { |
2011 | /* dest = ~arg1 + arg2 [+ ca]. */ | |
2012 | if (NARROW_MODE(ctx)) { | |
efe843d8 DG |
2013 | /* |
2014 | * Caution: a non-obvious corner case of the spec is that | |
2015 | * we must produce the *entire* 64-bit addition, but | |
2016 | * produce the carry into bit 32. | |
2017 | */ | |
79482e5a | 2018 | TCGv inv1 = tcg_temp_new(); |
752d634e | 2019 | TCGv t1 = tcg_temp_new(); |
79482e5a | 2020 | tcg_gen_not_tl(inv1, arg1); |
79482e5a | 2021 | if (add_ca) { |
752d634e | 2022 | tcg_gen_add_tl(t0, arg2, cpu_ca); |
79482e5a | 2023 | } else { |
752d634e | 2024 | tcg_gen_addi_tl(t0, arg2, 1); |
79482e5a | 2025 | } |
752d634e | 2026 | tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ |
79482e5a | 2027 | tcg_gen_add_tl(t0, t0, inv1); |
752d634e | 2028 | tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ |
e2622073 | 2029 | tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); |
33903d0a ND |
2030 | if (is_isa300(ctx)) { |
2031 | tcg_gen_mov_tl(cpu_ca32, cpu_ca); | |
2032 | } | |
79482e5a | 2033 | } else if (add_ca) { |
08f4a0f7 RH |
2034 | TCGv zero, inv1 = tcg_temp_new(); |
2035 | tcg_gen_not_tl(inv1, arg1); | |
7058ff52 | 2036 | zero = tcg_constant_tl(0); |
b5a73f8d | 2037 | tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); |
08f4a0f7 | 2038 | tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); |
4c5920af | 2039 | gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); |
b5a73f8d | 2040 | } else { |
79482e5a | 2041 | tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); |
b5a73f8d | 2042 | tcg_gen_sub_tl(t0, arg2, arg1); |
4c5920af | 2043 | gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); |
b5a73f8d | 2044 | } |
79482e5a | 2045 | } else if (add_ca) { |
efe843d8 DG |
2046 | /* |
2047 | * Since we're ignoring carry-out, we can simplify the | |
2048 | * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. | |
2049 | */ | |
79482e5a RH |
2050 | tcg_gen_sub_tl(t0, arg2, arg1); |
2051 | tcg_gen_add_tl(t0, t0, cpu_ca); | |
2052 | tcg_gen_subi_tl(t0, t0, 1); | |
79aceca5 | 2053 | } else { |
b5a73f8d | 2054 | tcg_gen_sub_tl(t0, arg2, arg1); |
74637406 | 2055 | } |
b5a73f8d | 2056 | |
74637406 AJ |
2057 | if (compute_ov) { |
2058 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); | |
2059 | } | |
b5a73f8d | 2060 | if (unlikely(compute_rc0)) { |
74637406 | 2061 | gen_set_Rc0(ctx, t0); |
b5a73f8d | 2062 | } |
74637406 | 2063 | |
11f4e8f8 | 2064 | if (t0 != ret) { |
74637406 | 2065 | tcg_gen_mov_tl(ret, t0); |
79aceca5 | 2066 | } |
79aceca5 | 2067 | } |
74637406 AJ |
2068 | /* Sub functions with Two operands functions */ |
2069 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 2070 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
2071 | { \ |
2072 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
2073 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
b5a73f8d | 2074 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
2075 | } |
2076 | /* Sub functions with one operand and one immediate */ | |
2077 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ | |
2078 | add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 2079 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 2080 | { \ |
7058ff52 | 2081 | TCGv t0 = tcg_constant_tl(const_val); \ |
74637406 AJ |
2082 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ |
2083 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
b5a73f8d | 2084 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
2085 | } |
2086 | /* subf subf. subfo subfo. */ | |
2087 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) | |
2088 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) | |
2089 | /* subfc subfc. subfco subfco. */ | |
2090 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) | |
2091 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) | |
2092 | /* subfe subfe. subfeo subfo. */ | |
2093 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) | |
2094 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) | |
2095 | /* subfme subfme. subfmeo subfmeo. */ | |
2096 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) | |
2097 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) | |
2098 | /* subfze subfze. subfzeo subfzeo.*/ | |
2099 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) | |
2100 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) | |
99e300ef | 2101 | |
54623277 | 2102 | /* subfic */ |
99e300ef | 2103 | static void gen_subfic(DisasContext *ctx) |
79aceca5 | 2104 | { |
7058ff52 | 2105 | TCGv c = tcg_constant_tl(SIMM(ctx->opcode)); |
b5a73f8d RH |
2106 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
2107 | c, 0, 1, 0, 0); | |
79aceca5 FB |
2108 | } |
2109 | ||
fd3f0081 RH |
2110 | /* neg neg. nego nego. */ |
2111 | static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) | |
2112 | { | |
7058ff52 | 2113 | TCGv zero = tcg_constant_tl(0); |
fd3f0081 RH |
2114 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
2115 | zero, 0, 0, compute_ov, Rc(ctx->opcode)); | |
fd3f0081 RH |
2116 | } |
2117 | ||
2118 | static void gen_neg(DisasContext *ctx) | |
2119 | { | |
1480d71c ND |
2120 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
2121 | if (unlikely(Rc(ctx->opcode))) { | |
2122 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
2123 | } | |
fd3f0081 RH |
2124 | } |
2125 | ||
2126 | static void gen_nego(DisasContext *ctx) | |
2127 | { | |
2128 | gen_op_arith_neg(ctx, 1); | |
2129 | } | |
2130 | ||
79aceca5 | 2131 | /*** Integer logical ***/ |
26d67362 | 2132 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ |
efe843d8 | 2133 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 2134 | { \ |
26d67362 AJ |
2135 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ |
2136 | cpu_gpr[rB(ctx->opcode)]); \ | |
76a66253 | 2137 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
26d67362 | 2138 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
79aceca5 | 2139 | } |
79aceca5 | 2140 | |
26d67362 | 2141 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ |
efe843d8 | 2142 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 2143 | { \ |
26d67362 | 2144 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ |
76a66253 | 2145 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
26d67362 | 2146 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
79aceca5 FB |
2147 | } |
2148 | ||
2149 | /* and & and. */ | |
26d67362 | 2150 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); |
79aceca5 | 2151 | /* andc & andc. */ |
26d67362 | 2152 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); |
e8eaa2c0 | 2153 | |
54623277 | 2154 | /* andi. */ |
e8eaa2c0 | 2155 | static void gen_andi_(DisasContext *ctx) |
79aceca5 | 2156 | { |
efe843d8 DG |
2157 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], |
2158 | UIMM(ctx->opcode)); | |
26d67362 | 2159 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 | 2160 | } |
e8eaa2c0 | 2161 | |
54623277 | 2162 | /* andis. */ |
e8eaa2c0 | 2163 | static void gen_andis_(DisasContext *ctx) |
79aceca5 | 2164 | { |
efe843d8 DG |
2165 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], |
2166 | UIMM(ctx->opcode) << 16); | |
26d67362 | 2167 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 | 2168 | } |
99e300ef | 2169 | |
54623277 | 2170 | /* cntlzw */ |
99e300ef | 2171 | static void gen_cntlzw(DisasContext *ctx) |
26d67362 | 2172 | { |
9b8514e5 RH |
2173 | TCGv_i32 t = tcg_temp_new_i32(); |
2174 | ||
2175 | tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); | |
2176 | tcg_gen_clzi_i32(t, t, 32); | |
2177 | tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); | |
9b8514e5 | 2178 | |
efe843d8 | 2179 | if (unlikely(Rc(ctx->opcode) != 0)) { |
2e31f5d3 | 2180 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 2181 | } |
26d67362 | 2182 | } |
b35344e4 ND |
2183 | |
2184 | /* cnttzw */ | |
2185 | static void gen_cnttzw(DisasContext *ctx) | |
2186 | { | |
9b8514e5 RH |
2187 | TCGv_i32 t = tcg_temp_new_i32(); |
2188 | ||
2189 | tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); | |
2190 | tcg_gen_ctzi_i32(t, t, 32); | |
2191 | tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); | |
9b8514e5 | 2192 | |
b35344e4 ND |
2193 | if (unlikely(Rc(ctx->opcode) != 0)) { |
2194 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2195 | } | |
2196 | } | |
2197 | ||
79aceca5 | 2198 | /* eqv & eqv. */ |
26d67362 | 2199 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); |
79aceca5 | 2200 | /* extsb & extsb. */ |
26d67362 | 2201 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); |
79aceca5 | 2202 | /* extsh & extsh. */ |
26d67362 | 2203 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); |
79aceca5 | 2204 | /* nand & nand. */ |
26d67362 | 2205 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); |
79aceca5 | 2206 | /* nor & nor. */ |
26d67362 | 2207 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); |
99e300ef | 2208 | |
7f2b1744 | 2209 | #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) |
b68e60e6 BH |
2210 | static void gen_pause(DisasContext *ctx) |
2211 | { | |
7058ff52 | 2212 | TCGv_i32 t0 = tcg_constant_i32(0); |
b68e60e6 BH |
2213 | tcg_gen_st_i32(t0, cpu_env, |
2214 | -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); | |
b68e60e6 BH |
2215 | |
2216 | /* Stop translation, this gives other CPUs a chance to run */ | |
b6bac4bc | 2217 | gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); |
b68e60e6 BH |
2218 | } |
2219 | #endif /* defined(TARGET_PPC64) */ | |
2220 | ||
54623277 | 2221 | /* or & or. */ |
99e300ef | 2222 | static void gen_or(DisasContext *ctx) |
9a64fbe4 | 2223 | { |
76a66253 JM |
2224 | int rs, ra, rb; |
2225 | ||
2226 | rs = rS(ctx->opcode); | |
2227 | ra = rA(ctx->opcode); | |
2228 | rb = rB(ctx->opcode); | |
2229 | /* Optimisation for mr. ri case */ | |
2230 | if (rs != ra || rs != rb) { | |
efe843d8 | 2231 | if (rs != rb) { |
26d67362 | 2232 | tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); |
efe843d8 | 2233 | } else { |
26d67362 | 2234 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); |
efe843d8 DG |
2235 | } |
2236 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
26d67362 | 2237 | gen_set_Rc0(ctx, cpu_gpr[ra]); |
efe843d8 | 2238 | } |
76a66253 | 2239 | } else if (unlikely(Rc(ctx->opcode) != 0)) { |
26d67362 | 2240 | gen_set_Rc0(ctx, cpu_gpr[rs]); |
c80f84e3 | 2241 | #if defined(TARGET_PPC64) |
9e196938 | 2242 | } else if (rs != 0) { /* 0 is nop */ |
26d67362 AJ |
2243 | int prio = 0; |
2244 | ||
c80f84e3 JM |
2245 | switch (rs) { |
2246 | case 1: | |
2247 | /* Set process priority to low */ | |
26d67362 | 2248 | prio = 2; |
c80f84e3 JM |
2249 | break; |
2250 | case 6: | |
2251 | /* Set process priority to medium-low */ | |
26d67362 | 2252 | prio = 3; |
c80f84e3 JM |
2253 | break; |
2254 | case 2: | |
2255 | /* Set process priority to normal */ | |
26d67362 | 2256 | prio = 4; |
c80f84e3 | 2257 | break; |
be147d08 JM |
2258 | #if !defined(CONFIG_USER_ONLY) |
2259 | case 31: | |
c47493f2 | 2260 | if (!ctx->pr) { |
be147d08 | 2261 | /* Set process priority to very low */ |
26d67362 | 2262 | prio = 1; |
be147d08 JM |
2263 | } |
2264 | break; | |
2265 | case 5: | |
c47493f2 | 2266 | if (!ctx->pr) { |
be147d08 | 2267 | /* Set process priority to medium-hight */ |
26d67362 | 2268 | prio = 5; |
be147d08 JM |
2269 | } |
2270 | break; | |
2271 | case 3: | |
c47493f2 | 2272 | if (!ctx->pr) { |
be147d08 | 2273 | /* Set process priority to high */ |
26d67362 | 2274 | prio = 6; |
be147d08 JM |
2275 | } |
2276 | break; | |
be147d08 | 2277 | case 7: |
b68e60e6 | 2278 | if (ctx->hv && !ctx->pr) { |
be147d08 | 2279 | /* Set process priority to very high */ |
26d67362 | 2280 | prio = 7; |
be147d08 JM |
2281 | } |
2282 | break; | |
be147d08 | 2283 | #endif |
c80f84e3 | 2284 | default: |
c80f84e3 JM |
2285 | break; |
2286 | } | |
26d67362 | 2287 | if (prio) { |
a7812ae4 | 2288 | TCGv t0 = tcg_temp_new(); |
54cdcae6 | 2289 | gen_load_spr(t0, SPR_PPR); |
ea363694 AJ |
2290 | tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); |
2291 | tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); | |
54cdcae6 | 2292 | gen_store_spr(SPR_PPR, t0); |
9e196938 | 2293 | } |
7f2b1744 | 2294 | #if !defined(CONFIG_USER_ONLY) |
efe843d8 DG |
2295 | /* |
2296 | * Pause out of TCG otherwise spin loops with smt_low eat too | |
2297 | * much CPU and the kernel hangs. This applies to all | |
2298 | * encodings other than no-op, e.g., miso(rs=26), yield(27), | |
2299 | * mdoio(29), mdoom(30), and all currently undefined. | |
9e196938 AL |
2300 | */ |
2301 | gen_pause(ctx); | |
7f2b1744 | 2302 | #endif |
c80f84e3 | 2303 | #endif |
9a64fbe4 | 2304 | } |
9a64fbe4 | 2305 | } |
79aceca5 | 2306 | /* orc & orc. */ |
26d67362 | 2307 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); |
99e300ef | 2308 | |
54623277 | 2309 | /* xor & xor. */ |
99e300ef | 2310 | static void gen_xor(DisasContext *ctx) |
9a64fbe4 | 2311 | { |
9a64fbe4 | 2312 | /* Optimisation for "set to zero" case */ |
efe843d8 DG |
2313 | if (rS(ctx->opcode) != rB(ctx->opcode)) { |
2314 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], | |
2315 | cpu_gpr[rB(ctx->opcode)]); | |
2316 | } else { | |
26d67362 | 2317 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); |
efe843d8 DG |
2318 | } |
2319 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
26d67362 | 2320 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 2321 | } |
9a64fbe4 | 2322 | } |
99e300ef | 2323 | |
54623277 | 2324 | /* ori */ |
99e300ef | 2325 | static void gen_ori(DisasContext *ctx) |
79aceca5 | 2326 | { |
76a66253 | 2327 | target_ulong uimm = UIMM(ctx->opcode); |
79aceca5 | 2328 | |
9a64fbe4 | 2329 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
9a64fbe4 | 2330 | return; |
76a66253 | 2331 | } |
26d67362 | 2332 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
79aceca5 | 2333 | } |
99e300ef | 2334 | |
54623277 | 2335 | /* oris */ |
99e300ef | 2336 | static void gen_oris(DisasContext *ctx) |
79aceca5 | 2337 | { |
76a66253 | 2338 | target_ulong uimm = UIMM(ctx->opcode); |
79aceca5 | 2339 | |
9a64fbe4 FB |
2340 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
2341 | /* NOP */ | |
2342 | return; | |
76a66253 | 2343 | } |
efe843d8 DG |
2344 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], |
2345 | uimm << 16); | |
79aceca5 | 2346 | } |
99e300ef | 2347 | |
54623277 | 2348 | /* xori */ |
99e300ef | 2349 | static void gen_xori(DisasContext *ctx) |
79aceca5 | 2350 | { |
76a66253 | 2351 | target_ulong uimm = UIMM(ctx->opcode); |
9a64fbe4 FB |
2352 | |
2353 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
2354 | /* NOP */ | |
2355 | return; | |
2356 | } | |
26d67362 | 2357 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
79aceca5 | 2358 | } |
99e300ef | 2359 | |
54623277 | 2360 | /* xoris */ |
99e300ef | 2361 | static void gen_xoris(DisasContext *ctx) |
79aceca5 | 2362 | { |
76a66253 | 2363 | target_ulong uimm = UIMM(ctx->opcode); |
9a64fbe4 FB |
2364 | |
2365 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
2366 | /* NOP */ | |
2367 | return; | |
2368 | } | |
efe843d8 DG |
2369 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], |
2370 | uimm << 16); | |
79aceca5 | 2371 | } |
99e300ef | 2372 | |
54623277 | 2373 | /* popcntb : PowerPC 2.03 specification */ |
99e300ef | 2374 | static void gen_popcntb(DisasContext *ctx) |
d9bce9d9 | 2375 | { |
eaabeef2 DG |
2376 | gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
2377 | } | |
2378 | ||
2379 | static void gen_popcntw(DisasContext *ctx) | |
2380 | { | |
79770002 | 2381 | #if defined(TARGET_PPC64) |
eaabeef2 | 2382 | gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
79770002 RH |
2383 | #else |
2384 | tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
2385 | #endif | |
eaabeef2 DG |
2386 | } |
2387 | ||
d9bce9d9 | 2388 | #if defined(TARGET_PPC64) |
eaabeef2 DG |
2389 | /* popcntd: PowerPC 2.06 specification */ |
2390 | static void gen_popcntd(DisasContext *ctx) | |
2391 | { | |
79770002 | 2392 | tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
d9bce9d9 | 2393 | } |
eaabeef2 | 2394 | #endif |
d9bce9d9 | 2395 | |
725bcec2 AJ |
2396 | /* prtyw: PowerPC 2.05 specification */ |
2397 | static void gen_prtyw(DisasContext *ctx) | |
2398 | { | |
2399 | TCGv ra = cpu_gpr[rA(ctx->opcode)]; | |
2400 | TCGv rs = cpu_gpr[rS(ctx->opcode)]; | |
2401 | TCGv t0 = tcg_temp_new(); | |
2402 | tcg_gen_shri_tl(t0, rs, 16); | |
2403 | tcg_gen_xor_tl(ra, rs, t0); | |
2404 | tcg_gen_shri_tl(t0, ra, 8); | |
2405 | tcg_gen_xor_tl(ra, ra, t0); | |
2406 | tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); | |
725bcec2 AJ |
2407 | } |
2408 | ||
2409 | #if defined(TARGET_PPC64) | |
2410 | /* prtyd: PowerPC 2.05 specification */ | |
2411 | static void gen_prtyd(DisasContext *ctx) | |
2412 | { | |
2413 | TCGv ra = cpu_gpr[rA(ctx->opcode)]; | |
2414 | TCGv rs = cpu_gpr[rS(ctx->opcode)]; | |
2415 | TCGv t0 = tcg_temp_new(); | |
2416 | tcg_gen_shri_tl(t0, rs, 32); | |
2417 | tcg_gen_xor_tl(ra, rs, t0); | |
2418 | tcg_gen_shri_tl(t0, ra, 16); | |
2419 | tcg_gen_xor_tl(ra, ra, t0); | |
2420 | tcg_gen_shri_tl(t0, ra, 8); | |
2421 | tcg_gen_xor_tl(ra, ra, t0); | |
2422 | tcg_gen_andi_tl(ra, ra, 1); | |
725bcec2 AJ |
2423 | } |
2424 | #endif | |
2425 | ||
86ba37ed TM |
2426 | #if defined(TARGET_PPC64) |
2427 | /* bpermd */ | |
2428 | static void gen_bpermd(DisasContext *ctx) | |
2429 | { | |
2430 | gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], | |
2431 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
2432 | } | |
2433 | #endif | |
2434 | ||
d9bce9d9 JM |
2435 | #if defined(TARGET_PPC64) |
2436 | /* extsw & extsw. */ | |
26d67362 | 2437 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); |
99e300ef | 2438 | |
54623277 | 2439 | /* cntlzd */ |
99e300ef | 2440 | static void gen_cntlzd(DisasContext *ctx) |
26d67362 | 2441 | { |
9b8514e5 | 2442 | tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); |
efe843d8 | 2443 | if (unlikely(Rc(ctx->opcode) != 0)) { |
26d67362 | 2444 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 2445 | } |
26d67362 | 2446 | } |
e91d95b2 SD |
2447 | |
2448 | /* cnttzd */ | |
2449 | static void gen_cnttzd(DisasContext *ctx) | |
2450 | { | |
9b8514e5 | 2451 | tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); |
e91d95b2 SD |
2452 | if (unlikely(Rc(ctx->opcode) != 0)) { |
2453 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2454 | } | |
2455 | } | |
fec5c62a RB |
2456 | |
2457 | /* darn */ | |
2458 | static void gen_darn(DisasContext *ctx) | |
2459 | { | |
2460 | int l = L(ctx->opcode); | |
2461 | ||
7e4357f6 | 2462 | if (l > 2) { |
fec5c62a | 2463 | tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); |
7e4357f6 | 2464 | } else { |
283a9177 | 2465 | translator_io_start(&ctx->base); |
7e4357f6 RH |
2466 | if (l == 0) { |
2467 | gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); | |
2468 | } else { | |
2469 | /* Return 64-bit random for both CRN and RRN */ | |
2470 | gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); | |
2471 | } | |
fec5c62a RB |
2472 | } |
2473 | } | |
d9bce9d9 JM |
2474 | #endif |
2475 | ||
79aceca5 | 2476 | /*** Integer rotate ***/ |
99e300ef | 2477 | |
54623277 | 2478 | /* rlwimi & rlwimi. */ |
99e300ef | 2479 | static void gen_rlwimi(DisasContext *ctx) |
79aceca5 | 2480 | { |
63ae0915 RH |
2481 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
2482 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
2483 | uint32_t sh = SH(ctx->opcode); | |
2484 | uint32_t mb = MB(ctx->opcode); | |
2485 | uint32_t me = ME(ctx->opcode); | |
2486 | ||
efe843d8 | 2487 | if (sh == (31 - me) && mb <= me) { |
63ae0915 | 2488 | tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); |
d03ef511 | 2489 | } else { |
d03ef511 | 2490 | target_ulong mask; |
c4f6a4a3 | 2491 | bool mask_in_32b = true; |
a7812ae4 | 2492 | TCGv t1; |
63ae0915 | 2493 | |
76a66253 | 2494 | #if defined(TARGET_PPC64) |
d03ef511 AJ |
2495 | mb += 32; |
2496 | me += 32; | |
76a66253 | 2497 | #endif |
d03ef511 | 2498 | mask = MASK(mb, me); |
63ae0915 | 2499 | |
c4f6a4a3 DB |
2500 | #if defined(TARGET_PPC64) |
2501 | if (mask > 0xffffffffu) { | |
2502 | mask_in_32b = false; | |
2503 | } | |
2504 | #endif | |
a7812ae4 | 2505 | t1 = tcg_temp_new(); |
c4f6a4a3 | 2506 | if (mask_in_32b) { |
2e11b15d RH |
2507 | TCGv_i32 t0 = tcg_temp_new_i32(); |
2508 | tcg_gen_trunc_tl_i32(t0, t_rs); | |
2509 | tcg_gen_rotli_i32(t0, t0, sh); | |
2510 | tcg_gen_extu_i32_tl(t1, t0); | |
2e11b15d RH |
2511 | } else { |
2512 | #if defined(TARGET_PPC64) | |
2513 | tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); | |
2514 | tcg_gen_rotli_i64(t1, t1, sh); | |
2515 | #else | |
2516 | g_assert_not_reached(); | |
2517 | #endif | |
2518 | } | |
63ae0915 RH |
2519 | |
2520 | tcg_gen_andi_tl(t1, t1, mask); | |
2521 | tcg_gen_andi_tl(t_ra, t_ra, ~mask); | |
2522 | tcg_gen_or_tl(t_ra, t_ra, t1); | |
d03ef511 | 2523 | } |
63ae0915 RH |
2524 | if (unlikely(Rc(ctx->opcode) != 0)) { |
2525 | gen_set_Rc0(ctx, t_ra); | |
2526 | } | |
79aceca5 | 2527 | } |
99e300ef | 2528 | |
54623277 | 2529 | /* rlwinm & rlwinm. */ |
99e300ef | 2530 | static void gen_rlwinm(DisasContext *ctx) |
79aceca5 | 2531 | { |
63ae0915 RH |
2532 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
2533 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
7b4d326f RH |
2534 | int sh = SH(ctx->opcode); |
2535 | int mb = MB(ctx->opcode); | |
2536 | int me = ME(ctx->opcode); | |
2537 | int len = me - mb + 1; | |
2538 | int rsh = (32 - sh) & 31; | |
2539 | ||
2540 | if (sh != 0 && len > 0 && me == (31 - sh)) { | |
2541 | tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); | |
2542 | } else if (me == 31 && rsh + len <= 32) { | |
2543 | tcg_gen_extract_tl(t_ra, t_rs, rsh, len); | |
d03ef511 | 2544 | } else { |
2e11b15d | 2545 | target_ulong mask; |
c4f6a4a3 | 2546 | bool mask_in_32b = true; |
76a66253 | 2547 | #if defined(TARGET_PPC64) |
d03ef511 AJ |
2548 | mb += 32; |
2549 | me += 32; | |
76a66253 | 2550 | #endif |
2e11b15d | 2551 | mask = MASK(mb, me); |
c4f6a4a3 DB |
2552 | #if defined(TARGET_PPC64) |
2553 | if (mask > 0xffffffffu) { | |
2554 | mask_in_32b = false; | |
2555 | } | |
2556 | #endif | |
2557 | if (mask_in_32b) { | |
94f040aa VC |
2558 | if (sh == 0) { |
2559 | tcg_gen_andi_tl(t_ra, t_rs, mask); | |
2560 | } else { | |
2561 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
2562 | tcg_gen_trunc_tl_i32(t0, t_rs); | |
2563 | tcg_gen_rotli_i32(t0, t0, sh); | |
2564 | tcg_gen_andi_i32(t0, t0, mask); | |
2565 | tcg_gen_extu_i32_tl(t_ra, t0); | |
94f040aa | 2566 | } |
2e11b15d RH |
2567 | } else { |
2568 | #if defined(TARGET_PPC64) | |
2569 | tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); | |
2570 | tcg_gen_rotli_i64(t_ra, t_ra, sh); | |
2571 | tcg_gen_andi_i64(t_ra, t_ra, mask); | |
2572 | #else | |
2573 | g_assert_not_reached(); | |
2574 | #endif | |
63ae0915 RH |
2575 | } |
2576 | } | |
2577 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2578 | gen_set_Rc0(ctx, t_ra); | |
d03ef511 | 2579 | } |
79aceca5 | 2580 | } |
99e300ef | 2581 | |
54623277 | 2582 | /* rlwnm & rlwnm. */ |
99e300ef | 2583 | static void gen_rlwnm(DisasContext *ctx) |
79aceca5 | 2584 | { |
63ae0915 RH |
2585 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
2586 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
2587 | TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; | |
2588 | uint32_t mb = MB(ctx->opcode); | |
2589 | uint32_t me = ME(ctx->opcode); | |
2e11b15d | 2590 | target_ulong mask; |
c4f6a4a3 | 2591 | bool mask_in_32b = true; |
57fca134 | 2592 | |
54843a58 | 2593 | #if defined(TARGET_PPC64) |
63ae0915 RH |
2594 | mb += 32; |
2595 | me += 32; | |
54843a58 | 2596 | #endif |
2e11b15d RH |
2597 | mask = MASK(mb, me); |
2598 | ||
c4f6a4a3 DB |
2599 | #if defined(TARGET_PPC64) |
2600 | if (mask > 0xffffffffu) { | |
2601 | mask_in_32b = false; | |
2602 | } | |
2603 | #endif | |
2604 | if (mask_in_32b) { | |
2e11b15d RH |
2605 | TCGv_i32 t0 = tcg_temp_new_i32(); |
2606 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
2607 | tcg_gen_trunc_tl_i32(t0, t_rb); | |
2608 | tcg_gen_trunc_tl_i32(t1, t_rs); | |
2609 | tcg_gen_andi_i32(t0, t0, 0x1f); | |
2610 | tcg_gen_rotl_i32(t1, t1, t0); | |
2611 | tcg_gen_extu_i32_tl(t_ra, t1); | |
2e11b15d RH |
2612 | } else { |
2613 | #if defined(TARGET_PPC64) | |
2614 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
2615 | tcg_gen_andi_i64(t0, t_rb, 0x1f); | |
2616 | tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); | |
2617 | tcg_gen_rotl_i64(t_ra, t_ra, t0); | |
2e11b15d RH |
2618 | #else |
2619 | g_assert_not_reached(); | |
2620 | #endif | |
2621 | } | |
57fca134 | 2622 | |
2e11b15d | 2623 | tcg_gen_andi_tl(t_ra, t_ra, mask); |
63ae0915 RH |
2624 | |
2625 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2626 | gen_set_Rc0(ctx, t_ra); | |
79aceca5 | 2627 | } |
79aceca5 FB |
2628 | } |
2629 | ||
d9bce9d9 JM |
2630 | #if defined(TARGET_PPC64) |
2631 | #define GEN_PPC64_R2(name, opc1, opc2) \ | |
e8eaa2c0 | 2632 | static void glue(gen_, name##0)(DisasContext *ctx) \ |
d9bce9d9 JM |
2633 | { \ |
2634 | gen_##name(ctx, 0); \ | |
2635 | } \ | |
e8eaa2c0 BS |
2636 | \ |
2637 | static void glue(gen_, name##1)(DisasContext *ctx) \ | |
d9bce9d9 JM |
2638 | { \ |
2639 | gen_##name(ctx, 1); \ | |
2640 | } | |
2641 | #define GEN_PPC64_R4(name, opc1, opc2) \ | |
e8eaa2c0 | 2642 | static void glue(gen_, name##0)(DisasContext *ctx) \ |
d9bce9d9 JM |
2643 | { \ |
2644 | gen_##name(ctx, 0, 0); \ | |
2645 | } \ | |
e8eaa2c0 BS |
2646 | \ |
2647 | static void glue(gen_, name##1)(DisasContext *ctx) \ | |
d9bce9d9 JM |
2648 | { \ |
2649 | gen_##name(ctx, 0, 1); \ | |
2650 | } \ | |
e8eaa2c0 BS |
2651 | \ |
2652 | static void glue(gen_, name##2)(DisasContext *ctx) \ | |
d9bce9d9 JM |
2653 | { \ |
2654 | gen_##name(ctx, 1, 0); \ | |
2655 | } \ | |
e8eaa2c0 BS |
2656 | \ |
2657 | static void glue(gen_, name##3)(DisasContext *ctx) \ | |
d9bce9d9 JM |
2658 | { \ |
2659 | gen_##name(ctx, 1, 1); \ | |
2660 | } | |
51789c41 | 2661 | |
a7b2c8b9 | 2662 | static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) |
51789c41 | 2663 | { |
a7b2c8b9 RH |
2664 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
2665 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
7b4d326f RH |
2666 | int len = me - mb + 1; |
2667 | int rsh = (64 - sh) & 63; | |
a7b2c8b9 | 2668 | |
7b4d326f RH |
2669 | if (sh != 0 && len > 0 && me == (63 - sh)) { |
2670 | tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); | |
2671 | } else if (me == 63 && rsh + len <= 64) { | |
2672 | tcg_gen_extract_tl(t_ra, t_rs, rsh, len); | |
d03ef511 | 2673 | } else { |
a7b2c8b9 RH |
2674 | tcg_gen_rotli_tl(t_ra, t_rs, sh); |
2675 | tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); | |
2676 | } | |
2677 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2678 | gen_set_Rc0(ctx, t_ra); | |
51789c41 | 2679 | } |
51789c41 | 2680 | } |
a7b2c8b9 | 2681 | |
d9bce9d9 | 2682 | /* rldicl - rldicl. */ |
636aa200 | 2683 | static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 2684 | { |
51789c41 | 2685 | uint32_t sh, mb; |
d9bce9d9 | 2686 | |
9d53c753 JM |
2687 | sh = SH(ctx->opcode) | (shn << 5); |
2688 | mb = MB(ctx->opcode) | (mbn << 5); | |
51789c41 | 2689 | gen_rldinm(ctx, mb, 63, sh); |
d9bce9d9 | 2690 | } |
51789c41 | 2691 | GEN_PPC64_R4(rldicl, 0x1E, 0x00); |
a7b2c8b9 | 2692 | |
d9bce9d9 | 2693 | /* rldicr - rldicr. */ |
636aa200 | 2694 | static inline void gen_rldicr(DisasContext *ctx, int men, int shn) |
d9bce9d9 | 2695 | { |
51789c41 | 2696 | uint32_t sh, me; |
d9bce9d9 | 2697 | |
9d53c753 JM |
2698 | sh = SH(ctx->opcode) | (shn << 5); |
2699 | me = MB(ctx->opcode) | (men << 5); | |
51789c41 | 2700 | gen_rldinm(ctx, 0, me, sh); |
d9bce9d9 | 2701 | } |
51789c41 | 2702 | GEN_PPC64_R4(rldicr, 0x1E, 0x02); |
a7b2c8b9 | 2703 | |
d9bce9d9 | 2704 | /* rldic - rldic. */ |
636aa200 | 2705 | static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 2706 | { |
51789c41 | 2707 | uint32_t sh, mb; |
d9bce9d9 | 2708 | |
9d53c753 JM |
2709 | sh = SH(ctx->opcode) | (shn << 5); |
2710 | mb = MB(ctx->opcode) | (mbn << 5); | |
51789c41 JM |
2711 | gen_rldinm(ctx, mb, 63 - sh, sh); |
2712 | } | |
2713 | GEN_PPC64_R4(rldic, 0x1E, 0x04); | |
2714 | ||
a7b2c8b9 | 2715 | static void gen_rldnm(DisasContext *ctx, int mb, int me) |
51789c41 | 2716 | { |
a7b2c8b9 RH |
2717 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
2718 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
2719 | TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; | |
54843a58 | 2720 | TCGv t0; |
d03ef511 | 2721 | |
a7812ae4 | 2722 | t0 = tcg_temp_new(); |
a7b2c8b9 RH |
2723 | tcg_gen_andi_tl(t0, t_rb, 0x3f); |
2724 | tcg_gen_rotl_tl(t_ra, t_rs, t0); | |
a7b2c8b9 RH |
2725 | |
2726 | tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); | |
2727 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2728 | gen_set_Rc0(ctx, t_ra); | |
2729 | } | |
d9bce9d9 | 2730 | } |
51789c41 | 2731 | |
d9bce9d9 | 2732 | /* rldcl - rldcl. */ |
636aa200 | 2733 | static inline void gen_rldcl(DisasContext *ctx, int mbn) |
d9bce9d9 | 2734 | { |
51789c41 | 2735 | uint32_t mb; |
d9bce9d9 | 2736 | |
9d53c753 | 2737 | mb = MB(ctx->opcode) | (mbn << 5); |
51789c41 | 2738 | gen_rldnm(ctx, mb, 63); |
d9bce9d9 | 2739 | } |
36081602 | 2740 | GEN_PPC64_R2(rldcl, 0x1E, 0x08); |
a7b2c8b9 | 2741 | |
d9bce9d9 | 2742 | /* rldcr - rldcr. */ |
636aa200 | 2743 | static inline void gen_rldcr(DisasContext *ctx, int men) |
d9bce9d9 | 2744 | { |
51789c41 | 2745 | uint32_t me; |
d9bce9d9 | 2746 | |
9d53c753 | 2747 | me = MB(ctx->opcode) | (men << 5); |
51789c41 | 2748 | gen_rldnm(ctx, 0, me); |
d9bce9d9 | 2749 | } |
36081602 | 2750 | GEN_PPC64_R2(rldcr, 0x1E, 0x09); |
a7b2c8b9 | 2751 | |
d9bce9d9 | 2752 | /* rldimi - rldimi. */ |
a7b2c8b9 | 2753 | static void gen_rldimi(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 2754 | { |
a7b2c8b9 RH |
2755 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
2756 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
2757 | uint32_t sh = SH(ctx->opcode) | (shn << 5); | |
2758 | uint32_t mb = MB(ctx->opcode) | (mbn << 5); | |
2759 | uint32_t me = 63 - sh; | |
d9bce9d9 | 2760 | |
a7b2c8b9 RH |
2761 | if (mb <= me) { |
2762 | tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); | |
d03ef511 | 2763 | } else { |
a7b2c8b9 RH |
2764 | target_ulong mask = MASK(mb, me); |
2765 | TCGv t1 = tcg_temp_new(); | |
d03ef511 | 2766 | |
a7b2c8b9 RH |
2767 | tcg_gen_rotli_tl(t1, t_rs, sh); |
2768 | tcg_gen_andi_tl(t1, t1, mask); | |
2769 | tcg_gen_andi_tl(t_ra, t_ra, ~mask); | |
2770 | tcg_gen_or_tl(t_ra, t_ra, t1); | |
51789c41 | 2771 | } |
a7b2c8b9 RH |
2772 | if (unlikely(Rc(ctx->opcode) != 0)) { |
2773 | gen_set_Rc0(ctx, t_ra); | |
2774 | } | |
d9bce9d9 | 2775 | } |
36081602 | 2776 | GEN_PPC64_R4(rldimi, 0x1E, 0x06); |
d9bce9d9 JM |
2777 | #endif |
2778 | ||
79aceca5 | 2779 | /*** Integer shift ***/ |
99e300ef | 2780 | |
54623277 | 2781 | /* slw & slw. */ |
99e300ef | 2782 | static void gen_slw(DisasContext *ctx) |
26d67362 | 2783 | { |
7fd6bf7d | 2784 | TCGv t0, t1; |
26d67362 | 2785 | |
7fd6bf7d AJ |
2786 | t0 = tcg_temp_new(); |
2787 | /* AND rS with a mask that is 0 when rB >= 0x20 */ | |
2788 | #if defined(TARGET_PPC64) | |
2789 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); | |
2790 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
2791 | #else | |
2792 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); | |
2793 | tcg_gen_sari_tl(t0, t0, 0x1f); | |
2794 | #endif | |
2795 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
2796 | t1 = tcg_temp_new(); | |
2797 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); | |
2798 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
7fd6bf7d | 2799 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 2800 | if (unlikely(Rc(ctx->opcode) != 0)) { |
26d67362 | 2801 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 2802 | } |
26d67362 | 2803 | } |
99e300ef | 2804 | |
54623277 | 2805 | /* sraw & sraw. */ |
99e300ef | 2806 | static void gen_sraw(DisasContext *ctx) |
26d67362 | 2807 | { |
d15f74fb | 2808 | gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, |
a7812ae4 | 2809 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
efe843d8 | 2810 | if (unlikely(Rc(ctx->opcode) != 0)) { |
26d67362 | 2811 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 2812 | } |
26d67362 | 2813 | } |
99e300ef | 2814 | |
54623277 | 2815 | /* srawi & srawi. */ |
99e300ef | 2816 | static void gen_srawi(DisasContext *ctx) |
79aceca5 | 2817 | { |
26d67362 | 2818 | int sh = SH(ctx->opcode); |
ba4af3e4 RH |
2819 | TCGv dst = cpu_gpr[rA(ctx->opcode)]; |
2820 | TCGv src = cpu_gpr[rS(ctx->opcode)]; | |
2821 | if (sh == 0) { | |
34a0fad1 | 2822 | tcg_gen_ext32s_tl(dst, src); |
da91a00f | 2823 | tcg_gen_movi_tl(cpu_ca, 0); |
af1c259f SD |
2824 | if (is_isa300(ctx)) { |
2825 | tcg_gen_movi_tl(cpu_ca32, 0); | |
2826 | } | |
26d67362 | 2827 | } else { |
ba4af3e4 RH |
2828 | TCGv t0; |
2829 | tcg_gen_ext32s_tl(dst, src); | |
2830 | tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); | |
2831 | t0 = tcg_temp_new(); | |
2832 | tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); | |
2833 | tcg_gen_and_tl(cpu_ca, cpu_ca, t0); | |
ba4af3e4 | 2834 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); |
af1c259f SD |
2835 | if (is_isa300(ctx)) { |
2836 | tcg_gen_mov_tl(cpu_ca32, cpu_ca); | |
2837 | } | |
ba4af3e4 RH |
2838 | tcg_gen_sari_tl(dst, dst, sh); |
2839 | } | |
2840 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2841 | gen_set_Rc0(ctx, dst); | |
d9bce9d9 | 2842 | } |
79aceca5 | 2843 | } |
99e300ef | 2844 | |
54623277 | 2845 | /* srw & srw. */ |
99e300ef | 2846 | static void gen_srw(DisasContext *ctx) |
26d67362 | 2847 | { |
fea0c503 | 2848 | TCGv t0, t1; |
d9bce9d9 | 2849 | |
7fd6bf7d AJ |
2850 | t0 = tcg_temp_new(); |
2851 | /* AND rS with a mask that is 0 when rB >= 0x20 */ | |
2852 | #if defined(TARGET_PPC64) | |
2853 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); | |
2854 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
2855 | #else | |
2856 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); | |
2857 | tcg_gen_sari_tl(t0, t0, 0x1f); | |
2858 | #endif | |
2859 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
2860 | tcg_gen_ext32u_tl(t0, t0); | |
a7812ae4 | 2861 | t1 = tcg_temp_new(); |
7fd6bf7d AJ |
2862 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); |
2863 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
efe843d8 | 2864 | if (unlikely(Rc(ctx->opcode) != 0)) { |
26d67362 | 2865 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 2866 | } |
26d67362 | 2867 | } |
54623277 | 2868 | |
d9bce9d9 JM |
2869 | #if defined(TARGET_PPC64) |
2870 | /* sld & sld. */ | |
99e300ef | 2871 | static void gen_sld(DisasContext *ctx) |
26d67362 | 2872 | { |
7fd6bf7d | 2873 | TCGv t0, t1; |
26d67362 | 2874 | |
7fd6bf7d AJ |
2875 | t0 = tcg_temp_new(); |
2876 | /* AND rS with a mask that is 0 when rB >= 0x40 */ | |
2877 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); | |
2878 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
2879 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
2880 | t1 = tcg_temp_new(); | |
2881 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); | |
2882 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
efe843d8 | 2883 | if (unlikely(Rc(ctx->opcode) != 0)) { |
26d67362 | 2884 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 2885 | } |
26d67362 | 2886 | } |
99e300ef | 2887 | |
54623277 | 2888 | /* srad & srad. */ |
99e300ef | 2889 | static void gen_srad(DisasContext *ctx) |
26d67362 | 2890 | { |
d15f74fb | 2891 | gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, |
a7812ae4 | 2892 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
efe843d8 | 2893 | if (unlikely(Rc(ctx->opcode) != 0)) { |
26d67362 | 2894 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 2895 | } |
26d67362 | 2896 | } |
d9bce9d9 | 2897 | /* sradi & sradi. */ |
636aa200 | 2898 | static inline void gen_sradi(DisasContext *ctx, int n) |
d9bce9d9 | 2899 | { |
26d67362 | 2900 | int sh = SH(ctx->opcode) + (n << 5); |
ba4af3e4 RH |
2901 | TCGv dst = cpu_gpr[rA(ctx->opcode)]; |
2902 | TCGv src = cpu_gpr[rS(ctx->opcode)]; | |
2903 | if (sh == 0) { | |
2904 | tcg_gen_mov_tl(dst, src); | |
da91a00f | 2905 | tcg_gen_movi_tl(cpu_ca, 0); |
af1c259f SD |
2906 | if (is_isa300(ctx)) { |
2907 | tcg_gen_movi_tl(cpu_ca32, 0); | |
2908 | } | |
26d67362 | 2909 | } else { |
ba4af3e4 RH |
2910 | TCGv t0; |
2911 | tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); | |
2912 | t0 = tcg_temp_new(); | |
2913 | tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); | |
2914 | tcg_gen_and_tl(cpu_ca, cpu_ca, t0); | |
ba4af3e4 | 2915 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); |
af1c259f SD |
2916 | if (is_isa300(ctx)) { |
2917 | tcg_gen_mov_tl(cpu_ca32, cpu_ca); | |
2918 | } | |
ba4af3e4 RH |
2919 | tcg_gen_sari_tl(dst, src, sh); |
2920 | } | |
2921 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2922 | gen_set_Rc0(ctx, dst); | |
d9bce9d9 | 2923 | } |
d9bce9d9 | 2924 | } |
e8eaa2c0 BS |
2925 | |
2926 | static void gen_sradi0(DisasContext *ctx) | |
d9bce9d9 JM |
2927 | { |
2928 | gen_sradi(ctx, 0); | |
2929 | } | |
e8eaa2c0 BS |
2930 | |
2931 | static void gen_sradi1(DisasContext *ctx) | |
d9bce9d9 JM |
2932 | { |
2933 | gen_sradi(ctx, 1); | |
2934 | } | |
99e300ef | 2935 | |
787bbe37 ND |
2936 | /* extswsli & extswsli. */ |
2937 | static inline void gen_extswsli(DisasContext *ctx, int n) | |
2938 | { | |
2939 | int sh = SH(ctx->opcode) + (n << 5); | |
2940 | TCGv dst = cpu_gpr[rA(ctx->opcode)]; | |
2941 | TCGv src = cpu_gpr[rS(ctx->opcode)]; | |
2942 | ||
2943 | tcg_gen_ext32s_tl(dst, src); | |
2944 | tcg_gen_shli_tl(dst, dst, sh); | |
2945 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2946 | gen_set_Rc0(ctx, dst); | |
2947 | } | |
2948 | } | |
2949 | ||
2950 | static void gen_extswsli0(DisasContext *ctx) | |
2951 | { | |
2952 | gen_extswsli(ctx, 0); | |
2953 | } | |
2954 | ||
2955 | static void gen_extswsli1(DisasContext *ctx) | |
2956 | { | |
2957 | gen_extswsli(ctx, 1); | |
2958 | } | |
2959 | ||
54623277 | 2960 | /* srd & srd. */ |
99e300ef | 2961 | static void gen_srd(DisasContext *ctx) |
26d67362 | 2962 | { |
7fd6bf7d | 2963 | TCGv t0, t1; |
26d67362 | 2964 | |
7fd6bf7d AJ |
2965 | t0 = tcg_temp_new(); |
2966 | /* AND rS with a mask that is 0 when rB >= 0x40 */ | |
2967 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); | |
2968 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
2969 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
2970 | t1 = tcg_temp_new(); | |
2971 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); | |
2972 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
efe843d8 | 2973 | if (unlikely(Rc(ctx->opcode) != 0)) { |
26d67362 | 2974 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 2975 | } |
26d67362 | 2976 | } |
d9bce9d9 | 2977 | #endif |
79aceca5 | 2978 | |
76a66253 JM |
2979 | /*** Addressing modes ***/ |
2980 | /* Register indirect with immediate index : EA = (rA|0) + SIMM */ | |
636aa200 BS |
2981 | static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, |
2982 | target_long maskl) | |
76a66253 JM |
2983 | { |
2984 | target_long simm = SIMM(ctx->opcode); | |
2985 | ||
be147d08 | 2986 | simm &= ~maskl; |
76db3ba4 | 2987 | if (rA(ctx->opcode) == 0) { |
c791fe84 RH |
2988 | if (NARROW_MODE(ctx)) { |
2989 | simm = (uint32_t)simm; | |
2990 | } | |
e2be8d8d | 2991 | tcg_gen_movi_tl(EA, simm); |
76db3ba4 | 2992 | } else if (likely(simm != 0)) { |
e2be8d8d | 2993 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); |
c791fe84 | 2994 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
2995 | tcg_gen_ext32u_tl(EA, EA); |
2996 | } | |
76db3ba4 | 2997 | } else { |
c791fe84 | 2998 | if (NARROW_MODE(ctx)) { |
76db3ba4 | 2999 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
c791fe84 RH |
3000 | } else { |
3001 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
3002 | } | |
76db3ba4 | 3003 | } |
76a66253 JM |
3004 | } |
3005 | ||
636aa200 | 3006 | static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) |
76a66253 | 3007 | { |
76db3ba4 | 3008 | if (rA(ctx->opcode) == 0) { |
c791fe84 | 3009 | if (NARROW_MODE(ctx)) { |
76db3ba4 | 3010 | tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); |
c791fe84 RH |
3011 | } else { |
3012 | tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); | |
3013 | } | |
76db3ba4 | 3014 | } else { |
e2be8d8d | 3015 | tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
c791fe84 | 3016 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
3017 | tcg_gen_ext32u_tl(EA, EA); |
3018 | } | |
76db3ba4 | 3019 | } |
76a66253 JM |
3020 | } |
3021 | ||
636aa200 | 3022 | static inline void gen_addr_register(DisasContext *ctx, TCGv EA) |
76a66253 | 3023 | { |
76db3ba4 | 3024 | if (rA(ctx->opcode) == 0) { |
e2be8d8d | 3025 | tcg_gen_movi_tl(EA, 0); |
c791fe84 RH |
3026 | } else if (NARROW_MODE(ctx)) { |
3027 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
76db3ba4 | 3028 | } else { |
c791fe84 | 3029 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
76db3ba4 AJ |
3030 | } |
3031 | } | |
3032 | ||
636aa200 BS |
3033 | static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
3034 | target_long val) | |
76db3ba4 AJ |
3035 | { |
3036 | tcg_gen_addi_tl(ret, arg1, val); | |
c791fe84 | 3037 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
3038 | tcg_gen_ext32u_tl(ret, ret); |
3039 | } | |
76a66253 JM |
3040 | } |
3041 | ||
65f2475f BH |
3042 | static inline void gen_align_no_le(DisasContext *ctx) |
3043 | { | |
3044 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, | |
3045 | (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); | |
3046 | } | |
3047 | ||
eb63efd9 FEV |
3048 | static TCGv do_ea_calc(DisasContext *ctx, int ra, TCGv displ) |
3049 | { | |
3050 | TCGv ea = tcg_temp_new(); | |
3051 | if (ra) { | |
3052 | tcg_gen_add_tl(ea, cpu_gpr[ra], displ); | |
3053 | } else { | |
3054 | tcg_gen_mov_tl(ea, displ); | |
3055 | } | |
3056 | if (NARROW_MODE(ctx)) { | |
3057 | tcg_gen_ext32u_tl(ea, ea); | |
3058 | } | |
3059 | return ea; | |
3060 | } | |
3061 | ||
7863667f | 3062 | /*** Integer load ***/ |
09bfe50d | 3063 | #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) |
ff5f3981 | 3064 | #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) |
b61f2753 | 3065 | |
09bfe50d ND |
3066 | #define GEN_QEMU_LOAD_TL(ldop, op) \ |
3067 | static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ | |
3068 | TCGv val, \ | |
3069 | TCGv addr) \ | |
3070 | { \ | |
3071 | tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ | |
b61f2753 AJ |
3072 | } |
3073 | ||
09bfe50d ND |
3074 | GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) |
3075 | GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) | |
3076 | GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) | |
3077 | GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) | |
3078 | GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) | |
f976b09e | 3079 | |
ff5f3981 ND |
3080 | GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) |
3081 | GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) | |
3082 | ||
09bfe50d ND |
3083 | #define GEN_QEMU_LOAD_64(ldop, op) \ |
3084 | static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ | |
3085 | TCGv_i64 val, \ | |
3086 | TCGv addr) \ | |
3087 | { \ | |
3088 | tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ | |
b61f2753 AJ |
3089 | } |
3090 | ||
740ae9a2 ND |
3091 | GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) |
3092 | GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) | |
09bfe50d ND |
3093 | GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) |
3094 | GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) | |
fc313c64 | 3095 | GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_UQ)) |
b61f2753 | 3096 | |
ff5f3981 | 3097 | #if defined(TARGET_PPC64) |
fc313c64 | 3098 | GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_UQ)) |
ff5f3981 ND |
3099 | #endif |
3100 | ||
761a89c6 ND |
3101 | #define GEN_QEMU_STORE_TL(stop, op) \ |
3102 | static void glue(gen_qemu_, stop)(DisasContext *ctx, \ | |
3103 | TCGv val, \ | |
3104 | TCGv addr) \ | |
3105 | { \ | |
3106 | tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ | |
b61f2753 AJ |
3107 | } |
3108 | ||
e8f4c8d6 | 3109 | #if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY) |
761a89c6 | 3110 | GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) |
e8f4c8d6 | 3111 | #endif |
761a89c6 ND |
3112 | GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) |
3113 | GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) | |
b61f2753 | 3114 | |
804108aa ND |
3115 | GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) |
3116 | GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) | |
3117 | ||
761a89c6 ND |
3118 | #define GEN_QEMU_STORE_64(stop, op) \ |
3119 | static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ | |
3120 | TCGv_i64 val, \ | |
3121 | TCGv addr) \ | |
3122 | { \ | |
3123 | tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ | |
b61f2753 AJ |
3124 | } |
3125 | ||
ddb9ac50 ND |
3126 | GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) |
3127 | GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) | |
761a89c6 | 3128 | GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) |
fc313c64 | 3129 | GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_UQ)) |
b61f2753 | 3130 | |
804108aa | 3131 | #if defined(TARGET_PPC64) |
fc313c64 | 3132 | GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ)) |
804108aa ND |
3133 | #endif |
3134 | ||
b7815375 | 3135 | #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ |
99e300ef | 3136 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 3137 | { \ |
76db3ba4 | 3138 | TCGv EA; \ |
9f0cf041 | 3139 | chk(ctx); \ |
76db3ba4 AJ |
3140 | gen_set_access_type(ctx, ACCESS_INT); \ |
3141 | EA = tcg_temp_new(); \ | |
3142 | gen_addr_reg_index(ctx, EA); \ | |
3143 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
79aceca5 | 3144 | } |
b7815375 | 3145 | |
cd6e9320 | 3146 | #define GEN_LDX(name, ldop, opc2, opc3, type) \ |
b7815375 BH |
3147 | GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) |
3148 | ||
3149 | #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ | |
3150 | GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) | |
79aceca5 | 3151 | |
50728199 RK |
3152 | #define GEN_LDEPX(name, ldop, opc2, opc3) \ |
3153 | static void glue(gen_, name##epx)(DisasContext *ctx) \ | |
3154 | { \ | |
3155 | TCGv EA; \ | |
9f0cf041 | 3156 | CHK_SV(ctx); \ |
50728199 RK |
3157 | gen_set_access_type(ctx, ACCESS_INT); \ |
3158 | EA = tcg_temp_new(); \ | |
3159 | gen_addr_reg_index(ctx, EA); \ | |
3160 | tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ | |
50728199 RK |
3161 | } |
3162 | ||
3163 | GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) | |
3164 | GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) | |
3165 | GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) | |
3166 | #if defined(TARGET_PPC64) | |
fc313c64 | 3167 | GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) |
50728199 RK |
3168 | #endif |
3169 | ||
d9bce9d9 | 3170 | #if defined(TARGET_PPC64) |
b7815375 | 3171 | /* CI load/store variants */ |
4f364fe7 | 3172 | GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) |
b7815375 BH |
3173 | GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) |
3174 | GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) | |
3175 | GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) | |
d9bce9d9 | 3176 | #endif |
79aceca5 FB |
3177 | |
3178 | /*** Integer store ***/ | |
b7815375 | 3179 | #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ |
cd6e9320 | 3180 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 3181 | { \ |
76db3ba4 | 3182 | TCGv EA; \ |
9f0cf041 | 3183 | chk(ctx); \ |
76db3ba4 AJ |
3184 | gen_set_access_type(ctx, ACCESS_INT); \ |
3185 | EA = tcg_temp_new(); \ | |
3186 | gen_addr_reg_index(ctx, EA); \ | |
3187 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
79aceca5 | 3188 | } |
cd6e9320 | 3189 | #define GEN_STX(name, stop, opc2, opc3, type) \ |
b7815375 BH |
3190 | GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) |
3191 | ||
3192 | #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ | |
3193 | GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) | |
79aceca5 | 3194 | |
50728199 RK |
3195 | #define GEN_STEPX(name, stop, opc2, opc3) \ |
3196 | static void glue(gen_, name##epx)(DisasContext *ctx) \ | |
3197 | { \ | |
3198 | TCGv EA; \ | |
9f0cf041 | 3199 | CHK_SV(ctx); \ |
50728199 RK |
3200 | gen_set_access_type(ctx, ACCESS_INT); \ |
3201 | EA = tcg_temp_new(); \ | |
3202 | gen_addr_reg_index(ctx, EA); \ | |
3203 | tcg_gen_qemu_st_tl( \ | |
3204 | cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ | |
50728199 RK |
3205 | } |
3206 | ||
3207 | GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) | |
3208 | GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) | |
3209 | GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) | |
3210 | #if defined(TARGET_PPC64) | |
fc313c64 | 3211 | GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1d, 0x04) |
50728199 RK |
3212 | #endif |
3213 | ||
d9bce9d9 | 3214 | #if defined(TARGET_PPC64) |
2468f23d | 3215 | GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) |
b7815375 BH |
3216 | GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) |
3217 | GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) | |
3218 | GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) | |
d9bce9d9 | 3219 | #endif |
79aceca5 | 3220 | /*** Integer load and store with byte reverse ***/ |
e22c357b | 3221 | |
79aceca5 | 3222 | /* lhbrx */ |
0c8aacd4 | 3223 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); |
b61f2753 | 3224 | |
79aceca5 | 3225 | /* lwbrx */ |
0c8aacd4 | 3226 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); |
b61f2753 | 3227 | |
cd6e9320 TH |
3228 | #if defined(TARGET_PPC64) |
3229 | /* ldbrx */ | |
ff5f3981 | 3230 | GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); |
804108aa ND |
3231 | /* stdbrx */ |
3232 | GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); | |
cd6e9320 TH |
3233 | #endif /* TARGET_PPC64 */ |
3234 | ||
79aceca5 | 3235 | /* sthbrx */ |
0c8aacd4 | 3236 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); |
79aceca5 | 3237 | /* stwbrx */ |
0c8aacd4 | 3238 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); |
79aceca5 FB |
3239 | |
3240 | /*** Integer load and store multiple ***/ | |
99e300ef | 3241 | |
54623277 | 3242 | /* lmw */ |
99e300ef | 3243 | static void gen_lmw(DisasContext *ctx) |
79aceca5 | 3244 | { |
76db3ba4 AJ |
3245 | TCGv t0; |
3246 | TCGv_i32 t1; | |
5817355e BH |
3247 | |
3248 | if (ctx->le_mode) { | |
3249 | gen_align_no_le(ctx); | |
3250 | return; | |
3251 | } | |
76db3ba4 | 3252 | gen_set_access_type(ctx, ACCESS_INT); |
76db3ba4 | 3253 | t0 = tcg_temp_new(); |
7058ff52 | 3254 | t1 = tcg_constant_i32(rD(ctx->opcode)); |
76db3ba4 | 3255 | gen_addr_imm_index(ctx, t0, 0); |
2f5a189c | 3256 | gen_helper_lmw(cpu_env, t0, t1); |
79aceca5 FB |
3257 | } |
3258 | ||
3259 | /* stmw */ | |
99e300ef | 3260 | static void gen_stmw(DisasContext *ctx) |
79aceca5 | 3261 | { |
76db3ba4 AJ |
3262 | TCGv t0; |
3263 | TCGv_i32 t1; | |
5817355e BH |
3264 | |
3265 | if (ctx->le_mode) { | |
3266 | gen_align_no_le(ctx); | |
3267 | return; | |
3268 | } | |
76db3ba4 | 3269 | gen_set_access_type(ctx, ACCESS_INT); |
76db3ba4 | 3270 | t0 = tcg_temp_new(); |
7058ff52 | 3271 | t1 = tcg_constant_i32(rS(ctx->opcode)); |
76db3ba4 | 3272 | gen_addr_imm_index(ctx, t0, 0); |
2f5a189c | 3273 | gen_helper_stmw(cpu_env, t0, t1); |
79aceca5 FB |
3274 | } |
3275 | ||
3276 | /*** Integer load and store strings ***/ | |
54623277 | 3277 | |
79aceca5 | 3278 | /* lswi */ |
efe843d8 DG |
3279 | /* |
3280 | * PowerPC32 specification says we must generate an exception if rA is | |
3281 | * in the range of registers to be loaded. In an other hand, IBM says | |
3282 | * this is valid, but rA won't be loaded. For now, I'll follow the | |
3283 | * spec... | |
9a64fbe4 | 3284 | */ |
99e300ef | 3285 | static void gen_lswi(DisasContext *ctx) |
79aceca5 | 3286 | { |
dfbc799d AJ |
3287 | TCGv t0; |
3288 | TCGv_i32 t1, t2; | |
79aceca5 FB |
3289 | int nb = NB(ctx->opcode); |
3290 | int start = rD(ctx->opcode); | |
9a64fbe4 | 3291 | int ra = rA(ctx->opcode); |
79aceca5 FB |
3292 | int nr; |
3293 | ||
5817355e BH |
3294 | if (ctx->le_mode) { |
3295 | gen_align_no_le(ctx); | |
3296 | return; | |
3297 | } | |
efe843d8 | 3298 | if (nb == 0) { |
79aceca5 | 3299 | nb = 32; |
efe843d8 | 3300 | } |
f0704d78 | 3301 | nr = DIV_ROUND_UP(nb, 4); |
afbee712 | 3302 | if (unlikely(lsw_reg_in_range(start, nr, ra))) { |
e06fcd75 | 3303 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); |
9fddaa0c | 3304 | return; |
297d8e62 | 3305 | } |
76db3ba4 | 3306 | gen_set_access_type(ctx, ACCESS_INT); |
dfbc799d | 3307 | t0 = tcg_temp_new(); |
76db3ba4 | 3308 | gen_addr_register(ctx, t0); |
7058ff52 RH |
3309 | t1 = tcg_constant_i32(nb); |
3310 | t2 = tcg_constant_i32(start); | |
2f5a189c | 3311 | gen_helper_lsw(cpu_env, t0, t1, t2); |
79aceca5 FB |
3312 | } |
3313 | ||
3314 | /* lswx */ | |
99e300ef | 3315 | static void gen_lswx(DisasContext *ctx) |
79aceca5 | 3316 | { |
76db3ba4 AJ |
3317 | TCGv t0; |
3318 | TCGv_i32 t1, t2, t3; | |
5817355e BH |
3319 | |
3320 | if (ctx->le_mode) { | |
3321 | gen_align_no_le(ctx); | |
3322 | return; | |
3323 | } | |
76db3ba4 | 3324 | gen_set_access_type(ctx, ACCESS_INT); |
76db3ba4 AJ |
3325 | t0 = tcg_temp_new(); |
3326 | gen_addr_reg_index(ctx, t0); | |
7058ff52 RH |
3327 | t1 = tcg_constant_i32(rD(ctx->opcode)); |
3328 | t2 = tcg_constant_i32(rA(ctx->opcode)); | |
3329 | t3 = tcg_constant_i32(rB(ctx->opcode)); | |
2f5a189c | 3330 | gen_helper_lswx(cpu_env, t0, t1, t2, t3); |
79aceca5 FB |
3331 | } |
3332 | ||
3333 | /* stswi */ | |
99e300ef | 3334 | static void gen_stswi(DisasContext *ctx) |
79aceca5 | 3335 | { |
76db3ba4 AJ |
3336 | TCGv t0; |
3337 | TCGv_i32 t1, t2; | |
4b3686fa | 3338 | int nb = NB(ctx->opcode); |
5817355e BH |
3339 | |
3340 | if (ctx->le_mode) { | |
3341 | gen_align_no_le(ctx); | |
3342 | return; | |
3343 | } | |
76db3ba4 | 3344 | gen_set_access_type(ctx, ACCESS_INT); |
76db3ba4 AJ |
3345 | t0 = tcg_temp_new(); |
3346 | gen_addr_register(ctx, t0); | |
efe843d8 | 3347 | if (nb == 0) { |
4b3686fa | 3348 | nb = 32; |
efe843d8 | 3349 | } |
7058ff52 RH |
3350 | t1 = tcg_constant_i32(nb); |
3351 | t2 = tcg_constant_i32(rS(ctx->opcode)); | |
2f5a189c | 3352 | gen_helper_stsw(cpu_env, t0, t1, t2); |
79aceca5 FB |
3353 | } |
3354 | ||
3355 | /* stswx */ | |
99e300ef | 3356 | static void gen_stswx(DisasContext *ctx) |
79aceca5 | 3357 | { |
76db3ba4 AJ |
3358 | TCGv t0; |
3359 | TCGv_i32 t1, t2; | |
5817355e BH |
3360 | |
3361 | if (ctx->le_mode) { | |
3362 | gen_align_no_le(ctx); | |
3363 | return; | |
3364 | } | |
76db3ba4 | 3365 | gen_set_access_type(ctx, ACCESS_INT); |
76db3ba4 AJ |
3366 | t0 = tcg_temp_new(); |
3367 | gen_addr_reg_index(ctx, t0); | |
3368 | t1 = tcg_temp_new_i32(); | |
dfbc799d AJ |
3369 | tcg_gen_trunc_tl_i32(t1, cpu_xer); |
3370 | tcg_gen_andi_i32(t1, t1, 0x7F); | |
7058ff52 | 3371 | t2 = tcg_constant_i32(rS(ctx->opcode)); |
2f5a189c | 3372 | gen_helper_stsw(cpu_env, t0, t1, t2); |
79aceca5 FB |
3373 | } |
3374 | ||
3375 | /*** Memory synchronisation ***/ | |
3376 | /* eieio */ | |
99e300ef | 3377 | static void gen_eieio(DisasContext *ctx) |
79aceca5 | 3378 | { |
fcb830af NP |
3379 | TCGBar bar = TCG_MO_ALL; |
3380 | ||
3381 | /* | |
3382 | * eieio has complex semanitcs. It provides memory ordering between | |
3383 | * operations in the set: | |
3384 | * - loads from CI memory. | |
3385 | * - stores to CI memory. | |
3386 | * - stores to WT memory. | |
3387 | * | |
3388 | * It separately also orders memory for operations in the set: | |
3389 | * - stores to cacheble memory. | |
3390 | * | |
3391 | * It also serializes instructions: | |
3392 | * - dcbt and dcbst. | |
3393 | * | |
3394 | * It separately serializes: | |
3395 | * - tlbie and tlbsync. | |
3396 | * | |
3397 | * And separately serializes: | |
3398 | * - slbieg, slbiag, and slbsync. | |
3399 | * | |
3400 | * The end result is that CI memory ordering requires TCG_MO_ALL | |
3401 | * and it is not possible to special-case more relaxed ordering for | |
3402 | * cacheable accesses. TCG_BAR_SC is required to provide this | |
3403 | * serialization. | |
3404 | */ | |
c8fd8373 CLG |
3405 | |
3406 | /* | |
3407 | * POWER9 has a eieio instruction variant using bit 6 as a hint to | |
3408 | * tell the CPU it is a store-forwarding barrier. | |
3409 | */ | |
3410 | if (ctx->opcode & 0x2000000) { | |
3411 | /* | |
3412 | * ISA says that "Reserved fields in instructions are ignored | |
3413 | * by the processor". So ignore the bit 6 on non-POWER9 CPU but | |
3414 | * as this is not an instruction software should be using, | |
3415 | * complain to the user. | |
3416 | */ | |
3417 | if (!(ctx->insns_flags2 & PPC2_ISA300)) { | |
3418 | qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" | |
2c2bcb1b | 3419 | TARGET_FMT_lx "\n", ctx->cia); |
c8fd8373 CLG |
3420 | } else { |
3421 | bar = TCG_MO_ST_LD; | |
3422 | } | |
3423 | } | |
3424 | ||
3425 | tcg_gen_mb(bar | TCG_BAR_SC); | |
79aceca5 FB |
3426 | } |
3427 | ||
c5a8d8f3 | 3428 | #if !defined(CONFIG_USER_ONLY) |
e3cffe6f | 3429 | static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) |
cd0c6f47 | 3430 | { |
c5a8d8f3 BH |
3431 | TCGv_i32 t; |
3432 | TCGLabel *l; | |
cd0c6f47 | 3433 | |
c5a8d8f3 BH |
3434 | if (!ctx->lazy_tlb_flush) { |
3435 | return; | |
3436 | } | |
3437 | l = gen_new_label(); | |
3438 | t = tcg_temp_new_i32(); | |
cd0c6f47 BH |
3439 | tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); |
3440 | tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); | |
e3cffe6f ND |
3441 | if (global) { |
3442 | gen_helper_check_tlb_flush_global(cpu_env); | |
3443 | } else { | |
3444 | gen_helper_check_tlb_flush_local(cpu_env); | |
3445 | } | |
cd0c6f47 | 3446 | gen_set_label(l); |
cd0c6f47 BH |
3447 | } |
3448 | #else | |
e3cffe6f | 3449 | static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } |
cd0c6f47 BH |
3450 | #endif |
3451 | ||
79aceca5 | 3452 | /* isync */ |
99e300ef | 3453 | static void gen_isync(DisasContext *ctx) |
79aceca5 | 3454 | { |
cd0c6f47 BH |
3455 | /* |
3456 | * We need to check for a pending TLB flush. This can only happen in | |
3457 | * kernel mode however so check MSR_PR | |
3458 | */ | |
3459 | if (!ctx->pr) { | |
e3cffe6f | 3460 | gen_check_tlb_flush(ctx, false); |
cd0c6f47 | 3461 | } |
4771df23 | 3462 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); |
d736de8f | 3463 | ctx->base.is_jmp = DISAS_EXIT_UPDATE; |
79aceca5 FB |
3464 | } |
3465 | ||
48793c95 ND |
3466 | #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) |
3467 | ||
14776ab5 | 3468 | static void gen_load_locked(DisasContext *ctx, MemOp memop) |
2a4e6c1b RH |
3469 | { |
3470 | TCGv gpr = cpu_gpr[rD(ctx->opcode)]; | |
3471 | TCGv t0 = tcg_temp_new(); | |
3472 | ||
3473 | gen_set_access_type(ctx, ACCESS_RES); | |
3474 | gen_addr_reg_index(ctx, t0); | |
3475 | tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); | |
3476 | tcg_gen_mov_tl(cpu_reserve, t0); | |
392d328a | 3477 | tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop)); |
2a4e6c1b | 3478 | tcg_gen_mov_tl(cpu_reserve_val, gpr); |
2a4e6c1b RH |
3479 | } |
3480 | ||
3481 | #define LARX(name, memop) \ | |
3482 | static void gen_##name(DisasContext *ctx) \ | |
3483 | { \ | |
3484 | gen_load_locked(ctx, memop); \ | |
79aceca5 FB |
3485 | } |
3486 | ||
5c77a786 | 3487 | /* lwarx */ |
48793c95 ND |
3488 | LARX(lbarx, DEF_MEMOP(MO_UB)) |
3489 | LARX(lharx, DEF_MEMOP(MO_UW)) | |
3490 | LARX(lwarx, DEF_MEMOP(MO_UL)) | |
5c77a786 | 3491 | |
14776ab5 | 3492 | static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, |
20923c1d RH |
3493 | TCGv EA, TCGCond cond, int addend) |
3494 | { | |
3495 | TCGv t = tcg_temp_new(); | |
3496 | TCGv t2 = tcg_temp_new(); | |
3497 | TCGv u = tcg_temp_new(); | |
3498 | ||
3499 | tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); | |
3500 | tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); | |
3501 | tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); | |
3502 | tcg_gen_addi_tl(u, t, addend); | |
3503 | ||
3504 | /* E.g. for fetch and increment bounded... */ | |
3505 | /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ | |
3506 | tcg_gen_movcond_tl(cond, u, t, t2, u, t); | |
3507 | tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); | |
3508 | ||
3509 | /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ | |
3510 | tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); | |
3511 | tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); | |
20923c1d RH |
3512 | } |
3513 | ||
14776ab5 | 3514 | static void gen_ld_atomic(DisasContext *ctx, MemOp memop) |
20ba8504 RH |
3515 | { |
3516 | uint32_t gpr_FC = FC(ctx->opcode); | |
3517 | TCGv EA = tcg_temp_new(); | |
20923c1d RH |
3518 | int rt = rD(ctx->opcode); |
3519 | bool need_serial; | |
20ba8504 RH |
3520 | TCGv src, dst; |
3521 | ||
3522 | gen_addr_register(ctx, EA); | |
20923c1d RH |
3523 | dst = cpu_gpr[rt]; |
3524 | src = cpu_gpr[(rt + 1) & 31]; | |
20ba8504 | 3525 | |
20923c1d | 3526 | need_serial = false; |
20ba8504 RH |
3527 | memop |= MO_ALIGN; |
3528 | switch (gpr_FC) { | |
3529 | case 0: /* Fetch and add */ | |
3530 | tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); | |
3531 | break; | |
3532 | case 1: /* Fetch and xor */ | |
3533 | tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); | |
3534 | break; | |
3535 | case 2: /* Fetch and or */ | |
3536 | tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); | |
3537 | break; | |
3538 | case 3: /* Fetch and 'and' */ | |
3539 | tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); | |
3540 | break; | |
20ba8504 | 3541 | case 4: /* Fetch and max unsigned */ |
b8ce0f86 RH |
3542 | tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); |
3543 | break; | |
20ba8504 | 3544 | case 5: /* Fetch and max signed */ |
b8ce0f86 RH |
3545 | tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); |
3546 | break; | |
20ba8504 | 3547 | case 6: /* Fetch and min unsigned */ |
b8ce0f86 RH |
3548 | tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); |
3549 | break; | |
20ba8504 | 3550 | case 7: /* Fetch and min signed */ |
b8ce0f86 RH |
3551 | tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); |
3552 | break; | |
3553 | case 8: /* Swap */ | |
3554 | tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); | |
3555 | break; | |
20923c1d RH |
3556 | |
3557 | case 16: /* Compare and swap not equal */ | |
3558 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { | |
3559 | need_serial = true; | |
3560 | } else { | |
3561 | TCGv t0 = tcg_temp_new(); | |
3562 | TCGv t1 = tcg_temp_new(); | |
3563 | ||
3564 | tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); | |
3565 | if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { | |
3566 | tcg_gen_mov_tl(t1, src); | |
3567 | } else { | |
3568 | tcg_gen_ext32u_tl(t1, src); | |
3569 | } | |
3570 | tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, | |
3571 | cpu_gpr[(rt + 2) & 31], t0); | |
3572 | tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); | |
3573 | tcg_gen_mov_tl(dst, t0); | |
20923c1d RH |
3574 | } |
3575 | break; | |
3576 | ||
20ba8504 | 3577 | case 24: /* Fetch and increment bounded */ |
20923c1d RH |
3578 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { |
3579 | need_serial = true; | |
3580 | } else { | |
3581 | gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); | |
3582 | } | |
3583 | break; | |
20ba8504 | 3584 | case 25: /* Fetch and increment equal */ |
20923c1d RH |
3585 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { |
3586 | need_serial = true; | |
3587 | } else { | |
3588 | gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); | |
3589 | } | |
3590 | break; | |
20ba8504 | 3591 | case 28: /* Fetch and decrement bounded */ |
20923c1d RH |
3592 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { |
3593 | need_serial = true; | |
3594 | } else { | |
3595 | gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); | |
3596 | } | |
20ba8504 | 3597 | break; |
20923c1d | 3598 | |
20ba8504 RH |
3599 | default: |
3600 | /* invoke data storage error handler */ | |
3601 | gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); | |
3602 | } | |
20923c1d RH |
3603 | |
3604 | if (need_serial) { | |
3605 | /* Restart with exclusive lock. */ | |
3606 | gen_helper_exit_atomic(cpu_env); | |
3607 | ctx->base.is_jmp = DISAS_NORETURN; | |
3608 | } | |
20ba8504 RH |
3609 | } |
3610 | ||
3611 | static void gen_lwat(DisasContext *ctx) | |
3612 | { | |
3613 | gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); | |
3614 | } | |
3615 | ||
3616 | #ifdef TARGET_PPC64 | |
3617 | static void gen_ldat(DisasContext *ctx) | |
3618 | { | |
fc313c64 | 3619 | gen_ld_atomic(ctx, DEF_MEMOP(MO_UQ)); |
20ba8504 | 3620 | } |
a68a6146 B |
3621 | #endif |
3622 | ||
14776ab5 | 3623 | static void gen_st_atomic(DisasContext *ctx, MemOp memop) |
9deb041c RH |
3624 | { |
3625 | uint32_t gpr_FC = FC(ctx->opcode); | |
3626 | TCGv EA = tcg_temp_new(); | |
3627 | TCGv src, discard; | |
3628 | ||
3629 | gen_addr_register(ctx, EA); | |
3630 | src = cpu_gpr[rD(ctx->opcode)]; | |
3631 | discard = tcg_temp_new(); | |
3632 | ||
3633 | memop |= MO_ALIGN; | |
3634 | switch (gpr_FC) { | |
3635 | case 0: /* add and Store */ | |
3636 | tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); | |
3637 | break; | |
3638 | case 1: /* xor and Store */ | |
3639 | tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); | |
3640 | break; | |
3641 | case 2: /* Or and Store */ | |
3642 | tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); | |
3643 | break; | |
3644 | case 3: /* 'and' and Store */ | |
3645 | tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); | |
3646 | break; | |
3647 | case 4: /* Store max unsigned */ | |
b8ce0f86 RH |
3648 | tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); |
3649 | break; | |
9deb041c | 3650 | case 5: /* Store max signed */ |
b8ce0f86 RH |
3651 | tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); |
3652 | break; | |
9deb041c | 3653 | case 6: /* Store min unsigned */ |
b8ce0f86 RH |
3654 | tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); |
3655 | break; | |
9deb041c | 3656 | case 7: /* Store min signed */ |
b8ce0f86 RH |
3657 | tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); |
3658 | break; | |
9deb041c | 3659 | case 24: /* Store twin */ |
7fbc2b20 RH |
3660 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { |
3661 | /* Restart with exclusive lock. */ | |
3662 | gen_helper_exit_atomic(cpu_env); | |
3663 | ctx->base.is_jmp = DISAS_NORETURN; | |
3664 | } else { | |
3665 | TCGv t = tcg_temp_new(); | |
3666 | TCGv t2 = tcg_temp_new(); | |
3667 | TCGv s = tcg_temp_new(); | |
3668 | TCGv s2 = tcg_temp_new(); | |
3669 | TCGv ea_plus_s = tcg_temp_new(); | |
3670 | ||
3671 | tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); | |
3672 | tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); | |
3673 | tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); | |
3674 | tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); | |
3675 | tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); | |
3676 | tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); | |
3677 | tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); | |
7fbc2b20 | 3678 | } |
9deb041c RH |
3679 | break; |
3680 | default: | |
3681 | /* invoke data storage error handler */ | |
3682 | gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); | |
3683 | } | |
9deb041c RH |
3684 | } |
3685 | ||
3686 | static void gen_stwat(DisasContext *ctx) | |
3687 | { | |
3688 | gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); | |
3689 | } | |
3690 | ||
3691 | #ifdef TARGET_PPC64 | |
3692 | static void gen_stdat(DisasContext *ctx) | |
3693 | { | |
fc313c64 | 3694 | gen_st_atomic(ctx, DEF_MEMOP(MO_UQ)); |
9deb041c | 3695 | } |
a3401188 B |
3696 | #endif |
3697 | ||
14776ab5 | 3698 | static void gen_conditional_store(DisasContext *ctx, MemOp memop) |
587c51f7 | 3699 | { |
253ce7b2 ND |
3700 | TCGLabel *l1 = gen_new_label(); |
3701 | TCGLabel *l2 = gen_new_label(); | |
d8b86898 RH |
3702 | TCGv t0 = tcg_temp_new(); |
3703 | int reg = rS(ctx->opcode); | |
4425265b | 3704 | |
d8b86898 RH |
3705 | gen_set_access_type(ctx, ACCESS_RES); |
3706 | gen_addr_reg_index(ctx, t0); | |
3707 | tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); | |
392d328a | 3708 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, memop_size(memop), l1); |
253ce7b2 ND |
3709 | |
3710 | t0 = tcg_temp_new(); | |
3711 | tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, | |
3712 | cpu_gpr[reg], ctx->mem_idx, | |
3713 | DEF_MEMOP(memop) | MO_ALIGN); | |
3714 | tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); | |
3715 | tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); | |
3716 | tcg_gen_or_tl(t0, t0, cpu_so); | |
3717 | tcg_gen_trunc_tl_i32(cpu_crf[0], t0); | |
253ce7b2 ND |
3718 | tcg_gen_br(l2); |
3719 | ||
587c51f7 | 3720 | gen_set_label(l1); |
4771df23 | 3721 | |
253ce7b2 ND |
3722 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
3723 | ||
3724 | gen_set_label(l2); | |
587c51f7 TM |
3725 | tcg_gen_movi_tl(cpu_reserve, -1); |
3726 | } | |
587c51f7 | 3727 | |
d8b86898 RH |
3728 | #define STCX(name, memop) \ |
3729 | static void gen_##name(DisasContext *ctx) \ | |
3730 | { \ | |
3731 | gen_conditional_store(ctx, memop); \ | |
2391b357 ND |
3732 | } |
3733 | ||
3734 | STCX(stbcx_, DEF_MEMOP(MO_UB)) | |
3735 | STCX(sthcx_, DEF_MEMOP(MO_UW)) | |
3736 | STCX(stwcx_, DEF_MEMOP(MO_UL)) | |
587c51f7 | 3737 | |
426613db | 3738 | #if defined(TARGET_PPC64) |
426613db | 3739 | /* ldarx */ |
fc313c64 | 3740 | LARX(ldarx, DEF_MEMOP(MO_UQ)) |
2391b357 | 3741 | /* stdcx. */ |
fc313c64 | 3742 | STCX(stdcx_, DEF_MEMOP(MO_UQ)) |
426613db | 3743 | |
9c294d5a TM |
3744 | /* lqarx */ |
3745 | static void gen_lqarx(DisasContext *ctx) | |
3746 | { | |
9c294d5a | 3747 | int rd = rD(ctx->opcode); |
94bf2658 | 3748 | TCGv EA, hi, lo; |
57b38ffd | 3749 | TCGv_i128 t16; |
9c294d5a TM |
3750 | |
3751 | if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || | |
3752 | (rd == rB(ctx->opcode)))) { | |
3753 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
3754 | return; | |
3755 | } | |
3756 | ||
3757 | gen_set_access_type(ctx, ACCESS_RES); | |
94bf2658 | 3758 | EA = tcg_temp_new(); |
9c294d5a | 3759 | gen_addr_reg_index(ctx, EA); |
94bf2658 RH |
3760 | |
3761 | /* Note that the low part is always in RD+1, even in LE mode. */ | |
3762 | lo = cpu_gpr[rd + 1]; | |
3763 | hi = cpu_gpr[rd]; | |
3764 | ||
57b38ffd RH |
3765 | t16 = tcg_temp_new_i128(); |
3766 | tcg_gen_qemu_ld_i128(t16, EA, ctx->mem_idx, DEF_MEMOP(MO_128 | MO_ALIGN)); | |
3767 | tcg_gen_extr_i128_i64(lo, hi, t16); | |
94bf2658 | 3768 | |
e025e8f5 | 3769 | tcg_gen_mov_tl(cpu_reserve, EA); |
392d328a | 3770 | tcg_gen_movi_tl(cpu_reserve_length, 16); |
94bf2658 RH |
3771 | tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); |
3772 | tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); | |
9c294d5a TM |
3773 | } |
3774 | ||
aa2008af ND |
3775 | /* stqcx. */ |
3776 | static void gen_stqcx_(DisasContext *ctx) | |
3777 | { | |
894448ae | 3778 | TCGLabel *lab_fail, *lab_over; |
4a9b3c5d | 3779 | int rs = rS(ctx->opcode); |
894448ae RH |
3780 | TCGv EA, t0, t1; |
3781 | TCGv_i128 cmp, val; | |
aa2008af | 3782 | |
4a9b3c5d | 3783 | if (unlikely(rs & 1)) { |
aa2008af ND |
3784 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
3785 | return; | |
3786 | } | |
4a9b3c5d | 3787 | |
894448ae RH |
3788 | lab_fail = gen_new_label(); |
3789 | lab_over = gen_new_label(); | |
3790 | ||
aa2008af | 3791 | gen_set_access_type(ctx, ACCESS_RES); |
4a9b3c5d | 3792 | EA = tcg_temp_new(); |
aa2008af | 3793 | gen_addr_reg_index(ctx, EA); |
aa2008af | 3794 | |
894448ae | 3795 | tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); |
392d328a | 3796 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, 16, lab_fail); |
894448ae RH |
3797 | |
3798 | cmp = tcg_temp_new_i128(); | |
3799 | val = tcg_temp_new_i128(); | |
3800 | ||
3801 | tcg_gen_concat_i64_i128(cmp, cpu_reserve_val2, cpu_reserve_val); | |
3802 | ||
4a9b3c5d | 3803 | /* Note that the low part is always in RS+1, even in LE mode. */ |
894448ae | 3804 | tcg_gen_concat_i64_i128(val, cpu_gpr[rs + 1], cpu_gpr[rs]); |
aa2008af | 3805 | |
894448ae RH |
3806 | tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx, |
3807 | DEF_MEMOP(MO_128 | MO_ALIGN)); | |
894448ae RH |
3808 | |
3809 | t0 = tcg_temp_new(); | |
3810 | t1 = tcg_temp_new(); | |
3811 | tcg_gen_extr_i128_i64(t1, t0, val); | |
894448ae RH |
3812 | |
3813 | tcg_gen_xor_tl(t1, t1, cpu_reserve_val2); | |
3814 | tcg_gen_xor_tl(t0, t0, cpu_reserve_val); | |
3815 | tcg_gen_or_tl(t0, t0, t1); | |
894448ae RH |
3816 | |
3817 | tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0); | |
3818 | tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); | |
3819 | tcg_gen_or_tl(t0, t0, cpu_so); | |
3820 | tcg_gen_trunc_tl_i32(cpu_crf[0], t0); | |
894448ae RH |
3821 | |
3822 | tcg_gen_br(lab_over); | |
3823 | gen_set_label(lab_fail); | |
3824 | ||
894448ae RH |
3825 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
3826 | ||
3827 | gen_set_label(lab_over); | |
3828 | tcg_gen_movi_tl(cpu_reserve, -1); | |
4a9b3c5d | 3829 | } |
426613db JM |
3830 | #endif /* defined(TARGET_PPC64) */ |
3831 | ||
79aceca5 | 3832 | /* sync */ |
99e300ef | 3833 | static void gen_sync(DisasContext *ctx) |
79aceca5 | 3834 | { |
03abfd90 | 3835 | TCGBar bar = TCG_MO_ALL; |
cd0c6f47 BH |
3836 | uint32_t l = (ctx->opcode >> 21) & 3; |
3837 | ||
03abfd90 NP |
3838 | if ((l == 1) && (ctx->insns_flags2 & PPC2_MEM_LWSYNC)) { |
3839 | bar = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST; | |
3840 | } | |
3841 | ||
cd0c6f47 | 3842 | /* |
c5a8d8f3 BH |
3843 | * We may need to check for a pending TLB flush. |
3844 | * | |
3845 | * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. | |
3846 | * | |
3847 | * Additionally, this can only happen in kernel mode however so | |
3848 | * check MSR_PR as well. | |
cd0c6f47 | 3849 | */ |
c5a8d8f3 | 3850 | if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { |
e3cffe6f | 3851 | gen_check_tlb_flush(ctx, true); |
cd0c6f47 | 3852 | } |
03abfd90 NP |
3853 | |
3854 | tcg_gen_mb(bar | TCG_BAR_SC); | |
79aceca5 FB |
3855 | } |
3856 | ||
0db1b20e | 3857 | /* wait */ |
99e300ef | 3858 | static void gen_wait(DisasContext *ctx) |
0db1b20e | 3859 | { |
0c9717ff NP |
3860 | uint32_t wc; |
3861 | ||
3862 | if (ctx->insns_flags & PPC_WAIT) { | |
3863 | /* v2.03-v2.07 define an older incompatible 'wait' encoding. */ | |
3864 | ||
3865 | if (ctx->insns_flags2 & PPC2_PM_ISA206) { | |
3866 | /* v2.06 introduced the WC field. WC > 0 may be treated as no-op. */ | |
3867 | wc = WC(ctx->opcode); | |
3868 | } else { | |
3869 | wc = 0; | |
3870 | } | |
3871 | ||
3872 | } else if (ctx->insns_flags2 & PPC2_ISA300) { | |
3873 | /* v3.0 defines a new 'wait' encoding. */ | |
3874 | wc = WC(ctx->opcode); | |
3875 | if (ctx->insns_flags2 & PPC2_ISA310) { | |
3876 | uint32_t pl = PL(ctx->opcode); | |
3877 | ||
3878 | /* WC 1,2 may be treated as no-op. WC 3 is reserved. */ | |
3879 | if (wc == 3) { | |
3880 | gen_invalid(ctx); | |
3881 | return; | |
3882 | } | |
3883 | ||
3884 | /* PL 1-3 are reserved. If WC=2 then the insn is treated as noop. */ | |
3885 | if (pl > 0 && wc != 2) { | |
3886 | gen_invalid(ctx); | |
3887 | return; | |
3888 | } | |
3889 | ||
3890 | } else { /* ISA300 */ | |
3891 | /* WC 1-3 are reserved */ | |
3892 | if (wc > 0) { | |
3893 | gen_invalid(ctx); | |
3894 | return; | |
3895 | } | |
3896 | } | |
3897 | ||
3898 | } else { | |
3899 | warn_report("wait instruction decoded with wrong ISA flags."); | |
3900 | gen_invalid(ctx); | |
3901 | return; | |
3902 | } | |
3903 | ||
3904 | /* | |
3905 | * wait without WC field or with WC=0 waits for an exception / interrupt | |
3906 | * to occur. | |
3907 | */ | |
3908 | if (wc == 0) { | |
7058ff52 | 3909 | TCGv_i32 t0 = tcg_constant_i32(1); |
0c9717ff NP |
3910 | tcg_gen_st_i32(t0, cpu_env, |
3911 | -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); | |
0c9717ff NP |
3912 | /* Stop translation, as the CPU is supposed to sleep from now */ |
3913 | gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); | |
3914 | } | |
3915 | ||
3916 | /* | |
3917 | * Other wait types must not just wait until an exception occurs because | |
3918 | * ignoring their other wake-up conditions could cause a hang. | |
3919 | * | |
3920 | * For v2.06 and 2.07, wc=1,2,3 are architected but may be implemented as | |
3921 | * no-ops. | |
3922 | * | |
3923 | * wc=1 and wc=3 explicitly allow the instruction to be treated as a no-op. | |
3924 | * | |
3925 | * wc=2 waits for an implementation-specific condition, such could be | |
3926 | * always true, so it can be implemented as a no-op. | |
3927 | * | |
3928 | * For v3.1, wc=1,2 are architected but may be implemented as no-ops. | |
3929 | * | |
3930 | * wc=1 (waitrsv) waits for an exception or a reservation to be lost. | |
3931 | * Reservation-loss may have implementation-specific conditions, so it | |
3932 | * can be implemented as a no-op. | |
3933 | * | |
3934 | * wc=2 waits for an exception or an amount of time to pass. This | |
3935 | * amount is implementation-specific so it can be implemented as a | |
3936 | * no-op. | |
3937 | * | |
3938 | * ISA v3.1 allows for execution to resume "in the rare case of | |
3939 | * an implementation-dependent event", so in any case software must | |
3940 | * not depend on the architected resumption condition to become | |
3941 | * true, so no-op implementations should be architecturally correct | |
3942 | * (if suboptimal). | |
3943 | */ | |
0db1b20e JM |
3944 | } |
3945 | ||
7778a575 BH |
3946 | #if defined(TARGET_PPC64) |
3947 | static void gen_doze(DisasContext *ctx) | |
3948 | { | |
3949 | #if defined(CONFIG_USER_ONLY) | |
9f0cf041 | 3950 | GEN_PRIV(ctx); |
7778a575 BH |
3951 | #else |
3952 | TCGv_i32 t; | |
3953 | ||
9f0cf041 | 3954 | CHK_HV(ctx); |
7058ff52 | 3955 | t = tcg_constant_i32(PPC_PM_DOZE); |
7778a575 | 3956 | gen_helper_pminsn(cpu_env, t); |
154c69f2 BH |
3957 | /* Stop translation, as the CPU is supposed to sleep from now */ |
3958 | gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); | |
7778a575 BH |
3959 | #endif /* defined(CONFIG_USER_ONLY) */ |
3960 | } | |
3961 | ||
3962 | static void gen_nap(DisasContext *ctx) | |
3963 | { | |
3964 | #if defined(CONFIG_USER_ONLY) | |
9f0cf041 | 3965 | GEN_PRIV(ctx); |
7778a575 BH |
3966 | #else |
3967 | TCGv_i32 t; | |
3968 | ||
9f0cf041 | 3969 | CHK_HV(ctx); |
7058ff52 | 3970 | t = tcg_constant_i32(PPC_PM_NAP); |
7778a575 | 3971 | gen_helper_pminsn(cpu_env, t); |
154c69f2 BH |
3972 | /* Stop translation, as the CPU is supposed to sleep from now */ |
3973 | gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); | |
7778a575 BH |
3974 | #endif /* defined(CONFIG_USER_ONLY) */ |
3975 | } | |
3976 | ||
cdee0e72 ND |
3977 | static void gen_stop(DisasContext *ctx) |
3978 | { | |
21c0d66a | 3979 | #if defined(CONFIG_USER_ONLY) |
9f0cf041 | 3980 | GEN_PRIV(ctx); |
21c0d66a BH |
3981 | #else |
3982 | TCGv_i32 t; | |
3983 | ||
9f0cf041 | 3984 | CHK_HV(ctx); |
7058ff52 | 3985 | t = tcg_constant_i32(PPC_PM_STOP); |
21c0d66a | 3986 | gen_helper_pminsn(cpu_env, t); |
21c0d66a BH |
3987 | /* Stop translation, as the CPU is supposed to sleep from now */ |
3988 | gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); | |
3989 | #endif /* defined(CONFIG_USER_ONLY) */ | |
cdee0e72 ND |
3990 | } |
3991 | ||
7778a575 BH |
3992 | static void gen_sleep(DisasContext *ctx) |
3993 | { | |
3994 | #if defined(CONFIG_USER_ONLY) | |
9f0cf041 | 3995 | GEN_PRIV(ctx); |
7778a575 BH |
3996 | #else |
3997 | TCGv_i32 t; | |
3998 | ||
9f0cf041 | 3999 | CHK_HV(ctx); |
7058ff52 | 4000 | t = tcg_constant_i32(PPC_PM_SLEEP); |
7778a575 | 4001 | gen_helper_pminsn(cpu_env, t); |
154c69f2 BH |
4002 | /* Stop translation, as the CPU is supposed to sleep from now */ |
4003 | gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); | |
7778a575 BH |
4004 | #endif /* defined(CONFIG_USER_ONLY) */ |
4005 | } | |
4006 | ||
4007 | static void gen_rvwinkle(DisasContext *ctx) | |
4008 | { | |
4009 | #if defined(CONFIG_USER_ONLY) | |
9f0cf041 | 4010 | GEN_PRIV(ctx); |
7778a575 BH |
4011 | #else |
4012 | TCGv_i32 t; | |
4013 | ||
9f0cf041 | 4014 | CHK_HV(ctx); |
7058ff52 | 4015 | t = tcg_constant_i32(PPC_PM_RVWINKLE); |
7778a575 | 4016 | gen_helper_pminsn(cpu_env, t); |
154c69f2 BH |
4017 | /* Stop translation, as the CPU is supposed to sleep from now */ |
4018 | gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); | |
7778a575 BH |
4019 | #endif /* defined(CONFIG_USER_ONLY) */ |
4020 | } | |
4021 | #endif /* #if defined(TARGET_PPC64) */ | |
4022 | ||
697ab892 DG |
4023 | static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) |
4024 | { | |
4025 | #if defined(TARGET_PPC64) | |
efe843d8 | 4026 | if (ctx->has_cfar) { |
697ab892 | 4027 | tcg_gen_movi_tl(cpu_cfar, nip); |
efe843d8 | 4028 | } |
697ab892 DG |
4029 | #endif |
4030 | } | |
4031 | ||
46d396bd DHB |
4032 | #if defined(TARGET_PPC64) |
4033 | static void pmu_count_insns(DisasContext *ctx) | |
4034 | { | |
4035 | /* | |
4036 | * Do not bother calling the helper if the PMU isn't counting | |
4037 | * instructions. | |
4038 | */ | |
4039 | if (!ctx->pmu_insn_cnt) { | |
4040 | return; | |
4041 | } | |
4042 | ||
4043 | #if !defined(CONFIG_USER_ONLY) | |
eeaaefe9 LL |
4044 | TCGLabel *l; |
4045 | TCGv t0; | |
4046 | ||
46d396bd DHB |
4047 | /* |
4048 | * The PMU insns_inc() helper stops the internal PMU timer if a | |
4049 | * counter overflows happens. In that case, if the guest is | |
4050 | * running with icount and we do not handle it beforehand, | |
4051 | * the helper can trigger a 'bad icount read'. | |
4052 | */ | |
283a9177 | 4053 | translator_io_start(&ctx->base); |
46d396bd | 4054 | |
eeaaefe9 LL |
4055 | /* Avoid helper calls when only PMC5-6 are enabled. */ |
4056 | if (!ctx->pmc_other) { | |
4057 | l = gen_new_label(); | |
4058 | t0 = tcg_temp_new(); | |
4059 | ||
4060 | gen_load_spr(t0, SPR_POWER_PMC5); | |
4061 | tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); | |
4062 | gen_store_spr(SPR_POWER_PMC5, t0); | |
4063 | /* Check for overflow, if it's enabled */ | |
4064 | if (ctx->mmcr0_pmcjce) { | |
4065 | tcg_gen_brcondi_tl(TCG_COND_LT, t0, PMC_COUNTER_NEGATIVE_VAL, l); | |
4066 | gen_helper_handle_pmc5_overflow(cpu_env); | |
4067 | } | |
4068 | ||
4069 | gen_set_label(l); | |
eeaaefe9 LL |
4070 | } else { |
4071 | gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns)); | |
4072 | } | |
4073 | #else | |
46d396bd DHB |
4074 | /* |
4075 | * User mode can read (but not write) PMC5 and start/stop | |
4076 | * the PMU via MMCR0_FC. In this case just increment | |
4077 | * PMC5 with base.num_insns. | |
4078 | */ | |
4079 | TCGv t0 = tcg_temp_new(); | |
4080 | ||
4081 | gen_load_spr(t0, SPR_POWER_PMC5); | |
4082 | tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); | |
4083 | gen_store_spr(SPR_POWER_PMC5, t0); | |
eeaaefe9 | 4084 | #endif /* #if !defined(CONFIG_USER_ONLY) */ |
46d396bd DHB |
4085 | } |
4086 | #else | |
4087 | static void pmu_count_insns(DisasContext *ctx) | |
4088 | { | |
4089 | return; | |
4090 | } | |
4091 | #endif /* #if defined(TARGET_PPC64) */ | |
4092 | ||
90aa39a1 SF |
4093 | static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) |
4094 | { | |
6e9cc373 | 4095 | return translator_use_goto_tb(&ctx->base, dest); |
90aa39a1 SF |
4096 | } |
4097 | ||
0e3bf489 RK |
4098 | static void gen_lookup_and_goto_ptr(DisasContext *ctx) |
4099 | { | |
9498d103 RH |
4100 | if (unlikely(ctx->singlestep_enabled)) { |
4101 | gen_debug_exception(ctx); | |
0e3bf489 | 4102 | } else { |
46d396bd DHB |
4103 | /* |
4104 | * tcg_gen_lookup_and_goto_ptr will exit the TB if | |
4105 | * CF_NO_GOTO_PTR is set. Count insns now. | |
4106 | */ | |
4107 | if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { | |
4108 | pmu_count_insns(ctx); | |
4109 | } | |
4110 | ||
0e3bf489 RK |
4111 | tcg_gen_lookup_and_goto_ptr(); |
4112 | } | |
4113 | } | |
4114 | ||
79aceca5 | 4115 | /*** Branch ***/ |
c4a2e3a9 | 4116 | static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) |
c1942362 | 4117 | { |
e0c8f9ce | 4118 | if (NARROW_MODE(ctx)) { |
a2ffb812 | 4119 | dest = (uint32_t) dest; |
e0c8f9ce | 4120 | } |
90aa39a1 | 4121 | if (use_goto_tb(ctx, dest)) { |
46d396bd | 4122 | pmu_count_insns(ctx); |
57fec1fe | 4123 | tcg_gen_goto_tb(n); |
a2ffb812 | 4124 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
07ea28b4 | 4125 | tcg_gen_exit_tb(ctx->base.tb, n); |
c1942362 | 4126 | } else { |
a2ffb812 | 4127 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
0e3bf489 | 4128 | gen_lookup_and_goto_ptr(ctx); |
c1942362 | 4129 | } |
c53be334 FB |
4130 | } |
4131 | ||
636aa200 | 4132 | static inline void gen_setlr(DisasContext *ctx, target_ulong nip) |
e1833e1f | 4133 | { |
e0c8f9ce RH |
4134 | if (NARROW_MODE(ctx)) { |
4135 | nip = (uint32_t)nip; | |
4136 | } | |
4137 | tcg_gen_movi_tl(cpu_lr, nip); | |
e1833e1f JM |
4138 | } |
4139 | ||
79aceca5 | 4140 | /* b ba bl bla */ |
99e300ef | 4141 | static void gen_b(DisasContext *ctx) |
79aceca5 | 4142 | { |
76a66253 | 4143 | target_ulong li, target; |
38a64f9d FB |
4144 | |
4145 | /* sign extend LI */ | |
e0c8f9ce RH |
4146 | li = LI(ctx->opcode); |
4147 | li = (li ^ 0x02000000) - 0x02000000; | |
4148 | if (likely(AA(ctx->opcode) == 0)) { | |
2c2bcb1b | 4149 | target = ctx->cia + li; |
e0c8f9ce | 4150 | } else { |
9a64fbe4 | 4151 | target = li; |
e0c8f9ce RH |
4152 | } |
4153 | if (LK(ctx->opcode)) { | |
b6bac4bc | 4154 | gen_setlr(ctx, ctx->base.pc_next); |
e0c8f9ce | 4155 | } |
2c2bcb1b | 4156 | gen_update_cfar(ctx, ctx->cia); |
c1942362 | 4157 | gen_goto_tb(ctx, 0, target); |
6086c751 | 4158 | ctx->base.is_jmp = DISAS_NORETURN; |
79aceca5 FB |
4159 | } |
4160 | ||
e98a6e40 FB |
4161 | #define BCOND_IM 0 |
4162 | #define BCOND_LR 1 | |
4163 | #define BCOND_CTR 2 | |
52a4984d | 4164 | #define BCOND_TAR 3 |
e98a6e40 | 4165 | |
c4a2e3a9 | 4166 | static void gen_bcond(DisasContext *ctx, int type) |
d9bce9d9 | 4167 | { |
d9bce9d9 | 4168 | uint32_t bo = BO(ctx->opcode); |
42a268c2 | 4169 | TCGLabel *l1; |
a2ffb812 | 4170 | TCGv target; |
0e3bf489 | 4171 | |
52a4984d | 4172 | if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { |
9723281f | 4173 | target = tcg_temp_new(); |
efe843d8 | 4174 | if (type == BCOND_CTR) { |
a2ffb812 | 4175 | tcg_gen_mov_tl(target, cpu_ctr); |
efe843d8 | 4176 | } else if (type == BCOND_TAR) { |
52a4984d | 4177 | gen_load_spr(target, SPR_TAR); |
efe843d8 | 4178 | } else { |
a2ffb812 | 4179 | tcg_gen_mov_tl(target, cpu_lr); |
efe843d8 | 4180 | } |
d2e9fd8f | 4181 | } else { |
f764718d | 4182 | target = NULL; |
e98a6e40 | 4183 | } |
efe843d8 | 4184 | if (LK(ctx->opcode)) { |
b6bac4bc | 4185 | gen_setlr(ctx, ctx->base.pc_next); |
efe843d8 | 4186 | } |
a2ffb812 AJ |
4187 | l1 = gen_new_label(); |
4188 | if ((bo & 0x4) == 0) { | |
4189 | /* Decrement and test CTR */ | |
a7812ae4 | 4190 | TCGv temp = tcg_temp_new(); |
fa200c95 GK |
4191 | |
4192 | if (type == BCOND_CTR) { | |
4193 | /* | |
4194 | * All ISAs up to v3 describe this form of bcctr as invalid but | |
4195 | * some processors, ie. 64-bit server processors compliant with | |
4196 | * arch 2.x, do implement a "test and decrement" logic instead, | |
15d68c5e GK |
4197 | * as described in their respective UMs. This logic involves CTR |
4198 | * to act as both the branch target and a counter, which makes | |
4199 | * it basically useless and thus never used in real code. | |
4200 | * | |
4201 | * This form was hence chosen to trigger extra micro-architectural | |
4202 | * side-effect on real HW needed for the Spectre v2 workaround. | |
4203 | * It is up to guests that implement such workaround, ie. linux, to | |
4204 | * use this form in a way it just triggers the side-effect without | |
4205 | * doing anything else harmful. | |
fa200c95 | 4206 | */ |
d0db7cad | 4207 | if (unlikely(!is_book3s_arch2x(ctx))) { |
fa200c95 | 4208 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
fa200c95 GK |
4209 | return; |
4210 | } | |
4211 | ||
4212 | if (NARROW_MODE(ctx)) { | |
4213 | tcg_gen_ext32u_tl(temp, cpu_ctr); | |
4214 | } else { | |
4215 | tcg_gen_mov_tl(temp, cpu_ctr); | |
4216 | } | |
4217 | if (bo & 0x2) { | |
4218 | tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); | |
4219 | } else { | |
4220 | tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); | |
4221 | } | |
4222 | tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); | |
a2ffb812 | 4223 | } else { |
fa200c95 GK |
4224 | tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); |
4225 | if (NARROW_MODE(ctx)) { | |
4226 | tcg_gen_ext32u_tl(temp, cpu_ctr); | |
4227 | } else { | |
4228 | tcg_gen_mov_tl(temp, cpu_ctr); | |
4229 | } | |
4230 | if (bo & 0x2) { | |
4231 | tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); | |
4232 | } else { | |
4233 | tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); | |
4234 | } | |
e98a6e40 | 4235 | } |
a2ffb812 AJ |
4236 | } |
4237 | if ((bo & 0x10) == 0) { | |
4238 | /* Test CR */ | |
4239 | uint32_t bi = BI(ctx->opcode); | |
8f9fb7ac | 4240 | uint32_t mask = 0x08 >> (bi & 0x03); |
a7812ae4 | 4241 | TCGv_i32 temp = tcg_temp_new_i32(); |
a2ffb812 | 4242 | |
d9bce9d9 | 4243 | if (bo & 0x8) { |
a2ffb812 AJ |
4244 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
4245 | tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); | |
d9bce9d9 | 4246 | } else { |
a2ffb812 AJ |
4247 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
4248 | tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); | |
d9bce9d9 JM |
4249 | } |
4250 | } | |
2c2bcb1b | 4251 | gen_update_cfar(ctx, ctx->cia); |
e98a6e40 | 4252 | if (type == BCOND_IM) { |
a2ffb812 AJ |
4253 | target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); |
4254 | if (likely(AA(ctx->opcode) == 0)) { | |
2c2bcb1b | 4255 | gen_goto_tb(ctx, 0, ctx->cia + li); |
a2ffb812 AJ |
4256 | } else { |
4257 | gen_goto_tb(ctx, 0, li); | |
4258 | } | |
e98a6e40 | 4259 | } else { |
e0c8f9ce | 4260 | if (NARROW_MODE(ctx)) { |
a2ffb812 | 4261 | tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); |
e0c8f9ce | 4262 | } else { |
a2ffb812 | 4263 | tcg_gen_andi_tl(cpu_nip, target, ~3); |
e0c8f9ce | 4264 | } |
0e3bf489 | 4265 | gen_lookup_and_goto_ptr(ctx); |
c80d1df5 | 4266 | } |
c4a2e3a9 | 4267 | if ((bo & 0x14) != 0x14) { |
0e3bf489 | 4268 | /* fallthrough case */ |
c4a2e3a9 | 4269 | gen_set_label(l1); |
b6bac4bc | 4270 | gen_goto_tb(ctx, 1, ctx->base.pc_next); |
c4a2e3a9 | 4271 | } |
6086c751 | 4272 | ctx->base.is_jmp = DISAS_NORETURN; |
e98a6e40 FB |
4273 | } |
4274 | ||
99e300ef | 4275 | static void gen_bc(DisasContext *ctx) |
3b46e624 | 4276 | { |
e98a6e40 FB |
4277 | gen_bcond(ctx, BCOND_IM); |
4278 | } | |
4279 | ||
99e300ef | 4280 | static void gen_bcctr(DisasContext *ctx) |
3b46e624 | 4281 | { |
e98a6e40 FB |
4282 | gen_bcond(ctx, BCOND_CTR); |
4283 | } | |
4284 | ||
99e300ef | 4285 | static void gen_bclr(DisasContext *ctx) |
3b46e624 | 4286 | { |
e98a6e40 FB |
4287 | gen_bcond(ctx, BCOND_LR); |
4288 | } | |
79aceca5 | 4289 | |
52a4984d TM |
4290 | static void gen_bctar(DisasContext *ctx) |
4291 | { | |
4292 | gen_bcond(ctx, BCOND_TAR); | |
4293 | } | |
4294 | ||
79aceca5 | 4295 | /*** Condition register logical ***/ |
e1571908 | 4296 | #define GEN_CRLOGIC(name, tcg_op, opc) \ |
efe843d8 | 4297 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 4298 | { \ |
fc0d441e JM |
4299 | uint8_t bitmask; \ |
4300 | int sh; \ | |
a7812ae4 | 4301 | TCGv_i32 t0, t1; \ |
fc0d441e | 4302 | sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ |
a7812ae4 | 4303 | t0 = tcg_temp_new_i32(); \ |
fc0d441e | 4304 | if (sh > 0) \ |
fea0c503 | 4305 | tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ |
fc0d441e | 4306 | else if (sh < 0) \ |
fea0c503 | 4307 | tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ |
e1571908 | 4308 | else \ |
fea0c503 | 4309 | tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ |
a7812ae4 | 4310 | t1 = tcg_temp_new_i32(); \ |
fc0d441e JM |
4311 | sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ |
4312 | if (sh > 0) \ | |
fea0c503 | 4313 | tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ |
fc0d441e | 4314 | else if (sh < 0) \ |
fea0c503 | 4315 | tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ |
e1571908 | 4316 | else \ |
fea0c503 AJ |
4317 | tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ |
4318 | tcg_op(t0, t0, t1); \ | |
8f9fb7ac | 4319 | bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ |
fea0c503 AJ |
4320 | tcg_gen_andi_i32(t0, t0, bitmask); \ |
4321 | tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ | |
4322 | tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ | |
79aceca5 FB |
4323 | } |
4324 | ||
4325 | /* crand */ | |
e1571908 | 4326 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); |
79aceca5 | 4327 | /* crandc */ |
e1571908 | 4328 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); |
79aceca5 | 4329 | /* creqv */ |
e1571908 | 4330 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); |
79aceca5 | 4331 | /* crnand */ |
e1571908 | 4332 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); |
79aceca5 | 4333 | /* crnor */ |
e1571908 | 4334 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); |
79aceca5 | 4335 | /* cror */ |
e1571908 | 4336 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); |
79aceca5 | 4337 | /* crorc */ |
e1571908 | 4338 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); |
79aceca5 | 4339 | /* crxor */ |
e1571908 | 4340 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); |
99e300ef | 4341 | |
54623277 | 4342 | /* mcrf */ |
99e300ef | 4343 | static void gen_mcrf(DisasContext *ctx) |
79aceca5 | 4344 | { |
47e4661c | 4345 | tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); |
79aceca5 FB |
4346 | } |
4347 | ||
4348 | /*** System linkage ***/ | |
99e300ef | 4349 | |
c47493f2 | 4350 | /* rfi (supervisor only) */ |
99e300ef | 4351 | static void gen_rfi(DisasContext *ctx) |
79aceca5 | 4352 | { |
9a64fbe4 | 4353 | #if defined(CONFIG_USER_ONLY) |
9f0cf041 | 4354 | GEN_PRIV(ctx); |
9a64fbe4 | 4355 | #else |
efe843d8 DG |
4356 | /* |
4357 | * This instruction doesn't exist anymore on 64-bit server | |
6ca038c2 | 4358 | * processors compliant with arch 2.x |
a2e71b28 | 4359 | */ |
d0db7cad | 4360 | if (is_book3s_arch2x(ctx)) { |
6ca038c2 BH |
4361 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
4362 | return; | |
4363 | } | |
9a64fbe4 | 4364 | /* Restore CPU state */ |
9f0cf041 | 4365 | CHK_SV(ctx); |
283a9177 | 4366 | translator_io_start(&ctx->base); |
2c2bcb1b | 4367 | gen_update_cfar(ctx, ctx->cia); |
e5f17ac6 | 4368 | gen_helper_rfi(cpu_env); |
59bf23fa | 4369 | ctx->base.is_jmp = DISAS_EXIT; |
9a64fbe4 | 4370 | #endif |
79aceca5 FB |
4371 | } |
4372 | ||
426613db | 4373 | #if defined(TARGET_PPC64) |
99e300ef | 4374 | static void gen_rfid(DisasContext *ctx) |
426613db JM |
4375 | { |
4376 | #if defined(CONFIG_USER_ONLY) | |
9f0cf041 | 4377 | GEN_PRIV(ctx); |
426613db JM |
4378 | #else |
4379 | /* Restore CPU state */ | |
9f0cf041 | 4380 | CHK_SV(ctx); |
283a9177 | 4381 | translator_io_start(&ctx->base); |
2c2bcb1b | 4382 | gen_update_cfar(ctx, ctx->cia); |
e5f17ac6 | 4383 | gen_helper_rfid(cpu_env); |
59bf23fa | 4384 | ctx->base.is_jmp = DISAS_EXIT; |
426613db JM |
4385 | #endif |
4386 | } | |
426613db | 4387 | |
3c89b8d6 NP |
4388 | #if !defined(CONFIG_USER_ONLY) |
4389 | static void gen_rfscv(DisasContext *ctx) | |
4390 | { | |
4391 | #if defined(CONFIG_USER_ONLY) | |
9f0cf041 | 4392 | GEN_PRIV(ctx); |
3c89b8d6 NP |
4393 | #else |
4394 | /* Restore CPU state */ | |
9f0cf041 | 4395 | CHK_SV(ctx); |
283a9177 | 4396 | translator_io_start(&ctx->base); |
2c2bcb1b | 4397 | gen_update_cfar(ctx, ctx->cia); |
3c89b8d6 | 4398 | gen_helper_rfscv(cpu_env); |
59bf23fa | 4399 | ctx->base.is_jmp = DISAS_EXIT; |
3c89b8d6 NP |
4400 | #endif |
4401 | } | |
4402 | #endif | |
4403 | ||
99e300ef | 4404 | static void gen_hrfid(DisasContext *ctx) |
be147d08 JM |
4405 | { |
4406 | #if defined(CONFIG_USER_ONLY) | |
9f0cf041 | 4407 | GEN_PRIV(ctx); |
be147d08 JM |
4408 | #else |
4409 | /* Restore CPU state */ | |
9f0cf041 | 4410 | CHK_HV(ctx); |
e5f17ac6 | 4411 | gen_helper_hrfid(cpu_env); |
59bf23fa | 4412 | ctx->base.is_jmp = DISAS_EXIT; |
be147d08 JM |
4413 | #endif |
4414 | } | |
4415 | #endif | |
4416 | ||
79aceca5 | 4417 | /* sc */ |
417bf010 JM |
4418 | #if defined(CONFIG_USER_ONLY) |
4419 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER | |
4420 | #else | |
4421 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL | |
3c89b8d6 | 4422 | #define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED |
417bf010 | 4423 | #endif |
99e300ef | 4424 | static void gen_sc(DisasContext *ctx) |
79aceca5 | 4425 | { |
e1833e1f JM |
4426 | uint32_t lev; |
4427 | ||
4428 | lev = (ctx->opcode >> 5) & 0x7F; | |
e06fcd75 | 4429 | gen_exception_err(ctx, POWERPC_SYSCALL, lev); |
79aceca5 FB |
4430 | } |
4431 | ||
3c89b8d6 NP |
4432 | #if defined(TARGET_PPC64) |
4433 | #if !defined(CONFIG_USER_ONLY) | |
4434 | static void gen_scv(DisasContext *ctx) | |
4435 | { | |
f43520e5 | 4436 | uint32_t lev = (ctx->opcode >> 5) & 0x7F; |
3c89b8d6 | 4437 | |
f43520e5 | 4438 | /* Set the PC back to the faulting instruction. */ |
7a3fe174 | 4439 | gen_update_nip(ctx, ctx->cia); |
f43520e5 | 4440 | gen_helper_scv(cpu_env, tcg_constant_i32(lev)); |
3c89b8d6 | 4441 | |
7a3fe174 | 4442 | ctx->base.is_jmp = DISAS_NORETURN; |
3c89b8d6 NP |
4443 | } |
4444 | #endif | |
4445 | #endif | |
4446 | ||
79aceca5 | 4447 | /*** Trap ***/ |
99e300ef | 4448 | |
22b56ee5 BH |
4449 | /* Check for unconditional traps (always or never) */ |
4450 | static bool check_unconditional_trap(DisasContext *ctx) | |
4451 | { | |
4452 | /* Trap never */ | |
4453 | if (TO(ctx->opcode) == 0) { | |
4454 | return true; | |
4455 | } | |
4456 | /* Trap always */ | |
4457 | if (TO(ctx->opcode) == 31) { | |
4458 | gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); | |
4459 | return true; | |
4460 | } | |
4461 | return false; | |
4462 | } | |
4463 | ||
54623277 | 4464 | /* tw */ |
99e300ef | 4465 | static void gen_tw(DisasContext *ctx) |
79aceca5 | 4466 | { |
22b56ee5 BH |
4467 | TCGv_i32 t0; |
4468 | ||
4469 | if (check_unconditional_trap(ctx)) { | |
4470 | return; | |
4471 | } | |
7058ff52 | 4472 | t0 = tcg_constant_i32(TO(ctx->opcode)); |
e5f17ac6 BS |
4473 | gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
4474 | t0); | |
79aceca5 FB |
4475 | } |
4476 | ||
4477 | /* twi */ | |
99e300ef | 4478 | static void gen_twi(DisasContext *ctx) |
79aceca5 | 4479 | { |
22b56ee5 BH |
4480 | TCGv t0; |
4481 | TCGv_i32 t1; | |
4482 | ||
4483 | if (check_unconditional_trap(ctx)) { | |
4484 | return; | |
4485 | } | |
7058ff52 RH |
4486 | t0 = tcg_constant_tl(SIMM(ctx->opcode)); |
4487 | t1 = tcg_constant_i32(TO(ctx->opcode)); | |
e5f17ac6 | 4488 | gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); |
79aceca5 FB |
4489 | } |
4490 | ||
d9bce9d9 JM |
4491 | #if defined(TARGET_PPC64) |
4492 | /* td */ | |
99e300ef | 4493 | static void gen_td(DisasContext *ctx) |
d9bce9d9 | 4494 | { |
22b56ee5 BH |
4495 | TCGv_i32 t0; |
4496 | ||
4497 | if (check_unconditional_trap(ctx)) { | |
4498 | return; | |
4499 | } | |
7058ff52 | 4500 | t0 = tcg_constant_i32(TO(ctx->opcode)); |
e5f17ac6 BS |
4501 | gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
4502 | t0); | |
d9bce9d9 JM |
4503 | } |
4504 | ||
4505 | /* tdi */ | |
99e300ef | 4506 | static void gen_tdi(DisasContext *ctx) |
d9bce9d9 | 4507 | { |
22b56ee5 BH |
4508 | TCGv t0; |
4509 | TCGv_i32 t1; | |
4510 | ||
4511 | if (check_unconditional_trap(ctx)) { | |
4512 | return; | |
4513 | } | |
7058ff52 RH |
4514 | t0 = tcg_constant_tl(SIMM(ctx->opcode)); |
4515 | t1 = tcg_constant_i32(TO(ctx->opcode)); | |
e5f17ac6 | 4516 | gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); |
d9bce9d9 JM |
4517 | } |
4518 | #endif | |
4519 | ||
79aceca5 | 4520 | /*** Processor control ***/ |
99e300ef | 4521 | |
54623277 | 4522 | /* mcrxr */ |
99e300ef | 4523 | static void gen_mcrxr(DisasContext *ctx) |
79aceca5 | 4524 | { |
da91a00f RH |
4525 | TCGv_i32 t0 = tcg_temp_new_i32(); |
4526 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
4527 | TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; | |
4528 | ||
4529 | tcg_gen_trunc_tl_i32(t0, cpu_so); | |
4530 | tcg_gen_trunc_tl_i32(t1, cpu_ov); | |
4531 | tcg_gen_trunc_tl_i32(dst, cpu_ca); | |
294d1292 SB |
4532 | tcg_gen_shli_i32(t0, t0, 3); |
4533 | tcg_gen_shli_i32(t1, t1, 2); | |
4534 | tcg_gen_shli_i32(dst, dst, 1); | |
da91a00f RH |
4535 | tcg_gen_or_i32(dst, dst, t0); |
4536 | tcg_gen_or_i32(dst, dst, t1); | |
da91a00f RH |
4537 | |
4538 | tcg_gen_movi_tl(cpu_so, 0); | |
4539 | tcg_gen_movi_tl(cpu_ov, 0); | |
4540 | tcg_gen_movi_tl(cpu_ca, 0); | |
79aceca5 FB |
4541 | } |
4542 | ||
b63d0434 ND |
4543 | #ifdef TARGET_PPC64 |
4544 | /* mcrxrx */ | |
4545 | static void gen_mcrxrx(DisasContext *ctx) | |
4546 | { | |
4547 | TCGv t0 = tcg_temp_new(); | |
4548 | TCGv t1 = tcg_temp_new(); | |
4549 | TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; | |
4550 | ||
4551 | /* copy OV and OV32 */ | |
4552 | tcg_gen_shli_tl(t0, cpu_ov, 1); | |
4553 | tcg_gen_or_tl(t0, t0, cpu_ov32); | |
4554 | tcg_gen_shli_tl(t0, t0, 2); | |
4555 | /* copy CA and CA32 */ | |
4556 | tcg_gen_shli_tl(t1, cpu_ca, 1); | |
4557 | tcg_gen_or_tl(t1, t1, cpu_ca32); | |
4558 | tcg_gen_or_tl(t0, t0, t1); | |
4559 | tcg_gen_trunc_tl_i32(dst, t0); | |
b63d0434 ND |
4560 | } |
4561 | #endif | |
4562 | ||
0cfe11ea | 4563 | /* mfcr mfocrf */ |
99e300ef | 4564 | static void gen_mfcr(DisasContext *ctx) |
79aceca5 | 4565 | { |
76a66253 | 4566 | uint32_t crm, crn; |
3b46e624 | 4567 | |
76a66253 JM |
4568 | if (likely(ctx->opcode & 0x00100000)) { |
4569 | crm = CRM(ctx->opcode); | |
8dd640e4 | 4570 | if (likely(crm && ((crm & (crm - 1)) == 0))) { |
efe843d8 | 4571 | crn = ctz32(crm); |
e1571908 | 4572 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); |
0497d2f4 AJ |
4573 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], |
4574 | cpu_gpr[rD(ctx->opcode)], crn * 4); | |
76a66253 | 4575 | } |
d9bce9d9 | 4576 | } else { |
651721b2 AJ |
4577 | TCGv_i32 t0 = tcg_temp_new_i32(); |
4578 | tcg_gen_mov_i32(t0, cpu_crf[0]); | |
4579 | tcg_gen_shli_i32(t0, t0, 4); | |
4580 | tcg_gen_or_i32(t0, t0, cpu_crf[1]); | |
4581 | tcg_gen_shli_i32(t0, t0, 4); | |
4582 | tcg_gen_or_i32(t0, t0, cpu_crf[2]); | |
4583 | tcg_gen_shli_i32(t0, t0, 4); | |
4584 | tcg_gen_or_i32(t0, t0, cpu_crf[3]); | |
4585 | tcg_gen_shli_i32(t0, t0, 4); | |
4586 | tcg_gen_or_i32(t0, t0, cpu_crf[4]); | |
4587 | tcg_gen_shli_i32(t0, t0, 4); | |
4588 | tcg_gen_or_i32(t0, t0, cpu_crf[5]); | |
4589 | tcg_gen_shli_i32(t0, t0, 4); | |
4590 | tcg_gen_or_i32(t0, t0, cpu_crf[6]); | |
4591 | tcg_gen_shli_i32(t0, t0, 4); | |
4592 | tcg_gen_or_i32(t0, t0, cpu_crf[7]); | |
4593 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
d9bce9d9 | 4594 | } |
79aceca5 FB |
4595 | } |
4596 | ||
4597 | /* mfmsr */ | |
99e300ef | 4598 | static void gen_mfmsr(DisasContext *ctx) |
79aceca5 | 4599 | { |
9f0cf041 | 4600 | CHK_SV(ctx); |
6527f6ea | 4601 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); |
79aceca5 FB |
4602 | } |
4603 | ||
4604 | /* mfspr */ | |
636aa200 | 4605 | static inline void gen_op_mfspr(DisasContext *ctx) |
79aceca5 | 4606 | { |
69b058c8 | 4607 | void (*read_cb)(DisasContext *ctx, int gprn, int sprn); |
79aceca5 FB |
4608 | uint32_t sprn = SPR(ctx->opcode); |
4609 | ||
eb94268e BH |
4610 | #if defined(CONFIG_USER_ONLY) |
4611 | read_cb = ctx->spr_cb[sprn].uea_read; | |
4612 | #else | |
4613 | if (ctx->pr) { | |
4614 | read_cb = ctx->spr_cb[sprn].uea_read; | |
4615 | } else if (ctx->hv) { | |
be147d08 | 4616 | read_cb = ctx->spr_cb[sprn].hea_read; |
eb94268e | 4617 | } else { |
3fc6c082 | 4618 | read_cb = ctx->spr_cb[sprn].oea_read; |
eb94268e | 4619 | } |
9a64fbe4 | 4620 | #endif |
76a66253 JM |
4621 | if (likely(read_cb != NULL)) { |
4622 | if (likely(read_cb != SPR_NOACCESS)) { | |
45d827d2 | 4623 | (*read_cb)(ctx, rD(ctx->opcode), sprn); |
3fc6c082 FB |
4624 | } else { |
4625 | /* Privilege exception */ | |
efe843d8 DG |
4626 | /* |
4627 | * This is a hack to avoid warnings when running Linux: | |
9fceefa7 JM |
4628 | * this OS breaks the PowerPC virtualisation model, |
4629 | * allowing userland application to read the PVR | |
4630 | */ | |
4631 | if (sprn != SPR_PVR) { | |
31085338 TH |
4632 | qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " |
4633 | "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, | |
2c2bcb1b | 4634 | ctx->cia); |
f24e5695 | 4635 | } |
9b2fadda | 4636 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); |
79aceca5 | 4637 | } |
3fc6c082 | 4638 | } else { |
9b2fadda BH |
4639 | /* ISA 2.07 defines these as no-ops */ |
4640 | if ((ctx->insns_flags2 & PPC2_ISA207S) && | |
4641 | (sprn >= 808 && sprn <= 811)) { | |
4642 | /* This is a nop */ | |
4643 | return; | |
4644 | } | |
3fc6c082 | 4645 | /* Not defined */ |
31085338 TH |
4646 | qemu_log_mask(LOG_GUEST_ERROR, |
4647 | "Trying to read invalid spr %d (0x%03x) at " | |
2c2bcb1b | 4648 | TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); |
9b2fadda | 4649 | |
efe843d8 DG |
4650 | /* |
4651 | * The behaviour depends on MSR:PR and SPR# bit 0x10, it can | |
4652 | * generate a priv, a hv emu or a no-op | |
9b2fadda BH |
4653 | */ |
4654 | if (sprn & 0x10) { | |
4655 | if (ctx->pr) { | |
1315eed6 | 4656 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9b2fadda BH |
4657 | } |
4658 | } else { | |
4659 | if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { | |
1315eed6 | 4660 | gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9b2fadda | 4661 | } |
4d6a0680 | 4662 | } |
79aceca5 | 4663 | } |
79aceca5 FB |
4664 | } |
4665 | ||
99e300ef | 4666 | static void gen_mfspr(DisasContext *ctx) |
79aceca5 | 4667 | { |
3fc6c082 | 4668 | gen_op_mfspr(ctx); |
76a66253 | 4669 | } |
3fc6c082 FB |
4670 | |
4671 | /* mftb */ | |
99e300ef | 4672 | static void gen_mftb(DisasContext *ctx) |
3fc6c082 FB |
4673 | { |
4674 | gen_op_mfspr(ctx); | |
79aceca5 FB |
4675 | } |
4676 | ||
0cfe11ea | 4677 | /* mtcrf mtocrf*/ |
99e300ef | 4678 | static void gen_mtcrf(DisasContext *ctx) |
79aceca5 | 4679 | { |
76a66253 | 4680 | uint32_t crm, crn; |
3b46e624 | 4681 | |
76a66253 | 4682 | crm = CRM(ctx->opcode); |
8dd640e4 | 4683 | if (likely((ctx->opcode & 0x00100000))) { |
4684 | if (crm && ((crm & (crm - 1)) == 0)) { | |
4685 | TCGv_i32 temp = tcg_temp_new_i32(); | |
efe843d8 | 4686 | crn = ctz32(crm); |
8dd640e4 | 4687 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); |
0cfe11ea AJ |
4688 | tcg_gen_shri_i32(temp, temp, crn * 4); |
4689 | tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); | |
8dd640e4 | 4690 | } |
76a66253 | 4691 | } else { |
651721b2 AJ |
4692 | TCGv_i32 temp = tcg_temp_new_i32(); |
4693 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); | |
4694 | for (crn = 0 ; crn < 8 ; crn++) { | |
4695 | if (crm & (1 << crn)) { | |
4696 | tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); | |
4697 | tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); | |
4698 | } | |
4699 | } | |
76a66253 | 4700 | } |
79aceca5 FB |
4701 | } |
4702 | ||
4703 | /* mtmsr */ | |
426613db | 4704 | #if defined(TARGET_PPC64) |
99e300ef | 4705 | static void gen_mtmsrd(DisasContext *ctx) |
426613db | 4706 | { |
caf590dd NP |
4707 | if (unlikely(!is_book3s_arch2x(ctx))) { |
4708 | gen_invalid(ctx); | |
4709 | return; | |
4710 | } | |
4711 | ||
9f0cf041 | 4712 | CHK_SV(ctx); |
9b2fadda BH |
4713 | |
4714 | #if !defined(CONFIG_USER_ONLY) | |
6fa5726b MF |
4715 | TCGv t0, t1; |
4716 | target_ulong mask; | |
4717 | ||
4718 | t0 = tcg_temp_new(); | |
4719 | t1 = tcg_temp_new(); | |
4720 | ||
283a9177 | 4721 | translator_io_start(&ctx->base); |
6fa5726b | 4722 | |
be147d08 | 4723 | if (ctx->opcode & 0x00010000) { |
5ed19506 | 4724 | /* L=1 form only updates EE and RI */ |
6fa5726b | 4725 | mask = (1ULL << MSR_RI) | (1ULL << MSR_EE); |
be147d08 | 4726 | } else { |
6fa5726b MF |
4727 | /* mtmsrd does not alter HV, S, ME, or LE */ |
4728 | mask = ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) | | |
4729 | (1ULL << MSR_HV)); | |
efe843d8 DG |
4730 | /* |
4731 | * XXX: we need to update nip before the store if we enter | |
4732 | * power saving mode, we will exit the loop directly from | |
4733 | * ppc_store_msr | |
056b05f8 | 4734 | */ |
b6bac4bc | 4735 | gen_update_nip(ctx, ctx->base.pc_next); |
be147d08 | 4736 | } |
6fa5726b MF |
4737 | |
4738 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); | |
4739 | tcg_gen_andi_tl(t1, cpu_msr, ~mask); | |
4740 | tcg_gen_or_tl(t0, t0, t1); | |
4741 | ||
4742 | gen_helper_store_msr(cpu_env, t0); | |
4743 | ||
5ed19506 | 4744 | /* Must stop the translation as machine state (may have) changed */ |
d736de8f | 4745 | ctx->base.is_jmp = DISAS_EXIT_UPDATE; |
9b2fadda | 4746 | #endif /* !defined(CONFIG_USER_ONLY) */ |
426613db | 4747 | } |
9b2fadda | 4748 | #endif /* defined(TARGET_PPC64) */ |
426613db | 4749 | |
99e300ef | 4750 | static void gen_mtmsr(DisasContext *ctx) |
79aceca5 | 4751 | { |
9f0cf041 | 4752 | CHK_SV(ctx); |
9b2fadda BH |
4753 | |
4754 | #if !defined(CONFIG_USER_ONLY) | |
6fa5726b MF |
4755 | TCGv t0, t1; |
4756 | target_ulong mask = 0xFFFFFFFF; | |
4757 | ||
4758 | t0 = tcg_temp_new(); | |
4759 | t1 = tcg_temp_new(); | |
4760 | ||
283a9177 | 4761 | translator_io_start(&ctx->base); |
5ed19506 NP |
4762 | if (ctx->opcode & 0x00010000) { |
4763 | /* L=1 form only updates EE and RI */ | |
6fa5726b | 4764 | mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE); |
be147d08 | 4765 | } else { |
6fa5726b MF |
4766 | /* mtmsr does not alter S, ME, or LE */ |
4767 | mask &= ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S)); | |
8018dc63 | 4768 | |
efe843d8 DG |
4769 | /* |
4770 | * XXX: we need to update nip before the store if we enter | |
4771 | * power saving mode, we will exit the loop directly from | |
4772 | * ppc_store_msr | |
056b05f8 | 4773 | */ |
b6bac4bc | 4774 | gen_update_nip(ctx, ctx->base.pc_next); |
be147d08 | 4775 | } |
6fa5726b MF |
4776 | |
4777 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); | |
4778 | tcg_gen_andi_tl(t1, cpu_msr, ~mask); | |
4779 | tcg_gen_or_tl(t0, t0, t1); | |
4780 | ||
4781 | gen_helper_store_msr(cpu_env, t0); | |
4782 | ||
5ed19506 | 4783 | /* Must stop the translation as machine state (may have) changed */ |
d736de8f | 4784 | ctx->base.is_jmp = DISAS_EXIT_UPDATE; |
9a64fbe4 | 4785 | #endif |
79aceca5 FB |
4786 | } |
4787 | ||
4788 | /* mtspr */ | |
99e300ef | 4789 | static void gen_mtspr(DisasContext *ctx) |
79aceca5 | 4790 | { |
69b058c8 | 4791 | void (*write_cb)(DisasContext *ctx, int sprn, int gprn); |
79aceca5 FB |
4792 | uint32_t sprn = SPR(ctx->opcode); |
4793 | ||
eb94268e BH |
4794 | #if defined(CONFIG_USER_ONLY) |
4795 | write_cb = ctx->spr_cb[sprn].uea_write; | |
4796 | #else | |
4797 | if (ctx->pr) { | |
4798 | write_cb = ctx->spr_cb[sprn].uea_write; | |
4799 | } else if (ctx->hv) { | |
be147d08 | 4800 | write_cb = ctx->spr_cb[sprn].hea_write; |
eb94268e | 4801 | } else { |
3fc6c082 | 4802 | write_cb = ctx->spr_cb[sprn].oea_write; |
eb94268e | 4803 | } |
9a64fbe4 | 4804 | #endif |
76a66253 JM |
4805 | if (likely(write_cb != NULL)) { |
4806 | if (likely(write_cb != SPR_NOACCESS)) { | |
45d827d2 | 4807 | (*write_cb)(ctx, sprn, rS(ctx->opcode)); |
3fc6c082 FB |
4808 | } else { |
4809 | /* Privilege exception */ | |
31085338 TH |
4810 | qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " |
4811 | "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, | |
2c2bcb1b | 4812 | ctx->cia); |
9b2fadda | 4813 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 4814 | } |
3fc6c082 | 4815 | } else { |
9b2fadda BH |
4816 | /* ISA 2.07 defines these as no-ops */ |
4817 | if ((ctx->insns_flags2 & PPC2_ISA207S) && | |
4818 | (sprn >= 808 && sprn <= 811)) { | |
4819 | /* This is a nop */ | |
4820 | return; | |
4821 | } | |
4822 | ||
3fc6c082 | 4823 | /* Not defined */ |
31085338 TH |
4824 | qemu_log_mask(LOG_GUEST_ERROR, |
4825 | "Trying to write invalid spr %d (0x%03x) at " | |
2c2bcb1b | 4826 | TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); |
4d6a0680 | 4827 | |
9b2fadda | 4828 | |
efe843d8 DG |
4829 | /* |
4830 | * The behaviour depends on MSR:PR and SPR# bit 0x10, it can | |
4831 | * generate a priv, a hv emu or a no-op | |
9b2fadda BH |
4832 | */ |
4833 | if (sprn & 0x10) { | |
4834 | if (ctx->pr) { | |
1315eed6 | 4835 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9b2fadda BH |
4836 | } |
4837 | } else { | |
4838 | if (ctx->pr || sprn == 0) { | |
1315eed6 | 4839 | gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9b2fadda | 4840 | } |
4d6a0680 | 4841 | } |
79aceca5 | 4842 | } |
79aceca5 FB |
4843 | } |
4844 | ||
dc2ee038 VAS |
4845 | #if defined(TARGET_PPC64) |
4846 | /* setb */ | |
4847 | static void gen_setb(DisasContext *ctx) | |
4848 | { | |
4849 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
6f4912a4 PMD |
4850 | TCGv_i32 t8 = tcg_constant_i32(8); |
4851 | TCGv_i32 tm1 = tcg_constant_i32(-1); | |
dc2ee038 VAS |
4852 | int crf = crfS(ctx->opcode); |
4853 | ||
4854 | tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); | |
dc2ee038 VAS |
4855 | tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); |
4856 | tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
dc2ee038 VAS |
4857 | } |
4858 | #endif | |
4859 | ||
79aceca5 | 4860 | /*** Cache management ***/ |
99e300ef | 4861 | |
54623277 | 4862 | /* dcbf */ |
99e300ef | 4863 | static void gen_dcbf(DisasContext *ctx) |
79aceca5 | 4864 | { |
dac454af | 4865 | /* XXX: specification says this is treated as a load by the MMU */ |
76db3ba4 AJ |
4866 | TCGv t0; |
4867 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4868 | t0 = tcg_temp_new(); | |
4869 | gen_addr_reg_index(ctx, t0); | |
4870 | gen_qemu_ld8u(ctx, t0, t0); | |
79aceca5 FB |
4871 | } |
4872 | ||
50728199 RK |
4873 | /* dcbfep (external PID dcbf) */ |
4874 | static void gen_dcbfep(DisasContext *ctx) | |
4875 | { | |
4876 | /* XXX: specification says this is treated as a load by the MMU */ | |
4877 | TCGv t0; | |
9f0cf041 | 4878 | CHK_SV(ctx); |
50728199 RK |
4879 | gen_set_access_type(ctx, ACCESS_CACHE); |
4880 | t0 = tcg_temp_new(); | |
4881 | gen_addr_reg_index(ctx, t0); | |
4882 | tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); | |
50728199 RK |
4883 | } |
4884 | ||
79aceca5 | 4885 | /* dcbi (Supervisor only) */ |
99e300ef | 4886 | static void gen_dcbi(DisasContext *ctx) |
79aceca5 | 4887 | { |
a541f297 | 4888 | #if defined(CONFIG_USER_ONLY) |
9f0cf041 | 4889 | GEN_PRIV(ctx); |
a541f297 | 4890 | #else |
b61f2753 | 4891 | TCGv EA, val; |
9b2fadda | 4892 | |
9f0cf041 | 4893 | CHK_SV(ctx); |
a7812ae4 | 4894 | EA = tcg_temp_new(); |
76db3ba4 AJ |
4895 | gen_set_access_type(ctx, ACCESS_CACHE); |
4896 | gen_addr_reg_index(ctx, EA); | |
a7812ae4 | 4897 | val = tcg_temp_new(); |
76a66253 | 4898 | /* XXX: specification says this should be treated as a store by the MMU */ |
76db3ba4 AJ |
4899 | gen_qemu_ld8u(ctx, val, EA); |
4900 | gen_qemu_st8(ctx, val, EA); | |
9b2fadda | 4901 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4902 | } |
4903 | ||
4904 | /* dcdst */ | |
99e300ef | 4905 | static void gen_dcbst(DisasContext *ctx) |
79aceca5 | 4906 | { |
76a66253 | 4907 | /* XXX: specification say this is treated as a load by the MMU */ |
76db3ba4 AJ |
4908 | TCGv t0; |
4909 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4910 | t0 = tcg_temp_new(); | |
4911 | gen_addr_reg_index(ctx, t0); | |
4912 | gen_qemu_ld8u(ctx, t0, t0); | |
79aceca5 FB |
4913 | } |
4914 | ||
50728199 RK |
4915 | /* dcbstep (dcbstep External PID version) */ |
4916 | static void gen_dcbstep(DisasContext *ctx) | |
4917 | { | |
4918 | /* XXX: specification say this is treated as a load by the MMU */ | |
4919 | TCGv t0; | |
4920 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4921 | t0 = tcg_temp_new(); | |
4922 | gen_addr_reg_index(ctx, t0); | |
4923 | tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); | |
50728199 RK |
4924 | } |
4925 | ||
79aceca5 | 4926 | /* dcbt */ |
99e300ef | 4927 | static void gen_dcbt(DisasContext *ctx) |
79aceca5 | 4928 | { |
efe843d8 DG |
4929 | /* |
4930 | * interpreted as no-op | |
4931 | * XXX: specification say this is treated as a load by the MMU but | |
4932 | * does not generate any exception | |
76a66253 | 4933 | */ |
79aceca5 FB |
4934 | } |
4935 | ||
50728199 RK |
4936 | /* dcbtep */ |
4937 | static void gen_dcbtep(DisasContext *ctx) | |
4938 | { | |
efe843d8 DG |
4939 | /* |
4940 | * interpreted as no-op | |
4941 | * XXX: specification say this is treated as a load by the MMU but | |
4942 | * does not generate any exception | |
50728199 RK |
4943 | */ |
4944 | } | |
4945 | ||
79aceca5 | 4946 | /* dcbtst */ |
99e300ef | 4947 | static void gen_dcbtst(DisasContext *ctx) |
79aceca5 | 4948 | { |
efe843d8 DG |
4949 | /* |
4950 | * interpreted as no-op | |
4951 | * XXX: specification say this is treated as a load by the MMU but | |
4952 | * does not generate any exception | |
76a66253 | 4953 | */ |
79aceca5 FB |
4954 | } |
4955 | ||
50728199 RK |
4956 | /* dcbtstep */ |
4957 | static void gen_dcbtstep(DisasContext *ctx) | |
4958 | { | |
efe843d8 DG |
4959 | /* |
4960 | * interpreted as no-op | |
4961 | * XXX: specification say this is treated as a load by the MMU but | |
4962 | * does not generate any exception | |
50728199 RK |
4963 | */ |
4964 | } | |
4965 | ||
4d09d529 AG |
4966 | /* dcbtls */ |
4967 | static void gen_dcbtls(DisasContext *ctx) | |
4968 | { | |
4969 | /* Always fails locking the cache */ | |
4970 | TCGv t0 = tcg_temp_new(); | |
4971 | gen_load_spr(t0, SPR_Exxx_L1CSR0); | |
4972 | tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); | |
4973 | gen_store_spr(SPR_Exxx_L1CSR0, t0); | |
4d09d529 AG |
4974 | } |
4975 | ||
e64645ba BB |
4976 | /* dcblc */ |
4977 | static void gen_dcblc(DisasContext *ctx) | |
4978 | { | |
4979 | /* | |
4980 | * interpreted as no-op | |
4981 | */ | |
4982 | } | |
4983 | ||
79aceca5 | 4984 | /* dcbz */ |
99e300ef | 4985 | static void gen_dcbz(DisasContext *ctx) |
79aceca5 | 4986 | { |
8e33944f | 4987 | TCGv tcgv_addr; |
c9f82d01 | 4988 | TCGv_i32 tcgv_op; |
d63001d1 | 4989 | |
76db3ba4 | 4990 | gen_set_access_type(ctx, ACCESS_CACHE); |
8e33944f | 4991 | tcgv_addr = tcg_temp_new(); |
7058ff52 | 4992 | tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); |
8e33944f | 4993 | gen_addr_reg_index(ctx, tcgv_addr); |
c9f82d01 | 4994 | gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); |
79aceca5 FB |
4995 | } |
4996 | ||
50728199 RK |
4997 | /* dcbzep */ |
4998 | static void gen_dcbzep(DisasContext *ctx) | |
4999 | { | |
5000 | TCGv tcgv_addr; | |
5001 | TCGv_i32 tcgv_op; | |
5002 | ||
5003 | gen_set_access_type(ctx, ACCESS_CACHE); | |
5004 | tcgv_addr = tcg_temp_new(); | |
7058ff52 | 5005 | tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); |
50728199 RK |
5006 | gen_addr_reg_index(ctx, tcgv_addr); |
5007 | gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); | |
50728199 RK |
5008 | } |
5009 | ||
ae1c1a3d | 5010 | /* dst / dstt */ |
99e300ef | 5011 | static void gen_dst(DisasContext *ctx) |
ae1c1a3d AJ |
5012 | { |
5013 | if (rA(ctx->opcode) == 0) { | |
e41029b3 | 5014 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
ae1c1a3d AJ |
5015 | } else { |
5016 | /* interpreted as no-op */ | |
5017 | } | |
5018 | } | |
5019 | ||
5020 | /* dstst /dststt */ | |
99e300ef | 5021 | static void gen_dstst(DisasContext *ctx) |
ae1c1a3d AJ |
5022 | { |
5023 | if (rA(ctx->opcode) == 0) { | |
e41029b3 | 5024 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
ae1c1a3d AJ |
5025 | } else { |
5026 | /* interpreted as no-op */ | |
5027 | } | |
5028 | ||
5029 | } | |
5030 | ||
5031 | /* dss / dssall */ | |
99e300ef | 5032 | static void gen_dss(DisasContext *ctx) |
ae1c1a3d AJ |
5033 | { |
5034 | /* interpreted as no-op */ | |
5035 | } | |
5036 | ||
79aceca5 | 5037 | /* icbi */ |
99e300ef | 5038 | static void gen_icbi(DisasContext *ctx) |
79aceca5 | 5039 | { |
76db3ba4 AJ |
5040 | TCGv t0; |
5041 | gen_set_access_type(ctx, ACCESS_CACHE); | |
76db3ba4 AJ |
5042 | t0 = tcg_temp_new(); |
5043 | gen_addr_reg_index(ctx, t0); | |
2f5a189c | 5044 | gen_helper_icbi(cpu_env, t0); |
79aceca5 FB |
5045 | } |
5046 | ||
50728199 RK |
5047 | /* icbiep */ |
5048 | static void gen_icbiep(DisasContext *ctx) | |
5049 | { | |
5050 | TCGv t0; | |
5051 | gen_set_access_type(ctx, ACCESS_CACHE); | |
5052 | t0 = tcg_temp_new(); | |
5053 | gen_addr_reg_index(ctx, t0); | |
5054 | gen_helper_icbiep(cpu_env, t0); | |
50728199 RK |
5055 | } |
5056 | ||
79aceca5 FB |
5057 | /* Optional: */ |
5058 | /* dcba */ | |
99e300ef | 5059 | static void gen_dcba(DisasContext *ctx) |
79aceca5 | 5060 | { |
efe843d8 DG |
5061 | /* |
5062 | * interpreted as no-op | |
5063 | * XXX: specification say this is treated as a store by the MMU | |
0db1b20e JM |
5064 | * but does not generate any exception |
5065 | */ | |
79aceca5 FB |
5066 | } |
5067 | ||
5068 | /*** Segment register manipulation ***/ | |
5069 | /* Supervisor only: */ | |
99e300ef | 5070 | |
54623277 | 5071 | /* mfsr */ |
99e300ef | 5072 | static void gen_mfsr(DisasContext *ctx) |
79aceca5 | 5073 | { |
9a64fbe4 | 5074 | #if defined(CONFIG_USER_ONLY) |
9f0cf041 | 5075 | GEN_PRIV(ctx); |
9a64fbe4 | 5076 | #else |
74d37793 | 5077 | TCGv t0; |
9b2fadda | 5078 | |
9f0cf041 | 5079 | CHK_SV(ctx); |
7058ff52 | 5080 | t0 = tcg_constant_tl(SR(ctx->opcode)); |
c6c7cf05 | 5081 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
9b2fadda | 5082 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
5083 | } |
5084 | ||
5085 | /* mfsrin */ | |
99e300ef | 5086 | static void gen_mfsrin(DisasContext *ctx) |
79aceca5 | 5087 | { |
9a64fbe4 | 5088 | #if defined(CONFIG_USER_ONLY) |
9f0cf041 | 5089 | GEN_PRIV(ctx); |
9a64fbe4 | 5090 | #else |
74d37793 | 5091 | TCGv t0; |
9b2fadda | 5092 | |
9f0cf041 | 5093 | CHK_SV(ctx); |
74d37793 | 5094 | t0 = tcg_temp_new(); |
e2622073 | 5095 | tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); |
c6c7cf05 | 5096 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
9b2fadda | 5097 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
5098 | } |
5099 | ||
5100 | /* mtsr */ | |
99e300ef | 5101 | static void gen_mtsr(DisasContext *ctx) |
79aceca5 | 5102 | { |
9a64fbe4 | 5103 | #if defined(CONFIG_USER_ONLY) |
9f0cf041 | 5104 | GEN_PRIV(ctx); |
9a64fbe4 | 5105 | #else |
74d37793 | 5106 | TCGv t0; |
9b2fadda | 5107 | |
9f0cf041 | 5108 | CHK_SV(ctx); |
7058ff52 | 5109 | t0 = tcg_constant_tl(SR(ctx->opcode)); |
c6c7cf05 | 5110 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
9b2fadda | 5111 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
5112 | } |
5113 | ||
5114 | /* mtsrin */ | |
99e300ef | 5115 | static void gen_mtsrin(DisasContext *ctx) |
79aceca5 | 5116 | { |
9a64fbe4 | 5117 | #if defined(CONFIG_USER_ONLY) |
9f0cf041 | 5118 | GEN_PRIV(ctx); |
9a64fbe4 | 5119 | #else |
74d37793 | 5120 | TCGv t0; |
9f0cf041 | 5121 | CHK_SV(ctx); |
9b2fadda | 5122 | |
74d37793 | 5123 | t0 = tcg_temp_new(); |
e2622073 | 5124 | tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); |
c6c7cf05 | 5125 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); |
9b2fadda | 5126 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
5127 | } |
5128 | ||
12de9a39 JM |
5129 | #if defined(TARGET_PPC64) |
5130 | /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ | |
e8eaa2c0 | 5131 | |
54623277 | 5132 | /* mfsr */ |
e8eaa2c0 | 5133 | static void gen_mfsr_64b(DisasContext *ctx) |
12de9a39 JM |
5134 | { |
5135 | #if defined(CONFIG_USER_ONLY) | |
9f0cf041 | 5136 | GEN_PRIV(ctx); |
12de9a39 | 5137 | #else |
74d37793 | 5138 | TCGv t0; |
9b2fadda | 5139 | |
9f0cf041 | 5140 | CHK_SV(ctx); |
7058ff52 | 5141 | t0 = tcg_constant_tl(SR(ctx->opcode)); |
c6c7cf05 | 5142 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
9b2fadda | 5143 | #endif /* defined(CONFIG_USER_ONLY) */ |
12de9a39 JM |
5144 | } |
5145 | ||
5146 | /* mfsrin */ | |
e8eaa2c0 | 5147 | static void gen_mfsrin_64b(DisasContext *ctx) |
12de9a39 JM |
5148 | { |
5149 | #if defined(CONFIG_USER_ONLY) | |
9f0cf041 | 5150 | GEN_PRIV(ctx); |
12de9a39 | 5151 | #else |
74d37793 | 5152 | TCGv t0; |
9b2fadda | 5153 | |
9f0cf041 | 5154 | CHK_SV(ctx); |
74d37793 | 5155 | t0 = tcg_temp_new(); |
e2622073 | 5156 | tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); |
c6c7cf05 | 5157 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
9b2fadda | 5158 | #endif /* defined(CONFIG_USER_ONLY) */ |
12de9a39 JM |
5159 | } |
5160 | ||
5161 | /* mtsr */ | |
e8eaa2c0 | 5162 | static void gen_mtsr_64b(DisasContext *ctx) |
12de9a39 JM |
5163 | { |
5164 | #if defined(CONFIG_USER_ONLY) | |
9f0cf041 | 5165 | GEN_PRIV(ctx); |
12de9a39 | 5166 | #else |
74d37793 | 5167 | TCGv t0; |
9b2fadda | 5168 | |
9f0cf041 | 5169 | CHK_SV(ctx); |
7058ff52 | 5170 | t0 = tcg_constant_tl(SR(ctx->opcode)); |
c6c7cf05 | 5171 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
9b2fadda | 5172 | #endif /* defined(CONFIG_USER_ONLY) */ |
12de9a39 JM |
5173 | } |
5174 | ||
5175 | /* mtsrin */ | |
e8eaa2c0 | 5176 | static void gen_mtsrin_64b(DisasContext *ctx) |
12de9a39 JM |
5177 | { |
5178 | #if defined(CONFIG_USER_ONLY) | |
9f0cf041 | 5179 | GEN_PRIV(ctx); |
12de9a39 | 5180 | #else |
74d37793 | 5181 | TCGv t0; |
9b2fadda | 5182 | |
9f0cf041 | 5183 | CHK_SV(ctx); |
74d37793 | 5184 | t0 = tcg_temp_new(); |
e2622073 | 5185 | tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); |
c6c7cf05 | 5186 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
9b2fadda | 5187 | #endif /* defined(CONFIG_USER_ONLY) */ |
12de9a39 | 5188 | } |
f6b868fc | 5189 | |
12de9a39 JM |
5190 | #endif /* defined(TARGET_PPC64) */ |
5191 | ||
79aceca5 | 5192 | /*** Lookaside buffer management ***/ |
c47493f2 | 5193 | /* Optional & supervisor only: */ |
99e300ef | 5194 | |
54623277 | 5195 | /* tlbia */ |
99e300ef | 5196 | static void gen_tlbia(DisasContext *ctx) |
79aceca5 | 5197 | { |
9a64fbe4 | 5198 | #if defined(CONFIG_USER_ONLY) |
9f0cf041 | 5199 | GEN_PRIV(ctx); |
9a64fbe4 | 5200 | #else |
9f0cf041 | 5201 | CHK_HV(ctx); |
9b2fadda | 5202 | |
c6c7cf05 | 5203 | gen_helper_tlbia(cpu_env); |
9b2fadda | 5204 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
5205 | } |
5206 | ||
79aceca5 | 5207 | /* tlbsync */ |
99e300ef | 5208 | static void gen_tlbsync(DisasContext *ctx) |
79aceca5 | 5209 | { |
9a64fbe4 | 5210 | #if defined(CONFIG_USER_ONLY) |
9f0cf041 | 5211 | GEN_PRIV(ctx); |
9a64fbe4 | 5212 | #else |
91c60f12 CLG |
5213 | |
5214 | if (ctx->gtse) { | |
9f0cf041 | 5215 | CHK_SV(ctx); /* If gtse is set then tlbsync is supervisor privileged */ |
91c60f12 | 5216 | } else { |
9f0cf041 | 5217 | CHK_HV(ctx); /* Else hypervisor privileged */ |
91c60f12 | 5218 | } |
9b2fadda | 5219 | |
e3cffe6f ND |
5220 | /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ |
5221 | if (ctx->insns_flags & PPC_BOOKE) { | |
5222 | gen_check_tlb_flush(ctx, true); | |
5223 | } | |
9b2fadda | 5224 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
5225 | } |
5226 | ||
5227 | /*** External control ***/ | |
5228 | /* Optional: */ | |
99e300ef | 5229 | |
54623277 | 5230 | /* eciwx */ |
99e300ef | 5231 | static void gen_eciwx(DisasContext *ctx) |
79aceca5 | 5232 | { |
76db3ba4 | 5233 | TCGv t0; |
fa407c03 | 5234 | /* Should check EAR[E] ! */ |
76db3ba4 AJ |
5235 | gen_set_access_type(ctx, ACCESS_EXT); |
5236 | t0 = tcg_temp_new(); | |
5237 | gen_addr_reg_index(ctx, t0); | |
c674a983 RH |
5238 | tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, |
5239 | DEF_MEMOP(MO_UL | MO_ALIGN)); | |
76a66253 JM |
5240 | } |
5241 | ||
5242 | /* ecowx */ | |
99e300ef | 5243 | static void gen_ecowx(DisasContext *ctx) |
76a66253 | 5244 | { |
76db3ba4 | 5245 | TCGv t0; |
fa407c03 | 5246 | /* Should check EAR[E] ! */ |
76db3ba4 AJ |
5247 | gen_set_access_type(ctx, ACCESS_EXT); |
5248 | t0 = tcg_temp_new(); | |
5249 | gen_addr_reg_index(ctx, t0); | |
c674a983 RH |
5250 | tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, |
5251 | DEF_MEMOP(MO_UL | MO_ALIGN)); | |
76a66253 JM |
5252 | } |
5253 | ||
76a66253 | 5254 | /* 602 - 603 - G2 TLB management */ |
e8eaa2c0 | 5255 | |
54623277 | 5256 | /* tlbld */ |
e8eaa2c0 | 5257 | static void gen_tlbld_6xx(DisasContext *ctx) |
76a66253 JM |
5258 | { |
5259 | #if defined(CONFIG_USER_ONLY) | |
9f0cf041 | 5260 | GEN_PRIV(ctx); |
76a66253 | 5261 | #else |
9f0cf041 | 5262 | CHK_SV(ctx); |
c6c7cf05 | 5263 | gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 5264 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5265 | } |
5266 | ||
5267 | /* tlbli */ | |
e8eaa2c0 | 5268 | static void gen_tlbli_6xx(DisasContext *ctx) |
76a66253 JM |
5269 | { |
5270 | #if defined(CONFIG_USER_ONLY) | |
9f0cf041 | 5271 | GEN_PRIV(ctx); |
76a66253 | 5272 | #else |
9f0cf041 | 5273 | CHK_SV(ctx); |
c6c7cf05 | 5274 | gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 5275 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5276 | } |
5277 | ||
76a66253 | 5278 | /* BookE specific instructions */ |
99e300ef | 5279 | |
54623277 | 5280 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5281 | static void gen_mfapidi(DisasContext *ctx) |
76a66253 JM |
5282 | { |
5283 | /* XXX: TODO */ | |
e06fcd75 | 5284 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5285 | } |
5286 | ||
2662a059 | 5287 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5288 | static void gen_tlbiva(DisasContext *ctx) |
76a66253 JM |
5289 | { |
5290 | #if defined(CONFIG_USER_ONLY) | |
9f0cf041 | 5291 | GEN_PRIV(ctx); |
76a66253 | 5292 | #else |
74d37793 | 5293 | TCGv t0; |
9b2fadda | 5294 | |
9f0cf041 | 5295 | CHK_SV(ctx); |
ec72e276 | 5296 | t0 = tcg_temp_new(); |
76db3ba4 | 5297 | gen_addr_reg_index(ctx, t0); |
4693364f | 5298 | gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 5299 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5300 | } |
5301 | ||
5302 | /* All 405 MAC instructions are translated here */ | |
636aa200 BS |
5303 | static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, |
5304 | int ra, int rb, int rt, int Rc) | |
76a66253 | 5305 | { |
182608d4 AJ |
5306 | TCGv t0, t1; |
5307 | ||
9723281f RH |
5308 | t0 = tcg_temp_new(); |
5309 | t1 = tcg_temp_new(); | |
182608d4 | 5310 | |
76a66253 JM |
5311 | switch (opc3 & 0x0D) { |
5312 | case 0x05: | |
5313 | /* macchw - macchw. - macchwo - macchwo. */ | |
5314 | /* macchws - macchws. - macchwso - macchwso. */ | |
5315 | /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ | |
5316 | /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ | |
5317 | /* mulchw - mulchw. */ | |
182608d4 AJ |
5318 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5319 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5320 | tcg_gen_ext16s_tl(t1, t1); | |
76a66253 JM |
5321 | break; |
5322 | case 0x04: | |
5323 | /* macchwu - macchwu. - macchwuo - macchwuo. */ | |
5324 | /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ | |
5325 | /* mulchwu - mulchwu. */ | |
182608d4 AJ |
5326 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5327 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5328 | tcg_gen_ext16u_tl(t1, t1); | |
76a66253 JM |
5329 | break; |
5330 | case 0x01: | |
5331 | /* machhw - machhw. - machhwo - machhwo. */ | |
5332 | /* machhws - machhws. - machhwso - machhwso. */ | |
5333 | /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ | |
5334 | /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ | |
5335 | /* mulhhw - mulhhw. */ | |
182608d4 AJ |
5336 | tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); |
5337 | tcg_gen_ext16s_tl(t0, t0); | |
5338 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5339 | tcg_gen_ext16s_tl(t1, t1); | |
76a66253 JM |
5340 | break; |
5341 | case 0x00: | |
5342 | /* machhwu - machhwu. - machhwuo - machhwuo. */ | |
5343 | /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ | |
5344 | /* mulhhwu - mulhhwu. */ | |
182608d4 AJ |
5345 | tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); |
5346 | tcg_gen_ext16u_tl(t0, t0); | |
5347 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5348 | tcg_gen_ext16u_tl(t1, t1); | |
76a66253 JM |
5349 | break; |
5350 | case 0x0D: | |
5351 | /* maclhw - maclhw. - maclhwo - maclhwo. */ | |
5352 | /* maclhws - maclhws. - maclhwso - maclhwso. */ | |
5353 | /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ | |
5354 | /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ | |
5355 | /* mullhw - mullhw. */ | |
182608d4 AJ |
5356 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5357 | tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); | |
76a66253 JM |
5358 | break; |
5359 | case 0x0C: | |
5360 | /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ | |
5361 | /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ | |
5362 | /* mullhwu - mullhwu. */ | |
182608d4 AJ |
5363 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5364 | tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); | |
76a66253 JM |
5365 | break; |
5366 | } | |
76a66253 | 5367 | if (opc2 & 0x04) { |
182608d4 AJ |
5368 | /* (n)multiply-and-accumulate (0x0C / 0x0E) */ |
5369 | tcg_gen_mul_tl(t1, t0, t1); | |
5370 | if (opc2 & 0x02) { | |
5371 | /* nmultiply-and-accumulate (0x0E) */ | |
5372 | tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); | |
5373 | } else { | |
5374 | /* multiply-and-accumulate (0x0C) */ | |
5375 | tcg_gen_add_tl(t0, cpu_gpr[rt], t1); | |
5376 | } | |
5377 | ||
5378 | if (opc3 & 0x12) { | |
5379 | /* Check overflow and/or saturate */ | |
42a268c2 | 5380 | TCGLabel *l1 = gen_new_label(); |
182608d4 AJ |
5381 | |
5382 | if (opc3 & 0x10) { | |
5383 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 5384 | tcg_gen_movi_tl(cpu_ov, 0); |
182608d4 AJ |
5385 | } |
5386 | if (opc3 & 0x01) { | |
5387 | /* Signed */ | |
5388 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); | |
5389 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); | |
5390 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); | |
5391 | tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); | |
bdc4e053 | 5392 | if (opc3 & 0x02) { |
182608d4 AJ |
5393 | /* Saturate */ |
5394 | tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); | |
5395 | tcg_gen_xori_tl(t0, t0, 0x7fffffff); | |
5396 | } | |
5397 | } else { | |
5398 | /* Unsigned */ | |
5399 | tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); | |
bdc4e053 | 5400 | if (opc3 & 0x02) { |
182608d4 AJ |
5401 | /* Saturate */ |
5402 | tcg_gen_movi_tl(t0, UINT32_MAX); | |
5403 | } | |
5404 | } | |
5405 | if (opc3 & 0x10) { | |
5406 | /* Check overflow */ | |
da91a00f RH |
5407 | tcg_gen_movi_tl(cpu_ov, 1); |
5408 | tcg_gen_movi_tl(cpu_so, 1); | |
182608d4 AJ |
5409 | } |
5410 | gen_set_label(l1); | |
5411 | tcg_gen_mov_tl(cpu_gpr[rt], t0); | |
5412 | } | |
5413 | } else { | |
5414 | tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); | |
76a66253 | 5415 | } |
76a66253 JM |
5416 | if (unlikely(Rc) != 0) { |
5417 | /* Update Rc0 */ | |
182608d4 | 5418 | gen_set_Rc0(ctx, cpu_gpr[rt]); |
76a66253 JM |
5419 | } |
5420 | } | |
5421 | ||
a750fc0b | 5422 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ |
99e300ef | 5423 | static void glue(gen_, name)(DisasContext *ctx) \ |
76a66253 JM |
5424 | { \ |
5425 | gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ | |
5426 | rD(ctx->opcode), Rc(ctx->opcode)); \ | |
5427 | } | |
5428 | ||
5429 | /* macchw - macchw. */ | |
a750fc0b | 5430 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05); |
76a66253 | 5431 | /* macchwo - macchwo. */ |
a750fc0b | 5432 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); |
76a66253 | 5433 | /* macchws - macchws. */ |
a750fc0b | 5434 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07); |
76a66253 | 5435 | /* macchwso - macchwso. */ |
a750fc0b | 5436 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); |
76a66253 | 5437 | /* macchwsu - macchwsu. */ |
a750fc0b | 5438 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); |
76a66253 | 5439 | /* macchwsuo - macchwsuo. */ |
a750fc0b | 5440 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); |
76a66253 | 5441 | /* macchwu - macchwu. */ |
a750fc0b | 5442 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); |
76a66253 | 5443 | /* macchwuo - macchwuo. */ |
a750fc0b | 5444 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); |
76a66253 | 5445 | /* machhw - machhw. */ |
a750fc0b | 5446 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01); |
76a66253 | 5447 | /* machhwo - machhwo. */ |
a750fc0b | 5448 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); |
76a66253 | 5449 | /* machhws - machhws. */ |
a750fc0b | 5450 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03); |
76a66253 | 5451 | /* machhwso - machhwso. */ |
a750fc0b | 5452 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); |
76a66253 | 5453 | /* machhwsu - machhwsu. */ |
a750fc0b | 5454 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); |
76a66253 | 5455 | /* machhwsuo - machhwsuo. */ |
a750fc0b | 5456 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); |
76a66253 | 5457 | /* machhwu - machhwu. */ |
a750fc0b | 5458 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); |
76a66253 | 5459 | /* machhwuo - machhwuo. */ |
a750fc0b | 5460 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); |
76a66253 | 5461 | /* maclhw - maclhw. */ |
a750fc0b | 5462 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); |
76a66253 | 5463 | /* maclhwo - maclhwo. */ |
a750fc0b | 5464 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); |
76a66253 | 5465 | /* maclhws - maclhws. */ |
a750fc0b | 5466 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); |
76a66253 | 5467 | /* maclhwso - maclhwso. */ |
a750fc0b | 5468 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); |
76a66253 | 5469 | /* maclhwu - maclhwu. */ |
a750fc0b | 5470 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); |
76a66253 | 5471 | /* maclhwuo - maclhwuo. */ |
a750fc0b | 5472 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); |
76a66253 | 5473 | /* maclhwsu - maclhwsu. */ |
a750fc0b | 5474 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); |
76a66253 | 5475 | /* maclhwsuo - maclhwsuo. */ |
a750fc0b | 5476 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); |
76a66253 | 5477 | /* nmacchw - nmacchw. */ |
a750fc0b | 5478 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); |
76a66253 | 5479 | /* nmacchwo - nmacchwo. */ |
a750fc0b | 5480 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); |
76a66253 | 5481 | /* nmacchws - nmacchws. */ |
a750fc0b | 5482 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); |
76a66253 | 5483 | /* nmacchwso - nmacchwso. */ |
a750fc0b | 5484 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); |
76a66253 | 5485 | /* nmachhw - nmachhw. */ |
a750fc0b | 5486 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); |
76a66253 | 5487 | /* nmachhwo - nmachhwo. */ |
a750fc0b | 5488 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); |
76a66253 | 5489 | /* nmachhws - nmachhws. */ |
a750fc0b | 5490 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); |
76a66253 | 5491 | /* nmachhwso - nmachhwso. */ |
a750fc0b | 5492 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); |
76a66253 | 5493 | /* nmaclhw - nmaclhw. */ |
a750fc0b | 5494 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); |
76a66253 | 5495 | /* nmaclhwo - nmaclhwo. */ |
a750fc0b | 5496 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); |
76a66253 | 5497 | /* nmaclhws - nmaclhws. */ |
a750fc0b | 5498 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); |
76a66253 | 5499 | /* nmaclhwso - nmaclhwso. */ |
a750fc0b | 5500 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); |
76a66253 JM |
5501 | |
5502 | /* mulchw - mulchw. */ | |
a750fc0b | 5503 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05); |
76a66253 | 5504 | /* mulchwu - mulchwu. */ |
a750fc0b | 5505 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); |
76a66253 | 5506 | /* mulhhw - mulhhw. */ |
a750fc0b | 5507 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); |
76a66253 | 5508 | /* mulhhwu - mulhhwu. */ |
a750fc0b | 5509 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); |
76a66253 | 5510 | /* mullhw - mullhw. */ |
a750fc0b | 5511 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); |
76a66253 | 5512 | /* mullhwu - mullhwu. */ |
a750fc0b | 5513 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); |
76a66253 JM |
5514 | |
5515 | /* mfdcr */ | |
99e300ef | 5516 | static void gen_mfdcr(DisasContext *ctx) |
76a66253 JM |
5517 | { |
5518 | #if defined(CONFIG_USER_ONLY) | |
9f0cf041 | 5519 | GEN_PRIV(ctx); |
76a66253 | 5520 | #else |
06dca6a7 | 5521 | TCGv dcrn; |
9b2fadda | 5522 | |
9f0cf041 | 5523 | CHK_SV(ctx); |
7058ff52 | 5524 | dcrn = tcg_constant_tl(SPR(ctx->opcode)); |
d0f1562d | 5525 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); |
9b2fadda | 5526 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5527 | } |
5528 | ||
5529 | /* mtdcr */ | |
99e300ef | 5530 | static void gen_mtdcr(DisasContext *ctx) |
76a66253 JM |
5531 | { |
5532 | #if defined(CONFIG_USER_ONLY) | |
9f0cf041 | 5533 | GEN_PRIV(ctx); |
76a66253 | 5534 | #else |
06dca6a7 | 5535 | TCGv dcrn; |
9b2fadda | 5536 | |
9f0cf041 | 5537 | CHK_SV(ctx); |
7058ff52 | 5538 | dcrn = tcg_constant_tl(SPR(ctx->opcode)); |
d0f1562d | 5539 | gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); |
9b2fadda | 5540 | #endif /* defined(CONFIG_USER_ONLY) */ |
a42bd6cc JM |
5541 | } |
5542 | ||
5543 | /* mfdcrx */ | |
2662a059 | 5544 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5545 | static void gen_mfdcrx(DisasContext *ctx) |
a42bd6cc JM |
5546 | { |
5547 | #if defined(CONFIG_USER_ONLY) | |
9f0cf041 | 5548 | GEN_PRIV(ctx); |
a42bd6cc | 5549 | #else |
9f0cf041 | 5550 | CHK_SV(ctx); |
d0f1562d BS |
5551 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5552 | cpu_gpr[rA(ctx->opcode)]); | |
a750fc0b | 5553 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
9b2fadda | 5554 | #endif /* defined(CONFIG_USER_ONLY) */ |
a42bd6cc JM |
5555 | } |
5556 | ||
5557 | /* mtdcrx */ | |
2662a059 | 5558 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5559 | static void gen_mtdcrx(DisasContext *ctx) |
a42bd6cc JM |
5560 | { |
5561 | #if defined(CONFIG_USER_ONLY) | |
9f0cf041 | 5562 | GEN_PRIV(ctx); |
a42bd6cc | 5563 | #else |
9f0cf041 | 5564 | CHK_SV(ctx); |
d0f1562d BS |
5565 | gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], |
5566 | cpu_gpr[rS(ctx->opcode)]); | |
a750fc0b | 5567 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
9b2fadda | 5568 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5569 | } |
5570 | ||
5571 | /* dccci */ | |
99e300ef | 5572 | static void gen_dccci(DisasContext *ctx) |
76a66253 | 5573 | { |
9f0cf041 | 5574 | CHK_SV(ctx); |
76a66253 | 5575 | /* interpreted as no-op */ |
76a66253 JM |
5576 | } |
5577 | ||
5578 | /* dcread */ | |
99e300ef | 5579 | static void gen_dcread(DisasContext *ctx) |
76a66253 JM |
5580 | { |
5581 | #if defined(CONFIG_USER_ONLY) | |
9f0cf041 | 5582 | GEN_PRIV(ctx); |
76a66253 | 5583 | #else |
b61f2753 | 5584 | TCGv EA, val; |
9b2fadda | 5585 | |
9f0cf041 | 5586 | CHK_SV(ctx); |
76db3ba4 | 5587 | gen_set_access_type(ctx, ACCESS_CACHE); |
a7812ae4 | 5588 | EA = tcg_temp_new(); |
76db3ba4 | 5589 | gen_addr_reg_index(ctx, EA); |
a7812ae4 | 5590 | val = tcg_temp_new(); |
76db3ba4 | 5591 | gen_qemu_ld32u(ctx, val, EA); |
b61f2753 | 5592 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); |
9b2fadda | 5593 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5594 | } |
5595 | ||
5596 | /* icbt */ | |
e8eaa2c0 | 5597 | static void gen_icbt_40x(DisasContext *ctx) |
76a66253 | 5598 | { |
efe843d8 DG |
5599 | /* |
5600 | * interpreted as no-op | |
5601 | * XXX: specification say this is treated as a load by the MMU but | |
5602 | * does not generate any exception | |
76a66253 JM |
5603 | */ |
5604 | } | |
5605 | ||
5606 | /* iccci */ | |
99e300ef | 5607 | static void gen_iccci(DisasContext *ctx) |
76a66253 | 5608 | { |
9f0cf041 | 5609 | CHK_SV(ctx); |
76a66253 | 5610 | /* interpreted as no-op */ |
76a66253 JM |
5611 | } |
5612 | ||
5613 | /* icread */ | |
99e300ef | 5614 | static void gen_icread(DisasContext *ctx) |
76a66253 | 5615 | { |
9f0cf041 | 5616 | CHK_SV(ctx); |
76a66253 | 5617 | /* interpreted as no-op */ |
76a66253 JM |
5618 | } |
5619 | ||
c47493f2 | 5620 | /* rfci (supervisor only) */ |
e8eaa2c0 | 5621 | static void gen_rfci_40x(DisasContext *ctx) |
a42bd6cc JM |
5622 | { |
5623 | #if defined(CONFIG_USER_ONLY) | |
9f0cf041 | 5624 | GEN_PRIV(ctx); |
a42bd6cc | 5625 | #else |
9f0cf041 | 5626 | CHK_SV(ctx); |
a42bd6cc | 5627 | /* Restore CPU state */ |
e5f17ac6 | 5628 | gen_helper_40x_rfci(cpu_env); |
59bf23fa | 5629 | ctx->base.is_jmp = DISAS_EXIT; |
9b2fadda | 5630 | #endif /* defined(CONFIG_USER_ONLY) */ |
a42bd6cc JM |
5631 | } |
5632 | ||
99e300ef | 5633 | static void gen_rfci(DisasContext *ctx) |
a42bd6cc JM |
5634 | { |
5635 | #if defined(CONFIG_USER_ONLY) | |
9f0cf041 | 5636 | GEN_PRIV(ctx); |
a42bd6cc | 5637 | #else |
9f0cf041 | 5638 | CHK_SV(ctx); |
a42bd6cc | 5639 | /* Restore CPU state */ |
e5f17ac6 | 5640 | gen_helper_rfci(cpu_env); |
59bf23fa | 5641 | ctx->base.is_jmp = DISAS_EXIT; |
9b2fadda | 5642 | #endif /* defined(CONFIG_USER_ONLY) */ |
a42bd6cc JM |
5643 | } |
5644 | ||
5645 | /* BookE specific */ | |
99e300ef | 5646 | |
54623277 | 5647 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5648 | static void gen_rfdi(DisasContext *ctx) |
76a66253 JM |
5649 | { |
5650 | #if defined(CONFIG_USER_ONLY) | |
9f0cf041 | 5651 | GEN_PRIV(ctx); |
76a66253 | 5652 | #else |
9f0cf041 | 5653 | CHK_SV(ctx); |
76a66253 | 5654 | /* Restore CPU state */ |
e5f17ac6 | 5655 | gen_helper_rfdi(cpu_env); |
59bf23fa | 5656 | ctx->base.is_jmp = DISAS_EXIT; |
9b2fadda | 5657 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5658 | } |
5659 | ||
2662a059 | 5660 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5661 | static void gen_rfmci(DisasContext *ctx) |
a42bd6cc JM |
5662 | { |
5663 | #if defined(CONFIG_USER_ONLY) | |
9f0cf041 | 5664 | GEN_PRIV(ctx); |
a42bd6cc | 5665 | #else |
9f0cf041 | 5666 | CHK_SV(ctx); |
a42bd6cc | 5667 | /* Restore CPU state */ |
e5f17ac6 | 5668 | gen_helper_rfmci(cpu_env); |
59bf23fa | 5669 | ctx->base.is_jmp = DISAS_EXIT; |
9b2fadda | 5670 | #endif /* defined(CONFIG_USER_ONLY) */ |
a42bd6cc | 5671 | } |
5eb7995e | 5672 | |
d9bce9d9 | 5673 | /* TLB management - PowerPC 405 implementation */ |
e8eaa2c0 | 5674 | |
54623277 | 5675 | /* tlbre */ |
e8eaa2c0 | 5676 | static void gen_tlbre_40x(DisasContext *ctx) |
76a66253 JM |
5677 | { |
5678 | #if defined(CONFIG_USER_ONLY) | |
9f0cf041 | 5679 | GEN_PRIV(ctx); |
76a66253 | 5680 | #else |
9f0cf041 | 5681 | CHK_SV(ctx); |
76a66253 JM |
5682 | switch (rB(ctx->opcode)) { |
5683 | case 0: | |
c6c7cf05 BS |
5684 | gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5685 | cpu_gpr[rA(ctx->opcode)]); | |
76a66253 JM |
5686 | break; |
5687 | case 1: | |
c6c7cf05 BS |
5688 | gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5689 | cpu_gpr[rA(ctx->opcode)]); | |
76a66253 JM |
5690 | break; |
5691 | default: | |
e06fcd75 | 5692 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 | 5693 | break; |
9a64fbe4 | 5694 | } |
9b2fadda | 5695 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5696 | } |
5697 | ||
d9bce9d9 | 5698 | /* tlbsx - tlbsx. */ |
e8eaa2c0 | 5699 | static void gen_tlbsx_40x(DisasContext *ctx) |
76a66253 JM |
5700 | { |
5701 | #if defined(CONFIG_USER_ONLY) | |
9f0cf041 | 5702 | GEN_PRIV(ctx); |
76a66253 | 5703 | #else |
74d37793 | 5704 | TCGv t0; |
9b2fadda | 5705 | |
9f0cf041 | 5706 | CHK_SV(ctx); |
74d37793 | 5707 | t0 = tcg_temp_new(); |
76db3ba4 | 5708 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 5709 | gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 5710 | if (Rc(ctx->opcode)) { |
42a268c2 | 5711 | TCGLabel *l1 = gen_new_label(); |
da91a00f | 5712 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
74d37793 AJ |
5713 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); |
5714 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); | |
5715 | gen_set_label(l1); | |
5716 | } | |
9b2fadda | 5717 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
5718 | } |
5719 | ||
76a66253 | 5720 | /* tlbwe */ |
e8eaa2c0 | 5721 | static void gen_tlbwe_40x(DisasContext *ctx) |
79aceca5 | 5722 | { |
76a66253 | 5723 | #if defined(CONFIG_USER_ONLY) |
9f0cf041 | 5724 | GEN_PRIV(ctx); |
76a66253 | 5725 | #else |
9f0cf041 | 5726 | CHK_SV(ctx); |
9b2fadda | 5727 | |
76a66253 JM |
5728 | switch (rB(ctx->opcode)) { |
5729 | case 0: | |
c6c7cf05 BS |
5730 | gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], |
5731 | cpu_gpr[rS(ctx->opcode)]); | |
76a66253 JM |
5732 | break; |
5733 | case 1: | |
c6c7cf05 BS |
5734 | gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], |
5735 | cpu_gpr[rS(ctx->opcode)]); | |
76a66253 JM |
5736 | break; |
5737 | default: | |
e06fcd75 | 5738 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 | 5739 | break; |
9a64fbe4 | 5740 | } |
9b2fadda | 5741 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5742 | } |
5743 | ||
a4bb6c3e | 5744 | /* TLB management - PowerPC 440 implementation */ |
e8eaa2c0 | 5745 | |
54623277 | 5746 | /* tlbre */ |
e8eaa2c0 | 5747 | static void gen_tlbre_440(DisasContext *ctx) |
5eb7995e JM |
5748 | { |
5749 | #if defined(CONFIG_USER_ONLY) | |
9f0cf041 | 5750 | GEN_PRIV(ctx); |
5eb7995e | 5751 | #else |
9f0cf041 | 5752 | CHK_SV(ctx); |
9b2fadda | 5753 | |
5eb7995e JM |
5754 | switch (rB(ctx->opcode)) { |
5755 | case 0: | |
5eb7995e | 5756 | case 1: |
5eb7995e | 5757 | case 2: |
74d37793 | 5758 | { |
7058ff52 | 5759 | TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); |
c6c7cf05 BS |
5760 | gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5761 | t0, cpu_gpr[rA(ctx->opcode)]); | |
74d37793 | 5762 | } |
5eb7995e JM |
5763 | break; |
5764 | default: | |
e06fcd75 | 5765 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5eb7995e JM |
5766 | break; |
5767 | } | |
9b2fadda | 5768 | #endif /* defined(CONFIG_USER_ONLY) */ |
5eb7995e JM |
5769 | } |
5770 | ||
5771 | /* tlbsx - tlbsx. */ | |
e8eaa2c0 | 5772 | static void gen_tlbsx_440(DisasContext *ctx) |
5eb7995e JM |
5773 | { |
5774 | #if defined(CONFIG_USER_ONLY) | |
9f0cf041 | 5775 | GEN_PRIV(ctx); |
5eb7995e | 5776 | #else |
74d37793 | 5777 | TCGv t0; |
9b2fadda | 5778 | |
9f0cf041 | 5779 | CHK_SV(ctx); |
74d37793 | 5780 | t0 = tcg_temp_new(); |
76db3ba4 | 5781 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 5782 | gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 5783 | if (Rc(ctx->opcode)) { |
42a268c2 | 5784 | TCGLabel *l1 = gen_new_label(); |
da91a00f | 5785 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
74d37793 AJ |
5786 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); |
5787 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); | |
5788 | gen_set_label(l1); | |
5789 | } | |
9b2fadda | 5790 | #endif /* defined(CONFIG_USER_ONLY) */ |
5eb7995e JM |
5791 | } |
5792 | ||
5793 | /* tlbwe */ | |
e8eaa2c0 | 5794 | static void gen_tlbwe_440(DisasContext *ctx) |
5eb7995e JM |
5795 | { |
5796 | #if defined(CONFIG_USER_ONLY) | |
9f0cf041 | 5797 | GEN_PRIV(ctx); |
5eb7995e | 5798 | #else |
9f0cf041 | 5799 | CHK_SV(ctx); |
5eb7995e JM |
5800 | switch (rB(ctx->opcode)) { |
5801 | case 0: | |
5eb7995e | 5802 | case 1: |
5eb7995e | 5803 | case 2: |
74d37793 | 5804 | { |
7058ff52 | 5805 | TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); |
c6c7cf05 BS |
5806 | gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], |
5807 | cpu_gpr[rS(ctx->opcode)]); | |
74d37793 | 5808 | } |
5eb7995e JM |
5809 | break; |
5810 | default: | |
e06fcd75 | 5811 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5eb7995e JM |
5812 | break; |
5813 | } | |
9b2fadda | 5814 | #endif /* defined(CONFIG_USER_ONLY) */ |
5eb7995e JM |
5815 | } |
5816 | ||
01662f3e AG |
5817 | /* TLB management - PowerPC BookE 2.06 implementation */ |
5818 | ||
5819 | /* tlbre */ | |
5820 | static void gen_tlbre_booke206(DisasContext *ctx) | |
5821 | { | |
9b2fadda | 5822 | #if defined(CONFIG_USER_ONLY) |
9f0cf041 | 5823 | GEN_PRIV(ctx); |
01662f3e | 5824 | #else |
9f0cf041 | 5825 | CHK_SV(ctx); |
c6c7cf05 | 5826 | gen_helper_booke206_tlbre(cpu_env); |
9b2fadda | 5827 | #endif /* defined(CONFIG_USER_ONLY) */ |
01662f3e AG |
5828 | } |
5829 | ||
5830 | /* tlbsx - tlbsx. */ | |
5831 | static void gen_tlbsx_booke206(DisasContext *ctx) | |
5832 | { | |
5833 | #if defined(CONFIG_USER_ONLY) | |
9f0cf041 | 5834 | GEN_PRIV(ctx); |
01662f3e AG |
5835 | #else |
5836 | TCGv t0; | |
01662f3e | 5837 | |
9f0cf041 | 5838 | CHK_SV(ctx); |
01662f3e AG |
5839 | if (rA(ctx->opcode)) { |
5840 | t0 = tcg_temp_new(); | |
9d15d8e1 | 5841 | tcg_gen_add_tl(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
01662f3e | 5842 | } else { |
9d15d8e1 | 5843 | t0 = cpu_gpr[rB(ctx->opcode)]; |
01662f3e | 5844 | } |
c6c7cf05 | 5845 | gen_helper_booke206_tlbsx(cpu_env, t0); |
9b2fadda | 5846 | #endif /* defined(CONFIG_USER_ONLY) */ |
01662f3e AG |
5847 | } |
5848 | ||
5849 | /* tlbwe */ | |
5850 | static void gen_tlbwe_booke206(DisasContext *ctx) | |
5851 | { | |
5852 | #if defined(CONFIG_USER_ONLY) | |
9f0cf041 | 5853 | GEN_PRIV(ctx); |
01662f3e | 5854 | #else |
9f0cf041 | 5855 | CHK_SV(ctx); |
c6c7cf05 | 5856 | gen_helper_booke206_tlbwe(cpu_env); |
9b2fadda | 5857 | #endif /* defined(CONFIG_USER_ONLY) */ |
01662f3e AG |
5858 | } |
5859 | ||
5860 | static void gen_tlbivax_booke206(DisasContext *ctx) | |
5861 | { | |
5862 | #if defined(CONFIG_USER_ONLY) | |
9f0cf041 | 5863 | GEN_PRIV(ctx); |
01662f3e AG |
5864 | #else |
5865 | TCGv t0; | |
01662f3e | 5866 | |
9f0cf041 | 5867 | CHK_SV(ctx); |
01662f3e AG |
5868 | t0 = tcg_temp_new(); |
5869 | gen_addr_reg_index(ctx, t0); | |
c6c7cf05 | 5870 | gen_helper_booke206_tlbivax(cpu_env, t0); |
9b2fadda | 5871 | #endif /* defined(CONFIG_USER_ONLY) */ |
01662f3e AG |
5872 | } |
5873 | ||
6d3db821 AG |
5874 | static void gen_tlbilx_booke206(DisasContext *ctx) |
5875 | { | |
5876 | #if defined(CONFIG_USER_ONLY) | |
9f0cf041 | 5877 | GEN_PRIV(ctx); |
6d3db821 AG |
5878 | #else |
5879 | TCGv t0; | |
6d3db821 | 5880 | |
9f0cf041 | 5881 | CHK_SV(ctx); |
6d3db821 AG |
5882 | t0 = tcg_temp_new(); |
5883 | gen_addr_reg_index(ctx, t0); | |
5884 | ||
efe843d8 | 5885 | switch ((ctx->opcode >> 21) & 0x3) { |
6d3db821 | 5886 | case 0: |
c6c7cf05 | 5887 | gen_helper_booke206_tlbilx0(cpu_env, t0); |
6d3db821 AG |
5888 | break; |
5889 | case 1: | |
c6c7cf05 | 5890 | gen_helper_booke206_tlbilx1(cpu_env, t0); |
6d3db821 AG |
5891 | break; |
5892 | case 3: | |
c6c7cf05 | 5893 | gen_helper_booke206_tlbilx3(cpu_env, t0); |
6d3db821 AG |
5894 | break; |
5895 | default: | |
5896 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
5897 | break; | |
5898 | } | |
9b2fadda | 5899 | #endif /* defined(CONFIG_USER_ONLY) */ |
6d3db821 AG |
5900 | } |
5901 | ||
76a66253 | 5902 | /* wrtee */ |
99e300ef | 5903 | static void gen_wrtee(DisasContext *ctx) |
76a66253 JM |
5904 | { |
5905 | #if defined(CONFIG_USER_ONLY) | |
9f0cf041 | 5906 | GEN_PRIV(ctx); |
76a66253 | 5907 | #else |
6527f6ea | 5908 | TCGv t0; |
9b2fadda | 5909 | |
9f0cf041 | 5910 | CHK_SV(ctx); |
6527f6ea AJ |
5911 | t0 = tcg_temp_new(); |
5912 | tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); | |
5913 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); | |
5914 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
2fdedcbc | 5915 | gen_ppc_maybe_interrupt(ctx); |
efe843d8 DG |
5916 | /* |
5917 | * Stop translation to have a chance to raise an exception if we | |
5918 | * just set msr_ee to 1 | |
dee96f6c | 5919 | */ |
d736de8f | 5920 | ctx->base.is_jmp = DISAS_EXIT_UPDATE; |
9b2fadda | 5921 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5922 | } |
5923 | ||
5924 | /* wrteei */ | |
99e300ef | 5925 | static void gen_wrteei(DisasContext *ctx) |
76a66253 JM |
5926 | { |
5927 | #if defined(CONFIG_USER_ONLY) | |
9f0cf041 | 5928 | GEN_PRIV(ctx); |
76a66253 | 5929 | #else |
9f0cf041 | 5930 | CHK_SV(ctx); |
fbe73008 | 5931 | if (ctx->opcode & 0x00008000) { |
6527f6ea | 5932 | tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); |
2fdedcbc | 5933 | gen_ppc_maybe_interrupt(ctx); |
6527f6ea | 5934 | /* Stop translation to have a chance to raise an exception */ |
d736de8f | 5935 | ctx->base.is_jmp = DISAS_EXIT_UPDATE; |
6527f6ea | 5936 | } else { |
1b6e5f99 | 5937 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); |
6527f6ea | 5938 | } |
9b2fadda | 5939 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5940 | } |
5941 | ||
08e46e54 | 5942 | /* PowerPC 440 specific instructions */ |
99e300ef | 5943 | |
54623277 | 5944 | /* dlmzb */ |
99e300ef | 5945 | static void gen_dlmzb(DisasContext *ctx) |
76a66253 | 5946 | { |
7058ff52 | 5947 | TCGv_i32 t0 = tcg_constant_i32(Rc(ctx->opcode)); |
d15f74fb BS |
5948 | gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, |
5949 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); | |
76a66253 JM |
5950 | } |
5951 | ||
5952 | /* mbar replaces eieio on 440 */ | |
99e300ef | 5953 | static void gen_mbar(DisasContext *ctx) |
76a66253 JM |
5954 | { |
5955 | /* interpreted as no-op */ | |
5956 | } | |
5957 | ||
5958 | /* msync replaces sync on 440 */ | |
dcb2b9e1 | 5959 | static void gen_msync_4xx(DisasContext *ctx) |
76a66253 | 5960 | { |
27a3ea7e BZ |
5961 | /* Only e500 seems to treat reserved bits as invalid */ |
5962 | if ((ctx->insns_flags2 & PPC2_BOOKE206) && | |
5963 | (ctx->opcode & 0x03FFF801)) { | |
5964 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
5965 | } | |
5966 | /* otherwise interpreted as no-op */ | |
76a66253 JM |
5967 | } |
5968 | ||
5969 | /* icbt */ | |
e8eaa2c0 | 5970 | static void gen_icbt_440(DisasContext *ctx) |
76a66253 | 5971 | { |
efe843d8 DG |
5972 | /* |
5973 | * interpreted as no-op | |
5974 | * XXX: specification say this is treated as a load by the MMU but | |
5975 | * does not generate any exception | |
76a66253 | 5976 | */ |
79aceca5 FB |
5977 | } |
5978 | ||
aeeb044c ND |
5979 | #if defined(TARGET_PPC64) |
5980 | static void gen_maddld(DisasContext *ctx) | |
5981 | { | |
5982 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
5983 | ||
5984 | tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
5985 | tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); | |
aeeb044c | 5986 | } |
5f29cc82 ND |
5987 | |
5988 | /* maddhd maddhdu */ | |
5989 | static void gen_maddhd_maddhdu(DisasContext *ctx) | |
5990 | { | |
5991 | TCGv_i64 lo = tcg_temp_new_i64(); | |
5992 | TCGv_i64 hi = tcg_temp_new_i64(); | |
5993 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
5994 | ||
5995 | if (Rc(ctx->opcode)) { | |
5996 | tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], | |
5997 | cpu_gpr[rB(ctx->opcode)]); | |
5998 | tcg_gen_movi_i64(t1, 0); | |
5999 | } else { | |
6000 | tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], | |
6001 | cpu_gpr[rB(ctx->opcode)]); | |
6002 | tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); | |
6003 | } | |
6004 | tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, | |
6005 | cpu_gpr[rC(ctx->opcode)], t1); | |
5f29cc82 | 6006 | } |
aeeb044c ND |
6007 | #endif /* defined(TARGET_PPC64) */ |
6008 | ||
0ff93d11 TM |
6009 | static void gen_tbegin(DisasContext *ctx) |
6010 | { | |
6011 | if (unlikely(!ctx->tm_enabled)) { | |
6012 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); | |
6013 | return; | |
6014 | } | |
6015 | gen_helper_tbegin(cpu_env); | |
6016 | } | |
6017 | ||
56a84615 TM |
6018 | #define GEN_TM_NOOP(name) \ |
6019 | static inline void gen_##name(DisasContext *ctx) \ | |
6020 | { \ | |
6021 | if (unlikely(!ctx->tm_enabled)) { \ | |
6022 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ | |
6023 | return; \ | |
6024 | } \ | |
efe843d8 DG |
6025 | /* \ |
6026 | * Because tbegin always fails in QEMU, these user \ | |
56a84615 TM |
6027 | * space instructions all have a simple implementation: \ |
6028 | * \ | |
6029 | * CR[0] = 0b0 || MSR[TS] || 0b0 \ | |
6030 | * = 0b0 || 0b00 || 0b0 \ | |
6031 | */ \ | |
6032 | tcg_gen_movi_i32(cpu_crf[0], 0); \ | |
6033 | } | |
6034 | ||
6035 | GEN_TM_NOOP(tend); | |
6036 | GEN_TM_NOOP(tabort); | |
6037 | GEN_TM_NOOP(tabortwc); | |
6038 | GEN_TM_NOOP(tabortwci); | |
6039 | GEN_TM_NOOP(tabortdc); | |
6040 | GEN_TM_NOOP(tabortdci); | |
6041 | GEN_TM_NOOP(tsr); | |
efe843d8 | 6042 | |
b8b4576e SJS |
6043 | static inline void gen_cp_abort(DisasContext *ctx) |
6044 | { | |
efe843d8 | 6045 | /* Do Nothing */ |
b8b4576e | 6046 | } |
56a84615 | 6047 | |
80b8c1ee ND |
6048 | #define GEN_CP_PASTE_NOOP(name) \ |
6049 | static inline void gen_##name(DisasContext *ctx) \ | |
6050 | { \ | |
efe843d8 DG |
6051 | /* \ |
6052 | * Generate invalid exception until we have an \ | |
6053 | * implementation of the copy paste facility \ | |
80b8c1ee ND |
6054 | */ \ |
6055 | gen_invalid(ctx); \ | |
6056 | } | |
6057 | ||
6058 | GEN_CP_PASTE_NOOP(copy) | |
6059 | GEN_CP_PASTE_NOOP(paste) | |
6060 | ||
aeedd582 TM |
6061 | static void gen_tcheck(DisasContext *ctx) |
6062 | { | |
6063 | if (unlikely(!ctx->tm_enabled)) { | |
6064 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); | |
6065 | return; | |
6066 | } | |
efe843d8 DG |
6067 | /* |
6068 | * Because tbegin always fails, the tcheck implementation is | |
6069 | * simple: | |
aeedd582 TM |
6070 | * |
6071 | * CR[CRF] = TDOOMED || MSR[TS] || 0b0 | |
6072 | * = 0b1 || 0b00 || 0b0 | |
6073 | */ | |
6074 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); | |
6075 | } | |
6076 | ||
f83c2378 TM |
6077 | #if defined(CONFIG_USER_ONLY) |
6078 | #define GEN_TM_PRIV_NOOP(name) \ | |
6079 | static inline void gen_##name(DisasContext *ctx) \ | |
6080 | { \ | |
9f0cf041 | 6081 | gen_priv_opc(ctx); \ |
f83c2378 TM |
6082 | } |
6083 | ||
6084 | #else | |
6085 | ||
6086 | #define GEN_TM_PRIV_NOOP(name) \ | |
6087 | static inline void gen_##name(DisasContext *ctx) \ | |
6088 | { \ | |
9f0cf041 | 6089 | CHK_SV(ctx); \ |
f83c2378 TM |
6090 | if (unlikely(!ctx->tm_enabled)) { \ |
6091 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ | |
6092 | return; \ | |
6093 | } \ | |
efe843d8 DG |
6094 | /* \ |
6095 | * Because tbegin always fails, the implementation is \ | |
f83c2378 TM |
6096 | * simple: \ |
6097 | * \ | |
6098 | * CR[0] = 0b0 || MSR[TS] || 0b0 \ | |
6099 | * = 0b0 || 0b00 | 0b0 \ | |
6100 | */ \ | |
6101 | tcg_gen_movi_i32(cpu_crf[0], 0); \ | |
6102 | } | |
6103 | ||
6104 | #endif | |
6105 | ||
6106 | GEN_TM_PRIV_NOOP(treclaim); | |
6107 | GEN_TM_PRIV_NOOP(trechkpt); | |
6108 | ||
1a404c91 MCA |
6109 | static inline void get_fpr(TCGv_i64 dst, int regno) |
6110 | { | |
e7d3b272 | 6111 | tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); |
1a404c91 MCA |
6112 | } |
6113 | ||
6114 | static inline void set_fpr(int regno, TCGv_i64 src) | |
6115 | { | |
e7d3b272 | 6116 | tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); |
4b65b6e7 VC |
6117 | /* |
6118 | * Before PowerISA v3.1 the result of doubleword 1 of the VSR | |
6119 | * corresponding to the target FPR was undefined. However, | |
6120 | * most (if not all) real hardware were setting the result to 0. | |
6121 | * Starting at ISA v3.1, the result for doubleword 1 is now defined | |
6122 | * to be 0. | |
6123 | */ | |
6124 | tcg_gen_st_i64(tcg_constant_i64(0), cpu_env, vsr64_offset(regno, false)); | |
1a404c91 MCA |
6125 | } |
6126 | ||
c4a18dbf MCA |
6127 | static inline void get_avr64(TCGv_i64 dst, int regno, bool high) |
6128 | { | |
37da91f1 | 6129 | tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); |
c4a18dbf MCA |
6130 | } |
6131 | ||
6132 | static inline void set_avr64(int regno, TCGv_i64 src, bool high) | |
6133 | { | |
37da91f1 | 6134 | tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); |
c4a18dbf MCA |
6135 | } |
6136 | ||
f2aabda8 RH |
6137 | /* |
6138 | * Helpers for decodetree used by !function for decoding arguments. | |
6139 | */ | |
d39b2cc7 LP |
6140 | static int times_2(DisasContext *ctx, int x) |
6141 | { | |
6142 | return x * 2; | |
6143 | } | |
6144 | ||
f2aabda8 RH |
6145 | static int times_4(DisasContext *ctx, int x) |
6146 | { | |
6147 | return x * 4; | |
6148 | } | |
6149 | ||
e10271e1 MF |
6150 | static int times_16(DisasContext *ctx, int x) |
6151 | { | |
6152 | return x * 16; | |
6153 | } | |
6154 | ||
670f1da3 VC |
6155 | static int64_t dw_compose_ea(DisasContext *ctx, int x) |
6156 | { | |
6157 | return deposit64(0xfffffffffffffe00, 3, 6, x); | |
6158 | } | |
6159 | ||
c9826ae9 RH |
6160 | /* |
6161 | * Helpers for trans_* functions to check for specific insns flags. | |
6162 | * Use token pasting to ensure that we use the proper flag with the | |
6163 | * proper variable. | |
6164 | */ | |
6165 | #define REQUIRE_INSNS_FLAGS(CTX, NAME) \ | |
6166 | do { \ | |
6167 | if (((CTX)->insns_flags & PPC_##NAME) == 0) { \ | |
6168 | return false; \ | |
6169 | } \ | |
6170 | } while (0) | |
6171 | ||
6172 | #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \ | |
6173 | do { \ | |
6174 | if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \ | |
6175 | return false; \ | |
6176 | } \ | |
6177 | } while (0) | |
6178 | ||
6179 | /* Then special-case the check for 64-bit so that we elide code for ppc32. */ | |
6180 | #if TARGET_LONG_BITS == 32 | |
6181 | # define REQUIRE_64BIT(CTX) return false | |
6182 | #else | |
6183 | # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) | |
6184 | #endif | |
6185 | ||
e2205a46 BL |
6186 | #define REQUIRE_VECTOR(CTX) \ |
6187 | do { \ | |
6188 | if (unlikely(!(CTX)->altivec_enabled)) { \ | |
6189 | gen_exception((CTX), POWERPC_EXCP_VPU); \ | |
6190 | return true; \ | |
6191 | } \ | |
8226cb2d BL |
6192 | } while (0) |
6193 | ||
6194 | #define REQUIRE_VSX(CTX) \ | |
6195 | do { \ | |
6196 | if (unlikely(!(CTX)->vsx_enabled)) { \ | |
6197 | gen_exception((CTX), POWERPC_EXCP_VSXU); \ | |
6198 | return true; \ | |
6199 | } \ | |
e2205a46 BL |
6200 | } while (0) |
6201 | ||
86057426 FV |
6202 | #define REQUIRE_FPU(ctx) \ |
6203 | do { \ | |
6204 | if (unlikely(!(ctx)->fpu_enabled)) { \ | |
6205 | gen_exception((ctx), POWERPC_EXCP_FPU); \ | |
6206 | return true; \ | |
6207 | } \ | |
6208 | } while (0) | |
6209 | ||
fc34e81a MF |
6210 | #if !defined(CONFIG_USER_ONLY) |
6211 | #define REQUIRE_SV(CTX) \ | |
6212 | do { \ | |
6213 | if (unlikely((CTX)->pr)) { \ | |
6214 | gen_priv_opc(CTX); \ | |
6215 | return true; \ | |
6216 | } \ | |
6217 | } while (0) | |
6218 | ||
e8db3cc7 MF |
6219 | #define REQUIRE_HV(CTX) \ |
6220 | do { \ | |
6221 | if (unlikely((CTX)->pr || !(CTX)->hv)) { \ | |
6222 | gen_priv_opc(CTX); \ | |
6223 | return true; \ | |
6224 | } \ | |
fc34e81a MF |
6225 | } while (0) |
6226 | #else | |
6227 | #define REQUIRE_SV(CTX) do { gen_priv_opc(CTX); return true; } while (0) | |
6228 | #define REQUIRE_HV(CTX) do { gen_priv_opc(CTX); return true; } while (0) | |
6229 | #endif | |
6230 | ||
f2aabda8 RH |
6231 | /* |
6232 | * Helpers for implementing sets of trans_* functions. | |
6233 | * Defer the implementation of NAME to FUNC, with optional extra arguments. | |
6234 | */ | |
6235 | #define TRANS(NAME, FUNC, ...) \ | |
6236 | static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ | |
6237 | { return FUNC(ctx, a, __VA_ARGS__); } | |
19f0862d LP |
6238 | #define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \ |
6239 | static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ | |
6240 | { \ | |
6241 | REQUIRE_INSNS_FLAGS(ctx, FLAGS); \ | |
6242 | return FUNC(ctx, a, __VA_ARGS__); \ | |
6243 | } | |
6244 | #define TRANS_FLAGS2(FLAGS2, NAME, FUNC, ...) \ | |
6245 | static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ | |
6246 | { \ | |
6247 | REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ | |
6248 | return FUNC(ctx, a, __VA_ARGS__); \ | |
6249 | } | |
f2aabda8 RH |
6250 | |
6251 | #define TRANS64(NAME, FUNC, ...) \ | |
6252 | static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ | |
6253 | { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } | |
19f0862d LP |
6254 | #define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \ |
6255 | static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ | |
6256 | { \ | |
6257 | REQUIRE_64BIT(ctx); \ | |
6258 | REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ | |
6259 | return FUNC(ctx, a, __VA_ARGS__); \ | |
6260 | } | |
f2aabda8 RH |
6261 | |
6262 | /* TODO: More TRANS* helpers for extra insn_flags checks. */ | |
6263 | ||
6264 | ||
99082815 RH |
6265 | #include "decode-insn32.c.inc" |
6266 | #include "decode-insn64.c.inc" | |
565cb109 GR |
6267 | #include "power8-pmu-regs.c.inc" |
6268 | ||
725b2d4d FEV |
6269 | /* |
6270 | * Incorporate CIA into the constant when R=1. | |
6271 | * Validate that when R=1, RA=0. | |
6272 | */ | |
6273 | static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a) | |
6274 | { | |
6275 | d->rt = a->rt; | |
6276 | d->ra = a->ra; | |
6277 | d->si = a->si; | |
6278 | if (a->r) { | |
6279 | if (unlikely(a->ra != 0)) { | |
6280 | gen_invalid(ctx); | |
6281 | return false; | |
6282 | } | |
6283 | d->si += ctx->cia; | |
6284 | } | |
6285 | return true; | |
6286 | } | |
6287 | ||
99082815 RH |
6288 | #include "translate/fixedpoint-impl.c.inc" |
6289 | ||
139c1837 | 6290 | #include "translate/fp-impl.c.inc" |
15848410 | 6291 | |
139c1837 | 6292 | #include "translate/vmx-impl.c.inc" |
15848410 | 6293 | |
139c1837 | 6294 | #include "translate/vsx-impl.c.inc" |
15848410 | 6295 | |
139c1837 | 6296 | #include "translate/dfp-impl.c.inc" |
15848410 | 6297 | |
139c1837 | 6298 | #include "translate/spe-impl.c.inc" |
15848410 | 6299 | |
1f26c751 DHB |
6300 | #include "translate/branch-impl.c.inc" |
6301 | ||
98f43417 MF |
6302 | #include "translate/processor-ctrl-impl.c.inc" |
6303 | ||
016b6e1d LL |
6304 | #include "translate/storage-ctrl-impl.c.inc" |
6305 | ||
20e2d04e | 6306 | /* Handles lfdp */ |
5cb091a4 ND |
6307 | static void gen_dform39(DisasContext *ctx) |
6308 | { | |
20e2d04e | 6309 | if ((ctx->opcode & 0x3) == 0) { |
5cb091a4 ND |
6310 | if (ctx->insns_flags2 & PPC2_ISA205) { |
6311 | return gen_lfdp(ctx); | |
6312 | } | |
5cb091a4 ND |
6313 | } |
6314 | return gen_invalid(ctx); | |
6315 | } | |
6316 | ||
20e2d04e | 6317 | /* Handles stfdp */ |
e3001664 ND |
6318 | static void gen_dform3D(DisasContext *ctx) |
6319 | { | |
20e2d04e LL |
6320 | if ((ctx->opcode & 3) == 0) { /* DS-FORM */ |
6321 | /* stfdp */ | |
6322 | if (ctx->insns_flags2 & PPC2_ISA205) { | |
6323 | return gen_stfdp(ctx); | |
e3001664 ND |
6324 | } |
6325 | } | |
6326 | return gen_invalid(ctx); | |
6327 | } | |
6328 | ||
9d69cfa2 LP |
6329 | #if defined(TARGET_PPC64) |
6330 | /* brd */ | |
6331 | static void gen_brd(DisasContext *ctx) | |
6332 | { | |
6333 | tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
6334 | } | |
6335 | ||
6336 | /* brw */ | |
6337 | static void gen_brw(DisasContext *ctx) | |
6338 | { | |
6339 | tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
6340 | tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); | |
6341 | ||
6342 | } | |
6343 | ||
6344 | /* brh */ | |
6345 | static void gen_brh(DisasContext *ctx) | |
6346 | { | |
491b3cca | 6347 | TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull); |
9d69cfa2 LP |
6348 | TCGv_i64 t1 = tcg_temp_new_i64(); |
6349 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
6350 | ||
9d69cfa2 | 6351 | tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); |
491b3cca PMD |
6352 | tcg_gen_and_i64(t2, t1, mask); |
6353 | tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); | |
9d69cfa2 LP |
6354 | tcg_gen_shli_i64(t1, t1, 8); |
6355 | tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); | |
9d69cfa2 LP |
6356 | } |
6357 | #endif | |
6358 | ||
c227f099 | 6359 | static opcode_t opcodes[] = { |
9d69cfa2 LP |
6360 | #if defined(TARGET_PPC64) |
6361 | GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), | |
6362 | GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), | |
6363 | GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), | |
6364 | #endif | |
5c55ff99 | 6365 | GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), |
082ce330 ND |
6366 | #if defined(TARGET_PPC64) |
6367 | GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), | |
6368 | #endif | |
fcfda20f | 6369 | GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), |
f2442ef9 | 6370 | GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), |
5c55ff99 | 6371 | GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), |
5c55ff99 BS |
6372 | GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
6373 | GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
5c55ff99 BS |
6374 | GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), |
6375 | GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), | |
6376 | GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), | |
6377 | GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), | |
6378 | GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6379 | #if defined(TARGET_PPC64) | |
6380 | GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), | |
6381 | #endif | |
6382 | GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), | |
6383 | GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), | |
6384 | GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6385 | GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6386 | GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6387 | GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), | |
b35344e4 | 6388 | GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), |
80b8c1ee | 6389 | GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), |
b8b4576e | 6390 | GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), |
80b8c1ee | 6391 | GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), |
5c55ff99 BS |
6392 | GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), |
6393 | GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), | |
6394 | GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6395 | GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6396 | GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6397 | GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6ab39b1b | 6398 | GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), |
eaabeef2 | 6399 | GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), |
725bcec2 | 6400 | GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), |
5c55ff99 | 6401 | #if defined(TARGET_PPC64) |
eaabeef2 | 6402 | GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), |
5c55ff99 | 6403 | GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), |
e91d95b2 | 6404 | GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), |
fec5c62a | 6405 | GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), |
725bcec2 | 6406 | GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), |
86ba37ed | 6407 | GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), |
5c55ff99 BS |
6408 | #endif |
6409 | GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6410 | GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6411 | GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6412 | GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), | |
6413 | GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), | |
6414 | GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), | |
6415 | GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), | |
6416 | #if defined(TARGET_PPC64) | |
6417 | GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), | |
6418 | GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), | |
6419 | GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), | |
6420 | GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), | |
6421 | GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), | |
787bbe37 ND |
6422 | GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, |
6423 | PPC_NONE, PPC2_ISA300), | |
6424 | GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, | |
6425 | PPC_NONE, PPC2_ISA300), | |
5c55ff99 | 6426 | #endif |
5cb091a4 ND |
6427 | /* handles lfdp, lxsd, lxssp */ |
6428 | GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), | |
72b70d5c | 6429 | /* handles stfdp, stxsd, stxssp */ |
e3001664 | 6430 | GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), |
5c55ff99 BS |
6431 | GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
6432 | GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6433 | GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), | |
6434 | GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), | |
6435 | GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), | |
6436 | GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), | |
c8fd8373 | 6437 | GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), |
5c55ff99 | 6438 | GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), |
5c77a786 TM |
6439 | GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), |
6440 | GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), | |
f844c817 | 6441 | GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), |
a68a6146 | 6442 | GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), |
a3401188 | 6443 | GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), |
587c51f7 TM |
6444 | GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), |
6445 | GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), | |
5c55ff99 BS |
6446 | GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), |
6447 | #if defined(TARGET_PPC64) | |
a68a6146 | 6448 | GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), |
a3401188 | 6449 | GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), |
f844c817 | 6450 | GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), |
9c294d5a | 6451 | GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), |
5c55ff99 | 6452 | GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), |
27b95bfe | 6453 | GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), |
5c55ff99 BS |
6454 | #endif |
6455 | GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), | |
0c9717ff NP |
6456 | /* ISA v3.0 changed the extended opcode from 62 to 30 */ |
6457 | GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), | |
6458 | GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), | |
5c55ff99 BS |
6459 | GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), |
6460 | GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
6461 | GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), | |
6462 | GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), | |
4aaefd93 | 6463 | GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), |
5c55ff99 BS |
6464 | GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), |
6465 | GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), | |
6466 | #if defined(TARGET_PPC64) | |
6467 | GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), | |
3c89b8d6 NP |
6468 | #if !defined(CONFIG_USER_ONLY) |
6469 | /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ | |
6470 | GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), | |
6471 | GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), | |
6472 | GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), | |
6473 | #endif | |
cdee0e72 | 6474 | GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), |
7778a575 BH |
6475 | GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), |
6476 | GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), | |
6477 | GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), | |
6478 | GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), | |
5c55ff99 BS |
6479 | GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), |
6480 | #endif | |
3c89b8d6 NP |
6481 | /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ |
6482 | GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), | |
6483 | GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), | |
5c55ff99 BS |
6484 | GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), |
6485 | GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
6486 | #if defined(TARGET_PPC64) | |
6487 | GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), | |
6488 | GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
6489 | #endif | |
6490 | GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), | |
6491 | GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), | |
6492 | GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), | |
6493 | GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), | |
6494 | GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), | |
6495 | GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), | |
6496 | #if defined(TARGET_PPC64) | |
6497 | GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), | |
dc2ee038 | 6498 | GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), |
b63d0434 | 6499 | GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), |
5c55ff99 | 6500 | #endif |
5e31867f | 6501 | GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), |
4248b336 | 6502 | GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), |
5c55ff99 | 6503 | GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), |
50728199 | 6504 | GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), |
5c55ff99 BS |
6505 | GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), |
6506 | GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), | |
50728199 | 6507 | GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), |
3f34cf91 | 6508 | GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), |
50728199 | 6509 | GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), |
3f34cf91 | 6510 | GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), |
50728199 | 6511 | GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), |
4d09d529 | 6512 | GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), |
e64645ba | 6513 | GEN_HANDLER_E(dcblc, 0x1F, 0x06, 0x0c, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), |
8e33944f | 6514 | GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), |
50728199 | 6515 | GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), |
5c55ff99 | 6516 | GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), |
99d45f8f | 6517 | GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), |
5c55ff99 BS |
6518 | GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), |
6519 | GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), | |
50728199 | 6520 | GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), |
5c55ff99 BS |
6521 | GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), |
6522 | GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), | |
6523 | GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), | |
6524 | GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), | |
6525 | GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), | |
6526 | #if defined(TARGET_PPC64) | |
6527 | GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), | |
6528 | GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, | |
6529 | PPC_SEGMENT_64B), | |
6530 | GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), | |
6531 | GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, | |
6532 | PPC_SEGMENT_64B), | |
5c55ff99 BS |
6533 | #endif |
6534 | GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), | |
efe843d8 DG |
6535 | /* |
6536 | * XXX Those instructions will need to be handled differently for | |
6537 | * different ISA versions | |
6538 | */ | |
5c55ff99 | 6539 | GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), |
5c55ff99 BS |
6540 | GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), |
6541 | GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), | |
5c55ff99 BS |
6542 | GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), |
6543 | GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), | |
5c55ff99 BS |
6544 | GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), |
6545 | GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), | |
6546 | GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), | |
6547 | GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), | |
6548 | GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), | |
6549 | GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), | |
5c55ff99 BS |
6550 | GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), |
6551 | GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), | |
6552 | GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), | |
6553 | GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), | |
6554 | GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), | |
6555 | GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), | |
01662f3e | 6556 | GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), |
5c55ff99 BS |
6557 | GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), |
6558 | GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), | |
6559 | GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), | |
6560 | GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), | |
6561 | GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), | |
6562 | GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), | |
6563 | GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), | |
6564 | GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), | |
01662f3e AG |
6565 | GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, |
6566 | PPC_NONE, PPC2_BOOKE206), | |
6567 | GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, | |
6568 | PPC_NONE, PPC2_BOOKE206), | |
6569 | GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, | |
6570 | PPC_NONE, PPC2_BOOKE206), | |
6571 | GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, | |
6572 | PPC_NONE, PPC2_BOOKE206), | |
6d3db821 AG |
6573 | GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, |
6574 | PPC_NONE, PPC2_BOOKE206), | |
5c55ff99 | 6575 | GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), |
fbe73008 | 6576 | GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), |
5c55ff99 | 6577 | GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), |
01662f3e AG |
6578 | GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, |
6579 | PPC_BOOKE, PPC2_BOOKE206), | |
27a3ea7e | 6580 | GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), |
01662f3e AG |
6581 | GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, |
6582 | PPC_BOOKE, PPC2_BOOKE206), | |
0c8d8c8b | 6583 | GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, |
27a3ea7e | 6584 | PPC_440_SPEC), |
5c55ff99 BS |
6585 | GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), |
6586 | GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), | |
6587 | GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), | |
6588 | GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), | |
aeeb044c | 6589 | #if defined(TARGET_PPC64) |
5f29cc82 ND |
6590 | GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, |
6591 | PPC2_ISA300), | |
aeeb044c ND |
6592 | GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), |
6593 | #endif | |
5c55ff99 BS |
6594 | |
6595 | #undef GEN_INT_ARITH_ADD | |
6596 | #undef GEN_INT_ARITH_ADD_CONST | |
6597 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ | |
6598 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), | |
6599 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ | |
6600 | add_ca, compute_ca, compute_ov) \ | |
6601 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), | |
6602 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) | |
6603 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) | |
6604 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) | |
6605 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) | |
6606 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) | |
6607 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) | |
6608 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) | |
6609 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) | |
4c5920af | 6610 | GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), |
5c55ff99 BS |
6611 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) |
6612 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) | |
6613 | ||
6614 | #undef GEN_INT_ARITH_DIVW | |
6615 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ | |
6616 | GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) | |
6617 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), | |
6618 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), | |
6619 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), | |
6620 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), | |
a98eb9e9 TM |
6621 | GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), |
6622 | GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
6a4fda33 TM |
6623 | GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), |
6624 | GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
af2c6620 ND |
6625 | GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), |
6626 | GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), | |
5c55ff99 BS |
6627 | |
6628 | #if defined(TARGET_PPC64) | |
6629 | #undef GEN_INT_ARITH_DIVD | |
6630 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ | |
6631 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) | |
6632 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), | |
6633 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), | |
6634 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), | |
6635 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), | |
6636 | ||
98d1eb27 TM |
6637 | GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), |
6638 | GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
e44259b6 TM |
6639 | GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), |
6640 | GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
063cf14f ND |
6641 | GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), |
6642 | GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), | |
98d1eb27 | 6643 | |
5c55ff99 BS |
6644 | #undef GEN_INT_ARITH_MUL_HELPER |
6645 | #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ | |
6646 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) | |
6647 | GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), | |
6648 | GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), | |
6649 | GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), | |
6650 | #endif | |
6651 | ||
6652 | #undef GEN_INT_ARITH_SUBF | |
6653 | #undef GEN_INT_ARITH_SUBF_CONST | |
6654 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ | |
6655 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), | |
6656 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ | |
6657 | add_ca, compute_ca, compute_ov) \ | |
6658 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), | |
6659 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) | |
6660 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) | |
6661 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) | |
6662 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) | |
6663 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) | |
6664 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) | |
6665 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) | |
6666 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) | |
6667 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) | |
6668 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) | |
6669 | ||
6670 | #undef GEN_LOGICAL1 | |
6671 | #undef GEN_LOGICAL2 | |
6672 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ | |
6673 | GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) | |
6674 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ | |
6675 | GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) | |
6676 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), | |
6677 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), | |
6678 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), | |
6679 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), | |
6680 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), | |
6681 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), | |
6682 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), | |
6683 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), | |
6684 | #if defined(TARGET_PPC64) | |
6685 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), | |
6686 | #endif | |
6687 | ||
6688 | #if defined(TARGET_PPC64) | |
6689 | #undef GEN_PPC64_R2 | |
6690 | #undef GEN_PPC64_R4 | |
6691 | #define GEN_PPC64_R2(name, opc1, opc2) \ | |
6692 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ | |
6693 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ | |
6694 | PPC_64B) | |
6695 | #define GEN_PPC64_R4(name, opc1, opc2) \ | |
6696 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ | |
6697 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ | |
6698 | PPC_64B), \ | |
6699 | GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ | |
6700 | PPC_64B), \ | |
6701 | GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ | |
6702 | PPC_64B) | |
6703 | GEN_PPC64_R4(rldicl, 0x1E, 0x00), | |
6704 | GEN_PPC64_R4(rldicr, 0x1E, 0x02), | |
6705 | GEN_PPC64_R4(rldic, 0x1E, 0x04), | |
6706 | GEN_PPC64_R2(rldcl, 0x1E, 0x08), | |
6707 | GEN_PPC64_R2(rldcr, 0x1E, 0x09), | |
6708 | GEN_PPC64_R4(rldimi, 0x1E, 0x06), | |
6709 | #endif | |
6710 | ||
cd6e9320 | 6711 | #undef GEN_LDX_E |
b7815375 | 6712 | #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ |
cd6e9320 | 6713 | GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), |
f2aabda8 | 6714 | |
5c55ff99 | 6715 | #if defined(TARGET_PPC64) |
ff5f3981 | 6716 | GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) |
b7815375 BH |
6717 | |
6718 | /* HV/P7 and later only */ | |
4f364fe7 | 6719 | GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) |
b7815375 BH |
6720 | GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) |
6721 | GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) | |
6722 | GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) | |
5c55ff99 BS |
6723 | #endif |
6724 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) | |
6725 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) | |
6726 | ||
50728199 RK |
6727 | /* External PID based load */ |
6728 | #undef GEN_LDEPX | |
6729 | #define GEN_LDEPX(name, ldop, opc2, opc3) \ | |
6730 | GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ | |
6731 | 0x00000001, PPC_NONE, PPC2_BOOKE206), | |
6732 | ||
6733 | GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) | |
6734 | GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) | |
6735 | GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) | |
6736 | #if defined(TARGET_PPC64) | |
fc313c64 | 6737 | GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) |
50728199 RK |
6738 | #endif |
6739 | ||
cd6e9320 | 6740 | #undef GEN_STX_E |
b7815375 | 6741 | #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ |
0123d3cb | 6742 | GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), |
e8f4c8d6 | 6743 | |
5c55ff99 | 6744 | #if defined(TARGET_PPC64) |
804108aa | 6745 | GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) |
2468f23d | 6746 | GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) |
b7815375 BH |
6747 | GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) |
6748 | GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) | |
6749 | GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) | |
5c55ff99 BS |
6750 | #endif |
6751 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) | |
6752 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) | |
6753 | ||
50728199 RK |
6754 | #undef GEN_STEPX |
6755 | #define GEN_STEPX(name, ldop, opc2, opc3) \ | |
6756 | GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ | |
6757 | 0x00000001, PPC_NONE, PPC2_BOOKE206), | |
6758 | ||
6759 | GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) | |
6760 | GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) | |
6761 | GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) | |
6762 | #if defined(TARGET_PPC64) | |
fc313c64 | 6763 | GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04) |
50728199 RK |
6764 | #endif |
6765 | ||
5c55ff99 BS |
6766 | #undef GEN_CRLOGIC |
6767 | #define GEN_CRLOGIC(name, tcg_op, opc) \ | |
6768 | GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) | |
6769 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), | |
6770 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), | |
6771 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), | |
6772 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), | |
6773 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), | |
6774 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), | |
6775 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), | |
6776 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), | |
6777 | ||
6778 | #undef GEN_MAC_HANDLER | |
6779 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ | |
6780 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) | |
6781 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05), | |
6782 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), | |
6783 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07), | |
6784 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), | |
6785 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), | |
6786 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), | |
6787 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), | |
6788 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), | |
6789 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01), | |
6790 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), | |
6791 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03), | |
6792 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), | |
6793 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), | |
6794 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), | |
6795 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), | |
6796 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), | |
6797 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), | |
6798 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), | |
6799 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), | |
6800 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), | |
6801 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), | |
6802 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), | |
6803 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), | |
6804 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), | |
6805 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), | |
6806 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), | |
6807 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), | |
6808 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), | |
6809 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), | |
6810 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), | |
6811 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), | |
6812 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), | |
6813 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), | |
6814 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), | |
6815 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), | |
6816 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), | |
6817 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05), | |
6818 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), | |
6819 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), | |
6820 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), | |
6821 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), | |
6822 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), | |
6823 | ||
0ff93d11 TM |
6824 | GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ |
6825 | PPC_NONE, PPC2_TM), | |
56a84615 TM |
6826 | GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ |
6827 | PPC_NONE, PPC2_TM), | |
6828 | GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ | |
6829 | PPC_NONE, PPC2_TM), | |
6830 | GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ | |
6831 | PPC_NONE, PPC2_TM), | |
6832 | GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ | |
6833 | PPC_NONE, PPC2_TM), | |
6834 | GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ | |
6835 | PPC_NONE, PPC2_TM), | |
6836 | GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ | |
6837 | PPC_NONE, PPC2_TM), | |
6838 | GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ | |
6839 | PPC_NONE, PPC2_TM), | |
aeedd582 TM |
6840 | GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ |
6841 | PPC_NONE, PPC2_TM), | |
f83c2378 TM |
6842 | GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ |
6843 | PPC_NONE, PPC2_TM), | |
6844 | GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ | |
6845 | PPC_NONE, PPC2_TM), | |
15848410 | 6846 | |
139c1837 | 6847 | #include "translate/fp-ops.c.inc" |
15848410 | 6848 | |
139c1837 | 6849 | #include "translate/vmx-ops.c.inc" |
15848410 | 6850 | |
139c1837 | 6851 | #include "translate/vsx-ops.c.inc" |
15848410 | 6852 | |
139c1837 | 6853 | #include "translate/spe-ops.c.inc" |
5c55ff99 BS |
6854 | }; |
6855 | ||
7468e2c8 BL |
6856 | /*****************************************************************************/ |
6857 | /* Opcode types */ | |
6858 | enum { | |
6859 | PPC_DIRECT = 0, /* Opcode routine */ | |
6860 | PPC_INDIRECT = 1, /* Indirect opcode table */ | |
6861 | }; | |
6862 | ||
6863 | #define PPC_OPCODE_MASK 0x3 | |
6864 | ||
6865 | static inline int is_indirect_opcode(void *handler) | |
6866 | { | |
6867 | return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; | |
6868 | } | |
6869 | ||
6870 | static inline opc_handler_t **ind_table(void *handler) | |
6871 | { | |
6872 | return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); | |
6873 | } | |
6874 | ||
6875 | /* Instruction table creation */ | |
6876 | /* Opcodes tables creation */ | |
6877 | static void fill_new_table(opc_handler_t **table, int len) | |
6878 | { | |
6879 | int i; | |
6880 | ||
6881 | for (i = 0; i < len; i++) { | |
6882 | table[i] = &invalid_handler; | |
6883 | } | |
6884 | } | |
6885 | ||
6886 | static int create_new_table(opc_handler_t **table, unsigned char idx) | |
6887 | { | |
6888 | opc_handler_t **tmp; | |
6889 | ||
6890 | tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); | |
6891 | fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); | |
6892 | table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); | |
6893 | ||
6894 | return 0; | |
6895 | } | |
6896 | ||
6897 | static int insert_in_table(opc_handler_t **table, unsigned char idx, | |
6898 | opc_handler_t *handler) | |
6899 | { | |
6900 | if (table[idx] != &invalid_handler) { | |
6901 | return -1; | |
6902 | } | |
6903 | table[idx] = handler; | |
6904 | ||
6905 | return 0; | |
6906 | } | |
6907 | ||
6908 | static int register_direct_insn(opc_handler_t **ppc_opcodes, | |
6909 | unsigned char idx, opc_handler_t *handler) | |
6910 | { | |
6911 | if (insert_in_table(ppc_opcodes, idx, handler) < 0) { | |
6912 | printf("*** ERROR: opcode %02x already assigned in main " | |
6913 | "opcode table\n", idx); | |
7468e2c8 BL |
6914 | return -1; |
6915 | } | |
6916 | ||
6917 | return 0; | |
6918 | } | |
6919 | ||
6920 | static int register_ind_in_table(opc_handler_t **table, | |
6921 | unsigned char idx1, unsigned char idx2, | |
6922 | opc_handler_t *handler) | |
6923 | { | |
6924 | if (table[idx1] == &invalid_handler) { | |
6925 | if (create_new_table(table, idx1) < 0) { | |
6926 | printf("*** ERROR: unable to create indirect table " | |
6927 | "idx=%02x\n", idx1); | |
6928 | return -1; | |
6929 | } | |
6930 | } else { | |
6931 | if (!is_indirect_opcode(table[idx1])) { | |
6932 | printf("*** ERROR: idx %02x already assigned to a direct " | |
6933 | "opcode\n", idx1); | |
7468e2c8 BL |
6934 | return -1; |
6935 | } | |
6936 | } | |
6937 | if (handler != NULL && | |
6938 | insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { | |
6939 | printf("*** ERROR: opcode %02x already assigned in " | |
6940 | "opcode table %02x\n", idx2, idx1); | |
7468e2c8 BL |
6941 | return -1; |
6942 | } | |
6943 | ||
6944 | return 0; | |
6945 | } | |
6946 | ||
6947 | static int register_ind_insn(opc_handler_t **ppc_opcodes, | |
6948 | unsigned char idx1, unsigned char idx2, | |
6949 | opc_handler_t *handler) | |
6950 | { | |
6951 | return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); | |
6952 | } | |
6953 | ||
6954 | static int register_dblind_insn(opc_handler_t **ppc_opcodes, | |
6955 | unsigned char idx1, unsigned char idx2, | |
6956 | unsigned char idx3, opc_handler_t *handler) | |
6957 | { | |
6958 | if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { | |
6959 | printf("*** ERROR: unable to join indirect table idx " | |
6960 | "[%02x-%02x]\n", idx1, idx2); | |
6961 | return -1; | |
6962 | } | |
6963 | if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, | |
6964 | handler) < 0) { | |
6965 | printf("*** ERROR: unable to insert opcode " | |
6966 | "[%02x-%02x-%02x]\n", idx1, idx2, idx3); | |
6967 | return -1; | |
6968 | } | |
6969 | ||
6970 | return 0; | |
6971 | } | |
6972 | ||
6973 | static int register_trplind_insn(opc_handler_t **ppc_opcodes, | |
6974 | unsigned char idx1, unsigned char idx2, | |
6975 | unsigned char idx3, unsigned char idx4, | |
6976 | opc_handler_t *handler) | |
6977 | { | |
6978 | opc_handler_t **table; | |
6979 | ||
6980 | if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { | |
6981 | printf("*** ERROR: unable to join indirect table idx " | |
6982 | "[%02x-%02x]\n", idx1, idx2); | |
6983 | return -1; | |
6984 | } | |
6985 | table = ind_table(ppc_opcodes[idx1]); | |
6986 | if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { | |
6987 | printf("*** ERROR: unable to join 2nd-level indirect table idx " | |
6988 | "[%02x-%02x-%02x]\n", idx1, idx2, idx3); | |
6989 | return -1; | |
6990 | } | |
6991 | table = ind_table(table[idx2]); | |
6992 | if (register_ind_in_table(table, idx3, idx4, handler) < 0) { | |
6993 | printf("*** ERROR: unable to insert opcode " | |
6994 | "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); | |
6995 | return -1; | |
6996 | } | |
6997 | return 0; | |
6998 | } | |
6999 | static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) | |
7000 | { | |
7001 | if (insn->opc2 != 0xFF) { | |
7002 | if (insn->opc3 != 0xFF) { | |
7003 | if (insn->opc4 != 0xFF) { | |
7004 | if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, | |
7005 | insn->opc3, insn->opc4, | |
7006 | &insn->handler) < 0) { | |
7007 | return -1; | |
7008 | } | |
7009 | } else { | |
7010 | if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, | |
7011 | insn->opc3, &insn->handler) < 0) { | |
7012 | return -1; | |
7013 | } | |
7014 | } | |
7015 | } else { | |
7016 | if (register_ind_insn(ppc_opcodes, insn->opc1, | |
7017 | insn->opc2, &insn->handler) < 0) { | |
7018 | return -1; | |
7019 | } | |
7020 | } | |
7021 | } else { | |
7022 | if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { | |
7023 | return -1; | |
7024 | } | |
7025 | } | |
7026 | ||
7027 | return 0; | |
7028 | } | |
7029 | ||
7030 | static int test_opcode_table(opc_handler_t **table, int len) | |
7031 | { | |
7032 | int i, count, tmp; | |
7033 | ||
7034 | for (i = 0, count = 0; i < len; i++) { | |
7035 | /* Consistency fixup */ | |
7036 | if (table[i] == NULL) { | |
7037 | table[i] = &invalid_handler; | |
7038 | } | |
7039 | if (table[i] != &invalid_handler) { | |
7040 | if (is_indirect_opcode(table[i])) { | |
7041 | tmp = test_opcode_table(ind_table(table[i]), | |
7042 | PPC_CPU_INDIRECT_OPCODES_LEN); | |
7043 | if (tmp == 0) { | |
7044 | free(table[i]); | |
7045 | table[i] = &invalid_handler; | |
7046 | } else { | |
7047 | count++; | |
7048 | } | |
7049 | } else { | |
7050 | count++; | |
7051 | } | |
7052 | } | |
7053 | } | |
7054 | ||
7055 | return count; | |
7056 | } | |
7057 | ||
7058 | static void fix_opcode_tables(opc_handler_t **ppc_opcodes) | |
7059 | { | |
7060 | if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { | |
7061 | printf("*** WARNING: no opcode defined !\n"); | |
7062 | } | |
7063 | } | |
7064 | ||
7065 | /*****************************************************************************/ | |
7066 | void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) | |
7067 | { | |
7068 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); | |
7069 | opcode_t *opc; | |
7070 | ||
7071 | fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); | |
7072 | for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { | |
7073 | if (((opc->handler.type & pcc->insns_flags) != 0) || | |
7074 | ((opc->handler.type2 & pcc->insns_flags2) != 0)) { | |
7075 | if (register_insn(cpu->opcodes, opc) < 0) { | |
7076 | error_setg(errp, "ERROR initializing PowerPC instruction " | |
7077 | "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, | |
7078 | opc->opc3); | |
7079 | return; | |
7080 | } | |
7081 | } | |
7082 | } | |
7083 | fix_opcode_tables(cpu->opcodes); | |
7084 | fflush(stdout); | |
7085 | fflush(stderr); | |
7086 | } | |
7087 | ||
7088 | void destroy_ppc_opcodes(PowerPCCPU *cpu) | |
7089 | { | |
7090 | opc_handler_t **table, **table_2; | |
7091 | int i, j, k; | |
7092 | ||
7093 | for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { | |
7094 | if (cpu->opcodes[i] == &invalid_handler) { | |
7095 | continue; | |
7096 | } | |
7097 | if (is_indirect_opcode(cpu->opcodes[i])) { | |
7098 | table = ind_table(cpu->opcodes[i]); | |
7099 | for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { | |
7100 | if (table[j] == &invalid_handler) { | |
7101 | continue; | |
7102 | } | |
7103 | if (is_indirect_opcode(table[j])) { | |
7104 | table_2 = ind_table(table[j]); | |
7105 | for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { | |
7106 | if (table_2[k] != &invalid_handler && | |
7107 | is_indirect_opcode(table_2[k])) { | |
7108 | g_free((opc_handler_t *)((uintptr_t)table_2[k] & | |
7109 | ~PPC_INDIRECT)); | |
7110 | } | |
7111 | } | |
7112 | g_free((opc_handler_t *)((uintptr_t)table[j] & | |
7113 | ~PPC_INDIRECT)); | |
7114 | } | |
7115 | } | |
7116 | g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & | |
7117 | ~PPC_INDIRECT)); | |
7118 | } | |
7119 | } | |
7120 | } | |
7121 | ||
7468e2c8 BL |
7122 | int ppc_fixup_cpu(PowerPCCPU *cpu) |
7123 | { | |
7124 | CPUPPCState *env = &cpu->env; | |
7125 | ||
7126 | /* | |
7127 | * TCG doesn't (yet) emulate some groups of instructions that are | |
7128 | * implemented on some otherwise supported CPUs (e.g. VSX and | |
7129 | * decimal floating point instructions on POWER7). We remove | |
7130 | * unsupported instruction groups from the cpu state's instruction | |
7131 | * masks and hope the guest can cope. For at least the pseries | |
7132 | * machine, the unavailability of these instructions can be | |
7133 | * advertised to the guest via the device tree. | |
7134 | */ | |
7135 | if ((env->insns_flags & ~PPC_TCG_INSNS) | |
7136 | || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { | |
7137 | warn_report("Disabling some instructions which are not " | |
7138 | "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", | |
7139 | env->insns_flags & ~PPC_TCG_INSNS, | |
7140 | env->insns_flags2 & ~PPC_TCG_INSNS2); | |
7141 | } | |
7142 | env->insns_flags &= PPC_TCG_INSNS; | |
7143 | env->insns_flags2 &= PPC_TCG_INSNS2; | |
7144 | return 0; | |
7145 | } | |
7146 | ||
624cb07f RH |
7147 | static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) |
7148 | { | |
7149 | opc_handler_t **table, *handler; | |
7150 | uint32_t inval; | |
7151 | ||
7152 | ctx->opcode = insn; | |
7153 | ||
7154 | LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", | |
7155 | insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), | |
7156 | ctx->le_mode ? "little" : "big"); | |
7157 | ||
7158 | table = cpu->opcodes; | |
7159 | handler = table[opc1(insn)]; | |
7160 | if (is_indirect_opcode(handler)) { | |
7161 | table = ind_table(handler); | |
7162 | handler = table[opc2(insn)]; | |
7163 | if (is_indirect_opcode(handler)) { | |
7164 | table = ind_table(handler); | |
7165 | handler = table[opc3(insn)]; | |
7166 | if (is_indirect_opcode(handler)) { | |
7167 | table = ind_table(handler); | |
7168 | handler = table[opc4(insn)]; | |
7169 | } | |
7170 | } | |
7171 | } | |
7172 | ||
7173 | /* Is opcode *REALLY* valid ? */ | |
7174 | if (unlikely(handler->handler == &gen_invalid)) { | |
7175 | qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " | |
7176 | "%02x - %02x - %02x - %02x (%08x) " | |
7177 | TARGET_FMT_lx "\n", | |
7178 | opc1(insn), opc2(insn), opc3(insn), opc4(insn), | |
7179 | insn, ctx->cia); | |
7180 | return false; | |
7181 | } | |
7182 | ||
7183 | if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) | |
7184 | && Rc(insn))) { | |
7185 | inval = handler->inval2; | |
7186 | } else { | |
7187 | inval = handler->inval1; | |
7188 | } | |
7189 | ||
7190 | if (unlikely((insn & inval) != 0)) { | |
7191 | qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " | |
7192 | "%02x - %02x - %02x - %02x (%08x) " | |
7193 | TARGET_FMT_lx "\n", insn & inval, | |
7194 | opc1(insn), opc2(insn), opc3(insn), opc4(insn), | |
7195 | insn, ctx->cia); | |
7196 | return false; | |
7197 | } | |
7198 | ||
7199 | handler->handler(ctx); | |
7200 | return true; | |
7201 | } | |
7202 | ||
b542683d | 7203 | static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) |
79aceca5 | 7204 | { |
b0c2d521 | 7205 | DisasContext *ctx = container_of(dcbase, DisasContext, base); |
9c489ea6 | 7206 | CPUPPCState *env = cs->env_ptr; |
2df4fe7a | 7207 | uint32_t hflags = ctx->base.tb->flags; |
b0c2d521 | 7208 | |
b0c2d521 | 7209 | ctx->spr_cb = env->spr_cb; |
2df4fe7a | 7210 | ctx->pr = (hflags >> HFLAGS_PR) & 1; |
d764184d | 7211 | ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; |
2df4fe7a RH |
7212 | ctx->dr = (hflags >> HFLAGS_DR) & 1; |
7213 | ctx->hv = (hflags >> HFLAGS_HV) & 1; | |
b0c2d521 EC |
7214 | ctx->insns_flags = env->insns_flags; |
7215 | ctx->insns_flags2 = env->insns_flags2; | |
7216 | ctx->access_type = -1; | |
d57d72a8 | 7217 | ctx->need_access_type = !mmu_is_64bit(env->mmu_model); |
2df4fe7a | 7218 | ctx->le_mode = (hflags >> HFLAGS_LE) & 1; |
b0c2d521 | 7219 | ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; |
0e3bf489 | 7220 | ctx->flags = env->flags; |
d9bce9d9 | 7221 | #if defined(TARGET_PPC64) |
2df4fe7a | 7222 | ctx->sf_mode = (hflags >> HFLAGS_64) & 1; |
b0c2d521 | 7223 | ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); |
9a64fbe4 | 7224 | #endif |
e69ba2b4 | 7225 | ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B |
d55dfd44 | 7226 | || env->mmu_model & POWERPC_MMU_64; |
c5a8d8f3 | 7227 | |
2df4fe7a RH |
7228 | ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; |
7229 | ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; | |
7230 | ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; | |
7231 | ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; | |
2df4fe7a | 7232 | ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; |
f03de3b4 | 7233 | ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; |
1db3632a | 7234 | ctx->hr = (hflags >> HFLAGS_HR) & 1; |
f7460df2 DHB |
7235 | ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1; |
7236 | ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1; | |
8b3d1c49 LL |
7237 | ctx->mmcr0_pmcjce = (hflags >> HFLAGS_PMCJCE) & 1; |
7238 | ctx->pmc_other = (hflags >> HFLAGS_PMC_OTHER) & 1; | |
46d396bd | 7239 | ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1; |
2df4fe7a RH |
7240 | |
7241 | ctx->singlestep_enabled = 0; | |
7242 | if ((hflags >> HFLAGS_SE) & 1) { | |
7243 | ctx->singlestep_enabled |= CPU_SINGLE_STEP; | |
9498d103 | 7244 | ctx->base.max_insns = 1; |
efe843d8 | 7245 | } |
2df4fe7a | 7246 | if ((hflags >> HFLAGS_BE) & 1) { |
b0c2d521 | 7247 | ctx->singlestep_enabled |= CPU_BRANCH_STEP; |
efe843d8 | 7248 | } |
b0c2d521 EC |
7249 | } |
7250 | ||
7251 | static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) | |
7252 | { | |
7253 | } | |
7254 | ||
7255 | static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) | |
7256 | { | |
7257 | tcg_gen_insn_start(dcbase->pc_next); | |
7258 | } | |
7259 | ||
99082815 RH |
7260 | static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) |
7261 | { | |
7262 | REQUIRE_INSNS_FLAGS2(ctx, ISA310); | |
7263 | return opc1(insn) == 1; | |
7264 | } | |
7265 | ||
b0c2d521 EC |
7266 | static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) |
7267 | { | |
7268 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
28876bf2 | 7269 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
b0c2d521 | 7270 | CPUPPCState *env = cs->env_ptr; |
99082815 | 7271 | target_ulong pc; |
624cb07f RH |
7272 | uint32_t insn; |
7273 | bool ok; | |
b0c2d521 EC |
7274 | |
7275 | LOG_DISAS("----------------\n"); | |
7276 | LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", | |
7277 | ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); | |
7278 | ||
99082815 | 7279 | ctx->cia = pc = ctx->base.pc_next; |
4e116893 | 7280 | insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx)); |
99082815 | 7281 | ctx->base.pc_next = pc += 4; |
70560da7 | 7282 | |
99082815 RH |
7283 | if (!is_prefix_insn(ctx, insn)) { |
7284 | ok = (decode_insn32(ctx, insn) || | |
7285 | decode_legacy(cpu, ctx, insn)); | |
7286 | } else if ((pc & 63) == 0) { | |
7287 | /* | |
7288 | * Power v3.1, section 1.9 Exceptions: | |
7289 | * attempt to execute a prefixed instruction that crosses a | |
7290 | * 64-byte address boundary (system alignment error). | |
7291 | */ | |
7292 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); | |
7293 | ok = true; | |
7294 | } else { | |
4e116893 IL |
7295 | uint32_t insn2 = translator_ldl_swap(env, dcbase, pc, |
7296 | need_byteswap(ctx)); | |
99082815 RH |
7297 | ctx->base.pc_next = pc += 4; |
7298 | ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); | |
7299 | } | |
624cb07f RH |
7300 | if (!ok) { |
7301 | gen_invalid(ctx); | |
b0c2d521 | 7302 | } |
624cb07f | 7303 | |
64a0f644 | 7304 | /* End the TB when crossing a page boundary. */ |
99082815 | 7305 | if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { |
64a0f644 RH |
7306 | ctx->base.is_jmp = DISAS_TOO_MANY; |
7307 | } | |
b0c2d521 EC |
7308 | } |
7309 | ||
7310 | static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) | |
7311 | { | |
7312 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
a9b5b3d0 RH |
7313 | DisasJumpType is_jmp = ctx->base.is_jmp; |
7314 | target_ulong nip = ctx->base.pc_next; | |
b0c2d521 | 7315 | |
a9b5b3d0 RH |
7316 | if (is_jmp == DISAS_NORETURN) { |
7317 | /* We have already exited the TB. */ | |
3d8a5b69 RH |
7318 | return; |
7319 | } | |
7320 | ||
a9b5b3d0 | 7321 | /* Honor single stepping. */ |
9498d103 RH |
7322 | if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP) |
7323 | && (nip <= 0x100 || nip > 0xf00)) { | |
a9b5b3d0 RH |
7324 | switch (is_jmp) { |
7325 | case DISAS_TOO_MANY: | |
7326 | case DISAS_EXIT_UPDATE: | |
7327 | case DISAS_CHAIN_UPDATE: | |
7328 | gen_update_nip(ctx, nip); | |
7329 | break; | |
7330 | case DISAS_EXIT: | |
7331 | case DISAS_CHAIN: | |
7332 | break; | |
7333 | default: | |
7334 | g_assert_not_reached(); | |
8cbcb4fa | 7335 | } |
13b45575 | 7336 | |
9498d103 RH |
7337 | gen_debug_exception(ctx); |
7338 | return; | |
a9b5b3d0 RH |
7339 | } |
7340 | ||
7341 | switch (is_jmp) { | |
7342 | case DISAS_TOO_MANY: | |
7343 | if (use_goto_tb(ctx, nip)) { | |
46d396bd | 7344 | pmu_count_insns(ctx); |
a9b5b3d0 RH |
7345 | tcg_gen_goto_tb(0); |
7346 | gen_update_nip(ctx, nip); | |
7347 | tcg_gen_exit_tb(ctx->base.tb, 0); | |
7348 | break; | |
7349 | } | |
7350 | /* fall through */ | |
7351 | case DISAS_CHAIN_UPDATE: | |
7352 | gen_update_nip(ctx, nip); | |
7353 | /* fall through */ | |
7354 | case DISAS_CHAIN: | |
46d396bd DHB |
7355 | /* |
7356 | * tcg_gen_lookup_and_goto_ptr will exit the TB if | |
7357 | * CF_NO_GOTO_PTR is set. Count insns now. | |
7358 | */ | |
7359 | if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { | |
7360 | pmu_count_insns(ctx); | |
7361 | } | |
7362 | ||
a9b5b3d0 RH |
7363 | tcg_gen_lookup_and_goto_ptr(); |
7364 | break; | |
7365 | ||
7366 | case DISAS_EXIT_UPDATE: | |
7367 | gen_update_nip(ctx, nip); | |
7368 | /* fall through */ | |
7369 | case DISAS_EXIT: | |
46d396bd | 7370 | pmu_count_insns(ctx); |
07ea28b4 | 7371 | tcg_gen_exit_tb(NULL, 0); |
a9b5b3d0 RH |
7372 | break; |
7373 | ||
7374 | default: | |
7375 | g_assert_not_reached(); | |
9a64fbe4 | 7376 | } |
b0c2d521 EC |
7377 | } |
7378 | ||
8eb806a7 RH |
7379 | static void ppc_tr_disas_log(const DisasContextBase *dcbase, |
7380 | CPUState *cs, FILE *logfile) | |
b0c2d521 | 7381 | { |
8eb806a7 RH |
7382 | fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); |
7383 | target_disas(logfile, cs, dcbase->pc_first, dcbase->tb->size); | |
b0c2d521 | 7384 | } |
0a7df5da | 7385 | |
b0c2d521 EC |
7386 | static const TranslatorOps ppc_tr_ops = { |
7387 | .init_disas_context = ppc_tr_init_disas_context, | |
7388 | .tb_start = ppc_tr_tb_start, | |
7389 | .insn_start = ppc_tr_insn_start, | |
b0c2d521 EC |
7390 | .translate_insn = ppc_tr_translate_insn, |
7391 | .tb_stop = ppc_tr_tb_stop, | |
7392 | .disas_log = ppc_tr_disas_log, | |
7393 | }; | |
4e5e1215 | 7394 | |
597f9b2d | 7395 | void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, |
306c8721 | 7396 | target_ulong pc, void *host_pc) |
b0c2d521 EC |
7397 | { |
7398 | DisasContext ctx; | |
7399 | ||
306c8721 | 7400 | translator_loop(cs, tb, max_insns, pc, host_pc, &ppc_tr_ops, &ctx.base); |
79aceca5 | 7401 | } |