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79aceca5 | 1 | /* |
3fc6c082 | 2 | * PowerPC emulation for qemu: main translation routines. |
5fafdf24 | 3 | * |
76a66253 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
90dc8812 | 5 | * Copyright (C) 2011 Freescale Semiconductor, Inc. |
79aceca5 FB |
6 | * |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
79aceca5 | 19 | */ |
c6a1c22b | 20 | |
0d75590d | 21 | #include "qemu/osdep.h" |
79aceca5 | 22 | #include "cpu.h" |
3e00884f | 23 | #include "internal.h" |
76cad711 | 24 | #include "disas/disas.h" |
63c91552 | 25 | #include "exec/exec-all.h" |
dcb32f1d PMD |
26 | #include "tcg/tcg-op.h" |
27 | #include "tcg/tcg-op-gvec.h" | |
1de7afc9 | 28 | #include "qemu/host-utils.h" |
db725815 | 29 | #include "qemu/main-loop.h" |
f08b6170 | 30 | #include "exec/cpu_ldst.h" |
79aceca5 | 31 | |
2ef6175a RH |
32 | #include "exec/helper-proto.h" |
33 | #include "exec/helper-gen.h" | |
a7812ae4 | 34 | |
a7e30d84 | 35 | #include "trace-tcg.h" |
b6bac4bc | 36 | #include "exec/translator.h" |
508127e2 | 37 | #include "exec/log.h" |
f34ec0f6 | 38 | #include "qemu/atomic128.h" |
a7e30d84 LV |
39 | |
40 | ||
8cbcb4fa AJ |
41 | #define CPU_SINGLE_STEP 0x1 |
42 | #define CPU_BRANCH_STEP 0x2 | |
43 | #define GDBSTUB_SINGLE_STEP 0x4 | |
44 | ||
a750fc0b | 45 | /* Include definitions for instructions classes and implementations flags */ |
efe843d8 DG |
46 | /* #define PPC_DEBUG_DISAS */ |
47 | /* #define DO_PPC_STATISTICS */ | |
79aceca5 | 48 | |
d12d51d5 | 49 | #ifdef PPC_DEBUG_DISAS |
93fcfe39 | 50 | # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) |
d12d51d5 AL |
51 | #else |
52 | # define LOG_DISAS(...) do { } while (0) | |
53 | #endif | |
a750fc0b JM |
54 | /*****************************************************************************/ |
55 | /* Code translation helpers */ | |
c53be334 | 56 | |
f78fb44e | 57 | /* global register indexes */ |
efe843d8 DG |
58 | static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ |
59 | + 10 * 4 + 22 * 5 /* SPE GPRh */ | |
60 | + 8 * 5 /* CRF */]; | |
f78fb44e | 61 | static TCGv cpu_gpr[32]; |
f78fb44e | 62 | static TCGv cpu_gprh[32]; |
a7812ae4 | 63 | static TCGv_i32 cpu_crf[8]; |
bd568f18 | 64 | static TCGv cpu_nip; |
6527f6ea | 65 | static TCGv cpu_msr; |
cfdcd37a AJ |
66 | static TCGv cpu_ctr; |
67 | static TCGv cpu_lr; | |
697ab892 DG |
68 | #if defined(TARGET_PPC64) |
69 | static TCGv cpu_cfar; | |
70 | #endif | |
dd09c361 | 71 | static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; |
cf360a32 | 72 | static TCGv cpu_reserve; |
253ce7b2 | 73 | static TCGv cpu_reserve_val; |
30304420 | 74 | static TCGv cpu_fpscr; |
a7859e89 | 75 | static TCGv_i32 cpu_access_type; |
f78fb44e | 76 | |
022c62cb | 77 | #include "exec/gen-icount.h" |
2e70f6ef PB |
78 | |
79 | void ppc_translate_init(void) | |
80 | { | |
f78fb44e | 81 | int i; |
efe843d8 | 82 | char *p; |
2dc766da | 83 | size_t cpu_reg_names_size; |
f78fb44e | 84 | |
f78fb44e | 85 | p = cpu_reg_names; |
2dc766da | 86 | cpu_reg_names_size = sizeof(cpu_reg_names); |
47e4661c AJ |
87 | |
88 | for (i = 0; i < 8; i++) { | |
2dc766da | 89 | snprintf(p, cpu_reg_names_size, "crf%d", i); |
e1ccc054 | 90 | cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, |
1328c2bf | 91 | offsetof(CPUPPCState, crf[i]), p); |
47e4661c | 92 | p += 5; |
2dc766da | 93 | cpu_reg_names_size -= 5; |
47e4661c AJ |
94 | } |
95 | ||
f78fb44e | 96 | for (i = 0; i < 32; i++) { |
2dc766da | 97 | snprintf(p, cpu_reg_names_size, "r%d", i); |
e1ccc054 | 98 | cpu_gpr[i] = tcg_global_mem_new(cpu_env, |
1328c2bf | 99 | offsetof(CPUPPCState, gpr[i]), p); |
f78fb44e | 100 | p += (i < 10) ? 3 : 4; |
2dc766da | 101 | cpu_reg_names_size -= (i < 10) ? 3 : 4; |
2dc766da | 102 | snprintf(p, cpu_reg_names_size, "r%dH", i); |
e1ccc054 | 103 | cpu_gprh[i] = tcg_global_mem_new(cpu_env, |
13b6a455 | 104 | offsetof(CPUPPCState, gprh[i]), p); |
f78fb44e | 105 | p += (i < 10) ? 4 : 5; |
2dc766da | 106 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
f78fb44e | 107 | } |
f10dc08e | 108 | |
e1ccc054 | 109 | cpu_nip = tcg_global_mem_new(cpu_env, |
1328c2bf | 110 | offsetof(CPUPPCState, nip), "nip"); |
bd568f18 | 111 | |
e1ccc054 | 112 | cpu_msr = tcg_global_mem_new(cpu_env, |
1328c2bf | 113 | offsetof(CPUPPCState, msr), "msr"); |
6527f6ea | 114 | |
e1ccc054 | 115 | cpu_ctr = tcg_global_mem_new(cpu_env, |
1328c2bf | 116 | offsetof(CPUPPCState, ctr), "ctr"); |
cfdcd37a | 117 | |
e1ccc054 | 118 | cpu_lr = tcg_global_mem_new(cpu_env, |
1328c2bf | 119 | offsetof(CPUPPCState, lr), "lr"); |
cfdcd37a | 120 | |
697ab892 | 121 | #if defined(TARGET_PPC64) |
e1ccc054 | 122 | cpu_cfar = tcg_global_mem_new(cpu_env, |
1328c2bf | 123 | offsetof(CPUPPCState, cfar), "cfar"); |
697ab892 DG |
124 | #endif |
125 | ||
e1ccc054 | 126 | cpu_xer = tcg_global_mem_new(cpu_env, |
1328c2bf | 127 | offsetof(CPUPPCState, xer), "xer"); |
e1ccc054 | 128 | cpu_so = tcg_global_mem_new(cpu_env, |
da91a00f | 129 | offsetof(CPUPPCState, so), "SO"); |
e1ccc054 | 130 | cpu_ov = tcg_global_mem_new(cpu_env, |
da91a00f | 131 | offsetof(CPUPPCState, ov), "OV"); |
e1ccc054 | 132 | cpu_ca = tcg_global_mem_new(cpu_env, |
da91a00f | 133 | offsetof(CPUPPCState, ca), "CA"); |
dd09c361 ND |
134 | cpu_ov32 = tcg_global_mem_new(cpu_env, |
135 | offsetof(CPUPPCState, ov32), "OV32"); | |
136 | cpu_ca32 = tcg_global_mem_new(cpu_env, | |
137 | offsetof(CPUPPCState, ca32), "CA32"); | |
3d7b417e | 138 | |
e1ccc054 | 139 | cpu_reserve = tcg_global_mem_new(cpu_env, |
1328c2bf | 140 | offsetof(CPUPPCState, reserve_addr), |
18b21a2f | 141 | "reserve_addr"); |
253ce7b2 ND |
142 | cpu_reserve_val = tcg_global_mem_new(cpu_env, |
143 | offsetof(CPUPPCState, reserve_val), | |
144 | "reserve_val"); | |
cf360a32 | 145 | |
e1ccc054 | 146 | cpu_fpscr = tcg_global_mem_new(cpu_env, |
30304420 | 147 | offsetof(CPUPPCState, fpscr), "fpscr"); |
e1571908 | 148 | |
e1ccc054 | 149 | cpu_access_type = tcg_global_mem_new_i32(cpu_env, |
efe843d8 DG |
150 | offsetof(CPUPPCState, access_type), |
151 | "access_type"); | |
2e70f6ef PB |
152 | } |
153 | ||
79aceca5 | 154 | /* internal defines */ |
69b058c8 | 155 | struct DisasContext { |
b6bac4bc | 156 | DisasContextBase base; |
79aceca5 | 157 | uint32_t opcode; |
9a64fbe4 | 158 | uint32_t exception; |
3cc62370 | 159 | /* Routine used to access memory */ |
5c3ae929 | 160 | bool pr, hv, dr, le_mode; |
c5a8d8f3 | 161 | bool lazy_tlb_flush; |
5f2a6254 | 162 | bool need_access_type; |
3cc62370 | 163 | int mem_idx; |
76db3ba4 | 164 | int access_type; |
3cc62370 | 165 | /* Translation flags */ |
14776ab5 | 166 | MemOp default_tcg_memop_mask; |
d9bce9d9 | 167 | #if defined(TARGET_PPC64) |
5c3ae929 BH |
168 | bool sf_mode; |
169 | bool has_cfar; | |
9a64fbe4 | 170 | #endif |
5c3ae929 BH |
171 | bool fpu_enabled; |
172 | bool altivec_enabled; | |
173 | bool vsx_enabled; | |
174 | bool spe_enabled; | |
175 | bool tm_enabled; | |
c6fd28fd | 176 | bool gtse; |
c227f099 | 177 | ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ |
ea4e754f | 178 | int singlestep_enabled; |
0e3bf489 | 179 | uint32_t flags; |
7d08d856 AJ |
180 | uint64_t insns_flags; |
181 | uint64_t insns_flags2; | |
69b058c8 | 182 | }; |
79aceca5 | 183 | |
e22c357b DK |
184 | /* Return true iff byteswap is needed in a scalar memop */ |
185 | static inline bool need_byteswap(const DisasContext *ctx) | |
186 | { | |
187 | #if defined(TARGET_WORDS_BIGENDIAN) | |
188 | return ctx->le_mode; | |
189 | #else | |
190 | return !ctx->le_mode; | |
191 | #endif | |
192 | } | |
193 | ||
79482e5a RH |
194 | /* True when active word size < size of target_long. */ |
195 | #ifdef TARGET_PPC64 | |
196 | # define NARROW_MODE(C) (!(C)->sf_mode) | |
197 | #else | |
198 | # define NARROW_MODE(C) 0 | |
199 | #endif | |
200 | ||
c227f099 | 201 | struct opc_handler_t { |
70560da7 FC |
202 | /* invalid bits for instruction 1 (Rc(opcode) == 0) */ |
203 | uint32_t inval1; | |
204 | /* invalid bits for instruction 2 (Rc(opcode) == 1) */ | |
205 | uint32_t inval2; | |
9a64fbe4 | 206 | /* instruction type */ |
0487d6a8 | 207 | uint64_t type; |
a5858d7a AG |
208 | /* extended instruction type */ |
209 | uint64_t type2; | |
79aceca5 FB |
210 | /* handler */ |
211 | void (*handler)(DisasContext *ctx); | |
a750fc0b | 212 | #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) |
b55266b5 | 213 | const char *oname; |
a750fc0b JM |
214 | #endif |
215 | #if defined(DO_PPC_STATISTICS) | |
76a66253 JM |
216 | uint64_t count; |
217 | #endif | |
3fc6c082 | 218 | }; |
79aceca5 | 219 | |
0e3bf489 RK |
220 | /* SPR load/store helpers */ |
221 | static inline void gen_load_spr(TCGv t, int reg) | |
222 | { | |
223 | tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); | |
224 | } | |
225 | ||
226 | static inline void gen_store_spr(int reg, TCGv t) | |
227 | { | |
228 | tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); | |
229 | } | |
230 | ||
636aa200 | 231 | static inline void gen_set_access_type(DisasContext *ctx, int access_type) |
a7859e89 | 232 | { |
5f2a6254 | 233 | if (ctx->need_access_type && ctx->access_type != access_type) { |
76db3ba4 AJ |
234 | tcg_gen_movi_i32(cpu_access_type, access_type); |
235 | ctx->access_type = access_type; | |
236 | } | |
a7859e89 AJ |
237 | } |
238 | ||
636aa200 | 239 | static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) |
d9bce9d9 | 240 | { |
e0c8f9ce RH |
241 | if (NARROW_MODE(ctx)) { |
242 | nip = (uint32_t)nip; | |
243 | } | |
244 | tcg_gen_movi_tl(cpu_nip, nip); | |
d9bce9d9 JM |
245 | } |
246 | ||
b9971cc5 | 247 | static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) |
e06fcd75 AJ |
248 | { |
249 | TCGv_i32 t0, t1; | |
bd6fefe7 | 250 | |
efe843d8 DG |
251 | /* |
252 | * These are all synchronous exceptions, we set the PC back to the | |
253 | * faulting instruction | |
bd6fefe7 | 254 | */ |
e06fcd75 | 255 | if (ctx->exception == POWERPC_EXCP_NONE) { |
b6bac4bc | 256 | gen_update_nip(ctx, ctx->base.pc_next - 4); |
e06fcd75 AJ |
257 | } |
258 | t0 = tcg_const_i32(excp); | |
259 | t1 = tcg_const_i32(error); | |
e5f17ac6 | 260 | gen_helper_raise_exception_err(cpu_env, t0, t1); |
e06fcd75 AJ |
261 | tcg_temp_free_i32(t0); |
262 | tcg_temp_free_i32(t1); | |
263 | ctx->exception = (excp); | |
264 | } | |
e1833e1f | 265 | |
b9971cc5 | 266 | static void gen_exception(DisasContext *ctx, uint32_t excp) |
e06fcd75 AJ |
267 | { |
268 | TCGv_i32 t0; | |
bd6fefe7 | 269 | |
efe843d8 DG |
270 | /* |
271 | * These are all synchronous exceptions, we set the PC back to the | |
272 | * faulting instruction | |
bd6fefe7 | 273 | */ |
e06fcd75 | 274 | if (ctx->exception == POWERPC_EXCP_NONE) { |
b6bac4bc | 275 | gen_update_nip(ctx, ctx->base.pc_next - 4); |
e06fcd75 AJ |
276 | } |
277 | t0 = tcg_const_i32(excp); | |
e5f17ac6 | 278 | gen_helper_raise_exception(cpu_env, t0); |
e06fcd75 AJ |
279 | tcg_temp_free_i32(t0); |
280 | ctx->exception = (excp); | |
281 | } | |
e1833e1f | 282 | |
bd6fefe7 BH |
283 | static void gen_exception_nip(DisasContext *ctx, uint32_t excp, |
284 | target_ulong nip) | |
285 | { | |
286 | TCGv_i32 t0; | |
287 | ||
288 | gen_update_nip(ctx, nip); | |
289 | t0 = tcg_const_i32(excp); | |
290 | gen_helper_raise_exception(cpu_env, t0); | |
291 | tcg_temp_free_i32(t0); | |
292 | ctx->exception = (excp); | |
293 | } | |
294 | ||
e150ac89 RK |
295 | /* |
296 | * Tells the caller what is the appropriate exception to generate and prepares | |
297 | * SPR registers for this exception. | |
298 | * | |
299 | * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or | |
300 | * POWERPC_EXCP_DEBUG (on BookE). | |
0e3bf489 | 301 | */ |
e150ac89 | 302 | static uint32_t gen_prep_dbgex(DisasContext *ctx) |
0e3bf489 | 303 | { |
0e3bf489 RK |
304 | if (ctx->flags & POWERPC_FLAG_DE) { |
305 | target_ulong dbsr = 0; | |
e150ac89 | 306 | if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { |
0e3bf489 | 307 | dbsr = DBCR0_ICMP; |
e150ac89 RK |
308 | } else { |
309 | /* Must have been branch */ | |
0e3bf489 | 310 | dbsr = DBCR0_BRT; |
0e3bf489 RK |
311 | } |
312 | TCGv t0 = tcg_temp_new(); | |
313 | gen_load_spr(t0, SPR_BOOKE_DBSR); | |
314 | tcg_gen_ori_tl(t0, t0, dbsr); | |
315 | gen_store_spr(SPR_BOOKE_DBSR, t0); | |
316 | tcg_temp_free(t0); | |
317 | return POWERPC_EXCP_DEBUG; | |
318 | } else { | |
e150ac89 | 319 | return POWERPC_EXCP_TRACE; |
0e3bf489 RK |
320 | } |
321 | } | |
322 | ||
b9971cc5 | 323 | static void gen_debug_exception(DisasContext *ctx) |
e06fcd75 AJ |
324 | { |
325 | TCGv_i32 t0; | |
5518f3a6 | 326 | |
efe843d8 DG |
327 | /* |
328 | * These are all synchronous exceptions, we set the PC back to the | |
329 | * faulting instruction | |
bd6fefe7 | 330 | */ |
ee2b3994 SB |
331 | if ((ctx->exception != POWERPC_EXCP_BRANCH) && |
332 | (ctx->exception != POWERPC_EXCP_SYNC)) { | |
b6bac4bc | 333 | gen_update_nip(ctx, ctx->base.pc_next); |
ee2b3994 | 334 | } |
e06fcd75 | 335 | t0 = tcg_const_i32(EXCP_DEBUG); |
e5f17ac6 | 336 | gen_helper_raise_exception(cpu_env, t0); |
e06fcd75 AJ |
337 | tcg_temp_free_i32(t0); |
338 | } | |
9a64fbe4 | 339 | |
636aa200 | 340 | static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) |
e06fcd75 | 341 | { |
9b2fadda BH |
342 | /* Will be converted to program check if needed */ |
343 | gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); | |
344 | } | |
345 | ||
346 | static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) | |
347 | { | |
348 | gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); | |
349 | } | |
350 | ||
351 | static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) | |
352 | { | |
353 | /* Will be converted to program check if needed */ | |
354 | gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); | |
e06fcd75 | 355 | } |
a9d9eb8f | 356 | |
f24e5695 | 357 | /* Stop translation */ |
636aa200 | 358 | static inline void gen_stop_exception(DisasContext *ctx) |
3fc6c082 | 359 | { |
b6bac4bc | 360 | gen_update_nip(ctx, ctx->base.pc_next); |
e1833e1f | 361 | ctx->exception = POWERPC_EXCP_STOP; |
3fc6c082 FB |
362 | } |
363 | ||
466976d9 | 364 | #ifndef CONFIG_USER_ONLY |
f24e5695 | 365 | /* No need to update nip here, as execution flow will change */ |
636aa200 | 366 | static inline void gen_sync_exception(DisasContext *ctx) |
2be0071f | 367 | { |
e1833e1f | 368 | ctx->exception = POWERPC_EXCP_SYNC; |
2be0071f | 369 | } |
466976d9 | 370 | #endif |
2be0071f | 371 | |
79aceca5 | 372 | #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ |
a5858d7a AG |
373 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) |
374 | ||
375 | #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ | |
376 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) | |
79aceca5 | 377 | |
c7697e1f | 378 | #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ |
a5858d7a AG |
379 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) |
380 | ||
381 | #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ | |
382 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) | |
c7697e1f | 383 | |
323ad19b ND |
384 | #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ |
385 | GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) | |
386 | ||
14fd8ab2 ND |
387 | #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ |
388 | GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) | |
389 | ||
c227f099 | 390 | typedef struct opcode_t { |
323ad19b | 391 | unsigned char opc1, opc2, opc3, opc4; |
1235fc06 | 392 | #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ |
323ad19b | 393 | unsigned char pad[4]; |
18fba28c | 394 | #endif |
c227f099 | 395 | opc_handler_t handler; |
b55266b5 | 396 | const char *oname; |
c227f099 | 397 | } opcode_t; |
79aceca5 | 398 | |
9b2fadda BH |
399 | /* Helpers for priv. check */ |
400 | #define GEN_PRIV \ | |
401 | do { \ | |
402 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ | |
403 | } while (0) | |
404 | ||
405 | #if defined(CONFIG_USER_ONLY) | |
406 | #define CHK_HV GEN_PRIV | |
407 | #define CHK_SV GEN_PRIV | |
b7815375 | 408 | #define CHK_HVRM GEN_PRIV |
9b2fadda BH |
409 | #else |
410 | #define CHK_HV \ | |
411 | do { \ | |
412 | if (unlikely(ctx->pr || !ctx->hv)) { \ | |
413 | GEN_PRIV; \ | |
414 | } \ | |
415 | } while (0) | |
416 | #define CHK_SV \ | |
417 | do { \ | |
418 | if (unlikely(ctx->pr)) { \ | |
419 | GEN_PRIV; \ | |
420 | } \ | |
421 | } while (0) | |
b7815375 BH |
422 | #define CHK_HVRM \ |
423 | do { \ | |
424 | if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ | |
425 | GEN_PRIV; \ | |
426 | } \ | |
427 | } while (0) | |
9b2fadda BH |
428 | #endif |
429 | ||
430 | #define CHK_NONE | |
431 | ||
a750fc0b | 432 | /*****************************************************************************/ |
a750fc0b | 433 | /* PowerPC instructions table */ |
933dc6eb | 434 | |
76a66253 | 435 | #if defined(DO_PPC_STATISTICS) |
a5858d7a | 436 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 437 | { \ |
79aceca5 FB |
438 | .opc1 = op1, \ |
439 | .opc2 = op2, \ | |
440 | .opc3 = op3, \ | |
323ad19b | 441 | .opc4 = 0xff, \ |
79aceca5 | 442 | .handler = { \ |
70560da7 FC |
443 | .inval1 = invl, \ |
444 | .type = _typ, \ | |
445 | .type2 = _typ2, \ | |
446 | .handler = &gen_##name, \ | |
447 | .oname = stringify(name), \ | |
448 | }, \ | |
449 | .oname = stringify(name), \ | |
450 | } | |
451 | #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ | |
452 | { \ | |
453 | .opc1 = op1, \ | |
454 | .opc2 = op2, \ | |
455 | .opc3 = op3, \ | |
323ad19b | 456 | .opc4 = 0xff, \ |
70560da7 FC |
457 | .handler = { \ |
458 | .inval1 = invl1, \ | |
459 | .inval2 = invl2, \ | |
9a64fbe4 | 460 | .type = _typ, \ |
a5858d7a | 461 | .type2 = _typ2, \ |
79aceca5 | 462 | .handler = &gen_##name, \ |
76a66253 | 463 | .oname = stringify(name), \ |
79aceca5 | 464 | }, \ |
3fc6c082 | 465 | .oname = stringify(name), \ |
79aceca5 | 466 | } |
a5858d7a | 467 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 468 | { \ |
c7697e1f JM |
469 | .opc1 = op1, \ |
470 | .opc2 = op2, \ | |
471 | .opc3 = op3, \ | |
323ad19b | 472 | .opc4 = 0xff, \ |
c7697e1f | 473 | .handler = { \ |
70560da7 | 474 | .inval1 = invl, \ |
c7697e1f | 475 | .type = _typ, \ |
a5858d7a | 476 | .type2 = _typ2, \ |
c7697e1f JM |
477 | .handler = &gen_##name, \ |
478 | .oname = onam, \ | |
479 | }, \ | |
480 | .oname = onam, \ | |
481 | } | |
323ad19b ND |
482 | #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ |
483 | { \ | |
484 | .opc1 = op1, \ | |
485 | .opc2 = op2, \ | |
486 | .opc3 = op3, \ | |
487 | .opc4 = op4, \ | |
488 | .handler = { \ | |
489 | .inval1 = invl, \ | |
490 | .type = _typ, \ | |
491 | .type2 = _typ2, \ | |
492 | .handler = &gen_##name, \ | |
493 | .oname = stringify(name), \ | |
494 | }, \ | |
495 | .oname = stringify(name), \ | |
496 | } | |
14fd8ab2 ND |
497 | #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ |
498 | { \ | |
499 | .opc1 = op1, \ | |
500 | .opc2 = op2, \ | |
501 | .opc3 = op3, \ | |
502 | .opc4 = op4, \ | |
503 | .handler = { \ | |
504 | .inval1 = invl, \ | |
505 | .type = _typ, \ | |
506 | .type2 = _typ2, \ | |
507 | .handler = &gen_##name, \ | |
508 | .oname = onam, \ | |
509 | }, \ | |
510 | .oname = onam, \ | |
511 | } | |
76a66253 | 512 | #else |
a5858d7a | 513 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 514 | { \ |
c7697e1f JM |
515 | .opc1 = op1, \ |
516 | .opc2 = op2, \ | |
517 | .opc3 = op3, \ | |
323ad19b | 518 | .opc4 = 0xff, \ |
c7697e1f | 519 | .handler = { \ |
70560da7 FC |
520 | .inval1 = invl, \ |
521 | .type = _typ, \ | |
522 | .type2 = _typ2, \ | |
523 | .handler = &gen_##name, \ | |
524 | }, \ | |
525 | .oname = stringify(name), \ | |
526 | } | |
527 | #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ | |
528 | { \ | |
529 | .opc1 = op1, \ | |
530 | .opc2 = op2, \ | |
531 | .opc3 = op3, \ | |
323ad19b | 532 | .opc4 = 0xff, \ |
70560da7 FC |
533 | .handler = { \ |
534 | .inval1 = invl1, \ | |
535 | .inval2 = invl2, \ | |
c7697e1f | 536 | .type = _typ, \ |
a5858d7a | 537 | .type2 = _typ2, \ |
c7697e1f | 538 | .handler = &gen_##name, \ |
5c55ff99 BS |
539 | }, \ |
540 | .oname = stringify(name), \ | |
541 | } | |
a5858d7a | 542 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 BS |
543 | { \ |
544 | .opc1 = op1, \ | |
545 | .opc2 = op2, \ | |
546 | .opc3 = op3, \ | |
323ad19b | 547 | .opc4 = 0xff, \ |
5c55ff99 | 548 | .handler = { \ |
70560da7 | 549 | .inval1 = invl, \ |
5c55ff99 | 550 | .type = _typ, \ |
a5858d7a | 551 | .type2 = _typ2, \ |
5c55ff99 BS |
552 | .handler = &gen_##name, \ |
553 | }, \ | |
554 | .oname = onam, \ | |
555 | } | |
323ad19b ND |
556 | #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ |
557 | { \ | |
558 | .opc1 = op1, \ | |
559 | .opc2 = op2, \ | |
560 | .opc3 = op3, \ | |
561 | .opc4 = op4, \ | |
562 | .handler = { \ | |
563 | .inval1 = invl, \ | |
564 | .type = _typ, \ | |
565 | .type2 = _typ2, \ | |
566 | .handler = &gen_##name, \ | |
567 | }, \ | |
568 | .oname = stringify(name), \ | |
569 | } | |
14fd8ab2 ND |
570 | #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ |
571 | { \ | |
572 | .opc1 = op1, \ | |
573 | .opc2 = op2, \ | |
574 | .opc3 = op3, \ | |
575 | .opc4 = op4, \ | |
576 | .handler = { \ | |
577 | .inval1 = invl, \ | |
578 | .type = _typ, \ | |
579 | .type2 = _typ2, \ | |
580 | .handler = &gen_##name, \ | |
581 | }, \ | |
582 | .oname = onam, \ | |
583 | } | |
5c55ff99 | 584 | #endif |
2e610050 | 585 | |
54623277 | 586 | /* Invalid instruction */ |
99e300ef | 587 | static void gen_invalid(DisasContext *ctx) |
9a64fbe4 | 588 | { |
e06fcd75 | 589 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
9a64fbe4 FB |
590 | } |
591 | ||
c227f099 | 592 | static opc_handler_t invalid_handler = { |
70560da7 FC |
593 | .inval1 = 0xFFFFFFFF, |
594 | .inval2 = 0xFFFFFFFF, | |
9a64fbe4 | 595 | .type = PPC_NONE, |
a5858d7a | 596 | .type2 = PPC_NONE, |
79aceca5 FB |
597 | .handler = gen_invalid, |
598 | }; | |
599 | ||
e1571908 AJ |
600 | /*** Integer comparison ***/ |
601 | ||
636aa200 | 602 | static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) |
e1571908 | 603 | { |
2fdcb629 | 604 | TCGv t0 = tcg_temp_new(); |
b62b3686 PB |
605 | TCGv t1 = tcg_temp_new(); |
606 | TCGv_i32 t = tcg_temp_new_i32(); | |
e1571908 | 607 | |
b62b3686 PB |
608 | tcg_gen_movi_tl(t0, CRF_EQ); |
609 | tcg_gen_movi_tl(t1, CRF_LT); | |
efe843d8 DG |
610 | tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), |
611 | t0, arg0, arg1, t1, t0); | |
b62b3686 | 612 | tcg_gen_movi_tl(t1, CRF_GT); |
efe843d8 DG |
613 | tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), |
614 | t0, arg0, arg1, t1, t0); | |
2fdcb629 | 615 | |
b62b3686 PB |
616 | tcg_gen_trunc_tl_i32(t, t0); |
617 | tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); | |
618 | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); | |
2fdcb629 RH |
619 | |
620 | tcg_temp_free(t0); | |
b62b3686 PB |
621 | tcg_temp_free(t1); |
622 | tcg_temp_free_i32(t); | |
e1571908 AJ |
623 | } |
624 | ||
636aa200 | 625 | static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) |
e1571908 | 626 | { |
2fdcb629 | 627 | TCGv t0 = tcg_const_tl(arg1); |
ea363694 AJ |
628 | gen_op_cmp(arg0, t0, s, crf); |
629 | tcg_temp_free(t0); | |
e1571908 AJ |
630 | } |
631 | ||
636aa200 | 632 | static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) |
e1571908 | 633 | { |
ea363694 | 634 | TCGv t0, t1; |
2fdcb629 RH |
635 | t0 = tcg_temp_new(); |
636 | t1 = tcg_temp_new(); | |
e1571908 | 637 | if (s) { |
ea363694 AJ |
638 | tcg_gen_ext32s_tl(t0, arg0); |
639 | tcg_gen_ext32s_tl(t1, arg1); | |
e1571908 | 640 | } else { |
ea363694 AJ |
641 | tcg_gen_ext32u_tl(t0, arg0); |
642 | tcg_gen_ext32u_tl(t1, arg1); | |
e1571908 | 643 | } |
ea363694 AJ |
644 | gen_op_cmp(t0, t1, s, crf); |
645 | tcg_temp_free(t1); | |
646 | tcg_temp_free(t0); | |
e1571908 AJ |
647 | } |
648 | ||
636aa200 | 649 | static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) |
e1571908 | 650 | { |
2fdcb629 | 651 | TCGv t0 = tcg_const_tl(arg1); |
ea363694 AJ |
652 | gen_op_cmp32(arg0, t0, s, crf); |
653 | tcg_temp_free(t0); | |
e1571908 | 654 | } |
e1571908 | 655 | |
636aa200 | 656 | static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) |
e1571908 | 657 | { |
02765534 | 658 | if (NARROW_MODE(ctx)) { |
e1571908 | 659 | gen_op_cmpi32(reg, 0, 1, 0); |
02765534 | 660 | } else { |
e1571908 | 661 | gen_op_cmpi(reg, 0, 1, 0); |
02765534 | 662 | } |
e1571908 AJ |
663 | } |
664 | ||
665 | /* cmp */ | |
99e300ef | 666 | static void gen_cmp(DisasContext *ctx) |
e1571908 | 667 | { |
36f48d9c | 668 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
669 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
670 | 1, crfD(ctx->opcode)); | |
36f48d9c AG |
671 | } else { |
672 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
673 | 1, crfD(ctx->opcode)); | |
02765534 | 674 | } |
e1571908 AJ |
675 | } |
676 | ||
677 | /* cmpi */ | |
99e300ef | 678 | static void gen_cmpi(DisasContext *ctx) |
e1571908 | 679 | { |
36f48d9c | 680 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
681 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), |
682 | 1, crfD(ctx->opcode)); | |
36f48d9c AG |
683 | } else { |
684 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), | |
685 | 1, crfD(ctx->opcode)); | |
02765534 | 686 | } |
e1571908 AJ |
687 | } |
688 | ||
689 | /* cmpl */ | |
99e300ef | 690 | static void gen_cmpl(DisasContext *ctx) |
e1571908 | 691 | { |
36f48d9c | 692 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
693 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
694 | 0, crfD(ctx->opcode)); | |
36f48d9c AG |
695 | } else { |
696 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
697 | 0, crfD(ctx->opcode)); | |
02765534 | 698 | } |
e1571908 AJ |
699 | } |
700 | ||
701 | /* cmpli */ | |
99e300ef | 702 | static void gen_cmpli(DisasContext *ctx) |
e1571908 | 703 | { |
36f48d9c | 704 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
705 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), |
706 | 0, crfD(ctx->opcode)); | |
36f48d9c AG |
707 | } else { |
708 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), | |
709 | 0, crfD(ctx->opcode)); | |
02765534 | 710 | } |
e1571908 AJ |
711 | } |
712 | ||
f2442ef9 ND |
713 | /* cmprb - range comparison: isupper, isaplha, islower*/ |
714 | static void gen_cmprb(DisasContext *ctx) | |
715 | { | |
716 | TCGv_i32 src1 = tcg_temp_new_i32(); | |
717 | TCGv_i32 src2 = tcg_temp_new_i32(); | |
718 | TCGv_i32 src2lo = tcg_temp_new_i32(); | |
719 | TCGv_i32 src2hi = tcg_temp_new_i32(); | |
720 | TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; | |
721 | ||
722 | tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); | |
723 | tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); | |
724 | ||
725 | tcg_gen_andi_i32(src1, src1, 0xFF); | |
726 | tcg_gen_ext8u_i32(src2lo, src2); | |
727 | tcg_gen_shri_i32(src2, src2, 8); | |
728 | tcg_gen_ext8u_i32(src2hi, src2); | |
729 | ||
730 | tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); | |
731 | tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); | |
732 | tcg_gen_and_i32(crf, src2lo, src2hi); | |
733 | ||
734 | if (ctx->opcode & 0x00200000) { | |
735 | tcg_gen_shri_i32(src2, src2, 8); | |
736 | tcg_gen_ext8u_i32(src2lo, src2); | |
737 | tcg_gen_shri_i32(src2, src2, 8); | |
738 | tcg_gen_ext8u_i32(src2hi, src2); | |
739 | tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); | |
740 | tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); | |
741 | tcg_gen_and_i32(src2lo, src2lo, src2hi); | |
742 | tcg_gen_or_i32(crf, crf, src2lo); | |
743 | } | |
efa73196 | 744 | tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); |
f2442ef9 ND |
745 | tcg_temp_free_i32(src1); |
746 | tcg_temp_free_i32(src2); | |
747 | tcg_temp_free_i32(src2lo); | |
748 | tcg_temp_free_i32(src2hi); | |
749 | } | |
750 | ||
082ce330 ND |
751 | #if defined(TARGET_PPC64) |
752 | /* cmpeqb */ | |
753 | static void gen_cmpeqb(DisasContext *ctx) | |
754 | { | |
755 | gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
756 | cpu_gpr[rB(ctx->opcode)]); | |
757 | } | |
758 | #endif | |
759 | ||
e1571908 | 760 | /* isel (PowerPC 2.03 specification) */ |
99e300ef | 761 | static void gen_isel(DisasContext *ctx) |
e1571908 | 762 | { |
e1571908 | 763 | uint32_t bi = rC(ctx->opcode); |
24f9cd95 RH |
764 | uint32_t mask = 0x08 >> (bi & 0x03); |
765 | TCGv t0 = tcg_temp_new(); | |
766 | TCGv zr; | |
e1571908 | 767 | |
24f9cd95 RH |
768 | tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); |
769 | tcg_gen_andi_tl(t0, t0, mask); | |
770 | ||
771 | zr = tcg_const_tl(0); | |
772 | tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, | |
773 | rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, | |
774 | cpu_gpr[rB(ctx->opcode)]); | |
775 | tcg_temp_free(zr); | |
776 | tcg_temp_free(t0); | |
e1571908 AJ |
777 | } |
778 | ||
fcfda20f AJ |
779 | /* cmpb: PowerPC 2.05 specification */ |
780 | static void gen_cmpb(DisasContext *ctx) | |
781 | { | |
782 | gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], | |
783 | cpu_gpr[rB(ctx->opcode)]); | |
784 | } | |
785 | ||
79aceca5 | 786 | /*** Integer arithmetic ***/ |
79aceca5 | 787 | |
636aa200 BS |
788 | static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, |
789 | TCGv arg1, TCGv arg2, int sub) | |
74637406 | 790 | { |
ffe30937 | 791 | TCGv t0 = tcg_temp_new(); |
79aceca5 | 792 | |
8e7a6db9 | 793 | tcg_gen_xor_tl(cpu_ov, arg0, arg2); |
74637406 | 794 | tcg_gen_xor_tl(t0, arg1, arg2); |
ffe30937 RH |
795 | if (sub) { |
796 | tcg_gen_and_tl(cpu_ov, cpu_ov, t0); | |
797 | } else { | |
798 | tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); | |
799 | } | |
800 | tcg_temp_free(t0); | |
02765534 | 801 | if (NARROW_MODE(ctx)) { |
dc0ad844 ND |
802 | tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); |
803 | if (is_isa300(ctx)) { | |
804 | tcg_gen_mov_tl(cpu_ov32, cpu_ov); | |
805 | } | |
806 | } else { | |
807 | if (is_isa300(ctx)) { | |
808 | tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); | |
809 | } | |
38a61d34 | 810 | tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); |
ffe30937 | 811 | } |
ffe30937 | 812 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); |
79aceca5 FB |
813 | } |
814 | ||
6b10d008 ND |
815 | static inline void gen_op_arith_compute_ca32(DisasContext *ctx, |
816 | TCGv res, TCGv arg0, TCGv arg1, | |
4c5920af | 817 | TCGv ca32, int sub) |
6b10d008 ND |
818 | { |
819 | TCGv t0; | |
820 | ||
821 | if (!is_isa300(ctx)) { | |
822 | return; | |
823 | } | |
824 | ||
825 | t0 = tcg_temp_new(); | |
33903d0a ND |
826 | if (sub) { |
827 | tcg_gen_eqv_tl(t0, arg0, arg1); | |
828 | } else { | |
829 | tcg_gen_xor_tl(t0, arg0, arg1); | |
830 | } | |
6b10d008 | 831 | tcg_gen_xor_tl(t0, t0, res); |
4c5920af | 832 | tcg_gen_extract_tl(ca32, t0, 32, 1); |
6b10d008 ND |
833 | tcg_temp_free(t0); |
834 | } | |
835 | ||
74637406 | 836 | /* Common add function */ |
636aa200 | 837 | static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
4c5920af SJS |
838 | TCGv arg2, TCGv ca, TCGv ca32, |
839 | bool add_ca, bool compute_ca, | |
b5a73f8d | 840 | bool compute_ov, bool compute_rc0) |
74637406 | 841 | { |
b5a73f8d | 842 | TCGv t0 = ret; |
d9bce9d9 | 843 | |
752d634e | 844 | if (compute_ca || compute_ov) { |
146de60d | 845 | t0 = tcg_temp_new(); |
74637406 | 846 | } |
79aceca5 | 847 | |
da91a00f | 848 | if (compute_ca) { |
79482e5a | 849 | if (NARROW_MODE(ctx)) { |
efe843d8 DG |
850 | /* |
851 | * Caution: a non-obvious corner case of the spec is that | |
852 | * we must produce the *entire* 64-bit addition, but | |
853 | * produce the carry into bit 32. | |
854 | */ | |
79482e5a | 855 | TCGv t1 = tcg_temp_new(); |
752d634e RH |
856 | tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ |
857 | tcg_gen_add_tl(t0, arg1, arg2); | |
79482e5a | 858 | if (add_ca) { |
4c5920af | 859 | tcg_gen_add_tl(t0, t0, ca); |
79482e5a | 860 | } |
4c5920af | 861 | tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ |
752d634e | 862 | tcg_temp_free(t1); |
4c5920af | 863 | tcg_gen_extract_tl(ca, ca, 32, 1); |
6b10d008 | 864 | if (is_isa300(ctx)) { |
4c5920af | 865 | tcg_gen_mov_tl(ca32, ca); |
6b10d008 | 866 | } |
b5a73f8d | 867 | } else { |
79482e5a RH |
868 | TCGv zero = tcg_const_tl(0); |
869 | if (add_ca) { | |
4c5920af SJS |
870 | tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); |
871 | tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); | |
79482e5a | 872 | } else { |
4c5920af | 873 | tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); |
79482e5a | 874 | } |
4c5920af | 875 | gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); |
79482e5a | 876 | tcg_temp_free(zero); |
b5a73f8d | 877 | } |
b5a73f8d RH |
878 | } else { |
879 | tcg_gen_add_tl(t0, arg1, arg2); | |
880 | if (add_ca) { | |
4c5920af | 881 | tcg_gen_add_tl(t0, t0, ca); |
b5a73f8d | 882 | } |
da91a00f | 883 | } |
79aceca5 | 884 | |
74637406 AJ |
885 | if (compute_ov) { |
886 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); | |
887 | } | |
b5a73f8d | 888 | if (unlikely(compute_rc0)) { |
74637406 | 889 | gen_set_Rc0(ctx, t0); |
b5a73f8d | 890 | } |
74637406 | 891 | |
11f4e8f8 | 892 | if (t0 != ret) { |
74637406 AJ |
893 | tcg_gen_mov_tl(ret, t0); |
894 | tcg_temp_free(t0); | |
895 | } | |
39dd32ee | 896 | } |
74637406 | 897 | /* Add functions with two operands */ |
4c5920af | 898 | #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ |
b5a73f8d | 899 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
900 | { \ |
901 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
902 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
4c5920af | 903 | ca, glue(ca, 32), \ |
b5a73f8d | 904 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
905 | } |
906 | /* Add functions with one operand and one immediate */ | |
4c5920af | 907 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ |
74637406 | 908 | add_ca, compute_ca, compute_ov) \ |
b5a73f8d | 909 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 910 | { \ |
b5a73f8d | 911 | TCGv t0 = tcg_const_tl(const_val); \ |
74637406 AJ |
912 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ |
913 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
4c5920af | 914 | ca, glue(ca, 32), \ |
b5a73f8d | 915 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
916 | tcg_temp_free(t0); \ |
917 | } | |
918 | ||
919 | /* add add. addo addo. */ | |
4c5920af SJS |
920 | GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) |
921 | GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) | |
74637406 | 922 | /* addc addc. addco addco. */ |
4c5920af SJS |
923 | GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) |
924 | GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) | |
74637406 | 925 | /* adde adde. addeo addeo. */ |
4c5920af SJS |
926 | GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) |
927 | GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) | |
74637406 | 928 | /* addme addme. addmeo addmeo. */ |
4c5920af SJS |
929 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) |
930 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) | |
931 | /* addex */ | |
932 | GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); | |
74637406 | 933 | /* addze addze. addzeo addzeo.*/ |
4c5920af SJS |
934 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) |
935 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) | |
74637406 | 936 | /* addi */ |
99e300ef | 937 | static void gen_addi(DisasContext *ctx) |
d9bce9d9 | 938 | { |
74637406 AJ |
939 | target_long simm = SIMM(ctx->opcode); |
940 | ||
941 | if (rA(ctx->opcode) == 0) { | |
942 | /* li case */ | |
943 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); | |
944 | } else { | |
b5a73f8d RH |
945 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], |
946 | cpu_gpr[rA(ctx->opcode)], simm); | |
74637406 | 947 | } |
d9bce9d9 | 948 | } |
74637406 | 949 | /* addic addic.*/ |
b5a73f8d | 950 | static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) |
d9bce9d9 | 951 | { |
b5a73f8d RH |
952 | TCGv c = tcg_const_tl(SIMM(ctx->opcode)); |
953 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
4c5920af | 954 | c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); |
b5a73f8d | 955 | tcg_temp_free(c); |
d9bce9d9 | 956 | } |
99e300ef BS |
957 | |
958 | static void gen_addic(DisasContext *ctx) | |
d9bce9d9 | 959 | { |
b5a73f8d | 960 | gen_op_addic(ctx, 0); |
d9bce9d9 | 961 | } |
e8eaa2c0 BS |
962 | |
963 | static void gen_addic_(DisasContext *ctx) | |
d9bce9d9 | 964 | { |
b5a73f8d | 965 | gen_op_addic(ctx, 1); |
d9bce9d9 | 966 | } |
99e300ef | 967 | |
54623277 | 968 | /* addis */ |
99e300ef | 969 | static void gen_addis(DisasContext *ctx) |
d9bce9d9 | 970 | { |
74637406 AJ |
971 | target_long simm = SIMM(ctx->opcode); |
972 | ||
973 | if (rA(ctx->opcode) == 0) { | |
974 | /* lis case */ | |
975 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); | |
976 | } else { | |
b5a73f8d RH |
977 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], |
978 | cpu_gpr[rA(ctx->opcode)], simm << 16); | |
74637406 | 979 | } |
d9bce9d9 | 980 | } |
74637406 | 981 | |
c5b2b9ce ND |
982 | /* addpcis */ |
983 | static void gen_addpcis(DisasContext *ctx) | |
984 | { | |
985 | target_long d = DX(ctx->opcode); | |
986 | ||
b6bac4bc | 987 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16)); |
c5b2b9ce ND |
988 | } |
989 | ||
636aa200 BS |
990 | static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, |
991 | TCGv arg2, int sign, int compute_ov) | |
d9bce9d9 | 992 | { |
b07c32dc ND |
993 | TCGv_i32 t0 = tcg_temp_new_i32(); |
994 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
995 | TCGv_i32 t2 = tcg_temp_new_i32(); | |
996 | TCGv_i32 t3 = tcg_temp_new_i32(); | |
74637406 | 997 | |
2ef1b120 AJ |
998 | tcg_gen_trunc_tl_i32(t0, arg1); |
999 | tcg_gen_trunc_tl_i32(t1, arg2); | |
74637406 | 1000 | if (sign) { |
b07c32dc ND |
1001 | tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); |
1002 | tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); | |
1003 | tcg_gen_and_i32(t2, t2, t3); | |
1004 | tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); | |
1005 | tcg_gen_or_i32(t2, t2, t3); | |
1006 | tcg_gen_movi_i32(t3, 0); | |
1007 | tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1008 | tcg_gen_div_i32(t3, t0, t1); | |
1009 | tcg_gen_extu_i32_tl(ret, t3); | |
74637406 | 1010 | } else { |
b07c32dc ND |
1011 | tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); |
1012 | tcg_gen_movi_i32(t3, 0); | |
1013 | tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1014 | tcg_gen_divu_i32(t3, t0, t1); | |
1015 | tcg_gen_extu_i32_tl(ret, t3); | |
74637406 AJ |
1016 | } |
1017 | if (compute_ov) { | |
b07c32dc | 1018 | tcg_gen_extu_i32_tl(cpu_ov, t2); |
c44027ff ND |
1019 | if (is_isa300(ctx)) { |
1020 | tcg_gen_extu_i32_tl(cpu_ov32, t2); | |
1021 | } | |
b07c32dc | 1022 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); |
74637406 | 1023 | } |
a7812ae4 PB |
1024 | tcg_temp_free_i32(t0); |
1025 | tcg_temp_free_i32(t1); | |
b07c32dc ND |
1026 | tcg_temp_free_i32(t2); |
1027 | tcg_temp_free_i32(t3); | |
1028 | ||
efe843d8 | 1029 | if (unlikely(Rc(ctx->opcode) != 0)) { |
74637406 | 1030 | gen_set_Rc0(ctx, ret); |
efe843d8 | 1031 | } |
d9bce9d9 | 1032 | } |
74637406 AJ |
1033 | /* Div functions */ |
1034 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ | |
efe843d8 | 1035 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
1036 | { \ |
1037 | gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1038 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1039 | sign, compute_ov); \ | |
1040 | } | |
1041 | /* divwu divwu. divwuo divwuo. */ | |
1042 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); | |
1043 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); | |
1044 | /* divw divw. divwo divwo. */ | |
1045 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); | |
1046 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); | |
98d1eb27 TM |
1047 | |
1048 | /* div[wd]eu[o][.] */ | |
1049 | #define GEN_DIVE(name, hlpr, compute_ov) \ | |
1050 | static void gen_##name(DisasContext *ctx) \ | |
1051 | { \ | |
1052 | TCGv_i32 t0 = tcg_const_i32(compute_ov); \ | |
1053 | gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ | |
1054 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ | |
1055 | tcg_temp_free_i32(t0); \ | |
1056 | if (unlikely(Rc(ctx->opcode) != 0)) { \ | |
1057 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ | |
1058 | } \ | |
1059 | } | |
1060 | ||
6a4fda33 TM |
1061 | GEN_DIVE(divweu, divweu, 0); |
1062 | GEN_DIVE(divweuo, divweu, 1); | |
a98eb9e9 TM |
1063 | GEN_DIVE(divwe, divwe, 0); |
1064 | GEN_DIVE(divweo, divwe, 1); | |
6a4fda33 | 1065 | |
d9bce9d9 | 1066 | #if defined(TARGET_PPC64) |
636aa200 BS |
1067 | static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, |
1068 | TCGv arg2, int sign, int compute_ov) | |
d9bce9d9 | 1069 | { |
4110b586 ND |
1070 | TCGv_i64 t0 = tcg_temp_new_i64(); |
1071 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1072 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1073 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
74637406 | 1074 | |
4110b586 ND |
1075 | tcg_gen_mov_i64(t0, arg1); |
1076 | tcg_gen_mov_i64(t1, arg2); | |
74637406 | 1077 | if (sign) { |
4110b586 ND |
1078 | tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); |
1079 | tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); | |
1080 | tcg_gen_and_i64(t2, t2, t3); | |
1081 | tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); | |
1082 | tcg_gen_or_i64(t2, t2, t3); | |
1083 | tcg_gen_movi_i64(t3, 0); | |
1084 | tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1085 | tcg_gen_div_i64(ret, t0, t1); | |
74637406 | 1086 | } else { |
4110b586 ND |
1087 | tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); |
1088 | tcg_gen_movi_i64(t3, 0); | |
1089 | tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1090 | tcg_gen_divu_i64(ret, t0, t1); | |
74637406 AJ |
1091 | } |
1092 | if (compute_ov) { | |
4110b586 | 1093 | tcg_gen_mov_tl(cpu_ov, t2); |
c44027ff ND |
1094 | if (is_isa300(ctx)) { |
1095 | tcg_gen_mov_tl(cpu_ov32, t2); | |
1096 | } | |
4110b586 | 1097 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); |
74637406 | 1098 | } |
4110b586 ND |
1099 | tcg_temp_free_i64(t0); |
1100 | tcg_temp_free_i64(t1); | |
1101 | tcg_temp_free_i64(t2); | |
1102 | tcg_temp_free_i64(t3); | |
1103 | ||
efe843d8 | 1104 | if (unlikely(Rc(ctx->opcode) != 0)) { |
74637406 | 1105 | gen_set_Rc0(ctx, ret); |
efe843d8 | 1106 | } |
d9bce9d9 | 1107 | } |
4110b586 | 1108 | |
74637406 | 1109 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ |
efe843d8 | 1110 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 1111 | { \ |
2ef1b120 AJ |
1112 | gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1113 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1114 | sign, compute_ov); \ | |
74637406 | 1115 | } |
c44027ff | 1116 | /* divdu divdu. divduo divduo. */ |
74637406 AJ |
1117 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); |
1118 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); | |
c44027ff | 1119 | /* divd divd. divdo divdo. */ |
74637406 AJ |
1120 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); |
1121 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); | |
98d1eb27 TM |
1122 | |
1123 | GEN_DIVE(divdeu, divdeu, 0); | |
1124 | GEN_DIVE(divdeuo, divdeu, 1); | |
e44259b6 TM |
1125 | GEN_DIVE(divde, divde, 0); |
1126 | GEN_DIVE(divdeo, divde, 1); | |
d9bce9d9 | 1127 | #endif |
74637406 | 1128 | |
af2c6620 ND |
1129 | static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, |
1130 | TCGv arg2, int sign) | |
1131 | { | |
1132 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
1133 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
1134 | ||
1135 | tcg_gen_trunc_tl_i32(t0, arg1); | |
1136 | tcg_gen_trunc_tl_i32(t1, arg2); | |
1137 | if (sign) { | |
1138 | TCGv_i32 t2 = tcg_temp_new_i32(); | |
1139 | TCGv_i32 t3 = tcg_temp_new_i32(); | |
1140 | tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); | |
1141 | tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); | |
1142 | tcg_gen_and_i32(t2, t2, t3); | |
1143 | tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); | |
1144 | tcg_gen_or_i32(t2, t2, t3); | |
1145 | tcg_gen_movi_i32(t3, 0); | |
1146 | tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1147 | tcg_gen_rem_i32(t3, t0, t1); | |
1148 | tcg_gen_ext_i32_tl(ret, t3); | |
1149 | tcg_temp_free_i32(t2); | |
1150 | tcg_temp_free_i32(t3); | |
1151 | } else { | |
1152 | TCGv_i32 t2 = tcg_const_i32(1); | |
1153 | TCGv_i32 t3 = tcg_const_i32(0); | |
1154 | tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); | |
1155 | tcg_gen_remu_i32(t3, t0, t1); | |
1156 | tcg_gen_extu_i32_tl(ret, t3); | |
1157 | tcg_temp_free_i32(t2); | |
1158 | tcg_temp_free_i32(t3); | |
1159 | } | |
1160 | tcg_temp_free_i32(t0); | |
1161 | tcg_temp_free_i32(t1); | |
1162 | } | |
1163 | ||
1164 | #define GEN_INT_ARITH_MODW(name, opc3, sign) \ | |
1165 | static void glue(gen_, name)(DisasContext *ctx) \ | |
1166 | { \ | |
1167 | gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1168 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1169 | sign); \ | |
1170 | } | |
1171 | ||
1172 | GEN_INT_ARITH_MODW(moduw, 0x08, 0); | |
1173 | GEN_INT_ARITH_MODW(modsw, 0x18, 1); | |
1174 | ||
063cf14f ND |
1175 | #if defined(TARGET_PPC64) |
1176 | static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, | |
1177 | TCGv arg2, int sign) | |
1178 | { | |
1179 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
1180 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1181 | ||
1182 | tcg_gen_mov_i64(t0, arg1); | |
1183 | tcg_gen_mov_i64(t1, arg2); | |
1184 | if (sign) { | |
1185 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1186 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
1187 | tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); | |
1188 | tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); | |
1189 | tcg_gen_and_i64(t2, t2, t3); | |
1190 | tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); | |
1191 | tcg_gen_or_i64(t2, t2, t3); | |
1192 | tcg_gen_movi_i64(t3, 0); | |
1193 | tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1194 | tcg_gen_rem_i64(ret, t0, t1); | |
1195 | tcg_temp_free_i64(t2); | |
1196 | tcg_temp_free_i64(t3); | |
1197 | } else { | |
1198 | TCGv_i64 t2 = tcg_const_i64(1); | |
1199 | TCGv_i64 t3 = tcg_const_i64(0); | |
1200 | tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); | |
1201 | tcg_gen_remu_i64(ret, t0, t1); | |
1202 | tcg_temp_free_i64(t2); | |
1203 | tcg_temp_free_i64(t3); | |
1204 | } | |
1205 | tcg_temp_free_i64(t0); | |
1206 | tcg_temp_free_i64(t1); | |
1207 | } | |
1208 | ||
1209 | #define GEN_INT_ARITH_MODD(name, opc3, sign) \ | |
1210 | static void glue(gen_, name)(DisasContext *ctx) \ | |
1211 | { \ | |
1212 | gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1213 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1214 | sign); \ | |
1215 | } | |
1216 | ||
1217 | GEN_INT_ARITH_MODD(modud, 0x08, 0); | |
1218 | GEN_INT_ARITH_MODD(modsd, 0x18, 1); | |
1219 | #endif | |
1220 | ||
74637406 | 1221 | /* mulhw mulhw. */ |
99e300ef | 1222 | static void gen_mulhw(DisasContext *ctx) |
d9bce9d9 | 1223 | { |
23ad1d5d RH |
1224 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1225 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1226 | |
23ad1d5d RH |
1227 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1228 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1229 | tcg_gen_muls2_i32(t0, t1, t0, t1); | |
1230 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
1231 | tcg_temp_free_i32(t0); | |
1232 | tcg_temp_free_i32(t1); | |
efe843d8 | 1233 | if (unlikely(Rc(ctx->opcode) != 0)) { |
74637406 | 1234 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
efe843d8 | 1235 | } |
d9bce9d9 | 1236 | } |
99e300ef | 1237 | |
54623277 | 1238 | /* mulhwu mulhwu. */ |
99e300ef | 1239 | static void gen_mulhwu(DisasContext *ctx) |
d9bce9d9 | 1240 | { |
23ad1d5d RH |
1241 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1242 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1243 | |
23ad1d5d RH |
1244 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1245 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1246 | tcg_gen_mulu2_i32(t0, t1, t0, t1); | |
1247 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
1248 | tcg_temp_free_i32(t0); | |
1249 | tcg_temp_free_i32(t1); | |
efe843d8 | 1250 | if (unlikely(Rc(ctx->opcode) != 0)) { |
74637406 | 1251 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
efe843d8 | 1252 | } |
d9bce9d9 | 1253 | } |
99e300ef | 1254 | |
54623277 | 1255 | /* mullw mullw. */ |
99e300ef | 1256 | static void gen_mullw(DisasContext *ctx) |
d9bce9d9 | 1257 | { |
1fa74845 TM |
1258 | #if defined(TARGET_PPC64) |
1259 | TCGv_i64 t0, t1; | |
1260 | t0 = tcg_temp_new_i64(); | |
1261 | t1 = tcg_temp_new_i64(); | |
1262 | tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); | |
1263 | tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); | |
1264 | tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
1265 | tcg_temp_free(t0); | |
1266 | tcg_temp_free(t1); | |
1267 | #else | |
03039e5e TM |
1268 | tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1269 | cpu_gpr[rB(ctx->opcode)]); | |
1fa74845 | 1270 | #endif |
efe843d8 | 1271 | if (unlikely(Rc(ctx->opcode) != 0)) { |
74637406 | 1272 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
efe843d8 | 1273 | } |
d9bce9d9 | 1274 | } |
99e300ef | 1275 | |
54623277 | 1276 | /* mullwo mullwo. */ |
99e300ef | 1277 | static void gen_mullwo(DisasContext *ctx) |
d9bce9d9 | 1278 | { |
e4a2c846 RH |
1279 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1280 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1281 | |
e4a2c846 RH |
1282 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1283 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1284 | tcg_gen_muls2_i32(t0, t1, t0, t1); | |
f11ebbf8 | 1285 | #if defined(TARGET_PPC64) |
26977876 TM |
1286 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); |
1287 | #else | |
1288 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); | |
f11ebbf8 | 1289 | #endif |
e4a2c846 RH |
1290 | |
1291 | tcg_gen_sari_i32(t0, t0, 31); | |
1292 | tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); | |
1293 | tcg_gen_extu_i32_tl(cpu_ov, t0); | |
61aa9a69 ND |
1294 | if (is_isa300(ctx)) { |
1295 | tcg_gen_mov_tl(cpu_ov32, cpu_ov); | |
1296 | } | |
e4a2c846 RH |
1297 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); |
1298 | ||
1299 | tcg_temp_free_i32(t0); | |
1300 | tcg_temp_free_i32(t1); | |
efe843d8 | 1301 | if (unlikely(Rc(ctx->opcode) != 0)) { |
74637406 | 1302 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
efe843d8 | 1303 | } |
d9bce9d9 | 1304 | } |
99e300ef | 1305 | |
54623277 | 1306 | /* mulli */ |
99e300ef | 1307 | static void gen_mulli(DisasContext *ctx) |
d9bce9d9 | 1308 | { |
74637406 AJ |
1309 | tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1310 | SIMM(ctx->opcode)); | |
d9bce9d9 | 1311 | } |
23ad1d5d | 1312 | |
d9bce9d9 | 1313 | #if defined(TARGET_PPC64) |
74637406 | 1314 | /* mulhd mulhd. */ |
23ad1d5d RH |
1315 | static void gen_mulhd(DisasContext *ctx) |
1316 | { | |
1317 | TCGv lo = tcg_temp_new(); | |
1318 | tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], | |
1319 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1320 | tcg_temp_free(lo); | |
1321 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1322 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1323 | } | |
1324 | } | |
1325 | ||
74637406 | 1326 | /* mulhdu mulhdu. */ |
23ad1d5d RH |
1327 | static void gen_mulhdu(DisasContext *ctx) |
1328 | { | |
1329 | TCGv lo = tcg_temp_new(); | |
1330 | tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], | |
1331 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1332 | tcg_temp_free(lo); | |
1333 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1334 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1335 | } | |
1336 | } | |
99e300ef | 1337 | |
54623277 | 1338 | /* mulld mulld. */ |
99e300ef | 1339 | static void gen_mulld(DisasContext *ctx) |
d9bce9d9 | 1340 | { |
74637406 AJ |
1341 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1342 | cpu_gpr[rB(ctx->opcode)]); | |
efe843d8 | 1343 | if (unlikely(Rc(ctx->opcode) != 0)) { |
74637406 | 1344 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
efe843d8 | 1345 | } |
d9bce9d9 | 1346 | } |
d15f74fb | 1347 | |
74637406 | 1348 | /* mulldo mulldo. */ |
d15f74fb BS |
1349 | static void gen_mulldo(DisasContext *ctx) |
1350 | { | |
22ffad31 TM |
1351 | TCGv_i64 t0 = tcg_temp_new_i64(); |
1352 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1353 | ||
1354 | tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], | |
1355 | cpu_gpr[rB(ctx->opcode)]); | |
1356 | tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); | |
1357 | ||
1358 | tcg_gen_sari_i64(t0, t0, 63); | |
1359 | tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); | |
61aa9a69 ND |
1360 | if (is_isa300(ctx)) { |
1361 | tcg_gen_mov_tl(cpu_ov32, cpu_ov); | |
1362 | } | |
22ffad31 TM |
1363 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); |
1364 | ||
1365 | tcg_temp_free_i64(t0); | |
1366 | tcg_temp_free_i64(t1); | |
1367 | ||
d15f74fb BS |
1368 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1369 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1370 | } | |
1371 | } | |
d9bce9d9 | 1372 | #endif |
74637406 | 1373 | |
74637406 | 1374 | /* Common subf function */ |
636aa200 | 1375 | static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, |
b5a73f8d RH |
1376 | TCGv arg2, bool add_ca, bool compute_ca, |
1377 | bool compute_ov, bool compute_rc0) | |
79aceca5 | 1378 | { |
b5a73f8d | 1379 | TCGv t0 = ret; |
79aceca5 | 1380 | |
752d634e | 1381 | if (compute_ca || compute_ov) { |
b5a73f8d | 1382 | t0 = tcg_temp_new(); |
da91a00f | 1383 | } |
74637406 | 1384 | |
79482e5a RH |
1385 | if (compute_ca) { |
1386 | /* dest = ~arg1 + arg2 [+ ca]. */ | |
1387 | if (NARROW_MODE(ctx)) { | |
efe843d8 DG |
1388 | /* |
1389 | * Caution: a non-obvious corner case of the spec is that | |
1390 | * we must produce the *entire* 64-bit addition, but | |
1391 | * produce the carry into bit 32. | |
1392 | */ | |
79482e5a | 1393 | TCGv inv1 = tcg_temp_new(); |
752d634e | 1394 | TCGv t1 = tcg_temp_new(); |
79482e5a | 1395 | tcg_gen_not_tl(inv1, arg1); |
79482e5a | 1396 | if (add_ca) { |
752d634e | 1397 | tcg_gen_add_tl(t0, arg2, cpu_ca); |
79482e5a | 1398 | } else { |
752d634e | 1399 | tcg_gen_addi_tl(t0, arg2, 1); |
79482e5a | 1400 | } |
752d634e | 1401 | tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ |
79482e5a | 1402 | tcg_gen_add_tl(t0, t0, inv1); |
c80d1df5 | 1403 | tcg_temp_free(inv1); |
752d634e RH |
1404 | tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ |
1405 | tcg_temp_free(t1); | |
e2622073 | 1406 | tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); |
33903d0a ND |
1407 | if (is_isa300(ctx)) { |
1408 | tcg_gen_mov_tl(cpu_ca32, cpu_ca); | |
1409 | } | |
79482e5a | 1410 | } else if (add_ca) { |
08f4a0f7 RH |
1411 | TCGv zero, inv1 = tcg_temp_new(); |
1412 | tcg_gen_not_tl(inv1, arg1); | |
b5a73f8d RH |
1413 | zero = tcg_const_tl(0); |
1414 | tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); | |
08f4a0f7 | 1415 | tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); |
4c5920af | 1416 | gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); |
b5a73f8d | 1417 | tcg_temp_free(zero); |
08f4a0f7 | 1418 | tcg_temp_free(inv1); |
b5a73f8d | 1419 | } else { |
79482e5a | 1420 | tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); |
b5a73f8d | 1421 | tcg_gen_sub_tl(t0, arg2, arg1); |
4c5920af | 1422 | gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); |
b5a73f8d | 1423 | } |
79482e5a | 1424 | } else if (add_ca) { |
efe843d8 DG |
1425 | /* |
1426 | * Since we're ignoring carry-out, we can simplify the | |
1427 | * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. | |
1428 | */ | |
79482e5a RH |
1429 | tcg_gen_sub_tl(t0, arg2, arg1); |
1430 | tcg_gen_add_tl(t0, t0, cpu_ca); | |
1431 | tcg_gen_subi_tl(t0, t0, 1); | |
79aceca5 | 1432 | } else { |
b5a73f8d | 1433 | tcg_gen_sub_tl(t0, arg2, arg1); |
74637406 | 1434 | } |
b5a73f8d | 1435 | |
74637406 AJ |
1436 | if (compute_ov) { |
1437 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); | |
1438 | } | |
b5a73f8d | 1439 | if (unlikely(compute_rc0)) { |
74637406 | 1440 | gen_set_Rc0(ctx, t0); |
b5a73f8d | 1441 | } |
74637406 | 1442 | |
11f4e8f8 | 1443 | if (t0 != ret) { |
74637406 AJ |
1444 | tcg_gen_mov_tl(ret, t0); |
1445 | tcg_temp_free(t0); | |
79aceca5 | 1446 | } |
79aceca5 | 1447 | } |
74637406 AJ |
1448 | /* Sub functions with Two operands functions */ |
1449 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 1450 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
1451 | { \ |
1452 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1453 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
b5a73f8d | 1454 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
1455 | } |
1456 | /* Sub functions with one operand and one immediate */ | |
1457 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ | |
1458 | add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 1459 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 1460 | { \ |
b5a73f8d | 1461 | TCGv t0 = tcg_const_tl(const_val); \ |
74637406 AJ |
1462 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1463 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
b5a73f8d | 1464 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
1465 | tcg_temp_free(t0); \ |
1466 | } | |
1467 | /* subf subf. subfo subfo. */ | |
1468 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) | |
1469 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) | |
1470 | /* subfc subfc. subfco subfco. */ | |
1471 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) | |
1472 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) | |
1473 | /* subfe subfe. subfeo subfo. */ | |
1474 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) | |
1475 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) | |
1476 | /* subfme subfme. subfmeo subfmeo. */ | |
1477 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) | |
1478 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) | |
1479 | /* subfze subfze. subfzeo subfzeo.*/ | |
1480 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) | |
1481 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) | |
99e300ef | 1482 | |
54623277 | 1483 | /* subfic */ |
99e300ef | 1484 | static void gen_subfic(DisasContext *ctx) |
79aceca5 | 1485 | { |
b5a73f8d RH |
1486 | TCGv c = tcg_const_tl(SIMM(ctx->opcode)); |
1487 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
1488 | c, 0, 1, 0, 0); | |
1489 | tcg_temp_free(c); | |
79aceca5 FB |
1490 | } |
1491 | ||
fd3f0081 RH |
1492 | /* neg neg. nego nego. */ |
1493 | static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) | |
1494 | { | |
1495 | TCGv zero = tcg_const_tl(0); | |
1496 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
1497 | zero, 0, 0, compute_ov, Rc(ctx->opcode)); | |
1498 | tcg_temp_free(zero); | |
1499 | } | |
1500 | ||
1501 | static void gen_neg(DisasContext *ctx) | |
1502 | { | |
1480d71c ND |
1503 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
1504 | if (unlikely(Rc(ctx->opcode))) { | |
1505 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1506 | } | |
fd3f0081 RH |
1507 | } |
1508 | ||
1509 | static void gen_nego(DisasContext *ctx) | |
1510 | { | |
1511 | gen_op_arith_neg(ctx, 1); | |
1512 | } | |
1513 | ||
79aceca5 | 1514 | /*** Integer logical ***/ |
26d67362 | 1515 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ |
efe843d8 | 1516 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 1517 | { \ |
26d67362 AJ |
1518 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ |
1519 | cpu_gpr[rB(ctx->opcode)]); \ | |
76a66253 | 1520 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
26d67362 | 1521 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
79aceca5 | 1522 | } |
79aceca5 | 1523 | |
26d67362 | 1524 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ |
efe843d8 | 1525 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 1526 | { \ |
26d67362 | 1527 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ |
76a66253 | 1528 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
26d67362 | 1529 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
79aceca5 FB |
1530 | } |
1531 | ||
1532 | /* and & and. */ | |
26d67362 | 1533 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); |
79aceca5 | 1534 | /* andc & andc. */ |
26d67362 | 1535 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); |
e8eaa2c0 | 1536 | |
54623277 | 1537 | /* andi. */ |
e8eaa2c0 | 1538 | static void gen_andi_(DisasContext *ctx) |
79aceca5 | 1539 | { |
efe843d8 DG |
1540 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], |
1541 | UIMM(ctx->opcode)); | |
26d67362 | 1542 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 | 1543 | } |
e8eaa2c0 | 1544 | |
54623277 | 1545 | /* andis. */ |
e8eaa2c0 | 1546 | static void gen_andis_(DisasContext *ctx) |
79aceca5 | 1547 | { |
efe843d8 DG |
1548 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], |
1549 | UIMM(ctx->opcode) << 16); | |
26d67362 | 1550 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 | 1551 | } |
99e300ef | 1552 | |
54623277 | 1553 | /* cntlzw */ |
99e300ef | 1554 | static void gen_cntlzw(DisasContext *ctx) |
26d67362 | 1555 | { |
9b8514e5 RH |
1556 | TCGv_i32 t = tcg_temp_new_i32(); |
1557 | ||
1558 | tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); | |
1559 | tcg_gen_clzi_i32(t, t, 32); | |
1560 | tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); | |
1561 | tcg_temp_free_i32(t); | |
1562 | ||
efe843d8 | 1563 | if (unlikely(Rc(ctx->opcode) != 0)) { |
2e31f5d3 | 1564 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 1565 | } |
26d67362 | 1566 | } |
b35344e4 ND |
1567 | |
1568 | /* cnttzw */ | |
1569 | static void gen_cnttzw(DisasContext *ctx) | |
1570 | { | |
9b8514e5 RH |
1571 | TCGv_i32 t = tcg_temp_new_i32(); |
1572 | ||
1573 | tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); | |
1574 | tcg_gen_ctzi_i32(t, t, 32); | |
1575 | tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); | |
1576 | tcg_temp_free_i32(t); | |
1577 | ||
b35344e4 ND |
1578 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1579 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1580 | } | |
1581 | } | |
1582 | ||
79aceca5 | 1583 | /* eqv & eqv. */ |
26d67362 | 1584 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); |
79aceca5 | 1585 | /* extsb & extsb. */ |
26d67362 | 1586 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); |
79aceca5 | 1587 | /* extsh & extsh. */ |
26d67362 | 1588 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); |
79aceca5 | 1589 | /* nand & nand. */ |
26d67362 | 1590 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); |
79aceca5 | 1591 | /* nor & nor. */ |
26d67362 | 1592 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); |
99e300ef | 1593 | |
7f2b1744 | 1594 | #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) |
b68e60e6 BH |
1595 | static void gen_pause(DisasContext *ctx) |
1596 | { | |
1597 | TCGv_i32 t0 = tcg_const_i32(0); | |
1598 | tcg_gen_st_i32(t0, cpu_env, | |
1599 | -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); | |
1600 | tcg_temp_free_i32(t0); | |
1601 | ||
1602 | /* Stop translation, this gives other CPUs a chance to run */ | |
b6bac4bc | 1603 | gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); |
b68e60e6 BH |
1604 | } |
1605 | #endif /* defined(TARGET_PPC64) */ | |
1606 | ||
54623277 | 1607 | /* or & or. */ |
99e300ef | 1608 | static void gen_or(DisasContext *ctx) |
9a64fbe4 | 1609 | { |
76a66253 JM |
1610 | int rs, ra, rb; |
1611 | ||
1612 | rs = rS(ctx->opcode); | |
1613 | ra = rA(ctx->opcode); | |
1614 | rb = rB(ctx->opcode); | |
1615 | /* Optimisation for mr. ri case */ | |
1616 | if (rs != ra || rs != rb) { | |
efe843d8 | 1617 | if (rs != rb) { |
26d67362 | 1618 | tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); |
efe843d8 | 1619 | } else { |
26d67362 | 1620 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); |
efe843d8 DG |
1621 | } |
1622 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
26d67362 | 1623 | gen_set_Rc0(ctx, cpu_gpr[ra]); |
efe843d8 | 1624 | } |
76a66253 | 1625 | } else if (unlikely(Rc(ctx->opcode) != 0)) { |
26d67362 | 1626 | gen_set_Rc0(ctx, cpu_gpr[rs]); |
c80f84e3 | 1627 | #if defined(TARGET_PPC64) |
9e196938 | 1628 | } else if (rs != 0) { /* 0 is nop */ |
26d67362 AJ |
1629 | int prio = 0; |
1630 | ||
c80f84e3 JM |
1631 | switch (rs) { |
1632 | case 1: | |
1633 | /* Set process priority to low */ | |
26d67362 | 1634 | prio = 2; |
c80f84e3 JM |
1635 | break; |
1636 | case 6: | |
1637 | /* Set process priority to medium-low */ | |
26d67362 | 1638 | prio = 3; |
c80f84e3 JM |
1639 | break; |
1640 | case 2: | |
1641 | /* Set process priority to normal */ | |
26d67362 | 1642 | prio = 4; |
c80f84e3 | 1643 | break; |
be147d08 JM |
1644 | #if !defined(CONFIG_USER_ONLY) |
1645 | case 31: | |
c47493f2 | 1646 | if (!ctx->pr) { |
be147d08 | 1647 | /* Set process priority to very low */ |
26d67362 | 1648 | prio = 1; |
be147d08 JM |
1649 | } |
1650 | break; | |
1651 | case 5: | |
c47493f2 | 1652 | if (!ctx->pr) { |
be147d08 | 1653 | /* Set process priority to medium-hight */ |
26d67362 | 1654 | prio = 5; |
be147d08 JM |
1655 | } |
1656 | break; | |
1657 | case 3: | |
c47493f2 | 1658 | if (!ctx->pr) { |
be147d08 | 1659 | /* Set process priority to high */ |
26d67362 | 1660 | prio = 6; |
be147d08 JM |
1661 | } |
1662 | break; | |
be147d08 | 1663 | case 7: |
b68e60e6 | 1664 | if (ctx->hv && !ctx->pr) { |
be147d08 | 1665 | /* Set process priority to very high */ |
26d67362 | 1666 | prio = 7; |
be147d08 JM |
1667 | } |
1668 | break; | |
be147d08 | 1669 | #endif |
c80f84e3 | 1670 | default: |
c80f84e3 JM |
1671 | break; |
1672 | } | |
26d67362 | 1673 | if (prio) { |
a7812ae4 | 1674 | TCGv t0 = tcg_temp_new(); |
54cdcae6 | 1675 | gen_load_spr(t0, SPR_PPR); |
ea363694 AJ |
1676 | tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); |
1677 | tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); | |
54cdcae6 | 1678 | gen_store_spr(SPR_PPR, t0); |
ea363694 | 1679 | tcg_temp_free(t0); |
9e196938 | 1680 | } |
7f2b1744 | 1681 | #if !defined(CONFIG_USER_ONLY) |
efe843d8 DG |
1682 | /* |
1683 | * Pause out of TCG otherwise spin loops with smt_low eat too | |
1684 | * much CPU and the kernel hangs. This applies to all | |
1685 | * encodings other than no-op, e.g., miso(rs=26), yield(27), | |
1686 | * mdoio(29), mdoom(30), and all currently undefined. | |
9e196938 AL |
1687 | */ |
1688 | gen_pause(ctx); | |
7f2b1744 | 1689 | #endif |
c80f84e3 | 1690 | #endif |
9a64fbe4 | 1691 | } |
9a64fbe4 | 1692 | } |
79aceca5 | 1693 | /* orc & orc. */ |
26d67362 | 1694 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); |
99e300ef | 1695 | |
54623277 | 1696 | /* xor & xor. */ |
99e300ef | 1697 | static void gen_xor(DisasContext *ctx) |
9a64fbe4 | 1698 | { |
9a64fbe4 | 1699 | /* Optimisation for "set to zero" case */ |
efe843d8 DG |
1700 | if (rS(ctx->opcode) != rB(ctx->opcode)) { |
1701 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], | |
1702 | cpu_gpr[rB(ctx->opcode)]); | |
1703 | } else { | |
26d67362 | 1704 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); |
efe843d8 DG |
1705 | } |
1706 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
26d67362 | 1707 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 1708 | } |
9a64fbe4 | 1709 | } |
99e300ef | 1710 | |
54623277 | 1711 | /* ori */ |
99e300ef | 1712 | static void gen_ori(DisasContext *ctx) |
79aceca5 | 1713 | { |
76a66253 | 1714 | target_ulong uimm = UIMM(ctx->opcode); |
79aceca5 | 1715 | |
9a64fbe4 | 1716 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
9a64fbe4 | 1717 | return; |
76a66253 | 1718 | } |
26d67362 | 1719 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
79aceca5 | 1720 | } |
99e300ef | 1721 | |
54623277 | 1722 | /* oris */ |
99e300ef | 1723 | static void gen_oris(DisasContext *ctx) |
79aceca5 | 1724 | { |
76a66253 | 1725 | target_ulong uimm = UIMM(ctx->opcode); |
79aceca5 | 1726 | |
9a64fbe4 FB |
1727 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1728 | /* NOP */ | |
1729 | return; | |
76a66253 | 1730 | } |
efe843d8 DG |
1731 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], |
1732 | uimm << 16); | |
79aceca5 | 1733 | } |
99e300ef | 1734 | |
54623277 | 1735 | /* xori */ |
99e300ef | 1736 | static void gen_xori(DisasContext *ctx) |
79aceca5 | 1737 | { |
76a66253 | 1738 | target_ulong uimm = UIMM(ctx->opcode); |
9a64fbe4 FB |
1739 | |
1740 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
1741 | /* NOP */ | |
1742 | return; | |
1743 | } | |
26d67362 | 1744 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
79aceca5 | 1745 | } |
99e300ef | 1746 | |
54623277 | 1747 | /* xoris */ |
99e300ef | 1748 | static void gen_xoris(DisasContext *ctx) |
79aceca5 | 1749 | { |
76a66253 | 1750 | target_ulong uimm = UIMM(ctx->opcode); |
9a64fbe4 FB |
1751 | |
1752 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
1753 | /* NOP */ | |
1754 | return; | |
1755 | } | |
efe843d8 DG |
1756 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], |
1757 | uimm << 16); | |
79aceca5 | 1758 | } |
99e300ef | 1759 | |
54623277 | 1760 | /* popcntb : PowerPC 2.03 specification */ |
99e300ef | 1761 | static void gen_popcntb(DisasContext *ctx) |
d9bce9d9 | 1762 | { |
eaabeef2 DG |
1763 | gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1764 | } | |
1765 | ||
1766 | static void gen_popcntw(DisasContext *ctx) | |
1767 | { | |
79770002 | 1768 | #if defined(TARGET_PPC64) |
eaabeef2 | 1769 | gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
79770002 RH |
1770 | #else |
1771 | tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1772 | #endif | |
eaabeef2 DG |
1773 | } |
1774 | ||
d9bce9d9 | 1775 | #if defined(TARGET_PPC64) |
eaabeef2 DG |
1776 | /* popcntd: PowerPC 2.06 specification */ |
1777 | static void gen_popcntd(DisasContext *ctx) | |
1778 | { | |
79770002 | 1779 | tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
d9bce9d9 | 1780 | } |
eaabeef2 | 1781 | #endif |
d9bce9d9 | 1782 | |
725bcec2 AJ |
1783 | /* prtyw: PowerPC 2.05 specification */ |
1784 | static void gen_prtyw(DisasContext *ctx) | |
1785 | { | |
1786 | TCGv ra = cpu_gpr[rA(ctx->opcode)]; | |
1787 | TCGv rs = cpu_gpr[rS(ctx->opcode)]; | |
1788 | TCGv t0 = tcg_temp_new(); | |
1789 | tcg_gen_shri_tl(t0, rs, 16); | |
1790 | tcg_gen_xor_tl(ra, rs, t0); | |
1791 | tcg_gen_shri_tl(t0, ra, 8); | |
1792 | tcg_gen_xor_tl(ra, ra, t0); | |
1793 | tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); | |
1794 | tcg_temp_free(t0); | |
1795 | } | |
1796 | ||
1797 | #if defined(TARGET_PPC64) | |
1798 | /* prtyd: PowerPC 2.05 specification */ | |
1799 | static void gen_prtyd(DisasContext *ctx) | |
1800 | { | |
1801 | TCGv ra = cpu_gpr[rA(ctx->opcode)]; | |
1802 | TCGv rs = cpu_gpr[rS(ctx->opcode)]; | |
1803 | TCGv t0 = tcg_temp_new(); | |
1804 | tcg_gen_shri_tl(t0, rs, 32); | |
1805 | tcg_gen_xor_tl(ra, rs, t0); | |
1806 | tcg_gen_shri_tl(t0, ra, 16); | |
1807 | tcg_gen_xor_tl(ra, ra, t0); | |
1808 | tcg_gen_shri_tl(t0, ra, 8); | |
1809 | tcg_gen_xor_tl(ra, ra, t0); | |
1810 | tcg_gen_andi_tl(ra, ra, 1); | |
1811 | tcg_temp_free(t0); | |
1812 | } | |
1813 | #endif | |
1814 | ||
86ba37ed TM |
1815 | #if defined(TARGET_PPC64) |
1816 | /* bpermd */ | |
1817 | static void gen_bpermd(DisasContext *ctx) | |
1818 | { | |
1819 | gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], | |
1820 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1821 | } | |
1822 | #endif | |
1823 | ||
d9bce9d9 JM |
1824 | #if defined(TARGET_PPC64) |
1825 | /* extsw & extsw. */ | |
26d67362 | 1826 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); |
99e300ef | 1827 | |
54623277 | 1828 | /* cntlzd */ |
99e300ef | 1829 | static void gen_cntlzd(DisasContext *ctx) |
26d67362 | 1830 | { |
9b8514e5 | 1831 | tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); |
efe843d8 | 1832 | if (unlikely(Rc(ctx->opcode) != 0)) { |
26d67362 | 1833 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 1834 | } |
26d67362 | 1835 | } |
e91d95b2 SD |
1836 | |
1837 | /* cnttzd */ | |
1838 | static void gen_cnttzd(DisasContext *ctx) | |
1839 | { | |
9b8514e5 | 1840 | tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); |
e91d95b2 SD |
1841 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1842 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1843 | } | |
1844 | } | |
fec5c62a RB |
1845 | |
1846 | /* darn */ | |
1847 | static void gen_darn(DisasContext *ctx) | |
1848 | { | |
1849 | int l = L(ctx->opcode); | |
1850 | ||
7e4357f6 | 1851 | if (l > 2) { |
fec5c62a | 1852 | tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); |
7e4357f6 RH |
1853 | } else { |
1854 | if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { | |
1855 | gen_io_start(); | |
1856 | } | |
1857 | if (l == 0) { | |
1858 | gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); | |
1859 | } else { | |
1860 | /* Return 64-bit random for both CRN and RRN */ | |
1861 | gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); | |
1862 | } | |
1863 | if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { | |
7e4357f6 RH |
1864 | gen_stop_exception(ctx); |
1865 | } | |
fec5c62a RB |
1866 | } |
1867 | } | |
d9bce9d9 JM |
1868 | #endif |
1869 | ||
79aceca5 | 1870 | /*** Integer rotate ***/ |
99e300ef | 1871 | |
54623277 | 1872 | /* rlwimi & rlwimi. */ |
99e300ef | 1873 | static void gen_rlwimi(DisasContext *ctx) |
79aceca5 | 1874 | { |
63ae0915 RH |
1875 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
1876 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
1877 | uint32_t sh = SH(ctx->opcode); | |
1878 | uint32_t mb = MB(ctx->opcode); | |
1879 | uint32_t me = ME(ctx->opcode); | |
1880 | ||
efe843d8 | 1881 | if (sh == (31 - me) && mb <= me) { |
63ae0915 | 1882 | tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); |
d03ef511 | 1883 | } else { |
d03ef511 | 1884 | target_ulong mask; |
a7812ae4 | 1885 | TCGv t1; |
63ae0915 | 1886 | |
76a66253 | 1887 | #if defined(TARGET_PPC64) |
d03ef511 AJ |
1888 | mb += 32; |
1889 | me += 32; | |
76a66253 | 1890 | #endif |
d03ef511 | 1891 | mask = MASK(mb, me); |
63ae0915 | 1892 | |
a7812ae4 | 1893 | t1 = tcg_temp_new(); |
2e11b15d RH |
1894 | if (mask <= 0xffffffffu) { |
1895 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
1896 | tcg_gen_trunc_tl_i32(t0, t_rs); | |
1897 | tcg_gen_rotli_i32(t0, t0, sh); | |
1898 | tcg_gen_extu_i32_tl(t1, t0); | |
1899 | tcg_temp_free_i32(t0); | |
1900 | } else { | |
1901 | #if defined(TARGET_PPC64) | |
1902 | tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); | |
1903 | tcg_gen_rotli_i64(t1, t1, sh); | |
1904 | #else | |
1905 | g_assert_not_reached(); | |
1906 | #endif | |
1907 | } | |
63ae0915 RH |
1908 | |
1909 | tcg_gen_andi_tl(t1, t1, mask); | |
1910 | tcg_gen_andi_tl(t_ra, t_ra, ~mask); | |
1911 | tcg_gen_or_tl(t_ra, t_ra, t1); | |
d03ef511 AJ |
1912 | tcg_temp_free(t1); |
1913 | } | |
63ae0915 RH |
1914 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1915 | gen_set_Rc0(ctx, t_ra); | |
1916 | } | |
79aceca5 | 1917 | } |
99e300ef | 1918 | |
54623277 | 1919 | /* rlwinm & rlwinm. */ |
99e300ef | 1920 | static void gen_rlwinm(DisasContext *ctx) |
79aceca5 | 1921 | { |
63ae0915 RH |
1922 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
1923 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
7b4d326f RH |
1924 | int sh = SH(ctx->opcode); |
1925 | int mb = MB(ctx->opcode); | |
1926 | int me = ME(ctx->opcode); | |
1927 | int len = me - mb + 1; | |
1928 | int rsh = (32 - sh) & 31; | |
1929 | ||
1930 | if (sh != 0 && len > 0 && me == (31 - sh)) { | |
1931 | tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); | |
1932 | } else if (me == 31 && rsh + len <= 32) { | |
1933 | tcg_gen_extract_tl(t_ra, t_rs, rsh, len); | |
d03ef511 | 1934 | } else { |
2e11b15d | 1935 | target_ulong mask; |
76a66253 | 1936 | #if defined(TARGET_PPC64) |
d03ef511 AJ |
1937 | mb += 32; |
1938 | me += 32; | |
76a66253 | 1939 | #endif |
2e11b15d | 1940 | mask = MASK(mb, me); |
7b4d326f RH |
1941 | if (sh == 0) { |
1942 | tcg_gen_andi_tl(t_ra, t_rs, mask); | |
1943 | } else if (mask <= 0xffffffffu) { | |
63ae0915 | 1944 | TCGv_i32 t0 = tcg_temp_new_i32(); |
63ae0915 RH |
1945 | tcg_gen_trunc_tl_i32(t0, t_rs); |
1946 | tcg_gen_rotli_i32(t0, t0, sh); | |
2e11b15d | 1947 | tcg_gen_andi_i32(t0, t0, mask); |
63ae0915 RH |
1948 | tcg_gen_extu_i32_tl(t_ra, t0); |
1949 | tcg_temp_free_i32(t0); | |
2e11b15d RH |
1950 | } else { |
1951 | #if defined(TARGET_PPC64) | |
1952 | tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); | |
1953 | tcg_gen_rotli_i64(t_ra, t_ra, sh); | |
1954 | tcg_gen_andi_i64(t_ra, t_ra, mask); | |
1955 | #else | |
1956 | g_assert_not_reached(); | |
1957 | #endif | |
63ae0915 RH |
1958 | } |
1959 | } | |
1960 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1961 | gen_set_Rc0(ctx, t_ra); | |
d03ef511 | 1962 | } |
79aceca5 | 1963 | } |
99e300ef | 1964 | |
54623277 | 1965 | /* rlwnm & rlwnm. */ |
99e300ef | 1966 | static void gen_rlwnm(DisasContext *ctx) |
79aceca5 | 1967 | { |
63ae0915 RH |
1968 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
1969 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
1970 | TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; | |
1971 | uint32_t mb = MB(ctx->opcode); | |
1972 | uint32_t me = ME(ctx->opcode); | |
2e11b15d | 1973 | target_ulong mask; |
57fca134 | 1974 | |
54843a58 | 1975 | #if defined(TARGET_PPC64) |
63ae0915 RH |
1976 | mb += 32; |
1977 | me += 32; | |
54843a58 | 1978 | #endif |
2e11b15d RH |
1979 | mask = MASK(mb, me); |
1980 | ||
1981 | if (mask <= 0xffffffffu) { | |
1982 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
1983 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
1984 | tcg_gen_trunc_tl_i32(t0, t_rb); | |
1985 | tcg_gen_trunc_tl_i32(t1, t_rs); | |
1986 | tcg_gen_andi_i32(t0, t0, 0x1f); | |
1987 | tcg_gen_rotl_i32(t1, t1, t0); | |
1988 | tcg_gen_extu_i32_tl(t_ra, t1); | |
1989 | tcg_temp_free_i32(t0); | |
1990 | tcg_temp_free_i32(t1); | |
1991 | } else { | |
1992 | #if defined(TARGET_PPC64) | |
1993 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
1994 | tcg_gen_andi_i64(t0, t_rb, 0x1f); | |
1995 | tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); | |
1996 | tcg_gen_rotl_i64(t_ra, t_ra, t0); | |
1997 | tcg_temp_free_i64(t0); | |
1998 | #else | |
1999 | g_assert_not_reached(); | |
2000 | #endif | |
2001 | } | |
57fca134 | 2002 | |
2e11b15d | 2003 | tcg_gen_andi_tl(t_ra, t_ra, mask); |
63ae0915 RH |
2004 | |
2005 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2006 | gen_set_Rc0(ctx, t_ra); | |
79aceca5 | 2007 | } |
79aceca5 FB |
2008 | } |
2009 | ||
d9bce9d9 JM |
2010 | #if defined(TARGET_PPC64) |
2011 | #define GEN_PPC64_R2(name, opc1, opc2) \ | |
e8eaa2c0 | 2012 | static void glue(gen_, name##0)(DisasContext *ctx) \ |
d9bce9d9 JM |
2013 | { \ |
2014 | gen_##name(ctx, 0); \ | |
2015 | } \ | |
e8eaa2c0 BS |
2016 | \ |
2017 | static void glue(gen_, name##1)(DisasContext *ctx) \ | |
d9bce9d9 JM |
2018 | { \ |
2019 | gen_##name(ctx, 1); \ | |
2020 | } | |
2021 | #define GEN_PPC64_R4(name, opc1, opc2) \ | |
e8eaa2c0 | 2022 | static void glue(gen_, name##0)(DisasContext *ctx) \ |
d9bce9d9 JM |
2023 | { \ |
2024 | gen_##name(ctx, 0, 0); \ | |
2025 | } \ | |
e8eaa2c0 BS |
2026 | \ |
2027 | static void glue(gen_, name##1)(DisasContext *ctx) \ | |
d9bce9d9 JM |
2028 | { \ |
2029 | gen_##name(ctx, 0, 1); \ | |
2030 | } \ | |
e8eaa2c0 BS |
2031 | \ |
2032 | static void glue(gen_, name##2)(DisasContext *ctx) \ | |
d9bce9d9 JM |
2033 | { \ |
2034 | gen_##name(ctx, 1, 0); \ | |
2035 | } \ | |
e8eaa2c0 BS |
2036 | \ |
2037 | static void glue(gen_, name##3)(DisasContext *ctx) \ | |
d9bce9d9 JM |
2038 | { \ |
2039 | gen_##name(ctx, 1, 1); \ | |
2040 | } | |
51789c41 | 2041 | |
a7b2c8b9 | 2042 | static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) |
51789c41 | 2043 | { |
a7b2c8b9 RH |
2044 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
2045 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
7b4d326f RH |
2046 | int len = me - mb + 1; |
2047 | int rsh = (64 - sh) & 63; | |
a7b2c8b9 | 2048 | |
7b4d326f RH |
2049 | if (sh != 0 && len > 0 && me == (63 - sh)) { |
2050 | tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); | |
2051 | } else if (me == 63 && rsh + len <= 64) { | |
2052 | tcg_gen_extract_tl(t_ra, t_rs, rsh, len); | |
d03ef511 | 2053 | } else { |
a7b2c8b9 RH |
2054 | tcg_gen_rotli_tl(t_ra, t_rs, sh); |
2055 | tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); | |
2056 | } | |
2057 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2058 | gen_set_Rc0(ctx, t_ra); | |
51789c41 | 2059 | } |
51789c41 | 2060 | } |
a7b2c8b9 | 2061 | |
d9bce9d9 | 2062 | /* rldicl - rldicl. */ |
636aa200 | 2063 | static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 2064 | { |
51789c41 | 2065 | uint32_t sh, mb; |
d9bce9d9 | 2066 | |
9d53c753 JM |
2067 | sh = SH(ctx->opcode) | (shn << 5); |
2068 | mb = MB(ctx->opcode) | (mbn << 5); | |
51789c41 | 2069 | gen_rldinm(ctx, mb, 63, sh); |
d9bce9d9 | 2070 | } |
51789c41 | 2071 | GEN_PPC64_R4(rldicl, 0x1E, 0x00); |
a7b2c8b9 | 2072 | |
d9bce9d9 | 2073 | /* rldicr - rldicr. */ |
636aa200 | 2074 | static inline void gen_rldicr(DisasContext *ctx, int men, int shn) |
d9bce9d9 | 2075 | { |
51789c41 | 2076 | uint32_t sh, me; |
d9bce9d9 | 2077 | |
9d53c753 JM |
2078 | sh = SH(ctx->opcode) | (shn << 5); |
2079 | me = MB(ctx->opcode) | (men << 5); | |
51789c41 | 2080 | gen_rldinm(ctx, 0, me, sh); |
d9bce9d9 | 2081 | } |
51789c41 | 2082 | GEN_PPC64_R4(rldicr, 0x1E, 0x02); |
a7b2c8b9 | 2083 | |
d9bce9d9 | 2084 | /* rldic - rldic. */ |
636aa200 | 2085 | static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 2086 | { |
51789c41 | 2087 | uint32_t sh, mb; |
d9bce9d9 | 2088 | |
9d53c753 JM |
2089 | sh = SH(ctx->opcode) | (shn << 5); |
2090 | mb = MB(ctx->opcode) | (mbn << 5); | |
51789c41 JM |
2091 | gen_rldinm(ctx, mb, 63 - sh, sh); |
2092 | } | |
2093 | GEN_PPC64_R4(rldic, 0x1E, 0x04); | |
2094 | ||
a7b2c8b9 | 2095 | static void gen_rldnm(DisasContext *ctx, int mb, int me) |
51789c41 | 2096 | { |
a7b2c8b9 RH |
2097 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
2098 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
2099 | TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; | |
54843a58 | 2100 | TCGv t0; |
d03ef511 | 2101 | |
a7812ae4 | 2102 | t0 = tcg_temp_new(); |
a7b2c8b9 RH |
2103 | tcg_gen_andi_tl(t0, t_rb, 0x3f); |
2104 | tcg_gen_rotl_tl(t_ra, t_rs, t0); | |
54843a58 | 2105 | tcg_temp_free(t0); |
a7b2c8b9 RH |
2106 | |
2107 | tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); | |
2108 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2109 | gen_set_Rc0(ctx, t_ra); | |
2110 | } | |
d9bce9d9 | 2111 | } |
51789c41 | 2112 | |
d9bce9d9 | 2113 | /* rldcl - rldcl. */ |
636aa200 | 2114 | static inline void gen_rldcl(DisasContext *ctx, int mbn) |
d9bce9d9 | 2115 | { |
51789c41 | 2116 | uint32_t mb; |
d9bce9d9 | 2117 | |
9d53c753 | 2118 | mb = MB(ctx->opcode) | (mbn << 5); |
51789c41 | 2119 | gen_rldnm(ctx, mb, 63); |
d9bce9d9 | 2120 | } |
36081602 | 2121 | GEN_PPC64_R2(rldcl, 0x1E, 0x08); |
a7b2c8b9 | 2122 | |
d9bce9d9 | 2123 | /* rldcr - rldcr. */ |
636aa200 | 2124 | static inline void gen_rldcr(DisasContext *ctx, int men) |
d9bce9d9 | 2125 | { |
51789c41 | 2126 | uint32_t me; |
d9bce9d9 | 2127 | |
9d53c753 | 2128 | me = MB(ctx->opcode) | (men << 5); |
51789c41 | 2129 | gen_rldnm(ctx, 0, me); |
d9bce9d9 | 2130 | } |
36081602 | 2131 | GEN_PPC64_R2(rldcr, 0x1E, 0x09); |
a7b2c8b9 | 2132 | |
d9bce9d9 | 2133 | /* rldimi - rldimi. */ |
a7b2c8b9 | 2134 | static void gen_rldimi(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 2135 | { |
a7b2c8b9 RH |
2136 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
2137 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
2138 | uint32_t sh = SH(ctx->opcode) | (shn << 5); | |
2139 | uint32_t mb = MB(ctx->opcode) | (mbn << 5); | |
2140 | uint32_t me = 63 - sh; | |
d9bce9d9 | 2141 | |
a7b2c8b9 RH |
2142 | if (mb <= me) { |
2143 | tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); | |
d03ef511 | 2144 | } else { |
a7b2c8b9 RH |
2145 | target_ulong mask = MASK(mb, me); |
2146 | TCGv t1 = tcg_temp_new(); | |
d03ef511 | 2147 | |
a7b2c8b9 RH |
2148 | tcg_gen_rotli_tl(t1, t_rs, sh); |
2149 | tcg_gen_andi_tl(t1, t1, mask); | |
2150 | tcg_gen_andi_tl(t_ra, t_ra, ~mask); | |
2151 | tcg_gen_or_tl(t_ra, t_ra, t1); | |
d03ef511 | 2152 | tcg_temp_free(t1); |
51789c41 | 2153 | } |
a7b2c8b9 RH |
2154 | if (unlikely(Rc(ctx->opcode) != 0)) { |
2155 | gen_set_Rc0(ctx, t_ra); | |
2156 | } | |
d9bce9d9 | 2157 | } |
36081602 | 2158 | GEN_PPC64_R4(rldimi, 0x1E, 0x06); |
d9bce9d9 JM |
2159 | #endif |
2160 | ||
79aceca5 | 2161 | /*** Integer shift ***/ |
99e300ef | 2162 | |
54623277 | 2163 | /* slw & slw. */ |
99e300ef | 2164 | static void gen_slw(DisasContext *ctx) |
26d67362 | 2165 | { |
7fd6bf7d | 2166 | TCGv t0, t1; |
26d67362 | 2167 | |
7fd6bf7d AJ |
2168 | t0 = tcg_temp_new(); |
2169 | /* AND rS with a mask that is 0 when rB >= 0x20 */ | |
2170 | #if defined(TARGET_PPC64) | |
2171 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); | |
2172 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
2173 | #else | |
2174 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); | |
2175 | tcg_gen_sari_tl(t0, t0, 0x1f); | |
2176 | #endif | |
2177 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
2178 | t1 = tcg_temp_new(); | |
2179 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); | |
2180 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
2181 | tcg_temp_free(t1); | |
fea0c503 | 2182 | tcg_temp_free(t0); |
7fd6bf7d | 2183 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 2184 | if (unlikely(Rc(ctx->opcode) != 0)) { |
26d67362 | 2185 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 2186 | } |
26d67362 | 2187 | } |
99e300ef | 2188 | |
54623277 | 2189 | /* sraw & sraw. */ |
99e300ef | 2190 | static void gen_sraw(DisasContext *ctx) |
26d67362 | 2191 | { |
d15f74fb | 2192 | gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, |
a7812ae4 | 2193 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
efe843d8 | 2194 | if (unlikely(Rc(ctx->opcode) != 0)) { |
26d67362 | 2195 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 2196 | } |
26d67362 | 2197 | } |
99e300ef | 2198 | |
54623277 | 2199 | /* srawi & srawi. */ |
99e300ef | 2200 | static void gen_srawi(DisasContext *ctx) |
79aceca5 | 2201 | { |
26d67362 | 2202 | int sh = SH(ctx->opcode); |
ba4af3e4 RH |
2203 | TCGv dst = cpu_gpr[rA(ctx->opcode)]; |
2204 | TCGv src = cpu_gpr[rS(ctx->opcode)]; | |
2205 | if (sh == 0) { | |
34a0fad1 | 2206 | tcg_gen_ext32s_tl(dst, src); |
da91a00f | 2207 | tcg_gen_movi_tl(cpu_ca, 0); |
af1c259f SD |
2208 | if (is_isa300(ctx)) { |
2209 | tcg_gen_movi_tl(cpu_ca32, 0); | |
2210 | } | |
26d67362 | 2211 | } else { |
ba4af3e4 RH |
2212 | TCGv t0; |
2213 | tcg_gen_ext32s_tl(dst, src); | |
2214 | tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); | |
2215 | t0 = tcg_temp_new(); | |
2216 | tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); | |
2217 | tcg_gen_and_tl(cpu_ca, cpu_ca, t0); | |
2218 | tcg_temp_free(t0); | |
2219 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); | |
af1c259f SD |
2220 | if (is_isa300(ctx)) { |
2221 | tcg_gen_mov_tl(cpu_ca32, cpu_ca); | |
2222 | } | |
ba4af3e4 RH |
2223 | tcg_gen_sari_tl(dst, dst, sh); |
2224 | } | |
2225 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2226 | gen_set_Rc0(ctx, dst); | |
d9bce9d9 | 2227 | } |
79aceca5 | 2228 | } |
99e300ef | 2229 | |
54623277 | 2230 | /* srw & srw. */ |
99e300ef | 2231 | static void gen_srw(DisasContext *ctx) |
26d67362 | 2232 | { |
fea0c503 | 2233 | TCGv t0, t1; |
d9bce9d9 | 2234 | |
7fd6bf7d AJ |
2235 | t0 = tcg_temp_new(); |
2236 | /* AND rS with a mask that is 0 when rB >= 0x20 */ | |
2237 | #if defined(TARGET_PPC64) | |
2238 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); | |
2239 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
2240 | #else | |
2241 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); | |
2242 | tcg_gen_sari_tl(t0, t0, 0x1f); | |
2243 | #endif | |
2244 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
2245 | tcg_gen_ext32u_tl(t0, t0); | |
a7812ae4 | 2246 | t1 = tcg_temp_new(); |
7fd6bf7d AJ |
2247 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); |
2248 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
fea0c503 | 2249 | tcg_temp_free(t1); |
fea0c503 | 2250 | tcg_temp_free(t0); |
efe843d8 | 2251 | if (unlikely(Rc(ctx->opcode) != 0)) { |
26d67362 | 2252 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 2253 | } |
26d67362 | 2254 | } |
54623277 | 2255 | |
d9bce9d9 JM |
2256 | #if defined(TARGET_PPC64) |
2257 | /* sld & sld. */ | |
99e300ef | 2258 | static void gen_sld(DisasContext *ctx) |
26d67362 | 2259 | { |
7fd6bf7d | 2260 | TCGv t0, t1; |
26d67362 | 2261 | |
7fd6bf7d AJ |
2262 | t0 = tcg_temp_new(); |
2263 | /* AND rS with a mask that is 0 when rB >= 0x40 */ | |
2264 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); | |
2265 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
2266 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
2267 | t1 = tcg_temp_new(); | |
2268 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); | |
2269 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
2270 | tcg_temp_free(t1); | |
fea0c503 | 2271 | tcg_temp_free(t0); |
efe843d8 | 2272 | if (unlikely(Rc(ctx->opcode) != 0)) { |
26d67362 | 2273 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 2274 | } |
26d67362 | 2275 | } |
99e300ef | 2276 | |
54623277 | 2277 | /* srad & srad. */ |
99e300ef | 2278 | static void gen_srad(DisasContext *ctx) |
26d67362 | 2279 | { |
d15f74fb | 2280 | gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, |
a7812ae4 | 2281 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
efe843d8 | 2282 | if (unlikely(Rc(ctx->opcode) != 0)) { |
26d67362 | 2283 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 2284 | } |
26d67362 | 2285 | } |
d9bce9d9 | 2286 | /* sradi & sradi. */ |
636aa200 | 2287 | static inline void gen_sradi(DisasContext *ctx, int n) |
d9bce9d9 | 2288 | { |
26d67362 | 2289 | int sh = SH(ctx->opcode) + (n << 5); |
ba4af3e4 RH |
2290 | TCGv dst = cpu_gpr[rA(ctx->opcode)]; |
2291 | TCGv src = cpu_gpr[rS(ctx->opcode)]; | |
2292 | if (sh == 0) { | |
2293 | tcg_gen_mov_tl(dst, src); | |
da91a00f | 2294 | tcg_gen_movi_tl(cpu_ca, 0); |
af1c259f SD |
2295 | if (is_isa300(ctx)) { |
2296 | tcg_gen_movi_tl(cpu_ca32, 0); | |
2297 | } | |
26d67362 | 2298 | } else { |
ba4af3e4 RH |
2299 | TCGv t0; |
2300 | tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); | |
2301 | t0 = tcg_temp_new(); | |
2302 | tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); | |
2303 | tcg_gen_and_tl(cpu_ca, cpu_ca, t0); | |
2304 | tcg_temp_free(t0); | |
2305 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); | |
af1c259f SD |
2306 | if (is_isa300(ctx)) { |
2307 | tcg_gen_mov_tl(cpu_ca32, cpu_ca); | |
2308 | } | |
ba4af3e4 RH |
2309 | tcg_gen_sari_tl(dst, src, sh); |
2310 | } | |
2311 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2312 | gen_set_Rc0(ctx, dst); | |
d9bce9d9 | 2313 | } |
d9bce9d9 | 2314 | } |
e8eaa2c0 BS |
2315 | |
2316 | static void gen_sradi0(DisasContext *ctx) | |
d9bce9d9 JM |
2317 | { |
2318 | gen_sradi(ctx, 0); | |
2319 | } | |
e8eaa2c0 BS |
2320 | |
2321 | static void gen_sradi1(DisasContext *ctx) | |
d9bce9d9 JM |
2322 | { |
2323 | gen_sradi(ctx, 1); | |
2324 | } | |
99e300ef | 2325 | |
787bbe37 ND |
2326 | /* extswsli & extswsli. */ |
2327 | static inline void gen_extswsli(DisasContext *ctx, int n) | |
2328 | { | |
2329 | int sh = SH(ctx->opcode) + (n << 5); | |
2330 | TCGv dst = cpu_gpr[rA(ctx->opcode)]; | |
2331 | TCGv src = cpu_gpr[rS(ctx->opcode)]; | |
2332 | ||
2333 | tcg_gen_ext32s_tl(dst, src); | |
2334 | tcg_gen_shli_tl(dst, dst, sh); | |
2335 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2336 | gen_set_Rc0(ctx, dst); | |
2337 | } | |
2338 | } | |
2339 | ||
2340 | static void gen_extswsli0(DisasContext *ctx) | |
2341 | { | |
2342 | gen_extswsli(ctx, 0); | |
2343 | } | |
2344 | ||
2345 | static void gen_extswsli1(DisasContext *ctx) | |
2346 | { | |
2347 | gen_extswsli(ctx, 1); | |
2348 | } | |
2349 | ||
54623277 | 2350 | /* srd & srd. */ |
99e300ef | 2351 | static void gen_srd(DisasContext *ctx) |
26d67362 | 2352 | { |
7fd6bf7d | 2353 | TCGv t0, t1; |
26d67362 | 2354 | |
7fd6bf7d AJ |
2355 | t0 = tcg_temp_new(); |
2356 | /* AND rS with a mask that is 0 when rB >= 0x40 */ | |
2357 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); | |
2358 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
2359 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
2360 | t1 = tcg_temp_new(); | |
2361 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); | |
2362 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
2363 | tcg_temp_free(t1); | |
fea0c503 | 2364 | tcg_temp_free(t0); |
efe843d8 | 2365 | if (unlikely(Rc(ctx->opcode) != 0)) { |
26d67362 | 2366 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 2367 | } |
26d67362 | 2368 | } |
d9bce9d9 | 2369 | #endif |
79aceca5 | 2370 | |
76a66253 JM |
2371 | /*** Addressing modes ***/ |
2372 | /* Register indirect with immediate index : EA = (rA|0) + SIMM */ | |
636aa200 BS |
2373 | static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, |
2374 | target_long maskl) | |
76a66253 JM |
2375 | { |
2376 | target_long simm = SIMM(ctx->opcode); | |
2377 | ||
be147d08 | 2378 | simm &= ~maskl; |
76db3ba4 | 2379 | if (rA(ctx->opcode) == 0) { |
c791fe84 RH |
2380 | if (NARROW_MODE(ctx)) { |
2381 | simm = (uint32_t)simm; | |
2382 | } | |
e2be8d8d | 2383 | tcg_gen_movi_tl(EA, simm); |
76db3ba4 | 2384 | } else if (likely(simm != 0)) { |
e2be8d8d | 2385 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); |
c791fe84 | 2386 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
2387 | tcg_gen_ext32u_tl(EA, EA); |
2388 | } | |
76db3ba4 | 2389 | } else { |
c791fe84 | 2390 | if (NARROW_MODE(ctx)) { |
76db3ba4 | 2391 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
c791fe84 RH |
2392 | } else { |
2393 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
2394 | } | |
76db3ba4 | 2395 | } |
76a66253 JM |
2396 | } |
2397 | ||
636aa200 | 2398 | static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) |
76a66253 | 2399 | { |
76db3ba4 | 2400 | if (rA(ctx->opcode) == 0) { |
c791fe84 | 2401 | if (NARROW_MODE(ctx)) { |
76db3ba4 | 2402 | tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); |
c791fe84 RH |
2403 | } else { |
2404 | tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); | |
2405 | } | |
76db3ba4 | 2406 | } else { |
e2be8d8d | 2407 | tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
c791fe84 | 2408 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
2409 | tcg_gen_ext32u_tl(EA, EA); |
2410 | } | |
76db3ba4 | 2411 | } |
76a66253 JM |
2412 | } |
2413 | ||
636aa200 | 2414 | static inline void gen_addr_register(DisasContext *ctx, TCGv EA) |
76a66253 | 2415 | { |
76db3ba4 | 2416 | if (rA(ctx->opcode) == 0) { |
e2be8d8d | 2417 | tcg_gen_movi_tl(EA, 0); |
c791fe84 RH |
2418 | } else if (NARROW_MODE(ctx)) { |
2419 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
76db3ba4 | 2420 | } else { |
c791fe84 | 2421 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
76db3ba4 AJ |
2422 | } |
2423 | } | |
2424 | ||
636aa200 BS |
2425 | static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
2426 | target_long val) | |
76db3ba4 AJ |
2427 | { |
2428 | tcg_gen_addi_tl(ret, arg1, val); | |
c791fe84 | 2429 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
2430 | tcg_gen_ext32u_tl(ret, ret); |
2431 | } | |
76a66253 JM |
2432 | } |
2433 | ||
65f2475f BH |
2434 | static inline void gen_align_no_le(DisasContext *ctx) |
2435 | { | |
2436 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, | |
2437 | (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); | |
2438 | } | |
2439 | ||
7863667f | 2440 | /*** Integer load ***/ |
09bfe50d | 2441 | #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) |
ff5f3981 | 2442 | #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) |
b61f2753 | 2443 | |
09bfe50d ND |
2444 | #define GEN_QEMU_LOAD_TL(ldop, op) \ |
2445 | static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ | |
2446 | TCGv val, \ | |
2447 | TCGv addr) \ | |
2448 | { \ | |
2449 | tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ | |
b61f2753 AJ |
2450 | } |
2451 | ||
09bfe50d ND |
2452 | GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) |
2453 | GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) | |
2454 | GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) | |
2455 | GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) | |
2456 | GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) | |
f976b09e | 2457 | |
ff5f3981 ND |
2458 | GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) |
2459 | GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) | |
2460 | ||
09bfe50d ND |
2461 | #define GEN_QEMU_LOAD_64(ldop, op) \ |
2462 | static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ | |
2463 | TCGv_i64 val, \ | |
2464 | TCGv addr) \ | |
2465 | { \ | |
2466 | tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ | |
b61f2753 AJ |
2467 | } |
2468 | ||
740ae9a2 ND |
2469 | GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) |
2470 | GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) | |
09bfe50d ND |
2471 | GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) |
2472 | GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) | |
4f364fe7 | 2473 | GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) |
b61f2753 | 2474 | |
ff5f3981 ND |
2475 | #if defined(TARGET_PPC64) |
2476 | GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) | |
2477 | #endif | |
2478 | ||
761a89c6 ND |
2479 | #define GEN_QEMU_STORE_TL(stop, op) \ |
2480 | static void glue(gen_qemu_, stop)(DisasContext *ctx, \ | |
2481 | TCGv val, \ | |
2482 | TCGv addr) \ | |
2483 | { \ | |
2484 | tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ | |
b61f2753 AJ |
2485 | } |
2486 | ||
761a89c6 ND |
2487 | GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) |
2488 | GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) | |
2489 | GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) | |
b61f2753 | 2490 | |
804108aa ND |
2491 | GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) |
2492 | GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) | |
2493 | ||
761a89c6 ND |
2494 | #define GEN_QEMU_STORE_64(stop, op) \ |
2495 | static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ | |
2496 | TCGv_i64 val, \ | |
2497 | TCGv addr) \ | |
2498 | { \ | |
2499 | tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ | |
b61f2753 AJ |
2500 | } |
2501 | ||
ddb9ac50 ND |
2502 | GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) |
2503 | GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) | |
761a89c6 | 2504 | GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) |
2468f23d | 2505 | GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) |
b61f2753 | 2506 | |
804108aa ND |
2507 | #if defined(TARGET_PPC64) |
2508 | GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) | |
2509 | #endif | |
2510 | ||
0c8aacd4 | 2511 | #define GEN_LD(name, ldop, opc, type) \ |
efe843d8 | 2512 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 2513 | { \ |
76db3ba4 AJ |
2514 | TCGv EA; \ |
2515 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2516 | EA = tcg_temp_new(); \ | |
2517 | gen_addr_imm_index(ctx, EA, 0); \ | |
2518 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 | 2519 | tcg_temp_free(EA); \ |
79aceca5 FB |
2520 | } |
2521 | ||
0c8aacd4 | 2522 | #define GEN_LDU(name, ldop, opc, type) \ |
efe843d8 | 2523 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
79aceca5 | 2524 | { \ |
b61f2753 | 2525 | TCGv EA; \ |
76a66253 JM |
2526 | if (unlikely(rA(ctx->opcode) == 0 || \ |
2527 | rA(ctx->opcode) == rD(ctx->opcode))) { \ | |
e06fcd75 | 2528 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2529 | return; \ |
9a64fbe4 | 2530 | } \ |
76db3ba4 | 2531 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2532 | EA = tcg_temp_new(); \ |
9d53c753 | 2533 | if (type == PPC_64B) \ |
76db3ba4 | 2534 | gen_addr_imm_index(ctx, EA, 0x03); \ |
9d53c753 | 2535 | else \ |
76db3ba4 AJ |
2536 | gen_addr_imm_index(ctx, EA, 0); \ |
2537 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2538 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2539 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2540 | } |
2541 | ||
0c8aacd4 | 2542 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \ |
efe843d8 | 2543 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 2544 | { \ |
b61f2753 | 2545 | TCGv EA; \ |
76a66253 JM |
2546 | if (unlikely(rA(ctx->opcode) == 0 || \ |
2547 | rA(ctx->opcode) == rD(ctx->opcode))) { \ | |
e06fcd75 | 2548 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2549 | return; \ |
9a64fbe4 | 2550 | } \ |
76db3ba4 | 2551 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2552 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
2553 | gen_addr_reg_index(ctx, EA); \ |
2554 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2555 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2556 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2557 | } |
2558 | ||
b7815375 | 2559 | #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ |
99e300ef | 2560 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 2561 | { \ |
76db3ba4 | 2562 | TCGv EA; \ |
b7815375 | 2563 | chk; \ |
76db3ba4 AJ |
2564 | gen_set_access_type(ctx, ACCESS_INT); \ |
2565 | EA = tcg_temp_new(); \ | |
2566 | gen_addr_reg_index(ctx, EA); \ | |
2567 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 | 2568 | tcg_temp_free(EA); \ |
79aceca5 | 2569 | } |
b7815375 | 2570 | |
cd6e9320 | 2571 | #define GEN_LDX(name, ldop, opc2, opc3, type) \ |
b7815375 BH |
2572 | GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) |
2573 | ||
2574 | #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ | |
2575 | GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) | |
79aceca5 | 2576 | |
0c8aacd4 AJ |
2577 | #define GEN_LDS(name, ldop, op, type) \ |
2578 | GEN_LD(name, ldop, op | 0x20, type); \ | |
2579 | GEN_LDU(name, ldop, op | 0x21, type); \ | |
2580 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ | |
2581 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) | |
79aceca5 FB |
2582 | |
2583 | /* lbz lbzu lbzux lbzx */ | |
0c8aacd4 | 2584 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); |
79aceca5 | 2585 | /* lha lhau lhaux lhax */ |
0c8aacd4 | 2586 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); |
79aceca5 | 2587 | /* lhz lhzu lhzux lhzx */ |
0c8aacd4 | 2588 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); |
79aceca5 | 2589 | /* lwz lwzu lwzux lwzx */ |
0c8aacd4 | 2590 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); |
50728199 RK |
2591 | |
2592 | #define GEN_LDEPX(name, ldop, opc2, opc3) \ | |
2593 | static void glue(gen_, name##epx)(DisasContext *ctx) \ | |
2594 | { \ | |
2595 | TCGv EA; \ | |
2596 | CHK_SV; \ | |
2597 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2598 | EA = tcg_temp_new(); \ | |
2599 | gen_addr_reg_index(ctx, EA); \ | |
2600 | tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ | |
2601 | tcg_temp_free(EA); \ | |
2602 | } | |
2603 | ||
2604 | GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) | |
2605 | GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) | |
2606 | GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) | |
2607 | #if defined(TARGET_PPC64) | |
2608 | GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) | |
2609 | #endif | |
2610 | ||
d9bce9d9 | 2611 | #if defined(TARGET_PPC64) |
d9bce9d9 | 2612 | /* lwaux */ |
0c8aacd4 | 2613 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); |
d9bce9d9 | 2614 | /* lwax */ |
0c8aacd4 | 2615 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); |
d9bce9d9 | 2616 | /* ldux */ |
4f364fe7 | 2617 | GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B); |
d9bce9d9 | 2618 | /* ldx */ |
4f364fe7 | 2619 | GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B); |
99e300ef | 2620 | |
b7815375 | 2621 | /* CI load/store variants */ |
4f364fe7 | 2622 | GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) |
b7815375 BH |
2623 | GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) |
2624 | GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) | |
2625 | GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) | |
2626 | ||
99e300ef | 2627 | static void gen_ld(DisasContext *ctx) |
d9bce9d9 | 2628 | { |
b61f2753 | 2629 | TCGv EA; |
d9bce9d9 JM |
2630 | if (Rc(ctx->opcode)) { |
2631 | if (unlikely(rA(ctx->opcode) == 0 || | |
2632 | rA(ctx->opcode) == rD(ctx->opcode))) { | |
e06fcd75 | 2633 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
d9bce9d9 JM |
2634 | return; |
2635 | } | |
2636 | } | |
76db3ba4 | 2637 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2638 | EA = tcg_temp_new(); |
76db3ba4 | 2639 | gen_addr_imm_index(ctx, EA, 0x03); |
d9bce9d9 JM |
2640 | if (ctx->opcode & 0x02) { |
2641 | /* lwa (lwau is undefined) */ | |
76db3ba4 | 2642 | gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
d9bce9d9 JM |
2643 | } else { |
2644 | /* ld - ldu */ | |
4f364fe7 | 2645 | gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
d9bce9d9 | 2646 | } |
efe843d8 | 2647 | if (Rc(ctx->opcode)) { |
b61f2753 | 2648 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
efe843d8 | 2649 | } |
b61f2753 | 2650 | tcg_temp_free(EA); |
d9bce9d9 | 2651 | } |
99e300ef | 2652 | |
54623277 | 2653 | /* lq */ |
99e300ef | 2654 | static void gen_lq(DisasContext *ctx) |
be147d08 | 2655 | { |
be147d08 | 2656 | int ra, rd; |
94bf2658 | 2657 | TCGv EA, hi, lo; |
be147d08 | 2658 | |
e0498daa TM |
2659 | /* lq is a legal user mode instruction starting in ISA 2.07 */ |
2660 | bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; | |
2661 | bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; | |
2662 | ||
c47493f2 | 2663 | if (!legal_in_user_mode && ctx->pr) { |
9b2fadda | 2664 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2665 | return; |
2666 | } | |
e0498daa TM |
2667 | |
2668 | if (!le_is_supported && ctx->le_mode) { | |
65f2475f | 2669 | gen_align_no_le(ctx); |
e0498daa TM |
2670 | return; |
2671 | } | |
be147d08 JM |
2672 | ra = rA(ctx->opcode); |
2673 | rd = rD(ctx->opcode); | |
2674 | if (unlikely((rd & 1) || rd == ra)) { | |
e06fcd75 | 2675 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
be147d08 JM |
2676 | return; |
2677 | } | |
e0498daa | 2678 | |
76db3ba4 | 2679 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2680 | EA = tcg_temp_new(); |
76db3ba4 | 2681 | gen_addr_imm_index(ctx, EA, 0x0F); |
e0498daa | 2682 | |
94bf2658 RH |
2683 | /* Note that the low part is always in RD+1, even in LE mode. */ |
2684 | lo = cpu_gpr[rd + 1]; | |
2685 | hi = cpu_gpr[rd]; | |
2686 | ||
2687 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { | |
f34ec0f6 RH |
2688 | if (HAVE_ATOMIC128) { |
2689 | TCGv_i32 oi = tcg_temp_new_i32(); | |
2690 | if (ctx->le_mode) { | |
2691 | tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); | |
2692 | gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); | |
2693 | } else { | |
2694 | tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); | |
2695 | gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); | |
2696 | } | |
2697 | tcg_temp_free_i32(oi); | |
2698 | tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); | |
94bf2658 | 2699 | } else { |
f34ec0f6 RH |
2700 | /* Restart with exclusive lock. */ |
2701 | gen_helper_exit_atomic(cpu_env); | |
2702 | ctx->base.is_jmp = DISAS_NORETURN; | |
94bf2658 | 2703 | } |
94bf2658 RH |
2704 | } else if (ctx->le_mode) { |
2705 | tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ); | |
e0498daa | 2706 | gen_addr_add(ctx, EA, EA, 8); |
94bf2658 | 2707 | tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); |
e0498daa | 2708 | } else { |
94bf2658 | 2709 | tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ); |
e0498daa | 2710 | gen_addr_add(ctx, EA, EA, 8); |
94bf2658 | 2711 | tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); |
e0498daa | 2712 | } |
b61f2753 | 2713 | tcg_temp_free(EA); |
be147d08 | 2714 | } |
d9bce9d9 | 2715 | #endif |
79aceca5 FB |
2716 | |
2717 | /*** Integer store ***/ | |
0c8aacd4 | 2718 | #define GEN_ST(name, stop, opc, type) \ |
efe843d8 | 2719 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 2720 | { \ |
76db3ba4 AJ |
2721 | TCGv EA; \ |
2722 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2723 | EA = tcg_temp_new(); \ | |
2724 | gen_addr_imm_index(ctx, EA, 0); \ | |
2725 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 | 2726 | tcg_temp_free(EA); \ |
79aceca5 FB |
2727 | } |
2728 | ||
0c8aacd4 | 2729 | #define GEN_STU(name, stop, opc, type) \ |
efe843d8 | 2730 | static void glue(gen_, stop##u)(DisasContext *ctx) \ |
79aceca5 | 2731 | { \ |
b61f2753 | 2732 | TCGv EA; \ |
76a66253 | 2733 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 2734 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2735 | return; \ |
9a64fbe4 | 2736 | } \ |
76db3ba4 | 2737 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2738 | EA = tcg_temp_new(); \ |
9d53c753 | 2739 | if (type == PPC_64B) \ |
76db3ba4 | 2740 | gen_addr_imm_index(ctx, EA, 0x03); \ |
9d53c753 | 2741 | else \ |
76db3ba4 AJ |
2742 | gen_addr_imm_index(ctx, EA, 0); \ |
2743 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2744 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2745 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2746 | } |
2747 | ||
0c8aacd4 | 2748 | #define GEN_STUX(name, stop, opc2, opc3, type) \ |
efe843d8 | 2749 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 2750 | { \ |
b61f2753 | 2751 | TCGv EA; \ |
76a66253 | 2752 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 2753 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2754 | return; \ |
9a64fbe4 | 2755 | } \ |
76db3ba4 | 2756 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2757 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
2758 | gen_addr_reg_index(ctx, EA); \ |
2759 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2760 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2761 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2762 | } |
2763 | ||
b7815375 | 2764 | #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ |
cd6e9320 | 2765 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 2766 | { \ |
76db3ba4 | 2767 | TCGv EA; \ |
b7815375 | 2768 | chk; \ |
76db3ba4 AJ |
2769 | gen_set_access_type(ctx, ACCESS_INT); \ |
2770 | EA = tcg_temp_new(); \ | |
2771 | gen_addr_reg_index(ctx, EA); \ | |
2772 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 | 2773 | tcg_temp_free(EA); \ |
79aceca5 | 2774 | } |
cd6e9320 | 2775 | #define GEN_STX(name, stop, opc2, opc3, type) \ |
b7815375 BH |
2776 | GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) |
2777 | ||
2778 | #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ | |
2779 | GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) | |
79aceca5 | 2780 | |
0c8aacd4 AJ |
2781 | #define GEN_STS(name, stop, op, type) \ |
2782 | GEN_ST(name, stop, op | 0x20, type); \ | |
2783 | GEN_STU(name, stop, op | 0x21, type); \ | |
2784 | GEN_STUX(name, stop, 0x17, op | 0x01, type); \ | |
2785 | GEN_STX(name, stop, 0x17, op | 0x00, type) | |
79aceca5 FB |
2786 | |
2787 | /* stb stbu stbux stbx */ | |
0c8aacd4 | 2788 | GEN_STS(stb, st8, 0x06, PPC_INTEGER); |
79aceca5 | 2789 | /* sth sthu sthux sthx */ |
0c8aacd4 | 2790 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER); |
79aceca5 | 2791 | /* stw stwu stwux stwx */ |
0c8aacd4 | 2792 | GEN_STS(stw, st32, 0x04, PPC_INTEGER); |
50728199 RK |
2793 | |
2794 | #define GEN_STEPX(name, stop, opc2, opc3) \ | |
2795 | static void glue(gen_, name##epx)(DisasContext *ctx) \ | |
2796 | { \ | |
2797 | TCGv EA; \ | |
2798 | CHK_SV; \ | |
2799 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2800 | EA = tcg_temp_new(); \ | |
2801 | gen_addr_reg_index(ctx, EA); \ | |
2802 | tcg_gen_qemu_st_tl( \ | |
2803 | cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ | |
2804 | tcg_temp_free(EA); \ | |
2805 | } | |
2806 | ||
2807 | GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) | |
2808 | GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) | |
2809 | GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) | |
2810 | #if defined(TARGET_PPC64) | |
2811 | GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04) | |
2812 | #endif | |
2813 | ||
d9bce9d9 | 2814 | #if defined(TARGET_PPC64) |
2468f23d ND |
2815 | GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B); |
2816 | GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B); | |
2817 | GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) | |
b7815375 BH |
2818 | GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) |
2819 | GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) | |
2820 | GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) | |
99e300ef BS |
2821 | |
2822 | static void gen_std(DisasContext *ctx) | |
d9bce9d9 | 2823 | { |
be147d08 | 2824 | int rs; |
b61f2753 | 2825 | TCGv EA; |
be147d08 JM |
2826 | |
2827 | rs = rS(ctx->opcode); | |
84cab1e2 | 2828 | if ((ctx->opcode & 0x3) == 0x2) { /* stq */ |
84cab1e2 TM |
2829 | bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; |
2830 | bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; | |
f89ced5f | 2831 | TCGv hi, lo; |
84cab1e2 | 2832 | |
dfdd3e43 BH |
2833 | if (!(ctx->insns_flags & PPC_64BX)) { |
2834 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
2835 | } | |
2836 | ||
c47493f2 | 2837 | if (!legal_in_user_mode && ctx->pr) { |
9b2fadda | 2838 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2839 | return; |
2840 | } | |
84cab1e2 TM |
2841 | |
2842 | if (!le_is_supported && ctx->le_mode) { | |
65f2475f | 2843 | gen_align_no_le(ctx); |
d9bce9d9 JM |
2844 | return; |
2845 | } | |
84cab1e2 TM |
2846 | |
2847 | if (unlikely(rs & 1)) { | |
2848 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
be147d08 JM |
2849 | return; |
2850 | } | |
76db3ba4 | 2851 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2852 | EA = tcg_temp_new(); |
76db3ba4 | 2853 | gen_addr_imm_index(ctx, EA, 0x03); |
84cab1e2 | 2854 | |
f89ced5f RH |
2855 | /* Note that the low part is always in RS+1, even in LE mode. */ |
2856 | lo = cpu_gpr[rs + 1]; | |
2857 | hi = cpu_gpr[rs]; | |
2858 | ||
2859 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { | |
f34ec0f6 RH |
2860 | if (HAVE_ATOMIC128) { |
2861 | TCGv_i32 oi = tcg_temp_new_i32(); | |
2862 | if (ctx->le_mode) { | |
2863 | tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); | |
2864 | gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi); | |
2865 | } else { | |
2866 | tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); | |
2867 | gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi); | |
2868 | } | |
2869 | tcg_temp_free_i32(oi); | |
f89ced5f | 2870 | } else { |
f34ec0f6 RH |
2871 | /* Restart with exclusive lock. */ |
2872 | gen_helper_exit_atomic(cpu_env); | |
2873 | ctx->base.is_jmp = DISAS_NORETURN; | |
f89ced5f | 2874 | } |
f89ced5f RH |
2875 | } else if (ctx->le_mode) { |
2876 | tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ); | |
84cab1e2 | 2877 | gen_addr_add(ctx, EA, EA, 8); |
f89ced5f | 2878 | tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ); |
84cab1e2 | 2879 | } else { |
f89ced5f | 2880 | tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ); |
84cab1e2 | 2881 | gen_addr_add(ctx, EA, EA, 8); |
f89ced5f | 2882 | tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ); |
84cab1e2 | 2883 | } |
b61f2753 | 2884 | tcg_temp_free(EA); |
be147d08 | 2885 | } else { |
f89ced5f | 2886 | /* std / stdu */ |
be147d08 JM |
2887 | if (Rc(ctx->opcode)) { |
2888 | if (unlikely(rA(ctx->opcode) == 0)) { | |
e06fcd75 | 2889 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
be147d08 JM |
2890 | return; |
2891 | } | |
2892 | } | |
76db3ba4 | 2893 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2894 | EA = tcg_temp_new(); |
76db3ba4 | 2895 | gen_addr_imm_index(ctx, EA, 0x03); |
2468f23d | 2896 | gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); |
efe843d8 | 2897 | if (Rc(ctx->opcode)) { |
b61f2753 | 2898 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
efe843d8 | 2899 | } |
b61f2753 | 2900 | tcg_temp_free(EA); |
d9bce9d9 | 2901 | } |
d9bce9d9 JM |
2902 | } |
2903 | #endif | |
79aceca5 | 2904 | /*** Integer load and store with byte reverse ***/ |
e22c357b | 2905 | |
79aceca5 | 2906 | /* lhbrx */ |
0c8aacd4 | 2907 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); |
b61f2753 | 2908 | |
79aceca5 | 2909 | /* lwbrx */ |
0c8aacd4 | 2910 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); |
b61f2753 | 2911 | |
cd6e9320 TH |
2912 | #if defined(TARGET_PPC64) |
2913 | /* ldbrx */ | |
ff5f3981 | 2914 | GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); |
804108aa ND |
2915 | /* stdbrx */ |
2916 | GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); | |
cd6e9320 TH |
2917 | #endif /* TARGET_PPC64 */ |
2918 | ||
79aceca5 | 2919 | /* sthbrx */ |
0c8aacd4 | 2920 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); |
79aceca5 | 2921 | /* stwbrx */ |
0c8aacd4 | 2922 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); |
79aceca5 FB |
2923 | |
2924 | /*** Integer load and store multiple ***/ | |
99e300ef | 2925 | |
54623277 | 2926 | /* lmw */ |
99e300ef | 2927 | static void gen_lmw(DisasContext *ctx) |
79aceca5 | 2928 | { |
76db3ba4 AJ |
2929 | TCGv t0; |
2930 | TCGv_i32 t1; | |
5817355e BH |
2931 | |
2932 | if (ctx->le_mode) { | |
2933 | gen_align_no_le(ctx); | |
2934 | return; | |
2935 | } | |
76db3ba4 | 2936 | gen_set_access_type(ctx, ACCESS_INT); |
76db3ba4 AJ |
2937 | t0 = tcg_temp_new(); |
2938 | t1 = tcg_const_i32(rD(ctx->opcode)); | |
2939 | gen_addr_imm_index(ctx, t0, 0); | |
2f5a189c | 2940 | gen_helper_lmw(cpu_env, t0, t1); |
ff4a62cd AJ |
2941 | tcg_temp_free(t0); |
2942 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
2943 | } |
2944 | ||
2945 | /* stmw */ | |
99e300ef | 2946 | static void gen_stmw(DisasContext *ctx) |
79aceca5 | 2947 | { |
76db3ba4 AJ |
2948 | TCGv t0; |
2949 | TCGv_i32 t1; | |
5817355e BH |
2950 | |
2951 | if (ctx->le_mode) { | |
2952 | gen_align_no_le(ctx); | |
2953 | return; | |
2954 | } | |
76db3ba4 | 2955 | gen_set_access_type(ctx, ACCESS_INT); |
76db3ba4 AJ |
2956 | t0 = tcg_temp_new(); |
2957 | t1 = tcg_const_i32(rS(ctx->opcode)); | |
2958 | gen_addr_imm_index(ctx, t0, 0); | |
2f5a189c | 2959 | gen_helper_stmw(cpu_env, t0, t1); |
ff4a62cd AJ |
2960 | tcg_temp_free(t0); |
2961 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
2962 | } |
2963 | ||
2964 | /*** Integer load and store strings ***/ | |
54623277 | 2965 | |
79aceca5 | 2966 | /* lswi */ |
efe843d8 DG |
2967 | /* |
2968 | * PowerPC32 specification says we must generate an exception if rA is | |
2969 | * in the range of registers to be loaded. In an other hand, IBM says | |
2970 | * this is valid, but rA won't be loaded. For now, I'll follow the | |
2971 | * spec... | |
9a64fbe4 | 2972 | */ |
99e300ef | 2973 | static void gen_lswi(DisasContext *ctx) |
79aceca5 | 2974 | { |
dfbc799d AJ |
2975 | TCGv t0; |
2976 | TCGv_i32 t1, t2; | |
79aceca5 FB |
2977 | int nb = NB(ctx->opcode); |
2978 | int start = rD(ctx->opcode); | |
9a64fbe4 | 2979 | int ra = rA(ctx->opcode); |
79aceca5 FB |
2980 | int nr; |
2981 | ||
5817355e BH |
2982 | if (ctx->le_mode) { |
2983 | gen_align_no_le(ctx); | |
2984 | return; | |
2985 | } | |
efe843d8 | 2986 | if (nb == 0) { |
79aceca5 | 2987 | nb = 32; |
efe843d8 | 2988 | } |
f0704d78 | 2989 | nr = DIV_ROUND_UP(nb, 4); |
afbee712 | 2990 | if (unlikely(lsw_reg_in_range(start, nr, ra))) { |
e06fcd75 | 2991 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); |
9fddaa0c | 2992 | return; |
297d8e62 | 2993 | } |
76db3ba4 | 2994 | gen_set_access_type(ctx, ACCESS_INT); |
dfbc799d | 2995 | t0 = tcg_temp_new(); |
76db3ba4 | 2996 | gen_addr_register(ctx, t0); |
dfbc799d AJ |
2997 | t1 = tcg_const_i32(nb); |
2998 | t2 = tcg_const_i32(start); | |
2f5a189c | 2999 | gen_helper_lsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
3000 | tcg_temp_free(t0); |
3001 | tcg_temp_free_i32(t1); | |
3002 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
3003 | } |
3004 | ||
3005 | /* lswx */ | |
99e300ef | 3006 | static void gen_lswx(DisasContext *ctx) |
79aceca5 | 3007 | { |
76db3ba4 AJ |
3008 | TCGv t0; |
3009 | TCGv_i32 t1, t2, t3; | |
5817355e BH |
3010 | |
3011 | if (ctx->le_mode) { | |
3012 | gen_align_no_le(ctx); | |
3013 | return; | |
3014 | } | |
76db3ba4 | 3015 | gen_set_access_type(ctx, ACCESS_INT); |
76db3ba4 AJ |
3016 | t0 = tcg_temp_new(); |
3017 | gen_addr_reg_index(ctx, t0); | |
3018 | t1 = tcg_const_i32(rD(ctx->opcode)); | |
3019 | t2 = tcg_const_i32(rA(ctx->opcode)); | |
3020 | t3 = tcg_const_i32(rB(ctx->opcode)); | |
2f5a189c | 3021 | gen_helper_lswx(cpu_env, t0, t1, t2, t3); |
dfbc799d AJ |
3022 | tcg_temp_free(t0); |
3023 | tcg_temp_free_i32(t1); | |
3024 | tcg_temp_free_i32(t2); | |
3025 | tcg_temp_free_i32(t3); | |
79aceca5 FB |
3026 | } |
3027 | ||
3028 | /* stswi */ | |
99e300ef | 3029 | static void gen_stswi(DisasContext *ctx) |
79aceca5 | 3030 | { |
76db3ba4 AJ |
3031 | TCGv t0; |
3032 | TCGv_i32 t1, t2; | |
4b3686fa | 3033 | int nb = NB(ctx->opcode); |
5817355e BH |
3034 | |
3035 | if (ctx->le_mode) { | |
3036 | gen_align_no_le(ctx); | |
3037 | return; | |
3038 | } | |
76db3ba4 | 3039 | gen_set_access_type(ctx, ACCESS_INT); |
76db3ba4 AJ |
3040 | t0 = tcg_temp_new(); |
3041 | gen_addr_register(ctx, t0); | |
efe843d8 | 3042 | if (nb == 0) { |
4b3686fa | 3043 | nb = 32; |
efe843d8 | 3044 | } |
dfbc799d | 3045 | t1 = tcg_const_i32(nb); |
76db3ba4 | 3046 | t2 = tcg_const_i32(rS(ctx->opcode)); |
2f5a189c | 3047 | gen_helper_stsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
3048 | tcg_temp_free(t0); |
3049 | tcg_temp_free_i32(t1); | |
3050 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
3051 | } |
3052 | ||
3053 | /* stswx */ | |
99e300ef | 3054 | static void gen_stswx(DisasContext *ctx) |
79aceca5 | 3055 | { |
76db3ba4 AJ |
3056 | TCGv t0; |
3057 | TCGv_i32 t1, t2; | |
5817355e BH |
3058 | |
3059 | if (ctx->le_mode) { | |
3060 | gen_align_no_le(ctx); | |
3061 | return; | |
3062 | } | |
76db3ba4 | 3063 | gen_set_access_type(ctx, ACCESS_INT); |
76db3ba4 AJ |
3064 | t0 = tcg_temp_new(); |
3065 | gen_addr_reg_index(ctx, t0); | |
3066 | t1 = tcg_temp_new_i32(); | |
dfbc799d AJ |
3067 | tcg_gen_trunc_tl_i32(t1, cpu_xer); |
3068 | tcg_gen_andi_i32(t1, t1, 0x7F); | |
76db3ba4 | 3069 | t2 = tcg_const_i32(rS(ctx->opcode)); |
2f5a189c | 3070 | gen_helper_stsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
3071 | tcg_temp_free(t0); |
3072 | tcg_temp_free_i32(t1); | |
3073 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
3074 | } |
3075 | ||
3076 | /*** Memory synchronisation ***/ | |
3077 | /* eieio */ | |
99e300ef | 3078 | static void gen_eieio(DisasContext *ctx) |
79aceca5 | 3079 | { |
c8fd8373 CLG |
3080 | TCGBar bar = TCG_MO_LD_ST; |
3081 | ||
3082 | /* | |
3083 | * POWER9 has a eieio instruction variant using bit 6 as a hint to | |
3084 | * tell the CPU it is a store-forwarding barrier. | |
3085 | */ | |
3086 | if (ctx->opcode & 0x2000000) { | |
3087 | /* | |
3088 | * ISA says that "Reserved fields in instructions are ignored | |
3089 | * by the processor". So ignore the bit 6 on non-POWER9 CPU but | |
3090 | * as this is not an instruction software should be using, | |
3091 | * complain to the user. | |
3092 | */ | |
3093 | if (!(ctx->insns_flags2 & PPC2_ISA300)) { | |
3094 | qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" | |
3095 | TARGET_FMT_lx "\n", ctx->base.pc_next - 4); | |
3096 | } else { | |
3097 | bar = TCG_MO_ST_LD; | |
3098 | } | |
3099 | } | |
3100 | ||
3101 | tcg_gen_mb(bar | TCG_BAR_SC); | |
79aceca5 FB |
3102 | } |
3103 | ||
c5a8d8f3 | 3104 | #if !defined(CONFIG_USER_ONLY) |
e3cffe6f | 3105 | static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) |
cd0c6f47 | 3106 | { |
c5a8d8f3 BH |
3107 | TCGv_i32 t; |
3108 | TCGLabel *l; | |
cd0c6f47 | 3109 | |
c5a8d8f3 BH |
3110 | if (!ctx->lazy_tlb_flush) { |
3111 | return; | |
3112 | } | |
3113 | l = gen_new_label(); | |
3114 | t = tcg_temp_new_i32(); | |
cd0c6f47 BH |
3115 | tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); |
3116 | tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); | |
e3cffe6f ND |
3117 | if (global) { |
3118 | gen_helper_check_tlb_flush_global(cpu_env); | |
3119 | } else { | |
3120 | gen_helper_check_tlb_flush_local(cpu_env); | |
3121 | } | |
cd0c6f47 BH |
3122 | gen_set_label(l); |
3123 | tcg_temp_free_i32(t); | |
3124 | } | |
3125 | #else | |
e3cffe6f | 3126 | static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } |
cd0c6f47 BH |
3127 | #endif |
3128 | ||
79aceca5 | 3129 | /* isync */ |
99e300ef | 3130 | static void gen_isync(DisasContext *ctx) |
79aceca5 | 3131 | { |
cd0c6f47 BH |
3132 | /* |
3133 | * We need to check for a pending TLB flush. This can only happen in | |
3134 | * kernel mode however so check MSR_PR | |
3135 | */ | |
3136 | if (!ctx->pr) { | |
e3cffe6f | 3137 | gen_check_tlb_flush(ctx, false); |
cd0c6f47 | 3138 | } |
4771df23 | 3139 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); |
e06fcd75 | 3140 | gen_stop_exception(ctx); |
79aceca5 FB |
3141 | } |
3142 | ||
48793c95 ND |
3143 | #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) |
3144 | ||
14776ab5 | 3145 | static void gen_load_locked(DisasContext *ctx, MemOp memop) |
2a4e6c1b RH |
3146 | { |
3147 | TCGv gpr = cpu_gpr[rD(ctx->opcode)]; | |
3148 | TCGv t0 = tcg_temp_new(); | |
3149 | ||
3150 | gen_set_access_type(ctx, ACCESS_RES); | |
3151 | gen_addr_reg_index(ctx, t0); | |
3152 | tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); | |
3153 | tcg_gen_mov_tl(cpu_reserve, t0); | |
3154 | tcg_gen_mov_tl(cpu_reserve_val, gpr); | |
3155 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | |
3156 | tcg_temp_free(t0); | |
3157 | } | |
3158 | ||
3159 | #define LARX(name, memop) \ | |
3160 | static void gen_##name(DisasContext *ctx) \ | |
3161 | { \ | |
3162 | gen_load_locked(ctx, memop); \ | |
79aceca5 FB |
3163 | } |
3164 | ||
5c77a786 | 3165 | /* lwarx */ |
48793c95 ND |
3166 | LARX(lbarx, DEF_MEMOP(MO_UB)) |
3167 | LARX(lharx, DEF_MEMOP(MO_UW)) | |
3168 | LARX(lwarx, DEF_MEMOP(MO_UL)) | |
5c77a786 | 3169 | |
14776ab5 | 3170 | static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, |
20923c1d RH |
3171 | TCGv EA, TCGCond cond, int addend) |
3172 | { | |
3173 | TCGv t = tcg_temp_new(); | |
3174 | TCGv t2 = tcg_temp_new(); | |
3175 | TCGv u = tcg_temp_new(); | |
3176 | ||
3177 | tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); | |
3178 | tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); | |
3179 | tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); | |
3180 | tcg_gen_addi_tl(u, t, addend); | |
3181 | ||
3182 | /* E.g. for fetch and increment bounded... */ | |
3183 | /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ | |
3184 | tcg_gen_movcond_tl(cond, u, t, t2, u, t); | |
3185 | tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); | |
3186 | ||
3187 | /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ | |
3188 | tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); | |
3189 | tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); | |
3190 | ||
3191 | tcg_temp_free(t); | |
3192 | tcg_temp_free(t2); | |
3193 | tcg_temp_free(u); | |
3194 | } | |
3195 | ||
14776ab5 | 3196 | static void gen_ld_atomic(DisasContext *ctx, MemOp memop) |
20ba8504 RH |
3197 | { |
3198 | uint32_t gpr_FC = FC(ctx->opcode); | |
3199 | TCGv EA = tcg_temp_new(); | |
20923c1d RH |
3200 | int rt = rD(ctx->opcode); |
3201 | bool need_serial; | |
20ba8504 RH |
3202 | TCGv src, dst; |
3203 | ||
3204 | gen_addr_register(ctx, EA); | |
20923c1d RH |
3205 | dst = cpu_gpr[rt]; |
3206 | src = cpu_gpr[(rt + 1) & 31]; | |
20ba8504 | 3207 | |
20923c1d | 3208 | need_serial = false; |
20ba8504 RH |
3209 | memop |= MO_ALIGN; |
3210 | switch (gpr_FC) { | |
3211 | case 0: /* Fetch and add */ | |
3212 | tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); | |
3213 | break; | |
3214 | case 1: /* Fetch and xor */ | |
3215 | tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); | |
3216 | break; | |
3217 | case 2: /* Fetch and or */ | |
3218 | tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); | |
3219 | break; | |
3220 | case 3: /* Fetch and 'and' */ | |
3221 | tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); | |
3222 | break; | |
20ba8504 | 3223 | case 4: /* Fetch and max unsigned */ |
b8ce0f86 RH |
3224 | tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); |
3225 | break; | |
20ba8504 | 3226 | case 5: /* Fetch and max signed */ |
b8ce0f86 RH |
3227 | tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); |
3228 | break; | |
20ba8504 | 3229 | case 6: /* Fetch and min unsigned */ |
b8ce0f86 RH |
3230 | tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); |
3231 | break; | |
20ba8504 | 3232 | case 7: /* Fetch and min signed */ |
b8ce0f86 RH |
3233 | tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); |
3234 | break; | |
3235 | case 8: /* Swap */ | |
3236 | tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); | |
3237 | break; | |
20923c1d RH |
3238 | |
3239 | case 16: /* Compare and swap not equal */ | |
3240 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { | |
3241 | need_serial = true; | |
3242 | } else { | |
3243 | TCGv t0 = tcg_temp_new(); | |
3244 | TCGv t1 = tcg_temp_new(); | |
3245 | ||
3246 | tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); | |
3247 | if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { | |
3248 | tcg_gen_mov_tl(t1, src); | |
3249 | } else { | |
3250 | tcg_gen_ext32u_tl(t1, src); | |
3251 | } | |
3252 | tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, | |
3253 | cpu_gpr[(rt + 2) & 31], t0); | |
3254 | tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); | |
3255 | tcg_gen_mov_tl(dst, t0); | |
3256 | ||
3257 | tcg_temp_free(t0); | |
3258 | tcg_temp_free(t1); | |
3259 | } | |
3260 | break; | |
3261 | ||
20ba8504 | 3262 | case 24: /* Fetch and increment bounded */ |
20923c1d RH |
3263 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { |
3264 | need_serial = true; | |
3265 | } else { | |
3266 | gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); | |
3267 | } | |
3268 | break; | |
20ba8504 | 3269 | case 25: /* Fetch and increment equal */ |
20923c1d RH |
3270 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { |
3271 | need_serial = true; | |
3272 | } else { | |
3273 | gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); | |
3274 | } | |
3275 | break; | |
20ba8504 | 3276 | case 28: /* Fetch and decrement bounded */ |
20923c1d RH |
3277 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { |
3278 | need_serial = true; | |
3279 | } else { | |
3280 | gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); | |
3281 | } | |
20ba8504 | 3282 | break; |
20923c1d | 3283 | |
20ba8504 RH |
3284 | default: |
3285 | /* invoke data storage error handler */ | |
3286 | gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); | |
3287 | } | |
3288 | tcg_temp_free(EA); | |
20923c1d RH |
3289 | |
3290 | if (need_serial) { | |
3291 | /* Restart with exclusive lock. */ | |
3292 | gen_helper_exit_atomic(cpu_env); | |
3293 | ctx->base.is_jmp = DISAS_NORETURN; | |
3294 | } | |
20ba8504 RH |
3295 | } |
3296 | ||
3297 | static void gen_lwat(DisasContext *ctx) | |
3298 | { | |
3299 | gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); | |
3300 | } | |
3301 | ||
3302 | #ifdef TARGET_PPC64 | |
3303 | static void gen_ldat(DisasContext *ctx) | |
3304 | { | |
3305 | gen_ld_atomic(ctx, DEF_MEMOP(MO_Q)); | |
3306 | } | |
a68a6146 B |
3307 | #endif |
3308 | ||
14776ab5 | 3309 | static void gen_st_atomic(DisasContext *ctx, MemOp memop) |
9deb041c RH |
3310 | { |
3311 | uint32_t gpr_FC = FC(ctx->opcode); | |
3312 | TCGv EA = tcg_temp_new(); | |
3313 | TCGv src, discard; | |
3314 | ||
3315 | gen_addr_register(ctx, EA); | |
3316 | src = cpu_gpr[rD(ctx->opcode)]; | |
3317 | discard = tcg_temp_new(); | |
3318 | ||
3319 | memop |= MO_ALIGN; | |
3320 | switch (gpr_FC) { | |
3321 | case 0: /* add and Store */ | |
3322 | tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); | |
3323 | break; | |
3324 | case 1: /* xor and Store */ | |
3325 | tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); | |
3326 | break; | |
3327 | case 2: /* Or and Store */ | |
3328 | tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); | |
3329 | break; | |
3330 | case 3: /* 'and' and Store */ | |
3331 | tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); | |
3332 | break; | |
3333 | case 4: /* Store max unsigned */ | |
b8ce0f86 RH |
3334 | tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); |
3335 | break; | |
9deb041c | 3336 | case 5: /* Store max signed */ |
b8ce0f86 RH |
3337 | tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); |
3338 | break; | |
9deb041c | 3339 | case 6: /* Store min unsigned */ |
b8ce0f86 RH |
3340 | tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); |
3341 | break; | |
9deb041c | 3342 | case 7: /* Store min signed */ |
b8ce0f86 RH |
3343 | tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); |
3344 | break; | |
9deb041c | 3345 | case 24: /* Store twin */ |
7fbc2b20 RH |
3346 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { |
3347 | /* Restart with exclusive lock. */ | |
3348 | gen_helper_exit_atomic(cpu_env); | |
3349 | ctx->base.is_jmp = DISAS_NORETURN; | |
3350 | } else { | |
3351 | TCGv t = tcg_temp_new(); | |
3352 | TCGv t2 = tcg_temp_new(); | |
3353 | TCGv s = tcg_temp_new(); | |
3354 | TCGv s2 = tcg_temp_new(); | |
3355 | TCGv ea_plus_s = tcg_temp_new(); | |
3356 | ||
3357 | tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); | |
3358 | tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); | |
3359 | tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); | |
3360 | tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); | |
3361 | tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); | |
3362 | tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); | |
3363 | tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); | |
3364 | ||
3365 | tcg_temp_free(ea_plus_s); | |
3366 | tcg_temp_free(s2); | |
3367 | tcg_temp_free(s); | |
3368 | tcg_temp_free(t2); | |
3369 | tcg_temp_free(t); | |
3370 | } | |
9deb041c RH |
3371 | break; |
3372 | default: | |
3373 | /* invoke data storage error handler */ | |
3374 | gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); | |
3375 | } | |
3376 | tcg_temp_free(discard); | |
3377 | tcg_temp_free(EA); | |
3378 | } | |
3379 | ||
3380 | static void gen_stwat(DisasContext *ctx) | |
3381 | { | |
3382 | gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); | |
3383 | } | |
3384 | ||
3385 | #ifdef TARGET_PPC64 | |
3386 | static void gen_stdat(DisasContext *ctx) | |
3387 | { | |
3388 | gen_st_atomic(ctx, DEF_MEMOP(MO_Q)); | |
3389 | } | |
a3401188 B |
3390 | #endif |
3391 | ||
14776ab5 | 3392 | static void gen_conditional_store(DisasContext *ctx, MemOp memop) |
587c51f7 | 3393 | { |
253ce7b2 ND |
3394 | TCGLabel *l1 = gen_new_label(); |
3395 | TCGLabel *l2 = gen_new_label(); | |
d8b86898 RH |
3396 | TCGv t0 = tcg_temp_new(); |
3397 | int reg = rS(ctx->opcode); | |
4425265b | 3398 | |
d8b86898 RH |
3399 | gen_set_access_type(ctx, ACCESS_RES); |
3400 | gen_addr_reg_index(ctx, t0); | |
3401 | tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); | |
3402 | tcg_temp_free(t0); | |
253ce7b2 ND |
3403 | |
3404 | t0 = tcg_temp_new(); | |
3405 | tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, | |
3406 | cpu_gpr[reg], ctx->mem_idx, | |
3407 | DEF_MEMOP(memop) | MO_ALIGN); | |
3408 | tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); | |
3409 | tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); | |
3410 | tcg_gen_or_tl(t0, t0, cpu_so); | |
3411 | tcg_gen_trunc_tl_i32(cpu_crf[0], t0); | |
3412 | tcg_temp_free(t0); | |
3413 | tcg_gen_br(l2); | |
3414 | ||
587c51f7 | 3415 | gen_set_label(l1); |
4771df23 | 3416 | |
efe843d8 DG |
3417 | /* |
3418 | * Address mismatch implies failure. But we still need to provide | |
3419 | * the memory barrier semantics of the instruction. | |
3420 | */ | |
4771df23 | 3421 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); |
253ce7b2 ND |
3422 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
3423 | ||
3424 | gen_set_label(l2); | |
587c51f7 TM |
3425 | tcg_gen_movi_tl(cpu_reserve, -1); |
3426 | } | |
587c51f7 | 3427 | |
d8b86898 RH |
3428 | #define STCX(name, memop) \ |
3429 | static void gen_##name(DisasContext *ctx) \ | |
3430 | { \ | |
3431 | gen_conditional_store(ctx, memop); \ | |
2391b357 ND |
3432 | } |
3433 | ||
3434 | STCX(stbcx_, DEF_MEMOP(MO_UB)) | |
3435 | STCX(sthcx_, DEF_MEMOP(MO_UW)) | |
3436 | STCX(stwcx_, DEF_MEMOP(MO_UL)) | |
587c51f7 | 3437 | |
426613db | 3438 | #if defined(TARGET_PPC64) |
426613db | 3439 | /* ldarx */ |
48793c95 | 3440 | LARX(ldarx, DEF_MEMOP(MO_Q)) |
2391b357 ND |
3441 | /* stdcx. */ |
3442 | STCX(stdcx_, DEF_MEMOP(MO_Q)) | |
426613db | 3443 | |
9c294d5a TM |
3444 | /* lqarx */ |
3445 | static void gen_lqarx(DisasContext *ctx) | |
3446 | { | |
9c294d5a | 3447 | int rd = rD(ctx->opcode); |
94bf2658 | 3448 | TCGv EA, hi, lo; |
9c294d5a TM |
3449 | |
3450 | if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || | |
3451 | (rd == rB(ctx->opcode)))) { | |
3452 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
3453 | return; | |
3454 | } | |
3455 | ||
3456 | gen_set_access_type(ctx, ACCESS_RES); | |
94bf2658 | 3457 | EA = tcg_temp_new(); |
9c294d5a | 3458 | gen_addr_reg_index(ctx, EA); |
94bf2658 RH |
3459 | |
3460 | /* Note that the low part is always in RD+1, even in LE mode. */ | |
3461 | lo = cpu_gpr[rd + 1]; | |
3462 | hi = cpu_gpr[rd]; | |
3463 | ||
3464 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { | |
f34ec0f6 RH |
3465 | if (HAVE_ATOMIC128) { |
3466 | TCGv_i32 oi = tcg_temp_new_i32(); | |
3467 | if (ctx->le_mode) { | |
3468 | tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16, | |
3469 | ctx->mem_idx)); | |
3470 | gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); | |
3471 | } else { | |
3472 | tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16, | |
3473 | ctx->mem_idx)); | |
3474 | gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); | |
3475 | } | |
3476 | tcg_temp_free_i32(oi); | |
3477 | tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); | |
94bf2658 | 3478 | } else { |
f34ec0f6 RH |
3479 | /* Restart with exclusive lock. */ |
3480 | gen_helper_exit_atomic(cpu_env); | |
3481 | ctx->base.is_jmp = DISAS_NORETURN; | |
3482 | tcg_temp_free(EA); | |
3483 | return; | |
94bf2658 | 3484 | } |
94bf2658 RH |
3485 | } else if (ctx->le_mode) { |
3486 | tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16); | |
3487 | tcg_gen_mov_tl(cpu_reserve, EA); | |
3488 | gen_addr_add(ctx, EA, EA, 8); | |
3489 | tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); | |
9c294d5a | 3490 | } else { |
94bf2658 RH |
3491 | tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16); |
3492 | tcg_gen_mov_tl(cpu_reserve, EA); | |
3493 | gen_addr_add(ctx, EA, EA, 8); | |
3494 | tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); | |
9c294d5a | 3495 | } |
9c294d5a | 3496 | tcg_temp_free(EA); |
94bf2658 RH |
3497 | |
3498 | tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); | |
3499 | tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); | |
9c294d5a TM |
3500 | } |
3501 | ||
aa2008af ND |
3502 | /* stqcx. */ |
3503 | static void gen_stqcx_(DisasContext *ctx) | |
3504 | { | |
4a9b3c5d RH |
3505 | int rs = rS(ctx->opcode); |
3506 | TCGv EA, hi, lo; | |
aa2008af | 3507 | |
4a9b3c5d | 3508 | if (unlikely(rs & 1)) { |
aa2008af ND |
3509 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
3510 | return; | |
3511 | } | |
4a9b3c5d | 3512 | |
aa2008af | 3513 | gen_set_access_type(ctx, ACCESS_RES); |
4a9b3c5d | 3514 | EA = tcg_temp_new(); |
aa2008af | 3515 | gen_addr_reg_index(ctx, EA); |
aa2008af | 3516 | |
4a9b3c5d RH |
3517 | /* Note that the low part is always in RS+1, even in LE mode. */ |
3518 | lo = cpu_gpr[rs + 1]; | |
3519 | hi = cpu_gpr[rs]; | |
aa2008af | 3520 | |
4a9b3c5d | 3521 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { |
f34ec0f6 RH |
3522 | if (HAVE_CMPXCHG128) { |
3523 | TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16); | |
3524 | if (ctx->le_mode) { | |
3525 | gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, | |
3526 | EA, lo, hi, oi); | |
3527 | } else { | |
3528 | gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env, | |
3529 | EA, lo, hi, oi); | |
3530 | } | |
3531 | tcg_temp_free_i32(oi); | |
4a9b3c5d | 3532 | } else { |
f34ec0f6 RH |
3533 | /* Restart with exclusive lock. */ |
3534 | gen_helper_exit_atomic(cpu_env); | |
3535 | ctx->base.is_jmp = DISAS_NORETURN; | |
4a9b3c5d | 3536 | } |
4a9b3c5d | 3537 | tcg_temp_free(EA); |
aa2008af | 3538 | } else { |
4a9b3c5d RH |
3539 | TCGLabel *lab_fail = gen_new_label(); |
3540 | TCGLabel *lab_over = gen_new_label(); | |
3541 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
3542 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
aa2008af | 3543 | |
4a9b3c5d RH |
3544 | tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); |
3545 | tcg_temp_free(EA); | |
aa2008af | 3546 | |
4a9b3c5d RH |
3547 | gen_qemu_ld64_i64(ctx, t0, cpu_reserve); |
3548 | tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode | |
3549 | ? offsetof(CPUPPCState, reserve_val2) | |
3550 | : offsetof(CPUPPCState, reserve_val))); | |
3551 | tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); | |
3552 | ||
3553 | tcg_gen_addi_i64(t0, cpu_reserve, 8); | |
3554 | gen_qemu_ld64_i64(ctx, t0, t0); | |
3555 | tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode | |
3556 | ? offsetof(CPUPPCState, reserve_val) | |
3557 | : offsetof(CPUPPCState, reserve_val2))); | |
3558 | tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); | |
3559 | ||
3560 | /* Success */ | |
3561 | gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve); | |
3562 | tcg_gen_addi_i64(t0, cpu_reserve, 8); | |
3563 | gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0); | |
3564 | ||
3565 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); | |
3566 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); | |
3567 | tcg_gen_br(lab_over); | |
3568 | ||
3569 | gen_set_label(lab_fail); | |
3570 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); | |
3571 | ||
3572 | gen_set_label(lab_over); | |
3573 | tcg_gen_movi_tl(cpu_reserve, -1); | |
3574 | tcg_temp_free_i64(t0); | |
3575 | tcg_temp_free_i64(t1); | |
3576 | } | |
3577 | } | |
426613db JM |
3578 | #endif /* defined(TARGET_PPC64) */ |
3579 | ||
79aceca5 | 3580 | /* sync */ |
99e300ef | 3581 | static void gen_sync(DisasContext *ctx) |
79aceca5 | 3582 | { |
cd0c6f47 BH |
3583 | uint32_t l = (ctx->opcode >> 21) & 3; |
3584 | ||
3585 | /* | |
c5a8d8f3 BH |
3586 | * We may need to check for a pending TLB flush. |
3587 | * | |
3588 | * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. | |
3589 | * | |
3590 | * Additionally, this can only happen in kernel mode however so | |
3591 | * check MSR_PR as well. | |
cd0c6f47 | 3592 | */ |
c5a8d8f3 | 3593 | if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { |
e3cffe6f | 3594 | gen_check_tlb_flush(ctx, true); |
cd0c6f47 | 3595 | } |
4771df23 | 3596 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); |
79aceca5 FB |
3597 | } |
3598 | ||
0db1b20e | 3599 | /* wait */ |
99e300ef | 3600 | static void gen_wait(DisasContext *ctx) |
0db1b20e | 3601 | { |
35b5066e | 3602 | TCGv_i32 t0 = tcg_const_i32(1); |
259186a7 AF |
3603 | tcg_gen_st_i32(t0, cpu_env, |
3604 | -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); | |
931ff272 | 3605 | tcg_temp_free_i32(t0); |
0db1b20e | 3606 | /* Stop translation, as the CPU is supposed to sleep from now */ |
b6bac4bc | 3607 | gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); |
0db1b20e JM |
3608 | } |
3609 | ||
7778a575 BH |
3610 | #if defined(TARGET_PPC64) |
3611 | static void gen_doze(DisasContext *ctx) | |
3612 | { | |
3613 | #if defined(CONFIG_USER_ONLY) | |
3614 | GEN_PRIV; | |
3615 | #else | |
3616 | TCGv_i32 t; | |
3617 | ||
3618 | CHK_HV; | |
3619 | t = tcg_const_i32(PPC_PM_DOZE); | |
3620 | gen_helper_pminsn(cpu_env, t); | |
3621 | tcg_temp_free_i32(t); | |
154c69f2 BH |
3622 | /* Stop translation, as the CPU is supposed to sleep from now */ |
3623 | gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); | |
7778a575 BH |
3624 | #endif /* defined(CONFIG_USER_ONLY) */ |
3625 | } | |
3626 | ||
3627 | static void gen_nap(DisasContext *ctx) | |
3628 | { | |
3629 | #if defined(CONFIG_USER_ONLY) | |
3630 | GEN_PRIV; | |
3631 | #else | |
3632 | TCGv_i32 t; | |
3633 | ||
3634 | CHK_HV; | |
3635 | t = tcg_const_i32(PPC_PM_NAP); | |
3636 | gen_helper_pminsn(cpu_env, t); | |
3637 | tcg_temp_free_i32(t); | |
154c69f2 BH |
3638 | /* Stop translation, as the CPU is supposed to sleep from now */ |
3639 | gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); | |
7778a575 BH |
3640 | #endif /* defined(CONFIG_USER_ONLY) */ |
3641 | } | |
3642 | ||
cdee0e72 ND |
3643 | static void gen_stop(DisasContext *ctx) |
3644 | { | |
21c0d66a BH |
3645 | #if defined(CONFIG_USER_ONLY) |
3646 | GEN_PRIV; | |
3647 | #else | |
3648 | TCGv_i32 t; | |
3649 | ||
3650 | CHK_HV; | |
3651 | t = tcg_const_i32(PPC_PM_STOP); | |
3652 | gen_helper_pminsn(cpu_env, t); | |
3653 | tcg_temp_free_i32(t); | |
3654 | /* Stop translation, as the CPU is supposed to sleep from now */ | |
3655 | gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); | |
3656 | #endif /* defined(CONFIG_USER_ONLY) */ | |
cdee0e72 ND |
3657 | } |
3658 | ||
7778a575 BH |
3659 | static void gen_sleep(DisasContext *ctx) |
3660 | { | |
3661 | #if defined(CONFIG_USER_ONLY) | |
3662 | GEN_PRIV; | |
3663 | #else | |
3664 | TCGv_i32 t; | |
3665 | ||
3666 | CHK_HV; | |
3667 | t = tcg_const_i32(PPC_PM_SLEEP); | |
3668 | gen_helper_pminsn(cpu_env, t); | |
3669 | tcg_temp_free_i32(t); | |
154c69f2 BH |
3670 | /* Stop translation, as the CPU is supposed to sleep from now */ |
3671 | gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); | |
7778a575 BH |
3672 | #endif /* defined(CONFIG_USER_ONLY) */ |
3673 | } | |
3674 | ||
3675 | static void gen_rvwinkle(DisasContext *ctx) | |
3676 | { | |
3677 | #if defined(CONFIG_USER_ONLY) | |
3678 | GEN_PRIV; | |
3679 | #else | |
3680 | TCGv_i32 t; | |
3681 | ||
3682 | CHK_HV; | |
3683 | t = tcg_const_i32(PPC_PM_RVWINKLE); | |
3684 | gen_helper_pminsn(cpu_env, t); | |
3685 | tcg_temp_free_i32(t); | |
154c69f2 BH |
3686 | /* Stop translation, as the CPU is supposed to sleep from now */ |
3687 | gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); | |
7778a575 BH |
3688 | #endif /* defined(CONFIG_USER_ONLY) */ |
3689 | } | |
3690 | #endif /* #if defined(TARGET_PPC64) */ | |
3691 | ||
697ab892 DG |
3692 | static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) |
3693 | { | |
3694 | #if defined(TARGET_PPC64) | |
efe843d8 | 3695 | if (ctx->has_cfar) { |
697ab892 | 3696 | tcg_gen_movi_tl(cpu_cfar, nip); |
efe843d8 | 3697 | } |
697ab892 DG |
3698 | #endif |
3699 | } | |
3700 | ||
90aa39a1 SF |
3701 | static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) |
3702 | { | |
3703 | if (unlikely(ctx->singlestep_enabled)) { | |
3704 | return false; | |
3705 | } | |
3706 | ||
3707 | #ifndef CONFIG_USER_ONLY | |
b6bac4bc | 3708 | return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); |
90aa39a1 SF |
3709 | #else |
3710 | return true; | |
3711 | #endif | |
3712 | } | |
3713 | ||
0e3bf489 RK |
3714 | static void gen_lookup_and_goto_ptr(DisasContext *ctx) |
3715 | { | |
3716 | int sse = ctx->singlestep_enabled; | |
3717 | if (unlikely(sse)) { | |
3718 | if (sse & GDBSTUB_SINGLE_STEP) { | |
3719 | gen_debug_exception(ctx); | |
3720 | } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) { | |
e150ac89 RK |
3721 | uint32_t excp = gen_prep_dbgex(ctx); |
3722 | gen_exception(ctx, excp); | |
0e3bf489 RK |
3723 | } |
3724 | tcg_gen_exit_tb(NULL, 0); | |
3725 | } else { | |
3726 | tcg_gen_lookup_and_goto_ptr(); | |
3727 | } | |
3728 | } | |
3729 | ||
79aceca5 | 3730 | /*** Branch ***/ |
c4a2e3a9 | 3731 | static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) |
c1942362 | 3732 | { |
e0c8f9ce | 3733 | if (NARROW_MODE(ctx)) { |
a2ffb812 | 3734 | dest = (uint32_t) dest; |
e0c8f9ce | 3735 | } |
90aa39a1 | 3736 | if (use_goto_tb(ctx, dest)) { |
57fec1fe | 3737 | tcg_gen_goto_tb(n); |
a2ffb812 | 3738 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
07ea28b4 | 3739 | tcg_gen_exit_tb(ctx->base.tb, n); |
c1942362 | 3740 | } else { |
a2ffb812 | 3741 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
0e3bf489 | 3742 | gen_lookup_and_goto_ptr(ctx); |
c1942362 | 3743 | } |
c53be334 FB |
3744 | } |
3745 | ||
636aa200 | 3746 | static inline void gen_setlr(DisasContext *ctx, target_ulong nip) |
e1833e1f | 3747 | { |
e0c8f9ce RH |
3748 | if (NARROW_MODE(ctx)) { |
3749 | nip = (uint32_t)nip; | |
3750 | } | |
3751 | tcg_gen_movi_tl(cpu_lr, nip); | |
e1833e1f JM |
3752 | } |
3753 | ||
79aceca5 | 3754 | /* b ba bl bla */ |
99e300ef | 3755 | static void gen_b(DisasContext *ctx) |
79aceca5 | 3756 | { |
76a66253 | 3757 | target_ulong li, target; |
38a64f9d | 3758 | |
8cbcb4fa | 3759 | ctx->exception = POWERPC_EXCP_BRANCH; |
38a64f9d | 3760 | /* sign extend LI */ |
e0c8f9ce RH |
3761 | li = LI(ctx->opcode); |
3762 | li = (li ^ 0x02000000) - 0x02000000; | |
3763 | if (likely(AA(ctx->opcode) == 0)) { | |
b6bac4bc | 3764 | target = ctx->base.pc_next + li - 4; |
e0c8f9ce | 3765 | } else { |
9a64fbe4 | 3766 | target = li; |
e0c8f9ce RH |
3767 | } |
3768 | if (LK(ctx->opcode)) { | |
b6bac4bc | 3769 | gen_setlr(ctx, ctx->base.pc_next); |
e0c8f9ce | 3770 | } |
b6bac4bc | 3771 | gen_update_cfar(ctx, ctx->base.pc_next - 4); |
c1942362 | 3772 | gen_goto_tb(ctx, 0, target); |
79aceca5 FB |
3773 | } |
3774 | ||
e98a6e40 FB |
3775 | #define BCOND_IM 0 |
3776 | #define BCOND_LR 1 | |
3777 | #define BCOND_CTR 2 | |
52a4984d | 3778 | #define BCOND_TAR 3 |
e98a6e40 | 3779 | |
c4a2e3a9 | 3780 | static void gen_bcond(DisasContext *ctx, int type) |
d9bce9d9 | 3781 | { |
d9bce9d9 | 3782 | uint32_t bo = BO(ctx->opcode); |
42a268c2 | 3783 | TCGLabel *l1; |
a2ffb812 | 3784 | TCGv target; |
8cbcb4fa | 3785 | ctx->exception = POWERPC_EXCP_BRANCH; |
0e3bf489 | 3786 | |
52a4984d | 3787 | if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { |
a7812ae4 | 3788 | target = tcg_temp_local_new(); |
efe843d8 | 3789 | if (type == BCOND_CTR) { |
a2ffb812 | 3790 | tcg_gen_mov_tl(target, cpu_ctr); |
efe843d8 | 3791 | } else if (type == BCOND_TAR) { |
52a4984d | 3792 | gen_load_spr(target, SPR_TAR); |
efe843d8 | 3793 | } else { |
a2ffb812 | 3794 | tcg_gen_mov_tl(target, cpu_lr); |
efe843d8 | 3795 | } |
d2e9fd8f | 3796 | } else { |
f764718d | 3797 | target = NULL; |
e98a6e40 | 3798 | } |
efe843d8 | 3799 | if (LK(ctx->opcode)) { |
b6bac4bc | 3800 | gen_setlr(ctx, ctx->base.pc_next); |
efe843d8 | 3801 | } |
a2ffb812 AJ |
3802 | l1 = gen_new_label(); |
3803 | if ((bo & 0x4) == 0) { | |
3804 | /* Decrement and test CTR */ | |
a7812ae4 | 3805 | TCGv temp = tcg_temp_new(); |
fa200c95 GK |
3806 | |
3807 | if (type == BCOND_CTR) { | |
3808 | /* | |
3809 | * All ISAs up to v3 describe this form of bcctr as invalid but | |
3810 | * some processors, ie. 64-bit server processors compliant with | |
3811 | * arch 2.x, do implement a "test and decrement" logic instead, | |
15d68c5e GK |
3812 | * as described in their respective UMs. This logic involves CTR |
3813 | * to act as both the branch target and a counter, which makes | |
3814 | * it basically useless and thus never used in real code. | |
3815 | * | |
3816 | * This form was hence chosen to trigger extra micro-architectural | |
3817 | * side-effect on real HW needed for the Spectre v2 workaround. | |
3818 | * It is up to guests that implement such workaround, ie. linux, to | |
3819 | * use this form in a way it just triggers the side-effect without | |
3820 | * doing anything else harmful. | |
fa200c95 | 3821 | */ |
d0db7cad | 3822 | if (unlikely(!is_book3s_arch2x(ctx))) { |
fa200c95 GK |
3823 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
3824 | tcg_temp_free(temp); | |
3825 | tcg_temp_free(target); | |
3826 | return; | |
3827 | } | |
3828 | ||
3829 | if (NARROW_MODE(ctx)) { | |
3830 | tcg_gen_ext32u_tl(temp, cpu_ctr); | |
3831 | } else { | |
3832 | tcg_gen_mov_tl(temp, cpu_ctr); | |
3833 | } | |
3834 | if (bo & 0x2) { | |
3835 | tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); | |
3836 | } else { | |
3837 | tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); | |
3838 | } | |
3839 | tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); | |
a2ffb812 | 3840 | } else { |
fa200c95 GK |
3841 | tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); |
3842 | if (NARROW_MODE(ctx)) { | |
3843 | tcg_gen_ext32u_tl(temp, cpu_ctr); | |
3844 | } else { | |
3845 | tcg_gen_mov_tl(temp, cpu_ctr); | |
3846 | } | |
3847 | if (bo & 0x2) { | |
3848 | tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); | |
3849 | } else { | |
3850 | tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); | |
3851 | } | |
e98a6e40 | 3852 | } |
a7812ae4 | 3853 | tcg_temp_free(temp); |
a2ffb812 AJ |
3854 | } |
3855 | if ((bo & 0x10) == 0) { | |
3856 | /* Test CR */ | |
3857 | uint32_t bi = BI(ctx->opcode); | |
8f9fb7ac | 3858 | uint32_t mask = 0x08 >> (bi & 0x03); |
a7812ae4 | 3859 | TCGv_i32 temp = tcg_temp_new_i32(); |
a2ffb812 | 3860 | |
d9bce9d9 | 3861 | if (bo & 0x8) { |
a2ffb812 AJ |
3862 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
3863 | tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); | |
d9bce9d9 | 3864 | } else { |
a2ffb812 AJ |
3865 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
3866 | tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); | |
d9bce9d9 | 3867 | } |
a7812ae4 | 3868 | tcg_temp_free_i32(temp); |
d9bce9d9 | 3869 | } |
b6bac4bc | 3870 | gen_update_cfar(ctx, ctx->base.pc_next - 4); |
e98a6e40 | 3871 | if (type == BCOND_IM) { |
a2ffb812 AJ |
3872 | target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); |
3873 | if (likely(AA(ctx->opcode) == 0)) { | |
b6bac4bc | 3874 | gen_goto_tb(ctx, 0, ctx->base.pc_next + li - 4); |
a2ffb812 AJ |
3875 | } else { |
3876 | gen_goto_tb(ctx, 0, li); | |
3877 | } | |
e98a6e40 | 3878 | } else { |
e0c8f9ce | 3879 | if (NARROW_MODE(ctx)) { |
a2ffb812 | 3880 | tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); |
e0c8f9ce | 3881 | } else { |
a2ffb812 | 3882 | tcg_gen_andi_tl(cpu_nip, target, ~3); |
e0c8f9ce | 3883 | } |
0e3bf489 | 3884 | gen_lookup_and_goto_ptr(ctx); |
c80d1df5 AG |
3885 | tcg_temp_free(target); |
3886 | } | |
c4a2e3a9 | 3887 | if ((bo & 0x14) != 0x14) { |
0e3bf489 | 3888 | /* fallthrough case */ |
c4a2e3a9 | 3889 | gen_set_label(l1); |
b6bac4bc | 3890 | gen_goto_tb(ctx, 1, ctx->base.pc_next); |
c4a2e3a9 | 3891 | } |
e98a6e40 FB |
3892 | } |
3893 | ||
99e300ef | 3894 | static void gen_bc(DisasContext *ctx) |
3b46e624 | 3895 | { |
e98a6e40 FB |
3896 | gen_bcond(ctx, BCOND_IM); |
3897 | } | |
3898 | ||
99e300ef | 3899 | static void gen_bcctr(DisasContext *ctx) |
3b46e624 | 3900 | { |
e98a6e40 FB |
3901 | gen_bcond(ctx, BCOND_CTR); |
3902 | } | |
3903 | ||
99e300ef | 3904 | static void gen_bclr(DisasContext *ctx) |
3b46e624 | 3905 | { |
e98a6e40 FB |
3906 | gen_bcond(ctx, BCOND_LR); |
3907 | } | |
79aceca5 | 3908 | |
52a4984d TM |
3909 | static void gen_bctar(DisasContext *ctx) |
3910 | { | |
3911 | gen_bcond(ctx, BCOND_TAR); | |
3912 | } | |
3913 | ||
79aceca5 | 3914 | /*** Condition register logical ***/ |
e1571908 | 3915 | #define GEN_CRLOGIC(name, tcg_op, opc) \ |
efe843d8 | 3916 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 3917 | { \ |
fc0d441e JM |
3918 | uint8_t bitmask; \ |
3919 | int sh; \ | |
a7812ae4 | 3920 | TCGv_i32 t0, t1; \ |
fc0d441e | 3921 | sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ |
a7812ae4 | 3922 | t0 = tcg_temp_new_i32(); \ |
fc0d441e | 3923 | if (sh > 0) \ |
fea0c503 | 3924 | tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ |
fc0d441e | 3925 | else if (sh < 0) \ |
fea0c503 | 3926 | tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ |
e1571908 | 3927 | else \ |
fea0c503 | 3928 | tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ |
a7812ae4 | 3929 | t1 = tcg_temp_new_i32(); \ |
fc0d441e JM |
3930 | sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ |
3931 | if (sh > 0) \ | |
fea0c503 | 3932 | tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ |
fc0d441e | 3933 | else if (sh < 0) \ |
fea0c503 | 3934 | tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ |
e1571908 | 3935 | else \ |
fea0c503 AJ |
3936 | tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ |
3937 | tcg_op(t0, t0, t1); \ | |
8f9fb7ac | 3938 | bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ |
fea0c503 AJ |
3939 | tcg_gen_andi_i32(t0, t0, bitmask); \ |
3940 | tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ | |
3941 | tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ | |
a7812ae4 PB |
3942 | tcg_temp_free_i32(t0); \ |
3943 | tcg_temp_free_i32(t1); \ | |
79aceca5 FB |
3944 | } |
3945 | ||
3946 | /* crand */ | |
e1571908 | 3947 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); |
79aceca5 | 3948 | /* crandc */ |
e1571908 | 3949 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); |
79aceca5 | 3950 | /* creqv */ |
e1571908 | 3951 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); |
79aceca5 | 3952 | /* crnand */ |
e1571908 | 3953 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); |
79aceca5 | 3954 | /* crnor */ |
e1571908 | 3955 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); |
79aceca5 | 3956 | /* cror */ |
e1571908 | 3957 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); |
79aceca5 | 3958 | /* crorc */ |
e1571908 | 3959 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); |
79aceca5 | 3960 | /* crxor */ |
e1571908 | 3961 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); |
99e300ef | 3962 | |
54623277 | 3963 | /* mcrf */ |
99e300ef | 3964 | static void gen_mcrf(DisasContext *ctx) |
79aceca5 | 3965 | { |
47e4661c | 3966 | tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); |
79aceca5 FB |
3967 | } |
3968 | ||
3969 | /*** System linkage ***/ | |
99e300ef | 3970 | |
c47493f2 | 3971 | /* rfi (supervisor only) */ |
99e300ef | 3972 | static void gen_rfi(DisasContext *ctx) |
79aceca5 | 3973 | { |
9a64fbe4 | 3974 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 3975 | GEN_PRIV; |
9a64fbe4 | 3976 | #else |
efe843d8 DG |
3977 | /* |
3978 | * This instruction doesn't exist anymore on 64-bit server | |
6ca038c2 | 3979 | * processors compliant with arch 2.x |
a2e71b28 | 3980 | */ |
d0db7cad | 3981 | if (is_book3s_arch2x(ctx)) { |
6ca038c2 BH |
3982 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
3983 | return; | |
3984 | } | |
9a64fbe4 | 3985 | /* Restore CPU state */ |
9b2fadda | 3986 | CHK_SV; |
a59d628f MK |
3987 | if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { |
3988 | gen_io_start(); | |
3989 | } | |
b6bac4bc | 3990 | gen_update_cfar(ctx, ctx->base.pc_next - 4); |
e5f17ac6 | 3991 | gen_helper_rfi(cpu_env); |
e06fcd75 | 3992 | gen_sync_exception(ctx); |
9a64fbe4 | 3993 | #endif |
79aceca5 FB |
3994 | } |
3995 | ||
426613db | 3996 | #if defined(TARGET_PPC64) |
99e300ef | 3997 | static void gen_rfid(DisasContext *ctx) |
426613db JM |
3998 | { |
3999 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4000 | GEN_PRIV; |
426613db JM |
4001 | #else |
4002 | /* Restore CPU state */ | |
9b2fadda | 4003 | CHK_SV; |
a59d628f MK |
4004 | if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { |
4005 | gen_io_start(); | |
4006 | } | |
b6bac4bc | 4007 | gen_update_cfar(ctx, ctx->base.pc_next - 4); |
e5f17ac6 | 4008 | gen_helper_rfid(cpu_env); |
e06fcd75 | 4009 | gen_sync_exception(ctx); |
426613db JM |
4010 | #endif |
4011 | } | |
426613db | 4012 | |
99e300ef | 4013 | static void gen_hrfid(DisasContext *ctx) |
be147d08 JM |
4014 | { |
4015 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4016 | GEN_PRIV; |
be147d08 JM |
4017 | #else |
4018 | /* Restore CPU state */ | |
9b2fadda | 4019 | CHK_HV; |
e5f17ac6 | 4020 | gen_helper_hrfid(cpu_env); |
e06fcd75 | 4021 | gen_sync_exception(ctx); |
be147d08 JM |
4022 | #endif |
4023 | } | |
4024 | #endif | |
4025 | ||
79aceca5 | 4026 | /* sc */ |
417bf010 JM |
4027 | #if defined(CONFIG_USER_ONLY) |
4028 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER | |
4029 | #else | |
4030 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL | |
4031 | #endif | |
99e300ef | 4032 | static void gen_sc(DisasContext *ctx) |
79aceca5 | 4033 | { |
e1833e1f JM |
4034 | uint32_t lev; |
4035 | ||
4036 | lev = (ctx->opcode >> 5) & 0x7F; | |
e06fcd75 | 4037 | gen_exception_err(ctx, POWERPC_SYSCALL, lev); |
79aceca5 FB |
4038 | } |
4039 | ||
4040 | /*** Trap ***/ | |
99e300ef | 4041 | |
22b56ee5 BH |
4042 | /* Check for unconditional traps (always or never) */ |
4043 | static bool check_unconditional_trap(DisasContext *ctx) | |
4044 | { | |
4045 | /* Trap never */ | |
4046 | if (TO(ctx->opcode) == 0) { | |
4047 | return true; | |
4048 | } | |
4049 | /* Trap always */ | |
4050 | if (TO(ctx->opcode) == 31) { | |
4051 | gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); | |
4052 | return true; | |
4053 | } | |
4054 | return false; | |
4055 | } | |
4056 | ||
54623277 | 4057 | /* tw */ |
99e300ef | 4058 | static void gen_tw(DisasContext *ctx) |
79aceca5 | 4059 | { |
22b56ee5 BH |
4060 | TCGv_i32 t0; |
4061 | ||
4062 | if (check_unconditional_trap(ctx)) { | |
4063 | return; | |
4064 | } | |
4065 | t0 = tcg_const_i32(TO(ctx->opcode)); | |
e5f17ac6 BS |
4066 | gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
4067 | t0); | |
cab3bee2 | 4068 | tcg_temp_free_i32(t0); |
79aceca5 FB |
4069 | } |
4070 | ||
4071 | /* twi */ | |
99e300ef | 4072 | static void gen_twi(DisasContext *ctx) |
79aceca5 | 4073 | { |
22b56ee5 BH |
4074 | TCGv t0; |
4075 | TCGv_i32 t1; | |
4076 | ||
4077 | if (check_unconditional_trap(ctx)) { | |
4078 | return; | |
4079 | } | |
4080 | t0 = tcg_const_tl(SIMM(ctx->opcode)); | |
4081 | t1 = tcg_const_i32(TO(ctx->opcode)); | |
e5f17ac6 | 4082 | gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); |
cab3bee2 AJ |
4083 | tcg_temp_free(t0); |
4084 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
4085 | } |
4086 | ||
d9bce9d9 JM |
4087 | #if defined(TARGET_PPC64) |
4088 | /* td */ | |
99e300ef | 4089 | static void gen_td(DisasContext *ctx) |
d9bce9d9 | 4090 | { |
22b56ee5 BH |
4091 | TCGv_i32 t0; |
4092 | ||
4093 | if (check_unconditional_trap(ctx)) { | |
4094 | return; | |
4095 | } | |
4096 | t0 = tcg_const_i32(TO(ctx->opcode)); | |
e5f17ac6 BS |
4097 | gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
4098 | t0); | |
cab3bee2 | 4099 | tcg_temp_free_i32(t0); |
d9bce9d9 JM |
4100 | } |
4101 | ||
4102 | /* tdi */ | |
99e300ef | 4103 | static void gen_tdi(DisasContext *ctx) |
d9bce9d9 | 4104 | { |
22b56ee5 BH |
4105 | TCGv t0; |
4106 | TCGv_i32 t1; | |
4107 | ||
4108 | if (check_unconditional_trap(ctx)) { | |
4109 | return; | |
4110 | } | |
4111 | t0 = tcg_const_tl(SIMM(ctx->opcode)); | |
4112 | t1 = tcg_const_i32(TO(ctx->opcode)); | |
e5f17ac6 | 4113 | gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); |
cab3bee2 AJ |
4114 | tcg_temp_free(t0); |
4115 | tcg_temp_free_i32(t1); | |
d9bce9d9 JM |
4116 | } |
4117 | #endif | |
4118 | ||
79aceca5 | 4119 | /*** Processor control ***/ |
99e300ef | 4120 | |
dd09c361 | 4121 | static void gen_read_xer(DisasContext *ctx, TCGv dst) |
da91a00f RH |
4122 | { |
4123 | TCGv t0 = tcg_temp_new(); | |
4124 | TCGv t1 = tcg_temp_new(); | |
4125 | TCGv t2 = tcg_temp_new(); | |
4126 | tcg_gen_mov_tl(dst, cpu_xer); | |
4127 | tcg_gen_shli_tl(t0, cpu_so, XER_SO); | |
4128 | tcg_gen_shli_tl(t1, cpu_ov, XER_OV); | |
4129 | tcg_gen_shli_tl(t2, cpu_ca, XER_CA); | |
4130 | tcg_gen_or_tl(t0, t0, t1); | |
4131 | tcg_gen_or_tl(dst, dst, t2); | |
4132 | tcg_gen_or_tl(dst, dst, t0); | |
dd09c361 ND |
4133 | if (is_isa300(ctx)) { |
4134 | tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); | |
4135 | tcg_gen_or_tl(dst, dst, t0); | |
4136 | tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); | |
4137 | tcg_gen_or_tl(dst, dst, t0); | |
4138 | } | |
da91a00f RH |
4139 | tcg_temp_free(t0); |
4140 | tcg_temp_free(t1); | |
4141 | tcg_temp_free(t2); | |
4142 | } | |
4143 | ||
4144 | static void gen_write_xer(TCGv src) | |
4145 | { | |
dd09c361 | 4146 | /* Write all flags, while reading back check for isa300 */ |
da91a00f | 4147 | tcg_gen_andi_tl(cpu_xer, src, |
dd09c361 ND |
4148 | ~((1u << XER_SO) | |
4149 | (1u << XER_OV) | (1u << XER_OV32) | | |
4150 | (1u << XER_CA) | (1u << XER_CA32))); | |
4151 | tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); | |
4152 | tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); | |
1bd33d0d ND |
4153 | tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); |
4154 | tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); | |
4155 | tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); | |
da91a00f RH |
4156 | } |
4157 | ||
54623277 | 4158 | /* mcrxr */ |
99e300ef | 4159 | static void gen_mcrxr(DisasContext *ctx) |
79aceca5 | 4160 | { |
da91a00f RH |
4161 | TCGv_i32 t0 = tcg_temp_new_i32(); |
4162 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
4163 | TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; | |
4164 | ||
4165 | tcg_gen_trunc_tl_i32(t0, cpu_so); | |
4166 | tcg_gen_trunc_tl_i32(t1, cpu_ov); | |
4167 | tcg_gen_trunc_tl_i32(dst, cpu_ca); | |
294d1292 SB |
4168 | tcg_gen_shli_i32(t0, t0, 3); |
4169 | tcg_gen_shli_i32(t1, t1, 2); | |
4170 | tcg_gen_shli_i32(dst, dst, 1); | |
da91a00f RH |
4171 | tcg_gen_or_i32(dst, dst, t0); |
4172 | tcg_gen_or_i32(dst, dst, t1); | |
4173 | tcg_temp_free_i32(t0); | |
4174 | tcg_temp_free_i32(t1); | |
4175 | ||
4176 | tcg_gen_movi_tl(cpu_so, 0); | |
4177 | tcg_gen_movi_tl(cpu_ov, 0); | |
4178 | tcg_gen_movi_tl(cpu_ca, 0); | |
79aceca5 FB |
4179 | } |
4180 | ||
b63d0434 ND |
4181 | #ifdef TARGET_PPC64 |
4182 | /* mcrxrx */ | |
4183 | static void gen_mcrxrx(DisasContext *ctx) | |
4184 | { | |
4185 | TCGv t0 = tcg_temp_new(); | |
4186 | TCGv t1 = tcg_temp_new(); | |
4187 | TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; | |
4188 | ||
4189 | /* copy OV and OV32 */ | |
4190 | tcg_gen_shli_tl(t0, cpu_ov, 1); | |
4191 | tcg_gen_or_tl(t0, t0, cpu_ov32); | |
4192 | tcg_gen_shli_tl(t0, t0, 2); | |
4193 | /* copy CA and CA32 */ | |
4194 | tcg_gen_shli_tl(t1, cpu_ca, 1); | |
4195 | tcg_gen_or_tl(t1, t1, cpu_ca32); | |
4196 | tcg_gen_or_tl(t0, t0, t1); | |
4197 | tcg_gen_trunc_tl_i32(dst, t0); | |
4198 | tcg_temp_free(t0); | |
4199 | tcg_temp_free(t1); | |
4200 | } | |
4201 | #endif | |
4202 | ||
0cfe11ea | 4203 | /* mfcr mfocrf */ |
99e300ef | 4204 | static void gen_mfcr(DisasContext *ctx) |
79aceca5 | 4205 | { |
76a66253 | 4206 | uint32_t crm, crn; |
3b46e624 | 4207 | |
76a66253 JM |
4208 | if (likely(ctx->opcode & 0x00100000)) { |
4209 | crm = CRM(ctx->opcode); | |
8dd640e4 | 4210 | if (likely(crm && ((crm & (crm - 1)) == 0))) { |
efe843d8 | 4211 | crn = ctz32(crm); |
e1571908 | 4212 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); |
0497d2f4 AJ |
4213 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], |
4214 | cpu_gpr[rD(ctx->opcode)], crn * 4); | |
76a66253 | 4215 | } |
d9bce9d9 | 4216 | } else { |
651721b2 AJ |
4217 | TCGv_i32 t0 = tcg_temp_new_i32(); |
4218 | tcg_gen_mov_i32(t0, cpu_crf[0]); | |
4219 | tcg_gen_shli_i32(t0, t0, 4); | |
4220 | tcg_gen_or_i32(t0, t0, cpu_crf[1]); | |
4221 | tcg_gen_shli_i32(t0, t0, 4); | |
4222 | tcg_gen_or_i32(t0, t0, cpu_crf[2]); | |
4223 | tcg_gen_shli_i32(t0, t0, 4); | |
4224 | tcg_gen_or_i32(t0, t0, cpu_crf[3]); | |
4225 | tcg_gen_shli_i32(t0, t0, 4); | |
4226 | tcg_gen_or_i32(t0, t0, cpu_crf[4]); | |
4227 | tcg_gen_shli_i32(t0, t0, 4); | |
4228 | tcg_gen_or_i32(t0, t0, cpu_crf[5]); | |
4229 | tcg_gen_shli_i32(t0, t0, 4); | |
4230 | tcg_gen_or_i32(t0, t0, cpu_crf[6]); | |
4231 | tcg_gen_shli_i32(t0, t0, 4); | |
4232 | tcg_gen_or_i32(t0, t0, cpu_crf[7]); | |
4233 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
4234 | tcg_temp_free_i32(t0); | |
d9bce9d9 | 4235 | } |
79aceca5 FB |
4236 | } |
4237 | ||
4238 | /* mfmsr */ | |
99e300ef | 4239 | static void gen_mfmsr(DisasContext *ctx) |
79aceca5 | 4240 | { |
9b2fadda | 4241 | CHK_SV; |
6527f6ea | 4242 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); |
79aceca5 FB |
4243 | } |
4244 | ||
69b058c8 | 4245 | static void spr_noaccess(DisasContext *ctx, int gprn, int sprn) |
3fc6c082 | 4246 | { |
7b13448f | 4247 | #if 0 |
3fc6c082 FB |
4248 | sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); |
4249 | printf("ERROR: try to access SPR %d !\n", sprn); | |
7b13448f | 4250 | #endif |
3fc6c082 FB |
4251 | } |
4252 | #define SPR_NOACCESS (&spr_noaccess) | |
3fc6c082 | 4253 | |
79aceca5 | 4254 | /* mfspr */ |
636aa200 | 4255 | static inline void gen_op_mfspr(DisasContext *ctx) |
79aceca5 | 4256 | { |
69b058c8 | 4257 | void (*read_cb)(DisasContext *ctx, int gprn, int sprn); |
79aceca5 FB |
4258 | uint32_t sprn = SPR(ctx->opcode); |
4259 | ||
eb94268e BH |
4260 | #if defined(CONFIG_USER_ONLY) |
4261 | read_cb = ctx->spr_cb[sprn].uea_read; | |
4262 | #else | |
4263 | if (ctx->pr) { | |
4264 | read_cb = ctx->spr_cb[sprn].uea_read; | |
4265 | } else if (ctx->hv) { | |
be147d08 | 4266 | read_cb = ctx->spr_cb[sprn].hea_read; |
eb94268e | 4267 | } else { |
3fc6c082 | 4268 | read_cb = ctx->spr_cb[sprn].oea_read; |
eb94268e | 4269 | } |
9a64fbe4 | 4270 | #endif |
76a66253 JM |
4271 | if (likely(read_cb != NULL)) { |
4272 | if (likely(read_cb != SPR_NOACCESS)) { | |
45d827d2 | 4273 | (*read_cb)(ctx, rD(ctx->opcode), sprn); |
3fc6c082 FB |
4274 | } else { |
4275 | /* Privilege exception */ | |
efe843d8 DG |
4276 | /* |
4277 | * This is a hack to avoid warnings when running Linux: | |
9fceefa7 JM |
4278 | * this OS breaks the PowerPC virtualisation model, |
4279 | * allowing userland application to read the PVR | |
4280 | */ | |
4281 | if (sprn != SPR_PVR) { | |
31085338 TH |
4282 | qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " |
4283 | "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, | |
4284 | ctx->base.pc_next - 4); | |
f24e5695 | 4285 | } |
9b2fadda | 4286 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); |
79aceca5 | 4287 | } |
3fc6c082 | 4288 | } else { |
9b2fadda BH |
4289 | /* ISA 2.07 defines these as no-ops */ |
4290 | if ((ctx->insns_flags2 & PPC2_ISA207S) && | |
4291 | (sprn >= 808 && sprn <= 811)) { | |
4292 | /* This is a nop */ | |
4293 | return; | |
4294 | } | |
3fc6c082 | 4295 | /* Not defined */ |
31085338 TH |
4296 | qemu_log_mask(LOG_GUEST_ERROR, |
4297 | "Trying to read invalid spr %d (0x%03x) at " | |
4298 | TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4); | |
9b2fadda | 4299 | |
efe843d8 DG |
4300 | /* |
4301 | * The behaviour depends on MSR:PR and SPR# bit 0x10, it can | |
4302 | * generate a priv, a hv emu or a no-op | |
9b2fadda BH |
4303 | */ |
4304 | if (sprn & 0x10) { | |
4305 | if (ctx->pr) { | |
4306 | gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); | |
4307 | } | |
4308 | } else { | |
4309 | if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { | |
4310 | gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); | |
4311 | } | |
4d6a0680 | 4312 | } |
79aceca5 | 4313 | } |
79aceca5 FB |
4314 | } |
4315 | ||
99e300ef | 4316 | static void gen_mfspr(DisasContext *ctx) |
79aceca5 | 4317 | { |
3fc6c082 | 4318 | gen_op_mfspr(ctx); |
76a66253 | 4319 | } |
3fc6c082 FB |
4320 | |
4321 | /* mftb */ | |
99e300ef | 4322 | static void gen_mftb(DisasContext *ctx) |
3fc6c082 FB |
4323 | { |
4324 | gen_op_mfspr(ctx); | |
79aceca5 FB |
4325 | } |
4326 | ||
0cfe11ea | 4327 | /* mtcrf mtocrf*/ |
99e300ef | 4328 | static void gen_mtcrf(DisasContext *ctx) |
79aceca5 | 4329 | { |
76a66253 | 4330 | uint32_t crm, crn; |
3b46e624 | 4331 | |
76a66253 | 4332 | crm = CRM(ctx->opcode); |
8dd640e4 | 4333 | if (likely((ctx->opcode & 0x00100000))) { |
4334 | if (crm && ((crm & (crm - 1)) == 0)) { | |
4335 | TCGv_i32 temp = tcg_temp_new_i32(); | |
efe843d8 | 4336 | crn = ctz32(crm); |
8dd640e4 | 4337 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); |
0cfe11ea AJ |
4338 | tcg_gen_shri_i32(temp, temp, crn * 4); |
4339 | tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); | |
8dd640e4 | 4340 | tcg_temp_free_i32(temp); |
4341 | } | |
76a66253 | 4342 | } else { |
651721b2 AJ |
4343 | TCGv_i32 temp = tcg_temp_new_i32(); |
4344 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); | |
4345 | for (crn = 0 ; crn < 8 ; crn++) { | |
4346 | if (crm & (1 << crn)) { | |
4347 | tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); | |
4348 | tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); | |
4349 | } | |
4350 | } | |
a7812ae4 | 4351 | tcg_temp_free_i32(temp); |
76a66253 | 4352 | } |
79aceca5 FB |
4353 | } |
4354 | ||
4355 | /* mtmsr */ | |
426613db | 4356 | #if defined(TARGET_PPC64) |
99e300ef | 4357 | static void gen_mtmsrd(DisasContext *ctx) |
426613db | 4358 | { |
9b2fadda BH |
4359 | CHK_SV; |
4360 | ||
4361 | #if !defined(CONFIG_USER_ONLY) | |
be147d08 JM |
4362 | if (ctx->opcode & 0x00010000) { |
4363 | /* Special form that does not need any synchronisation */ | |
6527f6ea | 4364 | TCGv t0 = tcg_temp_new(); |
efe843d8 DG |
4365 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], |
4366 | (1 << MSR_RI) | (1 << MSR_EE)); | |
4367 | tcg_gen_andi_tl(cpu_msr, cpu_msr, | |
4368 | ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); | |
6527f6ea AJ |
4369 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); |
4370 | tcg_temp_free(t0); | |
be147d08 | 4371 | } else { |
efe843d8 DG |
4372 | /* |
4373 | * XXX: we need to update nip before the store if we enter | |
4374 | * power saving mode, we will exit the loop directly from | |
4375 | * ppc_store_msr | |
056b05f8 | 4376 | */ |
b8edea50 PD |
4377 | if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { |
4378 | gen_io_start(); | |
4379 | } | |
b6bac4bc | 4380 | gen_update_nip(ctx, ctx->base.pc_next); |
e5f17ac6 | 4381 | gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); |
be147d08 JM |
4382 | /* Must stop the translation as machine state (may have) changed */ |
4383 | /* Note that mtmsr is not always defined as context-synchronizing */ | |
e06fcd75 | 4384 | gen_stop_exception(ctx); |
be147d08 | 4385 | } |
9b2fadda | 4386 | #endif /* !defined(CONFIG_USER_ONLY) */ |
426613db | 4387 | } |
9b2fadda | 4388 | #endif /* defined(TARGET_PPC64) */ |
426613db | 4389 | |
99e300ef | 4390 | static void gen_mtmsr(DisasContext *ctx) |
79aceca5 | 4391 | { |
9b2fadda BH |
4392 | CHK_SV; |
4393 | ||
4394 | #if !defined(CONFIG_USER_ONLY) | |
4395 | if (ctx->opcode & 0x00010000) { | |
be147d08 | 4396 | /* Special form that does not need any synchronisation */ |
6527f6ea | 4397 | TCGv t0 = tcg_temp_new(); |
efe843d8 DG |
4398 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], |
4399 | (1 << MSR_RI) | (1 << MSR_EE)); | |
4400 | tcg_gen_andi_tl(cpu_msr, cpu_msr, | |
4401 | ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); | |
6527f6ea AJ |
4402 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); |
4403 | tcg_temp_free(t0); | |
be147d08 | 4404 | } else { |
8018dc63 AG |
4405 | TCGv msr = tcg_temp_new(); |
4406 | ||
efe843d8 DG |
4407 | /* |
4408 | * XXX: we need to update nip before the store if we enter | |
4409 | * power saving mode, we will exit the loop directly from | |
4410 | * ppc_store_msr | |
056b05f8 | 4411 | */ |
b8edea50 PD |
4412 | if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { |
4413 | gen_io_start(); | |
4414 | } | |
b6bac4bc | 4415 | gen_update_nip(ctx, ctx->base.pc_next); |
d9bce9d9 | 4416 | #if defined(TARGET_PPC64) |
8018dc63 AG |
4417 | tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); |
4418 | #else | |
4419 | tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); | |
d9bce9d9 | 4420 | #endif |
e5f17ac6 | 4421 | gen_helper_store_msr(cpu_env, msr); |
c80d1df5 | 4422 | tcg_temp_free(msr); |
be147d08 | 4423 | /* Must stop the translation as machine state (may have) changed */ |
6527f6ea | 4424 | /* Note that mtmsr is not always defined as context-synchronizing */ |
e06fcd75 | 4425 | gen_stop_exception(ctx); |
be147d08 | 4426 | } |
9a64fbe4 | 4427 | #endif |
79aceca5 FB |
4428 | } |
4429 | ||
4430 | /* mtspr */ | |
99e300ef | 4431 | static void gen_mtspr(DisasContext *ctx) |
79aceca5 | 4432 | { |
69b058c8 | 4433 | void (*write_cb)(DisasContext *ctx, int sprn, int gprn); |
79aceca5 FB |
4434 | uint32_t sprn = SPR(ctx->opcode); |
4435 | ||
eb94268e BH |
4436 | #if defined(CONFIG_USER_ONLY) |
4437 | write_cb = ctx->spr_cb[sprn].uea_write; | |
4438 | #else | |
4439 | if (ctx->pr) { | |
4440 | write_cb = ctx->spr_cb[sprn].uea_write; | |
4441 | } else if (ctx->hv) { | |
be147d08 | 4442 | write_cb = ctx->spr_cb[sprn].hea_write; |
eb94268e | 4443 | } else { |
3fc6c082 | 4444 | write_cb = ctx->spr_cb[sprn].oea_write; |
eb94268e | 4445 | } |
9a64fbe4 | 4446 | #endif |
76a66253 JM |
4447 | if (likely(write_cb != NULL)) { |
4448 | if (likely(write_cb != SPR_NOACCESS)) { | |
45d827d2 | 4449 | (*write_cb)(ctx, sprn, rS(ctx->opcode)); |
3fc6c082 FB |
4450 | } else { |
4451 | /* Privilege exception */ | |
31085338 TH |
4452 | qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " |
4453 | "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, | |
4454 | ctx->base.pc_next - 4); | |
9b2fadda | 4455 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 4456 | } |
3fc6c082 | 4457 | } else { |
9b2fadda BH |
4458 | /* ISA 2.07 defines these as no-ops */ |
4459 | if ((ctx->insns_flags2 & PPC2_ISA207S) && | |
4460 | (sprn >= 808 && sprn <= 811)) { | |
4461 | /* This is a nop */ | |
4462 | return; | |
4463 | } | |
4464 | ||
3fc6c082 | 4465 | /* Not defined */ |
31085338 TH |
4466 | qemu_log_mask(LOG_GUEST_ERROR, |
4467 | "Trying to write invalid spr %d (0x%03x) at " | |
4468 | TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4); | |
4d6a0680 | 4469 | |
9b2fadda | 4470 | |
efe843d8 DG |
4471 | /* |
4472 | * The behaviour depends on MSR:PR and SPR# bit 0x10, it can | |
4473 | * generate a priv, a hv emu or a no-op | |
9b2fadda BH |
4474 | */ |
4475 | if (sprn & 0x10) { | |
4476 | if (ctx->pr) { | |
4477 | gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); | |
4478 | } | |
4479 | } else { | |
4480 | if (ctx->pr || sprn == 0) { | |
4481 | gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); | |
4482 | } | |
4d6a0680 | 4483 | } |
79aceca5 | 4484 | } |
79aceca5 FB |
4485 | } |
4486 | ||
dc2ee038 VAS |
4487 | #if defined(TARGET_PPC64) |
4488 | /* setb */ | |
4489 | static void gen_setb(DisasContext *ctx) | |
4490 | { | |
4491 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
4492 | TCGv_i32 t8 = tcg_temp_new_i32(); | |
4493 | TCGv_i32 tm1 = tcg_temp_new_i32(); | |
4494 | int crf = crfS(ctx->opcode); | |
4495 | ||
4496 | tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); | |
4497 | tcg_gen_movi_i32(t8, 8); | |
4498 | tcg_gen_movi_i32(tm1, -1); | |
4499 | tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); | |
4500 | tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
4501 | ||
4502 | tcg_temp_free_i32(t0); | |
4503 | tcg_temp_free_i32(t8); | |
4504 | tcg_temp_free_i32(tm1); | |
4505 | } | |
4506 | #endif | |
4507 | ||
79aceca5 | 4508 | /*** Cache management ***/ |
99e300ef | 4509 | |
54623277 | 4510 | /* dcbf */ |
99e300ef | 4511 | static void gen_dcbf(DisasContext *ctx) |
79aceca5 | 4512 | { |
dac454af | 4513 | /* XXX: specification says this is treated as a load by the MMU */ |
76db3ba4 AJ |
4514 | TCGv t0; |
4515 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4516 | t0 = tcg_temp_new(); | |
4517 | gen_addr_reg_index(ctx, t0); | |
4518 | gen_qemu_ld8u(ctx, t0, t0); | |
fea0c503 | 4519 | tcg_temp_free(t0); |
79aceca5 FB |
4520 | } |
4521 | ||
50728199 RK |
4522 | /* dcbfep (external PID dcbf) */ |
4523 | static void gen_dcbfep(DisasContext *ctx) | |
4524 | { | |
4525 | /* XXX: specification says this is treated as a load by the MMU */ | |
4526 | TCGv t0; | |
4527 | CHK_SV; | |
4528 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4529 | t0 = tcg_temp_new(); | |
4530 | gen_addr_reg_index(ctx, t0); | |
4531 | tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); | |
4532 | tcg_temp_free(t0); | |
4533 | } | |
4534 | ||
79aceca5 | 4535 | /* dcbi (Supervisor only) */ |
99e300ef | 4536 | static void gen_dcbi(DisasContext *ctx) |
79aceca5 | 4537 | { |
a541f297 | 4538 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4539 | GEN_PRIV; |
a541f297 | 4540 | #else |
b61f2753 | 4541 | TCGv EA, val; |
9b2fadda BH |
4542 | |
4543 | CHK_SV; | |
a7812ae4 | 4544 | EA = tcg_temp_new(); |
76db3ba4 AJ |
4545 | gen_set_access_type(ctx, ACCESS_CACHE); |
4546 | gen_addr_reg_index(ctx, EA); | |
a7812ae4 | 4547 | val = tcg_temp_new(); |
76a66253 | 4548 | /* XXX: specification says this should be treated as a store by the MMU */ |
76db3ba4 AJ |
4549 | gen_qemu_ld8u(ctx, val, EA); |
4550 | gen_qemu_st8(ctx, val, EA); | |
b61f2753 AJ |
4551 | tcg_temp_free(val); |
4552 | tcg_temp_free(EA); | |
9b2fadda | 4553 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4554 | } |
4555 | ||
4556 | /* dcdst */ | |
99e300ef | 4557 | static void gen_dcbst(DisasContext *ctx) |
79aceca5 | 4558 | { |
76a66253 | 4559 | /* XXX: specification say this is treated as a load by the MMU */ |
76db3ba4 AJ |
4560 | TCGv t0; |
4561 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4562 | t0 = tcg_temp_new(); | |
4563 | gen_addr_reg_index(ctx, t0); | |
4564 | gen_qemu_ld8u(ctx, t0, t0); | |
fea0c503 | 4565 | tcg_temp_free(t0); |
79aceca5 FB |
4566 | } |
4567 | ||
50728199 RK |
4568 | /* dcbstep (dcbstep External PID version) */ |
4569 | static void gen_dcbstep(DisasContext *ctx) | |
4570 | { | |
4571 | /* XXX: specification say this is treated as a load by the MMU */ | |
4572 | TCGv t0; | |
4573 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4574 | t0 = tcg_temp_new(); | |
4575 | gen_addr_reg_index(ctx, t0); | |
4576 | tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); | |
4577 | tcg_temp_free(t0); | |
4578 | } | |
4579 | ||
79aceca5 | 4580 | /* dcbt */ |
99e300ef | 4581 | static void gen_dcbt(DisasContext *ctx) |
79aceca5 | 4582 | { |
efe843d8 DG |
4583 | /* |
4584 | * interpreted as no-op | |
4585 | * XXX: specification say this is treated as a load by the MMU but | |
4586 | * does not generate any exception | |
76a66253 | 4587 | */ |
79aceca5 FB |
4588 | } |
4589 | ||
50728199 RK |
4590 | /* dcbtep */ |
4591 | static void gen_dcbtep(DisasContext *ctx) | |
4592 | { | |
efe843d8 DG |
4593 | /* |
4594 | * interpreted as no-op | |
4595 | * XXX: specification say this is treated as a load by the MMU but | |
4596 | * does not generate any exception | |
50728199 RK |
4597 | */ |
4598 | } | |
4599 | ||
79aceca5 | 4600 | /* dcbtst */ |
99e300ef | 4601 | static void gen_dcbtst(DisasContext *ctx) |
79aceca5 | 4602 | { |
efe843d8 DG |
4603 | /* |
4604 | * interpreted as no-op | |
4605 | * XXX: specification say this is treated as a load by the MMU but | |
4606 | * does not generate any exception | |
76a66253 | 4607 | */ |
79aceca5 FB |
4608 | } |
4609 | ||
50728199 RK |
4610 | /* dcbtstep */ |
4611 | static void gen_dcbtstep(DisasContext *ctx) | |
4612 | { | |
efe843d8 DG |
4613 | /* |
4614 | * interpreted as no-op | |
4615 | * XXX: specification say this is treated as a load by the MMU but | |
4616 | * does not generate any exception | |
50728199 RK |
4617 | */ |
4618 | } | |
4619 | ||
4d09d529 AG |
4620 | /* dcbtls */ |
4621 | static void gen_dcbtls(DisasContext *ctx) | |
4622 | { | |
4623 | /* Always fails locking the cache */ | |
4624 | TCGv t0 = tcg_temp_new(); | |
4625 | gen_load_spr(t0, SPR_Exxx_L1CSR0); | |
4626 | tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); | |
4627 | gen_store_spr(SPR_Exxx_L1CSR0, t0); | |
4628 | tcg_temp_free(t0); | |
4629 | } | |
4630 | ||
79aceca5 | 4631 | /* dcbz */ |
99e300ef | 4632 | static void gen_dcbz(DisasContext *ctx) |
79aceca5 | 4633 | { |
8e33944f | 4634 | TCGv tcgv_addr; |
c9f82d01 | 4635 | TCGv_i32 tcgv_op; |
d63001d1 | 4636 | |
76db3ba4 | 4637 | gen_set_access_type(ctx, ACCESS_CACHE); |
8e33944f | 4638 | tcgv_addr = tcg_temp_new(); |
c9f82d01 | 4639 | tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); |
8e33944f | 4640 | gen_addr_reg_index(ctx, tcgv_addr); |
c9f82d01 | 4641 | gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); |
8e33944f | 4642 | tcg_temp_free(tcgv_addr); |
c9f82d01 | 4643 | tcg_temp_free_i32(tcgv_op); |
79aceca5 FB |
4644 | } |
4645 | ||
50728199 RK |
4646 | /* dcbzep */ |
4647 | static void gen_dcbzep(DisasContext *ctx) | |
4648 | { | |
4649 | TCGv tcgv_addr; | |
4650 | TCGv_i32 tcgv_op; | |
4651 | ||
4652 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4653 | tcgv_addr = tcg_temp_new(); | |
4654 | tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); | |
4655 | gen_addr_reg_index(ctx, tcgv_addr); | |
4656 | gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); | |
4657 | tcg_temp_free(tcgv_addr); | |
4658 | tcg_temp_free_i32(tcgv_op); | |
4659 | } | |
4660 | ||
ae1c1a3d | 4661 | /* dst / dstt */ |
99e300ef | 4662 | static void gen_dst(DisasContext *ctx) |
ae1c1a3d AJ |
4663 | { |
4664 | if (rA(ctx->opcode) == 0) { | |
e41029b3 | 4665 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
ae1c1a3d AJ |
4666 | } else { |
4667 | /* interpreted as no-op */ | |
4668 | } | |
4669 | } | |
4670 | ||
4671 | /* dstst /dststt */ | |
99e300ef | 4672 | static void gen_dstst(DisasContext *ctx) |
ae1c1a3d AJ |
4673 | { |
4674 | if (rA(ctx->opcode) == 0) { | |
e41029b3 | 4675 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
ae1c1a3d AJ |
4676 | } else { |
4677 | /* interpreted as no-op */ | |
4678 | } | |
4679 | ||
4680 | } | |
4681 | ||
4682 | /* dss / dssall */ | |
99e300ef | 4683 | static void gen_dss(DisasContext *ctx) |
ae1c1a3d AJ |
4684 | { |
4685 | /* interpreted as no-op */ | |
4686 | } | |
4687 | ||
79aceca5 | 4688 | /* icbi */ |
99e300ef | 4689 | static void gen_icbi(DisasContext *ctx) |
79aceca5 | 4690 | { |
76db3ba4 AJ |
4691 | TCGv t0; |
4692 | gen_set_access_type(ctx, ACCESS_CACHE); | |
76db3ba4 AJ |
4693 | t0 = tcg_temp_new(); |
4694 | gen_addr_reg_index(ctx, t0); | |
2f5a189c | 4695 | gen_helper_icbi(cpu_env, t0); |
37d269df | 4696 | tcg_temp_free(t0); |
79aceca5 FB |
4697 | } |
4698 | ||
50728199 RK |
4699 | /* icbiep */ |
4700 | static void gen_icbiep(DisasContext *ctx) | |
4701 | { | |
4702 | TCGv t0; | |
4703 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4704 | t0 = tcg_temp_new(); | |
4705 | gen_addr_reg_index(ctx, t0); | |
4706 | gen_helper_icbiep(cpu_env, t0); | |
4707 | tcg_temp_free(t0); | |
4708 | } | |
4709 | ||
79aceca5 FB |
4710 | /* Optional: */ |
4711 | /* dcba */ | |
99e300ef | 4712 | static void gen_dcba(DisasContext *ctx) |
79aceca5 | 4713 | { |
efe843d8 DG |
4714 | /* |
4715 | * interpreted as no-op | |
4716 | * XXX: specification say this is treated as a store by the MMU | |
0db1b20e JM |
4717 | * but does not generate any exception |
4718 | */ | |
79aceca5 FB |
4719 | } |
4720 | ||
4721 | /*** Segment register manipulation ***/ | |
4722 | /* Supervisor only: */ | |
99e300ef | 4723 | |
54623277 | 4724 | /* mfsr */ |
99e300ef | 4725 | static void gen_mfsr(DisasContext *ctx) |
79aceca5 | 4726 | { |
9a64fbe4 | 4727 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4728 | GEN_PRIV; |
9a64fbe4 | 4729 | #else |
74d37793 | 4730 | TCGv t0; |
9b2fadda BH |
4731 | |
4732 | CHK_SV; | |
74d37793 | 4733 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4734 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4735 | tcg_temp_free(t0); |
9b2fadda | 4736 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4737 | } |
4738 | ||
4739 | /* mfsrin */ | |
99e300ef | 4740 | static void gen_mfsrin(DisasContext *ctx) |
79aceca5 | 4741 | { |
9a64fbe4 | 4742 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4743 | GEN_PRIV; |
9a64fbe4 | 4744 | #else |
74d37793 | 4745 | TCGv t0; |
9b2fadda BH |
4746 | |
4747 | CHK_SV; | |
74d37793 | 4748 | t0 = tcg_temp_new(); |
e2622073 | 4749 | tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); |
c6c7cf05 | 4750 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4751 | tcg_temp_free(t0); |
9b2fadda | 4752 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4753 | } |
4754 | ||
4755 | /* mtsr */ | |
99e300ef | 4756 | static void gen_mtsr(DisasContext *ctx) |
79aceca5 | 4757 | { |
9a64fbe4 | 4758 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4759 | GEN_PRIV; |
9a64fbe4 | 4760 | #else |
74d37793 | 4761 | TCGv t0; |
9b2fadda BH |
4762 | |
4763 | CHK_SV; | |
74d37793 | 4764 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4765 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4766 | tcg_temp_free(t0); |
9b2fadda | 4767 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4768 | } |
4769 | ||
4770 | /* mtsrin */ | |
99e300ef | 4771 | static void gen_mtsrin(DisasContext *ctx) |
79aceca5 | 4772 | { |
9a64fbe4 | 4773 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4774 | GEN_PRIV; |
9a64fbe4 | 4775 | #else |
74d37793 | 4776 | TCGv t0; |
9b2fadda BH |
4777 | CHK_SV; |
4778 | ||
74d37793 | 4779 | t0 = tcg_temp_new(); |
e2622073 | 4780 | tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); |
c6c7cf05 | 4781 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); |
74d37793 | 4782 | tcg_temp_free(t0); |
9b2fadda | 4783 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4784 | } |
4785 | ||
12de9a39 JM |
4786 | #if defined(TARGET_PPC64) |
4787 | /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ | |
e8eaa2c0 | 4788 | |
54623277 | 4789 | /* mfsr */ |
e8eaa2c0 | 4790 | static void gen_mfsr_64b(DisasContext *ctx) |
12de9a39 JM |
4791 | { |
4792 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4793 | GEN_PRIV; |
12de9a39 | 4794 | #else |
74d37793 | 4795 | TCGv t0; |
9b2fadda BH |
4796 | |
4797 | CHK_SV; | |
74d37793 | 4798 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4799 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4800 | tcg_temp_free(t0); |
9b2fadda | 4801 | #endif /* defined(CONFIG_USER_ONLY) */ |
12de9a39 JM |
4802 | } |
4803 | ||
4804 | /* mfsrin */ | |
e8eaa2c0 | 4805 | static void gen_mfsrin_64b(DisasContext *ctx) |
12de9a39 JM |
4806 | { |
4807 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4808 | GEN_PRIV; |
12de9a39 | 4809 | #else |
74d37793 | 4810 | TCGv t0; |
9b2fadda BH |
4811 | |
4812 | CHK_SV; | |
74d37793 | 4813 | t0 = tcg_temp_new(); |
e2622073 | 4814 | tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); |
c6c7cf05 | 4815 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4816 | tcg_temp_free(t0); |
9b2fadda | 4817 | #endif /* defined(CONFIG_USER_ONLY) */ |
12de9a39 JM |
4818 | } |
4819 | ||
4820 | /* mtsr */ | |
e8eaa2c0 | 4821 | static void gen_mtsr_64b(DisasContext *ctx) |
12de9a39 JM |
4822 | { |
4823 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4824 | GEN_PRIV; |
12de9a39 | 4825 | #else |
74d37793 | 4826 | TCGv t0; |
9b2fadda BH |
4827 | |
4828 | CHK_SV; | |
74d37793 | 4829 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4830 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4831 | tcg_temp_free(t0); |
9b2fadda | 4832 | #endif /* defined(CONFIG_USER_ONLY) */ |
12de9a39 JM |
4833 | } |
4834 | ||
4835 | /* mtsrin */ | |
e8eaa2c0 | 4836 | static void gen_mtsrin_64b(DisasContext *ctx) |
12de9a39 JM |
4837 | { |
4838 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4839 | GEN_PRIV; |
12de9a39 | 4840 | #else |
74d37793 | 4841 | TCGv t0; |
9b2fadda BH |
4842 | |
4843 | CHK_SV; | |
74d37793 | 4844 | t0 = tcg_temp_new(); |
e2622073 | 4845 | tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); |
c6c7cf05 | 4846 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4847 | tcg_temp_free(t0); |
9b2fadda | 4848 | #endif /* defined(CONFIG_USER_ONLY) */ |
12de9a39 | 4849 | } |
f6b868fc BS |
4850 | |
4851 | /* slbmte */ | |
e8eaa2c0 | 4852 | static void gen_slbmte(DisasContext *ctx) |
f6b868fc BS |
4853 | { |
4854 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4855 | GEN_PRIV; |
f6b868fc | 4856 | #else |
9b2fadda BH |
4857 | CHK_SV; |
4858 | ||
c6c7cf05 BS |
4859 | gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], |
4860 | cpu_gpr[rS(ctx->opcode)]); | |
9b2fadda | 4861 | #endif /* defined(CONFIG_USER_ONLY) */ |
f6b868fc BS |
4862 | } |
4863 | ||
efdef95f DG |
4864 | static void gen_slbmfee(DisasContext *ctx) |
4865 | { | |
4866 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4867 | GEN_PRIV; |
efdef95f | 4868 | #else |
9b2fadda BH |
4869 | CHK_SV; |
4870 | ||
c6c7cf05 | 4871 | gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, |
efdef95f | 4872 | cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 4873 | #endif /* defined(CONFIG_USER_ONLY) */ |
efdef95f DG |
4874 | } |
4875 | ||
4876 | static void gen_slbmfev(DisasContext *ctx) | |
4877 | { | |
4878 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4879 | GEN_PRIV; |
efdef95f | 4880 | #else |
9b2fadda BH |
4881 | CHK_SV; |
4882 | ||
c6c7cf05 | 4883 | gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, |
efdef95f | 4884 | cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 4885 | #endif /* defined(CONFIG_USER_ONLY) */ |
efdef95f | 4886 | } |
c76c22d5 BH |
4887 | |
4888 | static void gen_slbfee_(DisasContext *ctx) | |
4889 | { | |
4890 | #if defined(CONFIG_USER_ONLY) | |
4891 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4892 | #else | |
4893 | TCGLabel *l1, *l2; | |
4894 | ||
4895 | if (unlikely(ctx->pr)) { | |
4896 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4897 | return; | |
4898 | } | |
4899 | gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, | |
4900 | cpu_gpr[rB(ctx->opcode)]); | |
4901 | l1 = gen_new_label(); | |
4902 | l2 = gen_new_label(); | |
4903 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); | |
4904 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); | |
efa73196 | 4905 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); |
c76c22d5 BH |
4906 | tcg_gen_br(l2); |
4907 | gen_set_label(l1); | |
4908 | tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); | |
4909 | gen_set_label(l2); | |
4910 | #endif | |
4911 | } | |
12de9a39 JM |
4912 | #endif /* defined(TARGET_PPC64) */ |
4913 | ||
79aceca5 | 4914 | /*** Lookaside buffer management ***/ |
c47493f2 | 4915 | /* Optional & supervisor only: */ |
99e300ef | 4916 | |
54623277 | 4917 | /* tlbia */ |
99e300ef | 4918 | static void gen_tlbia(DisasContext *ctx) |
79aceca5 | 4919 | { |
9a64fbe4 | 4920 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4921 | GEN_PRIV; |
9a64fbe4 | 4922 | #else |
9b2fadda BH |
4923 | CHK_HV; |
4924 | ||
c6c7cf05 | 4925 | gen_helper_tlbia(cpu_env); |
9b2fadda | 4926 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4927 | } |
4928 | ||
bf14b1ce | 4929 | /* tlbiel */ |
99e300ef | 4930 | static void gen_tlbiel(DisasContext *ctx) |
bf14b1ce BS |
4931 | { |
4932 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4933 | GEN_PRIV; |
bf14b1ce | 4934 | #else |
9b2fadda BH |
4935 | CHK_SV; |
4936 | ||
c6c7cf05 | 4937 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 4938 | #endif /* defined(CONFIG_USER_ONLY) */ |
bf14b1ce BS |
4939 | } |
4940 | ||
79aceca5 | 4941 | /* tlbie */ |
99e300ef | 4942 | static void gen_tlbie(DisasContext *ctx) |
79aceca5 | 4943 | { |
9a64fbe4 | 4944 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4945 | GEN_PRIV; |
9a64fbe4 | 4946 | #else |
d76ab5e1 | 4947 | TCGv_i32 t1; |
c6fd28fd SJS |
4948 | |
4949 | if (ctx->gtse) { | |
91c60f12 | 4950 | CHK_SV; /* If gtse is set then tlbie is supervisor privileged */ |
c6fd28fd SJS |
4951 | } else { |
4952 | CHK_HV; /* Else hypervisor privileged */ | |
4953 | } | |
9b2fadda | 4954 | |
9ca3f7f3 | 4955 | if (NARROW_MODE(ctx)) { |
74d37793 AJ |
4956 | TCGv t0 = tcg_temp_new(); |
4957 | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); | |
c6c7cf05 | 4958 | gen_helper_tlbie(cpu_env, t0); |
74d37793 | 4959 | tcg_temp_free(t0); |
9ca3f7f3 | 4960 | } else { |
c6c7cf05 | 4961 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9ca3f7f3 | 4962 | } |
d76ab5e1 ND |
4963 | t1 = tcg_temp_new_i32(); |
4964 | tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); | |
4965 | tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); | |
4966 | tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); | |
4967 | tcg_temp_free_i32(t1); | |
9b2fadda | 4968 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4969 | } |
4970 | ||
4971 | /* tlbsync */ | |
99e300ef | 4972 | static void gen_tlbsync(DisasContext *ctx) |
79aceca5 | 4973 | { |
9a64fbe4 | 4974 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4975 | GEN_PRIV; |
9a64fbe4 | 4976 | #else |
91c60f12 CLG |
4977 | |
4978 | if (ctx->gtse) { | |
4979 | CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */ | |
4980 | } else { | |
4981 | CHK_HV; /* Else hypervisor privileged */ | |
4982 | } | |
9b2fadda | 4983 | |
e3cffe6f ND |
4984 | /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ |
4985 | if (ctx->insns_flags & PPC_BOOKE) { | |
4986 | gen_check_tlb_flush(ctx, true); | |
4987 | } | |
9b2fadda | 4988 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4989 | } |
4990 | ||
426613db JM |
4991 | #if defined(TARGET_PPC64) |
4992 | /* slbia */ | |
99e300ef | 4993 | static void gen_slbia(DisasContext *ctx) |
426613db JM |
4994 | { |
4995 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4996 | GEN_PRIV; |
426613db | 4997 | #else |
9b2fadda BH |
4998 | CHK_SV; |
4999 | ||
c6c7cf05 | 5000 | gen_helper_slbia(cpu_env); |
9b2fadda | 5001 | #endif /* defined(CONFIG_USER_ONLY) */ |
426613db JM |
5002 | } |
5003 | ||
5004 | /* slbie */ | |
99e300ef | 5005 | static void gen_slbie(DisasContext *ctx) |
426613db JM |
5006 | { |
5007 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5008 | GEN_PRIV; |
426613db | 5009 | #else |
9b2fadda BH |
5010 | CHK_SV; |
5011 | ||
c6c7cf05 | 5012 | gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 5013 | #endif /* defined(CONFIG_USER_ONLY) */ |
426613db | 5014 | } |
a63f1dfc ND |
5015 | |
5016 | /* slbieg */ | |
5017 | static void gen_slbieg(DisasContext *ctx) | |
5018 | { | |
5019 | #if defined(CONFIG_USER_ONLY) | |
5020 | GEN_PRIV; | |
5021 | #else | |
5022 | CHK_SV; | |
5023 | ||
5024 | gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]); | |
5025 | #endif /* defined(CONFIG_USER_ONLY) */ | |
5026 | } | |
5027 | ||
62d897ca ND |
5028 | /* slbsync */ |
5029 | static void gen_slbsync(DisasContext *ctx) | |
5030 | { | |
5031 | #if defined(CONFIG_USER_ONLY) | |
5032 | GEN_PRIV; | |
5033 | #else | |
5034 | CHK_SV; | |
5035 | gen_check_tlb_flush(ctx, true); | |
5036 | #endif /* defined(CONFIG_USER_ONLY) */ | |
5037 | } | |
5038 | ||
9b2fadda | 5039 | #endif /* defined(TARGET_PPC64) */ |
426613db | 5040 | |
79aceca5 FB |
5041 | /*** External control ***/ |
5042 | /* Optional: */ | |
99e300ef | 5043 | |
54623277 | 5044 | /* eciwx */ |
99e300ef | 5045 | static void gen_eciwx(DisasContext *ctx) |
79aceca5 | 5046 | { |
76db3ba4 | 5047 | TCGv t0; |
fa407c03 | 5048 | /* Should check EAR[E] ! */ |
76db3ba4 AJ |
5049 | gen_set_access_type(ctx, ACCESS_EXT); |
5050 | t0 = tcg_temp_new(); | |
5051 | gen_addr_reg_index(ctx, t0); | |
c674a983 RH |
5052 | tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, |
5053 | DEF_MEMOP(MO_UL | MO_ALIGN)); | |
fa407c03 | 5054 | tcg_temp_free(t0); |
76a66253 JM |
5055 | } |
5056 | ||
5057 | /* ecowx */ | |
99e300ef | 5058 | static void gen_ecowx(DisasContext *ctx) |
76a66253 | 5059 | { |
76db3ba4 | 5060 | TCGv t0; |
fa407c03 | 5061 | /* Should check EAR[E] ! */ |
76db3ba4 AJ |
5062 | gen_set_access_type(ctx, ACCESS_EXT); |
5063 | t0 = tcg_temp_new(); | |
5064 | gen_addr_reg_index(ctx, t0); | |
c674a983 RH |
5065 | tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, |
5066 | DEF_MEMOP(MO_UL | MO_ALIGN)); | |
fa407c03 | 5067 | tcg_temp_free(t0); |
76a66253 JM |
5068 | } |
5069 | ||
5070 | /* PowerPC 601 specific instructions */ | |
99e300ef | 5071 | |
54623277 | 5072 | /* abs - abs. */ |
99e300ef | 5073 | static void gen_abs(DisasContext *ctx) |
76a66253 | 5074 | { |
fe21b785 RH |
5075 | TCGv d = cpu_gpr[rD(ctx->opcode)]; |
5076 | TCGv a = cpu_gpr[rA(ctx->opcode)]; | |
5077 | ||
5078 | tcg_gen_abs_tl(d, a); | |
efe843d8 | 5079 | if (unlikely(Rc(ctx->opcode) != 0)) { |
fe21b785 | 5080 | gen_set_Rc0(ctx, d); |
efe843d8 | 5081 | } |
76a66253 JM |
5082 | } |
5083 | ||
5084 | /* abso - abso. */ | |
99e300ef | 5085 | static void gen_abso(DisasContext *ctx) |
76a66253 | 5086 | { |
fe21b785 RH |
5087 | TCGv d = cpu_gpr[rD(ctx->opcode)]; |
5088 | TCGv a = cpu_gpr[rA(ctx->opcode)]; | |
5089 | ||
5090 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_ov, a, 0x80000000); | |
5091 | tcg_gen_abs_tl(d, a); | |
5092 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); | |
efe843d8 | 5093 | if (unlikely(Rc(ctx->opcode) != 0)) { |
fe21b785 | 5094 | gen_set_Rc0(ctx, d); |
efe843d8 | 5095 | } |
76a66253 JM |
5096 | } |
5097 | ||
5098 | /* clcs */ | |
99e300ef | 5099 | static void gen_clcs(DisasContext *ctx) |
76a66253 | 5100 | { |
22e0e173 | 5101 | TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); |
d523dd00 | 5102 | gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
22e0e173 | 5103 | tcg_temp_free_i32(t0); |
c7697e1f | 5104 | /* Rc=1 sets CR0 to an undefined state */ |
76a66253 JM |
5105 | } |
5106 | ||
5107 | /* div - div. */ | |
99e300ef | 5108 | static void gen_div(DisasContext *ctx) |
76a66253 | 5109 | { |
d15f74fb BS |
5110 | gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
5111 | cpu_gpr[rB(ctx->opcode)]); | |
efe843d8 | 5112 | if (unlikely(Rc(ctx->opcode) != 0)) { |
22e0e173 | 5113 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
efe843d8 | 5114 | } |
76a66253 JM |
5115 | } |
5116 | ||
5117 | /* divo - divo. */ | |
99e300ef | 5118 | static void gen_divo(DisasContext *ctx) |
76a66253 | 5119 | { |
d15f74fb BS |
5120 | gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
5121 | cpu_gpr[rB(ctx->opcode)]); | |
efe843d8 | 5122 | if (unlikely(Rc(ctx->opcode) != 0)) { |
22e0e173 | 5123 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
efe843d8 | 5124 | } |
76a66253 JM |
5125 | } |
5126 | ||
5127 | /* divs - divs. */ | |
99e300ef | 5128 | static void gen_divs(DisasContext *ctx) |
76a66253 | 5129 | { |
d15f74fb BS |
5130 | gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
5131 | cpu_gpr[rB(ctx->opcode)]); | |
efe843d8 | 5132 | if (unlikely(Rc(ctx->opcode) != 0)) { |
22e0e173 | 5133 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
efe843d8 | 5134 | } |
76a66253 JM |
5135 | } |
5136 | ||
5137 | /* divso - divso. */ | |
99e300ef | 5138 | static void gen_divso(DisasContext *ctx) |
76a66253 | 5139 | { |
d15f74fb BS |
5140 | gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5141 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
efe843d8 | 5142 | if (unlikely(Rc(ctx->opcode) != 0)) { |
22e0e173 | 5143 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
efe843d8 | 5144 | } |
76a66253 JM |
5145 | } |
5146 | ||
5147 | /* doz - doz. */ | |
99e300ef | 5148 | static void gen_doz(DisasContext *ctx) |
76a66253 | 5149 | { |
42a268c2 RH |
5150 | TCGLabel *l1 = gen_new_label(); |
5151 | TCGLabel *l2 = gen_new_label(); | |
efe843d8 DG |
5152 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], |
5153 | cpu_gpr[rA(ctx->opcode)], l1); | |
5154 | tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
5155 | cpu_gpr[rA(ctx->opcode)]); | |
22e0e173 AJ |
5156 | tcg_gen_br(l2); |
5157 | gen_set_label(l1); | |
5158 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
5159 | gen_set_label(l2); | |
efe843d8 | 5160 | if (unlikely(Rc(ctx->opcode) != 0)) { |
22e0e173 | 5161 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
efe843d8 | 5162 | } |
76a66253 JM |
5163 | } |
5164 | ||
5165 | /* dozo - dozo. */ | |
99e300ef | 5166 | static void gen_dozo(DisasContext *ctx) |
76a66253 | 5167 | { |
42a268c2 RH |
5168 | TCGLabel *l1 = gen_new_label(); |
5169 | TCGLabel *l2 = gen_new_label(); | |
22e0e173 AJ |
5170 | TCGv t0 = tcg_temp_new(); |
5171 | TCGv t1 = tcg_temp_new(); | |
5172 | TCGv t2 = tcg_temp_new(); | |
5173 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 5174 | tcg_gen_movi_tl(cpu_ov, 0); |
efe843d8 DG |
5175 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], |
5176 | cpu_gpr[rA(ctx->opcode)], l1); | |
22e0e173 AJ |
5177 | tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
5178 | tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
5179 | tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); | |
5180 | tcg_gen_andc_tl(t1, t1, t2); | |
5181 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
5182 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); | |
da91a00f RH |
5183 | tcg_gen_movi_tl(cpu_ov, 1); |
5184 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
5185 | tcg_gen_br(l2); |
5186 | gen_set_label(l1); | |
5187 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
5188 | gen_set_label(l2); | |
5189 | tcg_temp_free(t0); | |
5190 | tcg_temp_free(t1); | |
5191 | tcg_temp_free(t2); | |
efe843d8 | 5192 | if (unlikely(Rc(ctx->opcode) != 0)) { |
22e0e173 | 5193 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
efe843d8 | 5194 | } |
76a66253 JM |
5195 | } |
5196 | ||
5197 | /* dozi */ | |
99e300ef | 5198 | static void gen_dozi(DisasContext *ctx) |
76a66253 | 5199 | { |
22e0e173 | 5200 | target_long simm = SIMM(ctx->opcode); |
42a268c2 RH |
5201 | TCGLabel *l1 = gen_new_label(); |
5202 | TCGLabel *l2 = gen_new_label(); | |
22e0e173 AJ |
5203 | tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); |
5204 | tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); | |
5205 | tcg_gen_br(l2); | |
5206 | gen_set_label(l1); | |
5207 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
5208 | gen_set_label(l2); | |
efe843d8 | 5209 | if (unlikely(Rc(ctx->opcode) != 0)) { |
22e0e173 | 5210 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
efe843d8 | 5211 | } |
76a66253 JM |
5212 | } |
5213 | ||
76a66253 | 5214 | /* lscbx - lscbx. */ |
99e300ef | 5215 | static void gen_lscbx(DisasContext *ctx) |
76a66253 | 5216 | { |
bdb4b689 AJ |
5217 | TCGv t0 = tcg_temp_new(); |
5218 | TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); | |
5219 | TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); | |
5220 | TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); | |
76a66253 | 5221 | |
76db3ba4 | 5222 | gen_addr_reg_index(ctx, t0); |
2f5a189c | 5223 | gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); |
bdb4b689 AJ |
5224 | tcg_temp_free_i32(t1); |
5225 | tcg_temp_free_i32(t2); | |
5226 | tcg_temp_free_i32(t3); | |
3d7b417e | 5227 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); |
bdb4b689 | 5228 | tcg_gen_or_tl(cpu_xer, cpu_xer, t0); |
efe843d8 | 5229 | if (unlikely(Rc(ctx->opcode) != 0)) { |
bdb4b689 | 5230 | gen_set_Rc0(ctx, t0); |
efe843d8 | 5231 | } |
bdb4b689 | 5232 | tcg_temp_free(t0); |
76a66253 JM |
5233 | } |
5234 | ||
5235 | /* maskg - maskg. */ | |
99e300ef | 5236 | static void gen_maskg(DisasContext *ctx) |
76a66253 | 5237 | { |
42a268c2 | 5238 | TCGLabel *l1 = gen_new_label(); |
22e0e173 AJ |
5239 | TCGv t0 = tcg_temp_new(); |
5240 | TCGv t1 = tcg_temp_new(); | |
5241 | TCGv t2 = tcg_temp_new(); | |
5242 | TCGv t3 = tcg_temp_new(); | |
5243 | tcg_gen_movi_tl(t3, 0xFFFFFFFF); | |
5244 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5245 | tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); | |
5246 | tcg_gen_addi_tl(t2, t0, 1); | |
5247 | tcg_gen_shr_tl(t2, t3, t2); | |
5248 | tcg_gen_shr_tl(t3, t3, t1); | |
5249 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); | |
5250 | tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); | |
5251 | tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
5252 | gen_set_label(l1); | |
5253 | tcg_temp_free(t0); | |
5254 | tcg_temp_free(t1); | |
5255 | tcg_temp_free(t2); | |
5256 | tcg_temp_free(t3); | |
efe843d8 | 5257 | if (unlikely(Rc(ctx->opcode) != 0)) { |
22e0e173 | 5258 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 5259 | } |
76a66253 JM |
5260 | } |
5261 | ||
5262 | /* maskir - maskir. */ | |
99e300ef | 5263 | static void gen_maskir(DisasContext *ctx) |
76a66253 | 5264 | { |
22e0e173 AJ |
5265 | TCGv t0 = tcg_temp_new(); |
5266 | TCGv t1 = tcg_temp_new(); | |
5267 | tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
5268 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
5269 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5270 | tcg_temp_free(t0); | |
5271 | tcg_temp_free(t1); | |
efe843d8 | 5272 | if (unlikely(Rc(ctx->opcode) != 0)) { |
22e0e173 | 5273 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 5274 | } |
76a66253 JM |
5275 | } |
5276 | ||
5277 | /* mul - mul. */ | |
99e300ef | 5278 | static void gen_mul(DisasContext *ctx) |
76a66253 | 5279 | { |
22e0e173 AJ |
5280 | TCGv_i64 t0 = tcg_temp_new_i64(); |
5281 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
5282 | TCGv t2 = tcg_temp_new(); | |
5283 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
5284 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
5285 | tcg_gen_mul_i64(t0, t0, t1); | |
5286 | tcg_gen_trunc_i64_tl(t2, t0); | |
5287 | gen_store_spr(SPR_MQ, t2); | |
5288 | tcg_gen_shri_i64(t1, t0, 32); | |
5289 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
5290 | tcg_temp_free_i64(t0); | |
5291 | tcg_temp_free_i64(t1); | |
5292 | tcg_temp_free(t2); | |
efe843d8 | 5293 | if (unlikely(Rc(ctx->opcode) != 0)) { |
22e0e173 | 5294 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
efe843d8 | 5295 | } |
76a66253 JM |
5296 | } |
5297 | ||
5298 | /* mulo - mulo. */ | |
99e300ef | 5299 | static void gen_mulo(DisasContext *ctx) |
76a66253 | 5300 | { |
42a268c2 | 5301 | TCGLabel *l1 = gen_new_label(); |
22e0e173 AJ |
5302 | TCGv_i64 t0 = tcg_temp_new_i64(); |
5303 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
5304 | TCGv t2 = tcg_temp_new(); | |
5305 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 5306 | tcg_gen_movi_tl(cpu_ov, 0); |
22e0e173 AJ |
5307 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
5308 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
5309 | tcg_gen_mul_i64(t0, t0, t1); | |
5310 | tcg_gen_trunc_i64_tl(t2, t0); | |
5311 | gen_store_spr(SPR_MQ, t2); | |
5312 | tcg_gen_shri_i64(t1, t0, 32); | |
5313 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
5314 | tcg_gen_ext32s_i64(t1, t0); | |
5315 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); | |
da91a00f RH |
5316 | tcg_gen_movi_tl(cpu_ov, 1); |
5317 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
5318 | gen_set_label(l1); |
5319 | tcg_temp_free_i64(t0); | |
5320 | tcg_temp_free_i64(t1); | |
5321 | tcg_temp_free(t2); | |
efe843d8 | 5322 | if (unlikely(Rc(ctx->opcode) != 0)) { |
22e0e173 | 5323 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
efe843d8 | 5324 | } |
76a66253 JM |
5325 | } |
5326 | ||
5327 | /* nabs - nabs. */ | |
99e300ef | 5328 | static void gen_nabs(DisasContext *ctx) |
76a66253 | 5329 | { |
fe21b785 RH |
5330 | TCGv d = cpu_gpr[rD(ctx->opcode)]; |
5331 | TCGv a = cpu_gpr[rA(ctx->opcode)]; | |
5332 | ||
5333 | tcg_gen_abs_tl(d, a); | |
5334 | tcg_gen_neg_tl(d, d); | |
efe843d8 | 5335 | if (unlikely(Rc(ctx->opcode) != 0)) { |
fe21b785 | 5336 | gen_set_Rc0(ctx, d); |
efe843d8 | 5337 | } |
76a66253 JM |
5338 | } |
5339 | ||
5340 | /* nabso - nabso. */ | |
99e300ef | 5341 | static void gen_nabso(DisasContext *ctx) |
76a66253 | 5342 | { |
fe21b785 RH |
5343 | TCGv d = cpu_gpr[rD(ctx->opcode)]; |
5344 | TCGv a = cpu_gpr[rA(ctx->opcode)]; | |
5345 | ||
5346 | tcg_gen_abs_tl(d, a); | |
5347 | tcg_gen_neg_tl(d, d); | |
22e0e173 | 5348 | /* nabs never overflows */ |
da91a00f | 5349 | tcg_gen_movi_tl(cpu_ov, 0); |
efe843d8 | 5350 | if (unlikely(Rc(ctx->opcode) != 0)) { |
fe21b785 | 5351 | gen_set_Rc0(ctx, d); |
efe843d8 | 5352 | } |
76a66253 JM |
5353 | } |
5354 | ||
5355 | /* rlmi - rlmi. */ | |
99e300ef | 5356 | static void gen_rlmi(DisasContext *ctx) |
76a66253 | 5357 | { |
7487953d AJ |
5358 | uint32_t mb = MB(ctx->opcode); |
5359 | uint32_t me = ME(ctx->opcode); | |
5360 | TCGv t0 = tcg_temp_new(); | |
5361 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5362 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
5363 | tcg_gen_andi_tl(t0, t0, MASK(mb, me)); | |
efe843d8 DG |
5364 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
5365 | ~MASK(mb, me)); | |
7487953d AJ |
5366 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); |
5367 | tcg_temp_free(t0); | |
efe843d8 | 5368 | if (unlikely(Rc(ctx->opcode) != 0)) { |
7487953d | 5369 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 5370 | } |
76a66253 JM |
5371 | } |
5372 | ||
5373 | /* rrib - rrib. */ | |
99e300ef | 5374 | static void gen_rrib(DisasContext *ctx) |
76a66253 | 5375 | { |
7487953d AJ |
5376 | TCGv t0 = tcg_temp_new(); |
5377 | TCGv t1 = tcg_temp_new(); | |
5378 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5379 | tcg_gen_movi_tl(t1, 0x80000000); | |
5380 | tcg_gen_shr_tl(t1, t1, t0); | |
5381 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
5382 | tcg_gen_and_tl(t0, t0, t1); | |
5383 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); | |
5384 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5385 | tcg_temp_free(t0); | |
5386 | tcg_temp_free(t1); | |
efe843d8 | 5387 | if (unlikely(Rc(ctx->opcode) != 0)) { |
7487953d | 5388 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 5389 | } |
76a66253 JM |
5390 | } |
5391 | ||
5392 | /* sle - sle. */ | |
99e300ef | 5393 | static void gen_sle(DisasContext *ctx) |
76a66253 | 5394 | { |
7487953d AJ |
5395 | TCGv t0 = tcg_temp_new(); |
5396 | TCGv t1 = tcg_temp_new(); | |
5397 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5398 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5399 | tcg_gen_subfi_tl(t1, 32, t1); | |
5400 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5401 | tcg_gen_or_tl(t1, t0, t1); | |
5402 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5403 | gen_store_spr(SPR_MQ, t1); | |
5404 | tcg_temp_free(t0); | |
5405 | tcg_temp_free(t1); | |
efe843d8 | 5406 | if (unlikely(Rc(ctx->opcode) != 0)) { |
7487953d | 5407 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 5408 | } |
76a66253 JM |
5409 | } |
5410 | ||
5411 | /* sleq - sleq. */ | |
99e300ef | 5412 | static void gen_sleq(DisasContext *ctx) |
76a66253 | 5413 | { |
7487953d AJ |
5414 | TCGv t0 = tcg_temp_new(); |
5415 | TCGv t1 = tcg_temp_new(); | |
5416 | TCGv t2 = tcg_temp_new(); | |
5417 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5418 | tcg_gen_movi_tl(t2, 0xFFFFFFFF); | |
5419 | tcg_gen_shl_tl(t2, t2, t0); | |
5420 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
5421 | gen_load_spr(t1, SPR_MQ); | |
5422 | gen_store_spr(SPR_MQ, t0); | |
5423 | tcg_gen_and_tl(t0, t0, t2); | |
5424 | tcg_gen_andc_tl(t1, t1, t2); | |
5425 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5426 | tcg_temp_free(t0); | |
5427 | tcg_temp_free(t1); | |
5428 | tcg_temp_free(t2); | |
efe843d8 | 5429 | if (unlikely(Rc(ctx->opcode) != 0)) { |
7487953d | 5430 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 5431 | } |
76a66253 JM |
5432 | } |
5433 | ||
5434 | /* sliq - sliq. */ | |
99e300ef | 5435 | static void gen_sliq(DisasContext *ctx) |
76a66253 | 5436 | { |
7487953d AJ |
5437 | int sh = SH(ctx->opcode); |
5438 | TCGv t0 = tcg_temp_new(); | |
5439 | TCGv t1 = tcg_temp_new(); | |
5440 | tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5441 | tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
5442 | tcg_gen_or_tl(t1, t0, t1); | |
5443 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5444 | gen_store_spr(SPR_MQ, t1); | |
5445 | tcg_temp_free(t0); | |
5446 | tcg_temp_free(t1); | |
efe843d8 | 5447 | if (unlikely(Rc(ctx->opcode) != 0)) { |
7487953d | 5448 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 5449 | } |
76a66253 JM |
5450 | } |
5451 | ||
5452 | /* slliq - slliq. */ | |
99e300ef | 5453 | static void gen_slliq(DisasContext *ctx) |
76a66253 | 5454 | { |
7487953d AJ |
5455 | int sh = SH(ctx->opcode); |
5456 | TCGv t0 = tcg_temp_new(); | |
5457 | TCGv t1 = tcg_temp_new(); | |
5458 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5459 | gen_load_spr(t1, SPR_MQ); | |
5460 | gen_store_spr(SPR_MQ, t0); | |
5461 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); | |
5462 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); | |
5463 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5464 | tcg_temp_free(t0); | |
5465 | tcg_temp_free(t1); | |
efe843d8 | 5466 | if (unlikely(Rc(ctx->opcode) != 0)) { |
7487953d | 5467 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 5468 | } |
76a66253 JM |
5469 | } |
5470 | ||
5471 | /* sllq - sllq. */ | |
99e300ef | 5472 | static void gen_sllq(DisasContext *ctx) |
76a66253 | 5473 | { |
42a268c2 RH |
5474 | TCGLabel *l1 = gen_new_label(); |
5475 | TCGLabel *l2 = gen_new_label(); | |
7487953d AJ |
5476 | TCGv t0 = tcg_temp_local_new(); |
5477 | TCGv t1 = tcg_temp_local_new(); | |
5478 | TCGv t2 = tcg_temp_local_new(); | |
5479 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5480 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5481 | tcg_gen_shl_tl(t1, t1, t2); | |
5482 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5483 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5484 | gen_load_spr(t0, SPR_MQ); | |
5485 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5486 | tcg_gen_br(l2); | |
5487 | gen_set_label(l1); | |
5488 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
5489 | gen_load_spr(t2, SPR_MQ); | |
5490 | tcg_gen_andc_tl(t1, t2, t1); | |
5491 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5492 | gen_set_label(l2); | |
5493 | tcg_temp_free(t0); | |
5494 | tcg_temp_free(t1); | |
5495 | tcg_temp_free(t2); | |
efe843d8 | 5496 | if (unlikely(Rc(ctx->opcode) != 0)) { |
7487953d | 5497 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 5498 | } |
76a66253 JM |
5499 | } |
5500 | ||
5501 | /* slq - slq. */ | |
99e300ef | 5502 | static void gen_slq(DisasContext *ctx) |
76a66253 | 5503 | { |
42a268c2 | 5504 | TCGLabel *l1 = gen_new_label(); |
7487953d AJ |
5505 | TCGv t0 = tcg_temp_new(); |
5506 | TCGv t1 = tcg_temp_new(); | |
5507 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5508 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5509 | tcg_gen_subfi_tl(t1, 32, t1); | |
5510 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5511 | tcg_gen_or_tl(t1, t0, t1); | |
5512 | gen_store_spr(SPR_MQ, t1); | |
5513 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5514 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5515 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); | |
5516 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
5517 | gen_set_label(l1); | |
5518 | tcg_temp_free(t0); | |
5519 | tcg_temp_free(t1); | |
efe843d8 | 5520 | if (unlikely(Rc(ctx->opcode) != 0)) { |
7487953d | 5521 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 5522 | } |
76a66253 JM |
5523 | } |
5524 | ||
d9bce9d9 | 5525 | /* sraiq - sraiq. */ |
99e300ef | 5526 | static void gen_sraiq(DisasContext *ctx) |
76a66253 | 5527 | { |
7487953d | 5528 | int sh = SH(ctx->opcode); |
42a268c2 | 5529 | TCGLabel *l1 = gen_new_label(); |
7487953d AJ |
5530 | TCGv t0 = tcg_temp_new(); |
5531 | TCGv t1 = tcg_temp_new(); | |
5532 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5533 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
5534 | tcg_gen_or_tl(t0, t0, t1); | |
5535 | gen_store_spr(SPR_MQ, t0); | |
da91a00f | 5536 | tcg_gen_movi_tl(cpu_ca, 0); |
7487953d AJ |
5537 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); |
5538 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); | |
da91a00f | 5539 | tcg_gen_movi_tl(cpu_ca, 1); |
7487953d AJ |
5540 | gen_set_label(l1); |
5541 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); | |
5542 | tcg_temp_free(t0); | |
5543 | tcg_temp_free(t1); | |
efe843d8 | 5544 | if (unlikely(Rc(ctx->opcode) != 0)) { |
7487953d | 5545 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 5546 | } |
76a66253 JM |
5547 | } |
5548 | ||
5549 | /* sraq - sraq. */ | |
99e300ef | 5550 | static void gen_sraq(DisasContext *ctx) |
76a66253 | 5551 | { |
42a268c2 RH |
5552 | TCGLabel *l1 = gen_new_label(); |
5553 | TCGLabel *l2 = gen_new_label(); | |
7487953d AJ |
5554 | TCGv t0 = tcg_temp_new(); |
5555 | TCGv t1 = tcg_temp_local_new(); | |
5556 | TCGv t2 = tcg_temp_local_new(); | |
5557 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5558 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
5559 | tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); | |
5560 | tcg_gen_subfi_tl(t2, 32, t2); | |
5561 | tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); | |
5562 | tcg_gen_or_tl(t0, t0, t2); | |
5563 | gen_store_spr(SPR_MQ, t0); | |
5564 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5565 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); | |
5566 | tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); | |
5567 | tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); | |
5568 | gen_set_label(l1); | |
5569 | tcg_temp_free(t0); | |
5570 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); | |
da91a00f | 5571 | tcg_gen_movi_tl(cpu_ca, 0); |
7487953d AJ |
5572 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); |
5573 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); | |
da91a00f | 5574 | tcg_gen_movi_tl(cpu_ca, 1); |
7487953d AJ |
5575 | gen_set_label(l2); |
5576 | tcg_temp_free(t1); | |
5577 | tcg_temp_free(t2); | |
efe843d8 | 5578 | if (unlikely(Rc(ctx->opcode) != 0)) { |
7487953d | 5579 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 5580 | } |
76a66253 JM |
5581 | } |
5582 | ||
5583 | /* sre - sre. */ | |
99e300ef | 5584 | static void gen_sre(DisasContext *ctx) |
76a66253 | 5585 | { |
7487953d AJ |
5586 | TCGv t0 = tcg_temp_new(); |
5587 | TCGv t1 = tcg_temp_new(); | |
5588 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5589 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5590 | tcg_gen_subfi_tl(t1, 32, t1); | |
5591 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5592 | tcg_gen_or_tl(t1, t0, t1); | |
5593 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5594 | gen_store_spr(SPR_MQ, t1); | |
5595 | tcg_temp_free(t0); | |
5596 | tcg_temp_free(t1); | |
efe843d8 | 5597 | if (unlikely(Rc(ctx->opcode) != 0)) { |
7487953d | 5598 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 5599 | } |
76a66253 JM |
5600 | } |
5601 | ||
5602 | /* srea - srea. */ | |
99e300ef | 5603 | static void gen_srea(DisasContext *ctx) |
76a66253 | 5604 | { |
7487953d AJ |
5605 | TCGv t0 = tcg_temp_new(); |
5606 | TCGv t1 = tcg_temp_new(); | |
5607 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5608 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5609 | gen_store_spr(SPR_MQ, t0); | |
5610 | tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); | |
5611 | tcg_temp_free(t0); | |
5612 | tcg_temp_free(t1); | |
efe843d8 | 5613 | if (unlikely(Rc(ctx->opcode) != 0)) { |
7487953d | 5614 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 5615 | } |
76a66253 JM |
5616 | } |
5617 | ||
5618 | /* sreq */ | |
99e300ef | 5619 | static void gen_sreq(DisasContext *ctx) |
76a66253 | 5620 | { |
7487953d AJ |
5621 | TCGv t0 = tcg_temp_new(); |
5622 | TCGv t1 = tcg_temp_new(); | |
5623 | TCGv t2 = tcg_temp_new(); | |
5624 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5625 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5626 | tcg_gen_shr_tl(t1, t1, t0); | |
5627 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
5628 | gen_load_spr(t2, SPR_MQ); | |
5629 | gen_store_spr(SPR_MQ, t0); | |
5630 | tcg_gen_and_tl(t0, t0, t1); | |
5631 | tcg_gen_andc_tl(t2, t2, t1); | |
5632 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); | |
5633 | tcg_temp_free(t0); | |
5634 | tcg_temp_free(t1); | |
5635 | tcg_temp_free(t2); | |
efe843d8 | 5636 | if (unlikely(Rc(ctx->opcode) != 0)) { |
7487953d | 5637 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 5638 | } |
76a66253 JM |
5639 | } |
5640 | ||
5641 | /* sriq */ | |
99e300ef | 5642 | static void gen_sriq(DisasContext *ctx) |
76a66253 | 5643 | { |
7487953d AJ |
5644 | int sh = SH(ctx->opcode); |
5645 | TCGv t0 = tcg_temp_new(); | |
5646 | TCGv t1 = tcg_temp_new(); | |
5647 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5648 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
5649 | tcg_gen_or_tl(t1, t0, t1); | |
5650 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5651 | gen_store_spr(SPR_MQ, t1); | |
5652 | tcg_temp_free(t0); | |
5653 | tcg_temp_free(t1); | |
efe843d8 | 5654 | if (unlikely(Rc(ctx->opcode) != 0)) { |
7487953d | 5655 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 5656 | } |
76a66253 JM |
5657 | } |
5658 | ||
5659 | /* srliq */ | |
99e300ef | 5660 | static void gen_srliq(DisasContext *ctx) |
76a66253 | 5661 | { |
7487953d AJ |
5662 | int sh = SH(ctx->opcode); |
5663 | TCGv t0 = tcg_temp_new(); | |
5664 | TCGv t1 = tcg_temp_new(); | |
5665 | tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5666 | gen_load_spr(t1, SPR_MQ); | |
5667 | gen_store_spr(SPR_MQ, t0); | |
5668 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); | |
5669 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); | |
5670 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5671 | tcg_temp_free(t0); | |
5672 | tcg_temp_free(t1); | |
efe843d8 | 5673 | if (unlikely(Rc(ctx->opcode) != 0)) { |
7487953d | 5674 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 5675 | } |
76a66253 JM |
5676 | } |
5677 | ||
5678 | /* srlq */ | |
99e300ef | 5679 | static void gen_srlq(DisasContext *ctx) |
76a66253 | 5680 | { |
42a268c2 RH |
5681 | TCGLabel *l1 = gen_new_label(); |
5682 | TCGLabel *l2 = gen_new_label(); | |
7487953d AJ |
5683 | TCGv t0 = tcg_temp_local_new(); |
5684 | TCGv t1 = tcg_temp_local_new(); | |
5685 | TCGv t2 = tcg_temp_local_new(); | |
5686 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5687 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5688 | tcg_gen_shr_tl(t2, t1, t2); | |
5689 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5690 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5691 | gen_load_spr(t0, SPR_MQ); | |
5692 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); | |
5693 | tcg_gen_br(l2); | |
5694 | gen_set_label(l1); | |
5695 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
5696 | tcg_gen_and_tl(t0, t0, t2); | |
5697 | gen_load_spr(t1, SPR_MQ); | |
5698 | tcg_gen_andc_tl(t1, t1, t2); | |
5699 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5700 | gen_set_label(l2); | |
5701 | tcg_temp_free(t0); | |
5702 | tcg_temp_free(t1); | |
5703 | tcg_temp_free(t2); | |
efe843d8 | 5704 | if (unlikely(Rc(ctx->opcode) != 0)) { |
7487953d | 5705 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 5706 | } |
76a66253 JM |
5707 | } |
5708 | ||
5709 | /* srq */ | |
99e300ef | 5710 | static void gen_srq(DisasContext *ctx) |
76a66253 | 5711 | { |
42a268c2 | 5712 | TCGLabel *l1 = gen_new_label(); |
7487953d AJ |
5713 | TCGv t0 = tcg_temp_new(); |
5714 | TCGv t1 = tcg_temp_new(); | |
5715 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5716 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5717 | tcg_gen_subfi_tl(t1, 32, t1); | |
5718 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5719 | tcg_gen_or_tl(t1, t0, t1); | |
5720 | gen_store_spr(SPR_MQ, t1); | |
5721 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5722 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5723 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5724 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
5725 | gen_set_label(l1); | |
5726 | tcg_temp_free(t0); | |
5727 | tcg_temp_free(t1); | |
efe843d8 | 5728 | if (unlikely(Rc(ctx->opcode) != 0)) { |
7487953d | 5729 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 5730 | } |
76a66253 JM |
5731 | } |
5732 | ||
5733 | /* PowerPC 602 specific instructions */ | |
99e300ef | 5734 | |
54623277 | 5735 | /* dsa */ |
99e300ef | 5736 | static void gen_dsa(DisasContext *ctx) |
76a66253 JM |
5737 | { |
5738 | /* XXX: TODO */ | |
e06fcd75 | 5739 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5740 | } |
5741 | ||
5742 | /* esa */ | |
99e300ef | 5743 | static void gen_esa(DisasContext *ctx) |
76a66253 JM |
5744 | { |
5745 | /* XXX: TODO */ | |
e06fcd75 | 5746 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5747 | } |
5748 | ||
5749 | /* mfrom */ | |
99e300ef | 5750 | static void gen_mfrom(DisasContext *ctx) |
76a66253 JM |
5751 | { |
5752 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5753 | GEN_PRIV; |
76a66253 | 5754 | #else |
9b2fadda | 5755 | CHK_SV; |
cf02a65c | 5756 | gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
9b2fadda | 5757 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5758 | } |
5759 | ||
5760 | /* 602 - 603 - G2 TLB management */ | |
e8eaa2c0 | 5761 | |
54623277 | 5762 | /* tlbld */ |
e8eaa2c0 | 5763 | static void gen_tlbld_6xx(DisasContext *ctx) |
76a66253 JM |
5764 | { |
5765 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5766 | GEN_PRIV; |
76a66253 | 5767 | #else |
9b2fadda | 5768 | CHK_SV; |
c6c7cf05 | 5769 | gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 5770 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5771 | } |
5772 | ||
5773 | /* tlbli */ | |
e8eaa2c0 | 5774 | static void gen_tlbli_6xx(DisasContext *ctx) |
76a66253 JM |
5775 | { |
5776 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5777 | GEN_PRIV; |
76a66253 | 5778 | #else |
9b2fadda | 5779 | CHK_SV; |
c6c7cf05 | 5780 | gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 5781 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5782 | } |
5783 | ||
7dbe11ac | 5784 | /* 74xx TLB management */ |
e8eaa2c0 | 5785 | |
54623277 | 5786 | /* tlbld */ |
e8eaa2c0 | 5787 | static void gen_tlbld_74xx(DisasContext *ctx) |
7dbe11ac JM |
5788 | { |
5789 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5790 | GEN_PRIV; |
7dbe11ac | 5791 | #else |
9b2fadda | 5792 | CHK_SV; |
c6c7cf05 | 5793 | gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 5794 | #endif /* defined(CONFIG_USER_ONLY) */ |
7dbe11ac JM |
5795 | } |
5796 | ||
5797 | /* tlbli */ | |
e8eaa2c0 | 5798 | static void gen_tlbli_74xx(DisasContext *ctx) |
7dbe11ac JM |
5799 | { |
5800 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5801 | GEN_PRIV; |
7dbe11ac | 5802 | #else |
9b2fadda | 5803 | CHK_SV; |
c6c7cf05 | 5804 | gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 5805 | #endif /* defined(CONFIG_USER_ONLY) */ |
7dbe11ac JM |
5806 | } |
5807 | ||
76a66253 | 5808 | /* POWER instructions not in PowerPC 601 */ |
99e300ef | 5809 | |
54623277 | 5810 | /* clf */ |
99e300ef | 5811 | static void gen_clf(DisasContext *ctx) |
76a66253 JM |
5812 | { |
5813 | /* Cache line flush: implemented as no-op */ | |
5814 | } | |
5815 | ||
5816 | /* cli */ | |
99e300ef | 5817 | static void gen_cli(DisasContext *ctx) |
76a66253 | 5818 | { |
76a66253 | 5819 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 5820 | GEN_PRIV; |
76a66253 | 5821 | #else |
9b2fadda BH |
5822 | /* Cache line invalidate: privileged and treated as no-op */ |
5823 | CHK_SV; | |
5824 | #endif /* defined(CONFIG_USER_ONLY) */ | |
76a66253 JM |
5825 | } |
5826 | ||
5827 | /* dclst */ | |
99e300ef | 5828 | static void gen_dclst(DisasContext *ctx) |
76a66253 JM |
5829 | { |
5830 | /* Data cache line store: treated as no-op */ | |
5831 | } | |
5832 | ||
99e300ef | 5833 | static void gen_mfsri(DisasContext *ctx) |
76a66253 JM |
5834 | { |
5835 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5836 | GEN_PRIV; |
76a66253 | 5837 | #else |
74d37793 AJ |
5838 | int ra = rA(ctx->opcode); |
5839 | int rd = rD(ctx->opcode); | |
5840 | TCGv t0; | |
9b2fadda BH |
5841 | |
5842 | CHK_SV; | |
74d37793 | 5843 | t0 = tcg_temp_new(); |
76db3ba4 | 5844 | gen_addr_reg_index(ctx, t0); |
e2622073 | 5845 | tcg_gen_extract_tl(t0, t0, 28, 4); |
c6c7cf05 | 5846 | gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); |
74d37793 | 5847 | tcg_temp_free(t0); |
efe843d8 | 5848 | if (ra != 0 && ra != rd) { |
74d37793 | 5849 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); |
efe843d8 | 5850 | } |
9b2fadda | 5851 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5852 | } |
5853 | ||
99e300ef | 5854 | static void gen_rac(DisasContext *ctx) |
76a66253 JM |
5855 | { |
5856 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5857 | GEN_PRIV; |
76a66253 | 5858 | #else |
22e0e173 | 5859 | TCGv t0; |
9b2fadda BH |
5860 | |
5861 | CHK_SV; | |
22e0e173 | 5862 | t0 = tcg_temp_new(); |
76db3ba4 | 5863 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 5864 | gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
22e0e173 | 5865 | tcg_temp_free(t0); |
9b2fadda | 5866 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5867 | } |
5868 | ||
99e300ef | 5869 | static void gen_rfsvc(DisasContext *ctx) |
76a66253 JM |
5870 | { |
5871 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5872 | GEN_PRIV; |
76a66253 | 5873 | #else |
9b2fadda BH |
5874 | CHK_SV; |
5875 | ||
e5f17ac6 | 5876 | gen_helper_rfsvc(cpu_env); |
e06fcd75 | 5877 | gen_sync_exception(ctx); |
9b2fadda | 5878 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5879 | } |
5880 | ||
f9651121 | 5881 | /* svc is not implemented for now */ |
76a66253 JM |
5882 | |
5883 | /* BookE specific instructions */ | |
99e300ef | 5884 | |
54623277 | 5885 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5886 | static void gen_mfapidi(DisasContext *ctx) |
76a66253 JM |
5887 | { |
5888 | /* XXX: TODO */ | |
e06fcd75 | 5889 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5890 | } |
5891 | ||
2662a059 | 5892 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5893 | static void gen_tlbiva(DisasContext *ctx) |
76a66253 JM |
5894 | { |
5895 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5896 | GEN_PRIV; |
76a66253 | 5897 | #else |
74d37793 | 5898 | TCGv t0; |
9b2fadda BH |
5899 | |
5900 | CHK_SV; | |
ec72e276 | 5901 | t0 = tcg_temp_new(); |
76db3ba4 | 5902 | gen_addr_reg_index(ctx, t0); |
4693364f | 5903 | gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
74d37793 | 5904 | tcg_temp_free(t0); |
9b2fadda | 5905 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5906 | } |
5907 | ||
5908 | /* All 405 MAC instructions are translated here */ | |
636aa200 BS |
5909 | static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, |
5910 | int ra, int rb, int rt, int Rc) | |
76a66253 | 5911 | { |
182608d4 AJ |
5912 | TCGv t0, t1; |
5913 | ||
a7812ae4 PB |
5914 | t0 = tcg_temp_local_new(); |
5915 | t1 = tcg_temp_local_new(); | |
182608d4 | 5916 | |
76a66253 JM |
5917 | switch (opc3 & 0x0D) { |
5918 | case 0x05: | |
5919 | /* macchw - macchw. - macchwo - macchwo. */ | |
5920 | /* macchws - macchws. - macchwso - macchwso. */ | |
5921 | /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ | |
5922 | /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ | |
5923 | /* mulchw - mulchw. */ | |
182608d4 AJ |
5924 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5925 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5926 | tcg_gen_ext16s_tl(t1, t1); | |
76a66253 JM |
5927 | break; |
5928 | case 0x04: | |
5929 | /* macchwu - macchwu. - macchwuo - macchwuo. */ | |
5930 | /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ | |
5931 | /* mulchwu - mulchwu. */ | |
182608d4 AJ |
5932 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5933 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5934 | tcg_gen_ext16u_tl(t1, t1); | |
76a66253 JM |
5935 | break; |
5936 | case 0x01: | |
5937 | /* machhw - machhw. - machhwo - machhwo. */ | |
5938 | /* machhws - machhws. - machhwso - machhwso. */ | |
5939 | /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ | |
5940 | /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ | |
5941 | /* mulhhw - mulhhw. */ | |
182608d4 AJ |
5942 | tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); |
5943 | tcg_gen_ext16s_tl(t0, t0); | |
5944 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5945 | tcg_gen_ext16s_tl(t1, t1); | |
76a66253 JM |
5946 | break; |
5947 | case 0x00: | |
5948 | /* machhwu - machhwu. - machhwuo - machhwuo. */ | |
5949 | /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ | |
5950 | /* mulhhwu - mulhhwu. */ | |
182608d4 AJ |
5951 | tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); |
5952 | tcg_gen_ext16u_tl(t0, t0); | |
5953 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5954 | tcg_gen_ext16u_tl(t1, t1); | |
76a66253 JM |
5955 | break; |
5956 | case 0x0D: | |
5957 | /* maclhw - maclhw. - maclhwo - maclhwo. */ | |
5958 | /* maclhws - maclhws. - maclhwso - maclhwso. */ | |
5959 | /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ | |
5960 | /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ | |
5961 | /* mullhw - mullhw. */ | |
182608d4 AJ |
5962 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5963 | tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); | |
76a66253 JM |
5964 | break; |
5965 | case 0x0C: | |
5966 | /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ | |
5967 | /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ | |
5968 | /* mullhwu - mullhwu. */ | |
182608d4 AJ |
5969 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5970 | tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); | |
76a66253 JM |
5971 | break; |
5972 | } | |
76a66253 | 5973 | if (opc2 & 0x04) { |
182608d4 AJ |
5974 | /* (n)multiply-and-accumulate (0x0C / 0x0E) */ |
5975 | tcg_gen_mul_tl(t1, t0, t1); | |
5976 | if (opc2 & 0x02) { | |
5977 | /* nmultiply-and-accumulate (0x0E) */ | |
5978 | tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); | |
5979 | } else { | |
5980 | /* multiply-and-accumulate (0x0C) */ | |
5981 | tcg_gen_add_tl(t0, cpu_gpr[rt], t1); | |
5982 | } | |
5983 | ||
5984 | if (opc3 & 0x12) { | |
5985 | /* Check overflow and/or saturate */ | |
42a268c2 | 5986 | TCGLabel *l1 = gen_new_label(); |
182608d4 AJ |
5987 | |
5988 | if (opc3 & 0x10) { | |
5989 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 5990 | tcg_gen_movi_tl(cpu_ov, 0); |
182608d4 AJ |
5991 | } |
5992 | if (opc3 & 0x01) { | |
5993 | /* Signed */ | |
5994 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); | |
5995 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); | |
5996 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); | |
5997 | tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); | |
bdc4e053 | 5998 | if (opc3 & 0x02) { |
182608d4 AJ |
5999 | /* Saturate */ |
6000 | tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); | |
6001 | tcg_gen_xori_tl(t0, t0, 0x7fffffff); | |
6002 | } | |
6003 | } else { | |
6004 | /* Unsigned */ | |
6005 | tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); | |
bdc4e053 | 6006 | if (opc3 & 0x02) { |
182608d4 AJ |
6007 | /* Saturate */ |
6008 | tcg_gen_movi_tl(t0, UINT32_MAX); | |
6009 | } | |
6010 | } | |
6011 | if (opc3 & 0x10) { | |
6012 | /* Check overflow */ | |
da91a00f RH |
6013 | tcg_gen_movi_tl(cpu_ov, 1); |
6014 | tcg_gen_movi_tl(cpu_so, 1); | |
182608d4 AJ |
6015 | } |
6016 | gen_set_label(l1); | |
6017 | tcg_gen_mov_tl(cpu_gpr[rt], t0); | |
6018 | } | |
6019 | } else { | |
6020 | tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); | |
76a66253 | 6021 | } |
182608d4 AJ |
6022 | tcg_temp_free(t0); |
6023 | tcg_temp_free(t1); | |
76a66253 JM |
6024 | if (unlikely(Rc) != 0) { |
6025 | /* Update Rc0 */ | |
182608d4 | 6026 | gen_set_Rc0(ctx, cpu_gpr[rt]); |
76a66253 JM |
6027 | } |
6028 | } | |
6029 | ||
a750fc0b | 6030 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ |
99e300ef | 6031 | static void glue(gen_, name)(DisasContext *ctx) \ |
76a66253 JM |
6032 | { \ |
6033 | gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ | |
6034 | rD(ctx->opcode), Rc(ctx->opcode)); \ | |
6035 | } | |
6036 | ||
6037 | /* macchw - macchw. */ | |
a750fc0b | 6038 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05); |
76a66253 | 6039 | /* macchwo - macchwo. */ |
a750fc0b | 6040 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); |
76a66253 | 6041 | /* macchws - macchws. */ |
a750fc0b | 6042 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07); |
76a66253 | 6043 | /* macchwso - macchwso. */ |
a750fc0b | 6044 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); |
76a66253 | 6045 | /* macchwsu - macchwsu. */ |
a750fc0b | 6046 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); |
76a66253 | 6047 | /* macchwsuo - macchwsuo. */ |
a750fc0b | 6048 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); |
76a66253 | 6049 | /* macchwu - macchwu. */ |
a750fc0b | 6050 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); |
76a66253 | 6051 | /* macchwuo - macchwuo. */ |
a750fc0b | 6052 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); |
76a66253 | 6053 | /* machhw - machhw. */ |
a750fc0b | 6054 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01); |
76a66253 | 6055 | /* machhwo - machhwo. */ |
a750fc0b | 6056 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); |
76a66253 | 6057 | /* machhws - machhws. */ |
a750fc0b | 6058 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03); |
76a66253 | 6059 | /* machhwso - machhwso. */ |
a750fc0b | 6060 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); |
76a66253 | 6061 | /* machhwsu - machhwsu. */ |
a750fc0b | 6062 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); |
76a66253 | 6063 | /* machhwsuo - machhwsuo. */ |
a750fc0b | 6064 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); |
76a66253 | 6065 | /* machhwu - machhwu. */ |
a750fc0b | 6066 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); |
76a66253 | 6067 | /* machhwuo - machhwuo. */ |
a750fc0b | 6068 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); |
76a66253 | 6069 | /* maclhw - maclhw. */ |
a750fc0b | 6070 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); |
76a66253 | 6071 | /* maclhwo - maclhwo. */ |
a750fc0b | 6072 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); |
76a66253 | 6073 | /* maclhws - maclhws. */ |
a750fc0b | 6074 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); |
76a66253 | 6075 | /* maclhwso - maclhwso. */ |
a750fc0b | 6076 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); |
76a66253 | 6077 | /* maclhwu - maclhwu. */ |
a750fc0b | 6078 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); |
76a66253 | 6079 | /* maclhwuo - maclhwuo. */ |
a750fc0b | 6080 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); |
76a66253 | 6081 | /* maclhwsu - maclhwsu. */ |
a750fc0b | 6082 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); |
76a66253 | 6083 | /* maclhwsuo - maclhwsuo. */ |
a750fc0b | 6084 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); |
76a66253 | 6085 | /* nmacchw - nmacchw. */ |
a750fc0b | 6086 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); |
76a66253 | 6087 | /* nmacchwo - nmacchwo. */ |
a750fc0b | 6088 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); |
76a66253 | 6089 | /* nmacchws - nmacchws. */ |
a750fc0b | 6090 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); |
76a66253 | 6091 | /* nmacchwso - nmacchwso. */ |
a750fc0b | 6092 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); |
76a66253 | 6093 | /* nmachhw - nmachhw. */ |
a750fc0b | 6094 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); |
76a66253 | 6095 | /* nmachhwo - nmachhwo. */ |
a750fc0b | 6096 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); |
76a66253 | 6097 | /* nmachhws - nmachhws. */ |
a750fc0b | 6098 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); |
76a66253 | 6099 | /* nmachhwso - nmachhwso. */ |
a750fc0b | 6100 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); |
76a66253 | 6101 | /* nmaclhw - nmaclhw. */ |
a750fc0b | 6102 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); |
76a66253 | 6103 | /* nmaclhwo - nmaclhwo. */ |
a750fc0b | 6104 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); |
76a66253 | 6105 | /* nmaclhws - nmaclhws. */ |
a750fc0b | 6106 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); |
76a66253 | 6107 | /* nmaclhwso - nmaclhwso. */ |
a750fc0b | 6108 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); |
76a66253 JM |
6109 | |
6110 | /* mulchw - mulchw. */ | |
a750fc0b | 6111 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05); |
76a66253 | 6112 | /* mulchwu - mulchwu. */ |
a750fc0b | 6113 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); |
76a66253 | 6114 | /* mulhhw - mulhhw. */ |
a750fc0b | 6115 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); |
76a66253 | 6116 | /* mulhhwu - mulhhwu. */ |
a750fc0b | 6117 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); |
76a66253 | 6118 | /* mullhw - mullhw. */ |
a750fc0b | 6119 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); |
76a66253 | 6120 | /* mullhwu - mullhwu. */ |
a750fc0b | 6121 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); |
76a66253 JM |
6122 | |
6123 | /* mfdcr */ | |
99e300ef | 6124 | static void gen_mfdcr(DisasContext *ctx) |
76a66253 JM |
6125 | { |
6126 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6127 | GEN_PRIV; |
76a66253 | 6128 | #else |
06dca6a7 | 6129 | TCGv dcrn; |
9b2fadda BH |
6130 | |
6131 | CHK_SV; | |
06dca6a7 | 6132 | dcrn = tcg_const_tl(SPR(ctx->opcode)); |
d0f1562d | 6133 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); |
06dca6a7 | 6134 | tcg_temp_free(dcrn); |
9b2fadda | 6135 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
6136 | } |
6137 | ||
6138 | /* mtdcr */ | |
99e300ef | 6139 | static void gen_mtdcr(DisasContext *ctx) |
76a66253 JM |
6140 | { |
6141 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6142 | GEN_PRIV; |
76a66253 | 6143 | #else |
06dca6a7 | 6144 | TCGv dcrn; |
9b2fadda BH |
6145 | |
6146 | CHK_SV; | |
06dca6a7 | 6147 | dcrn = tcg_const_tl(SPR(ctx->opcode)); |
d0f1562d | 6148 | gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); |
06dca6a7 | 6149 | tcg_temp_free(dcrn); |
9b2fadda | 6150 | #endif /* defined(CONFIG_USER_ONLY) */ |
a42bd6cc JM |
6151 | } |
6152 | ||
6153 | /* mfdcrx */ | |
2662a059 | 6154 | /* XXX: not implemented on 440 ? */ |
99e300ef | 6155 | static void gen_mfdcrx(DisasContext *ctx) |
a42bd6cc JM |
6156 | { |
6157 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6158 | GEN_PRIV; |
a42bd6cc | 6159 | #else |
9b2fadda | 6160 | CHK_SV; |
d0f1562d BS |
6161 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6162 | cpu_gpr[rA(ctx->opcode)]); | |
a750fc0b | 6163 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
9b2fadda | 6164 | #endif /* defined(CONFIG_USER_ONLY) */ |
a42bd6cc JM |
6165 | } |
6166 | ||
6167 | /* mtdcrx */ | |
2662a059 | 6168 | /* XXX: not implemented on 440 ? */ |
99e300ef | 6169 | static void gen_mtdcrx(DisasContext *ctx) |
a42bd6cc JM |
6170 | { |
6171 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6172 | GEN_PRIV; |
a42bd6cc | 6173 | #else |
9b2fadda | 6174 | CHK_SV; |
d0f1562d BS |
6175 | gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], |
6176 | cpu_gpr[rS(ctx->opcode)]); | |
a750fc0b | 6177 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
9b2fadda | 6178 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
6179 | } |
6180 | ||
a750fc0b | 6181 | /* mfdcrux (PPC 460) : user-mode access to DCR */ |
99e300ef | 6182 | static void gen_mfdcrux(DisasContext *ctx) |
a750fc0b | 6183 | { |
d0f1562d BS |
6184 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6185 | cpu_gpr[rA(ctx->opcode)]); | |
a750fc0b JM |
6186 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
6187 | } | |
6188 | ||
6189 | /* mtdcrux (PPC 460) : user-mode access to DCR */ | |
99e300ef | 6190 | static void gen_mtdcrux(DisasContext *ctx) |
a750fc0b | 6191 | { |
975e5463 | 6192 | gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], |
d0f1562d | 6193 | cpu_gpr[rS(ctx->opcode)]); |
a750fc0b JM |
6194 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
6195 | } | |
6196 | ||
76a66253 | 6197 | /* dccci */ |
99e300ef | 6198 | static void gen_dccci(DisasContext *ctx) |
76a66253 | 6199 | { |
9b2fadda | 6200 | CHK_SV; |
76a66253 | 6201 | /* interpreted as no-op */ |
76a66253 JM |
6202 | } |
6203 | ||
6204 | /* dcread */ | |
99e300ef | 6205 | static void gen_dcread(DisasContext *ctx) |
76a66253 JM |
6206 | { |
6207 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6208 | GEN_PRIV; |
76a66253 | 6209 | #else |
b61f2753 | 6210 | TCGv EA, val; |
9b2fadda BH |
6211 | |
6212 | CHK_SV; | |
76db3ba4 | 6213 | gen_set_access_type(ctx, ACCESS_CACHE); |
a7812ae4 | 6214 | EA = tcg_temp_new(); |
76db3ba4 | 6215 | gen_addr_reg_index(ctx, EA); |
a7812ae4 | 6216 | val = tcg_temp_new(); |
76db3ba4 | 6217 | gen_qemu_ld32u(ctx, val, EA); |
b61f2753 AJ |
6218 | tcg_temp_free(val); |
6219 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); | |
6220 | tcg_temp_free(EA); | |
9b2fadda | 6221 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
6222 | } |
6223 | ||
6224 | /* icbt */ | |
e8eaa2c0 | 6225 | static void gen_icbt_40x(DisasContext *ctx) |
76a66253 | 6226 | { |
efe843d8 DG |
6227 | /* |
6228 | * interpreted as no-op | |
6229 | * XXX: specification say this is treated as a load by the MMU but | |
6230 | * does not generate any exception | |
76a66253 JM |
6231 | */ |
6232 | } | |
6233 | ||
6234 | /* iccci */ | |
99e300ef | 6235 | static void gen_iccci(DisasContext *ctx) |
76a66253 | 6236 | { |
9b2fadda | 6237 | CHK_SV; |
76a66253 | 6238 | /* interpreted as no-op */ |
76a66253 JM |
6239 | } |
6240 | ||
6241 | /* icread */ | |
99e300ef | 6242 | static void gen_icread(DisasContext *ctx) |
76a66253 | 6243 | { |
9b2fadda | 6244 | CHK_SV; |
76a66253 | 6245 | /* interpreted as no-op */ |
76a66253 JM |
6246 | } |
6247 | ||
c47493f2 | 6248 | /* rfci (supervisor only) */ |
e8eaa2c0 | 6249 | static void gen_rfci_40x(DisasContext *ctx) |
a42bd6cc JM |
6250 | { |
6251 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6252 | GEN_PRIV; |
a42bd6cc | 6253 | #else |
9b2fadda | 6254 | CHK_SV; |
a42bd6cc | 6255 | /* Restore CPU state */ |
e5f17ac6 | 6256 | gen_helper_40x_rfci(cpu_env); |
e06fcd75 | 6257 | gen_sync_exception(ctx); |
9b2fadda | 6258 | #endif /* defined(CONFIG_USER_ONLY) */ |
a42bd6cc JM |
6259 | } |
6260 | ||
99e300ef | 6261 | static void gen_rfci(DisasContext *ctx) |
a42bd6cc JM |
6262 | { |
6263 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6264 | GEN_PRIV; |
a42bd6cc | 6265 | #else |
9b2fadda | 6266 | CHK_SV; |
a42bd6cc | 6267 | /* Restore CPU state */ |
e5f17ac6 | 6268 | gen_helper_rfci(cpu_env); |
e06fcd75 | 6269 | gen_sync_exception(ctx); |
9b2fadda | 6270 | #endif /* defined(CONFIG_USER_ONLY) */ |
a42bd6cc JM |
6271 | } |
6272 | ||
6273 | /* BookE specific */ | |
99e300ef | 6274 | |
54623277 | 6275 | /* XXX: not implemented on 440 ? */ |
99e300ef | 6276 | static void gen_rfdi(DisasContext *ctx) |
76a66253 JM |
6277 | { |
6278 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6279 | GEN_PRIV; |
76a66253 | 6280 | #else |
9b2fadda | 6281 | CHK_SV; |
76a66253 | 6282 | /* Restore CPU state */ |
e5f17ac6 | 6283 | gen_helper_rfdi(cpu_env); |
e06fcd75 | 6284 | gen_sync_exception(ctx); |
9b2fadda | 6285 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
6286 | } |
6287 | ||
2662a059 | 6288 | /* XXX: not implemented on 440 ? */ |
99e300ef | 6289 | static void gen_rfmci(DisasContext *ctx) |
a42bd6cc JM |
6290 | { |
6291 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6292 | GEN_PRIV; |
a42bd6cc | 6293 | #else |
9b2fadda | 6294 | CHK_SV; |
a42bd6cc | 6295 | /* Restore CPU state */ |
e5f17ac6 | 6296 | gen_helper_rfmci(cpu_env); |
e06fcd75 | 6297 | gen_sync_exception(ctx); |
9b2fadda | 6298 | #endif /* defined(CONFIG_USER_ONLY) */ |
a42bd6cc | 6299 | } |
5eb7995e | 6300 | |
d9bce9d9 | 6301 | /* TLB management - PowerPC 405 implementation */ |
e8eaa2c0 | 6302 | |
54623277 | 6303 | /* tlbre */ |
e8eaa2c0 | 6304 | static void gen_tlbre_40x(DisasContext *ctx) |
76a66253 JM |
6305 | { |
6306 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6307 | GEN_PRIV; |
76a66253 | 6308 | #else |
9b2fadda | 6309 | CHK_SV; |
76a66253 JM |
6310 | switch (rB(ctx->opcode)) { |
6311 | case 0: | |
c6c7cf05 BS |
6312 | gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6313 | cpu_gpr[rA(ctx->opcode)]); | |
76a66253 JM |
6314 | break; |
6315 | case 1: | |
c6c7cf05 BS |
6316 | gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6317 | cpu_gpr[rA(ctx->opcode)]); | |
76a66253 JM |
6318 | break; |
6319 | default: | |
e06fcd75 | 6320 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 | 6321 | break; |
9a64fbe4 | 6322 | } |
9b2fadda | 6323 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
6324 | } |
6325 | ||
d9bce9d9 | 6326 | /* tlbsx - tlbsx. */ |
e8eaa2c0 | 6327 | static void gen_tlbsx_40x(DisasContext *ctx) |
76a66253 JM |
6328 | { |
6329 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6330 | GEN_PRIV; |
76a66253 | 6331 | #else |
74d37793 | 6332 | TCGv t0; |
9b2fadda BH |
6333 | |
6334 | CHK_SV; | |
74d37793 | 6335 | t0 = tcg_temp_new(); |
76db3ba4 | 6336 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 6337 | gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 AJ |
6338 | tcg_temp_free(t0); |
6339 | if (Rc(ctx->opcode)) { | |
42a268c2 | 6340 | TCGLabel *l1 = gen_new_label(); |
da91a00f | 6341 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
74d37793 AJ |
6342 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); |
6343 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); | |
6344 | gen_set_label(l1); | |
6345 | } | |
9b2fadda | 6346 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
6347 | } |
6348 | ||
76a66253 | 6349 | /* tlbwe */ |
e8eaa2c0 | 6350 | static void gen_tlbwe_40x(DisasContext *ctx) |
79aceca5 | 6351 | { |
76a66253 | 6352 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 6353 | GEN_PRIV; |
76a66253 | 6354 | #else |
9b2fadda BH |
6355 | CHK_SV; |
6356 | ||
76a66253 JM |
6357 | switch (rB(ctx->opcode)) { |
6358 | case 0: | |
c6c7cf05 BS |
6359 | gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], |
6360 | cpu_gpr[rS(ctx->opcode)]); | |
76a66253 JM |
6361 | break; |
6362 | case 1: | |
c6c7cf05 BS |
6363 | gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], |
6364 | cpu_gpr[rS(ctx->opcode)]); | |
76a66253 JM |
6365 | break; |
6366 | default: | |
e06fcd75 | 6367 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 | 6368 | break; |
9a64fbe4 | 6369 | } |
9b2fadda | 6370 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
6371 | } |
6372 | ||
a4bb6c3e | 6373 | /* TLB management - PowerPC 440 implementation */ |
e8eaa2c0 | 6374 | |
54623277 | 6375 | /* tlbre */ |
e8eaa2c0 | 6376 | static void gen_tlbre_440(DisasContext *ctx) |
5eb7995e JM |
6377 | { |
6378 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6379 | GEN_PRIV; |
5eb7995e | 6380 | #else |
9b2fadda BH |
6381 | CHK_SV; |
6382 | ||
5eb7995e JM |
6383 | switch (rB(ctx->opcode)) { |
6384 | case 0: | |
5eb7995e | 6385 | case 1: |
5eb7995e | 6386 | case 2: |
74d37793 AJ |
6387 | { |
6388 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); | |
c6c7cf05 BS |
6389 | gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6390 | t0, cpu_gpr[rA(ctx->opcode)]); | |
74d37793 AJ |
6391 | tcg_temp_free_i32(t0); |
6392 | } | |
5eb7995e JM |
6393 | break; |
6394 | default: | |
e06fcd75 | 6395 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5eb7995e JM |
6396 | break; |
6397 | } | |
9b2fadda | 6398 | #endif /* defined(CONFIG_USER_ONLY) */ |
5eb7995e JM |
6399 | } |
6400 | ||
6401 | /* tlbsx - tlbsx. */ | |
e8eaa2c0 | 6402 | static void gen_tlbsx_440(DisasContext *ctx) |
5eb7995e JM |
6403 | { |
6404 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6405 | GEN_PRIV; |
5eb7995e | 6406 | #else |
74d37793 | 6407 | TCGv t0; |
9b2fadda BH |
6408 | |
6409 | CHK_SV; | |
74d37793 | 6410 | t0 = tcg_temp_new(); |
76db3ba4 | 6411 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 6412 | gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 AJ |
6413 | tcg_temp_free(t0); |
6414 | if (Rc(ctx->opcode)) { | |
42a268c2 | 6415 | TCGLabel *l1 = gen_new_label(); |
da91a00f | 6416 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
74d37793 AJ |
6417 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); |
6418 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); | |
6419 | gen_set_label(l1); | |
6420 | } | |
9b2fadda | 6421 | #endif /* defined(CONFIG_USER_ONLY) */ |
5eb7995e JM |
6422 | } |
6423 | ||
6424 | /* tlbwe */ | |
e8eaa2c0 | 6425 | static void gen_tlbwe_440(DisasContext *ctx) |
5eb7995e JM |
6426 | { |
6427 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6428 | GEN_PRIV; |
5eb7995e | 6429 | #else |
9b2fadda | 6430 | CHK_SV; |
5eb7995e JM |
6431 | switch (rB(ctx->opcode)) { |
6432 | case 0: | |
5eb7995e | 6433 | case 1: |
5eb7995e | 6434 | case 2: |
74d37793 AJ |
6435 | { |
6436 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); | |
c6c7cf05 BS |
6437 | gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], |
6438 | cpu_gpr[rS(ctx->opcode)]); | |
74d37793 AJ |
6439 | tcg_temp_free_i32(t0); |
6440 | } | |
5eb7995e JM |
6441 | break; |
6442 | default: | |
e06fcd75 | 6443 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5eb7995e JM |
6444 | break; |
6445 | } | |
9b2fadda | 6446 | #endif /* defined(CONFIG_USER_ONLY) */ |
5eb7995e JM |
6447 | } |
6448 | ||
01662f3e AG |
6449 | /* TLB management - PowerPC BookE 2.06 implementation */ |
6450 | ||
6451 | /* tlbre */ | |
6452 | static void gen_tlbre_booke206(DisasContext *ctx) | |
6453 | { | |
9b2fadda BH |
6454 | #if defined(CONFIG_USER_ONLY) |
6455 | GEN_PRIV; | |
01662f3e | 6456 | #else |
9b2fadda | 6457 | CHK_SV; |
c6c7cf05 | 6458 | gen_helper_booke206_tlbre(cpu_env); |
9b2fadda | 6459 | #endif /* defined(CONFIG_USER_ONLY) */ |
01662f3e AG |
6460 | } |
6461 | ||
6462 | /* tlbsx - tlbsx. */ | |
6463 | static void gen_tlbsx_booke206(DisasContext *ctx) | |
6464 | { | |
6465 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6466 | GEN_PRIV; |
01662f3e AG |
6467 | #else |
6468 | TCGv t0; | |
01662f3e | 6469 | |
9b2fadda | 6470 | CHK_SV; |
01662f3e AG |
6471 | if (rA(ctx->opcode)) { |
6472 | t0 = tcg_temp_new(); | |
6473 | tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); | |
6474 | } else { | |
6475 | t0 = tcg_const_tl(0); | |
6476 | } | |
6477 | ||
6478 | tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); | |
c6c7cf05 | 6479 | gen_helper_booke206_tlbsx(cpu_env, t0); |
c80d1df5 | 6480 | tcg_temp_free(t0); |
9b2fadda | 6481 | #endif /* defined(CONFIG_USER_ONLY) */ |
01662f3e AG |
6482 | } |
6483 | ||
6484 | /* tlbwe */ | |
6485 | static void gen_tlbwe_booke206(DisasContext *ctx) | |
6486 | { | |
6487 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6488 | GEN_PRIV; |
01662f3e | 6489 | #else |
9b2fadda | 6490 | CHK_SV; |
c6c7cf05 | 6491 | gen_helper_booke206_tlbwe(cpu_env); |
9b2fadda | 6492 | #endif /* defined(CONFIG_USER_ONLY) */ |
01662f3e AG |
6493 | } |
6494 | ||
6495 | static void gen_tlbivax_booke206(DisasContext *ctx) | |
6496 | { | |
6497 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6498 | GEN_PRIV; |
01662f3e AG |
6499 | #else |
6500 | TCGv t0; | |
01662f3e | 6501 | |
9b2fadda | 6502 | CHK_SV; |
01662f3e AG |
6503 | t0 = tcg_temp_new(); |
6504 | gen_addr_reg_index(ctx, t0); | |
c6c7cf05 | 6505 | gen_helper_booke206_tlbivax(cpu_env, t0); |
c80d1df5 | 6506 | tcg_temp_free(t0); |
9b2fadda | 6507 | #endif /* defined(CONFIG_USER_ONLY) */ |
01662f3e AG |
6508 | } |
6509 | ||
6d3db821 AG |
6510 | static void gen_tlbilx_booke206(DisasContext *ctx) |
6511 | { | |
6512 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6513 | GEN_PRIV; |
6d3db821 AG |
6514 | #else |
6515 | TCGv t0; | |
6d3db821 | 6516 | |
9b2fadda | 6517 | CHK_SV; |
6d3db821 AG |
6518 | t0 = tcg_temp_new(); |
6519 | gen_addr_reg_index(ctx, t0); | |
6520 | ||
efe843d8 | 6521 | switch ((ctx->opcode >> 21) & 0x3) { |
6d3db821 | 6522 | case 0: |
c6c7cf05 | 6523 | gen_helper_booke206_tlbilx0(cpu_env, t0); |
6d3db821 AG |
6524 | break; |
6525 | case 1: | |
c6c7cf05 | 6526 | gen_helper_booke206_tlbilx1(cpu_env, t0); |
6d3db821 AG |
6527 | break; |
6528 | case 3: | |
c6c7cf05 | 6529 | gen_helper_booke206_tlbilx3(cpu_env, t0); |
6d3db821 AG |
6530 | break; |
6531 | default: | |
6532 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
6533 | break; | |
6534 | } | |
6535 | ||
6536 | tcg_temp_free(t0); | |
9b2fadda | 6537 | #endif /* defined(CONFIG_USER_ONLY) */ |
6d3db821 AG |
6538 | } |
6539 | ||
01662f3e | 6540 | |
76a66253 | 6541 | /* wrtee */ |
99e300ef | 6542 | static void gen_wrtee(DisasContext *ctx) |
76a66253 JM |
6543 | { |
6544 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6545 | GEN_PRIV; |
76a66253 | 6546 | #else |
6527f6ea | 6547 | TCGv t0; |
9b2fadda BH |
6548 | |
6549 | CHK_SV; | |
6527f6ea AJ |
6550 | t0 = tcg_temp_new(); |
6551 | tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); | |
6552 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); | |
6553 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
6554 | tcg_temp_free(t0); | |
efe843d8 DG |
6555 | /* |
6556 | * Stop translation to have a chance to raise an exception if we | |
6557 | * just set msr_ee to 1 | |
dee96f6c | 6558 | */ |
e06fcd75 | 6559 | gen_stop_exception(ctx); |
9b2fadda | 6560 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
6561 | } |
6562 | ||
6563 | /* wrteei */ | |
99e300ef | 6564 | static void gen_wrteei(DisasContext *ctx) |
76a66253 JM |
6565 | { |
6566 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6567 | GEN_PRIV; |
76a66253 | 6568 | #else |
9b2fadda | 6569 | CHK_SV; |
fbe73008 | 6570 | if (ctx->opcode & 0x00008000) { |
6527f6ea AJ |
6571 | tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); |
6572 | /* Stop translation to have a chance to raise an exception */ | |
e06fcd75 | 6573 | gen_stop_exception(ctx); |
6527f6ea | 6574 | } else { |
1b6e5f99 | 6575 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); |
6527f6ea | 6576 | } |
9b2fadda | 6577 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
6578 | } |
6579 | ||
08e46e54 | 6580 | /* PowerPC 440 specific instructions */ |
99e300ef | 6581 | |
54623277 | 6582 | /* dlmzb */ |
99e300ef | 6583 | static void gen_dlmzb(DisasContext *ctx) |
76a66253 | 6584 | { |
ef0d51af | 6585 | TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); |
d15f74fb BS |
6586 | gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, |
6587 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); | |
ef0d51af | 6588 | tcg_temp_free_i32(t0); |
76a66253 JM |
6589 | } |
6590 | ||
6591 | /* mbar replaces eieio on 440 */ | |
99e300ef | 6592 | static void gen_mbar(DisasContext *ctx) |
76a66253 JM |
6593 | { |
6594 | /* interpreted as no-op */ | |
6595 | } | |
6596 | ||
6597 | /* msync replaces sync on 440 */ | |
dcb2b9e1 | 6598 | static void gen_msync_4xx(DisasContext *ctx) |
76a66253 | 6599 | { |
27a3ea7e BZ |
6600 | /* Only e500 seems to treat reserved bits as invalid */ |
6601 | if ((ctx->insns_flags2 & PPC2_BOOKE206) && | |
6602 | (ctx->opcode & 0x03FFF801)) { | |
6603 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
6604 | } | |
6605 | /* otherwise interpreted as no-op */ | |
76a66253 JM |
6606 | } |
6607 | ||
6608 | /* icbt */ | |
e8eaa2c0 | 6609 | static void gen_icbt_440(DisasContext *ctx) |
76a66253 | 6610 | { |
efe843d8 DG |
6611 | /* |
6612 | * interpreted as no-op | |
6613 | * XXX: specification say this is treated as a load by the MMU but | |
6614 | * does not generate any exception | |
76a66253 | 6615 | */ |
79aceca5 FB |
6616 | } |
6617 | ||
9e0b5cb1 AG |
6618 | /* Embedded.Processor Control */ |
6619 | ||
6620 | static void gen_msgclr(DisasContext *ctx) | |
6621 | { | |
6622 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6623 | GEN_PRIV; |
9e0b5cb1 | 6624 | #else |
ebca5e6d | 6625 | CHK_HV; |
d0db7cad | 6626 | if (is_book3s_arch2x(ctx)) { |
7af1e7b0 CLG |
6627 | gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
6628 | } else { | |
6629 | gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); | |
6630 | } | |
9b2fadda | 6631 | #endif /* defined(CONFIG_USER_ONLY) */ |
9e0b5cb1 AG |
6632 | } |
6633 | ||
d5d11a39 AG |
6634 | static void gen_msgsnd(DisasContext *ctx) |
6635 | { | |
6636 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6637 | GEN_PRIV; |
d5d11a39 | 6638 | #else |
ebca5e6d | 6639 | CHK_HV; |
d0db7cad | 6640 | if (is_book3s_arch2x(ctx)) { |
7af1e7b0 CLG |
6641 | gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]); |
6642 | } else { | |
6643 | gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); | |
6644 | } | |
9b2fadda | 6645 | #endif /* defined(CONFIG_USER_ONLY) */ |
d5d11a39 AG |
6646 | } |
6647 | ||
5ba7ba1d CLG |
6648 | #if defined(TARGET_PPC64) |
6649 | static void gen_msgclrp(DisasContext *ctx) | |
6650 | { | |
6651 | #if defined(CONFIG_USER_ONLY) | |
6652 | GEN_PRIV; | |
6653 | #else | |
6654 | CHK_SV; | |
6655 | gen_helper_book3s_msgclrp(cpu_env, cpu_gpr[rB(ctx->opcode)]); | |
6656 | #endif /* defined(CONFIG_USER_ONLY) */ | |
6657 | } | |
6658 | ||
6659 | static void gen_msgsndp(DisasContext *ctx) | |
6660 | { | |
6661 | #if defined(CONFIG_USER_ONLY) | |
6662 | GEN_PRIV; | |
6663 | #else | |
6664 | CHK_SV; | |
6665 | gen_helper_book3s_msgsndp(cpu_env, cpu_gpr[rB(ctx->opcode)]); | |
6666 | #endif /* defined(CONFIG_USER_ONLY) */ | |
6667 | } | |
6668 | #endif | |
6669 | ||
7af1e7b0 CLG |
6670 | static void gen_msgsync(DisasContext *ctx) |
6671 | { | |
6672 | #if defined(CONFIG_USER_ONLY) | |
6673 | GEN_PRIV; | |
6674 | #else | |
6675 | CHK_HV; | |
6676 | #endif /* defined(CONFIG_USER_ONLY) */ | |
6677 | /* interpreted as no-op */ | |
6678 | } | |
b04ae981 | 6679 | |
aeeb044c ND |
6680 | #if defined(TARGET_PPC64) |
6681 | static void gen_maddld(DisasContext *ctx) | |
6682 | { | |
6683 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
6684 | ||
6685 | tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
6686 | tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); | |
6687 | tcg_temp_free_i64(t1); | |
6688 | } | |
5f29cc82 ND |
6689 | |
6690 | /* maddhd maddhdu */ | |
6691 | static void gen_maddhd_maddhdu(DisasContext *ctx) | |
6692 | { | |
6693 | TCGv_i64 lo = tcg_temp_new_i64(); | |
6694 | TCGv_i64 hi = tcg_temp_new_i64(); | |
6695 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
6696 | ||
6697 | if (Rc(ctx->opcode)) { | |
6698 | tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], | |
6699 | cpu_gpr[rB(ctx->opcode)]); | |
6700 | tcg_gen_movi_i64(t1, 0); | |
6701 | } else { | |
6702 | tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], | |
6703 | cpu_gpr[rB(ctx->opcode)]); | |
6704 | tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); | |
6705 | } | |
6706 | tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, | |
6707 | cpu_gpr[rC(ctx->opcode)], t1); | |
6708 | tcg_temp_free_i64(lo); | |
6709 | tcg_temp_free_i64(hi); | |
6710 | tcg_temp_free_i64(t1); | |
6711 | } | |
aeeb044c ND |
6712 | #endif /* defined(TARGET_PPC64) */ |
6713 | ||
0ff93d11 TM |
6714 | static void gen_tbegin(DisasContext *ctx) |
6715 | { | |
6716 | if (unlikely(!ctx->tm_enabled)) { | |
6717 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); | |
6718 | return; | |
6719 | } | |
6720 | gen_helper_tbegin(cpu_env); | |
6721 | } | |
6722 | ||
56a84615 TM |
6723 | #define GEN_TM_NOOP(name) \ |
6724 | static inline void gen_##name(DisasContext *ctx) \ | |
6725 | { \ | |
6726 | if (unlikely(!ctx->tm_enabled)) { \ | |
6727 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ | |
6728 | return; \ | |
6729 | } \ | |
efe843d8 DG |
6730 | /* \ |
6731 | * Because tbegin always fails in QEMU, these user \ | |
56a84615 TM |
6732 | * space instructions all have a simple implementation: \ |
6733 | * \ | |
6734 | * CR[0] = 0b0 || MSR[TS] || 0b0 \ | |
6735 | * = 0b0 || 0b00 || 0b0 \ | |
6736 | */ \ | |
6737 | tcg_gen_movi_i32(cpu_crf[0], 0); \ | |
6738 | } | |
6739 | ||
6740 | GEN_TM_NOOP(tend); | |
6741 | GEN_TM_NOOP(tabort); | |
6742 | GEN_TM_NOOP(tabortwc); | |
6743 | GEN_TM_NOOP(tabortwci); | |
6744 | GEN_TM_NOOP(tabortdc); | |
6745 | GEN_TM_NOOP(tabortdci); | |
6746 | GEN_TM_NOOP(tsr); | |
efe843d8 | 6747 | |
b8b4576e SJS |
6748 | static inline void gen_cp_abort(DisasContext *ctx) |
6749 | { | |
efe843d8 | 6750 | /* Do Nothing */ |
b8b4576e | 6751 | } |
56a84615 | 6752 | |
80b8c1ee ND |
6753 | #define GEN_CP_PASTE_NOOP(name) \ |
6754 | static inline void gen_##name(DisasContext *ctx) \ | |
6755 | { \ | |
efe843d8 DG |
6756 | /* \ |
6757 | * Generate invalid exception until we have an \ | |
6758 | * implementation of the copy paste facility \ | |
80b8c1ee ND |
6759 | */ \ |
6760 | gen_invalid(ctx); \ | |
6761 | } | |
6762 | ||
6763 | GEN_CP_PASTE_NOOP(copy) | |
6764 | GEN_CP_PASTE_NOOP(paste) | |
6765 | ||
aeedd582 TM |
6766 | static void gen_tcheck(DisasContext *ctx) |
6767 | { | |
6768 | if (unlikely(!ctx->tm_enabled)) { | |
6769 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); | |
6770 | return; | |
6771 | } | |
efe843d8 DG |
6772 | /* |
6773 | * Because tbegin always fails, the tcheck implementation is | |
6774 | * simple: | |
aeedd582 TM |
6775 | * |
6776 | * CR[CRF] = TDOOMED || MSR[TS] || 0b0 | |
6777 | * = 0b1 || 0b00 || 0b0 | |
6778 | */ | |
6779 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); | |
6780 | } | |
6781 | ||
f83c2378 TM |
6782 | #if defined(CONFIG_USER_ONLY) |
6783 | #define GEN_TM_PRIV_NOOP(name) \ | |
6784 | static inline void gen_##name(DisasContext *ctx) \ | |
6785 | { \ | |
efe843d8 | 6786 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ |
f83c2378 TM |
6787 | } |
6788 | ||
6789 | #else | |
6790 | ||
6791 | #define GEN_TM_PRIV_NOOP(name) \ | |
6792 | static inline void gen_##name(DisasContext *ctx) \ | |
6793 | { \ | |
9b2fadda | 6794 | CHK_SV; \ |
f83c2378 TM |
6795 | if (unlikely(!ctx->tm_enabled)) { \ |
6796 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ | |
6797 | return; \ | |
6798 | } \ | |
efe843d8 DG |
6799 | /* \ |
6800 | * Because tbegin always fails, the implementation is \ | |
f83c2378 TM |
6801 | * simple: \ |
6802 | * \ | |
6803 | * CR[0] = 0b0 || MSR[TS] || 0b0 \ | |
6804 | * = 0b0 || 0b00 | 0b0 \ | |
6805 | */ \ | |
6806 | tcg_gen_movi_i32(cpu_crf[0], 0); \ | |
6807 | } | |
6808 | ||
6809 | #endif | |
6810 | ||
6811 | GEN_TM_PRIV_NOOP(treclaim); | |
6812 | GEN_TM_PRIV_NOOP(trechkpt); | |
6813 | ||
1a404c91 MCA |
6814 | static inline void get_fpr(TCGv_i64 dst, int regno) |
6815 | { | |
e7d3b272 | 6816 | tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); |
1a404c91 MCA |
6817 | } |
6818 | ||
6819 | static inline void set_fpr(int regno, TCGv_i64 src) | |
6820 | { | |
e7d3b272 | 6821 | tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); |
1a404c91 MCA |
6822 | } |
6823 | ||
c4a18dbf MCA |
6824 | static inline void get_avr64(TCGv_i64 dst, int regno, bool high) |
6825 | { | |
37da91f1 | 6826 | tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); |
c4a18dbf MCA |
6827 | } |
6828 | ||
6829 | static inline void set_avr64(int regno, TCGv_i64 src, bool high) | |
6830 | { | |
37da91f1 | 6831 | tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); |
c4a18dbf MCA |
6832 | } |
6833 | ||
15848410 BH |
6834 | #include "translate/fp-impl.inc.c" |
6835 | ||
6836 | #include "translate/vmx-impl.inc.c" | |
6837 | ||
6838 | #include "translate/vsx-impl.inc.c" | |
6839 | ||
6840 | #include "translate/dfp-impl.inc.c" | |
6841 | ||
6842 | #include "translate/spe-impl.inc.c" | |
6843 | ||
5cb091a4 ND |
6844 | /* Handles lfdp, lxsd, lxssp */ |
6845 | static void gen_dform39(DisasContext *ctx) | |
6846 | { | |
6847 | switch (ctx->opcode & 0x3) { | |
6848 | case 0: /* lfdp */ | |
6849 | if (ctx->insns_flags2 & PPC2_ISA205) { | |
6850 | return gen_lfdp(ctx); | |
6851 | } | |
6852 | break; | |
6853 | case 2: /* lxsd */ | |
6854 | if (ctx->insns_flags2 & PPC2_ISA300) { | |
6855 | return gen_lxsd(ctx); | |
6856 | } | |
6857 | break; | |
6858 | case 3: /* lxssp */ | |
6859 | if (ctx->insns_flags2 & PPC2_ISA300) { | |
6860 | return gen_lxssp(ctx); | |
6861 | } | |
6862 | break; | |
6863 | } | |
6864 | return gen_invalid(ctx); | |
6865 | } | |
6866 | ||
d59ba583 | 6867 | /* handles stfdp, lxv, stxsd, stxssp lxvx */ |
e3001664 ND |
6868 | static void gen_dform3D(DisasContext *ctx) |
6869 | { | |
6870 | if ((ctx->opcode & 3) == 1) { /* DQ-FORM */ | |
6871 | switch (ctx->opcode & 0x7) { | |
6872 | case 1: /* lxv */ | |
d59ba583 ND |
6873 | if (ctx->insns_flags2 & PPC2_ISA300) { |
6874 | return gen_lxv(ctx); | |
6875 | } | |
e3001664 ND |
6876 | break; |
6877 | case 5: /* stxv */ | |
d59ba583 ND |
6878 | if (ctx->insns_flags2 & PPC2_ISA300) { |
6879 | return gen_stxv(ctx); | |
6880 | } | |
e3001664 ND |
6881 | break; |
6882 | } | |
6883 | } else { /* DS-FORM */ | |
6884 | switch (ctx->opcode & 0x3) { | |
6885 | case 0: /* stfdp */ | |
6886 | if (ctx->insns_flags2 & PPC2_ISA205) { | |
6887 | return gen_stfdp(ctx); | |
6888 | } | |
6889 | break; | |
6890 | case 2: /* stxsd */ | |
6891 | if (ctx->insns_flags2 & PPC2_ISA300) { | |
6892 | return gen_stxsd(ctx); | |
6893 | } | |
6894 | break; | |
6895 | case 3: /* stxssp */ | |
6896 | if (ctx->insns_flags2 & PPC2_ISA300) { | |
6897 | return gen_stxssp(ctx); | |
6898 | } | |
6899 | break; | |
6900 | } | |
6901 | } | |
6902 | return gen_invalid(ctx); | |
6903 | } | |
6904 | ||
c227f099 | 6905 | static opcode_t opcodes[] = { |
5c55ff99 BS |
6906 | GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), |
6907 | GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), | |
6908 | GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), | |
4aaefd93 | 6909 | GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER), |
5c55ff99 | 6910 | GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), |
082ce330 ND |
6911 | #if defined(TARGET_PPC64) |
6912 | GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), | |
6913 | #endif | |
fcfda20f | 6914 | GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), |
f2442ef9 | 6915 | GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), |
5c55ff99 BS |
6916 | GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), |
6917 | GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6918 | GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6919 | GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6920 | GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
c5b2b9ce | 6921 | GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), |
5c55ff99 BS |
6922 | GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), |
6923 | GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), | |
6924 | GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), | |
6925 | GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), | |
6926 | GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6927 | #if defined(TARGET_PPC64) | |
6928 | GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), | |
6929 | #endif | |
6930 | GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), | |
6931 | GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), | |
6932 | GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6933 | GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6934 | GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6935 | GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), | |
b35344e4 | 6936 | GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), |
80b8c1ee | 6937 | GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), |
b8b4576e | 6938 | GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), |
80b8c1ee | 6939 | GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), |
5c55ff99 BS |
6940 | GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), |
6941 | GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), | |
6942 | GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6943 | GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6944 | GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6945 | GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6ab39b1b | 6946 | GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), |
eaabeef2 | 6947 | GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), |
725bcec2 | 6948 | GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), |
5c55ff99 | 6949 | #if defined(TARGET_PPC64) |
eaabeef2 | 6950 | GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), |
5c55ff99 | 6951 | GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), |
e91d95b2 | 6952 | GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), |
fec5c62a | 6953 | GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), |
725bcec2 | 6954 | GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), |
86ba37ed | 6955 | GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), |
5c55ff99 BS |
6956 | #endif |
6957 | GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6958 | GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6959 | GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6960 | GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), | |
6961 | GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), | |
6962 | GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), | |
6963 | GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), | |
6964 | #if defined(TARGET_PPC64) | |
6965 | GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), | |
6966 | GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), | |
6967 | GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), | |
6968 | GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), | |
6969 | GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), | |
787bbe37 ND |
6970 | GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, |
6971 | PPC_NONE, PPC2_ISA300), | |
6972 | GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, | |
6973 | PPC_NONE, PPC2_ISA300), | |
5c55ff99 | 6974 | #endif |
5c55ff99 BS |
6975 | #if defined(TARGET_PPC64) |
6976 | GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
6977 | GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), | |
6978 | GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
6979 | #endif | |
5cb091a4 ND |
6980 | /* handles lfdp, lxsd, lxssp */ |
6981 | GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), | |
d59ba583 | 6982 | /* handles stfdp, lxv, stxsd, stxssp, stxv */ |
e3001664 | 6983 | GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), |
5c55ff99 BS |
6984 | GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
6985 | GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6986 | GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), | |
6987 | GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), | |
6988 | GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), | |
6989 | GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), | |
c8fd8373 | 6990 | GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), |
5c55ff99 | 6991 | GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), |
5c77a786 TM |
6992 | GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), |
6993 | GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), | |
f844c817 | 6994 | GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), |
a68a6146 | 6995 | GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), |
a3401188 | 6996 | GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), |
587c51f7 TM |
6997 | GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), |
6998 | GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), | |
5c55ff99 BS |
6999 | GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), |
7000 | #if defined(TARGET_PPC64) | |
a68a6146 | 7001 | GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), |
a3401188 | 7002 | GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), |
f844c817 | 7003 | GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), |
9c294d5a | 7004 | GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), |
5c55ff99 | 7005 | GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), |
27b95bfe | 7006 | GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), |
5c55ff99 BS |
7007 | #endif |
7008 | GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), | |
7009 | GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), | |
c09cec68 | 7010 | GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300), |
5c55ff99 BS |
7011 | GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), |
7012 | GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
7013 | GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), | |
7014 | GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), | |
4aaefd93 | 7015 | GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), |
5c55ff99 BS |
7016 | GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), |
7017 | GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), | |
7018 | #if defined(TARGET_PPC64) | |
7019 | GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), | |
cdee0e72 | 7020 | GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), |
7778a575 BH |
7021 | GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), |
7022 | GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), | |
7023 | GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), | |
7024 | GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), | |
5c55ff99 BS |
7025 | GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), |
7026 | #endif | |
7027 | GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW), | |
7028 | GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), | |
7029 | GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
7030 | #if defined(TARGET_PPC64) | |
7031 | GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), | |
7032 | GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
7033 | #endif | |
7034 | GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), | |
7035 | GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), | |
7036 | GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), | |
7037 | GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), | |
7038 | GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), | |
7039 | GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), | |
7040 | #if defined(TARGET_PPC64) | |
7041 | GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), | |
dc2ee038 | 7042 | GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), |
b63d0434 | 7043 | GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), |
5c55ff99 | 7044 | #endif |
5e31867f | 7045 | GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), |
4248b336 | 7046 | GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), |
5c55ff99 | 7047 | GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), |
50728199 | 7048 | GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), |
5c55ff99 BS |
7049 | GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), |
7050 | GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), | |
50728199 | 7051 | GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), |
3f34cf91 | 7052 | GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), |
50728199 | 7053 | GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), |
3f34cf91 | 7054 | GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), |
50728199 | 7055 | GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), |
4d09d529 | 7056 | GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), |
8e33944f | 7057 | GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), |
50728199 | 7058 | GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), |
5c55ff99 | 7059 | GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), |
99d45f8f | 7060 | GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), |
5c55ff99 BS |
7061 | GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), |
7062 | GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), | |
50728199 | 7063 | GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), |
5c55ff99 BS |
7064 | GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), |
7065 | GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), | |
7066 | GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), | |
7067 | GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), | |
7068 | GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), | |
7069 | #if defined(TARGET_PPC64) | |
7070 | GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), | |
7071 | GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, | |
7072 | PPC_SEGMENT_64B), | |
7073 | GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), | |
7074 | GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, | |
7075 | PPC_SEGMENT_64B), | |
efdef95f DG |
7076 | GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), |
7077 | GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), | |
7078 | GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), | |
c76c22d5 | 7079 | GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), |
5c55ff99 BS |
7080 | #endif |
7081 | GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), | |
efe843d8 DG |
7082 | /* |
7083 | * XXX Those instructions will need to be handled differently for | |
7084 | * different ISA versions | |
7085 | */ | |
f9ef0527 BH |
7086 | GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), |
7087 | GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), | |
c8830502 SJS |
7088 | GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300), |
7089 | GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300), | |
5c55ff99 BS |
7090 | GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), |
7091 | #if defined(TARGET_PPC64) | |
2f9254d9 | 7092 | GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), |
5c55ff99 | 7093 | GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), |
a63f1dfc | 7094 | GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300), |
62d897ca | 7095 | GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300), |
5c55ff99 BS |
7096 | #endif |
7097 | GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), | |
7098 | GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), | |
7099 | GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), | |
7100 | GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), | |
7101 | GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), | |
7102 | GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), | |
7103 | GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), | |
7104 | GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), | |
7105 | GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), | |
7106 | GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), | |
7107 | GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), | |
7108 | GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), | |
7109 | GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), | |
7110 | GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), | |
7111 | GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), | |
7112 | GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), | |
7113 | GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), | |
7114 | GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), | |
7115 | GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), | |
7116 | GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), | |
7117 | GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), | |
7118 | GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), | |
7119 | GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), | |
7120 | GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), | |
7121 | GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), | |
7122 | GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), | |
7123 | GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), | |
7124 | GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), | |
7125 | GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), | |
7126 | GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), | |
7127 | GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), | |
7128 | GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), | |
7129 | GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), | |
7130 | GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), | |
7131 | GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), | |
7132 | GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), | |
7133 | GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), | |
7134 | GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), | |
7135 | GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), | |
7136 | GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), | |
7137 | GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), | |
7138 | GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), | |
7139 | GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), | |
7140 | GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), | |
7141 | GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), | |
7142 | GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), | |
7143 | GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), | |
7144 | GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), | |
7145 | GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), | |
7146 | GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
7147 | GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
7148 | GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), | |
7149 | GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), | |
7150 | GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
7151 | GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
7152 | GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), | |
7153 | GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), | |
7154 | GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), | |
7155 | GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), | |
7156 | GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), | |
7157 | GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), | |
7158 | GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), | |
7159 | GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), | |
7160 | GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), | |
7161 | GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), | |
7162 | GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), | |
7163 | GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), | |
7164 | GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), | |
7165 | GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), | |
7166 | GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), | |
7167 | GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), | |
01662f3e | 7168 | GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), |
5c55ff99 BS |
7169 | GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), |
7170 | GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), | |
7171 | GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), | |
7172 | GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), | |
7173 | GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), | |
7174 | GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), | |
7175 | GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), | |
7176 | GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), | |
01662f3e AG |
7177 | GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, |
7178 | PPC_NONE, PPC2_BOOKE206), | |
7179 | GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, | |
7180 | PPC_NONE, PPC2_BOOKE206), | |
7181 | GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, | |
7182 | PPC_NONE, PPC2_BOOKE206), | |
7183 | GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, | |
7184 | PPC_NONE, PPC2_BOOKE206), | |
6d3db821 AG |
7185 | GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, |
7186 | PPC_NONE, PPC2_BOOKE206), | |
d5d11a39 AG |
7187 | GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, |
7188 | PPC_NONE, PPC2_PRCNTL), | |
9e0b5cb1 AG |
7189 | GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, |
7190 | PPC_NONE, PPC2_PRCNTL), | |
7af1e7b0 CLG |
7191 | GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000, |
7192 | PPC_NONE, PPC2_PRCNTL), | |
5c55ff99 | 7193 | GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), |
fbe73008 | 7194 | GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), |
5c55ff99 | 7195 | GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), |
01662f3e AG |
7196 | GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, |
7197 | PPC_BOOKE, PPC2_BOOKE206), | |
27a3ea7e | 7198 | GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), |
01662f3e AG |
7199 | GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, |
7200 | PPC_BOOKE, PPC2_BOOKE206), | |
0c8d8c8b | 7201 | GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, |
27a3ea7e | 7202 | PPC_440_SPEC), |
5c55ff99 BS |
7203 | GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), |
7204 | GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), | |
7205 | GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), | |
7206 | GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), | |
5c55ff99 | 7207 | GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), |
aeeb044c | 7208 | #if defined(TARGET_PPC64) |
5f29cc82 ND |
7209 | GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, |
7210 | PPC2_ISA300), | |
aeeb044c | 7211 | GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), |
5ba7ba1d CLG |
7212 | GEN_HANDLER2_E(msgsndp, "msgsndp", 0x1F, 0x0E, 0x04, 0x03ff0001, |
7213 | PPC_NONE, PPC2_ISA207S), | |
7214 | GEN_HANDLER2_E(msgclrp, "msgclrp", 0x1F, 0x0E, 0x05, 0x03ff0001, | |
7215 | PPC_NONE, PPC2_ISA207S), | |
aeeb044c | 7216 | #endif |
5c55ff99 BS |
7217 | |
7218 | #undef GEN_INT_ARITH_ADD | |
7219 | #undef GEN_INT_ARITH_ADD_CONST | |
7220 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ | |
7221 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), | |
7222 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ | |
7223 | add_ca, compute_ca, compute_ov) \ | |
7224 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), | |
7225 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) | |
7226 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) | |
7227 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) | |
7228 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) | |
7229 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) | |
7230 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) | |
7231 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) | |
7232 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) | |
4c5920af | 7233 | GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), |
5c55ff99 BS |
7234 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) |
7235 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) | |
7236 | ||
7237 | #undef GEN_INT_ARITH_DIVW | |
7238 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ | |
7239 | GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) | |
7240 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), | |
7241 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), | |
7242 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), | |
7243 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), | |
a98eb9e9 TM |
7244 | GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), |
7245 | GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
6a4fda33 TM |
7246 | GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), |
7247 | GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
af2c6620 ND |
7248 | GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), |
7249 | GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), | |
5c55ff99 BS |
7250 | |
7251 | #if defined(TARGET_PPC64) | |
7252 | #undef GEN_INT_ARITH_DIVD | |
7253 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ | |
7254 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) | |
7255 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), | |
7256 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), | |
7257 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), | |
7258 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), | |
7259 | ||
98d1eb27 TM |
7260 | GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), |
7261 | GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
e44259b6 TM |
7262 | GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), |
7263 | GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
063cf14f ND |
7264 | GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), |
7265 | GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), | |
98d1eb27 | 7266 | |
5c55ff99 BS |
7267 | #undef GEN_INT_ARITH_MUL_HELPER |
7268 | #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ | |
7269 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) | |
7270 | GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), | |
7271 | GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), | |
7272 | GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), | |
7273 | #endif | |
7274 | ||
7275 | #undef GEN_INT_ARITH_SUBF | |
7276 | #undef GEN_INT_ARITH_SUBF_CONST | |
7277 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ | |
7278 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), | |
7279 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ | |
7280 | add_ca, compute_ca, compute_ov) \ | |
7281 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), | |
7282 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) | |
7283 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) | |
7284 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) | |
7285 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) | |
7286 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) | |
7287 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) | |
7288 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) | |
7289 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) | |
7290 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) | |
7291 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) | |
7292 | ||
7293 | #undef GEN_LOGICAL1 | |
7294 | #undef GEN_LOGICAL2 | |
7295 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ | |
7296 | GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) | |
7297 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ | |
7298 | GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) | |
7299 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), | |
7300 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), | |
7301 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), | |
7302 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), | |
7303 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), | |
7304 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), | |
7305 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), | |
7306 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), | |
7307 | #if defined(TARGET_PPC64) | |
7308 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), | |
7309 | #endif | |
7310 | ||
7311 | #if defined(TARGET_PPC64) | |
7312 | #undef GEN_PPC64_R2 | |
7313 | #undef GEN_PPC64_R4 | |
7314 | #define GEN_PPC64_R2(name, opc1, opc2) \ | |
7315 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ | |
7316 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ | |
7317 | PPC_64B) | |
7318 | #define GEN_PPC64_R4(name, opc1, opc2) \ | |
7319 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ | |
7320 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ | |
7321 | PPC_64B), \ | |
7322 | GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ | |
7323 | PPC_64B), \ | |
7324 | GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ | |
7325 | PPC_64B) | |
7326 | GEN_PPC64_R4(rldicl, 0x1E, 0x00), | |
7327 | GEN_PPC64_R4(rldicr, 0x1E, 0x02), | |
7328 | GEN_PPC64_R4(rldic, 0x1E, 0x04), | |
7329 | GEN_PPC64_R2(rldcl, 0x1E, 0x08), | |
7330 | GEN_PPC64_R2(rldcr, 0x1E, 0x09), | |
7331 | GEN_PPC64_R4(rldimi, 0x1E, 0x06), | |
7332 | #endif | |
7333 | ||
5c55ff99 BS |
7334 | #undef GEN_LD |
7335 | #undef GEN_LDU | |
7336 | #undef GEN_LDUX | |
cd6e9320 | 7337 | #undef GEN_LDX_E |
5c55ff99 BS |
7338 | #undef GEN_LDS |
7339 | #define GEN_LD(name, ldop, opc, type) \ | |
7340 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
7341 | #define GEN_LDU(name, ldop, opc, type) \ | |
7342 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
7343 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \ | |
7344 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), | |
b7815375 | 7345 | #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ |
cd6e9320 | 7346 | GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), |
5c55ff99 BS |
7347 | #define GEN_LDS(name, ldop, op, type) \ |
7348 | GEN_LD(name, ldop, op | 0x20, type) \ | |
7349 | GEN_LDU(name, ldop, op | 0x21, type) \ | |
7350 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ | |
7351 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) | |
7352 | ||
7353 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) | |
7354 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) | |
7355 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) | |
7356 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) | |
7357 | #if defined(TARGET_PPC64) | |
7358 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) | |
7359 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) | |
4f364fe7 ND |
7360 | GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B) |
7361 | GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B) | |
ff5f3981 | 7362 | GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) |
b7815375 BH |
7363 | |
7364 | /* HV/P7 and later only */ | |
4f364fe7 | 7365 | GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) |
b7815375 BH |
7366 | GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) |
7367 | GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) | |
7368 | GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) | |
5c55ff99 BS |
7369 | #endif |
7370 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) | |
7371 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) | |
7372 | ||
50728199 RK |
7373 | /* External PID based load */ |
7374 | #undef GEN_LDEPX | |
7375 | #define GEN_LDEPX(name, ldop, opc2, opc3) \ | |
7376 | GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ | |
7377 | 0x00000001, PPC_NONE, PPC2_BOOKE206), | |
7378 | ||
7379 | GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) | |
7380 | GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) | |
7381 | GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) | |
7382 | #if defined(TARGET_PPC64) | |
7383 | GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) | |
7384 | #endif | |
7385 | ||
5c55ff99 BS |
7386 | #undef GEN_ST |
7387 | #undef GEN_STU | |
7388 | #undef GEN_STUX | |
cd6e9320 | 7389 | #undef GEN_STX_E |
5c55ff99 BS |
7390 | #undef GEN_STS |
7391 | #define GEN_ST(name, stop, opc, type) \ | |
7392 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
7393 | #define GEN_STU(name, stop, opc, type) \ | |
7394 | GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
7395 | #define GEN_STUX(name, stop, opc2, opc3, type) \ | |
7396 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), | |
b7815375 | 7397 | #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ |
0123d3cb | 7398 | GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), |
5c55ff99 BS |
7399 | #define GEN_STS(name, stop, op, type) \ |
7400 | GEN_ST(name, stop, op | 0x20, type) \ | |
7401 | GEN_STU(name, stop, op | 0x21, type) \ | |
7402 | GEN_STUX(name, stop, 0x17, op | 0x01, type) \ | |
7403 | GEN_STX(name, stop, 0x17, op | 0x00, type) | |
7404 | ||
7405 | GEN_STS(stb, st8, 0x06, PPC_INTEGER) | |
7406 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER) | |
7407 | GEN_STS(stw, st32, 0x04, PPC_INTEGER) | |
7408 | #if defined(TARGET_PPC64) | |
2468f23d ND |
7409 | GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B) |
7410 | GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B) | |
804108aa | 7411 | GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) |
2468f23d | 7412 | GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) |
b7815375 BH |
7413 | GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) |
7414 | GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) | |
7415 | GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) | |
5c55ff99 BS |
7416 | #endif |
7417 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) | |
7418 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) | |
7419 | ||
50728199 RK |
7420 | #undef GEN_STEPX |
7421 | #define GEN_STEPX(name, ldop, opc2, opc3) \ | |
7422 | GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ | |
7423 | 0x00000001, PPC_NONE, PPC2_BOOKE206), | |
7424 | ||
7425 | GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) | |
7426 | GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) | |
7427 | GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) | |
7428 | #if defined(TARGET_PPC64) | |
7429 | GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1D, 0x04) | |
7430 | #endif | |
7431 | ||
5c55ff99 BS |
7432 | #undef GEN_CRLOGIC |
7433 | #define GEN_CRLOGIC(name, tcg_op, opc) \ | |
7434 | GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) | |
7435 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), | |
7436 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), | |
7437 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), | |
7438 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), | |
7439 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), | |
7440 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), | |
7441 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), | |
7442 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), | |
7443 | ||
7444 | #undef GEN_MAC_HANDLER | |
7445 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ | |
7446 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) | |
7447 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05), | |
7448 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), | |
7449 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07), | |
7450 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), | |
7451 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), | |
7452 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), | |
7453 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), | |
7454 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), | |
7455 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01), | |
7456 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), | |
7457 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03), | |
7458 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), | |
7459 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), | |
7460 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), | |
7461 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), | |
7462 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), | |
7463 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), | |
7464 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), | |
7465 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), | |
7466 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), | |
7467 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), | |
7468 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), | |
7469 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), | |
7470 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), | |
7471 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), | |
7472 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), | |
7473 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), | |
7474 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), | |
7475 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), | |
7476 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), | |
7477 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), | |
7478 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), | |
7479 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), | |
7480 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), | |
7481 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), | |
7482 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), | |
7483 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05), | |
7484 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), | |
7485 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), | |
7486 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), | |
7487 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), | |
7488 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), | |
7489 | ||
0ff93d11 TM |
7490 | GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ |
7491 | PPC_NONE, PPC2_TM), | |
56a84615 TM |
7492 | GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ |
7493 | PPC_NONE, PPC2_TM), | |
7494 | GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ | |
7495 | PPC_NONE, PPC2_TM), | |
7496 | GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ | |
7497 | PPC_NONE, PPC2_TM), | |
7498 | GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ | |
7499 | PPC_NONE, PPC2_TM), | |
7500 | GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ | |
7501 | PPC_NONE, PPC2_TM), | |
7502 | GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ | |
7503 | PPC_NONE, PPC2_TM), | |
7504 | GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ | |
7505 | PPC_NONE, PPC2_TM), | |
aeedd582 TM |
7506 | GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ |
7507 | PPC_NONE, PPC2_TM), | |
f83c2378 TM |
7508 | GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ |
7509 | PPC_NONE, PPC2_TM), | |
7510 | GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ | |
7511 | PPC_NONE, PPC2_TM), | |
15848410 BH |
7512 | |
7513 | #include "translate/fp-ops.inc.c" | |
7514 | ||
7515 | #include "translate/vmx-ops.inc.c" | |
7516 | ||
7517 | #include "translate/vsx-ops.inc.c" | |
7518 | ||
7519 | #include "translate/dfp-ops.inc.c" | |
7520 | ||
7521 | #include "translate/spe-ops.inc.c" | |
5c55ff99 BS |
7522 | }; |
7523 | ||
0411a972 | 7524 | #include "helper_regs.h" |
5b27a92d | 7525 | #include "translate_init.inc.c" |
79aceca5 | 7526 | |
9a64fbe4 | 7527 | /*****************************************************************************/ |
3fc6c082 | 7528 | /* Misc PowerPC helpers */ |
90c84c56 | 7529 | void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) |
79aceca5 | 7530 | { |
3fc6c082 FB |
7531 | #define RGPL 4 |
7532 | #define RFPL 4 | |
3fc6c082 | 7533 | |
878096ee AF |
7534 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
7535 | CPUPPCState *env = &cpu->env; | |
79aceca5 FB |
7536 | int i; |
7537 | ||
90c84c56 MA |
7538 | qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " |
7539 | TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", | |
7540 | env->nip, env->lr, env->ctr, cpu_read_xer(env), | |
7541 | cs->cpu_index); | |
7542 | qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " | |
7543 | TARGET_FMT_lx " iidx %d didx %d\n", | |
7544 | env->msr, env->spr[SPR_HID0], | |
7545 | env->hflags, env->immu_idx, env->dmmu_idx); | |
d9bce9d9 | 7546 | #if !defined(NO_TIMER_DUMP) |
90c84c56 | 7547 | qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 |
76a66253 | 7548 | #if !defined(CONFIG_USER_ONLY) |
90c84c56 | 7549 | " DECR " TARGET_FMT_lu |
76a66253 | 7550 | #endif |
90c84c56 MA |
7551 | "\n", |
7552 | cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) | |
76a66253 | 7553 | #if !defined(CONFIG_USER_ONLY) |
90c84c56 | 7554 | , cpu_ppc_load_decr(env) |
76a66253 | 7555 | #endif |
90c84c56 | 7556 | ); |
077fc206 | 7557 | #endif |
76a66253 | 7558 | for (i = 0; i < 32; i++) { |
efe843d8 | 7559 | if ((i & (RGPL - 1)) == 0) { |
90c84c56 | 7560 | qemu_fprintf(f, "GPR%02d", i); |
efe843d8 | 7561 | } |
90c84c56 | 7562 | qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); |
efe843d8 | 7563 | if ((i & (RGPL - 1)) == (RGPL - 1)) { |
90c84c56 | 7564 | qemu_fprintf(f, "\n"); |
efe843d8 | 7565 | } |
76a66253 | 7566 | } |
90c84c56 | 7567 | qemu_fprintf(f, "CR "); |
76a66253 | 7568 | for (i = 0; i < 8; i++) |
90c84c56 MA |
7569 | qemu_fprintf(f, "%01x", env->crf[i]); |
7570 | qemu_fprintf(f, " ["); | |
76a66253 JM |
7571 | for (i = 0; i < 8; i++) { |
7572 | char a = '-'; | |
efe843d8 | 7573 | if (env->crf[i] & 0x08) { |
76a66253 | 7574 | a = 'L'; |
efe843d8 | 7575 | } else if (env->crf[i] & 0x04) { |
76a66253 | 7576 | a = 'G'; |
efe843d8 | 7577 | } else if (env->crf[i] & 0x02) { |
76a66253 | 7578 | a = 'E'; |
efe843d8 | 7579 | } |
90c84c56 | 7580 | qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); |
76a66253 | 7581 | } |
90c84c56 MA |
7582 | qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", |
7583 | env->reserve_addr); | |
685f1ce2 RH |
7584 | |
7585 | if (flags & CPU_DUMP_FPU) { | |
7586 | for (i = 0; i < 32; i++) { | |
7587 | if ((i & (RFPL - 1)) == 0) { | |
90c84c56 | 7588 | qemu_fprintf(f, "FPR%02d", i); |
685f1ce2 | 7589 | } |
90c84c56 | 7590 | qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i)); |
685f1ce2 | 7591 | if ((i & (RFPL - 1)) == (RFPL - 1)) { |
90c84c56 | 7592 | qemu_fprintf(f, "\n"); |
685f1ce2 RH |
7593 | } |
7594 | } | |
90c84c56 | 7595 | qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); |
79aceca5 | 7596 | } |
685f1ce2 | 7597 | |
f2e63a42 | 7598 | #if !defined(CONFIG_USER_ONLY) |
90c84c56 MA |
7599 | qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx |
7600 | " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", | |
7601 | env->spr[SPR_SRR0], env->spr[SPR_SRR1], | |
7602 | env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); | |
90dc8812 | 7603 | |
90c84c56 MA |
7604 | qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx |
7605 | " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", | |
7606 | env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], | |
7607 | env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); | |
90dc8812 | 7608 | |
90c84c56 MA |
7609 | qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx |
7610 | " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", | |
7611 | env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], | |
7612 | env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); | |
90dc8812 | 7613 | |
f2b70fde BH |
7614 | #if defined(TARGET_PPC64) |
7615 | if (env->excp_model == POWERPC_EXCP_POWER7 || | |
a790e82b BH |
7616 | env->excp_model == POWERPC_EXCP_POWER8 || |
7617 | env->excp_model == POWERPC_EXCP_POWER9) { | |
90c84c56 MA |
7618 | qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", |
7619 | env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); | |
f2b70fde BH |
7620 | } |
7621 | #endif | |
90dc8812 | 7622 | if (env->excp_model == POWERPC_EXCP_BOOKE) { |
90c84c56 MA |
7623 | qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx |
7624 | " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", | |
7625 | env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], | |
7626 | env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); | |
7627 | ||
7628 | qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx | |
7629 | " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", | |
7630 | env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], | |
7631 | env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); | |
7632 | ||
7633 | qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx | |
7634 | " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", | |
7635 | env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], | |
7636 | env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); | |
7637 | ||
7638 | qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx | |
7639 | " EPR " TARGET_FMT_lx "\n", | |
7640 | env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], | |
7641 | env->spr[SPR_BOOKE_EPR]); | |
90dc8812 SW |
7642 | |
7643 | /* FSL-specific */ | |
90c84c56 MA |
7644 | qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx |
7645 | " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", | |
7646 | env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], | |
7647 | env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); | |
90dc8812 SW |
7648 | |
7649 | /* | |
7650 | * IVORs are left out as they are large and do not change often -- | |
7651 | * they can be read with "p $ivor0", "p $ivor1", etc. | |
7652 | */ | |
7653 | } | |
7654 | ||
697ab892 DG |
7655 | #if defined(TARGET_PPC64) |
7656 | if (env->flags & POWERPC_FLAG_CFAR) { | |
90c84c56 | 7657 | qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); |
697ab892 DG |
7658 | } |
7659 | #endif | |
7660 | ||
efe843d8 | 7661 | if (env->spr_cb[SPR_LPCR].name) { |
90c84c56 | 7662 | qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); |
efe843d8 | 7663 | } |
d801a61e | 7664 | |
0941d728 | 7665 | switch (env->mmu_model) { |
90dc8812 SW |
7666 | case POWERPC_MMU_32B: |
7667 | case POWERPC_MMU_601: | |
7668 | case POWERPC_MMU_SOFT_6xx: | |
7669 | case POWERPC_MMU_SOFT_74xx: | |
7670 | #if defined(TARGET_PPC64) | |
0941d728 DG |
7671 | case POWERPC_MMU_64B: |
7672 | case POWERPC_MMU_2_03: | |
7673 | case POWERPC_MMU_2_06: | |
7674 | case POWERPC_MMU_2_07: | |
7675 | case POWERPC_MMU_3_00: | |
90dc8812 | 7676 | #endif |
4f4f28ff | 7677 | if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ |
90c84c56 | 7678 | qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); |
4f4f28ff | 7679 | } |
4a7518e0 | 7680 | if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ |
90c84c56 | 7681 | qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); |
4a7518e0 | 7682 | } |
90c84c56 MA |
7683 | qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", |
7684 | env->spr[SPR_DAR], env->spr[SPR_DSISR]); | |
90dc8812 | 7685 | break; |
01662f3e | 7686 | case POWERPC_MMU_BOOKE206: |
90c84c56 MA |
7687 | qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx |
7688 | " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", | |
7689 | env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], | |
7690 | env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); | |
7691 | ||
7692 | qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx | |
7693 | " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", | |
7694 | env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], | |
7695 | env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); | |
7696 | ||
7697 | qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx | |
7698 | " TLB1CFG " TARGET_FMT_lx "\n", | |
7699 | env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], | |
7700 | env->spr[SPR_BOOKE_TLB1CFG]); | |
90dc8812 SW |
7701 | break; |
7702 | default: | |
7703 | break; | |
7704 | } | |
f2e63a42 | 7705 | #endif |
79aceca5 | 7706 | |
3fc6c082 FB |
7707 | #undef RGPL |
7708 | #undef RFPL | |
79aceca5 FB |
7709 | } |
7710 | ||
11cb6c15 | 7711 | void ppc_cpu_dump_statistics(CPUState *cs, int flags) |
76a66253 JM |
7712 | { |
7713 | #if defined(DO_PPC_STATISTICS) | |
878096ee | 7714 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
c227f099 | 7715 | opc_handler_t **t1, **t2, **t3, *handler; |
76a66253 JM |
7716 | int op1, op2, op3; |
7717 | ||
878096ee | 7718 | t1 = cpu->env.opcodes; |
76a66253 JM |
7719 | for (op1 = 0; op1 < 64; op1++) { |
7720 | handler = t1[op1]; | |
7721 | if (is_indirect_opcode(handler)) { | |
7722 | t2 = ind_table(handler); | |
7723 | for (op2 = 0; op2 < 32; op2++) { | |
7724 | handler = t2[op2]; | |
7725 | if (is_indirect_opcode(handler)) { | |
7726 | t3 = ind_table(handler); | |
7727 | for (op3 = 0; op3 < 32; op3++) { | |
7728 | handler = t3[op3]; | |
efe843d8 | 7729 | if (handler->count == 0) { |
76a66253 | 7730 | continue; |
efe843d8 | 7731 | } |
11cb6c15 | 7732 | qemu_printf("%02x %02x %02x (%02x %04d) %16s: " |
0bfcd599 | 7733 | "%016" PRIx64 " %" PRId64 "\n", |
76a66253 JM |
7734 | op1, op2, op3, op1, (op3 << 5) | op2, |
7735 | handler->oname, | |
7736 | handler->count, handler->count); | |
7737 | } | |
7738 | } else { | |
efe843d8 | 7739 | if (handler->count == 0) { |
76a66253 | 7740 | continue; |
efe843d8 | 7741 | } |
11cb6c15 | 7742 | qemu_printf("%02x %02x (%02x %04d) %16s: " |
0bfcd599 | 7743 | "%016" PRIx64 " %" PRId64 "\n", |
76a66253 JM |
7744 | op1, op2, op1, op2, handler->oname, |
7745 | handler->count, handler->count); | |
7746 | } | |
7747 | } | |
7748 | } else { | |
efe843d8 | 7749 | if (handler->count == 0) { |
76a66253 | 7750 | continue; |
efe843d8 | 7751 | } |
11cb6c15 | 7752 | qemu_printf("%02x (%02x ) %16s: %016" PRIx64 |
0bfcd599 | 7753 | " %" PRId64 "\n", |
76a66253 JM |
7754 | op1, op1, handler->oname, |
7755 | handler->count, handler->count); | |
7756 | } | |
7757 | } | |
7758 | #endif | |
7759 | } | |
7760 | ||
b542683d | 7761 | static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) |
79aceca5 | 7762 | { |
b0c2d521 | 7763 | DisasContext *ctx = container_of(dcbase, DisasContext, base); |
9c489ea6 | 7764 | CPUPPCState *env = cs->env_ptr; |
b0c2d521 EC |
7765 | int bound; |
7766 | ||
7767 | ctx->exception = POWERPC_EXCP_NONE; | |
7768 | ctx->spr_cb = env->spr_cb; | |
7769 | ctx->pr = msr_pr; | |
7770 | ctx->mem_idx = env->dmmu_idx; | |
7771 | ctx->dr = msr_dr; | |
932ccbdd | 7772 | #if !defined(CONFIG_USER_ONLY) |
b0c2d521 | 7773 | ctx->hv = msr_hv || !env->has_hv_mode; |
932ccbdd | 7774 | #endif |
b0c2d521 EC |
7775 | ctx->insns_flags = env->insns_flags; |
7776 | ctx->insns_flags2 = env->insns_flags2; | |
7777 | ctx->access_type = -1; | |
7778 | ctx->need_access_type = !(env->mmu_model & POWERPC_MMU_64B); | |
7779 | ctx->le_mode = !!(env->hflags & (1 << MSR_LE)); | |
7780 | ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; | |
0e3bf489 | 7781 | ctx->flags = env->flags; |
d9bce9d9 | 7782 | #if defined(TARGET_PPC64) |
b0c2d521 EC |
7783 | ctx->sf_mode = msr_is_64bit(env, env->msr); |
7784 | ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); | |
9a64fbe4 | 7785 | #endif |
e69ba2b4 DG |
7786 | ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B |
7787 | || env->mmu_model == POWERPC_MMU_601 | |
7788 | || (env->mmu_model & POWERPC_MMU_64B); | |
c5a8d8f3 | 7789 | |
b0c2d521 | 7790 | ctx->fpu_enabled = !!msr_fp; |
efe843d8 | 7791 | if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) { |
b0c2d521 | 7792 | ctx->spe_enabled = !!msr_spe; |
efe843d8 | 7793 | } else { |
b0c2d521 | 7794 | ctx->spe_enabled = false; |
efe843d8 DG |
7795 | } |
7796 | if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) { | |
b0c2d521 | 7797 | ctx->altivec_enabled = !!msr_vr; |
efe843d8 | 7798 | } else { |
b0c2d521 | 7799 | ctx->altivec_enabled = false; |
efe843d8 | 7800 | } |
1f29871c | 7801 | if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) { |
b0c2d521 | 7802 | ctx->vsx_enabled = !!msr_vsx; |
1f29871c | 7803 | } else { |
b0c2d521 | 7804 | ctx->vsx_enabled = false; |
1f29871c | 7805 | } |
69d1a937 TM |
7806 | #if defined(TARGET_PPC64) |
7807 | if ((env->flags & POWERPC_FLAG_TM) && msr_tm) { | |
b0c2d521 | 7808 | ctx->tm_enabled = !!msr_tm; |
69d1a937 | 7809 | } else { |
b0c2d521 | 7810 | ctx->tm_enabled = false; |
69d1a937 TM |
7811 | } |
7812 | #endif | |
b0c2d521 | 7813 | ctx->gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE); |
efe843d8 | 7814 | if ((env->flags & POWERPC_FLAG_SE) && msr_se) { |
b0c2d521 | 7815 | ctx->singlestep_enabled = CPU_SINGLE_STEP; |
efe843d8 | 7816 | } else { |
b0c2d521 | 7817 | ctx->singlestep_enabled = 0; |
efe843d8 DG |
7818 | } |
7819 | if ((env->flags & POWERPC_FLAG_BE) && msr_be) { | |
b0c2d521 | 7820 | ctx->singlestep_enabled |= CPU_BRANCH_STEP; |
efe843d8 | 7821 | } |
0e3bf489 RK |
7822 | if ((env->flags & POWERPC_FLAG_DE) && msr_de) { |
7823 | ctx->singlestep_enabled = 0; | |
7824 | target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0]; | |
7825 | if (dbcr0 & DBCR0_ICMP) { | |
7826 | ctx->singlestep_enabled |= CPU_SINGLE_STEP; | |
7827 | } | |
7828 | if (dbcr0 & DBCR0_BRT) { | |
7829 | ctx->singlestep_enabled |= CPU_BRANCH_STEP; | |
7830 | } | |
7831 | ||
7832 | } | |
b0c2d521 EC |
7833 | if (unlikely(ctx->base.singlestep_enabled)) { |
7834 | ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP; | |
ed2803da | 7835 | } |
efe843d8 | 7836 | #if defined(DO_SINGLE_STEP) && 0 |
9a64fbe4 FB |
7837 | /* Single step trace mode */ |
7838 | msr_se = 1; | |
7839 | #endif | |
b933066a | 7840 | |
b0c2d521 | 7841 | bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; |
b542683d | 7842 | ctx->base.max_insns = MIN(ctx->base.max_insns, bound); |
b0c2d521 EC |
7843 | } |
7844 | ||
7845 | static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) | |
7846 | { | |
7847 | } | |
7848 | ||
7849 | static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) | |
7850 | { | |
7851 | tcg_gen_insn_start(dcbase->pc_next); | |
7852 | } | |
7853 | ||
7854 | static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, | |
7855 | const CPUBreakpoint *bp) | |
7856 | { | |
7857 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
7858 | ||
7859 | gen_debug_exception(ctx); | |
2a8ceefc | 7860 | dcbase->is_jmp = DISAS_NORETURN; |
efe843d8 DG |
7861 | /* |
7862 | * The address covered by the breakpoint must be included in | |
7863 | * [tb->pc, tb->pc + tb->size) in order to for it to be properly | |
7864 | * cleared -- thus we increment the PC here so that the logic | |
7865 | * setting tb->size below does the right thing. | |
7866 | */ | |
b0c2d521 EC |
7867 | ctx->base.pc_next += 4; |
7868 | return true; | |
7869 | } | |
7870 | ||
7871 | static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) | |
7872 | { | |
7873 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
28876bf2 | 7874 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
b0c2d521 EC |
7875 | CPUPPCState *env = cs->env_ptr; |
7876 | opc_handler_t **table, *handler; | |
7877 | ||
7878 | LOG_DISAS("----------------\n"); | |
7879 | LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", | |
7880 | ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); | |
7881 | ||
23f42b60 EC |
7882 | ctx->opcode = translator_ldl_swap(env, ctx->base.pc_next, |
7883 | need_byteswap(ctx)); | |
7884 | ||
b0c2d521 EC |
7885 | LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", |
7886 | ctx->opcode, opc1(ctx->opcode), opc2(ctx->opcode), | |
7887 | opc3(ctx->opcode), opc4(ctx->opcode), | |
7888 | ctx->le_mode ? "little" : "big"); | |
7889 | ctx->base.pc_next += 4; | |
28876bf2 | 7890 | table = cpu->opcodes; |
b0c2d521 EC |
7891 | handler = table[opc1(ctx->opcode)]; |
7892 | if (is_indirect_opcode(handler)) { | |
7893 | table = ind_table(handler); | |
7894 | handler = table[opc2(ctx->opcode)]; | |
79aceca5 FB |
7895 | if (is_indirect_opcode(handler)) { |
7896 | table = ind_table(handler); | |
b0c2d521 | 7897 | handler = table[opc3(ctx->opcode)]; |
79aceca5 FB |
7898 | if (is_indirect_opcode(handler)) { |
7899 | table = ind_table(handler); | |
b0c2d521 | 7900 | handler = table[opc4(ctx->opcode)]; |
79aceca5 FB |
7901 | } |
7902 | } | |
b0c2d521 EC |
7903 | } |
7904 | /* Is opcode *REALLY* valid ? */ | |
7905 | if (unlikely(handler->handler == &gen_invalid)) { | |
7906 | qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " | |
7907 | "%02x - %02x - %02x - %02x (%08x) " | |
7908 | TARGET_FMT_lx " %d\n", | |
7909 | opc1(ctx->opcode), opc2(ctx->opcode), | |
7910 | opc3(ctx->opcode), opc4(ctx->opcode), | |
7911 | ctx->opcode, ctx->base.pc_next - 4, (int)msr_ir); | |
7912 | } else { | |
7913 | uint32_t inval; | |
70560da7 | 7914 | |
b0c2d521 EC |
7915 | if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) |
7916 | && Rc(ctx->opcode))) { | |
7917 | inval = handler->inval2; | |
7918 | } else { | |
7919 | inval = handler->inval1; | |
7920 | } | |
70560da7 | 7921 | |
b0c2d521 EC |
7922 | if (unlikely((ctx->opcode & inval) != 0)) { |
7923 | qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " | |
7924 | "%02x - %02x - %02x - %02x (%08x) " | |
7925 | TARGET_FMT_lx "\n", ctx->opcode & inval, | |
7926 | opc1(ctx->opcode), opc2(ctx->opcode), | |
7927 | opc3(ctx->opcode), opc4(ctx->opcode), | |
7928 | ctx->opcode, ctx->base.pc_next - 4); | |
7929 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
7930 | ctx->base.is_jmp = DISAS_NORETURN; | |
7931 | return; | |
79aceca5 | 7932 | } |
b0c2d521 EC |
7933 | } |
7934 | (*(handler->handler))(ctx); | |
76a66253 | 7935 | #if defined(DO_PPC_STATISTICS) |
b0c2d521 | 7936 | handler->count++; |
76a66253 | 7937 | #endif |
b0c2d521 EC |
7938 | /* Check trace mode exceptions */ |
7939 | if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP && | |
7940 | (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) && | |
7941 | ctx->exception != POWERPC_SYSCALL && | |
7942 | ctx->exception != POWERPC_EXCP_TRAP && | |
7943 | ctx->exception != POWERPC_EXCP_BRANCH)) { | |
e150ac89 RK |
7944 | uint32_t excp = gen_prep_dbgex(ctx); |
7945 | gen_exception_nip(ctx, excp, ctx->base.pc_next); | |
b0c2d521 EC |
7946 | } |
7947 | ||
7948 | if (tcg_check_temp_count()) { | |
7949 | qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked " | |
7950 | "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode), | |
7951 | opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode); | |
3fc6c082 | 7952 | } |
b0c2d521 EC |
7953 | |
7954 | ctx->base.is_jmp = ctx->exception == POWERPC_EXCP_NONE ? | |
7955 | DISAS_NEXT : DISAS_NORETURN; | |
7956 | } | |
7957 | ||
7958 | static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) | |
7959 | { | |
7960 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
7961 | ||
7962 | if (ctx->exception == POWERPC_EXCP_NONE) { | |
7963 | gen_goto_tb(ctx, 0, ctx->base.pc_next); | |
7964 | } else if (ctx->exception != POWERPC_EXCP_BRANCH) { | |
7965 | if (unlikely(ctx->base.singlestep_enabled)) { | |
7966 | gen_debug_exception(ctx); | |
8cbcb4fa | 7967 | } |
76a66253 | 7968 | /* Generate the return instruction */ |
07ea28b4 | 7969 | tcg_gen_exit_tb(NULL, 0); |
9a64fbe4 | 7970 | } |
b0c2d521 EC |
7971 | } |
7972 | ||
7973 | static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) | |
7974 | { | |
7975 | qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); | |
7976 | log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); | |
7977 | } | |
0a7df5da | 7978 | |
b0c2d521 EC |
7979 | static const TranslatorOps ppc_tr_ops = { |
7980 | .init_disas_context = ppc_tr_init_disas_context, | |
7981 | .tb_start = ppc_tr_tb_start, | |
7982 | .insn_start = ppc_tr_insn_start, | |
7983 | .breakpoint_check = ppc_tr_breakpoint_check, | |
7984 | .translate_insn = ppc_tr_translate_insn, | |
7985 | .tb_stop = ppc_tr_tb_stop, | |
7986 | .disas_log = ppc_tr_disas_log, | |
7987 | }; | |
4e5e1215 | 7988 | |
8b86d6d2 | 7989 | void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) |
b0c2d521 EC |
7990 | { |
7991 | DisasContext ctx; | |
7992 | ||
8b86d6d2 | 7993 | translator_loop(&ppc_tr_ops, &ctx.base, cs, tb, max_insns); |
79aceca5 FB |
7994 | } |
7995 | ||
bad729e2 RH |
7996 | void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, |
7997 | target_ulong *data) | |
d2856f1a | 7998 | { |
bad729e2 | 7999 | env->nip = data[0]; |
d2856f1a | 8000 | } |