]>
Commit | Line | Data |
---|---|---|
79aceca5 | 1 | /* |
3fc6c082 | 2 | * PowerPC emulation for qemu: main translation routines. |
5fafdf24 | 3 | * |
76a66253 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
90dc8812 | 5 | * Copyright (C) 2011 Freescale Semiconductor, Inc. |
79aceca5 FB |
6 | * |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
6bd039cd | 10 | * version 2.1 of the License, or (at your option) any later version. |
79aceca5 FB |
11 | * |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
79aceca5 | 19 | */ |
c6a1c22b | 20 | |
0d75590d | 21 | #include "qemu/osdep.h" |
79aceca5 | 22 | #include "cpu.h" |
3e00884f | 23 | #include "internal.h" |
76cad711 | 24 | #include "disas/disas.h" |
63c91552 | 25 | #include "exec/exec-all.h" |
dcb32f1d PMD |
26 | #include "tcg/tcg-op.h" |
27 | #include "tcg/tcg-op-gvec.h" | |
1de7afc9 | 28 | #include "qemu/host-utils.h" |
db725815 | 29 | #include "qemu/main-loop.h" |
f08b6170 | 30 | #include "exec/cpu_ldst.h" |
79aceca5 | 31 | |
2ef6175a RH |
32 | #include "exec/helper-proto.h" |
33 | #include "exec/helper-gen.h" | |
a7812ae4 | 34 | |
a7e30d84 | 35 | #include "trace-tcg.h" |
b6bac4bc | 36 | #include "exec/translator.h" |
508127e2 | 37 | #include "exec/log.h" |
f34ec0f6 | 38 | #include "qemu/atomic128.h" |
a7e30d84 LV |
39 | |
40 | ||
8cbcb4fa AJ |
41 | #define CPU_SINGLE_STEP 0x1 |
42 | #define CPU_BRANCH_STEP 0x2 | |
43 | #define GDBSTUB_SINGLE_STEP 0x4 | |
44 | ||
a750fc0b | 45 | /* Include definitions for instructions classes and implementations flags */ |
efe843d8 DG |
46 | /* #define PPC_DEBUG_DISAS */ |
47 | /* #define DO_PPC_STATISTICS */ | |
79aceca5 | 48 | |
d12d51d5 | 49 | #ifdef PPC_DEBUG_DISAS |
93fcfe39 | 50 | # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) |
d12d51d5 AL |
51 | #else |
52 | # define LOG_DISAS(...) do { } while (0) | |
53 | #endif | |
a750fc0b JM |
54 | /*****************************************************************************/ |
55 | /* Code translation helpers */ | |
c53be334 | 56 | |
f78fb44e | 57 | /* global register indexes */ |
efe843d8 DG |
58 | static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ |
59 | + 10 * 4 + 22 * 5 /* SPE GPRh */ | |
60 | + 8 * 5 /* CRF */]; | |
f78fb44e | 61 | static TCGv cpu_gpr[32]; |
f78fb44e | 62 | static TCGv cpu_gprh[32]; |
a7812ae4 | 63 | static TCGv_i32 cpu_crf[8]; |
bd568f18 | 64 | static TCGv cpu_nip; |
6527f6ea | 65 | static TCGv cpu_msr; |
cfdcd37a AJ |
66 | static TCGv cpu_ctr; |
67 | static TCGv cpu_lr; | |
697ab892 DG |
68 | #if defined(TARGET_PPC64) |
69 | static TCGv cpu_cfar; | |
70 | #endif | |
dd09c361 | 71 | static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; |
cf360a32 | 72 | static TCGv cpu_reserve; |
253ce7b2 | 73 | static TCGv cpu_reserve_val; |
30304420 | 74 | static TCGv cpu_fpscr; |
a7859e89 | 75 | static TCGv_i32 cpu_access_type; |
f78fb44e | 76 | |
022c62cb | 77 | #include "exec/gen-icount.h" |
2e70f6ef PB |
78 | |
79 | void ppc_translate_init(void) | |
80 | { | |
f78fb44e | 81 | int i; |
efe843d8 | 82 | char *p; |
2dc766da | 83 | size_t cpu_reg_names_size; |
f78fb44e | 84 | |
f78fb44e | 85 | p = cpu_reg_names; |
2dc766da | 86 | cpu_reg_names_size = sizeof(cpu_reg_names); |
47e4661c AJ |
87 | |
88 | for (i = 0; i < 8; i++) { | |
2dc766da | 89 | snprintf(p, cpu_reg_names_size, "crf%d", i); |
e1ccc054 | 90 | cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, |
1328c2bf | 91 | offsetof(CPUPPCState, crf[i]), p); |
47e4661c | 92 | p += 5; |
2dc766da | 93 | cpu_reg_names_size -= 5; |
47e4661c AJ |
94 | } |
95 | ||
f78fb44e | 96 | for (i = 0; i < 32; i++) { |
2dc766da | 97 | snprintf(p, cpu_reg_names_size, "r%d", i); |
e1ccc054 | 98 | cpu_gpr[i] = tcg_global_mem_new(cpu_env, |
1328c2bf | 99 | offsetof(CPUPPCState, gpr[i]), p); |
f78fb44e | 100 | p += (i < 10) ? 3 : 4; |
2dc766da | 101 | cpu_reg_names_size -= (i < 10) ? 3 : 4; |
2dc766da | 102 | snprintf(p, cpu_reg_names_size, "r%dH", i); |
e1ccc054 | 103 | cpu_gprh[i] = tcg_global_mem_new(cpu_env, |
13b6a455 | 104 | offsetof(CPUPPCState, gprh[i]), p); |
f78fb44e | 105 | p += (i < 10) ? 4 : 5; |
2dc766da | 106 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
f78fb44e | 107 | } |
f10dc08e | 108 | |
e1ccc054 | 109 | cpu_nip = tcg_global_mem_new(cpu_env, |
1328c2bf | 110 | offsetof(CPUPPCState, nip), "nip"); |
bd568f18 | 111 | |
e1ccc054 | 112 | cpu_msr = tcg_global_mem_new(cpu_env, |
1328c2bf | 113 | offsetof(CPUPPCState, msr), "msr"); |
6527f6ea | 114 | |
e1ccc054 | 115 | cpu_ctr = tcg_global_mem_new(cpu_env, |
1328c2bf | 116 | offsetof(CPUPPCState, ctr), "ctr"); |
cfdcd37a | 117 | |
e1ccc054 | 118 | cpu_lr = tcg_global_mem_new(cpu_env, |
1328c2bf | 119 | offsetof(CPUPPCState, lr), "lr"); |
cfdcd37a | 120 | |
697ab892 | 121 | #if defined(TARGET_PPC64) |
e1ccc054 | 122 | cpu_cfar = tcg_global_mem_new(cpu_env, |
1328c2bf | 123 | offsetof(CPUPPCState, cfar), "cfar"); |
697ab892 DG |
124 | #endif |
125 | ||
e1ccc054 | 126 | cpu_xer = tcg_global_mem_new(cpu_env, |
1328c2bf | 127 | offsetof(CPUPPCState, xer), "xer"); |
e1ccc054 | 128 | cpu_so = tcg_global_mem_new(cpu_env, |
da91a00f | 129 | offsetof(CPUPPCState, so), "SO"); |
e1ccc054 | 130 | cpu_ov = tcg_global_mem_new(cpu_env, |
da91a00f | 131 | offsetof(CPUPPCState, ov), "OV"); |
e1ccc054 | 132 | cpu_ca = tcg_global_mem_new(cpu_env, |
da91a00f | 133 | offsetof(CPUPPCState, ca), "CA"); |
dd09c361 ND |
134 | cpu_ov32 = tcg_global_mem_new(cpu_env, |
135 | offsetof(CPUPPCState, ov32), "OV32"); | |
136 | cpu_ca32 = tcg_global_mem_new(cpu_env, | |
137 | offsetof(CPUPPCState, ca32), "CA32"); | |
3d7b417e | 138 | |
e1ccc054 | 139 | cpu_reserve = tcg_global_mem_new(cpu_env, |
1328c2bf | 140 | offsetof(CPUPPCState, reserve_addr), |
18b21a2f | 141 | "reserve_addr"); |
253ce7b2 ND |
142 | cpu_reserve_val = tcg_global_mem_new(cpu_env, |
143 | offsetof(CPUPPCState, reserve_val), | |
144 | "reserve_val"); | |
cf360a32 | 145 | |
e1ccc054 | 146 | cpu_fpscr = tcg_global_mem_new(cpu_env, |
30304420 | 147 | offsetof(CPUPPCState, fpscr), "fpscr"); |
e1571908 | 148 | |
e1ccc054 | 149 | cpu_access_type = tcg_global_mem_new_i32(cpu_env, |
efe843d8 DG |
150 | offsetof(CPUPPCState, access_type), |
151 | "access_type"); | |
2e70f6ef PB |
152 | } |
153 | ||
79aceca5 | 154 | /* internal defines */ |
69b058c8 | 155 | struct DisasContext { |
b6bac4bc | 156 | DisasContextBase base; |
79aceca5 | 157 | uint32_t opcode; |
9a64fbe4 | 158 | uint32_t exception; |
3cc62370 | 159 | /* Routine used to access memory */ |
5c3ae929 | 160 | bool pr, hv, dr, le_mode; |
c5a8d8f3 | 161 | bool lazy_tlb_flush; |
5f2a6254 | 162 | bool need_access_type; |
3cc62370 | 163 | int mem_idx; |
76db3ba4 | 164 | int access_type; |
3cc62370 | 165 | /* Translation flags */ |
14776ab5 | 166 | MemOp default_tcg_memop_mask; |
d9bce9d9 | 167 | #if defined(TARGET_PPC64) |
5c3ae929 BH |
168 | bool sf_mode; |
169 | bool has_cfar; | |
9a64fbe4 | 170 | #endif |
5c3ae929 BH |
171 | bool fpu_enabled; |
172 | bool altivec_enabled; | |
173 | bool vsx_enabled; | |
174 | bool spe_enabled; | |
175 | bool tm_enabled; | |
c6fd28fd | 176 | bool gtse; |
c227f099 | 177 | ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ |
ea4e754f | 178 | int singlestep_enabled; |
0e3bf489 | 179 | uint32_t flags; |
7d08d856 AJ |
180 | uint64_t insns_flags; |
181 | uint64_t insns_flags2; | |
69b058c8 | 182 | }; |
79aceca5 | 183 | |
e22c357b DK |
184 | /* Return true iff byteswap is needed in a scalar memop */ |
185 | static inline bool need_byteswap(const DisasContext *ctx) | |
186 | { | |
187 | #if defined(TARGET_WORDS_BIGENDIAN) | |
188 | return ctx->le_mode; | |
189 | #else | |
190 | return !ctx->le_mode; | |
191 | #endif | |
192 | } | |
193 | ||
79482e5a RH |
194 | /* True when active word size < size of target_long. */ |
195 | #ifdef TARGET_PPC64 | |
196 | # define NARROW_MODE(C) (!(C)->sf_mode) | |
197 | #else | |
198 | # define NARROW_MODE(C) 0 | |
199 | #endif | |
200 | ||
c227f099 | 201 | struct opc_handler_t { |
70560da7 FC |
202 | /* invalid bits for instruction 1 (Rc(opcode) == 0) */ |
203 | uint32_t inval1; | |
204 | /* invalid bits for instruction 2 (Rc(opcode) == 1) */ | |
205 | uint32_t inval2; | |
9a64fbe4 | 206 | /* instruction type */ |
0487d6a8 | 207 | uint64_t type; |
a5858d7a AG |
208 | /* extended instruction type */ |
209 | uint64_t type2; | |
79aceca5 FB |
210 | /* handler */ |
211 | void (*handler)(DisasContext *ctx); | |
a750fc0b | 212 | #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) |
b55266b5 | 213 | const char *oname; |
a750fc0b JM |
214 | #endif |
215 | #if defined(DO_PPC_STATISTICS) | |
76a66253 JM |
216 | uint64_t count; |
217 | #endif | |
3fc6c082 | 218 | }; |
79aceca5 | 219 | |
0e3bf489 RK |
220 | /* SPR load/store helpers */ |
221 | static inline void gen_load_spr(TCGv t, int reg) | |
222 | { | |
223 | tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); | |
224 | } | |
225 | ||
226 | static inline void gen_store_spr(int reg, TCGv t) | |
227 | { | |
228 | tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); | |
229 | } | |
230 | ||
636aa200 | 231 | static inline void gen_set_access_type(DisasContext *ctx, int access_type) |
a7859e89 | 232 | { |
5f2a6254 | 233 | if (ctx->need_access_type && ctx->access_type != access_type) { |
76db3ba4 AJ |
234 | tcg_gen_movi_i32(cpu_access_type, access_type); |
235 | ctx->access_type = access_type; | |
236 | } | |
a7859e89 AJ |
237 | } |
238 | ||
636aa200 | 239 | static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) |
d9bce9d9 | 240 | { |
e0c8f9ce RH |
241 | if (NARROW_MODE(ctx)) { |
242 | nip = (uint32_t)nip; | |
243 | } | |
244 | tcg_gen_movi_tl(cpu_nip, nip); | |
d9bce9d9 JM |
245 | } |
246 | ||
b9971cc5 | 247 | static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) |
e06fcd75 AJ |
248 | { |
249 | TCGv_i32 t0, t1; | |
bd6fefe7 | 250 | |
efe843d8 DG |
251 | /* |
252 | * These are all synchronous exceptions, we set the PC back to the | |
253 | * faulting instruction | |
bd6fefe7 | 254 | */ |
e06fcd75 | 255 | if (ctx->exception == POWERPC_EXCP_NONE) { |
b6bac4bc | 256 | gen_update_nip(ctx, ctx->base.pc_next - 4); |
e06fcd75 AJ |
257 | } |
258 | t0 = tcg_const_i32(excp); | |
259 | t1 = tcg_const_i32(error); | |
e5f17ac6 | 260 | gen_helper_raise_exception_err(cpu_env, t0, t1); |
e06fcd75 AJ |
261 | tcg_temp_free_i32(t0); |
262 | tcg_temp_free_i32(t1); | |
263 | ctx->exception = (excp); | |
264 | } | |
e1833e1f | 265 | |
b9971cc5 | 266 | static void gen_exception(DisasContext *ctx, uint32_t excp) |
e06fcd75 AJ |
267 | { |
268 | TCGv_i32 t0; | |
bd6fefe7 | 269 | |
efe843d8 DG |
270 | /* |
271 | * These are all synchronous exceptions, we set the PC back to the | |
272 | * faulting instruction | |
bd6fefe7 | 273 | */ |
e06fcd75 | 274 | if (ctx->exception == POWERPC_EXCP_NONE) { |
b6bac4bc | 275 | gen_update_nip(ctx, ctx->base.pc_next - 4); |
e06fcd75 AJ |
276 | } |
277 | t0 = tcg_const_i32(excp); | |
e5f17ac6 | 278 | gen_helper_raise_exception(cpu_env, t0); |
e06fcd75 AJ |
279 | tcg_temp_free_i32(t0); |
280 | ctx->exception = (excp); | |
281 | } | |
e1833e1f | 282 | |
bd6fefe7 BH |
283 | static void gen_exception_nip(DisasContext *ctx, uint32_t excp, |
284 | target_ulong nip) | |
285 | { | |
286 | TCGv_i32 t0; | |
287 | ||
288 | gen_update_nip(ctx, nip); | |
289 | t0 = tcg_const_i32(excp); | |
290 | gen_helper_raise_exception(cpu_env, t0); | |
291 | tcg_temp_free_i32(t0); | |
292 | ctx->exception = (excp); | |
293 | } | |
294 | ||
e150ac89 RK |
295 | /* |
296 | * Tells the caller what is the appropriate exception to generate and prepares | |
297 | * SPR registers for this exception. | |
298 | * | |
299 | * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or | |
300 | * POWERPC_EXCP_DEBUG (on BookE). | |
0e3bf489 | 301 | */ |
e150ac89 | 302 | static uint32_t gen_prep_dbgex(DisasContext *ctx) |
0e3bf489 | 303 | { |
0e3bf489 RK |
304 | if (ctx->flags & POWERPC_FLAG_DE) { |
305 | target_ulong dbsr = 0; | |
e150ac89 | 306 | if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { |
0e3bf489 | 307 | dbsr = DBCR0_ICMP; |
e150ac89 RK |
308 | } else { |
309 | /* Must have been branch */ | |
0e3bf489 | 310 | dbsr = DBCR0_BRT; |
0e3bf489 RK |
311 | } |
312 | TCGv t0 = tcg_temp_new(); | |
313 | gen_load_spr(t0, SPR_BOOKE_DBSR); | |
314 | tcg_gen_ori_tl(t0, t0, dbsr); | |
315 | gen_store_spr(SPR_BOOKE_DBSR, t0); | |
316 | tcg_temp_free(t0); | |
317 | return POWERPC_EXCP_DEBUG; | |
318 | } else { | |
e150ac89 | 319 | return POWERPC_EXCP_TRACE; |
0e3bf489 RK |
320 | } |
321 | } | |
322 | ||
b9971cc5 | 323 | static void gen_debug_exception(DisasContext *ctx) |
e06fcd75 AJ |
324 | { |
325 | TCGv_i32 t0; | |
5518f3a6 | 326 | |
efe843d8 DG |
327 | /* |
328 | * These are all synchronous exceptions, we set the PC back to the | |
329 | * faulting instruction | |
bd6fefe7 | 330 | */ |
ee2b3994 SB |
331 | if ((ctx->exception != POWERPC_EXCP_BRANCH) && |
332 | (ctx->exception != POWERPC_EXCP_SYNC)) { | |
b6bac4bc | 333 | gen_update_nip(ctx, ctx->base.pc_next); |
ee2b3994 | 334 | } |
e06fcd75 | 335 | t0 = tcg_const_i32(EXCP_DEBUG); |
e5f17ac6 | 336 | gen_helper_raise_exception(cpu_env, t0); |
e06fcd75 AJ |
337 | tcg_temp_free_i32(t0); |
338 | } | |
9a64fbe4 | 339 | |
636aa200 | 340 | static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) |
e06fcd75 | 341 | { |
9b2fadda BH |
342 | /* Will be converted to program check if needed */ |
343 | gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); | |
344 | } | |
345 | ||
346 | static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) | |
347 | { | |
348 | gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); | |
349 | } | |
350 | ||
351 | static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) | |
352 | { | |
353 | /* Will be converted to program check if needed */ | |
354 | gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); | |
e06fcd75 | 355 | } |
a9d9eb8f | 356 | |
f24e5695 | 357 | /* Stop translation */ |
636aa200 | 358 | static inline void gen_stop_exception(DisasContext *ctx) |
3fc6c082 | 359 | { |
b6bac4bc | 360 | gen_update_nip(ctx, ctx->base.pc_next); |
e1833e1f | 361 | ctx->exception = POWERPC_EXCP_STOP; |
3fc6c082 FB |
362 | } |
363 | ||
466976d9 | 364 | #ifndef CONFIG_USER_ONLY |
f24e5695 | 365 | /* No need to update nip here, as execution flow will change */ |
636aa200 | 366 | static inline void gen_sync_exception(DisasContext *ctx) |
2be0071f | 367 | { |
e1833e1f | 368 | ctx->exception = POWERPC_EXCP_SYNC; |
2be0071f | 369 | } |
466976d9 | 370 | #endif |
2be0071f | 371 | |
79aceca5 | 372 | #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ |
a5858d7a AG |
373 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) |
374 | ||
375 | #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ | |
376 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) | |
79aceca5 | 377 | |
c7697e1f | 378 | #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ |
a5858d7a AG |
379 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) |
380 | ||
381 | #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ | |
382 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) | |
c7697e1f | 383 | |
323ad19b ND |
384 | #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ |
385 | GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) | |
386 | ||
14fd8ab2 ND |
387 | #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ |
388 | GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) | |
389 | ||
c227f099 | 390 | typedef struct opcode_t { |
323ad19b | 391 | unsigned char opc1, opc2, opc3, opc4; |
1235fc06 | 392 | #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ |
323ad19b | 393 | unsigned char pad[4]; |
18fba28c | 394 | #endif |
c227f099 | 395 | opc_handler_t handler; |
b55266b5 | 396 | const char *oname; |
c227f099 | 397 | } opcode_t; |
79aceca5 | 398 | |
9b2fadda BH |
399 | /* Helpers for priv. check */ |
400 | #define GEN_PRIV \ | |
401 | do { \ | |
402 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ | |
403 | } while (0) | |
404 | ||
405 | #if defined(CONFIG_USER_ONLY) | |
406 | #define CHK_HV GEN_PRIV | |
407 | #define CHK_SV GEN_PRIV | |
b7815375 | 408 | #define CHK_HVRM GEN_PRIV |
9b2fadda BH |
409 | #else |
410 | #define CHK_HV \ | |
411 | do { \ | |
412 | if (unlikely(ctx->pr || !ctx->hv)) { \ | |
413 | GEN_PRIV; \ | |
414 | } \ | |
415 | } while (0) | |
416 | #define CHK_SV \ | |
417 | do { \ | |
418 | if (unlikely(ctx->pr)) { \ | |
419 | GEN_PRIV; \ | |
420 | } \ | |
421 | } while (0) | |
b7815375 BH |
422 | #define CHK_HVRM \ |
423 | do { \ | |
424 | if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ | |
425 | GEN_PRIV; \ | |
426 | } \ | |
427 | } while (0) | |
9b2fadda BH |
428 | #endif |
429 | ||
430 | #define CHK_NONE | |
431 | ||
a750fc0b | 432 | /*****************************************************************************/ |
a750fc0b | 433 | /* PowerPC instructions table */ |
933dc6eb | 434 | |
76a66253 | 435 | #if defined(DO_PPC_STATISTICS) |
a5858d7a | 436 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 437 | { \ |
79aceca5 FB |
438 | .opc1 = op1, \ |
439 | .opc2 = op2, \ | |
440 | .opc3 = op3, \ | |
323ad19b | 441 | .opc4 = 0xff, \ |
79aceca5 | 442 | .handler = { \ |
70560da7 FC |
443 | .inval1 = invl, \ |
444 | .type = _typ, \ | |
445 | .type2 = _typ2, \ | |
446 | .handler = &gen_##name, \ | |
447 | .oname = stringify(name), \ | |
448 | }, \ | |
449 | .oname = stringify(name), \ | |
450 | } | |
451 | #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ | |
452 | { \ | |
453 | .opc1 = op1, \ | |
454 | .opc2 = op2, \ | |
455 | .opc3 = op3, \ | |
323ad19b | 456 | .opc4 = 0xff, \ |
70560da7 FC |
457 | .handler = { \ |
458 | .inval1 = invl1, \ | |
459 | .inval2 = invl2, \ | |
9a64fbe4 | 460 | .type = _typ, \ |
a5858d7a | 461 | .type2 = _typ2, \ |
79aceca5 | 462 | .handler = &gen_##name, \ |
76a66253 | 463 | .oname = stringify(name), \ |
79aceca5 | 464 | }, \ |
3fc6c082 | 465 | .oname = stringify(name), \ |
79aceca5 | 466 | } |
a5858d7a | 467 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 468 | { \ |
c7697e1f JM |
469 | .opc1 = op1, \ |
470 | .opc2 = op2, \ | |
471 | .opc3 = op3, \ | |
323ad19b | 472 | .opc4 = 0xff, \ |
c7697e1f | 473 | .handler = { \ |
70560da7 | 474 | .inval1 = invl, \ |
c7697e1f | 475 | .type = _typ, \ |
a5858d7a | 476 | .type2 = _typ2, \ |
c7697e1f JM |
477 | .handler = &gen_##name, \ |
478 | .oname = onam, \ | |
479 | }, \ | |
480 | .oname = onam, \ | |
481 | } | |
323ad19b ND |
482 | #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ |
483 | { \ | |
484 | .opc1 = op1, \ | |
485 | .opc2 = op2, \ | |
486 | .opc3 = op3, \ | |
487 | .opc4 = op4, \ | |
488 | .handler = { \ | |
489 | .inval1 = invl, \ | |
490 | .type = _typ, \ | |
491 | .type2 = _typ2, \ | |
492 | .handler = &gen_##name, \ | |
493 | .oname = stringify(name), \ | |
494 | }, \ | |
495 | .oname = stringify(name), \ | |
496 | } | |
14fd8ab2 ND |
497 | #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ |
498 | { \ | |
499 | .opc1 = op1, \ | |
500 | .opc2 = op2, \ | |
501 | .opc3 = op3, \ | |
502 | .opc4 = op4, \ | |
503 | .handler = { \ | |
504 | .inval1 = invl, \ | |
505 | .type = _typ, \ | |
506 | .type2 = _typ2, \ | |
507 | .handler = &gen_##name, \ | |
508 | .oname = onam, \ | |
509 | }, \ | |
510 | .oname = onam, \ | |
511 | } | |
76a66253 | 512 | #else |
a5858d7a | 513 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 514 | { \ |
c7697e1f JM |
515 | .opc1 = op1, \ |
516 | .opc2 = op2, \ | |
517 | .opc3 = op3, \ | |
323ad19b | 518 | .opc4 = 0xff, \ |
c7697e1f | 519 | .handler = { \ |
70560da7 FC |
520 | .inval1 = invl, \ |
521 | .type = _typ, \ | |
522 | .type2 = _typ2, \ | |
523 | .handler = &gen_##name, \ | |
524 | }, \ | |
525 | .oname = stringify(name), \ | |
526 | } | |
527 | #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ | |
528 | { \ | |
529 | .opc1 = op1, \ | |
530 | .opc2 = op2, \ | |
531 | .opc3 = op3, \ | |
323ad19b | 532 | .opc4 = 0xff, \ |
70560da7 FC |
533 | .handler = { \ |
534 | .inval1 = invl1, \ | |
535 | .inval2 = invl2, \ | |
c7697e1f | 536 | .type = _typ, \ |
a5858d7a | 537 | .type2 = _typ2, \ |
c7697e1f | 538 | .handler = &gen_##name, \ |
5c55ff99 BS |
539 | }, \ |
540 | .oname = stringify(name), \ | |
541 | } | |
a5858d7a | 542 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 BS |
543 | { \ |
544 | .opc1 = op1, \ | |
545 | .opc2 = op2, \ | |
546 | .opc3 = op3, \ | |
323ad19b | 547 | .opc4 = 0xff, \ |
5c55ff99 | 548 | .handler = { \ |
70560da7 | 549 | .inval1 = invl, \ |
5c55ff99 | 550 | .type = _typ, \ |
a5858d7a | 551 | .type2 = _typ2, \ |
5c55ff99 BS |
552 | .handler = &gen_##name, \ |
553 | }, \ | |
554 | .oname = onam, \ | |
555 | } | |
323ad19b ND |
556 | #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ |
557 | { \ | |
558 | .opc1 = op1, \ | |
559 | .opc2 = op2, \ | |
560 | .opc3 = op3, \ | |
561 | .opc4 = op4, \ | |
562 | .handler = { \ | |
563 | .inval1 = invl, \ | |
564 | .type = _typ, \ | |
565 | .type2 = _typ2, \ | |
566 | .handler = &gen_##name, \ | |
567 | }, \ | |
568 | .oname = stringify(name), \ | |
569 | } | |
14fd8ab2 ND |
570 | #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ |
571 | { \ | |
572 | .opc1 = op1, \ | |
573 | .opc2 = op2, \ | |
574 | .opc3 = op3, \ | |
575 | .opc4 = op4, \ | |
576 | .handler = { \ | |
577 | .inval1 = invl, \ | |
578 | .type = _typ, \ | |
579 | .type2 = _typ2, \ | |
580 | .handler = &gen_##name, \ | |
581 | }, \ | |
582 | .oname = onam, \ | |
583 | } | |
5c55ff99 | 584 | #endif |
2e610050 | 585 | |
54623277 | 586 | /* Invalid instruction */ |
99e300ef | 587 | static void gen_invalid(DisasContext *ctx) |
9a64fbe4 | 588 | { |
e06fcd75 | 589 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
9a64fbe4 FB |
590 | } |
591 | ||
c227f099 | 592 | static opc_handler_t invalid_handler = { |
70560da7 FC |
593 | .inval1 = 0xFFFFFFFF, |
594 | .inval2 = 0xFFFFFFFF, | |
9a64fbe4 | 595 | .type = PPC_NONE, |
a5858d7a | 596 | .type2 = PPC_NONE, |
79aceca5 FB |
597 | .handler = gen_invalid, |
598 | }; | |
599 | ||
e1571908 AJ |
600 | /*** Integer comparison ***/ |
601 | ||
636aa200 | 602 | static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) |
e1571908 | 603 | { |
2fdcb629 | 604 | TCGv t0 = tcg_temp_new(); |
b62b3686 PB |
605 | TCGv t1 = tcg_temp_new(); |
606 | TCGv_i32 t = tcg_temp_new_i32(); | |
e1571908 | 607 | |
b62b3686 PB |
608 | tcg_gen_movi_tl(t0, CRF_EQ); |
609 | tcg_gen_movi_tl(t1, CRF_LT); | |
efe843d8 DG |
610 | tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), |
611 | t0, arg0, arg1, t1, t0); | |
b62b3686 | 612 | tcg_gen_movi_tl(t1, CRF_GT); |
efe843d8 DG |
613 | tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), |
614 | t0, arg0, arg1, t1, t0); | |
2fdcb629 | 615 | |
b62b3686 PB |
616 | tcg_gen_trunc_tl_i32(t, t0); |
617 | tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); | |
618 | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); | |
2fdcb629 RH |
619 | |
620 | tcg_temp_free(t0); | |
b62b3686 PB |
621 | tcg_temp_free(t1); |
622 | tcg_temp_free_i32(t); | |
e1571908 AJ |
623 | } |
624 | ||
636aa200 | 625 | static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) |
e1571908 | 626 | { |
2fdcb629 | 627 | TCGv t0 = tcg_const_tl(arg1); |
ea363694 AJ |
628 | gen_op_cmp(arg0, t0, s, crf); |
629 | tcg_temp_free(t0); | |
e1571908 AJ |
630 | } |
631 | ||
636aa200 | 632 | static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) |
e1571908 | 633 | { |
ea363694 | 634 | TCGv t0, t1; |
2fdcb629 RH |
635 | t0 = tcg_temp_new(); |
636 | t1 = tcg_temp_new(); | |
e1571908 | 637 | if (s) { |
ea363694 AJ |
638 | tcg_gen_ext32s_tl(t0, arg0); |
639 | tcg_gen_ext32s_tl(t1, arg1); | |
e1571908 | 640 | } else { |
ea363694 AJ |
641 | tcg_gen_ext32u_tl(t0, arg0); |
642 | tcg_gen_ext32u_tl(t1, arg1); | |
e1571908 | 643 | } |
ea363694 AJ |
644 | gen_op_cmp(t0, t1, s, crf); |
645 | tcg_temp_free(t1); | |
646 | tcg_temp_free(t0); | |
e1571908 AJ |
647 | } |
648 | ||
636aa200 | 649 | static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) |
e1571908 | 650 | { |
2fdcb629 | 651 | TCGv t0 = tcg_const_tl(arg1); |
ea363694 AJ |
652 | gen_op_cmp32(arg0, t0, s, crf); |
653 | tcg_temp_free(t0); | |
e1571908 | 654 | } |
e1571908 | 655 | |
636aa200 | 656 | static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) |
e1571908 | 657 | { |
02765534 | 658 | if (NARROW_MODE(ctx)) { |
e1571908 | 659 | gen_op_cmpi32(reg, 0, 1, 0); |
02765534 | 660 | } else { |
e1571908 | 661 | gen_op_cmpi(reg, 0, 1, 0); |
02765534 | 662 | } |
e1571908 AJ |
663 | } |
664 | ||
665 | /* cmp */ | |
99e300ef | 666 | static void gen_cmp(DisasContext *ctx) |
e1571908 | 667 | { |
36f48d9c | 668 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
669 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
670 | 1, crfD(ctx->opcode)); | |
36f48d9c AG |
671 | } else { |
672 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
673 | 1, crfD(ctx->opcode)); | |
02765534 | 674 | } |
e1571908 AJ |
675 | } |
676 | ||
677 | /* cmpi */ | |
99e300ef | 678 | static void gen_cmpi(DisasContext *ctx) |
e1571908 | 679 | { |
36f48d9c | 680 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
681 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), |
682 | 1, crfD(ctx->opcode)); | |
36f48d9c AG |
683 | } else { |
684 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), | |
685 | 1, crfD(ctx->opcode)); | |
02765534 | 686 | } |
e1571908 AJ |
687 | } |
688 | ||
689 | /* cmpl */ | |
99e300ef | 690 | static void gen_cmpl(DisasContext *ctx) |
e1571908 | 691 | { |
36f48d9c | 692 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
693 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
694 | 0, crfD(ctx->opcode)); | |
36f48d9c AG |
695 | } else { |
696 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
697 | 0, crfD(ctx->opcode)); | |
02765534 | 698 | } |
e1571908 AJ |
699 | } |
700 | ||
701 | /* cmpli */ | |
99e300ef | 702 | static void gen_cmpli(DisasContext *ctx) |
e1571908 | 703 | { |
36f48d9c | 704 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
705 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), |
706 | 0, crfD(ctx->opcode)); | |
36f48d9c AG |
707 | } else { |
708 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), | |
709 | 0, crfD(ctx->opcode)); | |
02765534 | 710 | } |
e1571908 AJ |
711 | } |
712 | ||
f2442ef9 ND |
713 | /* cmprb - range comparison: isupper, isaplha, islower*/ |
714 | static void gen_cmprb(DisasContext *ctx) | |
715 | { | |
716 | TCGv_i32 src1 = tcg_temp_new_i32(); | |
717 | TCGv_i32 src2 = tcg_temp_new_i32(); | |
718 | TCGv_i32 src2lo = tcg_temp_new_i32(); | |
719 | TCGv_i32 src2hi = tcg_temp_new_i32(); | |
720 | TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; | |
721 | ||
722 | tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); | |
723 | tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); | |
724 | ||
725 | tcg_gen_andi_i32(src1, src1, 0xFF); | |
726 | tcg_gen_ext8u_i32(src2lo, src2); | |
727 | tcg_gen_shri_i32(src2, src2, 8); | |
728 | tcg_gen_ext8u_i32(src2hi, src2); | |
729 | ||
730 | tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); | |
731 | tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); | |
732 | tcg_gen_and_i32(crf, src2lo, src2hi); | |
733 | ||
734 | if (ctx->opcode & 0x00200000) { | |
735 | tcg_gen_shri_i32(src2, src2, 8); | |
736 | tcg_gen_ext8u_i32(src2lo, src2); | |
737 | tcg_gen_shri_i32(src2, src2, 8); | |
738 | tcg_gen_ext8u_i32(src2hi, src2); | |
739 | tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); | |
740 | tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); | |
741 | tcg_gen_and_i32(src2lo, src2lo, src2hi); | |
742 | tcg_gen_or_i32(crf, crf, src2lo); | |
743 | } | |
efa73196 | 744 | tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); |
f2442ef9 ND |
745 | tcg_temp_free_i32(src1); |
746 | tcg_temp_free_i32(src2); | |
747 | tcg_temp_free_i32(src2lo); | |
748 | tcg_temp_free_i32(src2hi); | |
749 | } | |
750 | ||
082ce330 ND |
751 | #if defined(TARGET_PPC64) |
752 | /* cmpeqb */ | |
753 | static void gen_cmpeqb(DisasContext *ctx) | |
754 | { | |
755 | gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
756 | cpu_gpr[rB(ctx->opcode)]); | |
757 | } | |
758 | #endif | |
759 | ||
e1571908 | 760 | /* isel (PowerPC 2.03 specification) */ |
99e300ef | 761 | static void gen_isel(DisasContext *ctx) |
e1571908 | 762 | { |
e1571908 | 763 | uint32_t bi = rC(ctx->opcode); |
24f9cd95 RH |
764 | uint32_t mask = 0x08 >> (bi & 0x03); |
765 | TCGv t0 = tcg_temp_new(); | |
766 | TCGv zr; | |
e1571908 | 767 | |
24f9cd95 RH |
768 | tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); |
769 | tcg_gen_andi_tl(t0, t0, mask); | |
770 | ||
771 | zr = tcg_const_tl(0); | |
772 | tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, | |
773 | rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, | |
774 | cpu_gpr[rB(ctx->opcode)]); | |
775 | tcg_temp_free(zr); | |
776 | tcg_temp_free(t0); | |
e1571908 AJ |
777 | } |
778 | ||
fcfda20f AJ |
779 | /* cmpb: PowerPC 2.05 specification */ |
780 | static void gen_cmpb(DisasContext *ctx) | |
781 | { | |
782 | gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], | |
783 | cpu_gpr[rB(ctx->opcode)]); | |
784 | } | |
785 | ||
79aceca5 | 786 | /*** Integer arithmetic ***/ |
79aceca5 | 787 | |
636aa200 BS |
788 | static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, |
789 | TCGv arg1, TCGv arg2, int sub) | |
74637406 | 790 | { |
ffe30937 | 791 | TCGv t0 = tcg_temp_new(); |
79aceca5 | 792 | |
8e7a6db9 | 793 | tcg_gen_xor_tl(cpu_ov, arg0, arg2); |
74637406 | 794 | tcg_gen_xor_tl(t0, arg1, arg2); |
ffe30937 RH |
795 | if (sub) { |
796 | tcg_gen_and_tl(cpu_ov, cpu_ov, t0); | |
797 | } else { | |
798 | tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); | |
799 | } | |
800 | tcg_temp_free(t0); | |
02765534 | 801 | if (NARROW_MODE(ctx)) { |
dc0ad844 ND |
802 | tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); |
803 | if (is_isa300(ctx)) { | |
804 | tcg_gen_mov_tl(cpu_ov32, cpu_ov); | |
805 | } | |
806 | } else { | |
807 | if (is_isa300(ctx)) { | |
808 | tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); | |
809 | } | |
38a61d34 | 810 | tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); |
ffe30937 | 811 | } |
ffe30937 | 812 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); |
79aceca5 FB |
813 | } |
814 | ||
6b10d008 ND |
815 | static inline void gen_op_arith_compute_ca32(DisasContext *ctx, |
816 | TCGv res, TCGv arg0, TCGv arg1, | |
4c5920af | 817 | TCGv ca32, int sub) |
6b10d008 ND |
818 | { |
819 | TCGv t0; | |
820 | ||
821 | if (!is_isa300(ctx)) { | |
822 | return; | |
823 | } | |
824 | ||
825 | t0 = tcg_temp_new(); | |
33903d0a ND |
826 | if (sub) { |
827 | tcg_gen_eqv_tl(t0, arg0, arg1); | |
828 | } else { | |
829 | tcg_gen_xor_tl(t0, arg0, arg1); | |
830 | } | |
6b10d008 | 831 | tcg_gen_xor_tl(t0, t0, res); |
4c5920af | 832 | tcg_gen_extract_tl(ca32, t0, 32, 1); |
6b10d008 ND |
833 | tcg_temp_free(t0); |
834 | } | |
835 | ||
74637406 | 836 | /* Common add function */ |
636aa200 | 837 | static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
4c5920af SJS |
838 | TCGv arg2, TCGv ca, TCGv ca32, |
839 | bool add_ca, bool compute_ca, | |
b5a73f8d | 840 | bool compute_ov, bool compute_rc0) |
74637406 | 841 | { |
b5a73f8d | 842 | TCGv t0 = ret; |
d9bce9d9 | 843 | |
752d634e | 844 | if (compute_ca || compute_ov) { |
146de60d | 845 | t0 = tcg_temp_new(); |
74637406 | 846 | } |
79aceca5 | 847 | |
da91a00f | 848 | if (compute_ca) { |
79482e5a | 849 | if (NARROW_MODE(ctx)) { |
efe843d8 DG |
850 | /* |
851 | * Caution: a non-obvious corner case of the spec is that | |
852 | * we must produce the *entire* 64-bit addition, but | |
853 | * produce the carry into bit 32. | |
854 | */ | |
79482e5a | 855 | TCGv t1 = tcg_temp_new(); |
752d634e RH |
856 | tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ |
857 | tcg_gen_add_tl(t0, arg1, arg2); | |
79482e5a | 858 | if (add_ca) { |
4c5920af | 859 | tcg_gen_add_tl(t0, t0, ca); |
79482e5a | 860 | } |
4c5920af | 861 | tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ |
752d634e | 862 | tcg_temp_free(t1); |
4c5920af | 863 | tcg_gen_extract_tl(ca, ca, 32, 1); |
6b10d008 | 864 | if (is_isa300(ctx)) { |
4c5920af | 865 | tcg_gen_mov_tl(ca32, ca); |
6b10d008 | 866 | } |
b5a73f8d | 867 | } else { |
79482e5a RH |
868 | TCGv zero = tcg_const_tl(0); |
869 | if (add_ca) { | |
4c5920af SJS |
870 | tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); |
871 | tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); | |
79482e5a | 872 | } else { |
4c5920af | 873 | tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); |
79482e5a | 874 | } |
4c5920af | 875 | gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); |
79482e5a | 876 | tcg_temp_free(zero); |
b5a73f8d | 877 | } |
b5a73f8d RH |
878 | } else { |
879 | tcg_gen_add_tl(t0, arg1, arg2); | |
880 | if (add_ca) { | |
4c5920af | 881 | tcg_gen_add_tl(t0, t0, ca); |
b5a73f8d | 882 | } |
da91a00f | 883 | } |
79aceca5 | 884 | |
74637406 AJ |
885 | if (compute_ov) { |
886 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); | |
887 | } | |
b5a73f8d | 888 | if (unlikely(compute_rc0)) { |
74637406 | 889 | gen_set_Rc0(ctx, t0); |
b5a73f8d | 890 | } |
74637406 | 891 | |
11f4e8f8 | 892 | if (t0 != ret) { |
74637406 AJ |
893 | tcg_gen_mov_tl(ret, t0); |
894 | tcg_temp_free(t0); | |
895 | } | |
39dd32ee | 896 | } |
74637406 | 897 | /* Add functions with two operands */ |
4c5920af | 898 | #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ |
b5a73f8d | 899 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
900 | { \ |
901 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
902 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
4c5920af | 903 | ca, glue(ca, 32), \ |
b5a73f8d | 904 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
905 | } |
906 | /* Add functions with one operand and one immediate */ | |
4c5920af | 907 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ |
74637406 | 908 | add_ca, compute_ca, compute_ov) \ |
b5a73f8d | 909 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 910 | { \ |
b5a73f8d | 911 | TCGv t0 = tcg_const_tl(const_val); \ |
74637406 AJ |
912 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ |
913 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
4c5920af | 914 | ca, glue(ca, 32), \ |
b5a73f8d | 915 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
916 | tcg_temp_free(t0); \ |
917 | } | |
918 | ||
919 | /* add add. addo addo. */ | |
4c5920af SJS |
920 | GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) |
921 | GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) | |
74637406 | 922 | /* addc addc. addco addco. */ |
4c5920af SJS |
923 | GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) |
924 | GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) | |
74637406 | 925 | /* adde adde. addeo addeo. */ |
4c5920af SJS |
926 | GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) |
927 | GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) | |
74637406 | 928 | /* addme addme. addmeo addmeo. */ |
4c5920af SJS |
929 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) |
930 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) | |
931 | /* addex */ | |
932 | GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); | |
74637406 | 933 | /* addze addze. addzeo addzeo.*/ |
4c5920af SJS |
934 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) |
935 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) | |
74637406 | 936 | /* addi */ |
99e300ef | 937 | static void gen_addi(DisasContext *ctx) |
d9bce9d9 | 938 | { |
74637406 AJ |
939 | target_long simm = SIMM(ctx->opcode); |
940 | ||
941 | if (rA(ctx->opcode) == 0) { | |
942 | /* li case */ | |
943 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); | |
944 | } else { | |
b5a73f8d RH |
945 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], |
946 | cpu_gpr[rA(ctx->opcode)], simm); | |
74637406 | 947 | } |
d9bce9d9 | 948 | } |
74637406 | 949 | /* addic addic.*/ |
b5a73f8d | 950 | static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) |
d9bce9d9 | 951 | { |
b5a73f8d RH |
952 | TCGv c = tcg_const_tl(SIMM(ctx->opcode)); |
953 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
4c5920af | 954 | c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); |
b5a73f8d | 955 | tcg_temp_free(c); |
d9bce9d9 | 956 | } |
99e300ef BS |
957 | |
958 | static void gen_addic(DisasContext *ctx) | |
d9bce9d9 | 959 | { |
b5a73f8d | 960 | gen_op_addic(ctx, 0); |
d9bce9d9 | 961 | } |
e8eaa2c0 BS |
962 | |
963 | static void gen_addic_(DisasContext *ctx) | |
d9bce9d9 | 964 | { |
b5a73f8d | 965 | gen_op_addic(ctx, 1); |
d9bce9d9 | 966 | } |
99e300ef | 967 | |
54623277 | 968 | /* addis */ |
99e300ef | 969 | static void gen_addis(DisasContext *ctx) |
d9bce9d9 | 970 | { |
74637406 AJ |
971 | target_long simm = SIMM(ctx->opcode); |
972 | ||
973 | if (rA(ctx->opcode) == 0) { | |
974 | /* lis case */ | |
975 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); | |
976 | } else { | |
b5a73f8d RH |
977 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], |
978 | cpu_gpr[rA(ctx->opcode)], simm << 16); | |
74637406 | 979 | } |
d9bce9d9 | 980 | } |
74637406 | 981 | |
c5b2b9ce ND |
982 | /* addpcis */ |
983 | static void gen_addpcis(DisasContext *ctx) | |
984 | { | |
985 | target_long d = DX(ctx->opcode); | |
986 | ||
b6bac4bc | 987 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16)); |
c5b2b9ce ND |
988 | } |
989 | ||
636aa200 BS |
990 | static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, |
991 | TCGv arg2, int sign, int compute_ov) | |
d9bce9d9 | 992 | { |
b07c32dc ND |
993 | TCGv_i32 t0 = tcg_temp_new_i32(); |
994 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
995 | TCGv_i32 t2 = tcg_temp_new_i32(); | |
996 | TCGv_i32 t3 = tcg_temp_new_i32(); | |
74637406 | 997 | |
2ef1b120 AJ |
998 | tcg_gen_trunc_tl_i32(t0, arg1); |
999 | tcg_gen_trunc_tl_i32(t1, arg2); | |
74637406 | 1000 | if (sign) { |
b07c32dc ND |
1001 | tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); |
1002 | tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); | |
1003 | tcg_gen_and_i32(t2, t2, t3); | |
1004 | tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); | |
1005 | tcg_gen_or_i32(t2, t2, t3); | |
1006 | tcg_gen_movi_i32(t3, 0); | |
1007 | tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1008 | tcg_gen_div_i32(t3, t0, t1); | |
1009 | tcg_gen_extu_i32_tl(ret, t3); | |
74637406 | 1010 | } else { |
b07c32dc ND |
1011 | tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); |
1012 | tcg_gen_movi_i32(t3, 0); | |
1013 | tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1014 | tcg_gen_divu_i32(t3, t0, t1); | |
1015 | tcg_gen_extu_i32_tl(ret, t3); | |
74637406 AJ |
1016 | } |
1017 | if (compute_ov) { | |
b07c32dc | 1018 | tcg_gen_extu_i32_tl(cpu_ov, t2); |
c44027ff ND |
1019 | if (is_isa300(ctx)) { |
1020 | tcg_gen_extu_i32_tl(cpu_ov32, t2); | |
1021 | } | |
b07c32dc | 1022 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); |
74637406 | 1023 | } |
a7812ae4 PB |
1024 | tcg_temp_free_i32(t0); |
1025 | tcg_temp_free_i32(t1); | |
b07c32dc ND |
1026 | tcg_temp_free_i32(t2); |
1027 | tcg_temp_free_i32(t3); | |
1028 | ||
efe843d8 | 1029 | if (unlikely(Rc(ctx->opcode) != 0)) { |
74637406 | 1030 | gen_set_Rc0(ctx, ret); |
efe843d8 | 1031 | } |
d9bce9d9 | 1032 | } |
74637406 AJ |
1033 | /* Div functions */ |
1034 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ | |
efe843d8 | 1035 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
1036 | { \ |
1037 | gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1038 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1039 | sign, compute_ov); \ | |
1040 | } | |
1041 | /* divwu divwu. divwuo divwuo. */ | |
1042 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); | |
1043 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); | |
1044 | /* divw divw. divwo divwo. */ | |
1045 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); | |
1046 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); | |
98d1eb27 TM |
1047 | |
1048 | /* div[wd]eu[o][.] */ | |
1049 | #define GEN_DIVE(name, hlpr, compute_ov) \ | |
1050 | static void gen_##name(DisasContext *ctx) \ | |
1051 | { \ | |
1052 | TCGv_i32 t0 = tcg_const_i32(compute_ov); \ | |
1053 | gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ | |
1054 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ | |
1055 | tcg_temp_free_i32(t0); \ | |
1056 | if (unlikely(Rc(ctx->opcode) != 0)) { \ | |
1057 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ | |
1058 | } \ | |
1059 | } | |
1060 | ||
6a4fda33 TM |
1061 | GEN_DIVE(divweu, divweu, 0); |
1062 | GEN_DIVE(divweuo, divweu, 1); | |
a98eb9e9 TM |
1063 | GEN_DIVE(divwe, divwe, 0); |
1064 | GEN_DIVE(divweo, divwe, 1); | |
6a4fda33 | 1065 | |
d9bce9d9 | 1066 | #if defined(TARGET_PPC64) |
636aa200 BS |
1067 | static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, |
1068 | TCGv arg2, int sign, int compute_ov) | |
d9bce9d9 | 1069 | { |
4110b586 ND |
1070 | TCGv_i64 t0 = tcg_temp_new_i64(); |
1071 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1072 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1073 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
74637406 | 1074 | |
4110b586 ND |
1075 | tcg_gen_mov_i64(t0, arg1); |
1076 | tcg_gen_mov_i64(t1, arg2); | |
74637406 | 1077 | if (sign) { |
4110b586 ND |
1078 | tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); |
1079 | tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); | |
1080 | tcg_gen_and_i64(t2, t2, t3); | |
1081 | tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); | |
1082 | tcg_gen_or_i64(t2, t2, t3); | |
1083 | tcg_gen_movi_i64(t3, 0); | |
1084 | tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1085 | tcg_gen_div_i64(ret, t0, t1); | |
74637406 | 1086 | } else { |
4110b586 ND |
1087 | tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); |
1088 | tcg_gen_movi_i64(t3, 0); | |
1089 | tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1090 | tcg_gen_divu_i64(ret, t0, t1); | |
74637406 AJ |
1091 | } |
1092 | if (compute_ov) { | |
4110b586 | 1093 | tcg_gen_mov_tl(cpu_ov, t2); |
c44027ff ND |
1094 | if (is_isa300(ctx)) { |
1095 | tcg_gen_mov_tl(cpu_ov32, t2); | |
1096 | } | |
4110b586 | 1097 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); |
74637406 | 1098 | } |
4110b586 ND |
1099 | tcg_temp_free_i64(t0); |
1100 | tcg_temp_free_i64(t1); | |
1101 | tcg_temp_free_i64(t2); | |
1102 | tcg_temp_free_i64(t3); | |
1103 | ||
efe843d8 | 1104 | if (unlikely(Rc(ctx->opcode) != 0)) { |
74637406 | 1105 | gen_set_Rc0(ctx, ret); |
efe843d8 | 1106 | } |
d9bce9d9 | 1107 | } |
4110b586 | 1108 | |
74637406 | 1109 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ |
efe843d8 | 1110 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 1111 | { \ |
2ef1b120 AJ |
1112 | gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1113 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1114 | sign, compute_ov); \ | |
74637406 | 1115 | } |
c44027ff | 1116 | /* divdu divdu. divduo divduo. */ |
74637406 AJ |
1117 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); |
1118 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); | |
c44027ff | 1119 | /* divd divd. divdo divdo. */ |
74637406 AJ |
1120 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); |
1121 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); | |
98d1eb27 TM |
1122 | |
1123 | GEN_DIVE(divdeu, divdeu, 0); | |
1124 | GEN_DIVE(divdeuo, divdeu, 1); | |
e44259b6 TM |
1125 | GEN_DIVE(divde, divde, 0); |
1126 | GEN_DIVE(divdeo, divde, 1); | |
d9bce9d9 | 1127 | #endif |
74637406 | 1128 | |
af2c6620 ND |
1129 | static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, |
1130 | TCGv arg2, int sign) | |
1131 | { | |
1132 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
1133 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
1134 | ||
1135 | tcg_gen_trunc_tl_i32(t0, arg1); | |
1136 | tcg_gen_trunc_tl_i32(t1, arg2); | |
1137 | if (sign) { | |
1138 | TCGv_i32 t2 = tcg_temp_new_i32(); | |
1139 | TCGv_i32 t3 = tcg_temp_new_i32(); | |
1140 | tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); | |
1141 | tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); | |
1142 | tcg_gen_and_i32(t2, t2, t3); | |
1143 | tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); | |
1144 | tcg_gen_or_i32(t2, t2, t3); | |
1145 | tcg_gen_movi_i32(t3, 0); | |
1146 | tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1147 | tcg_gen_rem_i32(t3, t0, t1); | |
1148 | tcg_gen_ext_i32_tl(ret, t3); | |
1149 | tcg_temp_free_i32(t2); | |
1150 | tcg_temp_free_i32(t3); | |
1151 | } else { | |
1152 | TCGv_i32 t2 = tcg_const_i32(1); | |
1153 | TCGv_i32 t3 = tcg_const_i32(0); | |
1154 | tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); | |
1155 | tcg_gen_remu_i32(t3, t0, t1); | |
1156 | tcg_gen_extu_i32_tl(ret, t3); | |
1157 | tcg_temp_free_i32(t2); | |
1158 | tcg_temp_free_i32(t3); | |
1159 | } | |
1160 | tcg_temp_free_i32(t0); | |
1161 | tcg_temp_free_i32(t1); | |
1162 | } | |
1163 | ||
1164 | #define GEN_INT_ARITH_MODW(name, opc3, sign) \ | |
1165 | static void glue(gen_, name)(DisasContext *ctx) \ | |
1166 | { \ | |
1167 | gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1168 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1169 | sign); \ | |
1170 | } | |
1171 | ||
1172 | GEN_INT_ARITH_MODW(moduw, 0x08, 0); | |
1173 | GEN_INT_ARITH_MODW(modsw, 0x18, 1); | |
1174 | ||
063cf14f ND |
1175 | #if defined(TARGET_PPC64) |
1176 | static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, | |
1177 | TCGv arg2, int sign) | |
1178 | { | |
1179 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
1180 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1181 | ||
1182 | tcg_gen_mov_i64(t0, arg1); | |
1183 | tcg_gen_mov_i64(t1, arg2); | |
1184 | if (sign) { | |
1185 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1186 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
1187 | tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); | |
1188 | tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); | |
1189 | tcg_gen_and_i64(t2, t2, t3); | |
1190 | tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); | |
1191 | tcg_gen_or_i64(t2, t2, t3); | |
1192 | tcg_gen_movi_i64(t3, 0); | |
1193 | tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1194 | tcg_gen_rem_i64(ret, t0, t1); | |
1195 | tcg_temp_free_i64(t2); | |
1196 | tcg_temp_free_i64(t3); | |
1197 | } else { | |
1198 | TCGv_i64 t2 = tcg_const_i64(1); | |
1199 | TCGv_i64 t3 = tcg_const_i64(0); | |
1200 | tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); | |
1201 | tcg_gen_remu_i64(ret, t0, t1); | |
1202 | tcg_temp_free_i64(t2); | |
1203 | tcg_temp_free_i64(t3); | |
1204 | } | |
1205 | tcg_temp_free_i64(t0); | |
1206 | tcg_temp_free_i64(t1); | |
1207 | } | |
1208 | ||
1209 | #define GEN_INT_ARITH_MODD(name, opc3, sign) \ | |
1210 | static void glue(gen_, name)(DisasContext *ctx) \ | |
1211 | { \ | |
1212 | gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1213 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1214 | sign); \ | |
1215 | } | |
1216 | ||
1217 | GEN_INT_ARITH_MODD(modud, 0x08, 0); | |
1218 | GEN_INT_ARITH_MODD(modsd, 0x18, 1); | |
1219 | #endif | |
1220 | ||
74637406 | 1221 | /* mulhw mulhw. */ |
99e300ef | 1222 | static void gen_mulhw(DisasContext *ctx) |
d9bce9d9 | 1223 | { |
23ad1d5d RH |
1224 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1225 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1226 | |
23ad1d5d RH |
1227 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1228 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1229 | tcg_gen_muls2_i32(t0, t1, t0, t1); | |
1230 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
1231 | tcg_temp_free_i32(t0); | |
1232 | tcg_temp_free_i32(t1); | |
efe843d8 | 1233 | if (unlikely(Rc(ctx->opcode) != 0)) { |
74637406 | 1234 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
efe843d8 | 1235 | } |
d9bce9d9 | 1236 | } |
99e300ef | 1237 | |
54623277 | 1238 | /* mulhwu mulhwu. */ |
99e300ef | 1239 | static void gen_mulhwu(DisasContext *ctx) |
d9bce9d9 | 1240 | { |
23ad1d5d RH |
1241 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1242 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1243 | |
23ad1d5d RH |
1244 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1245 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1246 | tcg_gen_mulu2_i32(t0, t1, t0, t1); | |
1247 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
1248 | tcg_temp_free_i32(t0); | |
1249 | tcg_temp_free_i32(t1); | |
efe843d8 | 1250 | if (unlikely(Rc(ctx->opcode) != 0)) { |
74637406 | 1251 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
efe843d8 | 1252 | } |
d9bce9d9 | 1253 | } |
99e300ef | 1254 | |
54623277 | 1255 | /* mullw mullw. */ |
99e300ef | 1256 | static void gen_mullw(DisasContext *ctx) |
d9bce9d9 | 1257 | { |
1fa74845 TM |
1258 | #if defined(TARGET_PPC64) |
1259 | TCGv_i64 t0, t1; | |
1260 | t0 = tcg_temp_new_i64(); | |
1261 | t1 = tcg_temp_new_i64(); | |
1262 | tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); | |
1263 | tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); | |
1264 | tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
1265 | tcg_temp_free(t0); | |
1266 | tcg_temp_free(t1); | |
1267 | #else | |
03039e5e TM |
1268 | tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1269 | cpu_gpr[rB(ctx->opcode)]); | |
1fa74845 | 1270 | #endif |
efe843d8 | 1271 | if (unlikely(Rc(ctx->opcode) != 0)) { |
74637406 | 1272 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
efe843d8 | 1273 | } |
d9bce9d9 | 1274 | } |
99e300ef | 1275 | |
54623277 | 1276 | /* mullwo mullwo. */ |
99e300ef | 1277 | static void gen_mullwo(DisasContext *ctx) |
d9bce9d9 | 1278 | { |
e4a2c846 RH |
1279 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1280 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1281 | |
e4a2c846 RH |
1282 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1283 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1284 | tcg_gen_muls2_i32(t0, t1, t0, t1); | |
f11ebbf8 | 1285 | #if defined(TARGET_PPC64) |
26977876 TM |
1286 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); |
1287 | #else | |
1288 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); | |
f11ebbf8 | 1289 | #endif |
e4a2c846 RH |
1290 | |
1291 | tcg_gen_sari_i32(t0, t0, 31); | |
1292 | tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); | |
1293 | tcg_gen_extu_i32_tl(cpu_ov, t0); | |
61aa9a69 ND |
1294 | if (is_isa300(ctx)) { |
1295 | tcg_gen_mov_tl(cpu_ov32, cpu_ov); | |
1296 | } | |
e4a2c846 RH |
1297 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); |
1298 | ||
1299 | tcg_temp_free_i32(t0); | |
1300 | tcg_temp_free_i32(t1); | |
efe843d8 | 1301 | if (unlikely(Rc(ctx->opcode) != 0)) { |
74637406 | 1302 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
efe843d8 | 1303 | } |
d9bce9d9 | 1304 | } |
99e300ef | 1305 | |
54623277 | 1306 | /* mulli */ |
99e300ef | 1307 | static void gen_mulli(DisasContext *ctx) |
d9bce9d9 | 1308 | { |
74637406 AJ |
1309 | tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1310 | SIMM(ctx->opcode)); | |
d9bce9d9 | 1311 | } |
23ad1d5d | 1312 | |
d9bce9d9 | 1313 | #if defined(TARGET_PPC64) |
74637406 | 1314 | /* mulhd mulhd. */ |
23ad1d5d RH |
1315 | static void gen_mulhd(DisasContext *ctx) |
1316 | { | |
1317 | TCGv lo = tcg_temp_new(); | |
1318 | tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], | |
1319 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1320 | tcg_temp_free(lo); | |
1321 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1322 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1323 | } | |
1324 | } | |
1325 | ||
74637406 | 1326 | /* mulhdu mulhdu. */ |
23ad1d5d RH |
1327 | static void gen_mulhdu(DisasContext *ctx) |
1328 | { | |
1329 | TCGv lo = tcg_temp_new(); | |
1330 | tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], | |
1331 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1332 | tcg_temp_free(lo); | |
1333 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1334 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1335 | } | |
1336 | } | |
99e300ef | 1337 | |
54623277 | 1338 | /* mulld mulld. */ |
99e300ef | 1339 | static void gen_mulld(DisasContext *ctx) |
d9bce9d9 | 1340 | { |
74637406 AJ |
1341 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1342 | cpu_gpr[rB(ctx->opcode)]); | |
efe843d8 | 1343 | if (unlikely(Rc(ctx->opcode) != 0)) { |
74637406 | 1344 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
efe843d8 | 1345 | } |
d9bce9d9 | 1346 | } |
d15f74fb | 1347 | |
74637406 | 1348 | /* mulldo mulldo. */ |
d15f74fb BS |
1349 | static void gen_mulldo(DisasContext *ctx) |
1350 | { | |
22ffad31 TM |
1351 | TCGv_i64 t0 = tcg_temp_new_i64(); |
1352 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1353 | ||
1354 | tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], | |
1355 | cpu_gpr[rB(ctx->opcode)]); | |
1356 | tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); | |
1357 | ||
1358 | tcg_gen_sari_i64(t0, t0, 63); | |
1359 | tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); | |
61aa9a69 ND |
1360 | if (is_isa300(ctx)) { |
1361 | tcg_gen_mov_tl(cpu_ov32, cpu_ov); | |
1362 | } | |
22ffad31 TM |
1363 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); |
1364 | ||
1365 | tcg_temp_free_i64(t0); | |
1366 | tcg_temp_free_i64(t1); | |
1367 | ||
d15f74fb BS |
1368 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1369 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1370 | } | |
1371 | } | |
d9bce9d9 | 1372 | #endif |
74637406 | 1373 | |
74637406 | 1374 | /* Common subf function */ |
636aa200 | 1375 | static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, |
b5a73f8d RH |
1376 | TCGv arg2, bool add_ca, bool compute_ca, |
1377 | bool compute_ov, bool compute_rc0) | |
79aceca5 | 1378 | { |
b5a73f8d | 1379 | TCGv t0 = ret; |
79aceca5 | 1380 | |
752d634e | 1381 | if (compute_ca || compute_ov) { |
b5a73f8d | 1382 | t0 = tcg_temp_new(); |
da91a00f | 1383 | } |
74637406 | 1384 | |
79482e5a RH |
1385 | if (compute_ca) { |
1386 | /* dest = ~arg1 + arg2 [+ ca]. */ | |
1387 | if (NARROW_MODE(ctx)) { | |
efe843d8 DG |
1388 | /* |
1389 | * Caution: a non-obvious corner case of the spec is that | |
1390 | * we must produce the *entire* 64-bit addition, but | |
1391 | * produce the carry into bit 32. | |
1392 | */ | |
79482e5a | 1393 | TCGv inv1 = tcg_temp_new(); |
752d634e | 1394 | TCGv t1 = tcg_temp_new(); |
79482e5a | 1395 | tcg_gen_not_tl(inv1, arg1); |
79482e5a | 1396 | if (add_ca) { |
752d634e | 1397 | tcg_gen_add_tl(t0, arg2, cpu_ca); |
79482e5a | 1398 | } else { |
752d634e | 1399 | tcg_gen_addi_tl(t0, arg2, 1); |
79482e5a | 1400 | } |
752d634e | 1401 | tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ |
79482e5a | 1402 | tcg_gen_add_tl(t0, t0, inv1); |
c80d1df5 | 1403 | tcg_temp_free(inv1); |
752d634e RH |
1404 | tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ |
1405 | tcg_temp_free(t1); | |
e2622073 | 1406 | tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); |
33903d0a ND |
1407 | if (is_isa300(ctx)) { |
1408 | tcg_gen_mov_tl(cpu_ca32, cpu_ca); | |
1409 | } | |
79482e5a | 1410 | } else if (add_ca) { |
08f4a0f7 RH |
1411 | TCGv zero, inv1 = tcg_temp_new(); |
1412 | tcg_gen_not_tl(inv1, arg1); | |
b5a73f8d RH |
1413 | zero = tcg_const_tl(0); |
1414 | tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); | |
08f4a0f7 | 1415 | tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); |
4c5920af | 1416 | gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); |
b5a73f8d | 1417 | tcg_temp_free(zero); |
08f4a0f7 | 1418 | tcg_temp_free(inv1); |
b5a73f8d | 1419 | } else { |
79482e5a | 1420 | tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); |
b5a73f8d | 1421 | tcg_gen_sub_tl(t0, arg2, arg1); |
4c5920af | 1422 | gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); |
b5a73f8d | 1423 | } |
79482e5a | 1424 | } else if (add_ca) { |
efe843d8 DG |
1425 | /* |
1426 | * Since we're ignoring carry-out, we can simplify the | |
1427 | * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. | |
1428 | */ | |
79482e5a RH |
1429 | tcg_gen_sub_tl(t0, arg2, arg1); |
1430 | tcg_gen_add_tl(t0, t0, cpu_ca); | |
1431 | tcg_gen_subi_tl(t0, t0, 1); | |
79aceca5 | 1432 | } else { |
b5a73f8d | 1433 | tcg_gen_sub_tl(t0, arg2, arg1); |
74637406 | 1434 | } |
b5a73f8d | 1435 | |
74637406 AJ |
1436 | if (compute_ov) { |
1437 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); | |
1438 | } | |
b5a73f8d | 1439 | if (unlikely(compute_rc0)) { |
74637406 | 1440 | gen_set_Rc0(ctx, t0); |
b5a73f8d | 1441 | } |
74637406 | 1442 | |
11f4e8f8 | 1443 | if (t0 != ret) { |
74637406 AJ |
1444 | tcg_gen_mov_tl(ret, t0); |
1445 | tcg_temp_free(t0); | |
79aceca5 | 1446 | } |
79aceca5 | 1447 | } |
74637406 AJ |
1448 | /* Sub functions with Two operands functions */ |
1449 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 1450 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
1451 | { \ |
1452 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1453 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
b5a73f8d | 1454 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
1455 | } |
1456 | /* Sub functions with one operand and one immediate */ | |
1457 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ | |
1458 | add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 1459 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 1460 | { \ |
b5a73f8d | 1461 | TCGv t0 = tcg_const_tl(const_val); \ |
74637406 AJ |
1462 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1463 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
b5a73f8d | 1464 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
1465 | tcg_temp_free(t0); \ |
1466 | } | |
1467 | /* subf subf. subfo subfo. */ | |
1468 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) | |
1469 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) | |
1470 | /* subfc subfc. subfco subfco. */ | |
1471 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) | |
1472 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) | |
1473 | /* subfe subfe. subfeo subfo. */ | |
1474 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) | |
1475 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) | |
1476 | /* subfme subfme. subfmeo subfmeo. */ | |
1477 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) | |
1478 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) | |
1479 | /* subfze subfze. subfzeo subfzeo.*/ | |
1480 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) | |
1481 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) | |
99e300ef | 1482 | |
54623277 | 1483 | /* subfic */ |
99e300ef | 1484 | static void gen_subfic(DisasContext *ctx) |
79aceca5 | 1485 | { |
b5a73f8d RH |
1486 | TCGv c = tcg_const_tl(SIMM(ctx->opcode)); |
1487 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
1488 | c, 0, 1, 0, 0); | |
1489 | tcg_temp_free(c); | |
79aceca5 FB |
1490 | } |
1491 | ||
fd3f0081 RH |
1492 | /* neg neg. nego nego. */ |
1493 | static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) | |
1494 | { | |
1495 | TCGv zero = tcg_const_tl(0); | |
1496 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
1497 | zero, 0, 0, compute_ov, Rc(ctx->opcode)); | |
1498 | tcg_temp_free(zero); | |
1499 | } | |
1500 | ||
1501 | static void gen_neg(DisasContext *ctx) | |
1502 | { | |
1480d71c ND |
1503 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
1504 | if (unlikely(Rc(ctx->opcode))) { | |
1505 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1506 | } | |
fd3f0081 RH |
1507 | } |
1508 | ||
1509 | static void gen_nego(DisasContext *ctx) | |
1510 | { | |
1511 | gen_op_arith_neg(ctx, 1); | |
1512 | } | |
1513 | ||
79aceca5 | 1514 | /*** Integer logical ***/ |
26d67362 | 1515 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ |
efe843d8 | 1516 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 1517 | { \ |
26d67362 AJ |
1518 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ |
1519 | cpu_gpr[rB(ctx->opcode)]); \ | |
76a66253 | 1520 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
26d67362 | 1521 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
79aceca5 | 1522 | } |
79aceca5 | 1523 | |
26d67362 | 1524 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ |
efe843d8 | 1525 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 1526 | { \ |
26d67362 | 1527 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ |
76a66253 | 1528 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
26d67362 | 1529 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
79aceca5 FB |
1530 | } |
1531 | ||
1532 | /* and & and. */ | |
26d67362 | 1533 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); |
79aceca5 | 1534 | /* andc & andc. */ |
26d67362 | 1535 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); |
e8eaa2c0 | 1536 | |
54623277 | 1537 | /* andi. */ |
e8eaa2c0 | 1538 | static void gen_andi_(DisasContext *ctx) |
79aceca5 | 1539 | { |
efe843d8 DG |
1540 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], |
1541 | UIMM(ctx->opcode)); | |
26d67362 | 1542 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 | 1543 | } |
e8eaa2c0 | 1544 | |
54623277 | 1545 | /* andis. */ |
e8eaa2c0 | 1546 | static void gen_andis_(DisasContext *ctx) |
79aceca5 | 1547 | { |
efe843d8 DG |
1548 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], |
1549 | UIMM(ctx->opcode) << 16); | |
26d67362 | 1550 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 | 1551 | } |
99e300ef | 1552 | |
54623277 | 1553 | /* cntlzw */ |
99e300ef | 1554 | static void gen_cntlzw(DisasContext *ctx) |
26d67362 | 1555 | { |
9b8514e5 RH |
1556 | TCGv_i32 t = tcg_temp_new_i32(); |
1557 | ||
1558 | tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); | |
1559 | tcg_gen_clzi_i32(t, t, 32); | |
1560 | tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); | |
1561 | tcg_temp_free_i32(t); | |
1562 | ||
efe843d8 | 1563 | if (unlikely(Rc(ctx->opcode) != 0)) { |
2e31f5d3 | 1564 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 1565 | } |
26d67362 | 1566 | } |
b35344e4 ND |
1567 | |
1568 | /* cnttzw */ | |
1569 | static void gen_cnttzw(DisasContext *ctx) | |
1570 | { | |
9b8514e5 RH |
1571 | TCGv_i32 t = tcg_temp_new_i32(); |
1572 | ||
1573 | tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); | |
1574 | tcg_gen_ctzi_i32(t, t, 32); | |
1575 | tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); | |
1576 | tcg_temp_free_i32(t); | |
1577 | ||
b35344e4 ND |
1578 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1579 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1580 | } | |
1581 | } | |
1582 | ||
79aceca5 | 1583 | /* eqv & eqv. */ |
26d67362 | 1584 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); |
79aceca5 | 1585 | /* extsb & extsb. */ |
26d67362 | 1586 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); |
79aceca5 | 1587 | /* extsh & extsh. */ |
26d67362 | 1588 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); |
79aceca5 | 1589 | /* nand & nand. */ |
26d67362 | 1590 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); |
79aceca5 | 1591 | /* nor & nor. */ |
26d67362 | 1592 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); |
99e300ef | 1593 | |
7f2b1744 | 1594 | #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) |
b68e60e6 BH |
1595 | static void gen_pause(DisasContext *ctx) |
1596 | { | |
1597 | TCGv_i32 t0 = tcg_const_i32(0); | |
1598 | tcg_gen_st_i32(t0, cpu_env, | |
1599 | -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); | |
1600 | tcg_temp_free_i32(t0); | |
1601 | ||
1602 | /* Stop translation, this gives other CPUs a chance to run */ | |
b6bac4bc | 1603 | gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); |
b68e60e6 BH |
1604 | } |
1605 | #endif /* defined(TARGET_PPC64) */ | |
1606 | ||
54623277 | 1607 | /* or & or. */ |
99e300ef | 1608 | static void gen_or(DisasContext *ctx) |
9a64fbe4 | 1609 | { |
76a66253 JM |
1610 | int rs, ra, rb; |
1611 | ||
1612 | rs = rS(ctx->opcode); | |
1613 | ra = rA(ctx->opcode); | |
1614 | rb = rB(ctx->opcode); | |
1615 | /* Optimisation for mr. ri case */ | |
1616 | if (rs != ra || rs != rb) { | |
efe843d8 | 1617 | if (rs != rb) { |
26d67362 | 1618 | tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); |
efe843d8 | 1619 | } else { |
26d67362 | 1620 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); |
efe843d8 DG |
1621 | } |
1622 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
26d67362 | 1623 | gen_set_Rc0(ctx, cpu_gpr[ra]); |
efe843d8 | 1624 | } |
76a66253 | 1625 | } else if (unlikely(Rc(ctx->opcode) != 0)) { |
26d67362 | 1626 | gen_set_Rc0(ctx, cpu_gpr[rs]); |
c80f84e3 | 1627 | #if defined(TARGET_PPC64) |
9e196938 | 1628 | } else if (rs != 0) { /* 0 is nop */ |
26d67362 AJ |
1629 | int prio = 0; |
1630 | ||
c80f84e3 JM |
1631 | switch (rs) { |
1632 | case 1: | |
1633 | /* Set process priority to low */ | |
26d67362 | 1634 | prio = 2; |
c80f84e3 JM |
1635 | break; |
1636 | case 6: | |
1637 | /* Set process priority to medium-low */ | |
26d67362 | 1638 | prio = 3; |
c80f84e3 JM |
1639 | break; |
1640 | case 2: | |
1641 | /* Set process priority to normal */ | |
26d67362 | 1642 | prio = 4; |
c80f84e3 | 1643 | break; |
be147d08 JM |
1644 | #if !defined(CONFIG_USER_ONLY) |
1645 | case 31: | |
c47493f2 | 1646 | if (!ctx->pr) { |
be147d08 | 1647 | /* Set process priority to very low */ |
26d67362 | 1648 | prio = 1; |
be147d08 JM |
1649 | } |
1650 | break; | |
1651 | case 5: | |
c47493f2 | 1652 | if (!ctx->pr) { |
be147d08 | 1653 | /* Set process priority to medium-hight */ |
26d67362 | 1654 | prio = 5; |
be147d08 JM |
1655 | } |
1656 | break; | |
1657 | case 3: | |
c47493f2 | 1658 | if (!ctx->pr) { |
be147d08 | 1659 | /* Set process priority to high */ |
26d67362 | 1660 | prio = 6; |
be147d08 JM |
1661 | } |
1662 | break; | |
be147d08 | 1663 | case 7: |
b68e60e6 | 1664 | if (ctx->hv && !ctx->pr) { |
be147d08 | 1665 | /* Set process priority to very high */ |
26d67362 | 1666 | prio = 7; |
be147d08 JM |
1667 | } |
1668 | break; | |
be147d08 | 1669 | #endif |
c80f84e3 | 1670 | default: |
c80f84e3 JM |
1671 | break; |
1672 | } | |
26d67362 | 1673 | if (prio) { |
a7812ae4 | 1674 | TCGv t0 = tcg_temp_new(); |
54cdcae6 | 1675 | gen_load_spr(t0, SPR_PPR); |
ea363694 AJ |
1676 | tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); |
1677 | tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); | |
54cdcae6 | 1678 | gen_store_spr(SPR_PPR, t0); |
ea363694 | 1679 | tcg_temp_free(t0); |
9e196938 | 1680 | } |
7f2b1744 | 1681 | #if !defined(CONFIG_USER_ONLY) |
efe843d8 DG |
1682 | /* |
1683 | * Pause out of TCG otherwise spin loops with smt_low eat too | |
1684 | * much CPU and the kernel hangs. This applies to all | |
1685 | * encodings other than no-op, e.g., miso(rs=26), yield(27), | |
1686 | * mdoio(29), mdoom(30), and all currently undefined. | |
9e196938 AL |
1687 | */ |
1688 | gen_pause(ctx); | |
7f2b1744 | 1689 | #endif |
c80f84e3 | 1690 | #endif |
9a64fbe4 | 1691 | } |
9a64fbe4 | 1692 | } |
79aceca5 | 1693 | /* orc & orc. */ |
26d67362 | 1694 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); |
99e300ef | 1695 | |
54623277 | 1696 | /* xor & xor. */ |
99e300ef | 1697 | static void gen_xor(DisasContext *ctx) |
9a64fbe4 | 1698 | { |
9a64fbe4 | 1699 | /* Optimisation for "set to zero" case */ |
efe843d8 DG |
1700 | if (rS(ctx->opcode) != rB(ctx->opcode)) { |
1701 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], | |
1702 | cpu_gpr[rB(ctx->opcode)]); | |
1703 | } else { | |
26d67362 | 1704 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); |
efe843d8 DG |
1705 | } |
1706 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
26d67362 | 1707 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 1708 | } |
9a64fbe4 | 1709 | } |
99e300ef | 1710 | |
54623277 | 1711 | /* ori */ |
99e300ef | 1712 | static void gen_ori(DisasContext *ctx) |
79aceca5 | 1713 | { |
76a66253 | 1714 | target_ulong uimm = UIMM(ctx->opcode); |
79aceca5 | 1715 | |
9a64fbe4 | 1716 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
9a64fbe4 | 1717 | return; |
76a66253 | 1718 | } |
26d67362 | 1719 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
79aceca5 | 1720 | } |
99e300ef | 1721 | |
54623277 | 1722 | /* oris */ |
99e300ef | 1723 | static void gen_oris(DisasContext *ctx) |
79aceca5 | 1724 | { |
76a66253 | 1725 | target_ulong uimm = UIMM(ctx->opcode); |
79aceca5 | 1726 | |
9a64fbe4 FB |
1727 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1728 | /* NOP */ | |
1729 | return; | |
76a66253 | 1730 | } |
efe843d8 DG |
1731 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], |
1732 | uimm << 16); | |
79aceca5 | 1733 | } |
99e300ef | 1734 | |
54623277 | 1735 | /* xori */ |
99e300ef | 1736 | static void gen_xori(DisasContext *ctx) |
79aceca5 | 1737 | { |
76a66253 | 1738 | target_ulong uimm = UIMM(ctx->opcode); |
9a64fbe4 FB |
1739 | |
1740 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
1741 | /* NOP */ | |
1742 | return; | |
1743 | } | |
26d67362 | 1744 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
79aceca5 | 1745 | } |
99e300ef | 1746 | |
54623277 | 1747 | /* xoris */ |
99e300ef | 1748 | static void gen_xoris(DisasContext *ctx) |
79aceca5 | 1749 | { |
76a66253 | 1750 | target_ulong uimm = UIMM(ctx->opcode); |
9a64fbe4 FB |
1751 | |
1752 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
1753 | /* NOP */ | |
1754 | return; | |
1755 | } | |
efe843d8 DG |
1756 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], |
1757 | uimm << 16); | |
79aceca5 | 1758 | } |
99e300ef | 1759 | |
54623277 | 1760 | /* popcntb : PowerPC 2.03 specification */ |
99e300ef | 1761 | static void gen_popcntb(DisasContext *ctx) |
d9bce9d9 | 1762 | { |
eaabeef2 DG |
1763 | gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1764 | } | |
1765 | ||
1766 | static void gen_popcntw(DisasContext *ctx) | |
1767 | { | |
79770002 | 1768 | #if defined(TARGET_PPC64) |
eaabeef2 | 1769 | gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
79770002 RH |
1770 | #else |
1771 | tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1772 | #endif | |
eaabeef2 DG |
1773 | } |
1774 | ||
d9bce9d9 | 1775 | #if defined(TARGET_PPC64) |
eaabeef2 DG |
1776 | /* popcntd: PowerPC 2.06 specification */ |
1777 | static void gen_popcntd(DisasContext *ctx) | |
1778 | { | |
79770002 | 1779 | tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
d9bce9d9 | 1780 | } |
eaabeef2 | 1781 | #endif |
d9bce9d9 | 1782 | |
725bcec2 AJ |
1783 | /* prtyw: PowerPC 2.05 specification */ |
1784 | static void gen_prtyw(DisasContext *ctx) | |
1785 | { | |
1786 | TCGv ra = cpu_gpr[rA(ctx->opcode)]; | |
1787 | TCGv rs = cpu_gpr[rS(ctx->opcode)]; | |
1788 | TCGv t0 = tcg_temp_new(); | |
1789 | tcg_gen_shri_tl(t0, rs, 16); | |
1790 | tcg_gen_xor_tl(ra, rs, t0); | |
1791 | tcg_gen_shri_tl(t0, ra, 8); | |
1792 | tcg_gen_xor_tl(ra, ra, t0); | |
1793 | tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); | |
1794 | tcg_temp_free(t0); | |
1795 | } | |
1796 | ||
1797 | #if defined(TARGET_PPC64) | |
1798 | /* prtyd: PowerPC 2.05 specification */ | |
1799 | static void gen_prtyd(DisasContext *ctx) | |
1800 | { | |
1801 | TCGv ra = cpu_gpr[rA(ctx->opcode)]; | |
1802 | TCGv rs = cpu_gpr[rS(ctx->opcode)]; | |
1803 | TCGv t0 = tcg_temp_new(); | |
1804 | tcg_gen_shri_tl(t0, rs, 32); | |
1805 | tcg_gen_xor_tl(ra, rs, t0); | |
1806 | tcg_gen_shri_tl(t0, ra, 16); | |
1807 | tcg_gen_xor_tl(ra, ra, t0); | |
1808 | tcg_gen_shri_tl(t0, ra, 8); | |
1809 | tcg_gen_xor_tl(ra, ra, t0); | |
1810 | tcg_gen_andi_tl(ra, ra, 1); | |
1811 | tcg_temp_free(t0); | |
1812 | } | |
1813 | #endif | |
1814 | ||
86ba37ed TM |
1815 | #if defined(TARGET_PPC64) |
1816 | /* bpermd */ | |
1817 | static void gen_bpermd(DisasContext *ctx) | |
1818 | { | |
1819 | gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], | |
1820 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1821 | } | |
1822 | #endif | |
1823 | ||
d9bce9d9 JM |
1824 | #if defined(TARGET_PPC64) |
1825 | /* extsw & extsw. */ | |
26d67362 | 1826 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); |
99e300ef | 1827 | |
54623277 | 1828 | /* cntlzd */ |
99e300ef | 1829 | static void gen_cntlzd(DisasContext *ctx) |
26d67362 | 1830 | { |
9b8514e5 | 1831 | tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); |
efe843d8 | 1832 | if (unlikely(Rc(ctx->opcode) != 0)) { |
26d67362 | 1833 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 1834 | } |
26d67362 | 1835 | } |
e91d95b2 SD |
1836 | |
1837 | /* cnttzd */ | |
1838 | static void gen_cnttzd(DisasContext *ctx) | |
1839 | { | |
9b8514e5 | 1840 | tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); |
e91d95b2 SD |
1841 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1842 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1843 | } | |
1844 | } | |
fec5c62a RB |
1845 | |
1846 | /* darn */ | |
1847 | static void gen_darn(DisasContext *ctx) | |
1848 | { | |
1849 | int l = L(ctx->opcode); | |
1850 | ||
7e4357f6 | 1851 | if (l > 2) { |
fec5c62a | 1852 | tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); |
7e4357f6 RH |
1853 | } else { |
1854 | if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { | |
1855 | gen_io_start(); | |
1856 | } | |
1857 | if (l == 0) { | |
1858 | gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); | |
1859 | } else { | |
1860 | /* Return 64-bit random for both CRN and RRN */ | |
1861 | gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); | |
1862 | } | |
1863 | if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { | |
7e4357f6 RH |
1864 | gen_stop_exception(ctx); |
1865 | } | |
fec5c62a RB |
1866 | } |
1867 | } | |
d9bce9d9 JM |
1868 | #endif |
1869 | ||
79aceca5 | 1870 | /*** Integer rotate ***/ |
99e300ef | 1871 | |
54623277 | 1872 | /* rlwimi & rlwimi. */ |
99e300ef | 1873 | static void gen_rlwimi(DisasContext *ctx) |
79aceca5 | 1874 | { |
63ae0915 RH |
1875 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
1876 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
1877 | uint32_t sh = SH(ctx->opcode); | |
1878 | uint32_t mb = MB(ctx->opcode); | |
1879 | uint32_t me = ME(ctx->opcode); | |
1880 | ||
efe843d8 | 1881 | if (sh == (31 - me) && mb <= me) { |
63ae0915 | 1882 | tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); |
d03ef511 | 1883 | } else { |
d03ef511 | 1884 | target_ulong mask; |
c4f6a4a3 | 1885 | bool mask_in_32b = true; |
a7812ae4 | 1886 | TCGv t1; |
63ae0915 | 1887 | |
76a66253 | 1888 | #if defined(TARGET_PPC64) |
d03ef511 AJ |
1889 | mb += 32; |
1890 | me += 32; | |
76a66253 | 1891 | #endif |
d03ef511 | 1892 | mask = MASK(mb, me); |
63ae0915 | 1893 | |
c4f6a4a3 DB |
1894 | #if defined(TARGET_PPC64) |
1895 | if (mask > 0xffffffffu) { | |
1896 | mask_in_32b = false; | |
1897 | } | |
1898 | #endif | |
a7812ae4 | 1899 | t1 = tcg_temp_new(); |
c4f6a4a3 | 1900 | if (mask_in_32b) { |
2e11b15d RH |
1901 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1902 | tcg_gen_trunc_tl_i32(t0, t_rs); | |
1903 | tcg_gen_rotli_i32(t0, t0, sh); | |
1904 | tcg_gen_extu_i32_tl(t1, t0); | |
1905 | tcg_temp_free_i32(t0); | |
1906 | } else { | |
1907 | #if defined(TARGET_PPC64) | |
1908 | tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); | |
1909 | tcg_gen_rotli_i64(t1, t1, sh); | |
1910 | #else | |
1911 | g_assert_not_reached(); | |
1912 | #endif | |
1913 | } | |
63ae0915 RH |
1914 | |
1915 | tcg_gen_andi_tl(t1, t1, mask); | |
1916 | tcg_gen_andi_tl(t_ra, t_ra, ~mask); | |
1917 | tcg_gen_or_tl(t_ra, t_ra, t1); | |
d03ef511 AJ |
1918 | tcg_temp_free(t1); |
1919 | } | |
63ae0915 RH |
1920 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1921 | gen_set_Rc0(ctx, t_ra); | |
1922 | } | |
79aceca5 | 1923 | } |
99e300ef | 1924 | |
54623277 | 1925 | /* rlwinm & rlwinm. */ |
99e300ef | 1926 | static void gen_rlwinm(DisasContext *ctx) |
79aceca5 | 1927 | { |
63ae0915 RH |
1928 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
1929 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
7b4d326f RH |
1930 | int sh = SH(ctx->opcode); |
1931 | int mb = MB(ctx->opcode); | |
1932 | int me = ME(ctx->opcode); | |
1933 | int len = me - mb + 1; | |
1934 | int rsh = (32 - sh) & 31; | |
1935 | ||
1936 | if (sh != 0 && len > 0 && me == (31 - sh)) { | |
1937 | tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); | |
1938 | } else if (me == 31 && rsh + len <= 32) { | |
1939 | tcg_gen_extract_tl(t_ra, t_rs, rsh, len); | |
d03ef511 | 1940 | } else { |
2e11b15d | 1941 | target_ulong mask; |
c4f6a4a3 | 1942 | bool mask_in_32b = true; |
76a66253 | 1943 | #if defined(TARGET_PPC64) |
d03ef511 AJ |
1944 | mb += 32; |
1945 | me += 32; | |
76a66253 | 1946 | #endif |
2e11b15d | 1947 | mask = MASK(mb, me); |
c4f6a4a3 DB |
1948 | #if defined(TARGET_PPC64) |
1949 | if (mask > 0xffffffffu) { | |
1950 | mask_in_32b = false; | |
1951 | } | |
1952 | #endif | |
1953 | if (mask_in_32b) { | |
94f040aa VC |
1954 | if (sh == 0) { |
1955 | tcg_gen_andi_tl(t_ra, t_rs, mask); | |
1956 | } else { | |
1957 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
1958 | tcg_gen_trunc_tl_i32(t0, t_rs); | |
1959 | tcg_gen_rotli_i32(t0, t0, sh); | |
1960 | tcg_gen_andi_i32(t0, t0, mask); | |
1961 | tcg_gen_extu_i32_tl(t_ra, t0); | |
1962 | tcg_temp_free_i32(t0); | |
1963 | } | |
2e11b15d RH |
1964 | } else { |
1965 | #if defined(TARGET_PPC64) | |
1966 | tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); | |
1967 | tcg_gen_rotli_i64(t_ra, t_ra, sh); | |
1968 | tcg_gen_andi_i64(t_ra, t_ra, mask); | |
1969 | #else | |
1970 | g_assert_not_reached(); | |
1971 | #endif | |
63ae0915 RH |
1972 | } |
1973 | } | |
1974 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1975 | gen_set_Rc0(ctx, t_ra); | |
d03ef511 | 1976 | } |
79aceca5 | 1977 | } |
99e300ef | 1978 | |
54623277 | 1979 | /* rlwnm & rlwnm. */ |
99e300ef | 1980 | static void gen_rlwnm(DisasContext *ctx) |
79aceca5 | 1981 | { |
63ae0915 RH |
1982 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
1983 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
1984 | TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; | |
1985 | uint32_t mb = MB(ctx->opcode); | |
1986 | uint32_t me = ME(ctx->opcode); | |
2e11b15d | 1987 | target_ulong mask; |
c4f6a4a3 | 1988 | bool mask_in_32b = true; |
57fca134 | 1989 | |
54843a58 | 1990 | #if defined(TARGET_PPC64) |
63ae0915 RH |
1991 | mb += 32; |
1992 | me += 32; | |
54843a58 | 1993 | #endif |
2e11b15d RH |
1994 | mask = MASK(mb, me); |
1995 | ||
c4f6a4a3 DB |
1996 | #if defined(TARGET_PPC64) |
1997 | if (mask > 0xffffffffu) { | |
1998 | mask_in_32b = false; | |
1999 | } | |
2000 | #endif | |
2001 | if (mask_in_32b) { | |
2e11b15d RH |
2002 | TCGv_i32 t0 = tcg_temp_new_i32(); |
2003 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
2004 | tcg_gen_trunc_tl_i32(t0, t_rb); | |
2005 | tcg_gen_trunc_tl_i32(t1, t_rs); | |
2006 | tcg_gen_andi_i32(t0, t0, 0x1f); | |
2007 | tcg_gen_rotl_i32(t1, t1, t0); | |
2008 | tcg_gen_extu_i32_tl(t_ra, t1); | |
2009 | tcg_temp_free_i32(t0); | |
2010 | tcg_temp_free_i32(t1); | |
2011 | } else { | |
2012 | #if defined(TARGET_PPC64) | |
2013 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
2014 | tcg_gen_andi_i64(t0, t_rb, 0x1f); | |
2015 | tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); | |
2016 | tcg_gen_rotl_i64(t_ra, t_ra, t0); | |
2017 | tcg_temp_free_i64(t0); | |
2018 | #else | |
2019 | g_assert_not_reached(); | |
2020 | #endif | |
2021 | } | |
57fca134 | 2022 | |
2e11b15d | 2023 | tcg_gen_andi_tl(t_ra, t_ra, mask); |
63ae0915 RH |
2024 | |
2025 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2026 | gen_set_Rc0(ctx, t_ra); | |
79aceca5 | 2027 | } |
79aceca5 FB |
2028 | } |
2029 | ||
d9bce9d9 JM |
2030 | #if defined(TARGET_PPC64) |
2031 | #define GEN_PPC64_R2(name, opc1, opc2) \ | |
e8eaa2c0 | 2032 | static void glue(gen_, name##0)(DisasContext *ctx) \ |
d9bce9d9 JM |
2033 | { \ |
2034 | gen_##name(ctx, 0); \ | |
2035 | } \ | |
e8eaa2c0 BS |
2036 | \ |
2037 | static void glue(gen_, name##1)(DisasContext *ctx) \ | |
d9bce9d9 JM |
2038 | { \ |
2039 | gen_##name(ctx, 1); \ | |
2040 | } | |
2041 | #define GEN_PPC64_R4(name, opc1, opc2) \ | |
e8eaa2c0 | 2042 | static void glue(gen_, name##0)(DisasContext *ctx) \ |
d9bce9d9 JM |
2043 | { \ |
2044 | gen_##name(ctx, 0, 0); \ | |
2045 | } \ | |
e8eaa2c0 BS |
2046 | \ |
2047 | static void glue(gen_, name##1)(DisasContext *ctx) \ | |
d9bce9d9 JM |
2048 | { \ |
2049 | gen_##name(ctx, 0, 1); \ | |
2050 | } \ | |
e8eaa2c0 BS |
2051 | \ |
2052 | static void glue(gen_, name##2)(DisasContext *ctx) \ | |
d9bce9d9 JM |
2053 | { \ |
2054 | gen_##name(ctx, 1, 0); \ | |
2055 | } \ | |
e8eaa2c0 BS |
2056 | \ |
2057 | static void glue(gen_, name##3)(DisasContext *ctx) \ | |
d9bce9d9 JM |
2058 | { \ |
2059 | gen_##name(ctx, 1, 1); \ | |
2060 | } | |
51789c41 | 2061 | |
a7b2c8b9 | 2062 | static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) |
51789c41 | 2063 | { |
a7b2c8b9 RH |
2064 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
2065 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
7b4d326f RH |
2066 | int len = me - mb + 1; |
2067 | int rsh = (64 - sh) & 63; | |
a7b2c8b9 | 2068 | |
7b4d326f RH |
2069 | if (sh != 0 && len > 0 && me == (63 - sh)) { |
2070 | tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); | |
2071 | } else if (me == 63 && rsh + len <= 64) { | |
2072 | tcg_gen_extract_tl(t_ra, t_rs, rsh, len); | |
d03ef511 | 2073 | } else { |
a7b2c8b9 RH |
2074 | tcg_gen_rotli_tl(t_ra, t_rs, sh); |
2075 | tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); | |
2076 | } | |
2077 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2078 | gen_set_Rc0(ctx, t_ra); | |
51789c41 | 2079 | } |
51789c41 | 2080 | } |
a7b2c8b9 | 2081 | |
d9bce9d9 | 2082 | /* rldicl - rldicl. */ |
636aa200 | 2083 | static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 2084 | { |
51789c41 | 2085 | uint32_t sh, mb; |
d9bce9d9 | 2086 | |
9d53c753 JM |
2087 | sh = SH(ctx->opcode) | (shn << 5); |
2088 | mb = MB(ctx->opcode) | (mbn << 5); | |
51789c41 | 2089 | gen_rldinm(ctx, mb, 63, sh); |
d9bce9d9 | 2090 | } |
51789c41 | 2091 | GEN_PPC64_R4(rldicl, 0x1E, 0x00); |
a7b2c8b9 | 2092 | |
d9bce9d9 | 2093 | /* rldicr - rldicr. */ |
636aa200 | 2094 | static inline void gen_rldicr(DisasContext *ctx, int men, int shn) |
d9bce9d9 | 2095 | { |
51789c41 | 2096 | uint32_t sh, me; |
d9bce9d9 | 2097 | |
9d53c753 JM |
2098 | sh = SH(ctx->opcode) | (shn << 5); |
2099 | me = MB(ctx->opcode) | (men << 5); | |
51789c41 | 2100 | gen_rldinm(ctx, 0, me, sh); |
d9bce9d9 | 2101 | } |
51789c41 | 2102 | GEN_PPC64_R4(rldicr, 0x1E, 0x02); |
a7b2c8b9 | 2103 | |
d9bce9d9 | 2104 | /* rldic - rldic. */ |
636aa200 | 2105 | static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 2106 | { |
51789c41 | 2107 | uint32_t sh, mb; |
d9bce9d9 | 2108 | |
9d53c753 JM |
2109 | sh = SH(ctx->opcode) | (shn << 5); |
2110 | mb = MB(ctx->opcode) | (mbn << 5); | |
51789c41 JM |
2111 | gen_rldinm(ctx, mb, 63 - sh, sh); |
2112 | } | |
2113 | GEN_PPC64_R4(rldic, 0x1E, 0x04); | |
2114 | ||
a7b2c8b9 | 2115 | static void gen_rldnm(DisasContext *ctx, int mb, int me) |
51789c41 | 2116 | { |
a7b2c8b9 RH |
2117 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
2118 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
2119 | TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; | |
54843a58 | 2120 | TCGv t0; |
d03ef511 | 2121 | |
a7812ae4 | 2122 | t0 = tcg_temp_new(); |
a7b2c8b9 RH |
2123 | tcg_gen_andi_tl(t0, t_rb, 0x3f); |
2124 | tcg_gen_rotl_tl(t_ra, t_rs, t0); | |
54843a58 | 2125 | tcg_temp_free(t0); |
a7b2c8b9 RH |
2126 | |
2127 | tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); | |
2128 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2129 | gen_set_Rc0(ctx, t_ra); | |
2130 | } | |
d9bce9d9 | 2131 | } |
51789c41 | 2132 | |
d9bce9d9 | 2133 | /* rldcl - rldcl. */ |
636aa200 | 2134 | static inline void gen_rldcl(DisasContext *ctx, int mbn) |
d9bce9d9 | 2135 | { |
51789c41 | 2136 | uint32_t mb; |
d9bce9d9 | 2137 | |
9d53c753 | 2138 | mb = MB(ctx->opcode) | (mbn << 5); |
51789c41 | 2139 | gen_rldnm(ctx, mb, 63); |
d9bce9d9 | 2140 | } |
36081602 | 2141 | GEN_PPC64_R2(rldcl, 0x1E, 0x08); |
a7b2c8b9 | 2142 | |
d9bce9d9 | 2143 | /* rldcr - rldcr. */ |
636aa200 | 2144 | static inline void gen_rldcr(DisasContext *ctx, int men) |
d9bce9d9 | 2145 | { |
51789c41 | 2146 | uint32_t me; |
d9bce9d9 | 2147 | |
9d53c753 | 2148 | me = MB(ctx->opcode) | (men << 5); |
51789c41 | 2149 | gen_rldnm(ctx, 0, me); |
d9bce9d9 | 2150 | } |
36081602 | 2151 | GEN_PPC64_R2(rldcr, 0x1E, 0x09); |
a7b2c8b9 | 2152 | |
d9bce9d9 | 2153 | /* rldimi - rldimi. */ |
a7b2c8b9 | 2154 | static void gen_rldimi(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 2155 | { |
a7b2c8b9 RH |
2156 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
2157 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
2158 | uint32_t sh = SH(ctx->opcode) | (shn << 5); | |
2159 | uint32_t mb = MB(ctx->opcode) | (mbn << 5); | |
2160 | uint32_t me = 63 - sh; | |
d9bce9d9 | 2161 | |
a7b2c8b9 RH |
2162 | if (mb <= me) { |
2163 | tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); | |
d03ef511 | 2164 | } else { |
a7b2c8b9 RH |
2165 | target_ulong mask = MASK(mb, me); |
2166 | TCGv t1 = tcg_temp_new(); | |
d03ef511 | 2167 | |
a7b2c8b9 RH |
2168 | tcg_gen_rotli_tl(t1, t_rs, sh); |
2169 | tcg_gen_andi_tl(t1, t1, mask); | |
2170 | tcg_gen_andi_tl(t_ra, t_ra, ~mask); | |
2171 | tcg_gen_or_tl(t_ra, t_ra, t1); | |
d03ef511 | 2172 | tcg_temp_free(t1); |
51789c41 | 2173 | } |
a7b2c8b9 RH |
2174 | if (unlikely(Rc(ctx->opcode) != 0)) { |
2175 | gen_set_Rc0(ctx, t_ra); | |
2176 | } | |
d9bce9d9 | 2177 | } |
36081602 | 2178 | GEN_PPC64_R4(rldimi, 0x1E, 0x06); |
d9bce9d9 JM |
2179 | #endif |
2180 | ||
79aceca5 | 2181 | /*** Integer shift ***/ |
99e300ef | 2182 | |
54623277 | 2183 | /* slw & slw. */ |
99e300ef | 2184 | static void gen_slw(DisasContext *ctx) |
26d67362 | 2185 | { |
7fd6bf7d | 2186 | TCGv t0, t1; |
26d67362 | 2187 | |
7fd6bf7d AJ |
2188 | t0 = tcg_temp_new(); |
2189 | /* AND rS with a mask that is 0 when rB >= 0x20 */ | |
2190 | #if defined(TARGET_PPC64) | |
2191 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); | |
2192 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
2193 | #else | |
2194 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); | |
2195 | tcg_gen_sari_tl(t0, t0, 0x1f); | |
2196 | #endif | |
2197 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
2198 | t1 = tcg_temp_new(); | |
2199 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); | |
2200 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
2201 | tcg_temp_free(t1); | |
fea0c503 | 2202 | tcg_temp_free(t0); |
7fd6bf7d | 2203 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 2204 | if (unlikely(Rc(ctx->opcode) != 0)) { |
26d67362 | 2205 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 2206 | } |
26d67362 | 2207 | } |
99e300ef | 2208 | |
54623277 | 2209 | /* sraw & sraw. */ |
99e300ef | 2210 | static void gen_sraw(DisasContext *ctx) |
26d67362 | 2211 | { |
d15f74fb | 2212 | gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, |
a7812ae4 | 2213 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
efe843d8 | 2214 | if (unlikely(Rc(ctx->opcode) != 0)) { |
26d67362 | 2215 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 2216 | } |
26d67362 | 2217 | } |
99e300ef | 2218 | |
54623277 | 2219 | /* srawi & srawi. */ |
99e300ef | 2220 | static void gen_srawi(DisasContext *ctx) |
79aceca5 | 2221 | { |
26d67362 | 2222 | int sh = SH(ctx->opcode); |
ba4af3e4 RH |
2223 | TCGv dst = cpu_gpr[rA(ctx->opcode)]; |
2224 | TCGv src = cpu_gpr[rS(ctx->opcode)]; | |
2225 | if (sh == 0) { | |
34a0fad1 | 2226 | tcg_gen_ext32s_tl(dst, src); |
da91a00f | 2227 | tcg_gen_movi_tl(cpu_ca, 0); |
af1c259f SD |
2228 | if (is_isa300(ctx)) { |
2229 | tcg_gen_movi_tl(cpu_ca32, 0); | |
2230 | } | |
26d67362 | 2231 | } else { |
ba4af3e4 RH |
2232 | TCGv t0; |
2233 | tcg_gen_ext32s_tl(dst, src); | |
2234 | tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); | |
2235 | t0 = tcg_temp_new(); | |
2236 | tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); | |
2237 | tcg_gen_and_tl(cpu_ca, cpu_ca, t0); | |
2238 | tcg_temp_free(t0); | |
2239 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); | |
af1c259f SD |
2240 | if (is_isa300(ctx)) { |
2241 | tcg_gen_mov_tl(cpu_ca32, cpu_ca); | |
2242 | } | |
ba4af3e4 RH |
2243 | tcg_gen_sari_tl(dst, dst, sh); |
2244 | } | |
2245 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2246 | gen_set_Rc0(ctx, dst); | |
d9bce9d9 | 2247 | } |
79aceca5 | 2248 | } |
99e300ef | 2249 | |
54623277 | 2250 | /* srw & srw. */ |
99e300ef | 2251 | static void gen_srw(DisasContext *ctx) |
26d67362 | 2252 | { |
fea0c503 | 2253 | TCGv t0, t1; |
d9bce9d9 | 2254 | |
7fd6bf7d AJ |
2255 | t0 = tcg_temp_new(); |
2256 | /* AND rS with a mask that is 0 when rB >= 0x20 */ | |
2257 | #if defined(TARGET_PPC64) | |
2258 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); | |
2259 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
2260 | #else | |
2261 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); | |
2262 | tcg_gen_sari_tl(t0, t0, 0x1f); | |
2263 | #endif | |
2264 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
2265 | tcg_gen_ext32u_tl(t0, t0); | |
a7812ae4 | 2266 | t1 = tcg_temp_new(); |
7fd6bf7d AJ |
2267 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); |
2268 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
fea0c503 | 2269 | tcg_temp_free(t1); |
fea0c503 | 2270 | tcg_temp_free(t0); |
efe843d8 | 2271 | if (unlikely(Rc(ctx->opcode) != 0)) { |
26d67362 | 2272 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 2273 | } |
26d67362 | 2274 | } |
54623277 | 2275 | |
d9bce9d9 JM |
2276 | #if defined(TARGET_PPC64) |
2277 | /* sld & sld. */ | |
99e300ef | 2278 | static void gen_sld(DisasContext *ctx) |
26d67362 | 2279 | { |
7fd6bf7d | 2280 | TCGv t0, t1; |
26d67362 | 2281 | |
7fd6bf7d AJ |
2282 | t0 = tcg_temp_new(); |
2283 | /* AND rS with a mask that is 0 when rB >= 0x40 */ | |
2284 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); | |
2285 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
2286 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
2287 | t1 = tcg_temp_new(); | |
2288 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); | |
2289 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
2290 | tcg_temp_free(t1); | |
fea0c503 | 2291 | tcg_temp_free(t0); |
efe843d8 | 2292 | if (unlikely(Rc(ctx->opcode) != 0)) { |
26d67362 | 2293 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 2294 | } |
26d67362 | 2295 | } |
99e300ef | 2296 | |
54623277 | 2297 | /* srad & srad. */ |
99e300ef | 2298 | static void gen_srad(DisasContext *ctx) |
26d67362 | 2299 | { |
d15f74fb | 2300 | gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, |
a7812ae4 | 2301 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
efe843d8 | 2302 | if (unlikely(Rc(ctx->opcode) != 0)) { |
26d67362 | 2303 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 2304 | } |
26d67362 | 2305 | } |
d9bce9d9 | 2306 | /* sradi & sradi. */ |
636aa200 | 2307 | static inline void gen_sradi(DisasContext *ctx, int n) |
d9bce9d9 | 2308 | { |
26d67362 | 2309 | int sh = SH(ctx->opcode) + (n << 5); |
ba4af3e4 RH |
2310 | TCGv dst = cpu_gpr[rA(ctx->opcode)]; |
2311 | TCGv src = cpu_gpr[rS(ctx->opcode)]; | |
2312 | if (sh == 0) { | |
2313 | tcg_gen_mov_tl(dst, src); | |
da91a00f | 2314 | tcg_gen_movi_tl(cpu_ca, 0); |
af1c259f SD |
2315 | if (is_isa300(ctx)) { |
2316 | tcg_gen_movi_tl(cpu_ca32, 0); | |
2317 | } | |
26d67362 | 2318 | } else { |
ba4af3e4 RH |
2319 | TCGv t0; |
2320 | tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); | |
2321 | t0 = tcg_temp_new(); | |
2322 | tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); | |
2323 | tcg_gen_and_tl(cpu_ca, cpu_ca, t0); | |
2324 | tcg_temp_free(t0); | |
2325 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); | |
af1c259f SD |
2326 | if (is_isa300(ctx)) { |
2327 | tcg_gen_mov_tl(cpu_ca32, cpu_ca); | |
2328 | } | |
ba4af3e4 RH |
2329 | tcg_gen_sari_tl(dst, src, sh); |
2330 | } | |
2331 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2332 | gen_set_Rc0(ctx, dst); | |
d9bce9d9 | 2333 | } |
d9bce9d9 | 2334 | } |
e8eaa2c0 BS |
2335 | |
2336 | static void gen_sradi0(DisasContext *ctx) | |
d9bce9d9 JM |
2337 | { |
2338 | gen_sradi(ctx, 0); | |
2339 | } | |
e8eaa2c0 BS |
2340 | |
2341 | static void gen_sradi1(DisasContext *ctx) | |
d9bce9d9 JM |
2342 | { |
2343 | gen_sradi(ctx, 1); | |
2344 | } | |
99e300ef | 2345 | |
787bbe37 ND |
2346 | /* extswsli & extswsli. */ |
2347 | static inline void gen_extswsli(DisasContext *ctx, int n) | |
2348 | { | |
2349 | int sh = SH(ctx->opcode) + (n << 5); | |
2350 | TCGv dst = cpu_gpr[rA(ctx->opcode)]; | |
2351 | TCGv src = cpu_gpr[rS(ctx->opcode)]; | |
2352 | ||
2353 | tcg_gen_ext32s_tl(dst, src); | |
2354 | tcg_gen_shli_tl(dst, dst, sh); | |
2355 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2356 | gen_set_Rc0(ctx, dst); | |
2357 | } | |
2358 | } | |
2359 | ||
2360 | static void gen_extswsli0(DisasContext *ctx) | |
2361 | { | |
2362 | gen_extswsli(ctx, 0); | |
2363 | } | |
2364 | ||
2365 | static void gen_extswsli1(DisasContext *ctx) | |
2366 | { | |
2367 | gen_extswsli(ctx, 1); | |
2368 | } | |
2369 | ||
54623277 | 2370 | /* srd & srd. */ |
99e300ef | 2371 | static void gen_srd(DisasContext *ctx) |
26d67362 | 2372 | { |
7fd6bf7d | 2373 | TCGv t0, t1; |
26d67362 | 2374 | |
7fd6bf7d AJ |
2375 | t0 = tcg_temp_new(); |
2376 | /* AND rS with a mask that is 0 when rB >= 0x40 */ | |
2377 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); | |
2378 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
2379 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
2380 | t1 = tcg_temp_new(); | |
2381 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); | |
2382 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
2383 | tcg_temp_free(t1); | |
fea0c503 | 2384 | tcg_temp_free(t0); |
efe843d8 | 2385 | if (unlikely(Rc(ctx->opcode) != 0)) { |
26d67362 | 2386 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 2387 | } |
26d67362 | 2388 | } |
d9bce9d9 | 2389 | #endif |
79aceca5 | 2390 | |
76a66253 JM |
2391 | /*** Addressing modes ***/ |
2392 | /* Register indirect with immediate index : EA = (rA|0) + SIMM */ | |
636aa200 BS |
2393 | static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, |
2394 | target_long maskl) | |
76a66253 JM |
2395 | { |
2396 | target_long simm = SIMM(ctx->opcode); | |
2397 | ||
be147d08 | 2398 | simm &= ~maskl; |
76db3ba4 | 2399 | if (rA(ctx->opcode) == 0) { |
c791fe84 RH |
2400 | if (NARROW_MODE(ctx)) { |
2401 | simm = (uint32_t)simm; | |
2402 | } | |
e2be8d8d | 2403 | tcg_gen_movi_tl(EA, simm); |
76db3ba4 | 2404 | } else if (likely(simm != 0)) { |
e2be8d8d | 2405 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); |
c791fe84 | 2406 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
2407 | tcg_gen_ext32u_tl(EA, EA); |
2408 | } | |
76db3ba4 | 2409 | } else { |
c791fe84 | 2410 | if (NARROW_MODE(ctx)) { |
76db3ba4 | 2411 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
c791fe84 RH |
2412 | } else { |
2413 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
2414 | } | |
76db3ba4 | 2415 | } |
76a66253 JM |
2416 | } |
2417 | ||
636aa200 | 2418 | static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) |
76a66253 | 2419 | { |
76db3ba4 | 2420 | if (rA(ctx->opcode) == 0) { |
c791fe84 | 2421 | if (NARROW_MODE(ctx)) { |
76db3ba4 | 2422 | tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); |
c791fe84 RH |
2423 | } else { |
2424 | tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); | |
2425 | } | |
76db3ba4 | 2426 | } else { |
e2be8d8d | 2427 | tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
c791fe84 | 2428 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
2429 | tcg_gen_ext32u_tl(EA, EA); |
2430 | } | |
76db3ba4 | 2431 | } |
76a66253 JM |
2432 | } |
2433 | ||
636aa200 | 2434 | static inline void gen_addr_register(DisasContext *ctx, TCGv EA) |
76a66253 | 2435 | { |
76db3ba4 | 2436 | if (rA(ctx->opcode) == 0) { |
e2be8d8d | 2437 | tcg_gen_movi_tl(EA, 0); |
c791fe84 RH |
2438 | } else if (NARROW_MODE(ctx)) { |
2439 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
76db3ba4 | 2440 | } else { |
c791fe84 | 2441 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
76db3ba4 AJ |
2442 | } |
2443 | } | |
2444 | ||
636aa200 BS |
2445 | static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
2446 | target_long val) | |
76db3ba4 AJ |
2447 | { |
2448 | tcg_gen_addi_tl(ret, arg1, val); | |
c791fe84 | 2449 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
2450 | tcg_gen_ext32u_tl(ret, ret); |
2451 | } | |
76a66253 JM |
2452 | } |
2453 | ||
65f2475f BH |
2454 | static inline void gen_align_no_le(DisasContext *ctx) |
2455 | { | |
2456 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, | |
2457 | (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); | |
2458 | } | |
2459 | ||
7863667f | 2460 | /*** Integer load ***/ |
09bfe50d | 2461 | #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) |
ff5f3981 | 2462 | #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) |
b61f2753 | 2463 | |
09bfe50d ND |
2464 | #define GEN_QEMU_LOAD_TL(ldop, op) \ |
2465 | static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ | |
2466 | TCGv val, \ | |
2467 | TCGv addr) \ | |
2468 | { \ | |
2469 | tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ | |
b61f2753 AJ |
2470 | } |
2471 | ||
09bfe50d ND |
2472 | GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) |
2473 | GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) | |
2474 | GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) | |
2475 | GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) | |
2476 | GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) | |
f976b09e | 2477 | |
ff5f3981 ND |
2478 | GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) |
2479 | GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) | |
2480 | ||
09bfe50d ND |
2481 | #define GEN_QEMU_LOAD_64(ldop, op) \ |
2482 | static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ | |
2483 | TCGv_i64 val, \ | |
2484 | TCGv addr) \ | |
2485 | { \ | |
2486 | tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ | |
b61f2753 AJ |
2487 | } |
2488 | ||
740ae9a2 ND |
2489 | GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) |
2490 | GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) | |
09bfe50d ND |
2491 | GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) |
2492 | GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) | |
4f364fe7 | 2493 | GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) |
b61f2753 | 2494 | |
ff5f3981 ND |
2495 | #if defined(TARGET_PPC64) |
2496 | GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) | |
2497 | #endif | |
2498 | ||
761a89c6 ND |
2499 | #define GEN_QEMU_STORE_TL(stop, op) \ |
2500 | static void glue(gen_qemu_, stop)(DisasContext *ctx, \ | |
2501 | TCGv val, \ | |
2502 | TCGv addr) \ | |
2503 | { \ | |
2504 | tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ | |
b61f2753 AJ |
2505 | } |
2506 | ||
761a89c6 ND |
2507 | GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) |
2508 | GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) | |
2509 | GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) | |
b61f2753 | 2510 | |
804108aa ND |
2511 | GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) |
2512 | GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) | |
2513 | ||
761a89c6 ND |
2514 | #define GEN_QEMU_STORE_64(stop, op) \ |
2515 | static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ | |
2516 | TCGv_i64 val, \ | |
2517 | TCGv addr) \ | |
2518 | { \ | |
2519 | tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ | |
b61f2753 AJ |
2520 | } |
2521 | ||
ddb9ac50 ND |
2522 | GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) |
2523 | GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) | |
761a89c6 | 2524 | GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) |
2468f23d | 2525 | GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) |
b61f2753 | 2526 | |
804108aa ND |
2527 | #if defined(TARGET_PPC64) |
2528 | GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) | |
2529 | #endif | |
2530 | ||
0c8aacd4 | 2531 | #define GEN_LD(name, ldop, opc, type) \ |
efe843d8 | 2532 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 2533 | { \ |
76db3ba4 AJ |
2534 | TCGv EA; \ |
2535 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2536 | EA = tcg_temp_new(); \ | |
2537 | gen_addr_imm_index(ctx, EA, 0); \ | |
2538 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 | 2539 | tcg_temp_free(EA); \ |
79aceca5 FB |
2540 | } |
2541 | ||
0c8aacd4 | 2542 | #define GEN_LDU(name, ldop, opc, type) \ |
efe843d8 | 2543 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
79aceca5 | 2544 | { \ |
b61f2753 | 2545 | TCGv EA; \ |
76a66253 JM |
2546 | if (unlikely(rA(ctx->opcode) == 0 || \ |
2547 | rA(ctx->opcode) == rD(ctx->opcode))) { \ | |
e06fcd75 | 2548 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2549 | return; \ |
9a64fbe4 | 2550 | } \ |
76db3ba4 | 2551 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2552 | EA = tcg_temp_new(); \ |
9d53c753 | 2553 | if (type == PPC_64B) \ |
76db3ba4 | 2554 | gen_addr_imm_index(ctx, EA, 0x03); \ |
9d53c753 | 2555 | else \ |
76db3ba4 AJ |
2556 | gen_addr_imm_index(ctx, EA, 0); \ |
2557 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2558 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2559 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2560 | } |
2561 | ||
0c8aacd4 | 2562 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \ |
efe843d8 | 2563 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 2564 | { \ |
b61f2753 | 2565 | TCGv EA; \ |
76a66253 JM |
2566 | if (unlikely(rA(ctx->opcode) == 0 || \ |
2567 | rA(ctx->opcode) == rD(ctx->opcode))) { \ | |
e06fcd75 | 2568 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2569 | return; \ |
9a64fbe4 | 2570 | } \ |
76db3ba4 | 2571 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2572 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
2573 | gen_addr_reg_index(ctx, EA); \ |
2574 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2575 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2576 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2577 | } |
2578 | ||
b7815375 | 2579 | #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ |
99e300ef | 2580 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 2581 | { \ |
76db3ba4 | 2582 | TCGv EA; \ |
b7815375 | 2583 | chk; \ |
76db3ba4 AJ |
2584 | gen_set_access_type(ctx, ACCESS_INT); \ |
2585 | EA = tcg_temp_new(); \ | |
2586 | gen_addr_reg_index(ctx, EA); \ | |
2587 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 | 2588 | tcg_temp_free(EA); \ |
79aceca5 | 2589 | } |
b7815375 | 2590 | |
cd6e9320 | 2591 | #define GEN_LDX(name, ldop, opc2, opc3, type) \ |
b7815375 BH |
2592 | GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) |
2593 | ||
2594 | #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ | |
2595 | GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) | |
79aceca5 | 2596 | |
0c8aacd4 AJ |
2597 | #define GEN_LDS(name, ldop, op, type) \ |
2598 | GEN_LD(name, ldop, op | 0x20, type); \ | |
2599 | GEN_LDU(name, ldop, op | 0x21, type); \ | |
2600 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ | |
2601 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) | |
79aceca5 FB |
2602 | |
2603 | /* lbz lbzu lbzux lbzx */ | |
0c8aacd4 | 2604 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); |
79aceca5 | 2605 | /* lha lhau lhaux lhax */ |
0c8aacd4 | 2606 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); |
79aceca5 | 2607 | /* lhz lhzu lhzux lhzx */ |
0c8aacd4 | 2608 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); |
79aceca5 | 2609 | /* lwz lwzu lwzux lwzx */ |
0c8aacd4 | 2610 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); |
50728199 RK |
2611 | |
2612 | #define GEN_LDEPX(name, ldop, opc2, opc3) \ | |
2613 | static void glue(gen_, name##epx)(DisasContext *ctx) \ | |
2614 | { \ | |
2615 | TCGv EA; \ | |
2616 | CHK_SV; \ | |
2617 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2618 | EA = tcg_temp_new(); \ | |
2619 | gen_addr_reg_index(ctx, EA); \ | |
2620 | tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ | |
2621 | tcg_temp_free(EA); \ | |
2622 | } | |
2623 | ||
2624 | GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) | |
2625 | GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) | |
2626 | GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) | |
2627 | #if defined(TARGET_PPC64) | |
2628 | GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) | |
2629 | #endif | |
2630 | ||
d9bce9d9 | 2631 | #if defined(TARGET_PPC64) |
d9bce9d9 | 2632 | /* lwaux */ |
0c8aacd4 | 2633 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); |
d9bce9d9 | 2634 | /* lwax */ |
0c8aacd4 | 2635 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); |
d9bce9d9 | 2636 | /* ldux */ |
4f364fe7 | 2637 | GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B); |
d9bce9d9 | 2638 | /* ldx */ |
4f364fe7 | 2639 | GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B); |
99e300ef | 2640 | |
b7815375 | 2641 | /* CI load/store variants */ |
4f364fe7 | 2642 | GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) |
b7815375 BH |
2643 | GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) |
2644 | GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) | |
2645 | GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) | |
2646 | ||
99e300ef | 2647 | static void gen_ld(DisasContext *ctx) |
d9bce9d9 | 2648 | { |
b61f2753 | 2649 | TCGv EA; |
d9bce9d9 JM |
2650 | if (Rc(ctx->opcode)) { |
2651 | if (unlikely(rA(ctx->opcode) == 0 || | |
2652 | rA(ctx->opcode) == rD(ctx->opcode))) { | |
e06fcd75 | 2653 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
d9bce9d9 JM |
2654 | return; |
2655 | } | |
2656 | } | |
76db3ba4 | 2657 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2658 | EA = tcg_temp_new(); |
76db3ba4 | 2659 | gen_addr_imm_index(ctx, EA, 0x03); |
d9bce9d9 JM |
2660 | if (ctx->opcode & 0x02) { |
2661 | /* lwa (lwau is undefined) */ | |
76db3ba4 | 2662 | gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
d9bce9d9 JM |
2663 | } else { |
2664 | /* ld - ldu */ | |
4f364fe7 | 2665 | gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
d9bce9d9 | 2666 | } |
efe843d8 | 2667 | if (Rc(ctx->opcode)) { |
b61f2753 | 2668 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
efe843d8 | 2669 | } |
b61f2753 | 2670 | tcg_temp_free(EA); |
d9bce9d9 | 2671 | } |
99e300ef | 2672 | |
54623277 | 2673 | /* lq */ |
99e300ef | 2674 | static void gen_lq(DisasContext *ctx) |
be147d08 | 2675 | { |
be147d08 | 2676 | int ra, rd; |
94bf2658 | 2677 | TCGv EA, hi, lo; |
be147d08 | 2678 | |
e0498daa TM |
2679 | /* lq is a legal user mode instruction starting in ISA 2.07 */ |
2680 | bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; | |
2681 | bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; | |
2682 | ||
c47493f2 | 2683 | if (!legal_in_user_mode && ctx->pr) { |
9b2fadda | 2684 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2685 | return; |
2686 | } | |
e0498daa TM |
2687 | |
2688 | if (!le_is_supported && ctx->le_mode) { | |
65f2475f | 2689 | gen_align_no_le(ctx); |
e0498daa TM |
2690 | return; |
2691 | } | |
be147d08 JM |
2692 | ra = rA(ctx->opcode); |
2693 | rd = rD(ctx->opcode); | |
2694 | if (unlikely((rd & 1) || rd == ra)) { | |
e06fcd75 | 2695 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
be147d08 JM |
2696 | return; |
2697 | } | |
e0498daa | 2698 | |
76db3ba4 | 2699 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2700 | EA = tcg_temp_new(); |
76db3ba4 | 2701 | gen_addr_imm_index(ctx, EA, 0x0F); |
e0498daa | 2702 | |
94bf2658 RH |
2703 | /* Note that the low part is always in RD+1, even in LE mode. */ |
2704 | lo = cpu_gpr[rd + 1]; | |
2705 | hi = cpu_gpr[rd]; | |
2706 | ||
2707 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { | |
f34ec0f6 RH |
2708 | if (HAVE_ATOMIC128) { |
2709 | TCGv_i32 oi = tcg_temp_new_i32(); | |
2710 | if (ctx->le_mode) { | |
2711 | tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); | |
2712 | gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); | |
2713 | } else { | |
2714 | tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); | |
2715 | gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); | |
2716 | } | |
2717 | tcg_temp_free_i32(oi); | |
2718 | tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); | |
94bf2658 | 2719 | } else { |
f34ec0f6 RH |
2720 | /* Restart with exclusive lock. */ |
2721 | gen_helper_exit_atomic(cpu_env); | |
2722 | ctx->base.is_jmp = DISAS_NORETURN; | |
94bf2658 | 2723 | } |
94bf2658 RH |
2724 | } else if (ctx->le_mode) { |
2725 | tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ); | |
e0498daa | 2726 | gen_addr_add(ctx, EA, EA, 8); |
94bf2658 | 2727 | tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); |
e0498daa | 2728 | } else { |
94bf2658 | 2729 | tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ); |
e0498daa | 2730 | gen_addr_add(ctx, EA, EA, 8); |
94bf2658 | 2731 | tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); |
e0498daa | 2732 | } |
b61f2753 | 2733 | tcg_temp_free(EA); |
be147d08 | 2734 | } |
d9bce9d9 | 2735 | #endif |
79aceca5 FB |
2736 | |
2737 | /*** Integer store ***/ | |
0c8aacd4 | 2738 | #define GEN_ST(name, stop, opc, type) \ |
efe843d8 | 2739 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 2740 | { \ |
76db3ba4 AJ |
2741 | TCGv EA; \ |
2742 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2743 | EA = tcg_temp_new(); \ | |
2744 | gen_addr_imm_index(ctx, EA, 0); \ | |
2745 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 | 2746 | tcg_temp_free(EA); \ |
79aceca5 FB |
2747 | } |
2748 | ||
0c8aacd4 | 2749 | #define GEN_STU(name, stop, opc, type) \ |
efe843d8 | 2750 | static void glue(gen_, stop##u)(DisasContext *ctx) \ |
79aceca5 | 2751 | { \ |
b61f2753 | 2752 | TCGv EA; \ |
76a66253 | 2753 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 2754 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2755 | return; \ |
9a64fbe4 | 2756 | } \ |
76db3ba4 | 2757 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2758 | EA = tcg_temp_new(); \ |
9d53c753 | 2759 | if (type == PPC_64B) \ |
76db3ba4 | 2760 | gen_addr_imm_index(ctx, EA, 0x03); \ |
9d53c753 | 2761 | else \ |
76db3ba4 AJ |
2762 | gen_addr_imm_index(ctx, EA, 0); \ |
2763 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2764 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2765 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2766 | } |
2767 | ||
0c8aacd4 | 2768 | #define GEN_STUX(name, stop, opc2, opc3, type) \ |
efe843d8 | 2769 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 2770 | { \ |
b61f2753 | 2771 | TCGv EA; \ |
76a66253 | 2772 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 2773 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2774 | return; \ |
9a64fbe4 | 2775 | } \ |
76db3ba4 | 2776 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2777 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
2778 | gen_addr_reg_index(ctx, EA); \ |
2779 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2780 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2781 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2782 | } |
2783 | ||
b7815375 | 2784 | #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ |
cd6e9320 | 2785 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 2786 | { \ |
76db3ba4 | 2787 | TCGv EA; \ |
b7815375 | 2788 | chk; \ |
76db3ba4 AJ |
2789 | gen_set_access_type(ctx, ACCESS_INT); \ |
2790 | EA = tcg_temp_new(); \ | |
2791 | gen_addr_reg_index(ctx, EA); \ | |
2792 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 | 2793 | tcg_temp_free(EA); \ |
79aceca5 | 2794 | } |
cd6e9320 | 2795 | #define GEN_STX(name, stop, opc2, opc3, type) \ |
b7815375 BH |
2796 | GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) |
2797 | ||
2798 | #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ | |
2799 | GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) | |
79aceca5 | 2800 | |
0c8aacd4 AJ |
2801 | #define GEN_STS(name, stop, op, type) \ |
2802 | GEN_ST(name, stop, op | 0x20, type); \ | |
2803 | GEN_STU(name, stop, op | 0x21, type); \ | |
2804 | GEN_STUX(name, stop, 0x17, op | 0x01, type); \ | |
2805 | GEN_STX(name, stop, 0x17, op | 0x00, type) | |
79aceca5 FB |
2806 | |
2807 | /* stb stbu stbux stbx */ | |
0c8aacd4 | 2808 | GEN_STS(stb, st8, 0x06, PPC_INTEGER); |
79aceca5 | 2809 | /* sth sthu sthux sthx */ |
0c8aacd4 | 2810 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER); |
79aceca5 | 2811 | /* stw stwu stwux stwx */ |
0c8aacd4 | 2812 | GEN_STS(stw, st32, 0x04, PPC_INTEGER); |
50728199 RK |
2813 | |
2814 | #define GEN_STEPX(name, stop, opc2, opc3) \ | |
2815 | static void glue(gen_, name##epx)(DisasContext *ctx) \ | |
2816 | { \ | |
2817 | TCGv EA; \ | |
2818 | CHK_SV; \ | |
2819 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2820 | EA = tcg_temp_new(); \ | |
2821 | gen_addr_reg_index(ctx, EA); \ | |
2822 | tcg_gen_qemu_st_tl( \ | |
2823 | cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ | |
2824 | tcg_temp_free(EA); \ | |
2825 | } | |
2826 | ||
2827 | GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) | |
2828 | GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) | |
2829 | GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) | |
2830 | #if defined(TARGET_PPC64) | |
2831 | GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04) | |
2832 | #endif | |
2833 | ||
d9bce9d9 | 2834 | #if defined(TARGET_PPC64) |
2468f23d ND |
2835 | GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B); |
2836 | GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B); | |
2837 | GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) | |
b7815375 BH |
2838 | GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) |
2839 | GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) | |
2840 | GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) | |
99e300ef BS |
2841 | |
2842 | static void gen_std(DisasContext *ctx) | |
d9bce9d9 | 2843 | { |
be147d08 | 2844 | int rs; |
b61f2753 | 2845 | TCGv EA; |
be147d08 JM |
2846 | |
2847 | rs = rS(ctx->opcode); | |
84cab1e2 | 2848 | if ((ctx->opcode & 0x3) == 0x2) { /* stq */ |
84cab1e2 TM |
2849 | bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; |
2850 | bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; | |
f89ced5f | 2851 | TCGv hi, lo; |
84cab1e2 | 2852 | |
dfdd3e43 BH |
2853 | if (!(ctx->insns_flags & PPC_64BX)) { |
2854 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
2855 | } | |
2856 | ||
c47493f2 | 2857 | if (!legal_in_user_mode && ctx->pr) { |
9b2fadda | 2858 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2859 | return; |
2860 | } | |
84cab1e2 TM |
2861 | |
2862 | if (!le_is_supported && ctx->le_mode) { | |
65f2475f | 2863 | gen_align_no_le(ctx); |
d9bce9d9 JM |
2864 | return; |
2865 | } | |
84cab1e2 TM |
2866 | |
2867 | if (unlikely(rs & 1)) { | |
2868 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
be147d08 JM |
2869 | return; |
2870 | } | |
76db3ba4 | 2871 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2872 | EA = tcg_temp_new(); |
76db3ba4 | 2873 | gen_addr_imm_index(ctx, EA, 0x03); |
84cab1e2 | 2874 | |
f89ced5f RH |
2875 | /* Note that the low part is always in RS+1, even in LE mode. */ |
2876 | lo = cpu_gpr[rs + 1]; | |
2877 | hi = cpu_gpr[rs]; | |
2878 | ||
2879 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { | |
f34ec0f6 RH |
2880 | if (HAVE_ATOMIC128) { |
2881 | TCGv_i32 oi = tcg_temp_new_i32(); | |
2882 | if (ctx->le_mode) { | |
2883 | tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); | |
2884 | gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi); | |
2885 | } else { | |
2886 | tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); | |
2887 | gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi); | |
2888 | } | |
2889 | tcg_temp_free_i32(oi); | |
f89ced5f | 2890 | } else { |
f34ec0f6 RH |
2891 | /* Restart with exclusive lock. */ |
2892 | gen_helper_exit_atomic(cpu_env); | |
2893 | ctx->base.is_jmp = DISAS_NORETURN; | |
f89ced5f | 2894 | } |
f89ced5f RH |
2895 | } else if (ctx->le_mode) { |
2896 | tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ); | |
84cab1e2 | 2897 | gen_addr_add(ctx, EA, EA, 8); |
f89ced5f | 2898 | tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ); |
84cab1e2 | 2899 | } else { |
f89ced5f | 2900 | tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ); |
84cab1e2 | 2901 | gen_addr_add(ctx, EA, EA, 8); |
f89ced5f | 2902 | tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ); |
84cab1e2 | 2903 | } |
b61f2753 | 2904 | tcg_temp_free(EA); |
be147d08 | 2905 | } else { |
f89ced5f | 2906 | /* std / stdu */ |
be147d08 JM |
2907 | if (Rc(ctx->opcode)) { |
2908 | if (unlikely(rA(ctx->opcode) == 0)) { | |
e06fcd75 | 2909 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
be147d08 JM |
2910 | return; |
2911 | } | |
2912 | } | |
76db3ba4 | 2913 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2914 | EA = tcg_temp_new(); |
76db3ba4 | 2915 | gen_addr_imm_index(ctx, EA, 0x03); |
2468f23d | 2916 | gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); |
efe843d8 | 2917 | if (Rc(ctx->opcode)) { |
b61f2753 | 2918 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
efe843d8 | 2919 | } |
b61f2753 | 2920 | tcg_temp_free(EA); |
d9bce9d9 | 2921 | } |
d9bce9d9 JM |
2922 | } |
2923 | #endif | |
79aceca5 | 2924 | /*** Integer load and store with byte reverse ***/ |
e22c357b | 2925 | |
79aceca5 | 2926 | /* lhbrx */ |
0c8aacd4 | 2927 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); |
b61f2753 | 2928 | |
79aceca5 | 2929 | /* lwbrx */ |
0c8aacd4 | 2930 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); |
b61f2753 | 2931 | |
cd6e9320 TH |
2932 | #if defined(TARGET_PPC64) |
2933 | /* ldbrx */ | |
ff5f3981 | 2934 | GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); |
804108aa ND |
2935 | /* stdbrx */ |
2936 | GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); | |
cd6e9320 TH |
2937 | #endif /* TARGET_PPC64 */ |
2938 | ||
79aceca5 | 2939 | /* sthbrx */ |
0c8aacd4 | 2940 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); |
79aceca5 | 2941 | /* stwbrx */ |
0c8aacd4 | 2942 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); |
79aceca5 FB |
2943 | |
2944 | /*** Integer load and store multiple ***/ | |
99e300ef | 2945 | |
54623277 | 2946 | /* lmw */ |
99e300ef | 2947 | static void gen_lmw(DisasContext *ctx) |
79aceca5 | 2948 | { |
76db3ba4 AJ |
2949 | TCGv t0; |
2950 | TCGv_i32 t1; | |
5817355e BH |
2951 | |
2952 | if (ctx->le_mode) { | |
2953 | gen_align_no_le(ctx); | |
2954 | return; | |
2955 | } | |
76db3ba4 | 2956 | gen_set_access_type(ctx, ACCESS_INT); |
76db3ba4 AJ |
2957 | t0 = tcg_temp_new(); |
2958 | t1 = tcg_const_i32(rD(ctx->opcode)); | |
2959 | gen_addr_imm_index(ctx, t0, 0); | |
2f5a189c | 2960 | gen_helper_lmw(cpu_env, t0, t1); |
ff4a62cd AJ |
2961 | tcg_temp_free(t0); |
2962 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
2963 | } |
2964 | ||
2965 | /* stmw */ | |
99e300ef | 2966 | static void gen_stmw(DisasContext *ctx) |
79aceca5 | 2967 | { |
76db3ba4 AJ |
2968 | TCGv t0; |
2969 | TCGv_i32 t1; | |
5817355e BH |
2970 | |
2971 | if (ctx->le_mode) { | |
2972 | gen_align_no_le(ctx); | |
2973 | return; | |
2974 | } | |
76db3ba4 | 2975 | gen_set_access_type(ctx, ACCESS_INT); |
76db3ba4 AJ |
2976 | t0 = tcg_temp_new(); |
2977 | t1 = tcg_const_i32(rS(ctx->opcode)); | |
2978 | gen_addr_imm_index(ctx, t0, 0); | |
2f5a189c | 2979 | gen_helper_stmw(cpu_env, t0, t1); |
ff4a62cd AJ |
2980 | tcg_temp_free(t0); |
2981 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
2982 | } |
2983 | ||
2984 | /*** Integer load and store strings ***/ | |
54623277 | 2985 | |
79aceca5 | 2986 | /* lswi */ |
efe843d8 DG |
2987 | /* |
2988 | * PowerPC32 specification says we must generate an exception if rA is | |
2989 | * in the range of registers to be loaded. In an other hand, IBM says | |
2990 | * this is valid, but rA won't be loaded. For now, I'll follow the | |
2991 | * spec... | |
9a64fbe4 | 2992 | */ |
99e300ef | 2993 | static void gen_lswi(DisasContext *ctx) |
79aceca5 | 2994 | { |
dfbc799d AJ |
2995 | TCGv t0; |
2996 | TCGv_i32 t1, t2; | |
79aceca5 FB |
2997 | int nb = NB(ctx->opcode); |
2998 | int start = rD(ctx->opcode); | |
9a64fbe4 | 2999 | int ra = rA(ctx->opcode); |
79aceca5 FB |
3000 | int nr; |
3001 | ||
5817355e BH |
3002 | if (ctx->le_mode) { |
3003 | gen_align_no_le(ctx); | |
3004 | return; | |
3005 | } | |
efe843d8 | 3006 | if (nb == 0) { |
79aceca5 | 3007 | nb = 32; |
efe843d8 | 3008 | } |
f0704d78 | 3009 | nr = DIV_ROUND_UP(nb, 4); |
afbee712 | 3010 | if (unlikely(lsw_reg_in_range(start, nr, ra))) { |
e06fcd75 | 3011 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); |
9fddaa0c | 3012 | return; |
297d8e62 | 3013 | } |
76db3ba4 | 3014 | gen_set_access_type(ctx, ACCESS_INT); |
dfbc799d | 3015 | t0 = tcg_temp_new(); |
76db3ba4 | 3016 | gen_addr_register(ctx, t0); |
dfbc799d AJ |
3017 | t1 = tcg_const_i32(nb); |
3018 | t2 = tcg_const_i32(start); | |
2f5a189c | 3019 | gen_helper_lsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
3020 | tcg_temp_free(t0); |
3021 | tcg_temp_free_i32(t1); | |
3022 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
3023 | } |
3024 | ||
3025 | /* lswx */ | |
99e300ef | 3026 | static void gen_lswx(DisasContext *ctx) |
79aceca5 | 3027 | { |
76db3ba4 AJ |
3028 | TCGv t0; |
3029 | TCGv_i32 t1, t2, t3; | |
5817355e BH |
3030 | |
3031 | if (ctx->le_mode) { | |
3032 | gen_align_no_le(ctx); | |
3033 | return; | |
3034 | } | |
76db3ba4 | 3035 | gen_set_access_type(ctx, ACCESS_INT); |
76db3ba4 AJ |
3036 | t0 = tcg_temp_new(); |
3037 | gen_addr_reg_index(ctx, t0); | |
3038 | t1 = tcg_const_i32(rD(ctx->opcode)); | |
3039 | t2 = tcg_const_i32(rA(ctx->opcode)); | |
3040 | t3 = tcg_const_i32(rB(ctx->opcode)); | |
2f5a189c | 3041 | gen_helper_lswx(cpu_env, t0, t1, t2, t3); |
dfbc799d AJ |
3042 | tcg_temp_free(t0); |
3043 | tcg_temp_free_i32(t1); | |
3044 | tcg_temp_free_i32(t2); | |
3045 | tcg_temp_free_i32(t3); | |
79aceca5 FB |
3046 | } |
3047 | ||
3048 | /* stswi */ | |
99e300ef | 3049 | static void gen_stswi(DisasContext *ctx) |
79aceca5 | 3050 | { |
76db3ba4 AJ |
3051 | TCGv t0; |
3052 | TCGv_i32 t1, t2; | |
4b3686fa | 3053 | int nb = NB(ctx->opcode); |
5817355e BH |
3054 | |
3055 | if (ctx->le_mode) { | |
3056 | gen_align_no_le(ctx); | |
3057 | return; | |
3058 | } | |
76db3ba4 | 3059 | gen_set_access_type(ctx, ACCESS_INT); |
76db3ba4 AJ |
3060 | t0 = tcg_temp_new(); |
3061 | gen_addr_register(ctx, t0); | |
efe843d8 | 3062 | if (nb == 0) { |
4b3686fa | 3063 | nb = 32; |
efe843d8 | 3064 | } |
dfbc799d | 3065 | t1 = tcg_const_i32(nb); |
76db3ba4 | 3066 | t2 = tcg_const_i32(rS(ctx->opcode)); |
2f5a189c | 3067 | gen_helper_stsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
3068 | tcg_temp_free(t0); |
3069 | tcg_temp_free_i32(t1); | |
3070 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
3071 | } |
3072 | ||
3073 | /* stswx */ | |
99e300ef | 3074 | static void gen_stswx(DisasContext *ctx) |
79aceca5 | 3075 | { |
76db3ba4 AJ |
3076 | TCGv t0; |
3077 | TCGv_i32 t1, t2; | |
5817355e BH |
3078 | |
3079 | if (ctx->le_mode) { | |
3080 | gen_align_no_le(ctx); | |
3081 | return; | |
3082 | } | |
76db3ba4 | 3083 | gen_set_access_type(ctx, ACCESS_INT); |
76db3ba4 AJ |
3084 | t0 = tcg_temp_new(); |
3085 | gen_addr_reg_index(ctx, t0); | |
3086 | t1 = tcg_temp_new_i32(); | |
dfbc799d AJ |
3087 | tcg_gen_trunc_tl_i32(t1, cpu_xer); |
3088 | tcg_gen_andi_i32(t1, t1, 0x7F); | |
76db3ba4 | 3089 | t2 = tcg_const_i32(rS(ctx->opcode)); |
2f5a189c | 3090 | gen_helper_stsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
3091 | tcg_temp_free(t0); |
3092 | tcg_temp_free_i32(t1); | |
3093 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
3094 | } |
3095 | ||
3096 | /*** Memory synchronisation ***/ | |
3097 | /* eieio */ | |
99e300ef | 3098 | static void gen_eieio(DisasContext *ctx) |
79aceca5 | 3099 | { |
c8fd8373 CLG |
3100 | TCGBar bar = TCG_MO_LD_ST; |
3101 | ||
3102 | /* | |
3103 | * POWER9 has a eieio instruction variant using bit 6 as a hint to | |
3104 | * tell the CPU it is a store-forwarding barrier. | |
3105 | */ | |
3106 | if (ctx->opcode & 0x2000000) { | |
3107 | /* | |
3108 | * ISA says that "Reserved fields in instructions are ignored | |
3109 | * by the processor". So ignore the bit 6 on non-POWER9 CPU but | |
3110 | * as this is not an instruction software should be using, | |
3111 | * complain to the user. | |
3112 | */ | |
3113 | if (!(ctx->insns_flags2 & PPC2_ISA300)) { | |
3114 | qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" | |
3115 | TARGET_FMT_lx "\n", ctx->base.pc_next - 4); | |
3116 | } else { | |
3117 | bar = TCG_MO_ST_LD; | |
3118 | } | |
3119 | } | |
3120 | ||
3121 | tcg_gen_mb(bar | TCG_BAR_SC); | |
79aceca5 FB |
3122 | } |
3123 | ||
c5a8d8f3 | 3124 | #if !defined(CONFIG_USER_ONLY) |
e3cffe6f | 3125 | static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) |
cd0c6f47 | 3126 | { |
c5a8d8f3 BH |
3127 | TCGv_i32 t; |
3128 | TCGLabel *l; | |
cd0c6f47 | 3129 | |
c5a8d8f3 BH |
3130 | if (!ctx->lazy_tlb_flush) { |
3131 | return; | |
3132 | } | |
3133 | l = gen_new_label(); | |
3134 | t = tcg_temp_new_i32(); | |
cd0c6f47 BH |
3135 | tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); |
3136 | tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); | |
e3cffe6f ND |
3137 | if (global) { |
3138 | gen_helper_check_tlb_flush_global(cpu_env); | |
3139 | } else { | |
3140 | gen_helper_check_tlb_flush_local(cpu_env); | |
3141 | } | |
cd0c6f47 BH |
3142 | gen_set_label(l); |
3143 | tcg_temp_free_i32(t); | |
3144 | } | |
3145 | #else | |
e3cffe6f | 3146 | static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } |
cd0c6f47 BH |
3147 | #endif |
3148 | ||
79aceca5 | 3149 | /* isync */ |
99e300ef | 3150 | static void gen_isync(DisasContext *ctx) |
79aceca5 | 3151 | { |
cd0c6f47 BH |
3152 | /* |
3153 | * We need to check for a pending TLB flush. This can only happen in | |
3154 | * kernel mode however so check MSR_PR | |
3155 | */ | |
3156 | if (!ctx->pr) { | |
e3cffe6f | 3157 | gen_check_tlb_flush(ctx, false); |
cd0c6f47 | 3158 | } |
4771df23 | 3159 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); |
e06fcd75 | 3160 | gen_stop_exception(ctx); |
79aceca5 FB |
3161 | } |
3162 | ||
48793c95 ND |
3163 | #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) |
3164 | ||
14776ab5 | 3165 | static void gen_load_locked(DisasContext *ctx, MemOp memop) |
2a4e6c1b RH |
3166 | { |
3167 | TCGv gpr = cpu_gpr[rD(ctx->opcode)]; | |
3168 | TCGv t0 = tcg_temp_new(); | |
3169 | ||
3170 | gen_set_access_type(ctx, ACCESS_RES); | |
3171 | gen_addr_reg_index(ctx, t0); | |
3172 | tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); | |
3173 | tcg_gen_mov_tl(cpu_reserve, t0); | |
3174 | tcg_gen_mov_tl(cpu_reserve_val, gpr); | |
3175 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | |
3176 | tcg_temp_free(t0); | |
3177 | } | |
3178 | ||
3179 | #define LARX(name, memop) \ | |
3180 | static void gen_##name(DisasContext *ctx) \ | |
3181 | { \ | |
3182 | gen_load_locked(ctx, memop); \ | |
79aceca5 FB |
3183 | } |
3184 | ||
5c77a786 | 3185 | /* lwarx */ |
48793c95 ND |
3186 | LARX(lbarx, DEF_MEMOP(MO_UB)) |
3187 | LARX(lharx, DEF_MEMOP(MO_UW)) | |
3188 | LARX(lwarx, DEF_MEMOP(MO_UL)) | |
5c77a786 | 3189 | |
14776ab5 | 3190 | static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, |
20923c1d RH |
3191 | TCGv EA, TCGCond cond, int addend) |
3192 | { | |
3193 | TCGv t = tcg_temp_new(); | |
3194 | TCGv t2 = tcg_temp_new(); | |
3195 | TCGv u = tcg_temp_new(); | |
3196 | ||
3197 | tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); | |
3198 | tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); | |
3199 | tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); | |
3200 | tcg_gen_addi_tl(u, t, addend); | |
3201 | ||
3202 | /* E.g. for fetch and increment bounded... */ | |
3203 | /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ | |
3204 | tcg_gen_movcond_tl(cond, u, t, t2, u, t); | |
3205 | tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); | |
3206 | ||
3207 | /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ | |
3208 | tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); | |
3209 | tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); | |
3210 | ||
3211 | tcg_temp_free(t); | |
3212 | tcg_temp_free(t2); | |
3213 | tcg_temp_free(u); | |
3214 | } | |
3215 | ||
14776ab5 | 3216 | static void gen_ld_atomic(DisasContext *ctx, MemOp memop) |
20ba8504 RH |
3217 | { |
3218 | uint32_t gpr_FC = FC(ctx->opcode); | |
3219 | TCGv EA = tcg_temp_new(); | |
20923c1d RH |
3220 | int rt = rD(ctx->opcode); |
3221 | bool need_serial; | |
20ba8504 RH |
3222 | TCGv src, dst; |
3223 | ||
3224 | gen_addr_register(ctx, EA); | |
20923c1d RH |
3225 | dst = cpu_gpr[rt]; |
3226 | src = cpu_gpr[(rt + 1) & 31]; | |
20ba8504 | 3227 | |
20923c1d | 3228 | need_serial = false; |
20ba8504 RH |
3229 | memop |= MO_ALIGN; |
3230 | switch (gpr_FC) { | |
3231 | case 0: /* Fetch and add */ | |
3232 | tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); | |
3233 | break; | |
3234 | case 1: /* Fetch and xor */ | |
3235 | tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); | |
3236 | break; | |
3237 | case 2: /* Fetch and or */ | |
3238 | tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); | |
3239 | break; | |
3240 | case 3: /* Fetch and 'and' */ | |
3241 | tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); | |
3242 | break; | |
20ba8504 | 3243 | case 4: /* Fetch and max unsigned */ |
b8ce0f86 RH |
3244 | tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); |
3245 | break; | |
20ba8504 | 3246 | case 5: /* Fetch and max signed */ |
b8ce0f86 RH |
3247 | tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); |
3248 | break; | |
20ba8504 | 3249 | case 6: /* Fetch and min unsigned */ |
b8ce0f86 RH |
3250 | tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); |
3251 | break; | |
20ba8504 | 3252 | case 7: /* Fetch and min signed */ |
b8ce0f86 RH |
3253 | tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); |
3254 | break; | |
3255 | case 8: /* Swap */ | |
3256 | tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); | |
3257 | break; | |
20923c1d RH |
3258 | |
3259 | case 16: /* Compare and swap not equal */ | |
3260 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { | |
3261 | need_serial = true; | |
3262 | } else { | |
3263 | TCGv t0 = tcg_temp_new(); | |
3264 | TCGv t1 = tcg_temp_new(); | |
3265 | ||
3266 | tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); | |
3267 | if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { | |
3268 | tcg_gen_mov_tl(t1, src); | |
3269 | } else { | |
3270 | tcg_gen_ext32u_tl(t1, src); | |
3271 | } | |
3272 | tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, | |
3273 | cpu_gpr[(rt + 2) & 31], t0); | |
3274 | tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); | |
3275 | tcg_gen_mov_tl(dst, t0); | |
3276 | ||
3277 | tcg_temp_free(t0); | |
3278 | tcg_temp_free(t1); | |
3279 | } | |
3280 | break; | |
3281 | ||
20ba8504 | 3282 | case 24: /* Fetch and increment bounded */ |
20923c1d RH |
3283 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { |
3284 | need_serial = true; | |
3285 | } else { | |
3286 | gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); | |
3287 | } | |
3288 | break; | |
20ba8504 | 3289 | case 25: /* Fetch and increment equal */ |
20923c1d RH |
3290 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { |
3291 | need_serial = true; | |
3292 | } else { | |
3293 | gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); | |
3294 | } | |
3295 | break; | |
20ba8504 | 3296 | case 28: /* Fetch and decrement bounded */ |
20923c1d RH |
3297 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { |
3298 | need_serial = true; | |
3299 | } else { | |
3300 | gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); | |
3301 | } | |
20ba8504 | 3302 | break; |
20923c1d | 3303 | |
20ba8504 RH |
3304 | default: |
3305 | /* invoke data storage error handler */ | |
3306 | gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); | |
3307 | } | |
3308 | tcg_temp_free(EA); | |
20923c1d RH |
3309 | |
3310 | if (need_serial) { | |
3311 | /* Restart with exclusive lock. */ | |
3312 | gen_helper_exit_atomic(cpu_env); | |
3313 | ctx->base.is_jmp = DISAS_NORETURN; | |
3314 | } | |
20ba8504 RH |
3315 | } |
3316 | ||
3317 | static void gen_lwat(DisasContext *ctx) | |
3318 | { | |
3319 | gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); | |
3320 | } | |
3321 | ||
3322 | #ifdef TARGET_PPC64 | |
3323 | static void gen_ldat(DisasContext *ctx) | |
3324 | { | |
3325 | gen_ld_atomic(ctx, DEF_MEMOP(MO_Q)); | |
3326 | } | |
a68a6146 B |
3327 | #endif |
3328 | ||
14776ab5 | 3329 | static void gen_st_atomic(DisasContext *ctx, MemOp memop) |
9deb041c RH |
3330 | { |
3331 | uint32_t gpr_FC = FC(ctx->opcode); | |
3332 | TCGv EA = tcg_temp_new(); | |
3333 | TCGv src, discard; | |
3334 | ||
3335 | gen_addr_register(ctx, EA); | |
3336 | src = cpu_gpr[rD(ctx->opcode)]; | |
3337 | discard = tcg_temp_new(); | |
3338 | ||
3339 | memop |= MO_ALIGN; | |
3340 | switch (gpr_FC) { | |
3341 | case 0: /* add and Store */ | |
3342 | tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); | |
3343 | break; | |
3344 | case 1: /* xor and Store */ | |
3345 | tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); | |
3346 | break; | |
3347 | case 2: /* Or and Store */ | |
3348 | tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); | |
3349 | break; | |
3350 | case 3: /* 'and' and Store */ | |
3351 | tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); | |
3352 | break; | |
3353 | case 4: /* Store max unsigned */ | |
b8ce0f86 RH |
3354 | tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); |
3355 | break; | |
9deb041c | 3356 | case 5: /* Store max signed */ |
b8ce0f86 RH |
3357 | tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); |
3358 | break; | |
9deb041c | 3359 | case 6: /* Store min unsigned */ |
b8ce0f86 RH |
3360 | tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); |
3361 | break; | |
9deb041c | 3362 | case 7: /* Store min signed */ |
b8ce0f86 RH |
3363 | tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); |
3364 | break; | |
9deb041c | 3365 | case 24: /* Store twin */ |
7fbc2b20 RH |
3366 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { |
3367 | /* Restart with exclusive lock. */ | |
3368 | gen_helper_exit_atomic(cpu_env); | |
3369 | ctx->base.is_jmp = DISAS_NORETURN; | |
3370 | } else { | |
3371 | TCGv t = tcg_temp_new(); | |
3372 | TCGv t2 = tcg_temp_new(); | |
3373 | TCGv s = tcg_temp_new(); | |
3374 | TCGv s2 = tcg_temp_new(); | |
3375 | TCGv ea_plus_s = tcg_temp_new(); | |
3376 | ||
3377 | tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); | |
3378 | tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); | |
3379 | tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); | |
3380 | tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); | |
3381 | tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); | |
3382 | tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); | |
3383 | tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); | |
3384 | ||
3385 | tcg_temp_free(ea_plus_s); | |
3386 | tcg_temp_free(s2); | |
3387 | tcg_temp_free(s); | |
3388 | tcg_temp_free(t2); | |
3389 | tcg_temp_free(t); | |
3390 | } | |
9deb041c RH |
3391 | break; |
3392 | default: | |
3393 | /* invoke data storage error handler */ | |
3394 | gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); | |
3395 | } | |
3396 | tcg_temp_free(discard); | |
3397 | tcg_temp_free(EA); | |
3398 | } | |
3399 | ||
3400 | static void gen_stwat(DisasContext *ctx) | |
3401 | { | |
3402 | gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); | |
3403 | } | |
3404 | ||
3405 | #ifdef TARGET_PPC64 | |
3406 | static void gen_stdat(DisasContext *ctx) | |
3407 | { | |
3408 | gen_st_atomic(ctx, DEF_MEMOP(MO_Q)); | |
3409 | } | |
a3401188 B |
3410 | #endif |
3411 | ||
14776ab5 | 3412 | static void gen_conditional_store(DisasContext *ctx, MemOp memop) |
587c51f7 | 3413 | { |
253ce7b2 ND |
3414 | TCGLabel *l1 = gen_new_label(); |
3415 | TCGLabel *l2 = gen_new_label(); | |
d8b86898 RH |
3416 | TCGv t0 = tcg_temp_new(); |
3417 | int reg = rS(ctx->opcode); | |
4425265b | 3418 | |
d8b86898 RH |
3419 | gen_set_access_type(ctx, ACCESS_RES); |
3420 | gen_addr_reg_index(ctx, t0); | |
3421 | tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); | |
3422 | tcg_temp_free(t0); | |
253ce7b2 ND |
3423 | |
3424 | t0 = tcg_temp_new(); | |
3425 | tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, | |
3426 | cpu_gpr[reg], ctx->mem_idx, | |
3427 | DEF_MEMOP(memop) | MO_ALIGN); | |
3428 | tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); | |
3429 | tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); | |
3430 | tcg_gen_or_tl(t0, t0, cpu_so); | |
3431 | tcg_gen_trunc_tl_i32(cpu_crf[0], t0); | |
3432 | tcg_temp_free(t0); | |
3433 | tcg_gen_br(l2); | |
3434 | ||
587c51f7 | 3435 | gen_set_label(l1); |
4771df23 | 3436 | |
efe843d8 DG |
3437 | /* |
3438 | * Address mismatch implies failure. But we still need to provide | |
3439 | * the memory barrier semantics of the instruction. | |
3440 | */ | |
4771df23 | 3441 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); |
253ce7b2 ND |
3442 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
3443 | ||
3444 | gen_set_label(l2); | |
587c51f7 TM |
3445 | tcg_gen_movi_tl(cpu_reserve, -1); |
3446 | } | |
587c51f7 | 3447 | |
d8b86898 RH |
3448 | #define STCX(name, memop) \ |
3449 | static void gen_##name(DisasContext *ctx) \ | |
3450 | { \ | |
3451 | gen_conditional_store(ctx, memop); \ | |
2391b357 ND |
3452 | } |
3453 | ||
3454 | STCX(stbcx_, DEF_MEMOP(MO_UB)) | |
3455 | STCX(sthcx_, DEF_MEMOP(MO_UW)) | |
3456 | STCX(stwcx_, DEF_MEMOP(MO_UL)) | |
587c51f7 | 3457 | |
426613db | 3458 | #if defined(TARGET_PPC64) |
426613db | 3459 | /* ldarx */ |
48793c95 | 3460 | LARX(ldarx, DEF_MEMOP(MO_Q)) |
2391b357 ND |
3461 | /* stdcx. */ |
3462 | STCX(stdcx_, DEF_MEMOP(MO_Q)) | |
426613db | 3463 | |
9c294d5a TM |
3464 | /* lqarx */ |
3465 | static void gen_lqarx(DisasContext *ctx) | |
3466 | { | |
9c294d5a | 3467 | int rd = rD(ctx->opcode); |
94bf2658 | 3468 | TCGv EA, hi, lo; |
9c294d5a TM |
3469 | |
3470 | if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || | |
3471 | (rd == rB(ctx->opcode)))) { | |
3472 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
3473 | return; | |
3474 | } | |
3475 | ||
3476 | gen_set_access_type(ctx, ACCESS_RES); | |
94bf2658 | 3477 | EA = tcg_temp_new(); |
9c294d5a | 3478 | gen_addr_reg_index(ctx, EA); |
94bf2658 RH |
3479 | |
3480 | /* Note that the low part is always in RD+1, even in LE mode. */ | |
3481 | lo = cpu_gpr[rd + 1]; | |
3482 | hi = cpu_gpr[rd]; | |
3483 | ||
3484 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { | |
f34ec0f6 RH |
3485 | if (HAVE_ATOMIC128) { |
3486 | TCGv_i32 oi = tcg_temp_new_i32(); | |
3487 | if (ctx->le_mode) { | |
3488 | tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16, | |
3489 | ctx->mem_idx)); | |
3490 | gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); | |
3491 | } else { | |
3492 | tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16, | |
3493 | ctx->mem_idx)); | |
3494 | gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); | |
3495 | } | |
3496 | tcg_temp_free_i32(oi); | |
3497 | tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); | |
94bf2658 | 3498 | } else { |
f34ec0f6 RH |
3499 | /* Restart with exclusive lock. */ |
3500 | gen_helper_exit_atomic(cpu_env); | |
3501 | ctx->base.is_jmp = DISAS_NORETURN; | |
3502 | tcg_temp_free(EA); | |
3503 | return; | |
94bf2658 | 3504 | } |
94bf2658 RH |
3505 | } else if (ctx->le_mode) { |
3506 | tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16); | |
3507 | tcg_gen_mov_tl(cpu_reserve, EA); | |
3508 | gen_addr_add(ctx, EA, EA, 8); | |
3509 | tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); | |
9c294d5a | 3510 | } else { |
94bf2658 RH |
3511 | tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16); |
3512 | tcg_gen_mov_tl(cpu_reserve, EA); | |
3513 | gen_addr_add(ctx, EA, EA, 8); | |
3514 | tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); | |
9c294d5a | 3515 | } |
9c294d5a | 3516 | tcg_temp_free(EA); |
94bf2658 RH |
3517 | |
3518 | tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); | |
3519 | tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); | |
9c294d5a TM |
3520 | } |
3521 | ||
aa2008af ND |
3522 | /* stqcx. */ |
3523 | static void gen_stqcx_(DisasContext *ctx) | |
3524 | { | |
4a9b3c5d RH |
3525 | int rs = rS(ctx->opcode); |
3526 | TCGv EA, hi, lo; | |
aa2008af | 3527 | |
4a9b3c5d | 3528 | if (unlikely(rs & 1)) { |
aa2008af ND |
3529 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
3530 | return; | |
3531 | } | |
4a9b3c5d | 3532 | |
aa2008af | 3533 | gen_set_access_type(ctx, ACCESS_RES); |
4a9b3c5d | 3534 | EA = tcg_temp_new(); |
aa2008af | 3535 | gen_addr_reg_index(ctx, EA); |
aa2008af | 3536 | |
4a9b3c5d RH |
3537 | /* Note that the low part is always in RS+1, even in LE mode. */ |
3538 | lo = cpu_gpr[rs + 1]; | |
3539 | hi = cpu_gpr[rs]; | |
aa2008af | 3540 | |
4a9b3c5d | 3541 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { |
f34ec0f6 RH |
3542 | if (HAVE_CMPXCHG128) { |
3543 | TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16); | |
3544 | if (ctx->le_mode) { | |
3545 | gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, | |
3546 | EA, lo, hi, oi); | |
3547 | } else { | |
3548 | gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env, | |
3549 | EA, lo, hi, oi); | |
3550 | } | |
3551 | tcg_temp_free_i32(oi); | |
4a9b3c5d | 3552 | } else { |
f34ec0f6 RH |
3553 | /* Restart with exclusive lock. */ |
3554 | gen_helper_exit_atomic(cpu_env); | |
3555 | ctx->base.is_jmp = DISAS_NORETURN; | |
4a9b3c5d | 3556 | } |
4a9b3c5d | 3557 | tcg_temp_free(EA); |
aa2008af | 3558 | } else { |
4a9b3c5d RH |
3559 | TCGLabel *lab_fail = gen_new_label(); |
3560 | TCGLabel *lab_over = gen_new_label(); | |
3561 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
3562 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
aa2008af | 3563 | |
4a9b3c5d RH |
3564 | tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); |
3565 | tcg_temp_free(EA); | |
aa2008af | 3566 | |
4a9b3c5d RH |
3567 | gen_qemu_ld64_i64(ctx, t0, cpu_reserve); |
3568 | tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode | |
3569 | ? offsetof(CPUPPCState, reserve_val2) | |
3570 | : offsetof(CPUPPCState, reserve_val))); | |
3571 | tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); | |
3572 | ||
3573 | tcg_gen_addi_i64(t0, cpu_reserve, 8); | |
3574 | gen_qemu_ld64_i64(ctx, t0, t0); | |
3575 | tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode | |
3576 | ? offsetof(CPUPPCState, reserve_val) | |
3577 | : offsetof(CPUPPCState, reserve_val2))); | |
3578 | tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); | |
3579 | ||
3580 | /* Success */ | |
3581 | gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve); | |
3582 | tcg_gen_addi_i64(t0, cpu_reserve, 8); | |
3583 | gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0); | |
3584 | ||
3585 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); | |
3586 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); | |
3587 | tcg_gen_br(lab_over); | |
3588 | ||
3589 | gen_set_label(lab_fail); | |
3590 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); | |
3591 | ||
3592 | gen_set_label(lab_over); | |
3593 | tcg_gen_movi_tl(cpu_reserve, -1); | |
3594 | tcg_temp_free_i64(t0); | |
3595 | tcg_temp_free_i64(t1); | |
3596 | } | |
3597 | } | |
426613db JM |
3598 | #endif /* defined(TARGET_PPC64) */ |
3599 | ||
79aceca5 | 3600 | /* sync */ |
99e300ef | 3601 | static void gen_sync(DisasContext *ctx) |
79aceca5 | 3602 | { |
cd0c6f47 BH |
3603 | uint32_t l = (ctx->opcode >> 21) & 3; |
3604 | ||
3605 | /* | |
c5a8d8f3 BH |
3606 | * We may need to check for a pending TLB flush. |
3607 | * | |
3608 | * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. | |
3609 | * | |
3610 | * Additionally, this can only happen in kernel mode however so | |
3611 | * check MSR_PR as well. | |
cd0c6f47 | 3612 | */ |
c5a8d8f3 | 3613 | if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { |
e3cffe6f | 3614 | gen_check_tlb_flush(ctx, true); |
cd0c6f47 | 3615 | } |
4771df23 | 3616 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); |
79aceca5 FB |
3617 | } |
3618 | ||
0db1b20e | 3619 | /* wait */ |
99e300ef | 3620 | static void gen_wait(DisasContext *ctx) |
0db1b20e | 3621 | { |
35b5066e | 3622 | TCGv_i32 t0 = tcg_const_i32(1); |
259186a7 AF |
3623 | tcg_gen_st_i32(t0, cpu_env, |
3624 | -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); | |
931ff272 | 3625 | tcg_temp_free_i32(t0); |
0db1b20e | 3626 | /* Stop translation, as the CPU is supposed to sleep from now */ |
b6bac4bc | 3627 | gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); |
0db1b20e JM |
3628 | } |
3629 | ||
7778a575 BH |
3630 | #if defined(TARGET_PPC64) |
3631 | static void gen_doze(DisasContext *ctx) | |
3632 | { | |
3633 | #if defined(CONFIG_USER_ONLY) | |
3634 | GEN_PRIV; | |
3635 | #else | |
3636 | TCGv_i32 t; | |
3637 | ||
3638 | CHK_HV; | |
3639 | t = tcg_const_i32(PPC_PM_DOZE); | |
3640 | gen_helper_pminsn(cpu_env, t); | |
3641 | tcg_temp_free_i32(t); | |
154c69f2 BH |
3642 | /* Stop translation, as the CPU is supposed to sleep from now */ |
3643 | gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); | |
7778a575 BH |
3644 | #endif /* defined(CONFIG_USER_ONLY) */ |
3645 | } | |
3646 | ||
3647 | static void gen_nap(DisasContext *ctx) | |
3648 | { | |
3649 | #if defined(CONFIG_USER_ONLY) | |
3650 | GEN_PRIV; | |
3651 | #else | |
3652 | TCGv_i32 t; | |
3653 | ||
3654 | CHK_HV; | |
3655 | t = tcg_const_i32(PPC_PM_NAP); | |
3656 | gen_helper_pminsn(cpu_env, t); | |
3657 | tcg_temp_free_i32(t); | |
154c69f2 BH |
3658 | /* Stop translation, as the CPU is supposed to sleep from now */ |
3659 | gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); | |
7778a575 BH |
3660 | #endif /* defined(CONFIG_USER_ONLY) */ |
3661 | } | |
3662 | ||
cdee0e72 ND |
3663 | static void gen_stop(DisasContext *ctx) |
3664 | { | |
21c0d66a BH |
3665 | #if defined(CONFIG_USER_ONLY) |
3666 | GEN_PRIV; | |
3667 | #else | |
3668 | TCGv_i32 t; | |
3669 | ||
3670 | CHK_HV; | |
3671 | t = tcg_const_i32(PPC_PM_STOP); | |
3672 | gen_helper_pminsn(cpu_env, t); | |
3673 | tcg_temp_free_i32(t); | |
3674 | /* Stop translation, as the CPU is supposed to sleep from now */ | |
3675 | gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); | |
3676 | #endif /* defined(CONFIG_USER_ONLY) */ | |
cdee0e72 ND |
3677 | } |
3678 | ||
7778a575 BH |
3679 | static void gen_sleep(DisasContext *ctx) |
3680 | { | |
3681 | #if defined(CONFIG_USER_ONLY) | |
3682 | GEN_PRIV; | |
3683 | #else | |
3684 | TCGv_i32 t; | |
3685 | ||
3686 | CHK_HV; | |
3687 | t = tcg_const_i32(PPC_PM_SLEEP); | |
3688 | gen_helper_pminsn(cpu_env, t); | |
3689 | tcg_temp_free_i32(t); | |
154c69f2 BH |
3690 | /* Stop translation, as the CPU is supposed to sleep from now */ |
3691 | gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); | |
7778a575 BH |
3692 | #endif /* defined(CONFIG_USER_ONLY) */ |
3693 | } | |
3694 | ||
3695 | static void gen_rvwinkle(DisasContext *ctx) | |
3696 | { | |
3697 | #if defined(CONFIG_USER_ONLY) | |
3698 | GEN_PRIV; | |
3699 | #else | |
3700 | TCGv_i32 t; | |
3701 | ||
3702 | CHK_HV; | |
3703 | t = tcg_const_i32(PPC_PM_RVWINKLE); | |
3704 | gen_helper_pminsn(cpu_env, t); | |
3705 | tcg_temp_free_i32(t); | |
154c69f2 BH |
3706 | /* Stop translation, as the CPU is supposed to sleep from now */ |
3707 | gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); | |
7778a575 BH |
3708 | #endif /* defined(CONFIG_USER_ONLY) */ |
3709 | } | |
3710 | #endif /* #if defined(TARGET_PPC64) */ | |
3711 | ||
697ab892 DG |
3712 | static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) |
3713 | { | |
3714 | #if defined(TARGET_PPC64) | |
efe843d8 | 3715 | if (ctx->has_cfar) { |
697ab892 | 3716 | tcg_gen_movi_tl(cpu_cfar, nip); |
efe843d8 | 3717 | } |
697ab892 DG |
3718 | #endif |
3719 | } | |
3720 | ||
90aa39a1 SF |
3721 | static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) |
3722 | { | |
3723 | if (unlikely(ctx->singlestep_enabled)) { | |
3724 | return false; | |
3725 | } | |
3726 | ||
3727 | #ifndef CONFIG_USER_ONLY | |
b6bac4bc | 3728 | return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); |
90aa39a1 SF |
3729 | #else |
3730 | return true; | |
3731 | #endif | |
3732 | } | |
3733 | ||
0e3bf489 RK |
3734 | static void gen_lookup_and_goto_ptr(DisasContext *ctx) |
3735 | { | |
3736 | int sse = ctx->singlestep_enabled; | |
3737 | if (unlikely(sse)) { | |
3738 | if (sse & GDBSTUB_SINGLE_STEP) { | |
3739 | gen_debug_exception(ctx); | |
3740 | } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) { | |
e150ac89 RK |
3741 | uint32_t excp = gen_prep_dbgex(ctx); |
3742 | gen_exception(ctx, excp); | |
0e3bf489 RK |
3743 | } |
3744 | tcg_gen_exit_tb(NULL, 0); | |
3745 | } else { | |
3746 | tcg_gen_lookup_and_goto_ptr(); | |
3747 | } | |
3748 | } | |
3749 | ||
79aceca5 | 3750 | /*** Branch ***/ |
c4a2e3a9 | 3751 | static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) |
c1942362 | 3752 | { |
e0c8f9ce | 3753 | if (NARROW_MODE(ctx)) { |
a2ffb812 | 3754 | dest = (uint32_t) dest; |
e0c8f9ce | 3755 | } |
90aa39a1 | 3756 | if (use_goto_tb(ctx, dest)) { |
57fec1fe | 3757 | tcg_gen_goto_tb(n); |
a2ffb812 | 3758 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
07ea28b4 | 3759 | tcg_gen_exit_tb(ctx->base.tb, n); |
c1942362 | 3760 | } else { |
a2ffb812 | 3761 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
0e3bf489 | 3762 | gen_lookup_and_goto_ptr(ctx); |
c1942362 | 3763 | } |
c53be334 FB |
3764 | } |
3765 | ||
636aa200 | 3766 | static inline void gen_setlr(DisasContext *ctx, target_ulong nip) |
e1833e1f | 3767 | { |
e0c8f9ce RH |
3768 | if (NARROW_MODE(ctx)) { |
3769 | nip = (uint32_t)nip; | |
3770 | } | |
3771 | tcg_gen_movi_tl(cpu_lr, nip); | |
e1833e1f JM |
3772 | } |
3773 | ||
79aceca5 | 3774 | /* b ba bl bla */ |
99e300ef | 3775 | static void gen_b(DisasContext *ctx) |
79aceca5 | 3776 | { |
76a66253 | 3777 | target_ulong li, target; |
38a64f9d | 3778 | |
8cbcb4fa | 3779 | ctx->exception = POWERPC_EXCP_BRANCH; |
38a64f9d | 3780 | /* sign extend LI */ |
e0c8f9ce RH |
3781 | li = LI(ctx->opcode); |
3782 | li = (li ^ 0x02000000) - 0x02000000; | |
3783 | if (likely(AA(ctx->opcode) == 0)) { | |
b6bac4bc | 3784 | target = ctx->base.pc_next + li - 4; |
e0c8f9ce | 3785 | } else { |
9a64fbe4 | 3786 | target = li; |
e0c8f9ce RH |
3787 | } |
3788 | if (LK(ctx->opcode)) { | |
b6bac4bc | 3789 | gen_setlr(ctx, ctx->base.pc_next); |
e0c8f9ce | 3790 | } |
b6bac4bc | 3791 | gen_update_cfar(ctx, ctx->base.pc_next - 4); |
c1942362 | 3792 | gen_goto_tb(ctx, 0, target); |
79aceca5 FB |
3793 | } |
3794 | ||
e98a6e40 FB |
3795 | #define BCOND_IM 0 |
3796 | #define BCOND_LR 1 | |
3797 | #define BCOND_CTR 2 | |
52a4984d | 3798 | #define BCOND_TAR 3 |
e98a6e40 | 3799 | |
c4a2e3a9 | 3800 | static void gen_bcond(DisasContext *ctx, int type) |
d9bce9d9 | 3801 | { |
d9bce9d9 | 3802 | uint32_t bo = BO(ctx->opcode); |
42a268c2 | 3803 | TCGLabel *l1; |
a2ffb812 | 3804 | TCGv target; |
8cbcb4fa | 3805 | ctx->exception = POWERPC_EXCP_BRANCH; |
0e3bf489 | 3806 | |
52a4984d | 3807 | if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { |
a7812ae4 | 3808 | target = tcg_temp_local_new(); |
efe843d8 | 3809 | if (type == BCOND_CTR) { |
a2ffb812 | 3810 | tcg_gen_mov_tl(target, cpu_ctr); |
efe843d8 | 3811 | } else if (type == BCOND_TAR) { |
52a4984d | 3812 | gen_load_spr(target, SPR_TAR); |
efe843d8 | 3813 | } else { |
a2ffb812 | 3814 | tcg_gen_mov_tl(target, cpu_lr); |
efe843d8 | 3815 | } |
d2e9fd8f | 3816 | } else { |
f764718d | 3817 | target = NULL; |
e98a6e40 | 3818 | } |
efe843d8 | 3819 | if (LK(ctx->opcode)) { |
b6bac4bc | 3820 | gen_setlr(ctx, ctx->base.pc_next); |
efe843d8 | 3821 | } |
a2ffb812 AJ |
3822 | l1 = gen_new_label(); |
3823 | if ((bo & 0x4) == 0) { | |
3824 | /* Decrement and test CTR */ | |
a7812ae4 | 3825 | TCGv temp = tcg_temp_new(); |
fa200c95 GK |
3826 | |
3827 | if (type == BCOND_CTR) { | |
3828 | /* | |
3829 | * All ISAs up to v3 describe this form of bcctr as invalid but | |
3830 | * some processors, ie. 64-bit server processors compliant with | |
3831 | * arch 2.x, do implement a "test and decrement" logic instead, | |
15d68c5e GK |
3832 | * as described in their respective UMs. This logic involves CTR |
3833 | * to act as both the branch target and a counter, which makes | |
3834 | * it basically useless and thus never used in real code. | |
3835 | * | |
3836 | * This form was hence chosen to trigger extra micro-architectural | |
3837 | * side-effect on real HW needed for the Spectre v2 workaround. | |
3838 | * It is up to guests that implement such workaround, ie. linux, to | |
3839 | * use this form in a way it just triggers the side-effect without | |
3840 | * doing anything else harmful. | |
fa200c95 | 3841 | */ |
d0db7cad | 3842 | if (unlikely(!is_book3s_arch2x(ctx))) { |
fa200c95 GK |
3843 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
3844 | tcg_temp_free(temp); | |
3845 | tcg_temp_free(target); | |
3846 | return; | |
3847 | } | |
3848 | ||
3849 | if (NARROW_MODE(ctx)) { | |
3850 | tcg_gen_ext32u_tl(temp, cpu_ctr); | |
3851 | } else { | |
3852 | tcg_gen_mov_tl(temp, cpu_ctr); | |
3853 | } | |
3854 | if (bo & 0x2) { | |
3855 | tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); | |
3856 | } else { | |
3857 | tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); | |
3858 | } | |
3859 | tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); | |
a2ffb812 | 3860 | } else { |
fa200c95 GK |
3861 | tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); |
3862 | if (NARROW_MODE(ctx)) { | |
3863 | tcg_gen_ext32u_tl(temp, cpu_ctr); | |
3864 | } else { | |
3865 | tcg_gen_mov_tl(temp, cpu_ctr); | |
3866 | } | |
3867 | if (bo & 0x2) { | |
3868 | tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); | |
3869 | } else { | |
3870 | tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); | |
3871 | } | |
e98a6e40 | 3872 | } |
a7812ae4 | 3873 | tcg_temp_free(temp); |
a2ffb812 AJ |
3874 | } |
3875 | if ((bo & 0x10) == 0) { | |
3876 | /* Test CR */ | |
3877 | uint32_t bi = BI(ctx->opcode); | |
8f9fb7ac | 3878 | uint32_t mask = 0x08 >> (bi & 0x03); |
a7812ae4 | 3879 | TCGv_i32 temp = tcg_temp_new_i32(); |
a2ffb812 | 3880 | |
d9bce9d9 | 3881 | if (bo & 0x8) { |
a2ffb812 AJ |
3882 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
3883 | tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); | |
d9bce9d9 | 3884 | } else { |
a2ffb812 AJ |
3885 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
3886 | tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); | |
d9bce9d9 | 3887 | } |
a7812ae4 | 3888 | tcg_temp_free_i32(temp); |
d9bce9d9 | 3889 | } |
b6bac4bc | 3890 | gen_update_cfar(ctx, ctx->base.pc_next - 4); |
e98a6e40 | 3891 | if (type == BCOND_IM) { |
a2ffb812 AJ |
3892 | target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); |
3893 | if (likely(AA(ctx->opcode) == 0)) { | |
b6bac4bc | 3894 | gen_goto_tb(ctx, 0, ctx->base.pc_next + li - 4); |
a2ffb812 AJ |
3895 | } else { |
3896 | gen_goto_tb(ctx, 0, li); | |
3897 | } | |
e98a6e40 | 3898 | } else { |
e0c8f9ce | 3899 | if (NARROW_MODE(ctx)) { |
a2ffb812 | 3900 | tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); |
e0c8f9ce | 3901 | } else { |
a2ffb812 | 3902 | tcg_gen_andi_tl(cpu_nip, target, ~3); |
e0c8f9ce | 3903 | } |
0e3bf489 | 3904 | gen_lookup_and_goto_ptr(ctx); |
c80d1df5 AG |
3905 | tcg_temp_free(target); |
3906 | } | |
c4a2e3a9 | 3907 | if ((bo & 0x14) != 0x14) { |
0e3bf489 | 3908 | /* fallthrough case */ |
c4a2e3a9 | 3909 | gen_set_label(l1); |
b6bac4bc | 3910 | gen_goto_tb(ctx, 1, ctx->base.pc_next); |
c4a2e3a9 | 3911 | } |
e98a6e40 FB |
3912 | } |
3913 | ||
99e300ef | 3914 | static void gen_bc(DisasContext *ctx) |
3b46e624 | 3915 | { |
e98a6e40 FB |
3916 | gen_bcond(ctx, BCOND_IM); |
3917 | } | |
3918 | ||
99e300ef | 3919 | static void gen_bcctr(DisasContext *ctx) |
3b46e624 | 3920 | { |
e98a6e40 FB |
3921 | gen_bcond(ctx, BCOND_CTR); |
3922 | } | |
3923 | ||
99e300ef | 3924 | static void gen_bclr(DisasContext *ctx) |
3b46e624 | 3925 | { |
e98a6e40 FB |
3926 | gen_bcond(ctx, BCOND_LR); |
3927 | } | |
79aceca5 | 3928 | |
52a4984d TM |
3929 | static void gen_bctar(DisasContext *ctx) |
3930 | { | |
3931 | gen_bcond(ctx, BCOND_TAR); | |
3932 | } | |
3933 | ||
79aceca5 | 3934 | /*** Condition register logical ***/ |
e1571908 | 3935 | #define GEN_CRLOGIC(name, tcg_op, opc) \ |
efe843d8 | 3936 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 3937 | { \ |
fc0d441e JM |
3938 | uint8_t bitmask; \ |
3939 | int sh; \ | |
a7812ae4 | 3940 | TCGv_i32 t0, t1; \ |
fc0d441e | 3941 | sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ |
a7812ae4 | 3942 | t0 = tcg_temp_new_i32(); \ |
fc0d441e | 3943 | if (sh > 0) \ |
fea0c503 | 3944 | tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ |
fc0d441e | 3945 | else if (sh < 0) \ |
fea0c503 | 3946 | tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ |
e1571908 | 3947 | else \ |
fea0c503 | 3948 | tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ |
a7812ae4 | 3949 | t1 = tcg_temp_new_i32(); \ |
fc0d441e JM |
3950 | sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ |
3951 | if (sh > 0) \ | |
fea0c503 | 3952 | tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ |
fc0d441e | 3953 | else if (sh < 0) \ |
fea0c503 | 3954 | tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ |
e1571908 | 3955 | else \ |
fea0c503 AJ |
3956 | tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ |
3957 | tcg_op(t0, t0, t1); \ | |
8f9fb7ac | 3958 | bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ |
fea0c503 AJ |
3959 | tcg_gen_andi_i32(t0, t0, bitmask); \ |
3960 | tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ | |
3961 | tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ | |
a7812ae4 PB |
3962 | tcg_temp_free_i32(t0); \ |
3963 | tcg_temp_free_i32(t1); \ | |
79aceca5 FB |
3964 | } |
3965 | ||
3966 | /* crand */ | |
e1571908 | 3967 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); |
79aceca5 | 3968 | /* crandc */ |
e1571908 | 3969 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); |
79aceca5 | 3970 | /* creqv */ |
e1571908 | 3971 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); |
79aceca5 | 3972 | /* crnand */ |
e1571908 | 3973 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); |
79aceca5 | 3974 | /* crnor */ |
e1571908 | 3975 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); |
79aceca5 | 3976 | /* cror */ |
e1571908 | 3977 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); |
79aceca5 | 3978 | /* crorc */ |
e1571908 | 3979 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); |
79aceca5 | 3980 | /* crxor */ |
e1571908 | 3981 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); |
99e300ef | 3982 | |
54623277 | 3983 | /* mcrf */ |
99e300ef | 3984 | static void gen_mcrf(DisasContext *ctx) |
79aceca5 | 3985 | { |
47e4661c | 3986 | tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); |
79aceca5 FB |
3987 | } |
3988 | ||
3989 | /*** System linkage ***/ | |
99e300ef | 3990 | |
c47493f2 | 3991 | /* rfi (supervisor only) */ |
99e300ef | 3992 | static void gen_rfi(DisasContext *ctx) |
79aceca5 | 3993 | { |
9a64fbe4 | 3994 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 3995 | GEN_PRIV; |
9a64fbe4 | 3996 | #else |
efe843d8 DG |
3997 | /* |
3998 | * This instruction doesn't exist anymore on 64-bit server | |
6ca038c2 | 3999 | * processors compliant with arch 2.x |
a2e71b28 | 4000 | */ |
d0db7cad | 4001 | if (is_book3s_arch2x(ctx)) { |
6ca038c2 BH |
4002 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
4003 | return; | |
4004 | } | |
9a64fbe4 | 4005 | /* Restore CPU state */ |
9b2fadda | 4006 | CHK_SV; |
a59d628f MK |
4007 | if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { |
4008 | gen_io_start(); | |
4009 | } | |
b6bac4bc | 4010 | gen_update_cfar(ctx, ctx->base.pc_next - 4); |
e5f17ac6 | 4011 | gen_helper_rfi(cpu_env); |
e06fcd75 | 4012 | gen_sync_exception(ctx); |
9a64fbe4 | 4013 | #endif |
79aceca5 FB |
4014 | } |
4015 | ||
426613db | 4016 | #if defined(TARGET_PPC64) |
99e300ef | 4017 | static void gen_rfid(DisasContext *ctx) |
426613db JM |
4018 | { |
4019 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4020 | GEN_PRIV; |
426613db JM |
4021 | #else |
4022 | /* Restore CPU state */ | |
9b2fadda | 4023 | CHK_SV; |
a59d628f MK |
4024 | if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { |
4025 | gen_io_start(); | |
4026 | } | |
b6bac4bc | 4027 | gen_update_cfar(ctx, ctx->base.pc_next - 4); |
e5f17ac6 | 4028 | gen_helper_rfid(cpu_env); |
e06fcd75 | 4029 | gen_sync_exception(ctx); |
426613db JM |
4030 | #endif |
4031 | } | |
426613db | 4032 | |
3c89b8d6 NP |
4033 | #if !defined(CONFIG_USER_ONLY) |
4034 | static void gen_rfscv(DisasContext *ctx) | |
4035 | { | |
4036 | #if defined(CONFIG_USER_ONLY) | |
4037 | GEN_PRIV; | |
4038 | #else | |
4039 | /* Restore CPU state */ | |
4040 | CHK_SV; | |
4041 | if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { | |
4042 | gen_io_start(); | |
4043 | } | |
4044 | gen_update_cfar(ctx, ctx->base.pc_next - 4); | |
4045 | gen_helper_rfscv(cpu_env); | |
4046 | gen_sync_exception(ctx); | |
4047 | #endif | |
4048 | } | |
4049 | #endif | |
4050 | ||
99e300ef | 4051 | static void gen_hrfid(DisasContext *ctx) |
be147d08 JM |
4052 | { |
4053 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4054 | GEN_PRIV; |
be147d08 JM |
4055 | #else |
4056 | /* Restore CPU state */ | |
9b2fadda | 4057 | CHK_HV; |
e5f17ac6 | 4058 | gen_helper_hrfid(cpu_env); |
e06fcd75 | 4059 | gen_sync_exception(ctx); |
be147d08 JM |
4060 | #endif |
4061 | } | |
4062 | #endif | |
4063 | ||
79aceca5 | 4064 | /* sc */ |
417bf010 JM |
4065 | #if defined(CONFIG_USER_ONLY) |
4066 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER | |
4067 | #else | |
4068 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL | |
3c89b8d6 | 4069 | #define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED |
417bf010 | 4070 | #endif |
99e300ef | 4071 | static void gen_sc(DisasContext *ctx) |
79aceca5 | 4072 | { |
e1833e1f JM |
4073 | uint32_t lev; |
4074 | ||
4075 | lev = (ctx->opcode >> 5) & 0x7F; | |
e06fcd75 | 4076 | gen_exception_err(ctx, POWERPC_SYSCALL, lev); |
79aceca5 FB |
4077 | } |
4078 | ||
3c89b8d6 NP |
4079 | #if defined(TARGET_PPC64) |
4080 | #if !defined(CONFIG_USER_ONLY) | |
4081 | static void gen_scv(DisasContext *ctx) | |
4082 | { | |
f43520e5 | 4083 | uint32_t lev = (ctx->opcode >> 5) & 0x7F; |
3c89b8d6 | 4084 | |
f43520e5 RH |
4085 | /* Set the PC back to the faulting instruction. */ |
4086 | if (ctx->exception == POWERPC_EXCP_NONE) { | |
4087 | gen_update_nip(ctx, ctx->base.pc_next - 4); | |
3c89b8d6 | 4088 | } |
f43520e5 | 4089 | gen_helper_scv(cpu_env, tcg_constant_i32(lev)); |
3c89b8d6 | 4090 | |
f43520e5 RH |
4091 | /* This need not be exact, just not POWERPC_EXCP_NONE */ |
4092 | ctx->exception = POWERPC_SYSCALL_VECTORED; | |
3c89b8d6 NP |
4093 | } |
4094 | #endif | |
4095 | #endif | |
4096 | ||
79aceca5 | 4097 | /*** Trap ***/ |
99e300ef | 4098 | |
22b56ee5 BH |
4099 | /* Check for unconditional traps (always or never) */ |
4100 | static bool check_unconditional_trap(DisasContext *ctx) | |
4101 | { | |
4102 | /* Trap never */ | |
4103 | if (TO(ctx->opcode) == 0) { | |
4104 | return true; | |
4105 | } | |
4106 | /* Trap always */ | |
4107 | if (TO(ctx->opcode) == 31) { | |
4108 | gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); | |
4109 | return true; | |
4110 | } | |
4111 | return false; | |
4112 | } | |
4113 | ||
54623277 | 4114 | /* tw */ |
99e300ef | 4115 | static void gen_tw(DisasContext *ctx) |
79aceca5 | 4116 | { |
22b56ee5 BH |
4117 | TCGv_i32 t0; |
4118 | ||
4119 | if (check_unconditional_trap(ctx)) { | |
4120 | return; | |
4121 | } | |
4122 | t0 = tcg_const_i32(TO(ctx->opcode)); | |
e5f17ac6 BS |
4123 | gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
4124 | t0); | |
cab3bee2 | 4125 | tcg_temp_free_i32(t0); |
79aceca5 FB |
4126 | } |
4127 | ||
4128 | /* twi */ | |
99e300ef | 4129 | static void gen_twi(DisasContext *ctx) |
79aceca5 | 4130 | { |
22b56ee5 BH |
4131 | TCGv t0; |
4132 | TCGv_i32 t1; | |
4133 | ||
4134 | if (check_unconditional_trap(ctx)) { | |
4135 | return; | |
4136 | } | |
4137 | t0 = tcg_const_tl(SIMM(ctx->opcode)); | |
4138 | t1 = tcg_const_i32(TO(ctx->opcode)); | |
e5f17ac6 | 4139 | gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); |
cab3bee2 AJ |
4140 | tcg_temp_free(t0); |
4141 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
4142 | } |
4143 | ||
d9bce9d9 JM |
4144 | #if defined(TARGET_PPC64) |
4145 | /* td */ | |
99e300ef | 4146 | static void gen_td(DisasContext *ctx) |
d9bce9d9 | 4147 | { |
22b56ee5 BH |
4148 | TCGv_i32 t0; |
4149 | ||
4150 | if (check_unconditional_trap(ctx)) { | |
4151 | return; | |
4152 | } | |
4153 | t0 = tcg_const_i32(TO(ctx->opcode)); | |
e5f17ac6 BS |
4154 | gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
4155 | t0); | |
cab3bee2 | 4156 | tcg_temp_free_i32(t0); |
d9bce9d9 JM |
4157 | } |
4158 | ||
4159 | /* tdi */ | |
99e300ef | 4160 | static void gen_tdi(DisasContext *ctx) |
d9bce9d9 | 4161 | { |
22b56ee5 BH |
4162 | TCGv t0; |
4163 | TCGv_i32 t1; | |
4164 | ||
4165 | if (check_unconditional_trap(ctx)) { | |
4166 | return; | |
4167 | } | |
4168 | t0 = tcg_const_tl(SIMM(ctx->opcode)); | |
4169 | t1 = tcg_const_i32(TO(ctx->opcode)); | |
e5f17ac6 | 4170 | gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); |
cab3bee2 AJ |
4171 | tcg_temp_free(t0); |
4172 | tcg_temp_free_i32(t1); | |
d9bce9d9 JM |
4173 | } |
4174 | #endif | |
4175 | ||
79aceca5 | 4176 | /*** Processor control ***/ |
99e300ef | 4177 | |
54623277 | 4178 | /* mcrxr */ |
99e300ef | 4179 | static void gen_mcrxr(DisasContext *ctx) |
79aceca5 | 4180 | { |
da91a00f RH |
4181 | TCGv_i32 t0 = tcg_temp_new_i32(); |
4182 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
4183 | TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; | |
4184 | ||
4185 | tcg_gen_trunc_tl_i32(t0, cpu_so); | |
4186 | tcg_gen_trunc_tl_i32(t1, cpu_ov); | |
4187 | tcg_gen_trunc_tl_i32(dst, cpu_ca); | |
294d1292 SB |
4188 | tcg_gen_shli_i32(t0, t0, 3); |
4189 | tcg_gen_shli_i32(t1, t1, 2); | |
4190 | tcg_gen_shli_i32(dst, dst, 1); | |
da91a00f RH |
4191 | tcg_gen_or_i32(dst, dst, t0); |
4192 | tcg_gen_or_i32(dst, dst, t1); | |
4193 | tcg_temp_free_i32(t0); | |
4194 | tcg_temp_free_i32(t1); | |
4195 | ||
4196 | tcg_gen_movi_tl(cpu_so, 0); | |
4197 | tcg_gen_movi_tl(cpu_ov, 0); | |
4198 | tcg_gen_movi_tl(cpu_ca, 0); | |
79aceca5 FB |
4199 | } |
4200 | ||
b63d0434 ND |
4201 | #ifdef TARGET_PPC64 |
4202 | /* mcrxrx */ | |
4203 | static void gen_mcrxrx(DisasContext *ctx) | |
4204 | { | |
4205 | TCGv t0 = tcg_temp_new(); | |
4206 | TCGv t1 = tcg_temp_new(); | |
4207 | TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; | |
4208 | ||
4209 | /* copy OV and OV32 */ | |
4210 | tcg_gen_shli_tl(t0, cpu_ov, 1); | |
4211 | tcg_gen_or_tl(t0, t0, cpu_ov32); | |
4212 | tcg_gen_shli_tl(t0, t0, 2); | |
4213 | /* copy CA and CA32 */ | |
4214 | tcg_gen_shli_tl(t1, cpu_ca, 1); | |
4215 | tcg_gen_or_tl(t1, t1, cpu_ca32); | |
4216 | tcg_gen_or_tl(t0, t0, t1); | |
4217 | tcg_gen_trunc_tl_i32(dst, t0); | |
4218 | tcg_temp_free(t0); | |
4219 | tcg_temp_free(t1); | |
4220 | } | |
4221 | #endif | |
4222 | ||
0cfe11ea | 4223 | /* mfcr mfocrf */ |
99e300ef | 4224 | static void gen_mfcr(DisasContext *ctx) |
79aceca5 | 4225 | { |
76a66253 | 4226 | uint32_t crm, crn; |
3b46e624 | 4227 | |
76a66253 JM |
4228 | if (likely(ctx->opcode & 0x00100000)) { |
4229 | crm = CRM(ctx->opcode); | |
8dd640e4 | 4230 | if (likely(crm && ((crm & (crm - 1)) == 0))) { |
efe843d8 | 4231 | crn = ctz32(crm); |
e1571908 | 4232 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); |
0497d2f4 AJ |
4233 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], |
4234 | cpu_gpr[rD(ctx->opcode)], crn * 4); | |
76a66253 | 4235 | } |
d9bce9d9 | 4236 | } else { |
651721b2 AJ |
4237 | TCGv_i32 t0 = tcg_temp_new_i32(); |
4238 | tcg_gen_mov_i32(t0, cpu_crf[0]); | |
4239 | tcg_gen_shli_i32(t0, t0, 4); | |
4240 | tcg_gen_or_i32(t0, t0, cpu_crf[1]); | |
4241 | tcg_gen_shli_i32(t0, t0, 4); | |
4242 | tcg_gen_or_i32(t0, t0, cpu_crf[2]); | |
4243 | tcg_gen_shli_i32(t0, t0, 4); | |
4244 | tcg_gen_or_i32(t0, t0, cpu_crf[3]); | |
4245 | tcg_gen_shli_i32(t0, t0, 4); | |
4246 | tcg_gen_or_i32(t0, t0, cpu_crf[4]); | |
4247 | tcg_gen_shli_i32(t0, t0, 4); | |
4248 | tcg_gen_or_i32(t0, t0, cpu_crf[5]); | |
4249 | tcg_gen_shli_i32(t0, t0, 4); | |
4250 | tcg_gen_or_i32(t0, t0, cpu_crf[6]); | |
4251 | tcg_gen_shli_i32(t0, t0, 4); | |
4252 | tcg_gen_or_i32(t0, t0, cpu_crf[7]); | |
4253 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
4254 | tcg_temp_free_i32(t0); | |
d9bce9d9 | 4255 | } |
79aceca5 FB |
4256 | } |
4257 | ||
4258 | /* mfmsr */ | |
99e300ef | 4259 | static void gen_mfmsr(DisasContext *ctx) |
79aceca5 | 4260 | { |
9b2fadda | 4261 | CHK_SV; |
6527f6ea | 4262 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); |
79aceca5 FB |
4263 | } |
4264 | ||
69b058c8 | 4265 | static void spr_noaccess(DisasContext *ctx, int gprn, int sprn) |
3fc6c082 | 4266 | { |
7b13448f | 4267 | #if 0 |
3fc6c082 FB |
4268 | sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); |
4269 | printf("ERROR: try to access SPR %d !\n", sprn); | |
7b13448f | 4270 | #endif |
3fc6c082 FB |
4271 | } |
4272 | #define SPR_NOACCESS (&spr_noaccess) | |
3fc6c082 | 4273 | |
79aceca5 | 4274 | /* mfspr */ |
636aa200 | 4275 | static inline void gen_op_mfspr(DisasContext *ctx) |
79aceca5 | 4276 | { |
69b058c8 | 4277 | void (*read_cb)(DisasContext *ctx, int gprn, int sprn); |
79aceca5 FB |
4278 | uint32_t sprn = SPR(ctx->opcode); |
4279 | ||
eb94268e BH |
4280 | #if defined(CONFIG_USER_ONLY) |
4281 | read_cb = ctx->spr_cb[sprn].uea_read; | |
4282 | #else | |
4283 | if (ctx->pr) { | |
4284 | read_cb = ctx->spr_cb[sprn].uea_read; | |
4285 | } else if (ctx->hv) { | |
be147d08 | 4286 | read_cb = ctx->spr_cb[sprn].hea_read; |
eb94268e | 4287 | } else { |
3fc6c082 | 4288 | read_cb = ctx->spr_cb[sprn].oea_read; |
eb94268e | 4289 | } |
9a64fbe4 | 4290 | #endif |
76a66253 JM |
4291 | if (likely(read_cb != NULL)) { |
4292 | if (likely(read_cb != SPR_NOACCESS)) { | |
45d827d2 | 4293 | (*read_cb)(ctx, rD(ctx->opcode), sprn); |
3fc6c082 FB |
4294 | } else { |
4295 | /* Privilege exception */ | |
efe843d8 DG |
4296 | /* |
4297 | * This is a hack to avoid warnings when running Linux: | |
9fceefa7 JM |
4298 | * this OS breaks the PowerPC virtualisation model, |
4299 | * allowing userland application to read the PVR | |
4300 | */ | |
4301 | if (sprn != SPR_PVR) { | |
31085338 TH |
4302 | qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " |
4303 | "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, | |
4304 | ctx->base.pc_next - 4); | |
f24e5695 | 4305 | } |
9b2fadda | 4306 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); |
79aceca5 | 4307 | } |
3fc6c082 | 4308 | } else { |
9b2fadda BH |
4309 | /* ISA 2.07 defines these as no-ops */ |
4310 | if ((ctx->insns_flags2 & PPC2_ISA207S) && | |
4311 | (sprn >= 808 && sprn <= 811)) { | |
4312 | /* This is a nop */ | |
4313 | return; | |
4314 | } | |
3fc6c082 | 4315 | /* Not defined */ |
31085338 TH |
4316 | qemu_log_mask(LOG_GUEST_ERROR, |
4317 | "Trying to read invalid spr %d (0x%03x) at " | |
4318 | TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4); | |
9b2fadda | 4319 | |
efe843d8 DG |
4320 | /* |
4321 | * The behaviour depends on MSR:PR and SPR# bit 0x10, it can | |
4322 | * generate a priv, a hv emu or a no-op | |
9b2fadda BH |
4323 | */ |
4324 | if (sprn & 0x10) { | |
4325 | if (ctx->pr) { | |
4326 | gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); | |
4327 | } | |
4328 | } else { | |
4329 | if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { | |
4330 | gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); | |
4331 | } | |
4d6a0680 | 4332 | } |
79aceca5 | 4333 | } |
79aceca5 FB |
4334 | } |
4335 | ||
99e300ef | 4336 | static void gen_mfspr(DisasContext *ctx) |
79aceca5 | 4337 | { |
3fc6c082 | 4338 | gen_op_mfspr(ctx); |
76a66253 | 4339 | } |
3fc6c082 FB |
4340 | |
4341 | /* mftb */ | |
99e300ef | 4342 | static void gen_mftb(DisasContext *ctx) |
3fc6c082 FB |
4343 | { |
4344 | gen_op_mfspr(ctx); | |
79aceca5 FB |
4345 | } |
4346 | ||
0cfe11ea | 4347 | /* mtcrf mtocrf*/ |
99e300ef | 4348 | static void gen_mtcrf(DisasContext *ctx) |
79aceca5 | 4349 | { |
76a66253 | 4350 | uint32_t crm, crn; |
3b46e624 | 4351 | |
76a66253 | 4352 | crm = CRM(ctx->opcode); |
8dd640e4 | 4353 | if (likely((ctx->opcode & 0x00100000))) { |
4354 | if (crm && ((crm & (crm - 1)) == 0)) { | |
4355 | TCGv_i32 temp = tcg_temp_new_i32(); | |
efe843d8 | 4356 | crn = ctz32(crm); |
8dd640e4 | 4357 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); |
0cfe11ea AJ |
4358 | tcg_gen_shri_i32(temp, temp, crn * 4); |
4359 | tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); | |
8dd640e4 | 4360 | tcg_temp_free_i32(temp); |
4361 | } | |
76a66253 | 4362 | } else { |
651721b2 AJ |
4363 | TCGv_i32 temp = tcg_temp_new_i32(); |
4364 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); | |
4365 | for (crn = 0 ; crn < 8 ; crn++) { | |
4366 | if (crm & (1 << crn)) { | |
4367 | tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); | |
4368 | tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); | |
4369 | } | |
4370 | } | |
a7812ae4 | 4371 | tcg_temp_free_i32(temp); |
76a66253 | 4372 | } |
79aceca5 FB |
4373 | } |
4374 | ||
4375 | /* mtmsr */ | |
426613db | 4376 | #if defined(TARGET_PPC64) |
99e300ef | 4377 | static void gen_mtmsrd(DisasContext *ctx) |
426613db | 4378 | { |
9b2fadda BH |
4379 | CHK_SV; |
4380 | ||
4381 | #if !defined(CONFIG_USER_ONLY) | |
5ed19506 NP |
4382 | if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { |
4383 | gen_io_start(); | |
4384 | } | |
be147d08 | 4385 | if (ctx->opcode & 0x00010000) { |
5ed19506 | 4386 | /* L=1 form only updates EE and RI */ |
6527f6ea | 4387 | TCGv t0 = tcg_temp_new(); |
5ed19506 | 4388 | TCGv t1 = tcg_temp_new(); |
efe843d8 DG |
4389 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], |
4390 | (1 << MSR_RI) | (1 << MSR_EE)); | |
5ed19506 | 4391 | tcg_gen_andi_tl(t1, cpu_msr, |
efe843d8 | 4392 | ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); |
5ed19506 NP |
4393 | tcg_gen_or_tl(t1, t1, t0); |
4394 | ||
4395 | gen_helper_store_msr(cpu_env, t1); | |
6527f6ea | 4396 | tcg_temp_free(t0); |
5ed19506 NP |
4397 | tcg_temp_free(t1); |
4398 | ||
be147d08 | 4399 | } else { |
efe843d8 DG |
4400 | /* |
4401 | * XXX: we need to update nip before the store if we enter | |
4402 | * power saving mode, we will exit the loop directly from | |
4403 | * ppc_store_msr | |
056b05f8 | 4404 | */ |
b6bac4bc | 4405 | gen_update_nip(ctx, ctx->base.pc_next); |
e5f17ac6 | 4406 | gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); |
be147d08 | 4407 | } |
5ed19506 NP |
4408 | /* Must stop the translation as machine state (may have) changed */ |
4409 | gen_stop_exception(ctx); | |
9b2fadda | 4410 | #endif /* !defined(CONFIG_USER_ONLY) */ |
426613db | 4411 | } |
9b2fadda | 4412 | #endif /* defined(TARGET_PPC64) */ |
426613db | 4413 | |
99e300ef | 4414 | static void gen_mtmsr(DisasContext *ctx) |
79aceca5 | 4415 | { |
9b2fadda BH |
4416 | CHK_SV; |
4417 | ||
4418 | #if !defined(CONFIG_USER_ONLY) | |
5ed19506 NP |
4419 | if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { |
4420 | gen_io_start(); | |
4421 | } | |
4422 | if (ctx->opcode & 0x00010000) { | |
4423 | /* L=1 form only updates EE and RI */ | |
6527f6ea | 4424 | TCGv t0 = tcg_temp_new(); |
5ed19506 | 4425 | TCGv t1 = tcg_temp_new(); |
efe843d8 DG |
4426 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], |
4427 | (1 << MSR_RI) | (1 << MSR_EE)); | |
5ed19506 | 4428 | tcg_gen_andi_tl(t1, cpu_msr, |
efe843d8 | 4429 | ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); |
5ed19506 NP |
4430 | tcg_gen_or_tl(t1, t1, t0); |
4431 | ||
4432 | gen_helper_store_msr(cpu_env, t1); | |
6527f6ea | 4433 | tcg_temp_free(t0); |
5ed19506 NP |
4434 | tcg_temp_free(t1); |
4435 | ||
be147d08 | 4436 | } else { |
8018dc63 AG |
4437 | TCGv msr = tcg_temp_new(); |
4438 | ||
efe843d8 DG |
4439 | /* |
4440 | * XXX: we need to update nip before the store if we enter | |
4441 | * power saving mode, we will exit the loop directly from | |
4442 | * ppc_store_msr | |
056b05f8 | 4443 | */ |
b6bac4bc | 4444 | gen_update_nip(ctx, ctx->base.pc_next); |
d9bce9d9 | 4445 | #if defined(TARGET_PPC64) |
8018dc63 AG |
4446 | tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); |
4447 | #else | |
4448 | tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); | |
d9bce9d9 | 4449 | #endif |
e5f17ac6 | 4450 | gen_helper_store_msr(cpu_env, msr); |
c80d1df5 | 4451 | tcg_temp_free(msr); |
be147d08 | 4452 | } |
5ed19506 NP |
4453 | /* Must stop the translation as machine state (may have) changed */ |
4454 | gen_stop_exception(ctx); | |
9a64fbe4 | 4455 | #endif |
79aceca5 FB |
4456 | } |
4457 | ||
4458 | /* mtspr */ | |
99e300ef | 4459 | static void gen_mtspr(DisasContext *ctx) |
79aceca5 | 4460 | { |
69b058c8 | 4461 | void (*write_cb)(DisasContext *ctx, int sprn, int gprn); |
79aceca5 FB |
4462 | uint32_t sprn = SPR(ctx->opcode); |
4463 | ||
eb94268e BH |
4464 | #if defined(CONFIG_USER_ONLY) |
4465 | write_cb = ctx->spr_cb[sprn].uea_write; | |
4466 | #else | |
4467 | if (ctx->pr) { | |
4468 | write_cb = ctx->spr_cb[sprn].uea_write; | |
4469 | } else if (ctx->hv) { | |
be147d08 | 4470 | write_cb = ctx->spr_cb[sprn].hea_write; |
eb94268e | 4471 | } else { |
3fc6c082 | 4472 | write_cb = ctx->spr_cb[sprn].oea_write; |
eb94268e | 4473 | } |
9a64fbe4 | 4474 | #endif |
76a66253 JM |
4475 | if (likely(write_cb != NULL)) { |
4476 | if (likely(write_cb != SPR_NOACCESS)) { | |
45d827d2 | 4477 | (*write_cb)(ctx, sprn, rS(ctx->opcode)); |
3fc6c082 FB |
4478 | } else { |
4479 | /* Privilege exception */ | |
31085338 TH |
4480 | qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " |
4481 | "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, | |
4482 | ctx->base.pc_next - 4); | |
9b2fadda | 4483 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 4484 | } |
3fc6c082 | 4485 | } else { |
9b2fadda BH |
4486 | /* ISA 2.07 defines these as no-ops */ |
4487 | if ((ctx->insns_flags2 & PPC2_ISA207S) && | |
4488 | (sprn >= 808 && sprn <= 811)) { | |
4489 | /* This is a nop */ | |
4490 | return; | |
4491 | } | |
4492 | ||
3fc6c082 | 4493 | /* Not defined */ |
31085338 TH |
4494 | qemu_log_mask(LOG_GUEST_ERROR, |
4495 | "Trying to write invalid spr %d (0x%03x) at " | |
4496 | TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4); | |
4d6a0680 | 4497 | |
9b2fadda | 4498 | |
efe843d8 DG |
4499 | /* |
4500 | * The behaviour depends on MSR:PR and SPR# bit 0x10, it can | |
4501 | * generate a priv, a hv emu or a no-op | |
9b2fadda BH |
4502 | */ |
4503 | if (sprn & 0x10) { | |
4504 | if (ctx->pr) { | |
4505 | gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); | |
4506 | } | |
4507 | } else { | |
4508 | if (ctx->pr || sprn == 0) { | |
4509 | gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); | |
4510 | } | |
4d6a0680 | 4511 | } |
79aceca5 | 4512 | } |
79aceca5 FB |
4513 | } |
4514 | ||
dc2ee038 VAS |
4515 | #if defined(TARGET_PPC64) |
4516 | /* setb */ | |
4517 | static void gen_setb(DisasContext *ctx) | |
4518 | { | |
4519 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
4520 | TCGv_i32 t8 = tcg_temp_new_i32(); | |
4521 | TCGv_i32 tm1 = tcg_temp_new_i32(); | |
4522 | int crf = crfS(ctx->opcode); | |
4523 | ||
4524 | tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); | |
4525 | tcg_gen_movi_i32(t8, 8); | |
4526 | tcg_gen_movi_i32(tm1, -1); | |
4527 | tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); | |
4528 | tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
4529 | ||
4530 | tcg_temp_free_i32(t0); | |
4531 | tcg_temp_free_i32(t8); | |
4532 | tcg_temp_free_i32(tm1); | |
4533 | } | |
4534 | #endif | |
4535 | ||
79aceca5 | 4536 | /*** Cache management ***/ |
99e300ef | 4537 | |
54623277 | 4538 | /* dcbf */ |
99e300ef | 4539 | static void gen_dcbf(DisasContext *ctx) |
79aceca5 | 4540 | { |
dac454af | 4541 | /* XXX: specification says this is treated as a load by the MMU */ |
76db3ba4 AJ |
4542 | TCGv t0; |
4543 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4544 | t0 = tcg_temp_new(); | |
4545 | gen_addr_reg_index(ctx, t0); | |
4546 | gen_qemu_ld8u(ctx, t0, t0); | |
fea0c503 | 4547 | tcg_temp_free(t0); |
79aceca5 FB |
4548 | } |
4549 | ||
50728199 RK |
4550 | /* dcbfep (external PID dcbf) */ |
4551 | static void gen_dcbfep(DisasContext *ctx) | |
4552 | { | |
4553 | /* XXX: specification says this is treated as a load by the MMU */ | |
4554 | TCGv t0; | |
4555 | CHK_SV; | |
4556 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4557 | t0 = tcg_temp_new(); | |
4558 | gen_addr_reg_index(ctx, t0); | |
4559 | tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); | |
4560 | tcg_temp_free(t0); | |
4561 | } | |
4562 | ||
79aceca5 | 4563 | /* dcbi (Supervisor only) */ |
99e300ef | 4564 | static void gen_dcbi(DisasContext *ctx) |
79aceca5 | 4565 | { |
a541f297 | 4566 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4567 | GEN_PRIV; |
a541f297 | 4568 | #else |
b61f2753 | 4569 | TCGv EA, val; |
9b2fadda BH |
4570 | |
4571 | CHK_SV; | |
a7812ae4 | 4572 | EA = tcg_temp_new(); |
76db3ba4 AJ |
4573 | gen_set_access_type(ctx, ACCESS_CACHE); |
4574 | gen_addr_reg_index(ctx, EA); | |
a7812ae4 | 4575 | val = tcg_temp_new(); |
76a66253 | 4576 | /* XXX: specification says this should be treated as a store by the MMU */ |
76db3ba4 AJ |
4577 | gen_qemu_ld8u(ctx, val, EA); |
4578 | gen_qemu_st8(ctx, val, EA); | |
b61f2753 AJ |
4579 | tcg_temp_free(val); |
4580 | tcg_temp_free(EA); | |
9b2fadda | 4581 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4582 | } |
4583 | ||
4584 | /* dcdst */ | |
99e300ef | 4585 | static void gen_dcbst(DisasContext *ctx) |
79aceca5 | 4586 | { |
76a66253 | 4587 | /* XXX: specification say this is treated as a load by the MMU */ |
76db3ba4 AJ |
4588 | TCGv t0; |
4589 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4590 | t0 = tcg_temp_new(); | |
4591 | gen_addr_reg_index(ctx, t0); | |
4592 | gen_qemu_ld8u(ctx, t0, t0); | |
fea0c503 | 4593 | tcg_temp_free(t0); |
79aceca5 FB |
4594 | } |
4595 | ||
50728199 RK |
4596 | /* dcbstep (dcbstep External PID version) */ |
4597 | static void gen_dcbstep(DisasContext *ctx) | |
4598 | { | |
4599 | /* XXX: specification say this is treated as a load by the MMU */ | |
4600 | TCGv t0; | |
4601 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4602 | t0 = tcg_temp_new(); | |
4603 | gen_addr_reg_index(ctx, t0); | |
4604 | tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); | |
4605 | tcg_temp_free(t0); | |
4606 | } | |
4607 | ||
79aceca5 | 4608 | /* dcbt */ |
99e300ef | 4609 | static void gen_dcbt(DisasContext *ctx) |
79aceca5 | 4610 | { |
efe843d8 DG |
4611 | /* |
4612 | * interpreted as no-op | |
4613 | * XXX: specification say this is treated as a load by the MMU but | |
4614 | * does not generate any exception | |
76a66253 | 4615 | */ |
79aceca5 FB |
4616 | } |
4617 | ||
50728199 RK |
4618 | /* dcbtep */ |
4619 | static void gen_dcbtep(DisasContext *ctx) | |
4620 | { | |
efe843d8 DG |
4621 | /* |
4622 | * interpreted as no-op | |
4623 | * XXX: specification say this is treated as a load by the MMU but | |
4624 | * does not generate any exception | |
50728199 RK |
4625 | */ |
4626 | } | |
4627 | ||
79aceca5 | 4628 | /* dcbtst */ |
99e300ef | 4629 | static void gen_dcbtst(DisasContext *ctx) |
79aceca5 | 4630 | { |
efe843d8 DG |
4631 | /* |
4632 | * interpreted as no-op | |
4633 | * XXX: specification say this is treated as a load by the MMU but | |
4634 | * does not generate any exception | |
76a66253 | 4635 | */ |
79aceca5 FB |
4636 | } |
4637 | ||
50728199 RK |
4638 | /* dcbtstep */ |
4639 | static void gen_dcbtstep(DisasContext *ctx) | |
4640 | { | |
efe843d8 DG |
4641 | /* |
4642 | * interpreted as no-op | |
4643 | * XXX: specification say this is treated as a load by the MMU but | |
4644 | * does not generate any exception | |
50728199 RK |
4645 | */ |
4646 | } | |
4647 | ||
4d09d529 AG |
4648 | /* dcbtls */ |
4649 | static void gen_dcbtls(DisasContext *ctx) | |
4650 | { | |
4651 | /* Always fails locking the cache */ | |
4652 | TCGv t0 = tcg_temp_new(); | |
4653 | gen_load_spr(t0, SPR_Exxx_L1CSR0); | |
4654 | tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); | |
4655 | gen_store_spr(SPR_Exxx_L1CSR0, t0); | |
4656 | tcg_temp_free(t0); | |
4657 | } | |
4658 | ||
79aceca5 | 4659 | /* dcbz */ |
99e300ef | 4660 | static void gen_dcbz(DisasContext *ctx) |
79aceca5 | 4661 | { |
8e33944f | 4662 | TCGv tcgv_addr; |
c9f82d01 | 4663 | TCGv_i32 tcgv_op; |
d63001d1 | 4664 | |
76db3ba4 | 4665 | gen_set_access_type(ctx, ACCESS_CACHE); |
8e33944f | 4666 | tcgv_addr = tcg_temp_new(); |
c9f82d01 | 4667 | tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); |
8e33944f | 4668 | gen_addr_reg_index(ctx, tcgv_addr); |
c9f82d01 | 4669 | gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); |
8e33944f | 4670 | tcg_temp_free(tcgv_addr); |
c9f82d01 | 4671 | tcg_temp_free_i32(tcgv_op); |
79aceca5 FB |
4672 | } |
4673 | ||
50728199 RK |
4674 | /* dcbzep */ |
4675 | static void gen_dcbzep(DisasContext *ctx) | |
4676 | { | |
4677 | TCGv tcgv_addr; | |
4678 | TCGv_i32 tcgv_op; | |
4679 | ||
4680 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4681 | tcgv_addr = tcg_temp_new(); | |
4682 | tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); | |
4683 | gen_addr_reg_index(ctx, tcgv_addr); | |
4684 | gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); | |
4685 | tcg_temp_free(tcgv_addr); | |
4686 | tcg_temp_free_i32(tcgv_op); | |
4687 | } | |
4688 | ||
ae1c1a3d | 4689 | /* dst / dstt */ |
99e300ef | 4690 | static void gen_dst(DisasContext *ctx) |
ae1c1a3d AJ |
4691 | { |
4692 | if (rA(ctx->opcode) == 0) { | |
e41029b3 | 4693 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
ae1c1a3d AJ |
4694 | } else { |
4695 | /* interpreted as no-op */ | |
4696 | } | |
4697 | } | |
4698 | ||
4699 | /* dstst /dststt */ | |
99e300ef | 4700 | static void gen_dstst(DisasContext *ctx) |
ae1c1a3d AJ |
4701 | { |
4702 | if (rA(ctx->opcode) == 0) { | |
e41029b3 | 4703 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
ae1c1a3d AJ |
4704 | } else { |
4705 | /* interpreted as no-op */ | |
4706 | } | |
4707 | ||
4708 | } | |
4709 | ||
4710 | /* dss / dssall */ | |
99e300ef | 4711 | static void gen_dss(DisasContext *ctx) |
ae1c1a3d AJ |
4712 | { |
4713 | /* interpreted as no-op */ | |
4714 | } | |
4715 | ||
79aceca5 | 4716 | /* icbi */ |
99e300ef | 4717 | static void gen_icbi(DisasContext *ctx) |
79aceca5 | 4718 | { |
76db3ba4 AJ |
4719 | TCGv t0; |
4720 | gen_set_access_type(ctx, ACCESS_CACHE); | |
76db3ba4 AJ |
4721 | t0 = tcg_temp_new(); |
4722 | gen_addr_reg_index(ctx, t0); | |
2f5a189c | 4723 | gen_helper_icbi(cpu_env, t0); |
37d269df | 4724 | tcg_temp_free(t0); |
79aceca5 FB |
4725 | } |
4726 | ||
50728199 RK |
4727 | /* icbiep */ |
4728 | static void gen_icbiep(DisasContext *ctx) | |
4729 | { | |
4730 | TCGv t0; | |
4731 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4732 | t0 = tcg_temp_new(); | |
4733 | gen_addr_reg_index(ctx, t0); | |
4734 | gen_helper_icbiep(cpu_env, t0); | |
4735 | tcg_temp_free(t0); | |
4736 | } | |
4737 | ||
79aceca5 FB |
4738 | /* Optional: */ |
4739 | /* dcba */ | |
99e300ef | 4740 | static void gen_dcba(DisasContext *ctx) |
79aceca5 | 4741 | { |
efe843d8 DG |
4742 | /* |
4743 | * interpreted as no-op | |
4744 | * XXX: specification say this is treated as a store by the MMU | |
0db1b20e JM |
4745 | * but does not generate any exception |
4746 | */ | |
79aceca5 FB |
4747 | } |
4748 | ||
4749 | /*** Segment register manipulation ***/ | |
4750 | /* Supervisor only: */ | |
99e300ef | 4751 | |
54623277 | 4752 | /* mfsr */ |
99e300ef | 4753 | static void gen_mfsr(DisasContext *ctx) |
79aceca5 | 4754 | { |
9a64fbe4 | 4755 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4756 | GEN_PRIV; |
9a64fbe4 | 4757 | #else |
74d37793 | 4758 | TCGv t0; |
9b2fadda BH |
4759 | |
4760 | CHK_SV; | |
74d37793 | 4761 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4762 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4763 | tcg_temp_free(t0); |
9b2fadda | 4764 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4765 | } |
4766 | ||
4767 | /* mfsrin */ | |
99e300ef | 4768 | static void gen_mfsrin(DisasContext *ctx) |
79aceca5 | 4769 | { |
9a64fbe4 | 4770 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4771 | GEN_PRIV; |
9a64fbe4 | 4772 | #else |
74d37793 | 4773 | TCGv t0; |
9b2fadda BH |
4774 | |
4775 | CHK_SV; | |
74d37793 | 4776 | t0 = tcg_temp_new(); |
e2622073 | 4777 | tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); |
c6c7cf05 | 4778 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4779 | tcg_temp_free(t0); |
9b2fadda | 4780 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4781 | } |
4782 | ||
4783 | /* mtsr */ | |
99e300ef | 4784 | static void gen_mtsr(DisasContext *ctx) |
79aceca5 | 4785 | { |
9a64fbe4 | 4786 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4787 | GEN_PRIV; |
9a64fbe4 | 4788 | #else |
74d37793 | 4789 | TCGv t0; |
9b2fadda BH |
4790 | |
4791 | CHK_SV; | |
74d37793 | 4792 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4793 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4794 | tcg_temp_free(t0); |
9b2fadda | 4795 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4796 | } |
4797 | ||
4798 | /* mtsrin */ | |
99e300ef | 4799 | static void gen_mtsrin(DisasContext *ctx) |
79aceca5 | 4800 | { |
9a64fbe4 | 4801 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4802 | GEN_PRIV; |
9a64fbe4 | 4803 | #else |
74d37793 | 4804 | TCGv t0; |
9b2fadda BH |
4805 | CHK_SV; |
4806 | ||
74d37793 | 4807 | t0 = tcg_temp_new(); |
e2622073 | 4808 | tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); |
c6c7cf05 | 4809 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); |
74d37793 | 4810 | tcg_temp_free(t0); |
9b2fadda | 4811 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4812 | } |
4813 | ||
12de9a39 JM |
4814 | #if defined(TARGET_PPC64) |
4815 | /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ | |
e8eaa2c0 | 4816 | |
54623277 | 4817 | /* mfsr */ |
e8eaa2c0 | 4818 | static void gen_mfsr_64b(DisasContext *ctx) |
12de9a39 JM |
4819 | { |
4820 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4821 | GEN_PRIV; |
12de9a39 | 4822 | #else |
74d37793 | 4823 | TCGv t0; |
9b2fadda BH |
4824 | |
4825 | CHK_SV; | |
74d37793 | 4826 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4827 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4828 | tcg_temp_free(t0); |
9b2fadda | 4829 | #endif /* defined(CONFIG_USER_ONLY) */ |
12de9a39 JM |
4830 | } |
4831 | ||
4832 | /* mfsrin */ | |
e8eaa2c0 | 4833 | static void gen_mfsrin_64b(DisasContext *ctx) |
12de9a39 JM |
4834 | { |
4835 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4836 | GEN_PRIV; |
12de9a39 | 4837 | #else |
74d37793 | 4838 | TCGv t0; |
9b2fadda BH |
4839 | |
4840 | CHK_SV; | |
74d37793 | 4841 | t0 = tcg_temp_new(); |
e2622073 | 4842 | tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); |
c6c7cf05 | 4843 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4844 | tcg_temp_free(t0); |
9b2fadda | 4845 | #endif /* defined(CONFIG_USER_ONLY) */ |
12de9a39 JM |
4846 | } |
4847 | ||
4848 | /* mtsr */ | |
e8eaa2c0 | 4849 | static void gen_mtsr_64b(DisasContext *ctx) |
12de9a39 JM |
4850 | { |
4851 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4852 | GEN_PRIV; |
12de9a39 | 4853 | #else |
74d37793 | 4854 | TCGv t0; |
9b2fadda BH |
4855 | |
4856 | CHK_SV; | |
74d37793 | 4857 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4858 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4859 | tcg_temp_free(t0); |
9b2fadda | 4860 | #endif /* defined(CONFIG_USER_ONLY) */ |
12de9a39 JM |
4861 | } |
4862 | ||
4863 | /* mtsrin */ | |
e8eaa2c0 | 4864 | static void gen_mtsrin_64b(DisasContext *ctx) |
12de9a39 JM |
4865 | { |
4866 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4867 | GEN_PRIV; |
12de9a39 | 4868 | #else |
74d37793 | 4869 | TCGv t0; |
9b2fadda BH |
4870 | |
4871 | CHK_SV; | |
74d37793 | 4872 | t0 = tcg_temp_new(); |
e2622073 | 4873 | tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); |
c6c7cf05 | 4874 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4875 | tcg_temp_free(t0); |
9b2fadda | 4876 | #endif /* defined(CONFIG_USER_ONLY) */ |
12de9a39 | 4877 | } |
f6b868fc BS |
4878 | |
4879 | /* slbmte */ | |
e8eaa2c0 | 4880 | static void gen_slbmte(DisasContext *ctx) |
f6b868fc BS |
4881 | { |
4882 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4883 | GEN_PRIV; |
f6b868fc | 4884 | #else |
9b2fadda BH |
4885 | CHK_SV; |
4886 | ||
c6c7cf05 BS |
4887 | gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], |
4888 | cpu_gpr[rS(ctx->opcode)]); | |
9b2fadda | 4889 | #endif /* defined(CONFIG_USER_ONLY) */ |
f6b868fc BS |
4890 | } |
4891 | ||
efdef95f DG |
4892 | static void gen_slbmfee(DisasContext *ctx) |
4893 | { | |
4894 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4895 | GEN_PRIV; |
efdef95f | 4896 | #else |
9b2fadda BH |
4897 | CHK_SV; |
4898 | ||
c6c7cf05 | 4899 | gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, |
efdef95f | 4900 | cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 4901 | #endif /* defined(CONFIG_USER_ONLY) */ |
efdef95f DG |
4902 | } |
4903 | ||
4904 | static void gen_slbmfev(DisasContext *ctx) | |
4905 | { | |
4906 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4907 | GEN_PRIV; |
efdef95f | 4908 | #else |
9b2fadda BH |
4909 | CHK_SV; |
4910 | ||
c6c7cf05 | 4911 | gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, |
efdef95f | 4912 | cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 4913 | #endif /* defined(CONFIG_USER_ONLY) */ |
efdef95f | 4914 | } |
c76c22d5 BH |
4915 | |
4916 | static void gen_slbfee_(DisasContext *ctx) | |
4917 | { | |
4918 | #if defined(CONFIG_USER_ONLY) | |
4919 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4920 | #else | |
4921 | TCGLabel *l1, *l2; | |
4922 | ||
4923 | if (unlikely(ctx->pr)) { | |
4924 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4925 | return; | |
4926 | } | |
4927 | gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, | |
4928 | cpu_gpr[rB(ctx->opcode)]); | |
4929 | l1 = gen_new_label(); | |
4930 | l2 = gen_new_label(); | |
4931 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); | |
4932 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); | |
efa73196 | 4933 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); |
c76c22d5 BH |
4934 | tcg_gen_br(l2); |
4935 | gen_set_label(l1); | |
4936 | tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); | |
4937 | gen_set_label(l2); | |
4938 | #endif | |
4939 | } | |
12de9a39 JM |
4940 | #endif /* defined(TARGET_PPC64) */ |
4941 | ||
79aceca5 | 4942 | /*** Lookaside buffer management ***/ |
c47493f2 | 4943 | /* Optional & supervisor only: */ |
99e300ef | 4944 | |
54623277 | 4945 | /* tlbia */ |
99e300ef | 4946 | static void gen_tlbia(DisasContext *ctx) |
79aceca5 | 4947 | { |
9a64fbe4 | 4948 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4949 | GEN_PRIV; |
9a64fbe4 | 4950 | #else |
9b2fadda BH |
4951 | CHK_HV; |
4952 | ||
c6c7cf05 | 4953 | gen_helper_tlbia(cpu_env); |
9b2fadda | 4954 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4955 | } |
4956 | ||
bf14b1ce | 4957 | /* tlbiel */ |
99e300ef | 4958 | static void gen_tlbiel(DisasContext *ctx) |
bf14b1ce BS |
4959 | { |
4960 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4961 | GEN_PRIV; |
bf14b1ce | 4962 | #else |
9b2fadda BH |
4963 | CHK_SV; |
4964 | ||
c6c7cf05 | 4965 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 4966 | #endif /* defined(CONFIG_USER_ONLY) */ |
bf14b1ce BS |
4967 | } |
4968 | ||
79aceca5 | 4969 | /* tlbie */ |
99e300ef | 4970 | static void gen_tlbie(DisasContext *ctx) |
79aceca5 | 4971 | { |
9a64fbe4 | 4972 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4973 | GEN_PRIV; |
9a64fbe4 | 4974 | #else |
d76ab5e1 | 4975 | TCGv_i32 t1; |
c6fd28fd SJS |
4976 | |
4977 | if (ctx->gtse) { | |
91c60f12 | 4978 | CHK_SV; /* If gtse is set then tlbie is supervisor privileged */ |
c6fd28fd SJS |
4979 | } else { |
4980 | CHK_HV; /* Else hypervisor privileged */ | |
4981 | } | |
9b2fadda | 4982 | |
9ca3f7f3 | 4983 | if (NARROW_MODE(ctx)) { |
74d37793 AJ |
4984 | TCGv t0 = tcg_temp_new(); |
4985 | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); | |
c6c7cf05 | 4986 | gen_helper_tlbie(cpu_env, t0); |
74d37793 | 4987 | tcg_temp_free(t0); |
9ca3f7f3 | 4988 | } else { |
c6c7cf05 | 4989 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9ca3f7f3 | 4990 | } |
d76ab5e1 ND |
4991 | t1 = tcg_temp_new_i32(); |
4992 | tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); | |
4993 | tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); | |
4994 | tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); | |
4995 | tcg_temp_free_i32(t1); | |
9b2fadda | 4996 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4997 | } |
4998 | ||
4999 | /* tlbsync */ | |
99e300ef | 5000 | static void gen_tlbsync(DisasContext *ctx) |
79aceca5 | 5001 | { |
9a64fbe4 | 5002 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 5003 | GEN_PRIV; |
9a64fbe4 | 5004 | #else |
91c60f12 CLG |
5005 | |
5006 | if (ctx->gtse) { | |
5007 | CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */ | |
5008 | } else { | |
5009 | CHK_HV; /* Else hypervisor privileged */ | |
5010 | } | |
9b2fadda | 5011 | |
e3cffe6f ND |
5012 | /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ |
5013 | if (ctx->insns_flags & PPC_BOOKE) { | |
5014 | gen_check_tlb_flush(ctx, true); | |
5015 | } | |
9b2fadda | 5016 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
5017 | } |
5018 | ||
426613db JM |
5019 | #if defined(TARGET_PPC64) |
5020 | /* slbia */ | |
99e300ef | 5021 | static void gen_slbia(DisasContext *ctx) |
426613db JM |
5022 | { |
5023 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5024 | GEN_PRIV; |
426613db | 5025 | #else |
0418bf78 NP |
5026 | uint32_t ih = (ctx->opcode >> 21) & 0x7; |
5027 | TCGv_i32 t0 = tcg_const_i32(ih); | |
5028 | ||
9b2fadda BH |
5029 | CHK_SV; |
5030 | ||
0418bf78 | 5031 | gen_helper_slbia(cpu_env, t0); |
3119154d | 5032 | tcg_temp_free_i32(t0); |
9b2fadda | 5033 | #endif /* defined(CONFIG_USER_ONLY) */ |
426613db JM |
5034 | } |
5035 | ||
5036 | /* slbie */ | |
99e300ef | 5037 | static void gen_slbie(DisasContext *ctx) |
426613db JM |
5038 | { |
5039 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5040 | GEN_PRIV; |
426613db | 5041 | #else |
9b2fadda BH |
5042 | CHK_SV; |
5043 | ||
c6c7cf05 | 5044 | gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 5045 | #endif /* defined(CONFIG_USER_ONLY) */ |
426613db | 5046 | } |
a63f1dfc ND |
5047 | |
5048 | /* slbieg */ | |
5049 | static void gen_slbieg(DisasContext *ctx) | |
5050 | { | |
5051 | #if defined(CONFIG_USER_ONLY) | |
5052 | GEN_PRIV; | |
5053 | #else | |
5054 | CHK_SV; | |
5055 | ||
5056 | gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]); | |
5057 | #endif /* defined(CONFIG_USER_ONLY) */ | |
5058 | } | |
5059 | ||
62d897ca ND |
5060 | /* slbsync */ |
5061 | static void gen_slbsync(DisasContext *ctx) | |
5062 | { | |
5063 | #if defined(CONFIG_USER_ONLY) | |
5064 | GEN_PRIV; | |
5065 | #else | |
5066 | CHK_SV; | |
5067 | gen_check_tlb_flush(ctx, true); | |
5068 | #endif /* defined(CONFIG_USER_ONLY) */ | |
5069 | } | |
5070 | ||
9b2fadda | 5071 | #endif /* defined(TARGET_PPC64) */ |
426613db | 5072 | |
79aceca5 FB |
5073 | /*** External control ***/ |
5074 | /* Optional: */ | |
99e300ef | 5075 | |
54623277 | 5076 | /* eciwx */ |
99e300ef | 5077 | static void gen_eciwx(DisasContext *ctx) |
79aceca5 | 5078 | { |
76db3ba4 | 5079 | TCGv t0; |
fa407c03 | 5080 | /* Should check EAR[E] ! */ |
76db3ba4 AJ |
5081 | gen_set_access_type(ctx, ACCESS_EXT); |
5082 | t0 = tcg_temp_new(); | |
5083 | gen_addr_reg_index(ctx, t0); | |
c674a983 RH |
5084 | tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, |
5085 | DEF_MEMOP(MO_UL | MO_ALIGN)); | |
fa407c03 | 5086 | tcg_temp_free(t0); |
76a66253 JM |
5087 | } |
5088 | ||
5089 | /* ecowx */ | |
99e300ef | 5090 | static void gen_ecowx(DisasContext *ctx) |
76a66253 | 5091 | { |
76db3ba4 | 5092 | TCGv t0; |
fa407c03 | 5093 | /* Should check EAR[E] ! */ |
76db3ba4 AJ |
5094 | gen_set_access_type(ctx, ACCESS_EXT); |
5095 | t0 = tcg_temp_new(); | |
5096 | gen_addr_reg_index(ctx, t0); | |
c674a983 RH |
5097 | tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, |
5098 | DEF_MEMOP(MO_UL | MO_ALIGN)); | |
fa407c03 | 5099 | tcg_temp_free(t0); |
76a66253 JM |
5100 | } |
5101 | ||
5102 | /* PowerPC 601 specific instructions */ | |
99e300ef | 5103 | |
54623277 | 5104 | /* abs - abs. */ |
99e300ef | 5105 | static void gen_abs(DisasContext *ctx) |
76a66253 | 5106 | { |
fe21b785 RH |
5107 | TCGv d = cpu_gpr[rD(ctx->opcode)]; |
5108 | TCGv a = cpu_gpr[rA(ctx->opcode)]; | |
5109 | ||
5110 | tcg_gen_abs_tl(d, a); | |
efe843d8 | 5111 | if (unlikely(Rc(ctx->opcode) != 0)) { |
fe21b785 | 5112 | gen_set_Rc0(ctx, d); |
efe843d8 | 5113 | } |
76a66253 JM |
5114 | } |
5115 | ||
5116 | /* abso - abso. */ | |
99e300ef | 5117 | static void gen_abso(DisasContext *ctx) |
76a66253 | 5118 | { |
fe21b785 RH |
5119 | TCGv d = cpu_gpr[rD(ctx->opcode)]; |
5120 | TCGv a = cpu_gpr[rA(ctx->opcode)]; | |
5121 | ||
5122 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_ov, a, 0x80000000); | |
5123 | tcg_gen_abs_tl(d, a); | |
5124 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); | |
efe843d8 | 5125 | if (unlikely(Rc(ctx->opcode) != 0)) { |
fe21b785 | 5126 | gen_set_Rc0(ctx, d); |
efe843d8 | 5127 | } |
76a66253 JM |
5128 | } |
5129 | ||
5130 | /* clcs */ | |
99e300ef | 5131 | static void gen_clcs(DisasContext *ctx) |
76a66253 | 5132 | { |
22e0e173 | 5133 | TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); |
d523dd00 | 5134 | gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
22e0e173 | 5135 | tcg_temp_free_i32(t0); |
c7697e1f | 5136 | /* Rc=1 sets CR0 to an undefined state */ |
76a66253 JM |
5137 | } |
5138 | ||
5139 | /* div - div. */ | |
99e300ef | 5140 | static void gen_div(DisasContext *ctx) |
76a66253 | 5141 | { |
d15f74fb BS |
5142 | gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
5143 | cpu_gpr[rB(ctx->opcode)]); | |
efe843d8 | 5144 | if (unlikely(Rc(ctx->opcode) != 0)) { |
22e0e173 | 5145 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
efe843d8 | 5146 | } |
76a66253 JM |
5147 | } |
5148 | ||
5149 | /* divo - divo. */ | |
99e300ef | 5150 | static void gen_divo(DisasContext *ctx) |
76a66253 | 5151 | { |
d15f74fb BS |
5152 | gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
5153 | cpu_gpr[rB(ctx->opcode)]); | |
efe843d8 | 5154 | if (unlikely(Rc(ctx->opcode) != 0)) { |
22e0e173 | 5155 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
efe843d8 | 5156 | } |
76a66253 JM |
5157 | } |
5158 | ||
5159 | /* divs - divs. */ | |
99e300ef | 5160 | static void gen_divs(DisasContext *ctx) |
76a66253 | 5161 | { |
d15f74fb BS |
5162 | gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
5163 | cpu_gpr[rB(ctx->opcode)]); | |
efe843d8 | 5164 | if (unlikely(Rc(ctx->opcode) != 0)) { |
22e0e173 | 5165 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
efe843d8 | 5166 | } |
76a66253 JM |
5167 | } |
5168 | ||
5169 | /* divso - divso. */ | |
99e300ef | 5170 | static void gen_divso(DisasContext *ctx) |
76a66253 | 5171 | { |
d15f74fb BS |
5172 | gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5173 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
efe843d8 | 5174 | if (unlikely(Rc(ctx->opcode) != 0)) { |
22e0e173 | 5175 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
efe843d8 | 5176 | } |
76a66253 JM |
5177 | } |
5178 | ||
5179 | /* doz - doz. */ | |
99e300ef | 5180 | static void gen_doz(DisasContext *ctx) |
76a66253 | 5181 | { |
42a268c2 RH |
5182 | TCGLabel *l1 = gen_new_label(); |
5183 | TCGLabel *l2 = gen_new_label(); | |
efe843d8 DG |
5184 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], |
5185 | cpu_gpr[rA(ctx->opcode)], l1); | |
5186 | tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
5187 | cpu_gpr[rA(ctx->opcode)]); | |
22e0e173 AJ |
5188 | tcg_gen_br(l2); |
5189 | gen_set_label(l1); | |
5190 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
5191 | gen_set_label(l2); | |
efe843d8 | 5192 | if (unlikely(Rc(ctx->opcode) != 0)) { |
22e0e173 | 5193 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
efe843d8 | 5194 | } |
76a66253 JM |
5195 | } |
5196 | ||
5197 | /* dozo - dozo. */ | |
99e300ef | 5198 | static void gen_dozo(DisasContext *ctx) |
76a66253 | 5199 | { |
42a268c2 RH |
5200 | TCGLabel *l1 = gen_new_label(); |
5201 | TCGLabel *l2 = gen_new_label(); | |
22e0e173 AJ |
5202 | TCGv t0 = tcg_temp_new(); |
5203 | TCGv t1 = tcg_temp_new(); | |
5204 | TCGv t2 = tcg_temp_new(); | |
5205 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 5206 | tcg_gen_movi_tl(cpu_ov, 0); |
efe843d8 DG |
5207 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], |
5208 | cpu_gpr[rA(ctx->opcode)], l1); | |
22e0e173 AJ |
5209 | tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
5210 | tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
5211 | tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); | |
5212 | tcg_gen_andc_tl(t1, t1, t2); | |
5213 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
5214 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); | |
da91a00f RH |
5215 | tcg_gen_movi_tl(cpu_ov, 1); |
5216 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
5217 | tcg_gen_br(l2); |
5218 | gen_set_label(l1); | |
5219 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
5220 | gen_set_label(l2); | |
5221 | tcg_temp_free(t0); | |
5222 | tcg_temp_free(t1); | |
5223 | tcg_temp_free(t2); | |
efe843d8 | 5224 | if (unlikely(Rc(ctx->opcode) != 0)) { |
22e0e173 | 5225 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
efe843d8 | 5226 | } |
76a66253 JM |
5227 | } |
5228 | ||
5229 | /* dozi */ | |
99e300ef | 5230 | static void gen_dozi(DisasContext *ctx) |
76a66253 | 5231 | { |
22e0e173 | 5232 | target_long simm = SIMM(ctx->opcode); |
42a268c2 RH |
5233 | TCGLabel *l1 = gen_new_label(); |
5234 | TCGLabel *l2 = gen_new_label(); | |
22e0e173 AJ |
5235 | tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); |
5236 | tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); | |
5237 | tcg_gen_br(l2); | |
5238 | gen_set_label(l1); | |
5239 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
5240 | gen_set_label(l2); | |
efe843d8 | 5241 | if (unlikely(Rc(ctx->opcode) != 0)) { |
22e0e173 | 5242 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
efe843d8 | 5243 | } |
76a66253 JM |
5244 | } |
5245 | ||
76a66253 | 5246 | /* lscbx - lscbx. */ |
99e300ef | 5247 | static void gen_lscbx(DisasContext *ctx) |
76a66253 | 5248 | { |
bdb4b689 AJ |
5249 | TCGv t0 = tcg_temp_new(); |
5250 | TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); | |
5251 | TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); | |
5252 | TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); | |
76a66253 | 5253 | |
76db3ba4 | 5254 | gen_addr_reg_index(ctx, t0); |
2f5a189c | 5255 | gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); |
bdb4b689 AJ |
5256 | tcg_temp_free_i32(t1); |
5257 | tcg_temp_free_i32(t2); | |
5258 | tcg_temp_free_i32(t3); | |
3d7b417e | 5259 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); |
bdb4b689 | 5260 | tcg_gen_or_tl(cpu_xer, cpu_xer, t0); |
efe843d8 | 5261 | if (unlikely(Rc(ctx->opcode) != 0)) { |
bdb4b689 | 5262 | gen_set_Rc0(ctx, t0); |
efe843d8 | 5263 | } |
bdb4b689 | 5264 | tcg_temp_free(t0); |
76a66253 JM |
5265 | } |
5266 | ||
5267 | /* maskg - maskg. */ | |
99e300ef | 5268 | static void gen_maskg(DisasContext *ctx) |
76a66253 | 5269 | { |
42a268c2 | 5270 | TCGLabel *l1 = gen_new_label(); |
22e0e173 AJ |
5271 | TCGv t0 = tcg_temp_new(); |
5272 | TCGv t1 = tcg_temp_new(); | |
5273 | TCGv t2 = tcg_temp_new(); | |
5274 | TCGv t3 = tcg_temp_new(); | |
5275 | tcg_gen_movi_tl(t3, 0xFFFFFFFF); | |
5276 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5277 | tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); | |
5278 | tcg_gen_addi_tl(t2, t0, 1); | |
5279 | tcg_gen_shr_tl(t2, t3, t2); | |
5280 | tcg_gen_shr_tl(t3, t3, t1); | |
5281 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); | |
5282 | tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); | |
5283 | tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
5284 | gen_set_label(l1); | |
5285 | tcg_temp_free(t0); | |
5286 | tcg_temp_free(t1); | |
5287 | tcg_temp_free(t2); | |
5288 | tcg_temp_free(t3); | |
efe843d8 | 5289 | if (unlikely(Rc(ctx->opcode) != 0)) { |
22e0e173 | 5290 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 5291 | } |
76a66253 JM |
5292 | } |
5293 | ||
5294 | /* maskir - maskir. */ | |
99e300ef | 5295 | static void gen_maskir(DisasContext *ctx) |
76a66253 | 5296 | { |
22e0e173 AJ |
5297 | TCGv t0 = tcg_temp_new(); |
5298 | TCGv t1 = tcg_temp_new(); | |
5299 | tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
5300 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
5301 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5302 | tcg_temp_free(t0); | |
5303 | tcg_temp_free(t1); | |
efe843d8 | 5304 | if (unlikely(Rc(ctx->opcode) != 0)) { |
22e0e173 | 5305 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 5306 | } |
76a66253 JM |
5307 | } |
5308 | ||
5309 | /* mul - mul. */ | |
99e300ef | 5310 | static void gen_mul(DisasContext *ctx) |
76a66253 | 5311 | { |
22e0e173 AJ |
5312 | TCGv_i64 t0 = tcg_temp_new_i64(); |
5313 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
5314 | TCGv t2 = tcg_temp_new(); | |
5315 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
5316 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
5317 | tcg_gen_mul_i64(t0, t0, t1); | |
5318 | tcg_gen_trunc_i64_tl(t2, t0); | |
5319 | gen_store_spr(SPR_MQ, t2); | |
5320 | tcg_gen_shri_i64(t1, t0, 32); | |
5321 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
5322 | tcg_temp_free_i64(t0); | |
5323 | tcg_temp_free_i64(t1); | |
5324 | tcg_temp_free(t2); | |
efe843d8 | 5325 | if (unlikely(Rc(ctx->opcode) != 0)) { |
22e0e173 | 5326 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
efe843d8 | 5327 | } |
76a66253 JM |
5328 | } |
5329 | ||
5330 | /* mulo - mulo. */ | |
99e300ef | 5331 | static void gen_mulo(DisasContext *ctx) |
76a66253 | 5332 | { |
42a268c2 | 5333 | TCGLabel *l1 = gen_new_label(); |
22e0e173 AJ |
5334 | TCGv_i64 t0 = tcg_temp_new_i64(); |
5335 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
5336 | TCGv t2 = tcg_temp_new(); | |
5337 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 5338 | tcg_gen_movi_tl(cpu_ov, 0); |
22e0e173 AJ |
5339 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
5340 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
5341 | tcg_gen_mul_i64(t0, t0, t1); | |
5342 | tcg_gen_trunc_i64_tl(t2, t0); | |
5343 | gen_store_spr(SPR_MQ, t2); | |
5344 | tcg_gen_shri_i64(t1, t0, 32); | |
5345 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
5346 | tcg_gen_ext32s_i64(t1, t0); | |
5347 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); | |
da91a00f RH |
5348 | tcg_gen_movi_tl(cpu_ov, 1); |
5349 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
5350 | gen_set_label(l1); |
5351 | tcg_temp_free_i64(t0); | |
5352 | tcg_temp_free_i64(t1); | |
5353 | tcg_temp_free(t2); | |
efe843d8 | 5354 | if (unlikely(Rc(ctx->opcode) != 0)) { |
22e0e173 | 5355 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
efe843d8 | 5356 | } |
76a66253 JM |
5357 | } |
5358 | ||
5359 | /* nabs - nabs. */ | |
99e300ef | 5360 | static void gen_nabs(DisasContext *ctx) |
76a66253 | 5361 | { |
fe21b785 RH |
5362 | TCGv d = cpu_gpr[rD(ctx->opcode)]; |
5363 | TCGv a = cpu_gpr[rA(ctx->opcode)]; | |
5364 | ||
5365 | tcg_gen_abs_tl(d, a); | |
5366 | tcg_gen_neg_tl(d, d); | |
efe843d8 | 5367 | if (unlikely(Rc(ctx->opcode) != 0)) { |
fe21b785 | 5368 | gen_set_Rc0(ctx, d); |
efe843d8 | 5369 | } |
76a66253 JM |
5370 | } |
5371 | ||
5372 | /* nabso - nabso. */ | |
99e300ef | 5373 | static void gen_nabso(DisasContext *ctx) |
76a66253 | 5374 | { |
fe21b785 RH |
5375 | TCGv d = cpu_gpr[rD(ctx->opcode)]; |
5376 | TCGv a = cpu_gpr[rA(ctx->opcode)]; | |
5377 | ||
5378 | tcg_gen_abs_tl(d, a); | |
5379 | tcg_gen_neg_tl(d, d); | |
22e0e173 | 5380 | /* nabs never overflows */ |
da91a00f | 5381 | tcg_gen_movi_tl(cpu_ov, 0); |
efe843d8 | 5382 | if (unlikely(Rc(ctx->opcode) != 0)) { |
fe21b785 | 5383 | gen_set_Rc0(ctx, d); |
efe843d8 | 5384 | } |
76a66253 JM |
5385 | } |
5386 | ||
5387 | /* rlmi - rlmi. */ | |
99e300ef | 5388 | static void gen_rlmi(DisasContext *ctx) |
76a66253 | 5389 | { |
7487953d AJ |
5390 | uint32_t mb = MB(ctx->opcode); |
5391 | uint32_t me = ME(ctx->opcode); | |
5392 | TCGv t0 = tcg_temp_new(); | |
5393 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5394 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
5395 | tcg_gen_andi_tl(t0, t0, MASK(mb, me)); | |
efe843d8 DG |
5396 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
5397 | ~MASK(mb, me)); | |
7487953d AJ |
5398 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); |
5399 | tcg_temp_free(t0); | |
efe843d8 | 5400 | if (unlikely(Rc(ctx->opcode) != 0)) { |
7487953d | 5401 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 5402 | } |
76a66253 JM |
5403 | } |
5404 | ||
5405 | /* rrib - rrib. */ | |
99e300ef | 5406 | static void gen_rrib(DisasContext *ctx) |
76a66253 | 5407 | { |
7487953d AJ |
5408 | TCGv t0 = tcg_temp_new(); |
5409 | TCGv t1 = tcg_temp_new(); | |
5410 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5411 | tcg_gen_movi_tl(t1, 0x80000000); | |
5412 | tcg_gen_shr_tl(t1, t1, t0); | |
5413 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
5414 | tcg_gen_and_tl(t0, t0, t1); | |
5415 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); | |
5416 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5417 | tcg_temp_free(t0); | |
5418 | tcg_temp_free(t1); | |
efe843d8 | 5419 | if (unlikely(Rc(ctx->opcode) != 0)) { |
7487953d | 5420 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 5421 | } |
76a66253 JM |
5422 | } |
5423 | ||
5424 | /* sle - sle. */ | |
99e300ef | 5425 | static void gen_sle(DisasContext *ctx) |
76a66253 | 5426 | { |
7487953d AJ |
5427 | TCGv t0 = tcg_temp_new(); |
5428 | TCGv t1 = tcg_temp_new(); | |
5429 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5430 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5431 | tcg_gen_subfi_tl(t1, 32, t1); | |
5432 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5433 | tcg_gen_or_tl(t1, t0, t1); | |
5434 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5435 | gen_store_spr(SPR_MQ, t1); | |
5436 | tcg_temp_free(t0); | |
5437 | tcg_temp_free(t1); | |
efe843d8 | 5438 | if (unlikely(Rc(ctx->opcode) != 0)) { |
7487953d | 5439 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 5440 | } |
76a66253 JM |
5441 | } |
5442 | ||
5443 | /* sleq - sleq. */ | |
99e300ef | 5444 | static void gen_sleq(DisasContext *ctx) |
76a66253 | 5445 | { |
7487953d AJ |
5446 | TCGv t0 = tcg_temp_new(); |
5447 | TCGv t1 = tcg_temp_new(); | |
5448 | TCGv t2 = tcg_temp_new(); | |
5449 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5450 | tcg_gen_movi_tl(t2, 0xFFFFFFFF); | |
5451 | tcg_gen_shl_tl(t2, t2, t0); | |
5452 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
5453 | gen_load_spr(t1, SPR_MQ); | |
5454 | gen_store_spr(SPR_MQ, t0); | |
5455 | tcg_gen_and_tl(t0, t0, t2); | |
5456 | tcg_gen_andc_tl(t1, t1, t2); | |
5457 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5458 | tcg_temp_free(t0); | |
5459 | tcg_temp_free(t1); | |
5460 | tcg_temp_free(t2); | |
efe843d8 | 5461 | if (unlikely(Rc(ctx->opcode) != 0)) { |
7487953d | 5462 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 5463 | } |
76a66253 JM |
5464 | } |
5465 | ||
5466 | /* sliq - sliq. */ | |
99e300ef | 5467 | static void gen_sliq(DisasContext *ctx) |
76a66253 | 5468 | { |
7487953d AJ |
5469 | int sh = SH(ctx->opcode); |
5470 | TCGv t0 = tcg_temp_new(); | |
5471 | TCGv t1 = tcg_temp_new(); | |
5472 | tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5473 | tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
5474 | tcg_gen_or_tl(t1, t0, t1); | |
5475 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5476 | gen_store_spr(SPR_MQ, t1); | |
5477 | tcg_temp_free(t0); | |
5478 | tcg_temp_free(t1); | |
efe843d8 | 5479 | if (unlikely(Rc(ctx->opcode) != 0)) { |
7487953d | 5480 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 5481 | } |
76a66253 JM |
5482 | } |
5483 | ||
5484 | /* slliq - slliq. */ | |
99e300ef | 5485 | static void gen_slliq(DisasContext *ctx) |
76a66253 | 5486 | { |
7487953d AJ |
5487 | int sh = SH(ctx->opcode); |
5488 | TCGv t0 = tcg_temp_new(); | |
5489 | TCGv t1 = tcg_temp_new(); | |
5490 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5491 | gen_load_spr(t1, SPR_MQ); | |
5492 | gen_store_spr(SPR_MQ, t0); | |
5493 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); | |
5494 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); | |
5495 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5496 | tcg_temp_free(t0); | |
5497 | tcg_temp_free(t1); | |
efe843d8 | 5498 | if (unlikely(Rc(ctx->opcode) != 0)) { |
7487953d | 5499 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 5500 | } |
76a66253 JM |
5501 | } |
5502 | ||
5503 | /* sllq - sllq. */ | |
99e300ef | 5504 | static void gen_sllq(DisasContext *ctx) |
76a66253 | 5505 | { |
42a268c2 RH |
5506 | TCGLabel *l1 = gen_new_label(); |
5507 | TCGLabel *l2 = gen_new_label(); | |
7487953d AJ |
5508 | TCGv t0 = tcg_temp_local_new(); |
5509 | TCGv t1 = tcg_temp_local_new(); | |
5510 | TCGv t2 = tcg_temp_local_new(); | |
5511 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5512 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5513 | tcg_gen_shl_tl(t1, t1, t2); | |
5514 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5515 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5516 | gen_load_spr(t0, SPR_MQ); | |
5517 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5518 | tcg_gen_br(l2); | |
5519 | gen_set_label(l1); | |
5520 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
5521 | gen_load_spr(t2, SPR_MQ); | |
5522 | tcg_gen_andc_tl(t1, t2, t1); | |
5523 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5524 | gen_set_label(l2); | |
5525 | tcg_temp_free(t0); | |
5526 | tcg_temp_free(t1); | |
5527 | tcg_temp_free(t2); | |
efe843d8 | 5528 | if (unlikely(Rc(ctx->opcode) != 0)) { |
7487953d | 5529 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 5530 | } |
76a66253 JM |
5531 | } |
5532 | ||
5533 | /* slq - slq. */ | |
99e300ef | 5534 | static void gen_slq(DisasContext *ctx) |
76a66253 | 5535 | { |
42a268c2 | 5536 | TCGLabel *l1 = gen_new_label(); |
7487953d AJ |
5537 | TCGv t0 = tcg_temp_new(); |
5538 | TCGv t1 = tcg_temp_new(); | |
5539 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5540 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5541 | tcg_gen_subfi_tl(t1, 32, t1); | |
5542 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5543 | tcg_gen_or_tl(t1, t0, t1); | |
5544 | gen_store_spr(SPR_MQ, t1); | |
5545 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5546 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5547 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); | |
5548 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
5549 | gen_set_label(l1); | |
5550 | tcg_temp_free(t0); | |
5551 | tcg_temp_free(t1); | |
efe843d8 | 5552 | if (unlikely(Rc(ctx->opcode) != 0)) { |
7487953d | 5553 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 5554 | } |
76a66253 JM |
5555 | } |
5556 | ||
d9bce9d9 | 5557 | /* sraiq - sraiq. */ |
99e300ef | 5558 | static void gen_sraiq(DisasContext *ctx) |
76a66253 | 5559 | { |
7487953d | 5560 | int sh = SH(ctx->opcode); |
42a268c2 | 5561 | TCGLabel *l1 = gen_new_label(); |
7487953d AJ |
5562 | TCGv t0 = tcg_temp_new(); |
5563 | TCGv t1 = tcg_temp_new(); | |
5564 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5565 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
5566 | tcg_gen_or_tl(t0, t0, t1); | |
5567 | gen_store_spr(SPR_MQ, t0); | |
da91a00f | 5568 | tcg_gen_movi_tl(cpu_ca, 0); |
7487953d AJ |
5569 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); |
5570 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); | |
da91a00f | 5571 | tcg_gen_movi_tl(cpu_ca, 1); |
7487953d AJ |
5572 | gen_set_label(l1); |
5573 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); | |
5574 | tcg_temp_free(t0); | |
5575 | tcg_temp_free(t1); | |
efe843d8 | 5576 | if (unlikely(Rc(ctx->opcode) != 0)) { |
7487953d | 5577 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 5578 | } |
76a66253 JM |
5579 | } |
5580 | ||
5581 | /* sraq - sraq. */ | |
99e300ef | 5582 | static void gen_sraq(DisasContext *ctx) |
76a66253 | 5583 | { |
42a268c2 RH |
5584 | TCGLabel *l1 = gen_new_label(); |
5585 | TCGLabel *l2 = gen_new_label(); | |
7487953d AJ |
5586 | TCGv t0 = tcg_temp_new(); |
5587 | TCGv t1 = tcg_temp_local_new(); | |
5588 | TCGv t2 = tcg_temp_local_new(); | |
5589 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5590 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
5591 | tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); | |
5592 | tcg_gen_subfi_tl(t2, 32, t2); | |
5593 | tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); | |
5594 | tcg_gen_or_tl(t0, t0, t2); | |
5595 | gen_store_spr(SPR_MQ, t0); | |
5596 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5597 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); | |
5598 | tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); | |
5599 | tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); | |
5600 | gen_set_label(l1); | |
5601 | tcg_temp_free(t0); | |
5602 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); | |
da91a00f | 5603 | tcg_gen_movi_tl(cpu_ca, 0); |
7487953d AJ |
5604 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); |
5605 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); | |
da91a00f | 5606 | tcg_gen_movi_tl(cpu_ca, 1); |
7487953d AJ |
5607 | gen_set_label(l2); |
5608 | tcg_temp_free(t1); | |
5609 | tcg_temp_free(t2); | |
efe843d8 | 5610 | if (unlikely(Rc(ctx->opcode) != 0)) { |
7487953d | 5611 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 5612 | } |
76a66253 JM |
5613 | } |
5614 | ||
5615 | /* sre - sre. */ | |
99e300ef | 5616 | static void gen_sre(DisasContext *ctx) |
76a66253 | 5617 | { |
7487953d AJ |
5618 | TCGv t0 = tcg_temp_new(); |
5619 | TCGv t1 = tcg_temp_new(); | |
5620 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5621 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5622 | tcg_gen_subfi_tl(t1, 32, t1); | |
5623 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5624 | tcg_gen_or_tl(t1, t0, t1); | |
5625 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5626 | gen_store_spr(SPR_MQ, t1); | |
5627 | tcg_temp_free(t0); | |
5628 | tcg_temp_free(t1); | |
efe843d8 | 5629 | if (unlikely(Rc(ctx->opcode) != 0)) { |
7487953d | 5630 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 5631 | } |
76a66253 JM |
5632 | } |
5633 | ||
5634 | /* srea - srea. */ | |
99e300ef | 5635 | static void gen_srea(DisasContext *ctx) |
76a66253 | 5636 | { |
7487953d AJ |
5637 | TCGv t0 = tcg_temp_new(); |
5638 | TCGv t1 = tcg_temp_new(); | |
5639 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5640 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5641 | gen_store_spr(SPR_MQ, t0); | |
5642 | tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); | |
5643 | tcg_temp_free(t0); | |
5644 | tcg_temp_free(t1); | |
efe843d8 | 5645 | if (unlikely(Rc(ctx->opcode) != 0)) { |
7487953d | 5646 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 5647 | } |
76a66253 JM |
5648 | } |
5649 | ||
5650 | /* sreq */ | |
99e300ef | 5651 | static void gen_sreq(DisasContext *ctx) |
76a66253 | 5652 | { |
7487953d AJ |
5653 | TCGv t0 = tcg_temp_new(); |
5654 | TCGv t1 = tcg_temp_new(); | |
5655 | TCGv t2 = tcg_temp_new(); | |
5656 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5657 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5658 | tcg_gen_shr_tl(t1, t1, t0); | |
5659 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
5660 | gen_load_spr(t2, SPR_MQ); | |
5661 | gen_store_spr(SPR_MQ, t0); | |
5662 | tcg_gen_and_tl(t0, t0, t1); | |
5663 | tcg_gen_andc_tl(t2, t2, t1); | |
5664 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); | |
5665 | tcg_temp_free(t0); | |
5666 | tcg_temp_free(t1); | |
5667 | tcg_temp_free(t2); | |
efe843d8 | 5668 | if (unlikely(Rc(ctx->opcode) != 0)) { |
7487953d | 5669 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 5670 | } |
76a66253 JM |
5671 | } |
5672 | ||
5673 | /* sriq */ | |
99e300ef | 5674 | static void gen_sriq(DisasContext *ctx) |
76a66253 | 5675 | { |
7487953d AJ |
5676 | int sh = SH(ctx->opcode); |
5677 | TCGv t0 = tcg_temp_new(); | |
5678 | TCGv t1 = tcg_temp_new(); | |
5679 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5680 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
5681 | tcg_gen_or_tl(t1, t0, t1); | |
5682 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5683 | gen_store_spr(SPR_MQ, t1); | |
5684 | tcg_temp_free(t0); | |
5685 | tcg_temp_free(t1); | |
efe843d8 | 5686 | if (unlikely(Rc(ctx->opcode) != 0)) { |
7487953d | 5687 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 5688 | } |
76a66253 JM |
5689 | } |
5690 | ||
5691 | /* srliq */ | |
99e300ef | 5692 | static void gen_srliq(DisasContext *ctx) |
76a66253 | 5693 | { |
7487953d AJ |
5694 | int sh = SH(ctx->opcode); |
5695 | TCGv t0 = tcg_temp_new(); | |
5696 | TCGv t1 = tcg_temp_new(); | |
5697 | tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5698 | gen_load_spr(t1, SPR_MQ); | |
5699 | gen_store_spr(SPR_MQ, t0); | |
5700 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); | |
5701 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); | |
5702 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5703 | tcg_temp_free(t0); | |
5704 | tcg_temp_free(t1); | |
efe843d8 | 5705 | if (unlikely(Rc(ctx->opcode) != 0)) { |
7487953d | 5706 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 5707 | } |
76a66253 JM |
5708 | } |
5709 | ||
5710 | /* srlq */ | |
99e300ef | 5711 | static void gen_srlq(DisasContext *ctx) |
76a66253 | 5712 | { |
42a268c2 RH |
5713 | TCGLabel *l1 = gen_new_label(); |
5714 | TCGLabel *l2 = gen_new_label(); | |
7487953d AJ |
5715 | TCGv t0 = tcg_temp_local_new(); |
5716 | TCGv t1 = tcg_temp_local_new(); | |
5717 | TCGv t2 = tcg_temp_local_new(); | |
5718 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5719 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5720 | tcg_gen_shr_tl(t2, t1, t2); | |
5721 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5722 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5723 | gen_load_spr(t0, SPR_MQ); | |
5724 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); | |
5725 | tcg_gen_br(l2); | |
5726 | gen_set_label(l1); | |
5727 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
5728 | tcg_gen_and_tl(t0, t0, t2); | |
5729 | gen_load_spr(t1, SPR_MQ); | |
5730 | tcg_gen_andc_tl(t1, t1, t2); | |
5731 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5732 | gen_set_label(l2); | |
5733 | tcg_temp_free(t0); | |
5734 | tcg_temp_free(t1); | |
5735 | tcg_temp_free(t2); | |
efe843d8 | 5736 | if (unlikely(Rc(ctx->opcode) != 0)) { |
7487953d | 5737 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 5738 | } |
76a66253 JM |
5739 | } |
5740 | ||
5741 | /* srq */ | |
99e300ef | 5742 | static void gen_srq(DisasContext *ctx) |
76a66253 | 5743 | { |
42a268c2 | 5744 | TCGLabel *l1 = gen_new_label(); |
7487953d AJ |
5745 | TCGv t0 = tcg_temp_new(); |
5746 | TCGv t1 = tcg_temp_new(); | |
5747 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5748 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5749 | tcg_gen_subfi_tl(t1, 32, t1); | |
5750 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5751 | tcg_gen_or_tl(t1, t0, t1); | |
5752 | gen_store_spr(SPR_MQ, t1); | |
5753 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5754 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5755 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5756 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
5757 | gen_set_label(l1); | |
5758 | tcg_temp_free(t0); | |
5759 | tcg_temp_free(t1); | |
efe843d8 | 5760 | if (unlikely(Rc(ctx->opcode) != 0)) { |
7487953d | 5761 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
efe843d8 | 5762 | } |
76a66253 JM |
5763 | } |
5764 | ||
5765 | /* PowerPC 602 specific instructions */ | |
99e300ef | 5766 | |
54623277 | 5767 | /* dsa */ |
99e300ef | 5768 | static void gen_dsa(DisasContext *ctx) |
76a66253 JM |
5769 | { |
5770 | /* XXX: TODO */ | |
e06fcd75 | 5771 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5772 | } |
5773 | ||
5774 | /* esa */ | |
99e300ef | 5775 | static void gen_esa(DisasContext *ctx) |
76a66253 JM |
5776 | { |
5777 | /* XXX: TODO */ | |
e06fcd75 | 5778 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5779 | } |
5780 | ||
5781 | /* mfrom */ | |
99e300ef | 5782 | static void gen_mfrom(DisasContext *ctx) |
76a66253 JM |
5783 | { |
5784 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5785 | GEN_PRIV; |
76a66253 | 5786 | #else |
9b2fadda | 5787 | CHK_SV; |
cf02a65c | 5788 | gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
9b2fadda | 5789 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5790 | } |
5791 | ||
5792 | /* 602 - 603 - G2 TLB management */ | |
e8eaa2c0 | 5793 | |
54623277 | 5794 | /* tlbld */ |
e8eaa2c0 | 5795 | static void gen_tlbld_6xx(DisasContext *ctx) |
76a66253 JM |
5796 | { |
5797 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5798 | GEN_PRIV; |
76a66253 | 5799 | #else |
9b2fadda | 5800 | CHK_SV; |
c6c7cf05 | 5801 | gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 5802 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5803 | } |
5804 | ||
5805 | /* tlbli */ | |
e8eaa2c0 | 5806 | static void gen_tlbli_6xx(DisasContext *ctx) |
76a66253 JM |
5807 | { |
5808 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5809 | GEN_PRIV; |
76a66253 | 5810 | #else |
9b2fadda | 5811 | CHK_SV; |
c6c7cf05 | 5812 | gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 5813 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5814 | } |
5815 | ||
7dbe11ac | 5816 | /* 74xx TLB management */ |
e8eaa2c0 | 5817 | |
54623277 | 5818 | /* tlbld */ |
e8eaa2c0 | 5819 | static void gen_tlbld_74xx(DisasContext *ctx) |
7dbe11ac JM |
5820 | { |
5821 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5822 | GEN_PRIV; |
7dbe11ac | 5823 | #else |
9b2fadda | 5824 | CHK_SV; |
c6c7cf05 | 5825 | gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 5826 | #endif /* defined(CONFIG_USER_ONLY) */ |
7dbe11ac JM |
5827 | } |
5828 | ||
5829 | /* tlbli */ | |
e8eaa2c0 | 5830 | static void gen_tlbli_74xx(DisasContext *ctx) |
7dbe11ac JM |
5831 | { |
5832 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5833 | GEN_PRIV; |
7dbe11ac | 5834 | #else |
9b2fadda | 5835 | CHK_SV; |
c6c7cf05 | 5836 | gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 5837 | #endif /* defined(CONFIG_USER_ONLY) */ |
7dbe11ac JM |
5838 | } |
5839 | ||
76a66253 | 5840 | /* POWER instructions not in PowerPC 601 */ |
99e300ef | 5841 | |
54623277 | 5842 | /* clf */ |
99e300ef | 5843 | static void gen_clf(DisasContext *ctx) |
76a66253 JM |
5844 | { |
5845 | /* Cache line flush: implemented as no-op */ | |
5846 | } | |
5847 | ||
5848 | /* cli */ | |
99e300ef | 5849 | static void gen_cli(DisasContext *ctx) |
76a66253 | 5850 | { |
76a66253 | 5851 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 5852 | GEN_PRIV; |
76a66253 | 5853 | #else |
9b2fadda BH |
5854 | /* Cache line invalidate: privileged and treated as no-op */ |
5855 | CHK_SV; | |
5856 | #endif /* defined(CONFIG_USER_ONLY) */ | |
76a66253 JM |
5857 | } |
5858 | ||
5859 | /* dclst */ | |
99e300ef | 5860 | static void gen_dclst(DisasContext *ctx) |
76a66253 JM |
5861 | { |
5862 | /* Data cache line store: treated as no-op */ | |
5863 | } | |
5864 | ||
99e300ef | 5865 | static void gen_mfsri(DisasContext *ctx) |
76a66253 JM |
5866 | { |
5867 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5868 | GEN_PRIV; |
76a66253 | 5869 | #else |
74d37793 AJ |
5870 | int ra = rA(ctx->opcode); |
5871 | int rd = rD(ctx->opcode); | |
5872 | TCGv t0; | |
9b2fadda BH |
5873 | |
5874 | CHK_SV; | |
74d37793 | 5875 | t0 = tcg_temp_new(); |
76db3ba4 | 5876 | gen_addr_reg_index(ctx, t0); |
e2622073 | 5877 | tcg_gen_extract_tl(t0, t0, 28, 4); |
c6c7cf05 | 5878 | gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); |
74d37793 | 5879 | tcg_temp_free(t0); |
efe843d8 | 5880 | if (ra != 0 && ra != rd) { |
74d37793 | 5881 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); |
efe843d8 | 5882 | } |
9b2fadda | 5883 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5884 | } |
5885 | ||
99e300ef | 5886 | static void gen_rac(DisasContext *ctx) |
76a66253 JM |
5887 | { |
5888 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5889 | GEN_PRIV; |
76a66253 | 5890 | #else |
22e0e173 | 5891 | TCGv t0; |
9b2fadda BH |
5892 | |
5893 | CHK_SV; | |
22e0e173 | 5894 | t0 = tcg_temp_new(); |
76db3ba4 | 5895 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 5896 | gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
22e0e173 | 5897 | tcg_temp_free(t0); |
9b2fadda | 5898 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5899 | } |
5900 | ||
99e300ef | 5901 | static void gen_rfsvc(DisasContext *ctx) |
76a66253 JM |
5902 | { |
5903 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5904 | GEN_PRIV; |
76a66253 | 5905 | #else |
9b2fadda BH |
5906 | CHK_SV; |
5907 | ||
e5f17ac6 | 5908 | gen_helper_rfsvc(cpu_env); |
e06fcd75 | 5909 | gen_sync_exception(ctx); |
9b2fadda | 5910 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5911 | } |
5912 | ||
f9651121 | 5913 | /* svc is not implemented for now */ |
76a66253 JM |
5914 | |
5915 | /* BookE specific instructions */ | |
99e300ef | 5916 | |
54623277 | 5917 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5918 | static void gen_mfapidi(DisasContext *ctx) |
76a66253 JM |
5919 | { |
5920 | /* XXX: TODO */ | |
e06fcd75 | 5921 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5922 | } |
5923 | ||
2662a059 | 5924 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5925 | static void gen_tlbiva(DisasContext *ctx) |
76a66253 JM |
5926 | { |
5927 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5928 | GEN_PRIV; |
76a66253 | 5929 | #else |
74d37793 | 5930 | TCGv t0; |
9b2fadda BH |
5931 | |
5932 | CHK_SV; | |
ec72e276 | 5933 | t0 = tcg_temp_new(); |
76db3ba4 | 5934 | gen_addr_reg_index(ctx, t0); |
4693364f | 5935 | gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
74d37793 | 5936 | tcg_temp_free(t0); |
9b2fadda | 5937 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5938 | } |
5939 | ||
5940 | /* All 405 MAC instructions are translated here */ | |
636aa200 BS |
5941 | static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, |
5942 | int ra, int rb, int rt, int Rc) | |
76a66253 | 5943 | { |
182608d4 AJ |
5944 | TCGv t0, t1; |
5945 | ||
a7812ae4 PB |
5946 | t0 = tcg_temp_local_new(); |
5947 | t1 = tcg_temp_local_new(); | |
182608d4 | 5948 | |
76a66253 JM |
5949 | switch (opc3 & 0x0D) { |
5950 | case 0x05: | |
5951 | /* macchw - macchw. - macchwo - macchwo. */ | |
5952 | /* macchws - macchws. - macchwso - macchwso. */ | |
5953 | /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ | |
5954 | /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ | |
5955 | /* mulchw - mulchw. */ | |
182608d4 AJ |
5956 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5957 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5958 | tcg_gen_ext16s_tl(t1, t1); | |
76a66253 JM |
5959 | break; |
5960 | case 0x04: | |
5961 | /* macchwu - macchwu. - macchwuo - macchwuo. */ | |
5962 | /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ | |
5963 | /* mulchwu - mulchwu. */ | |
182608d4 AJ |
5964 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5965 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5966 | tcg_gen_ext16u_tl(t1, t1); | |
76a66253 JM |
5967 | break; |
5968 | case 0x01: | |
5969 | /* machhw - machhw. - machhwo - machhwo. */ | |
5970 | /* machhws - machhws. - machhwso - machhwso. */ | |
5971 | /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ | |
5972 | /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ | |
5973 | /* mulhhw - mulhhw. */ | |
182608d4 AJ |
5974 | tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); |
5975 | tcg_gen_ext16s_tl(t0, t0); | |
5976 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5977 | tcg_gen_ext16s_tl(t1, t1); | |
76a66253 JM |
5978 | break; |
5979 | case 0x00: | |
5980 | /* machhwu - machhwu. - machhwuo - machhwuo. */ | |
5981 | /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ | |
5982 | /* mulhhwu - mulhhwu. */ | |
182608d4 AJ |
5983 | tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); |
5984 | tcg_gen_ext16u_tl(t0, t0); | |
5985 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5986 | tcg_gen_ext16u_tl(t1, t1); | |
76a66253 JM |
5987 | break; |
5988 | case 0x0D: | |
5989 | /* maclhw - maclhw. - maclhwo - maclhwo. */ | |
5990 | /* maclhws - maclhws. - maclhwso - maclhwso. */ | |
5991 | /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ | |
5992 | /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ | |
5993 | /* mullhw - mullhw. */ | |
182608d4 AJ |
5994 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5995 | tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); | |
76a66253 JM |
5996 | break; |
5997 | case 0x0C: | |
5998 | /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ | |
5999 | /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ | |
6000 | /* mullhwu - mullhwu. */ | |
182608d4 AJ |
6001 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
6002 | tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); | |
76a66253 JM |
6003 | break; |
6004 | } | |
76a66253 | 6005 | if (opc2 & 0x04) { |
182608d4 AJ |
6006 | /* (n)multiply-and-accumulate (0x0C / 0x0E) */ |
6007 | tcg_gen_mul_tl(t1, t0, t1); | |
6008 | if (opc2 & 0x02) { | |
6009 | /* nmultiply-and-accumulate (0x0E) */ | |
6010 | tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); | |
6011 | } else { | |
6012 | /* multiply-and-accumulate (0x0C) */ | |
6013 | tcg_gen_add_tl(t0, cpu_gpr[rt], t1); | |
6014 | } | |
6015 | ||
6016 | if (opc3 & 0x12) { | |
6017 | /* Check overflow and/or saturate */ | |
42a268c2 | 6018 | TCGLabel *l1 = gen_new_label(); |
182608d4 AJ |
6019 | |
6020 | if (opc3 & 0x10) { | |
6021 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 6022 | tcg_gen_movi_tl(cpu_ov, 0); |
182608d4 AJ |
6023 | } |
6024 | if (opc3 & 0x01) { | |
6025 | /* Signed */ | |
6026 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); | |
6027 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); | |
6028 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); | |
6029 | tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); | |
bdc4e053 | 6030 | if (opc3 & 0x02) { |
182608d4 AJ |
6031 | /* Saturate */ |
6032 | tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); | |
6033 | tcg_gen_xori_tl(t0, t0, 0x7fffffff); | |
6034 | } | |
6035 | } else { | |
6036 | /* Unsigned */ | |
6037 | tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); | |
bdc4e053 | 6038 | if (opc3 & 0x02) { |
182608d4 AJ |
6039 | /* Saturate */ |
6040 | tcg_gen_movi_tl(t0, UINT32_MAX); | |
6041 | } | |
6042 | } | |
6043 | if (opc3 & 0x10) { | |
6044 | /* Check overflow */ | |
da91a00f RH |
6045 | tcg_gen_movi_tl(cpu_ov, 1); |
6046 | tcg_gen_movi_tl(cpu_so, 1); | |
182608d4 AJ |
6047 | } |
6048 | gen_set_label(l1); | |
6049 | tcg_gen_mov_tl(cpu_gpr[rt], t0); | |
6050 | } | |
6051 | } else { | |
6052 | tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); | |
76a66253 | 6053 | } |
182608d4 AJ |
6054 | tcg_temp_free(t0); |
6055 | tcg_temp_free(t1); | |
76a66253 JM |
6056 | if (unlikely(Rc) != 0) { |
6057 | /* Update Rc0 */ | |
182608d4 | 6058 | gen_set_Rc0(ctx, cpu_gpr[rt]); |
76a66253 JM |
6059 | } |
6060 | } | |
6061 | ||
a750fc0b | 6062 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ |
99e300ef | 6063 | static void glue(gen_, name)(DisasContext *ctx) \ |
76a66253 JM |
6064 | { \ |
6065 | gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ | |
6066 | rD(ctx->opcode), Rc(ctx->opcode)); \ | |
6067 | } | |
6068 | ||
6069 | /* macchw - macchw. */ | |
a750fc0b | 6070 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05); |
76a66253 | 6071 | /* macchwo - macchwo. */ |
a750fc0b | 6072 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); |
76a66253 | 6073 | /* macchws - macchws. */ |
a750fc0b | 6074 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07); |
76a66253 | 6075 | /* macchwso - macchwso. */ |
a750fc0b | 6076 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); |
76a66253 | 6077 | /* macchwsu - macchwsu. */ |
a750fc0b | 6078 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); |
76a66253 | 6079 | /* macchwsuo - macchwsuo. */ |
a750fc0b | 6080 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); |
76a66253 | 6081 | /* macchwu - macchwu. */ |
a750fc0b | 6082 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); |
76a66253 | 6083 | /* macchwuo - macchwuo. */ |
a750fc0b | 6084 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); |
76a66253 | 6085 | /* machhw - machhw. */ |
a750fc0b | 6086 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01); |
76a66253 | 6087 | /* machhwo - machhwo. */ |
a750fc0b | 6088 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); |
76a66253 | 6089 | /* machhws - machhws. */ |
a750fc0b | 6090 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03); |
76a66253 | 6091 | /* machhwso - machhwso. */ |
a750fc0b | 6092 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); |
76a66253 | 6093 | /* machhwsu - machhwsu. */ |
a750fc0b | 6094 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); |
76a66253 | 6095 | /* machhwsuo - machhwsuo. */ |
a750fc0b | 6096 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); |
76a66253 | 6097 | /* machhwu - machhwu. */ |
a750fc0b | 6098 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); |
76a66253 | 6099 | /* machhwuo - machhwuo. */ |
a750fc0b | 6100 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); |
76a66253 | 6101 | /* maclhw - maclhw. */ |
a750fc0b | 6102 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); |
76a66253 | 6103 | /* maclhwo - maclhwo. */ |
a750fc0b | 6104 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); |
76a66253 | 6105 | /* maclhws - maclhws. */ |
a750fc0b | 6106 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); |
76a66253 | 6107 | /* maclhwso - maclhwso. */ |
a750fc0b | 6108 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); |
76a66253 | 6109 | /* maclhwu - maclhwu. */ |
a750fc0b | 6110 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); |
76a66253 | 6111 | /* maclhwuo - maclhwuo. */ |
a750fc0b | 6112 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); |
76a66253 | 6113 | /* maclhwsu - maclhwsu. */ |
a750fc0b | 6114 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); |
76a66253 | 6115 | /* maclhwsuo - maclhwsuo. */ |
a750fc0b | 6116 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); |
76a66253 | 6117 | /* nmacchw - nmacchw. */ |
a750fc0b | 6118 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); |
76a66253 | 6119 | /* nmacchwo - nmacchwo. */ |
a750fc0b | 6120 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); |
76a66253 | 6121 | /* nmacchws - nmacchws. */ |
a750fc0b | 6122 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); |
76a66253 | 6123 | /* nmacchwso - nmacchwso. */ |
a750fc0b | 6124 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); |
76a66253 | 6125 | /* nmachhw - nmachhw. */ |
a750fc0b | 6126 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); |
76a66253 | 6127 | /* nmachhwo - nmachhwo. */ |
a750fc0b | 6128 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); |
76a66253 | 6129 | /* nmachhws - nmachhws. */ |
a750fc0b | 6130 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); |
76a66253 | 6131 | /* nmachhwso - nmachhwso. */ |
a750fc0b | 6132 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); |
76a66253 | 6133 | /* nmaclhw - nmaclhw. */ |
a750fc0b | 6134 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); |
76a66253 | 6135 | /* nmaclhwo - nmaclhwo. */ |
a750fc0b | 6136 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); |
76a66253 | 6137 | /* nmaclhws - nmaclhws. */ |
a750fc0b | 6138 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); |
76a66253 | 6139 | /* nmaclhwso - nmaclhwso. */ |
a750fc0b | 6140 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); |
76a66253 JM |
6141 | |
6142 | /* mulchw - mulchw. */ | |
a750fc0b | 6143 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05); |
76a66253 | 6144 | /* mulchwu - mulchwu. */ |
a750fc0b | 6145 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); |
76a66253 | 6146 | /* mulhhw - mulhhw. */ |
a750fc0b | 6147 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); |
76a66253 | 6148 | /* mulhhwu - mulhhwu. */ |
a750fc0b | 6149 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); |
76a66253 | 6150 | /* mullhw - mullhw. */ |
a750fc0b | 6151 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); |
76a66253 | 6152 | /* mullhwu - mullhwu. */ |
a750fc0b | 6153 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); |
76a66253 JM |
6154 | |
6155 | /* mfdcr */ | |
99e300ef | 6156 | static void gen_mfdcr(DisasContext *ctx) |
76a66253 JM |
6157 | { |
6158 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6159 | GEN_PRIV; |
76a66253 | 6160 | #else |
06dca6a7 | 6161 | TCGv dcrn; |
9b2fadda BH |
6162 | |
6163 | CHK_SV; | |
06dca6a7 | 6164 | dcrn = tcg_const_tl(SPR(ctx->opcode)); |
d0f1562d | 6165 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); |
06dca6a7 | 6166 | tcg_temp_free(dcrn); |
9b2fadda | 6167 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
6168 | } |
6169 | ||
6170 | /* mtdcr */ | |
99e300ef | 6171 | static void gen_mtdcr(DisasContext *ctx) |
76a66253 JM |
6172 | { |
6173 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6174 | GEN_PRIV; |
76a66253 | 6175 | #else |
06dca6a7 | 6176 | TCGv dcrn; |
9b2fadda BH |
6177 | |
6178 | CHK_SV; | |
06dca6a7 | 6179 | dcrn = tcg_const_tl(SPR(ctx->opcode)); |
d0f1562d | 6180 | gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); |
06dca6a7 | 6181 | tcg_temp_free(dcrn); |
9b2fadda | 6182 | #endif /* defined(CONFIG_USER_ONLY) */ |
a42bd6cc JM |
6183 | } |
6184 | ||
6185 | /* mfdcrx */ | |
2662a059 | 6186 | /* XXX: not implemented on 440 ? */ |
99e300ef | 6187 | static void gen_mfdcrx(DisasContext *ctx) |
a42bd6cc JM |
6188 | { |
6189 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6190 | GEN_PRIV; |
a42bd6cc | 6191 | #else |
9b2fadda | 6192 | CHK_SV; |
d0f1562d BS |
6193 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6194 | cpu_gpr[rA(ctx->opcode)]); | |
a750fc0b | 6195 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
9b2fadda | 6196 | #endif /* defined(CONFIG_USER_ONLY) */ |
a42bd6cc JM |
6197 | } |
6198 | ||
6199 | /* mtdcrx */ | |
2662a059 | 6200 | /* XXX: not implemented on 440 ? */ |
99e300ef | 6201 | static void gen_mtdcrx(DisasContext *ctx) |
a42bd6cc JM |
6202 | { |
6203 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6204 | GEN_PRIV; |
a42bd6cc | 6205 | #else |
9b2fadda | 6206 | CHK_SV; |
d0f1562d BS |
6207 | gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], |
6208 | cpu_gpr[rS(ctx->opcode)]); | |
a750fc0b | 6209 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
9b2fadda | 6210 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
6211 | } |
6212 | ||
a750fc0b | 6213 | /* mfdcrux (PPC 460) : user-mode access to DCR */ |
99e300ef | 6214 | static void gen_mfdcrux(DisasContext *ctx) |
a750fc0b | 6215 | { |
d0f1562d BS |
6216 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6217 | cpu_gpr[rA(ctx->opcode)]); | |
a750fc0b JM |
6218 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
6219 | } | |
6220 | ||
6221 | /* mtdcrux (PPC 460) : user-mode access to DCR */ | |
99e300ef | 6222 | static void gen_mtdcrux(DisasContext *ctx) |
a750fc0b | 6223 | { |
975e5463 | 6224 | gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], |
d0f1562d | 6225 | cpu_gpr[rS(ctx->opcode)]); |
a750fc0b JM |
6226 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
6227 | } | |
6228 | ||
76a66253 | 6229 | /* dccci */ |
99e300ef | 6230 | static void gen_dccci(DisasContext *ctx) |
76a66253 | 6231 | { |
9b2fadda | 6232 | CHK_SV; |
76a66253 | 6233 | /* interpreted as no-op */ |
76a66253 JM |
6234 | } |
6235 | ||
6236 | /* dcread */ | |
99e300ef | 6237 | static void gen_dcread(DisasContext *ctx) |
76a66253 JM |
6238 | { |
6239 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6240 | GEN_PRIV; |
76a66253 | 6241 | #else |
b61f2753 | 6242 | TCGv EA, val; |
9b2fadda BH |
6243 | |
6244 | CHK_SV; | |
76db3ba4 | 6245 | gen_set_access_type(ctx, ACCESS_CACHE); |
a7812ae4 | 6246 | EA = tcg_temp_new(); |
76db3ba4 | 6247 | gen_addr_reg_index(ctx, EA); |
a7812ae4 | 6248 | val = tcg_temp_new(); |
76db3ba4 | 6249 | gen_qemu_ld32u(ctx, val, EA); |
b61f2753 AJ |
6250 | tcg_temp_free(val); |
6251 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); | |
6252 | tcg_temp_free(EA); | |
9b2fadda | 6253 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
6254 | } |
6255 | ||
6256 | /* icbt */ | |
e8eaa2c0 | 6257 | static void gen_icbt_40x(DisasContext *ctx) |
76a66253 | 6258 | { |
efe843d8 DG |
6259 | /* |
6260 | * interpreted as no-op | |
6261 | * XXX: specification say this is treated as a load by the MMU but | |
6262 | * does not generate any exception | |
76a66253 JM |
6263 | */ |
6264 | } | |
6265 | ||
6266 | /* iccci */ | |
99e300ef | 6267 | static void gen_iccci(DisasContext *ctx) |
76a66253 | 6268 | { |
9b2fadda | 6269 | CHK_SV; |
76a66253 | 6270 | /* interpreted as no-op */ |
76a66253 JM |
6271 | } |
6272 | ||
6273 | /* icread */ | |
99e300ef | 6274 | static void gen_icread(DisasContext *ctx) |
76a66253 | 6275 | { |
9b2fadda | 6276 | CHK_SV; |
76a66253 | 6277 | /* interpreted as no-op */ |
76a66253 JM |
6278 | } |
6279 | ||
c47493f2 | 6280 | /* rfci (supervisor only) */ |
e8eaa2c0 | 6281 | static void gen_rfci_40x(DisasContext *ctx) |
a42bd6cc JM |
6282 | { |
6283 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6284 | GEN_PRIV; |
a42bd6cc | 6285 | #else |
9b2fadda | 6286 | CHK_SV; |
a42bd6cc | 6287 | /* Restore CPU state */ |
e5f17ac6 | 6288 | gen_helper_40x_rfci(cpu_env); |
e06fcd75 | 6289 | gen_sync_exception(ctx); |
9b2fadda | 6290 | #endif /* defined(CONFIG_USER_ONLY) */ |
a42bd6cc JM |
6291 | } |
6292 | ||
99e300ef | 6293 | static void gen_rfci(DisasContext *ctx) |
a42bd6cc JM |
6294 | { |
6295 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6296 | GEN_PRIV; |
a42bd6cc | 6297 | #else |
9b2fadda | 6298 | CHK_SV; |
a42bd6cc | 6299 | /* Restore CPU state */ |
e5f17ac6 | 6300 | gen_helper_rfci(cpu_env); |
e06fcd75 | 6301 | gen_sync_exception(ctx); |
9b2fadda | 6302 | #endif /* defined(CONFIG_USER_ONLY) */ |
a42bd6cc JM |
6303 | } |
6304 | ||
6305 | /* BookE specific */ | |
99e300ef | 6306 | |
54623277 | 6307 | /* XXX: not implemented on 440 ? */ |
99e300ef | 6308 | static void gen_rfdi(DisasContext *ctx) |
76a66253 JM |
6309 | { |
6310 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6311 | GEN_PRIV; |
76a66253 | 6312 | #else |
9b2fadda | 6313 | CHK_SV; |
76a66253 | 6314 | /* Restore CPU state */ |
e5f17ac6 | 6315 | gen_helper_rfdi(cpu_env); |
e06fcd75 | 6316 | gen_sync_exception(ctx); |
9b2fadda | 6317 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
6318 | } |
6319 | ||
2662a059 | 6320 | /* XXX: not implemented on 440 ? */ |
99e300ef | 6321 | static void gen_rfmci(DisasContext *ctx) |
a42bd6cc JM |
6322 | { |
6323 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6324 | GEN_PRIV; |
a42bd6cc | 6325 | #else |
9b2fadda | 6326 | CHK_SV; |
a42bd6cc | 6327 | /* Restore CPU state */ |
e5f17ac6 | 6328 | gen_helper_rfmci(cpu_env); |
e06fcd75 | 6329 | gen_sync_exception(ctx); |
9b2fadda | 6330 | #endif /* defined(CONFIG_USER_ONLY) */ |
a42bd6cc | 6331 | } |
5eb7995e | 6332 | |
d9bce9d9 | 6333 | /* TLB management - PowerPC 405 implementation */ |
e8eaa2c0 | 6334 | |
54623277 | 6335 | /* tlbre */ |
e8eaa2c0 | 6336 | static void gen_tlbre_40x(DisasContext *ctx) |
76a66253 JM |
6337 | { |
6338 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6339 | GEN_PRIV; |
76a66253 | 6340 | #else |
9b2fadda | 6341 | CHK_SV; |
76a66253 JM |
6342 | switch (rB(ctx->opcode)) { |
6343 | case 0: | |
c6c7cf05 BS |
6344 | gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6345 | cpu_gpr[rA(ctx->opcode)]); | |
76a66253 JM |
6346 | break; |
6347 | case 1: | |
c6c7cf05 BS |
6348 | gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6349 | cpu_gpr[rA(ctx->opcode)]); | |
76a66253 JM |
6350 | break; |
6351 | default: | |
e06fcd75 | 6352 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 | 6353 | break; |
9a64fbe4 | 6354 | } |
9b2fadda | 6355 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
6356 | } |
6357 | ||
d9bce9d9 | 6358 | /* tlbsx - tlbsx. */ |
e8eaa2c0 | 6359 | static void gen_tlbsx_40x(DisasContext *ctx) |
76a66253 JM |
6360 | { |
6361 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6362 | GEN_PRIV; |
76a66253 | 6363 | #else |
74d37793 | 6364 | TCGv t0; |
9b2fadda BH |
6365 | |
6366 | CHK_SV; | |
74d37793 | 6367 | t0 = tcg_temp_new(); |
76db3ba4 | 6368 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 6369 | gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 AJ |
6370 | tcg_temp_free(t0); |
6371 | if (Rc(ctx->opcode)) { | |
42a268c2 | 6372 | TCGLabel *l1 = gen_new_label(); |
da91a00f | 6373 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
74d37793 AJ |
6374 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); |
6375 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); | |
6376 | gen_set_label(l1); | |
6377 | } | |
9b2fadda | 6378 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
6379 | } |
6380 | ||
76a66253 | 6381 | /* tlbwe */ |
e8eaa2c0 | 6382 | static void gen_tlbwe_40x(DisasContext *ctx) |
79aceca5 | 6383 | { |
76a66253 | 6384 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 6385 | GEN_PRIV; |
76a66253 | 6386 | #else |
9b2fadda BH |
6387 | CHK_SV; |
6388 | ||
76a66253 JM |
6389 | switch (rB(ctx->opcode)) { |
6390 | case 0: | |
c6c7cf05 BS |
6391 | gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], |
6392 | cpu_gpr[rS(ctx->opcode)]); | |
76a66253 JM |
6393 | break; |
6394 | case 1: | |
c6c7cf05 BS |
6395 | gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], |
6396 | cpu_gpr[rS(ctx->opcode)]); | |
76a66253 JM |
6397 | break; |
6398 | default: | |
e06fcd75 | 6399 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 | 6400 | break; |
9a64fbe4 | 6401 | } |
9b2fadda | 6402 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
6403 | } |
6404 | ||
a4bb6c3e | 6405 | /* TLB management - PowerPC 440 implementation */ |
e8eaa2c0 | 6406 | |
54623277 | 6407 | /* tlbre */ |
e8eaa2c0 | 6408 | static void gen_tlbre_440(DisasContext *ctx) |
5eb7995e JM |
6409 | { |
6410 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6411 | GEN_PRIV; |
5eb7995e | 6412 | #else |
9b2fadda BH |
6413 | CHK_SV; |
6414 | ||
5eb7995e JM |
6415 | switch (rB(ctx->opcode)) { |
6416 | case 0: | |
5eb7995e | 6417 | case 1: |
5eb7995e | 6418 | case 2: |
74d37793 AJ |
6419 | { |
6420 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); | |
c6c7cf05 BS |
6421 | gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6422 | t0, cpu_gpr[rA(ctx->opcode)]); | |
74d37793 AJ |
6423 | tcg_temp_free_i32(t0); |
6424 | } | |
5eb7995e JM |
6425 | break; |
6426 | default: | |
e06fcd75 | 6427 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5eb7995e JM |
6428 | break; |
6429 | } | |
9b2fadda | 6430 | #endif /* defined(CONFIG_USER_ONLY) */ |
5eb7995e JM |
6431 | } |
6432 | ||
6433 | /* tlbsx - tlbsx. */ | |
e8eaa2c0 | 6434 | static void gen_tlbsx_440(DisasContext *ctx) |
5eb7995e JM |
6435 | { |
6436 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6437 | GEN_PRIV; |
5eb7995e | 6438 | #else |
74d37793 | 6439 | TCGv t0; |
9b2fadda BH |
6440 | |
6441 | CHK_SV; | |
74d37793 | 6442 | t0 = tcg_temp_new(); |
76db3ba4 | 6443 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 6444 | gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 AJ |
6445 | tcg_temp_free(t0); |
6446 | if (Rc(ctx->opcode)) { | |
42a268c2 | 6447 | TCGLabel *l1 = gen_new_label(); |
da91a00f | 6448 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
74d37793 AJ |
6449 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); |
6450 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); | |
6451 | gen_set_label(l1); | |
6452 | } | |
9b2fadda | 6453 | #endif /* defined(CONFIG_USER_ONLY) */ |
5eb7995e JM |
6454 | } |
6455 | ||
6456 | /* tlbwe */ | |
e8eaa2c0 | 6457 | static void gen_tlbwe_440(DisasContext *ctx) |
5eb7995e JM |
6458 | { |
6459 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6460 | GEN_PRIV; |
5eb7995e | 6461 | #else |
9b2fadda | 6462 | CHK_SV; |
5eb7995e JM |
6463 | switch (rB(ctx->opcode)) { |
6464 | case 0: | |
5eb7995e | 6465 | case 1: |
5eb7995e | 6466 | case 2: |
74d37793 AJ |
6467 | { |
6468 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); | |
c6c7cf05 BS |
6469 | gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], |
6470 | cpu_gpr[rS(ctx->opcode)]); | |
74d37793 AJ |
6471 | tcg_temp_free_i32(t0); |
6472 | } | |
5eb7995e JM |
6473 | break; |
6474 | default: | |
e06fcd75 | 6475 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5eb7995e JM |
6476 | break; |
6477 | } | |
9b2fadda | 6478 | #endif /* defined(CONFIG_USER_ONLY) */ |
5eb7995e JM |
6479 | } |
6480 | ||
01662f3e AG |
6481 | /* TLB management - PowerPC BookE 2.06 implementation */ |
6482 | ||
6483 | /* tlbre */ | |
6484 | static void gen_tlbre_booke206(DisasContext *ctx) | |
6485 | { | |
9b2fadda BH |
6486 | #if defined(CONFIG_USER_ONLY) |
6487 | GEN_PRIV; | |
01662f3e | 6488 | #else |
9b2fadda | 6489 | CHK_SV; |
c6c7cf05 | 6490 | gen_helper_booke206_tlbre(cpu_env); |
9b2fadda | 6491 | #endif /* defined(CONFIG_USER_ONLY) */ |
01662f3e AG |
6492 | } |
6493 | ||
6494 | /* tlbsx - tlbsx. */ | |
6495 | static void gen_tlbsx_booke206(DisasContext *ctx) | |
6496 | { | |
6497 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6498 | GEN_PRIV; |
01662f3e AG |
6499 | #else |
6500 | TCGv t0; | |
01662f3e | 6501 | |
9b2fadda | 6502 | CHK_SV; |
01662f3e AG |
6503 | if (rA(ctx->opcode)) { |
6504 | t0 = tcg_temp_new(); | |
6505 | tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); | |
6506 | } else { | |
6507 | t0 = tcg_const_tl(0); | |
6508 | } | |
6509 | ||
6510 | tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); | |
c6c7cf05 | 6511 | gen_helper_booke206_tlbsx(cpu_env, t0); |
c80d1df5 | 6512 | tcg_temp_free(t0); |
9b2fadda | 6513 | #endif /* defined(CONFIG_USER_ONLY) */ |
01662f3e AG |
6514 | } |
6515 | ||
6516 | /* tlbwe */ | |
6517 | static void gen_tlbwe_booke206(DisasContext *ctx) | |
6518 | { | |
6519 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6520 | GEN_PRIV; |
01662f3e | 6521 | #else |
9b2fadda | 6522 | CHK_SV; |
c6c7cf05 | 6523 | gen_helper_booke206_tlbwe(cpu_env); |
9b2fadda | 6524 | #endif /* defined(CONFIG_USER_ONLY) */ |
01662f3e AG |
6525 | } |
6526 | ||
6527 | static void gen_tlbivax_booke206(DisasContext *ctx) | |
6528 | { | |
6529 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6530 | GEN_PRIV; |
01662f3e AG |
6531 | #else |
6532 | TCGv t0; | |
01662f3e | 6533 | |
9b2fadda | 6534 | CHK_SV; |
01662f3e AG |
6535 | t0 = tcg_temp_new(); |
6536 | gen_addr_reg_index(ctx, t0); | |
c6c7cf05 | 6537 | gen_helper_booke206_tlbivax(cpu_env, t0); |
c80d1df5 | 6538 | tcg_temp_free(t0); |
9b2fadda | 6539 | #endif /* defined(CONFIG_USER_ONLY) */ |
01662f3e AG |
6540 | } |
6541 | ||
6d3db821 AG |
6542 | static void gen_tlbilx_booke206(DisasContext *ctx) |
6543 | { | |
6544 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6545 | GEN_PRIV; |
6d3db821 AG |
6546 | #else |
6547 | TCGv t0; | |
6d3db821 | 6548 | |
9b2fadda | 6549 | CHK_SV; |
6d3db821 AG |
6550 | t0 = tcg_temp_new(); |
6551 | gen_addr_reg_index(ctx, t0); | |
6552 | ||
efe843d8 | 6553 | switch ((ctx->opcode >> 21) & 0x3) { |
6d3db821 | 6554 | case 0: |
c6c7cf05 | 6555 | gen_helper_booke206_tlbilx0(cpu_env, t0); |
6d3db821 AG |
6556 | break; |
6557 | case 1: | |
c6c7cf05 | 6558 | gen_helper_booke206_tlbilx1(cpu_env, t0); |
6d3db821 AG |
6559 | break; |
6560 | case 3: | |
c6c7cf05 | 6561 | gen_helper_booke206_tlbilx3(cpu_env, t0); |
6d3db821 AG |
6562 | break; |
6563 | default: | |
6564 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
6565 | break; | |
6566 | } | |
6567 | ||
6568 | tcg_temp_free(t0); | |
9b2fadda | 6569 | #endif /* defined(CONFIG_USER_ONLY) */ |
6d3db821 AG |
6570 | } |
6571 | ||
01662f3e | 6572 | |
76a66253 | 6573 | /* wrtee */ |
99e300ef | 6574 | static void gen_wrtee(DisasContext *ctx) |
76a66253 JM |
6575 | { |
6576 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6577 | GEN_PRIV; |
76a66253 | 6578 | #else |
6527f6ea | 6579 | TCGv t0; |
9b2fadda BH |
6580 | |
6581 | CHK_SV; | |
6527f6ea AJ |
6582 | t0 = tcg_temp_new(); |
6583 | tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); | |
6584 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); | |
6585 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
6586 | tcg_temp_free(t0); | |
efe843d8 DG |
6587 | /* |
6588 | * Stop translation to have a chance to raise an exception if we | |
6589 | * just set msr_ee to 1 | |
dee96f6c | 6590 | */ |
e06fcd75 | 6591 | gen_stop_exception(ctx); |
9b2fadda | 6592 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
6593 | } |
6594 | ||
6595 | /* wrteei */ | |
99e300ef | 6596 | static void gen_wrteei(DisasContext *ctx) |
76a66253 JM |
6597 | { |
6598 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6599 | GEN_PRIV; |
76a66253 | 6600 | #else |
9b2fadda | 6601 | CHK_SV; |
fbe73008 | 6602 | if (ctx->opcode & 0x00008000) { |
6527f6ea AJ |
6603 | tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); |
6604 | /* Stop translation to have a chance to raise an exception */ | |
e06fcd75 | 6605 | gen_stop_exception(ctx); |
6527f6ea | 6606 | } else { |
1b6e5f99 | 6607 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); |
6527f6ea | 6608 | } |
9b2fadda | 6609 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
6610 | } |
6611 | ||
08e46e54 | 6612 | /* PowerPC 440 specific instructions */ |
99e300ef | 6613 | |
54623277 | 6614 | /* dlmzb */ |
99e300ef | 6615 | static void gen_dlmzb(DisasContext *ctx) |
76a66253 | 6616 | { |
ef0d51af | 6617 | TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); |
d15f74fb BS |
6618 | gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, |
6619 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); | |
ef0d51af | 6620 | tcg_temp_free_i32(t0); |
76a66253 JM |
6621 | } |
6622 | ||
6623 | /* mbar replaces eieio on 440 */ | |
99e300ef | 6624 | static void gen_mbar(DisasContext *ctx) |
76a66253 JM |
6625 | { |
6626 | /* interpreted as no-op */ | |
6627 | } | |
6628 | ||
6629 | /* msync replaces sync on 440 */ | |
dcb2b9e1 | 6630 | static void gen_msync_4xx(DisasContext *ctx) |
76a66253 | 6631 | { |
27a3ea7e BZ |
6632 | /* Only e500 seems to treat reserved bits as invalid */ |
6633 | if ((ctx->insns_flags2 & PPC2_BOOKE206) && | |
6634 | (ctx->opcode & 0x03FFF801)) { | |
6635 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
6636 | } | |
6637 | /* otherwise interpreted as no-op */ | |
76a66253 JM |
6638 | } |
6639 | ||
6640 | /* icbt */ | |
e8eaa2c0 | 6641 | static void gen_icbt_440(DisasContext *ctx) |
76a66253 | 6642 | { |
efe843d8 DG |
6643 | /* |
6644 | * interpreted as no-op | |
6645 | * XXX: specification say this is treated as a load by the MMU but | |
6646 | * does not generate any exception | |
76a66253 | 6647 | */ |
79aceca5 FB |
6648 | } |
6649 | ||
9e0b5cb1 AG |
6650 | /* Embedded.Processor Control */ |
6651 | ||
6652 | static void gen_msgclr(DisasContext *ctx) | |
6653 | { | |
6654 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6655 | GEN_PRIV; |
9e0b5cb1 | 6656 | #else |
ebca5e6d | 6657 | CHK_HV; |
d0db7cad | 6658 | if (is_book3s_arch2x(ctx)) { |
7af1e7b0 CLG |
6659 | gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
6660 | } else { | |
6661 | gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); | |
6662 | } | |
9b2fadda | 6663 | #endif /* defined(CONFIG_USER_ONLY) */ |
9e0b5cb1 AG |
6664 | } |
6665 | ||
d5d11a39 AG |
6666 | static void gen_msgsnd(DisasContext *ctx) |
6667 | { | |
6668 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6669 | GEN_PRIV; |
d5d11a39 | 6670 | #else |
ebca5e6d | 6671 | CHK_HV; |
d0db7cad | 6672 | if (is_book3s_arch2x(ctx)) { |
7af1e7b0 CLG |
6673 | gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]); |
6674 | } else { | |
6675 | gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); | |
6676 | } | |
9b2fadda | 6677 | #endif /* defined(CONFIG_USER_ONLY) */ |
d5d11a39 AG |
6678 | } |
6679 | ||
5ba7ba1d CLG |
6680 | #if defined(TARGET_PPC64) |
6681 | static void gen_msgclrp(DisasContext *ctx) | |
6682 | { | |
6683 | #if defined(CONFIG_USER_ONLY) | |
6684 | GEN_PRIV; | |
6685 | #else | |
6686 | CHK_SV; | |
6687 | gen_helper_book3s_msgclrp(cpu_env, cpu_gpr[rB(ctx->opcode)]); | |
6688 | #endif /* defined(CONFIG_USER_ONLY) */ | |
6689 | } | |
6690 | ||
6691 | static void gen_msgsndp(DisasContext *ctx) | |
6692 | { | |
6693 | #if defined(CONFIG_USER_ONLY) | |
6694 | GEN_PRIV; | |
6695 | #else | |
6696 | CHK_SV; | |
6697 | gen_helper_book3s_msgsndp(cpu_env, cpu_gpr[rB(ctx->opcode)]); | |
6698 | #endif /* defined(CONFIG_USER_ONLY) */ | |
6699 | } | |
6700 | #endif | |
6701 | ||
7af1e7b0 CLG |
6702 | static void gen_msgsync(DisasContext *ctx) |
6703 | { | |
6704 | #if defined(CONFIG_USER_ONLY) | |
6705 | GEN_PRIV; | |
6706 | #else | |
6707 | CHK_HV; | |
6708 | #endif /* defined(CONFIG_USER_ONLY) */ | |
6709 | /* interpreted as no-op */ | |
6710 | } | |
b04ae981 | 6711 | |
aeeb044c ND |
6712 | #if defined(TARGET_PPC64) |
6713 | static void gen_maddld(DisasContext *ctx) | |
6714 | { | |
6715 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
6716 | ||
6717 | tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
6718 | tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); | |
6719 | tcg_temp_free_i64(t1); | |
6720 | } | |
5f29cc82 ND |
6721 | |
6722 | /* maddhd maddhdu */ | |
6723 | static void gen_maddhd_maddhdu(DisasContext *ctx) | |
6724 | { | |
6725 | TCGv_i64 lo = tcg_temp_new_i64(); | |
6726 | TCGv_i64 hi = tcg_temp_new_i64(); | |
6727 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
6728 | ||
6729 | if (Rc(ctx->opcode)) { | |
6730 | tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], | |
6731 | cpu_gpr[rB(ctx->opcode)]); | |
6732 | tcg_gen_movi_i64(t1, 0); | |
6733 | } else { | |
6734 | tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], | |
6735 | cpu_gpr[rB(ctx->opcode)]); | |
6736 | tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); | |
6737 | } | |
6738 | tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, | |
6739 | cpu_gpr[rC(ctx->opcode)], t1); | |
6740 | tcg_temp_free_i64(lo); | |
6741 | tcg_temp_free_i64(hi); | |
6742 | tcg_temp_free_i64(t1); | |
6743 | } | |
aeeb044c ND |
6744 | #endif /* defined(TARGET_PPC64) */ |
6745 | ||
0ff93d11 TM |
6746 | static void gen_tbegin(DisasContext *ctx) |
6747 | { | |
6748 | if (unlikely(!ctx->tm_enabled)) { | |
6749 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); | |
6750 | return; | |
6751 | } | |
6752 | gen_helper_tbegin(cpu_env); | |
6753 | } | |
6754 | ||
56a84615 TM |
6755 | #define GEN_TM_NOOP(name) \ |
6756 | static inline void gen_##name(DisasContext *ctx) \ | |
6757 | { \ | |
6758 | if (unlikely(!ctx->tm_enabled)) { \ | |
6759 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ | |
6760 | return; \ | |
6761 | } \ | |
efe843d8 DG |
6762 | /* \ |
6763 | * Because tbegin always fails in QEMU, these user \ | |
56a84615 TM |
6764 | * space instructions all have a simple implementation: \ |
6765 | * \ | |
6766 | * CR[0] = 0b0 || MSR[TS] || 0b0 \ | |
6767 | * = 0b0 || 0b00 || 0b0 \ | |
6768 | */ \ | |
6769 | tcg_gen_movi_i32(cpu_crf[0], 0); \ | |
6770 | } | |
6771 | ||
6772 | GEN_TM_NOOP(tend); | |
6773 | GEN_TM_NOOP(tabort); | |
6774 | GEN_TM_NOOP(tabortwc); | |
6775 | GEN_TM_NOOP(tabortwci); | |
6776 | GEN_TM_NOOP(tabortdc); | |
6777 | GEN_TM_NOOP(tabortdci); | |
6778 | GEN_TM_NOOP(tsr); | |
efe843d8 | 6779 | |
b8b4576e SJS |
6780 | static inline void gen_cp_abort(DisasContext *ctx) |
6781 | { | |
efe843d8 | 6782 | /* Do Nothing */ |
b8b4576e | 6783 | } |
56a84615 | 6784 | |
80b8c1ee ND |
6785 | #define GEN_CP_PASTE_NOOP(name) \ |
6786 | static inline void gen_##name(DisasContext *ctx) \ | |
6787 | { \ | |
efe843d8 DG |
6788 | /* \ |
6789 | * Generate invalid exception until we have an \ | |
6790 | * implementation of the copy paste facility \ | |
80b8c1ee ND |
6791 | */ \ |
6792 | gen_invalid(ctx); \ | |
6793 | } | |
6794 | ||
6795 | GEN_CP_PASTE_NOOP(copy) | |
6796 | GEN_CP_PASTE_NOOP(paste) | |
6797 | ||
aeedd582 TM |
6798 | static void gen_tcheck(DisasContext *ctx) |
6799 | { | |
6800 | if (unlikely(!ctx->tm_enabled)) { | |
6801 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); | |
6802 | return; | |
6803 | } | |
efe843d8 DG |
6804 | /* |
6805 | * Because tbegin always fails, the tcheck implementation is | |
6806 | * simple: | |
aeedd582 TM |
6807 | * |
6808 | * CR[CRF] = TDOOMED || MSR[TS] || 0b0 | |
6809 | * = 0b1 || 0b00 || 0b0 | |
6810 | */ | |
6811 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); | |
6812 | } | |
6813 | ||
f83c2378 TM |
6814 | #if defined(CONFIG_USER_ONLY) |
6815 | #define GEN_TM_PRIV_NOOP(name) \ | |
6816 | static inline void gen_##name(DisasContext *ctx) \ | |
6817 | { \ | |
efe843d8 | 6818 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ |
f83c2378 TM |
6819 | } |
6820 | ||
6821 | #else | |
6822 | ||
6823 | #define GEN_TM_PRIV_NOOP(name) \ | |
6824 | static inline void gen_##name(DisasContext *ctx) \ | |
6825 | { \ | |
9b2fadda | 6826 | CHK_SV; \ |
f83c2378 TM |
6827 | if (unlikely(!ctx->tm_enabled)) { \ |
6828 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ | |
6829 | return; \ | |
6830 | } \ | |
efe843d8 DG |
6831 | /* \ |
6832 | * Because tbegin always fails, the implementation is \ | |
f83c2378 TM |
6833 | * simple: \ |
6834 | * \ | |
6835 | * CR[0] = 0b0 || MSR[TS] || 0b0 \ | |
6836 | * = 0b0 || 0b00 | 0b0 \ | |
6837 | */ \ | |
6838 | tcg_gen_movi_i32(cpu_crf[0], 0); \ | |
6839 | } | |
6840 | ||
6841 | #endif | |
6842 | ||
6843 | GEN_TM_PRIV_NOOP(treclaim); | |
6844 | GEN_TM_PRIV_NOOP(trechkpt); | |
6845 | ||
1a404c91 MCA |
6846 | static inline void get_fpr(TCGv_i64 dst, int regno) |
6847 | { | |
e7d3b272 | 6848 | tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); |
1a404c91 MCA |
6849 | } |
6850 | ||
6851 | static inline void set_fpr(int regno, TCGv_i64 src) | |
6852 | { | |
e7d3b272 | 6853 | tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); |
1a404c91 MCA |
6854 | } |
6855 | ||
c4a18dbf MCA |
6856 | static inline void get_avr64(TCGv_i64 dst, int regno, bool high) |
6857 | { | |
37da91f1 | 6858 | tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); |
c4a18dbf MCA |
6859 | } |
6860 | ||
6861 | static inline void set_avr64(int regno, TCGv_i64 src, bool high) | |
6862 | { | |
37da91f1 | 6863 | tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); |
c4a18dbf MCA |
6864 | } |
6865 | ||
139c1837 | 6866 | #include "translate/fp-impl.c.inc" |
15848410 | 6867 | |
139c1837 | 6868 | #include "translate/vmx-impl.c.inc" |
15848410 | 6869 | |
139c1837 | 6870 | #include "translate/vsx-impl.c.inc" |
15848410 | 6871 | |
139c1837 | 6872 | #include "translate/dfp-impl.c.inc" |
15848410 | 6873 | |
139c1837 | 6874 | #include "translate/spe-impl.c.inc" |
15848410 | 6875 | |
5cb091a4 ND |
6876 | /* Handles lfdp, lxsd, lxssp */ |
6877 | static void gen_dform39(DisasContext *ctx) | |
6878 | { | |
6879 | switch (ctx->opcode & 0x3) { | |
6880 | case 0: /* lfdp */ | |
6881 | if (ctx->insns_flags2 & PPC2_ISA205) { | |
6882 | return gen_lfdp(ctx); | |
6883 | } | |
6884 | break; | |
6885 | case 2: /* lxsd */ | |
6886 | if (ctx->insns_flags2 & PPC2_ISA300) { | |
6887 | return gen_lxsd(ctx); | |
6888 | } | |
6889 | break; | |
6890 | case 3: /* lxssp */ | |
6891 | if (ctx->insns_flags2 & PPC2_ISA300) { | |
6892 | return gen_lxssp(ctx); | |
6893 | } | |
6894 | break; | |
6895 | } | |
6896 | return gen_invalid(ctx); | |
6897 | } | |
6898 | ||
d59ba583 | 6899 | /* handles stfdp, lxv, stxsd, stxssp lxvx */ |
e3001664 ND |
6900 | static void gen_dform3D(DisasContext *ctx) |
6901 | { | |
6902 | if ((ctx->opcode & 3) == 1) { /* DQ-FORM */ | |
6903 | switch (ctx->opcode & 0x7) { | |
6904 | case 1: /* lxv */ | |
d59ba583 ND |
6905 | if (ctx->insns_flags2 & PPC2_ISA300) { |
6906 | return gen_lxv(ctx); | |
6907 | } | |
e3001664 ND |
6908 | break; |
6909 | case 5: /* stxv */ | |
d59ba583 ND |
6910 | if (ctx->insns_flags2 & PPC2_ISA300) { |
6911 | return gen_stxv(ctx); | |
6912 | } | |
e3001664 ND |
6913 | break; |
6914 | } | |
6915 | } else { /* DS-FORM */ | |
6916 | switch (ctx->opcode & 0x3) { | |
6917 | case 0: /* stfdp */ | |
6918 | if (ctx->insns_flags2 & PPC2_ISA205) { | |
6919 | return gen_stfdp(ctx); | |
6920 | } | |
6921 | break; | |
6922 | case 2: /* stxsd */ | |
6923 | if (ctx->insns_flags2 & PPC2_ISA300) { | |
6924 | return gen_stxsd(ctx); | |
6925 | } | |
6926 | break; | |
6927 | case 3: /* stxssp */ | |
6928 | if (ctx->insns_flags2 & PPC2_ISA300) { | |
6929 | return gen_stxssp(ctx); | |
6930 | } | |
6931 | break; | |
6932 | } | |
6933 | } | |
6934 | return gen_invalid(ctx); | |
6935 | } | |
6936 | ||
9d69cfa2 LP |
6937 | #if defined(TARGET_PPC64) |
6938 | /* brd */ | |
6939 | static void gen_brd(DisasContext *ctx) | |
6940 | { | |
6941 | tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
6942 | } | |
6943 | ||
6944 | /* brw */ | |
6945 | static void gen_brw(DisasContext *ctx) | |
6946 | { | |
6947 | tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
6948 | tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); | |
6949 | ||
6950 | } | |
6951 | ||
6952 | /* brh */ | |
6953 | static void gen_brh(DisasContext *ctx) | |
6954 | { | |
6955 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
6956 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
6957 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
6958 | ||
6959 | tcg_gen_movi_i64(t0, 0x00ff00ff00ff00ffull); | |
6960 | tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); | |
6961 | tcg_gen_and_i64(t2, t1, t0); | |
6962 | tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], t0); | |
6963 | tcg_gen_shli_i64(t1, t1, 8); | |
6964 | tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); | |
6965 | ||
6966 | tcg_temp_free_i64(t0); | |
6967 | tcg_temp_free_i64(t1); | |
6968 | tcg_temp_free_i64(t2); | |
6969 | } | |
6970 | #endif | |
6971 | ||
c227f099 | 6972 | static opcode_t opcodes[] = { |
9d69cfa2 LP |
6973 | #if defined(TARGET_PPC64) |
6974 | GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), | |
6975 | GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), | |
6976 | GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), | |
6977 | #endif | |
5c55ff99 BS |
6978 | GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), |
6979 | GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), | |
6980 | GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), | |
4aaefd93 | 6981 | GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER), |
5c55ff99 | 6982 | GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), |
082ce330 ND |
6983 | #if defined(TARGET_PPC64) |
6984 | GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), | |
6985 | #endif | |
fcfda20f | 6986 | GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), |
f2442ef9 | 6987 | GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), |
5c55ff99 BS |
6988 | GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), |
6989 | GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6990 | GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6991 | GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6992 | GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
c5b2b9ce | 6993 | GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), |
5c55ff99 BS |
6994 | GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), |
6995 | GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), | |
6996 | GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), | |
6997 | GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), | |
6998 | GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6999 | #if defined(TARGET_PPC64) | |
7000 | GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), | |
7001 | #endif | |
7002 | GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), | |
7003 | GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), | |
7004 | GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
7005 | GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
7006 | GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
7007 | GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), | |
b35344e4 | 7008 | GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), |
80b8c1ee | 7009 | GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), |
b8b4576e | 7010 | GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), |
80b8c1ee | 7011 | GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), |
5c55ff99 BS |
7012 | GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), |
7013 | GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), | |
7014 | GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
7015 | GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
7016 | GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
7017 | GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6ab39b1b | 7018 | GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), |
eaabeef2 | 7019 | GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), |
725bcec2 | 7020 | GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), |
5c55ff99 | 7021 | #if defined(TARGET_PPC64) |
eaabeef2 | 7022 | GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), |
5c55ff99 | 7023 | GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), |
e91d95b2 | 7024 | GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), |
fec5c62a | 7025 | GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), |
725bcec2 | 7026 | GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), |
86ba37ed | 7027 | GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), |
5c55ff99 BS |
7028 | #endif |
7029 | GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
7030 | GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
7031 | GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
7032 | GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), | |
7033 | GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), | |
7034 | GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), | |
7035 | GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), | |
7036 | #if defined(TARGET_PPC64) | |
7037 | GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), | |
7038 | GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), | |
7039 | GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), | |
7040 | GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), | |
7041 | GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), | |
787bbe37 ND |
7042 | GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, |
7043 | PPC_NONE, PPC2_ISA300), | |
7044 | GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, | |
7045 | PPC_NONE, PPC2_ISA300), | |
5c55ff99 | 7046 | #endif |
5c55ff99 BS |
7047 | #if defined(TARGET_PPC64) |
7048 | GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
7049 | GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), | |
7050 | GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
7051 | #endif | |
5cb091a4 ND |
7052 | /* handles lfdp, lxsd, lxssp */ |
7053 | GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), | |
d59ba583 | 7054 | /* handles stfdp, lxv, stxsd, stxssp, stxv */ |
e3001664 | 7055 | GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), |
5c55ff99 BS |
7056 | GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
7057 | GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
7058 | GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), | |
7059 | GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), | |
7060 | GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), | |
7061 | GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), | |
c8fd8373 | 7062 | GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), |
5c55ff99 | 7063 | GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), |
5c77a786 TM |
7064 | GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), |
7065 | GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), | |
f844c817 | 7066 | GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), |
a68a6146 | 7067 | GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), |
a3401188 | 7068 | GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), |
587c51f7 TM |
7069 | GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), |
7070 | GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), | |
5c55ff99 BS |
7071 | GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), |
7072 | #if defined(TARGET_PPC64) | |
a68a6146 | 7073 | GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), |
a3401188 | 7074 | GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), |
f844c817 | 7075 | GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), |
9c294d5a | 7076 | GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), |
5c55ff99 | 7077 | GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), |
27b95bfe | 7078 | GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), |
5c55ff99 BS |
7079 | #endif |
7080 | GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), | |
7081 | GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), | |
c09cec68 | 7082 | GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300), |
5c55ff99 BS |
7083 | GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), |
7084 | GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
7085 | GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), | |
7086 | GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), | |
4aaefd93 | 7087 | GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), |
5c55ff99 BS |
7088 | GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), |
7089 | GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), | |
7090 | #if defined(TARGET_PPC64) | |
7091 | GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), | |
3c89b8d6 NP |
7092 | #if !defined(CONFIG_USER_ONLY) |
7093 | /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ | |
7094 | GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), | |
7095 | GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), | |
7096 | GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), | |
7097 | #endif | |
cdee0e72 | 7098 | GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), |
7778a575 BH |
7099 | GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), |
7100 | GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), | |
7101 | GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), | |
7102 | GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), | |
5c55ff99 BS |
7103 | GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), |
7104 | #endif | |
3c89b8d6 NP |
7105 | /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ |
7106 | GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), | |
7107 | GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), | |
5c55ff99 BS |
7108 | GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), |
7109 | GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
7110 | #if defined(TARGET_PPC64) | |
7111 | GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), | |
7112 | GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
7113 | #endif | |
7114 | GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), | |
7115 | GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), | |
7116 | GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), | |
7117 | GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), | |
7118 | GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), | |
7119 | GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), | |
7120 | #if defined(TARGET_PPC64) | |
7121 | GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), | |
dc2ee038 | 7122 | GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), |
b63d0434 | 7123 | GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), |
5c55ff99 | 7124 | #endif |
5e31867f | 7125 | GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), |
4248b336 | 7126 | GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), |
5c55ff99 | 7127 | GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), |
50728199 | 7128 | GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), |
5c55ff99 BS |
7129 | GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), |
7130 | GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), | |
50728199 | 7131 | GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), |
3f34cf91 | 7132 | GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), |
50728199 | 7133 | GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), |
3f34cf91 | 7134 | GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), |
50728199 | 7135 | GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), |
4d09d529 | 7136 | GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), |
8e33944f | 7137 | GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), |
50728199 | 7138 | GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), |
5c55ff99 | 7139 | GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), |
99d45f8f | 7140 | GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), |
5c55ff99 BS |
7141 | GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), |
7142 | GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), | |
50728199 | 7143 | GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), |
5c55ff99 BS |
7144 | GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), |
7145 | GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), | |
7146 | GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), | |
7147 | GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), | |
7148 | GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), | |
7149 | #if defined(TARGET_PPC64) | |
7150 | GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), | |
7151 | GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, | |
7152 | PPC_SEGMENT_64B), | |
7153 | GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), | |
7154 | GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, | |
7155 | PPC_SEGMENT_64B), | |
efdef95f DG |
7156 | GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), |
7157 | GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), | |
7158 | GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), | |
c76c22d5 | 7159 | GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), |
5c55ff99 BS |
7160 | #endif |
7161 | GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), | |
efe843d8 DG |
7162 | /* |
7163 | * XXX Those instructions will need to be handled differently for | |
7164 | * different ISA versions | |
7165 | */ | |
f9ef0527 BH |
7166 | GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), |
7167 | GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), | |
c8830502 SJS |
7168 | GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300), |
7169 | GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300), | |
5c55ff99 BS |
7170 | GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), |
7171 | #if defined(TARGET_PPC64) | |
2f9254d9 | 7172 | GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), |
5c55ff99 | 7173 | GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), |
a63f1dfc | 7174 | GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300), |
62d897ca | 7175 | GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300), |
5c55ff99 BS |
7176 | #endif |
7177 | GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), | |
7178 | GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), | |
7179 | GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), | |
7180 | GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), | |
7181 | GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), | |
7182 | GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), | |
7183 | GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), | |
7184 | GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), | |
7185 | GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), | |
7186 | GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), | |
7187 | GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), | |
7188 | GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), | |
7189 | GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), | |
7190 | GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), | |
7191 | GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), | |
7192 | GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), | |
7193 | GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), | |
7194 | GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), | |
7195 | GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), | |
7196 | GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), | |
7197 | GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), | |
7198 | GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), | |
7199 | GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), | |
7200 | GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), | |
7201 | GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), | |
7202 | GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), | |
7203 | GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), | |
7204 | GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), | |
7205 | GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), | |
7206 | GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), | |
7207 | GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), | |
7208 | GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), | |
7209 | GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), | |
7210 | GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), | |
7211 | GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), | |
7212 | GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), | |
7213 | GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), | |
7214 | GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), | |
7215 | GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), | |
7216 | GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), | |
7217 | GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), | |
7218 | GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), | |
7219 | GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), | |
7220 | GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), | |
7221 | GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), | |
7222 | GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), | |
7223 | GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), | |
7224 | GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), | |
7225 | GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), | |
7226 | GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
7227 | GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
7228 | GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), | |
7229 | GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), | |
7230 | GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
7231 | GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
7232 | GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), | |
7233 | GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), | |
7234 | GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), | |
7235 | GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), | |
7236 | GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), | |
7237 | GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), | |
7238 | GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), | |
7239 | GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), | |
7240 | GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), | |
7241 | GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), | |
7242 | GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), | |
7243 | GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), | |
7244 | GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), | |
7245 | GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), | |
7246 | GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), | |
7247 | GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), | |
01662f3e | 7248 | GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), |
5c55ff99 BS |
7249 | GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), |
7250 | GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), | |
7251 | GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), | |
7252 | GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), | |
7253 | GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), | |
7254 | GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), | |
7255 | GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), | |
7256 | GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), | |
01662f3e AG |
7257 | GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, |
7258 | PPC_NONE, PPC2_BOOKE206), | |
7259 | GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, | |
7260 | PPC_NONE, PPC2_BOOKE206), | |
7261 | GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, | |
7262 | PPC_NONE, PPC2_BOOKE206), | |
7263 | GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, | |
7264 | PPC_NONE, PPC2_BOOKE206), | |
6d3db821 AG |
7265 | GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, |
7266 | PPC_NONE, PPC2_BOOKE206), | |
d5d11a39 AG |
7267 | GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, |
7268 | PPC_NONE, PPC2_PRCNTL), | |
9e0b5cb1 AG |
7269 | GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, |
7270 | PPC_NONE, PPC2_PRCNTL), | |
7af1e7b0 CLG |
7271 | GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000, |
7272 | PPC_NONE, PPC2_PRCNTL), | |
5c55ff99 | 7273 | GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), |
fbe73008 | 7274 | GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), |
5c55ff99 | 7275 | GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), |
01662f3e AG |
7276 | GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, |
7277 | PPC_BOOKE, PPC2_BOOKE206), | |
27a3ea7e | 7278 | GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), |
01662f3e AG |
7279 | GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, |
7280 | PPC_BOOKE, PPC2_BOOKE206), | |
0c8d8c8b | 7281 | GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, |
27a3ea7e | 7282 | PPC_440_SPEC), |
5c55ff99 BS |
7283 | GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), |
7284 | GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), | |
7285 | GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), | |
7286 | GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), | |
5c55ff99 | 7287 | GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), |
aeeb044c | 7288 | #if defined(TARGET_PPC64) |
5f29cc82 ND |
7289 | GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, |
7290 | PPC2_ISA300), | |
aeeb044c | 7291 | GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), |
5ba7ba1d CLG |
7292 | GEN_HANDLER2_E(msgsndp, "msgsndp", 0x1F, 0x0E, 0x04, 0x03ff0001, |
7293 | PPC_NONE, PPC2_ISA207S), | |
7294 | GEN_HANDLER2_E(msgclrp, "msgclrp", 0x1F, 0x0E, 0x05, 0x03ff0001, | |
7295 | PPC_NONE, PPC2_ISA207S), | |
aeeb044c | 7296 | #endif |
5c55ff99 BS |
7297 | |
7298 | #undef GEN_INT_ARITH_ADD | |
7299 | #undef GEN_INT_ARITH_ADD_CONST | |
7300 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ | |
7301 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), | |
7302 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ | |
7303 | add_ca, compute_ca, compute_ov) \ | |
7304 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), | |
7305 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) | |
7306 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) | |
7307 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) | |
7308 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) | |
7309 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) | |
7310 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) | |
7311 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) | |
7312 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) | |
4c5920af | 7313 | GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), |
5c55ff99 BS |
7314 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) |
7315 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) | |
7316 | ||
7317 | #undef GEN_INT_ARITH_DIVW | |
7318 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ | |
7319 | GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) | |
7320 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), | |
7321 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), | |
7322 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), | |
7323 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), | |
a98eb9e9 TM |
7324 | GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), |
7325 | GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
6a4fda33 TM |
7326 | GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), |
7327 | GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
af2c6620 ND |
7328 | GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), |
7329 | GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), | |
5c55ff99 BS |
7330 | |
7331 | #if defined(TARGET_PPC64) | |
7332 | #undef GEN_INT_ARITH_DIVD | |
7333 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ | |
7334 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) | |
7335 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), | |
7336 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), | |
7337 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), | |
7338 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), | |
7339 | ||
98d1eb27 TM |
7340 | GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), |
7341 | GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
e44259b6 TM |
7342 | GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), |
7343 | GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
063cf14f ND |
7344 | GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), |
7345 | GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), | |
98d1eb27 | 7346 | |
5c55ff99 BS |
7347 | #undef GEN_INT_ARITH_MUL_HELPER |
7348 | #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ | |
7349 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) | |
7350 | GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), | |
7351 | GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), | |
7352 | GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), | |
7353 | #endif | |
7354 | ||
7355 | #undef GEN_INT_ARITH_SUBF | |
7356 | #undef GEN_INT_ARITH_SUBF_CONST | |
7357 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ | |
7358 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), | |
7359 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ | |
7360 | add_ca, compute_ca, compute_ov) \ | |
7361 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), | |
7362 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) | |
7363 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) | |
7364 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) | |
7365 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) | |
7366 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) | |
7367 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) | |
7368 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) | |
7369 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) | |
7370 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) | |
7371 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) | |
7372 | ||
7373 | #undef GEN_LOGICAL1 | |
7374 | #undef GEN_LOGICAL2 | |
7375 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ | |
7376 | GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) | |
7377 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ | |
7378 | GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) | |
7379 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), | |
7380 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), | |
7381 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), | |
7382 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), | |
7383 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), | |
7384 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), | |
7385 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), | |
7386 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), | |
7387 | #if defined(TARGET_PPC64) | |
7388 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), | |
7389 | #endif | |
7390 | ||
7391 | #if defined(TARGET_PPC64) | |
7392 | #undef GEN_PPC64_R2 | |
7393 | #undef GEN_PPC64_R4 | |
7394 | #define GEN_PPC64_R2(name, opc1, opc2) \ | |
7395 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ | |
7396 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ | |
7397 | PPC_64B) | |
7398 | #define GEN_PPC64_R4(name, opc1, opc2) \ | |
7399 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ | |
7400 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ | |
7401 | PPC_64B), \ | |
7402 | GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ | |
7403 | PPC_64B), \ | |
7404 | GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ | |
7405 | PPC_64B) | |
7406 | GEN_PPC64_R4(rldicl, 0x1E, 0x00), | |
7407 | GEN_PPC64_R4(rldicr, 0x1E, 0x02), | |
7408 | GEN_PPC64_R4(rldic, 0x1E, 0x04), | |
7409 | GEN_PPC64_R2(rldcl, 0x1E, 0x08), | |
7410 | GEN_PPC64_R2(rldcr, 0x1E, 0x09), | |
7411 | GEN_PPC64_R4(rldimi, 0x1E, 0x06), | |
7412 | #endif | |
7413 | ||
5c55ff99 BS |
7414 | #undef GEN_LD |
7415 | #undef GEN_LDU | |
7416 | #undef GEN_LDUX | |
cd6e9320 | 7417 | #undef GEN_LDX_E |
5c55ff99 BS |
7418 | #undef GEN_LDS |
7419 | #define GEN_LD(name, ldop, opc, type) \ | |
7420 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
7421 | #define GEN_LDU(name, ldop, opc, type) \ | |
7422 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
7423 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \ | |
7424 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), | |
b7815375 | 7425 | #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ |
cd6e9320 | 7426 | GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), |
5c55ff99 BS |
7427 | #define GEN_LDS(name, ldop, op, type) \ |
7428 | GEN_LD(name, ldop, op | 0x20, type) \ | |
7429 | GEN_LDU(name, ldop, op | 0x21, type) \ | |
7430 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ | |
7431 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) | |
7432 | ||
7433 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) | |
7434 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) | |
7435 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) | |
7436 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) | |
7437 | #if defined(TARGET_PPC64) | |
7438 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) | |
7439 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) | |
4f364fe7 ND |
7440 | GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B) |
7441 | GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B) | |
ff5f3981 | 7442 | GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) |
b7815375 BH |
7443 | |
7444 | /* HV/P7 and later only */ | |
4f364fe7 | 7445 | GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) |
b7815375 BH |
7446 | GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) |
7447 | GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) | |
7448 | GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) | |
5c55ff99 BS |
7449 | #endif |
7450 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) | |
7451 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) | |
7452 | ||
50728199 RK |
7453 | /* External PID based load */ |
7454 | #undef GEN_LDEPX | |
7455 | #define GEN_LDEPX(name, ldop, opc2, opc3) \ | |
7456 | GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ | |
7457 | 0x00000001, PPC_NONE, PPC2_BOOKE206), | |
7458 | ||
7459 | GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) | |
7460 | GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) | |
7461 | GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) | |
7462 | #if defined(TARGET_PPC64) | |
7463 | GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) | |
7464 | #endif | |
7465 | ||
5c55ff99 BS |
7466 | #undef GEN_ST |
7467 | #undef GEN_STU | |
7468 | #undef GEN_STUX | |
cd6e9320 | 7469 | #undef GEN_STX_E |
5c55ff99 BS |
7470 | #undef GEN_STS |
7471 | #define GEN_ST(name, stop, opc, type) \ | |
7472 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
7473 | #define GEN_STU(name, stop, opc, type) \ | |
7474 | GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
7475 | #define GEN_STUX(name, stop, opc2, opc3, type) \ | |
7476 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), | |
b7815375 | 7477 | #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ |
0123d3cb | 7478 | GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), |
5c55ff99 BS |
7479 | #define GEN_STS(name, stop, op, type) \ |
7480 | GEN_ST(name, stop, op | 0x20, type) \ | |
7481 | GEN_STU(name, stop, op | 0x21, type) \ | |
7482 | GEN_STUX(name, stop, 0x17, op | 0x01, type) \ | |
7483 | GEN_STX(name, stop, 0x17, op | 0x00, type) | |
7484 | ||
7485 | GEN_STS(stb, st8, 0x06, PPC_INTEGER) | |
7486 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER) | |
7487 | GEN_STS(stw, st32, 0x04, PPC_INTEGER) | |
7488 | #if defined(TARGET_PPC64) | |
2468f23d ND |
7489 | GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B) |
7490 | GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B) | |
804108aa | 7491 | GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) |
2468f23d | 7492 | GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) |
b7815375 BH |
7493 | GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) |
7494 | GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) | |
7495 | GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) | |
5c55ff99 BS |
7496 | #endif |
7497 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) | |
7498 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) | |
7499 | ||
50728199 RK |
7500 | #undef GEN_STEPX |
7501 | #define GEN_STEPX(name, ldop, opc2, opc3) \ | |
7502 | GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ | |
7503 | 0x00000001, PPC_NONE, PPC2_BOOKE206), | |
7504 | ||
7505 | GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) | |
7506 | GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) | |
7507 | GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) | |
7508 | #if defined(TARGET_PPC64) | |
7509 | GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1D, 0x04) | |
7510 | #endif | |
7511 | ||
5c55ff99 BS |
7512 | #undef GEN_CRLOGIC |
7513 | #define GEN_CRLOGIC(name, tcg_op, opc) \ | |
7514 | GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) | |
7515 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), | |
7516 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), | |
7517 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), | |
7518 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), | |
7519 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), | |
7520 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), | |
7521 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), | |
7522 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), | |
7523 | ||
7524 | #undef GEN_MAC_HANDLER | |
7525 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ | |
7526 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) | |
7527 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05), | |
7528 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), | |
7529 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07), | |
7530 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), | |
7531 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), | |
7532 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), | |
7533 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), | |
7534 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), | |
7535 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01), | |
7536 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), | |
7537 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03), | |
7538 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), | |
7539 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), | |
7540 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), | |
7541 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), | |
7542 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), | |
7543 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), | |
7544 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), | |
7545 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), | |
7546 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), | |
7547 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), | |
7548 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), | |
7549 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), | |
7550 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), | |
7551 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), | |
7552 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), | |
7553 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), | |
7554 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), | |
7555 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), | |
7556 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), | |
7557 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), | |
7558 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), | |
7559 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), | |
7560 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), | |
7561 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), | |
7562 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), | |
7563 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05), | |
7564 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), | |
7565 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), | |
7566 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), | |
7567 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), | |
7568 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), | |
7569 | ||
0ff93d11 TM |
7570 | GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ |
7571 | PPC_NONE, PPC2_TM), | |
56a84615 TM |
7572 | GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ |
7573 | PPC_NONE, PPC2_TM), | |
7574 | GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ | |
7575 | PPC_NONE, PPC2_TM), | |
7576 | GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ | |
7577 | PPC_NONE, PPC2_TM), | |
7578 | GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ | |
7579 | PPC_NONE, PPC2_TM), | |
7580 | GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ | |
7581 | PPC_NONE, PPC2_TM), | |
7582 | GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ | |
7583 | PPC_NONE, PPC2_TM), | |
7584 | GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ | |
7585 | PPC_NONE, PPC2_TM), | |
aeedd582 TM |
7586 | GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ |
7587 | PPC_NONE, PPC2_TM), | |
f83c2378 TM |
7588 | GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ |
7589 | PPC_NONE, PPC2_TM), | |
7590 | GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ | |
7591 | PPC_NONE, PPC2_TM), | |
15848410 | 7592 | |
139c1837 | 7593 | #include "translate/fp-ops.c.inc" |
15848410 | 7594 | |
139c1837 | 7595 | #include "translate/vmx-ops.c.inc" |
15848410 | 7596 | |
139c1837 | 7597 | #include "translate/vsx-ops.c.inc" |
15848410 | 7598 | |
139c1837 | 7599 | #include "translate/dfp-ops.c.inc" |
15848410 | 7600 | |
139c1837 | 7601 | #include "translate/spe-ops.c.inc" |
5c55ff99 BS |
7602 | }; |
7603 | ||
0411a972 | 7604 | #include "helper_regs.h" |
139c1837 | 7605 | #include "translate_init.c.inc" |
79aceca5 | 7606 | |
9a64fbe4 | 7607 | /*****************************************************************************/ |
3fc6c082 | 7608 | /* Misc PowerPC helpers */ |
90c84c56 | 7609 | void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) |
79aceca5 | 7610 | { |
3fc6c082 FB |
7611 | #define RGPL 4 |
7612 | #define RFPL 4 | |
3fc6c082 | 7613 | |
878096ee AF |
7614 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
7615 | CPUPPCState *env = &cpu->env; | |
79aceca5 FB |
7616 | int i; |
7617 | ||
90c84c56 MA |
7618 | qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " |
7619 | TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", | |
7620 | env->nip, env->lr, env->ctr, cpu_read_xer(env), | |
7621 | cs->cpu_index); | |
7622 | qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " | |
26c55599 | 7623 | "%08x iidx %d didx %d\n", |
d764184d RH |
7624 | env->msr, env->spr[SPR_HID0], env->hflags, |
7625 | cpu_mmu_index(env, true), cpu_mmu_index(env, false)); | |
d9bce9d9 | 7626 | #if !defined(NO_TIMER_DUMP) |
90c84c56 | 7627 | qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 |
76a66253 | 7628 | #if !defined(CONFIG_USER_ONLY) |
90c84c56 | 7629 | " DECR " TARGET_FMT_lu |
76a66253 | 7630 | #endif |
90c84c56 MA |
7631 | "\n", |
7632 | cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) | |
76a66253 | 7633 | #if !defined(CONFIG_USER_ONLY) |
90c84c56 | 7634 | , cpu_ppc_load_decr(env) |
76a66253 | 7635 | #endif |
90c84c56 | 7636 | ); |
077fc206 | 7637 | #endif |
76a66253 | 7638 | for (i = 0; i < 32; i++) { |
efe843d8 | 7639 | if ((i & (RGPL - 1)) == 0) { |
90c84c56 | 7640 | qemu_fprintf(f, "GPR%02d", i); |
efe843d8 | 7641 | } |
90c84c56 | 7642 | qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); |
efe843d8 | 7643 | if ((i & (RGPL - 1)) == (RGPL - 1)) { |
90c84c56 | 7644 | qemu_fprintf(f, "\n"); |
efe843d8 | 7645 | } |
76a66253 | 7646 | } |
90c84c56 | 7647 | qemu_fprintf(f, "CR "); |
76a66253 | 7648 | for (i = 0; i < 8; i++) |
90c84c56 MA |
7649 | qemu_fprintf(f, "%01x", env->crf[i]); |
7650 | qemu_fprintf(f, " ["); | |
76a66253 JM |
7651 | for (i = 0; i < 8; i++) { |
7652 | char a = '-'; | |
efe843d8 | 7653 | if (env->crf[i] & 0x08) { |
76a66253 | 7654 | a = 'L'; |
efe843d8 | 7655 | } else if (env->crf[i] & 0x04) { |
76a66253 | 7656 | a = 'G'; |
efe843d8 | 7657 | } else if (env->crf[i] & 0x02) { |
76a66253 | 7658 | a = 'E'; |
efe843d8 | 7659 | } |
90c84c56 | 7660 | qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); |
76a66253 | 7661 | } |
90c84c56 MA |
7662 | qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", |
7663 | env->reserve_addr); | |
685f1ce2 RH |
7664 | |
7665 | if (flags & CPU_DUMP_FPU) { | |
7666 | for (i = 0; i < 32; i++) { | |
7667 | if ((i & (RFPL - 1)) == 0) { | |
90c84c56 | 7668 | qemu_fprintf(f, "FPR%02d", i); |
685f1ce2 | 7669 | } |
90c84c56 | 7670 | qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i)); |
685f1ce2 | 7671 | if ((i & (RFPL - 1)) == (RFPL - 1)) { |
90c84c56 | 7672 | qemu_fprintf(f, "\n"); |
685f1ce2 RH |
7673 | } |
7674 | } | |
90c84c56 | 7675 | qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); |
79aceca5 | 7676 | } |
685f1ce2 | 7677 | |
f2e63a42 | 7678 | #if !defined(CONFIG_USER_ONLY) |
90c84c56 MA |
7679 | qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx |
7680 | " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", | |
7681 | env->spr[SPR_SRR0], env->spr[SPR_SRR1], | |
7682 | env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); | |
90dc8812 | 7683 | |
90c84c56 MA |
7684 | qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx |
7685 | " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", | |
7686 | env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], | |
7687 | env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); | |
90dc8812 | 7688 | |
90c84c56 MA |
7689 | qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx |
7690 | " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", | |
7691 | env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], | |
7692 | env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); | |
90dc8812 | 7693 | |
f2b70fde BH |
7694 | #if defined(TARGET_PPC64) |
7695 | if (env->excp_model == POWERPC_EXCP_POWER7 || | |
a790e82b | 7696 | env->excp_model == POWERPC_EXCP_POWER8 || |
526cdce7 NP |
7697 | env->excp_model == POWERPC_EXCP_POWER9 || |
7698 | env->excp_model == POWERPC_EXCP_POWER10) { | |
90c84c56 MA |
7699 | qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", |
7700 | env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); | |
f2b70fde BH |
7701 | } |
7702 | #endif | |
90dc8812 | 7703 | if (env->excp_model == POWERPC_EXCP_BOOKE) { |
90c84c56 MA |
7704 | qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx |
7705 | " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", | |
7706 | env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], | |
7707 | env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); | |
7708 | ||
7709 | qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx | |
7710 | " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", | |
7711 | env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], | |
7712 | env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); | |
7713 | ||
7714 | qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx | |
7715 | " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", | |
7716 | env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], | |
7717 | env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); | |
7718 | ||
7719 | qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx | |
7720 | " EPR " TARGET_FMT_lx "\n", | |
7721 | env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], | |
7722 | env->spr[SPR_BOOKE_EPR]); | |
90dc8812 SW |
7723 | |
7724 | /* FSL-specific */ | |
90c84c56 MA |
7725 | qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx |
7726 | " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", | |
7727 | env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], | |
7728 | env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); | |
90dc8812 SW |
7729 | |
7730 | /* | |
7731 | * IVORs are left out as they are large and do not change often -- | |
7732 | * they can be read with "p $ivor0", "p $ivor1", etc. | |
7733 | */ | |
7734 | } | |
7735 | ||
697ab892 DG |
7736 | #if defined(TARGET_PPC64) |
7737 | if (env->flags & POWERPC_FLAG_CFAR) { | |
90c84c56 | 7738 | qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); |
697ab892 DG |
7739 | } |
7740 | #endif | |
7741 | ||
efe843d8 | 7742 | if (env->spr_cb[SPR_LPCR].name) { |
90c84c56 | 7743 | qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); |
efe843d8 | 7744 | } |
d801a61e | 7745 | |
0941d728 | 7746 | switch (env->mmu_model) { |
90dc8812 SW |
7747 | case POWERPC_MMU_32B: |
7748 | case POWERPC_MMU_601: | |
7749 | case POWERPC_MMU_SOFT_6xx: | |
7750 | case POWERPC_MMU_SOFT_74xx: | |
7751 | #if defined(TARGET_PPC64) | |
0941d728 DG |
7752 | case POWERPC_MMU_64B: |
7753 | case POWERPC_MMU_2_03: | |
7754 | case POWERPC_MMU_2_06: | |
7755 | case POWERPC_MMU_2_07: | |
7756 | case POWERPC_MMU_3_00: | |
90dc8812 | 7757 | #endif |
4f4f28ff | 7758 | if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ |
90c84c56 | 7759 | qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); |
4f4f28ff | 7760 | } |
4a7518e0 | 7761 | if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ |
90c84c56 | 7762 | qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); |
4a7518e0 | 7763 | } |
90c84c56 MA |
7764 | qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", |
7765 | env->spr[SPR_DAR], env->spr[SPR_DSISR]); | |
90dc8812 | 7766 | break; |
01662f3e | 7767 | case POWERPC_MMU_BOOKE206: |
90c84c56 MA |
7768 | qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx |
7769 | " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", | |
7770 | env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], | |
7771 | env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); | |
7772 | ||
7773 | qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx | |
7774 | " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", | |
7775 | env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], | |
7776 | env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); | |
7777 | ||
7778 | qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx | |
7779 | " TLB1CFG " TARGET_FMT_lx "\n", | |
7780 | env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], | |
7781 | env->spr[SPR_BOOKE_TLB1CFG]); | |
90dc8812 SW |
7782 | break; |
7783 | default: | |
7784 | break; | |
7785 | } | |
f2e63a42 | 7786 | #endif |
79aceca5 | 7787 | |
3fc6c082 FB |
7788 | #undef RGPL |
7789 | #undef RFPL | |
79aceca5 FB |
7790 | } |
7791 | ||
7468e2c8 BL |
7792 | /*****************************************************************************/ |
7793 | /* Opcode types */ | |
7794 | enum { | |
7795 | PPC_DIRECT = 0, /* Opcode routine */ | |
7796 | PPC_INDIRECT = 1, /* Indirect opcode table */ | |
7797 | }; | |
7798 | ||
7799 | #define PPC_OPCODE_MASK 0x3 | |
7800 | ||
7801 | static inline int is_indirect_opcode(void *handler) | |
7802 | { | |
7803 | return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; | |
7804 | } | |
7805 | ||
7806 | static inline opc_handler_t **ind_table(void *handler) | |
7807 | { | |
7808 | return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); | |
7809 | } | |
7810 | ||
7811 | /* Instruction table creation */ | |
7812 | /* Opcodes tables creation */ | |
7813 | static void fill_new_table(opc_handler_t **table, int len) | |
7814 | { | |
7815 | int i; | |
7816 | ||
7817 | for (i = 0; i < len; i++) { | |
7818 | table[i] = &invalid_handler; | |
7819 | } | |
7820 | } | |
7821 | ||
7822 | static int create_new_table(opc_handler_t **table, unsigned char idx) | |
7823 | { | |
7824 | opc_handler_t **tmp; | |
7825 | ||
7826 | tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); | |
7827 | fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); | |
7828 | table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); | |
7829 | ||
7830 | return 0; | |
7831 | } | |
7832 | ||
7833 | static int insert_in_table(opc_handler_t **table, unsigned char idx, | |
7834 | opc_handler_t *handler) | |
7835 | { | |
7836 | if (table[idx] != &invalid_handler) { | |
7837 | return -1; | |
7838 | } | |
7839 | table[idx] = handler; | |
7840 | ||
7841 | return 0; | |
7842 | } | |
7843 | ||
7844 | static int register_direct_insn(opc_handler_t **ppc_opcodes, | |
7845 | unsigned char idx, opc_handler_t *handler) | |
7846 | { | |
7847 | if (insert_in_table(ppc_opcodes, idx, handler) < 0) { | |
7848 | printf("*** ERROR: opcode %02x already assigned in main " | |
7849 | "opcode table\n", idx); | |
7850 | #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) | |
7851 | printf(" Registered handler '%s' - new handler '%s'\n", | |
7852 | ppc_opcodes[idx]->oname, handler->oname); | |
7853 | #endif | |
7854 | return -1; | |
7855 | } | |
7856 | ||
7857 | return 0; | |
7858 | } | |
7859 | ||
7860 | static int register_ind_in_table(opc_handler_t **table, | |
7861 | unsigned char idx1, unsigned char idx2, | |
7862 | opc_handler_t *handler) | |
7863 | { | |
7864 | if (table[idx1] == &invalid_handler) { | |
7865 | if (create_new_table(table, idx1) < 0) { | |
7866 | printf("*** ERROR: unable to create indirect table " | |
7867 | "idx=%02x\n", idx1); | |
7868 | return -1; | |
7869 | } | |
7870 | } else { | |
7871 | if (!is_indirect_opcode(table[idx1])) { | |
7872 | printf("*** ERROR: idx %02x already assigned to a direct " | |
7873 | "opcode\n", idx1); | |
7874 | #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) | |
7875 | printf(" Registered handler '%s' - new handler '%s'\n", | |
7876 | ind_table(table[idx1])[idx2]->oname, handler->oname); | |
7877 | #endif | |
7878 | return -1; | |
7879 | } | |
7880 | } | |
7881 | if (handler != NULL && | |
7882 | insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { | |
7883 | printf("*** ERROR: opcode %02x already assigned in " | |
7884 | "opcode table %02x\n", idx2, idx1); | |
7885 | #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) | |
7886 | printf(" Registered handler '%s' - new handler '%s'\n", | |
7887 | ind_table(table[idx1])[idx2]->oname, handler->oname); | |
7888 | #endif | |
7889 | return -1; | |
7890 | } | |
7891 | ||
7892 | return 0; | |
7893 | } | |
7894 | ||
7895 | static int register_ind_insn(opc_handler_t **ppc_opcodes, | |
7896 | unsigned char idx1, unsigned char idx2, | |
7897 | opc_handler_t *handler) | |
7898 | { | |
7899 | return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); | |
7900 | } | |
7901 | ||
7902 | static int register_dblind_insn(opc_handler_t **ppc_opcodes, | |
7903 | unsigned char idx1, unsigned char idx2, | |
7904 | unsigned char idx3, opc_handler_t *handler) | |
7905 | { | |
7906 | if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { | |
7907 | printf("*** ERROR: unable to join indirect table idx " | |
7908 | "[%02x-%02x]\n", idx1, idx2); | |
7909 | return -1; | |
7910 | } | |
7911 | if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, | |
7912 | handler) < 0) { | |
7913 | printf("*** ERROR: unable to insert opcode " | |
7914 | "[%02x-%02x-%02x]\n", idx1, idx2, idx3); | |
7915 | return -1; | |
7916 | } | |
7917 | ||
7918 | return 0; | |
7919 | } | |
7920 | ||
7921 | static int register_trplind_insn(opc_handler_t **ppc_opcodes, | |
7922 | unsigned char idx1, unsigned char idx2, | |
7923 | unsigned char idx3, unsigned char idx4, | |
7924 | opc_handler_t *handler) | |
7925 | { | |
7926 | opc_handler_t **table; | |
7927 | ||
7928 | if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { | |
7929 | printf("*** ERROR: unable to join indirect table idx " | |
7930 | "[%02x-%02x]\n", idx1, idx2); | |
7931 | return -1; | |
7932 | } | |
7933 | table = ind_table(ppc_opcodes[idx1]); | |
7934 | if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { | |
7935 | printf("*** ERROR: unable to join 2nd-level indirect table idx " | |
7936 | "[%02x-%02x-%02x]\n", idx1, idx2, idx3); | |
7937 | return -1; | |
7938 | } | |
7939 | table = ind_table(table[idx2]); | |
7940 | if (register_ind_in_table(table, idx3, idx4, handler) < 0) { | |
7941 | printf("*** ERROR: unable to insert opcode " | |
7942 | "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); | |
7943 | return -1; | |
7944 | } | |
7945 | return 0; | |
7946 | } | |
7947 | static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) | |
7948 | { | |
7949 | if (insn->opc2 != 0xFF) { | |
7950 | if (insn->opc3 != 0xFF) { | |
7951 | if (insn->opc4 != 0xFF) { | |
7952 | if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, | |
7953 | insn->opc3, insn->opc4, | |
7954 | &insn->handler) < 0) { | |
7955 | return -1; | |
7956 | } | |
7957 | } else { | |
7958 | if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, | |
7959 | insn->opc3, &insn->handler) < 0) { | |
7960 | return -1; | |
7961 | } | |
7962 | } | |
7963 | } else { | |
7964 | if (register_ind_insn(ppc_opcodes, insn->opc1, | |
7965 | insn->opc2, &insn->handler) < 0) { | |
7966 | return -1; | |
7967 | } | |
7968 | } | |
7969 | } else { | |
7970 | if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { | |
7971 | return -1; | |
7972 | } | |
7973 | } | |
7974 | ||
7975 | return 0; | |
7976 | } | |
7977 | ||
7978 | static int test_opcode_table(opc_handler_t **table, int len) | |
7979 | { | |
7980 | int i, count, tmp; | |
7981 | ||
7982 | for (i = 0, count = 0; i < len; i++) { | |
7983 | /* Consistency fixup */ | |
7984 | if (table[i] == NULL) { | |
7985 | table[i] = &invalid_handler; | |
7986 | } | |
7987 | if (table[i] != &invalid_handler) { | |
7988 | if (is_indirect_opcode(table[i])) { | |
7989 | tmp = test_opcode_table(ind_table(table[i]), | |
7990 | PPC_CPU_INDIRECT_OPCODES_LEN); | |
7991 | if (tmp == 0) { | |
7992 | free(table[i]); | |
7993 | table[i] = &invalid_handler; | |
7994 | } else { | |
7995 | count++; | |
7996 | } | |
7997 | } else { | |
7998 | count++; | |
7999 | } | |
8000 | } | |
8001 | } | |
8002 | ||
8003 | return count; | |
8004 | } | |
8005 | ||
8006 | static void fix_opcode_tables(opc_handler_t **ppc_opcodes) | |
8007 | { | |
8008 | if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { | |
8009 | printf("*** WARNING: no opcode defined !\n"); | |
8010 | } | |
8011 | } | |
8012 | ||
8013 | /*****************************************************************************/ | |
8014 | void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) | |
8015 | { | |
8016 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); | |
8017 | opcode_t *opc; | |
8018 | ||
8019 | fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); | |
8020 | for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { | |
8021 | if (((opc->handler.type & pcc->insns_flags) != 0) || | |
8022 | ((opc->handler.type2 & pcc->insns_flags2) != 0)) { | |
8023 | if (register_insn(cpu->opcodes, opc) < 0) { | |
8024 | error_setg(errp, "ERROR initializing PowerPC instruction " | |
8025 | "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, | |
8026 | opc->opc3); | |
8027 | return; | |
8028 | } | |
8029 | } | |
8030 | } | |
8031 | fix_opcode_tables(cpu->opcodes); | |
8032 | fflush(stdout); | |
8033 | fflush(stderr); | |
8034 | } | |
8035 | ||
8036 | void destroy_ppc_opcodes(PowerPCCPU *cpu) | |
8037 | { | |
8038 | opc_handler_t **table, **table_2; | |
8039 | int i, j, k; | |
8040 | ||
8041 | for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { | |
8042 | if (cpu->opcodes[i] == &invalid_handler) { | |
8043 | continue; | |
8044 | } | |
8045 | if (is_indirect_opcode(cpu->opcodes[i])) { | |
8046 | table = ind_table(cpu->opcodes[i]); | |
8047 | for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { | |
8048 | if (table[j] == &invalid_handler) { | |
8049 | continue; | |
8050 | } | |
8051 | if (is_indirect_opcode(table[j])) { | |
8052 | table_2 = ind_table(table[j]); | |
8053 | for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { | |
8054 | if (table_2[k] != &invalid_handler && | |
8055 | is_indirect_opcode(table_2[k])) { | |
8056 | g_free((opc_handler_t *)((uintptr_t)table_2[k] & | |
8057 | ~PPC_INDIRECT)); | |
8058 | } | |
8059 | } | |
8060 | g_free((opc_handler_t *)((uintptr_t)table[j] & | |
8061 | ~PPC_INDIRECT)); | |
8062 | } | |
8063 | } | |
8064 | g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & | |
8065 | ~PPC_INDIRECT)); | |
8066 | } | |
8067 | } | |
8068 | } | |
8069 | ||
8070 | #if defined(PPC_DUMP_CPU) | |
8071 | static void dump_ppc_insns(CPUPPCState *env) | |
8072 | { | |
8073 | opc_handler_t **table, *handler; | |
8074 | const char *p, *q; | |
8075 | uint8_t opc1, opc2, opc3, opc4; | |
8076 | ||
8077 | printf("Instructions set:\n"); | |
8078 | /* opc1 is 6 bits long */ | |
8079 | for (opc1 = 0x00; opc1 < PPC_CPU_OPCODES_LEN; opc1++) { | |
8080 | table = env->opcodes; | |
8081 | handler = table[opc1]; | |
8082 | if (is_indirect_opcode(handler)) { | |
8083 | /* opc2 is 5 bits long */ | |
8084 | for (opc2 = 0; opc2 < PPC_CPU_INDIRECT_OPCODES_LEN; opc2++) { | |
8085 | table = env->opcodes; | |
8086 | handler = env->opcodes[opc1]; | |
8087 | table = ind_table(handler); | |
8088 | handler = table[opc2]; | |
8089 | if (is_indirect_opcode(handler)) { | |
8090 | table = ind_table(handler); | |
8091 | /* opc3 is 5 bits long */ | |
8092 | for (opc3 = 0; opc3 < PPC_CPU_INDIRECT_OPCODES_LEN; | |
8093 | opc3++) { | |
8094 | handler = table[opc3]; | |
8095 | if (is_indirect_opcode(handler)) { | |
8096 | table = ind_table(handler); | |
8097 | /* opc4 is 5 bits long */ | |
8098 | for (opc4 = 0; opc4 < PPC_CPU_INDIRECT_OPCODES_LEN; | |
8099 | opc4++) { | |
8100 | handler = table[opc4]; | |
8101 | if (handler->handler != &gen_invalid) { | |
8102 | printf("INSN: %02x %02x %02x %02x -- " | |
8103 | "(%02d %04d %02d) : %s\n", | |
8104 | opc1, opc2, opc3, opc4, | |
8105 | opc1, (opc3 << 5) | opc2, opc4, | |
8106 | handler->oname); | |
8107 | } | |
8108 | } | |
8109 | } else { | |
8110 | if (handler->handler != &gen_invalid) { | |
8111 | /* Special hack to properly dump SPE insns */ | |
8112 | p = strchr(handler->oname, '_'); | |
8113 | if (p == NULL) { | |
8114 | printf("INSN: %02x %02x %02x (%02d %04d) : " | |
8115 | "%s\n", | |
8116 | opc1, opc2, opc3, opc1, | |
8117 | (opc3 << 5) | opc2, | |
8118 | handler->oname); | |
8119 | } else { | |
8120 | q = "speundef"; | |
8121 | if ((p - handler->oname) != strlen(q) | |
8122 | || (memcmp(handler->oname, q, strlen(q)) | |
8123 | != 0)) { | |
8124 | /* First instruction */ | |
8125 | printf("INSN: %02x %02x %02x" | |
8126 | "(%02d %04d) : %.*s\n", | |
8127 | opc1, opc2 << 1, opc3, opc1, | |
8128 | (opc3 << 6) | (opc2 << 1), | |
8129 | (int)(p - handler->oname), | |
8130 | handler->oname); | |
8131 | } | |
8132 | if (strcmp(p + 1, q) != 0) { | |
8133 | /* Second instruction */ | |
8134 | printf("INSN: %02x %02x %02x " | |
8135 | "(%02d %04d) : %s\n", opc1, | |
8136 | (opc2 << 1) | 1, opc3, opc1, | |
8137 | (opc3 << 6) | (opc2 << 1) | 1, | |
8138 | p + 1); | |
8139 | } | |
8140 | } | |
8141 | } | |
8142 | } | |
8143 | } | |
8144 | } else { | |
8145 | if (handler->handler != &gen_invalid) { | |
8146 | printf("INSN: %02x %02x -- (%02d %04d) : %s\n", | |
8147 | opc1, opc2, opc1, opc2, handler->oname); | |
8148 | } | |
8149 | } | |
8150 | } | |
8151 | } else { | |
8152 | if (handler->handler != &gen_invalid) { | |
8153 | printf("INSN: %02x -- -- (%02d ----) : %s\n", | |
8154 | opc1, opc1, handler->oname); | |
8155 | } | |
8156 | } | |
8157 | } | |
8158 | } | |
8159 | #endif | |
8160 | int ppc_fixup_cpu(PowerPCCPU *cpu) | |
8161 | { | |
8162 | CPUPPCState *env = &cpu->env; | |
8163 | ||
8164 | /* | |
8165 | * TCG doesn't (yet) emulate some groups of instructions that are | |
8166 | * implemented on some otherwise supported CPUs (e.g. VSX and | |
8167 | * decimal floating point instructions on POWER7). We remove | |
8168 | * unsupported instruction groups from the cpu state's instruction | |
8169 | * masks and hope the guest can cope. For at least the pseries | |
8170 | * machine, the unavailability of these instructions can be | |
8171 | * advertised to the guest via the device tree. | |
8172 | */ | |
8173 | if ((env->insns_flags & ~PPC_TCG_INSNS) | |
8174 | || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { | |
8175 | warn_report("Disabling some instructions which are not " | |
8176 | "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", | |
8177 | env->insns_flags & ~PPC_TCG_INSNS, | |
8178 | env->insns_flags2 & ~PPC_TCG_INSNS2); | |
8179 | } | |
8180 | env->insns_flags &= PPC_TCG_INSNS; | |
8181 | env->insns_flags2 &= PPC_TCG_INSNS2; | |
8182 | return 0; | |
8183 | } | |
8184 | ||
8185 | ||
11cb6c15 | 8186 | void ppc_cpu_dump_statistics(CPUState *cs, int flags) |
76a66253 JM |
8187 | { |
8188 | #if defined(DO_PPC_STATISTICS) | |
878096ee | 8189 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
c227f099 | 8190 | opc_handler_t **t1, **t2, **t3, *handler; |
76a66253 JM |
8191 | int op1, op2, op3; |
8192 | ||
878096ee | 8193 | t1 = cpu->env.opcodes; |
76a66253 JM |
8194 | for (op1 = 0; op1 < 64; op1++) { |
8195 | handler = t1[op1]; | |
8196 | if (is_indirect_opcode(handler)) { | |
8197 | t2 = ind_table(handler); | |
8198 | for (op2 = 0; op2 < 32; op2++) { | |
8199 | handler = t2[op2]; | |
8200 | if (is_indirect_opcode(handler)) { | |
8201 | t3 = ind_table(handler); | |
8202 | for (op3 = 0; op3 < 32; op3++) { | |
8203 | handler = t3[op3]; | |
efe843d8 | 8204 | if (handler->count == 0) { |
76a66253 | 8205 | continue; |
efe843d8 | 8206 | } |
11cb6c15 | 8207 | qemu_printf("%02x %02x %02x (%02x %04d) %16s: " |
0bfcd599 | 8208 | "%016" PRIx64 " %" PRId64 "\n", |
76a66253 JM |
8209 | op1, op2, op3, op1, (op3 << 5) | op2, |
8210 | handler->oname, | |
8211 | handler->count, handler->count); | |
8212 | } | |
8213 | } else { | |
efe843d8 | 8214 | if (handler->count == 0) { |
76a66253 | 8215 | continue; |
efe843d8 | 8216 | } |
11cb6c15 | 8217 | qemu_printf("%02x %02x (%02x %04d) %16s: " |
0bfcd599 | 8218 | "%016" PRIx64 " %" PRId64 "\n", |
76a66253 JM |
8219 | op1, op2, op1, op2, handler->oname, |
8220 | handler->count, handler->count); | |
8221 | } | |
8222 | } | |
8223 | } else { | |
efe843d8 | 8224 | if (handler->count == 0) { |
76a66253 | 8225 | continue; |
efe843d8 | 8226 | } |
11cb6c15 | 8227 | qemu_printf("%02x (%02x ) %16s: %016" PRIx64 |
0bfcd599 | 8228 | " %" PRId64 "\n", |
76a66253 JM |
8229 | op1, op1, handler->oname, |
8230 | handler->count, handler->count); | |
8231 | } | |
8232 | } | |
8233 | #endif | |
8234 | } | |
8235 | ||
b542683d | 8236 | static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) |
79aceca5 | 8237 | { |
b0c2d521 | 8238 | DisasContext *ctx = container_of(dcbase, DisasContext, base); |
9c489ea6 | 8239 | CPUPPCState *env = cs->env_ptr; |
2df4fe7a | 8240 | uint32_t hflags = ctx->base.tb->flags; |
b0c2d521 EC |
8241 | int bound; |
8242 | ||
8243 | ctx->exception = POWERPC_EXCP_NONE; | |
8244 | ctx->spr_cb = env->spr_cb; | |
2df4fe7a | 8245 | ctx->pr = (hflags >> HFLAGS_PR) & 1; |
d764184d | 8246 | ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; |
2df4fe7a RH |
8247 | ctx->dr = (hflags >> HFLAGS_DR) & 1; |
8248 | ctx->hv = (hflags >> HFLAGS_HV) & 1; | |
b0c2d521 EC |
8249 | ctx->insns_flags = env->insns_flags; |
8250 | ctx->insns_flags2 = env->insns_flags2; | |
8251 | ctx->access_type = -1; | |
d57d72a8 | 8252 | ctx->need_access_type = !mmu_is_64bit(env->mmu_model); |
2df4fe7a | 8253 | ctx->le_mode = (hflags >> HFLAGS_LE) & 1; |
b0c2d521 | 8254 | ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; |
0e3bf489 | 8255 | ctx->flags = env->flags; |
d9bce9d9 | 8256 | #if defined(TARGET_PPC64) |
2df4fe7a | 8257 | ctx->sf_mode = (hflags >> HFLAGS_64) & 1; |
b0c2d521 | 8258 | ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); |
9a64fbe4 | 8259 | #endif |
e69ba2b4 DG |
8260 | ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B |
8261 | || env->mmu_model == POWERPC_MMU_601 | |
d55dfd44 | 8262 | || env->mmu_model & POWERPC_MMU_64; |
c5a8d8f3 | 8263 | |
2df4fe7a RH |
8264 | ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; |
8265 | ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; | |
8266 | ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; | |
8267 | ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; | |
2df4fe7a | 8268 | ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; |
f03de3b4 | 8269 | ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; |
2df4fe7a RH |
8270 | |
8271 | ctx->singlestep_enabled = 0; | |
8272 | if ((hflags >> HFLAGS_SE) & 1) { | |
8273 | ctx->singlestep_enabled |= CPU_SINGLE_STEP; | |
efe843d8 | 8274 | } |
2df4fe7a | 8275 | if ((hflags >> HFLAGS_BE) & 1) { |
b0c2d521 | 8276 | ctx->singlestep_enabled |= CPU_BRANCH_STEP; |
efe843d8 | 8277 | } |
b0c2d521 EC |
8278 | if (unlikely(ctx->base.singlestep_enabled)) { |
8279 | ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP; | |
ed2803da | 8280 | } |
b933066a | 8281 | |
b0c2d521 | 8282 | bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; |
b542683d | 8283 | ctx->base.max_insns = MIN(ctx->base.max_insns, bound); |
b0c2d521 EC |
8284 | } |
8285 | ||
8286 | static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) | |
8287 | { | |
8288 | } | |
8289 | ||
8290 | static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) | |
8291 | { | |
8292 | tcg_gen_insn_start(dcbase->pc_next); | |
8293 | } | |
8294 | ||
8295 | static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, | |
8296 | const CPUBreakpoint *bp) | |
8297 | { | |
8298 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
8299 | ||
8300 | gen_debug_exception(ctx); | |
2a8ceefc | 8301 | dcbase->is_jmp = DISAS_NORETURN; |
efe843d8 DG |
8302 | /* |
8303 | * The address covered by the breakpoint must be included in | |
8304 | * [tb->pc, tb->pc + tb->size) in order to for it to be properly | |
8305 | * cleared -- thus we increment the PC here so that the logic | |
8306 | * setting tb->size below does the right thing. | |
8307 | */ | |
b0c2d521 EC |
8308 | ctx->base.pc_next += 4; |
8309 | return true; | |
8310 | } | |
8311 | ||
8312 | static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) | |
8313 | { | |
8314 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
28876bf2 | 8315 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
b0c2d521 EC |
8316 | CPUPPCState *env = cs->env_ptr; |
8317 | opc_handler_t **table, *handler; | |
8318 | ||
8319 | LOG_DISAS("----------------\n"); | |
8320 | LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", | |
8321 | ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); | |
8322 | ||
23f42b60 EC |
8323 | ctx->opcode = translator_ldl_swap(env, ctx->base.pc_next, |
8324 | need_byteswap(ctx)); | |
8325 | ||
b0c2d521 EC |
8326 | LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", |
8327 | ctx->opcode, opc1(ctx->opcode), opc2(ctx->opcode), | |
8328 | opc3(ctx->opcode), opc4(ctx->opcode), | |
8329 | ctx->le_mode ? "little" : "big"); | |
8330 | ctx->base.pc_next += 4; | |
28876bf2 | 8331 | table = cpu->opcodes; |
b0c2d521 EC |
8332 | handler = table[opc1(ctx->opcode)]; |
8333 | if (is_indirect_opcode(handler)) { | |
8334 | table = ind_table(handler); | |
8335 | handler = table[opc2(ctx->opcode)]; | |
79aceca5 FB |
8336 | if (is_indirect_opcode(handler)) { |
8337 | table = ind_table(handler); | |
b0c2d521 | 8338 | handler = table[opc3(ctx->opcode)]; |
79aceca5 FB |
8339 | if (is_indirect_opcode(handler)) { |
8340 | table = ind_table(handler); | |
b0c2d521 | 8341 | handler = table[opc4(ctx->opcode)]; |
79aceca5 FB |
8342 | } |
8343 | } | |
b0c2d521 EC |
8344 | } |
8345 | /* Is opcode *REALLY* valid ? */ | |
8346 | if (unlikely(handler->handler == &gen_invalid)) { | |
8347 | qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " | |
8348 | "%02x - %02x - %02x - %02x (%08x) " | |
8349 | TARGET_FMT_lx " %d\n", | |
8350 | opc1(ctx->opcode), opc2(ctx->opcode), | |
8351 | opc3(ctx->opcode), opc4(ctx->opcode), | |
8352 | ctx->opcode, ctx->base.pc_next - 4, (int)msr_ir); | |
8353 | } else { | |
8354 | uint32_t inval; | |
70560da7 | 8355 | |
b0c2d521 EC |
8356 | if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) |
8357 | && Rc(ctx->opcode))) { | |
8358 | inval = handler->inval2; | |
8359 | } else { | |
8360 | inval = handler->inval1; | |
8361 | } | |
70560da7 | 8362 | |
b0c2d521 EC |
8363 | if (unlikely((ctx->opcode & inval) != 0)) { |
8364 | qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " | |
8365 | "%02x - %02x - %02x - %02x (%08x) " | |
8366 | TARGET_FMT_lx "\n", ctx->opcode & inval, | |
8367 | opc1(ctx->opcode), opc2(ctx->opcode), | |
8368 | opc3(ctx->opcode), opc4(ctx->opcode), | |
8369 | ctx->opcode, ctx->base.pc_next - 4); | |
8370 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
8371 | ctx->base.is_jmp = DISAS_NORETURN; | |
8372 | return; | |
79aceca5 | 8373 | } |
b0c2d521 EC |
8374 | } |
8375 | (*(handler->handler))(ctx); | |
76a66253 | 8376 | #if defined(DO_PPC_STATISTICS) |
b0c2d521 | 8377 | handler->count++; |
76a66253 | 8378 | #endif |
b0c2d521 EC |
8379 | /* Check trace mode exceptions */ |
8380 | if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP && | |
8381 | (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) && | |
8382 | ctx->exception != POWERPC_SYSCALL && | |
8383 | ctx->exception != POWERPC_EXCP_TRAP && | |
8384 | ctx->exception != POWERPC_EXCP_BRANCH)) { | |
e150ac89 RK |
8385 | uint32_t excp = gen_prep_dbgex(ctx); |
8386 | gen_exception_nip(ctx, excp, ctx->base.pc_next); | |
b0c2d521 EC |
8387 | } |
8388 | ||
8389 | if (tcg_check_temp_count()) { | |
8390 | qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked " | |
8391 | "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode), | |
8392 | opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode); | |
3fc6c082 | 8393 | } |
b0c2d521 EC |
8394 | |
8395 | ctx->base.is_jmp = ctx->exception == POWERPC_EXCP_NONE ? | |
8396 | DISAS_NEXT : DISAS_NORETURN; | |
8397 | } | |
8398 | ||
8399 | static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) | |
8400 | { | |
8401 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
8402 | ||
8403 | if (ctx->exception == POWERPC_EXCP_NONE) { | |
8404 | gen_goto_tb(ctx, 0, ctx->base.pc_next); | |
8405 | } else if (ctx->exception != POWERPC_EXCP_BRANCH) { | |
8406 | if (unlikely(ctx->base.singlestep_enabled)) { | |
8407 | gen_debug_exception(ctx); | |
8cbcb4fa | 8408 | } |
76a66253 | 8409 | /* Generate the return instruction */ |
07ea28b4 | 8410 | tcg_gen_exit_tb(NULL, 0); |
9a64fbe4 | 8411 | } |
b0c2d521 EC |
8412 | } |
8413 | ||
8414 | static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) | |
8415 | { | |
8416 | qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); | |
8417 | log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); | |
8418 | } | |
0a7df5da | 8419 | |
b0c2d521 EC |
8420 | static const TranslatorOps ppc_tr_ops = { |
8421 | .init_disas_context = ppc_tr_init_disas_context, | |
8422 | .tb_start = ppc_tr_tb_start, | |
8423 | .insn_start = ppc_tr_insn_start, | |
8424 | .breakpoint_check = ppc_tr_breakpoint_check, | |
8425 | .translate_insn = ppc_tr_translate_insn, | |
8426 | .tb_stop = ppc_tr_tb_stop, | |
8427 | .disas_log = ppc_tr_disas_log, | |
8428 | }; | |
4e5e1215 | 8429 | |
8b86d6d2 | 8430 | void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) |
b0c2d521 EC |
8431 | { |
8432 | DisasContext ctx; | |
8433 | ||
8b86d6d2 | 8434 | translator_loop(&ppc_tr_ops, &ctx.base, cs, tb, max_insns); |
79aceca5 FB |
8435 | } |
8436 | ||
bad729e2 RH |
8437 | void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, |
8438 | target_ulong *data) | |
d2856f1a | 8439 | { |
bad729e2 | 8440 | env->nip = data[0]; |
d2856f1a | 8441 | } |