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79aceca5 | 1 | /* |
3fc6c082 | 2 | * PowerPC emulation for qemu: main translation routines. |
5fafdf24 | 3 | * |
76a66253 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
90dc8812 | 5 | * Copyright (C) 2011 Freescale Semiconductor, Inc. |
79aceca5 FB |
6 | * |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
79aceca5 | 19 | */ |
c6a1c22b | 20 | |
0d75590d | 21 | #include "qemu/osdep.h" |
79aceca5 | 22 | #include "cpu.h" |
3e00884f | 23 | #include "internal.h" |
76cad711 | 24 | #include "disas/disas.h" |
63c91552 | 25 | #include "exec/exec-all.h" |
57fec1fe | 26 | #include "tcg-op.h" |
1de7afc9 | 27 | #include "qemu/host-utils.h" |
f08b6170 | 28 | #include "exec/cpu_ldst.h" |
79aceca5 | 29 | |
2ef6175a RH |
30 | #include "exec/helper-proto.h" |
31 | #include "exec/helper-gen.h" | |
a7812ae4 | 32 | |
a7e30d84 | 33 | #include "trace-tcg.h" |
b6bac4bc | 34 | #include "exec/translator.h" |
508127e2 | 35 | #include "exec/log.h" |
a7e30d84 LV |
36 | |
37 | ||
8cbcb4fa AJ |
38 | #define CPU_SINGLE_STEP 0x1 |
39 | #define CPU_BRANCH_STEP 0x2 | |
40 | #define GDBSTUB_SINGLE_STEP 0x4 | |
41 | ||
a750fc0b | 42 | /* Include definitions for instructions classes and implementations flags */ |
9fddaa0c | 43 | //#define PPC_DEBUG_DISAS |
76a66253 | 44 | //#define DO_PPC_STATISTICS |
79aceca5 | 45 | |
d12d51d5 | 46 | #ifdef PPC_DEBUG_DISAS |
93fcfe39 | 47 | # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) |
d12d51d5 AL |
48 | #else |
49 | # define LOG_DISAS(...) do { } while (0) | |
50 | #endif | |
a750fc0b JM |
51 | /*****************************************************************************/ |
52 | /* Code translation helpers */ | |
c53be334 | 53 | |
f78fb44e | 54 | /* global register indexes */ |
1d542695 | 55 | static char cpu_reg_names[10*3 + 22*4 /* GPR */ |
1d542695 | 56 | + 10*4 + 22*5 /* SPE GPRh */ |
a5e26afa | 57 | + 10*4 + 22*5 /* FPR */ |
47e4661c | 58 | + 2*(10*6 + 22*7) /* AVRh, AVRl */ |
472b24ce | 59 | + 10*5 + 22*6 /* VSR */ |
47e4661c | 60 | + 8*5 /* CRF */]; |
f78fb44e | 61 | static TCGv cpu_gpr[32]; |
f78fb44e | 62 | static TCGv cpu_gprh[32]; |
a7812ae4 PB |
63 | static TCGv_i64 cpu_fpr[32]; |
64 | static TCGv_i64 cpu_avrh[32], cpu_avrl[32]; | |
472b24ce | 65 | static TCGv_i64 cpu_vsr[32]; |
a7812ae4 | 66 | static TCGv_i32 cpu_crf[8]; |
bd568f18 | 67 | static TCGv cpu_nip; |
6527f6ea | 68 | static TCGv cpu_msr; |
cfdcd37a AJ |
69 | static TCGv cpu_ctr; |
70 | static TCGv cpu_lr; | |
697ab892 DG |
71 | #if defined(TARGET_PPC64) |
72 | static TCGv cpu_cfar; | |
73 | #endif | |
dd09c361 | 74 | static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; |
cf360a32 | 75 | static TCGv cpu_reserve; |
253ce7b2 | 76 | static TCGv cpu_reserve_val; |
30304420 | 77 | static TCGv cpu_fpscr; |
a7859e89 | 78 | static TCGv_i32 cpu_access_type; |
f78fb44e | 79 | |
022c62cb | 80 | #include "exec/gen-icount.h" |
2e70f6ef PB |
81 | |
82 | void ppc_translate_init(void) | |
83 | { | |
f78fb44e AJ |
84 | int i; |
85 | char* p; | |
2dc766da | 86 | size_t cpu_reg_names_size; |
f78fb44e | 87 | |
f78fb44e | 88 | p = cpu_reg_names; |
2dc766da | 89 | cpu_reg_names_size = sizeof(cpu_reg_names); |
47e4661c AJ |
90 | |
91 | for (i = 0; i < 8; i++) { | |
2dc766da | 92 | snprintf(p, cpu_reg_names_size, "crf%d", i); |
e1ccc054 | 93 | cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, |
1328c2bf | 94 | offsetof(CPUPPCState, crf[i]), p); |
47e4661c | 95 | p += 5; |
2dc766da | 96 | cpu_reg_names_size -= 5; |
47e4661c AJ |
97 | } |
98 | ||
f78fb44e | 99 | for (i = 0; i < 32; i++) { |
2dc766da | 100 | snprintf(p, cpu_reg_names_size, "r%d", i); |
e1ccc054 | 101 | cpu_gpr[i] = tcg_global_mem_new(cpu_env, |
1328c2bf | 102 | offsetof(CPUPPCState, gpr[i]), p); |
f78fb44e | 103 | p += (i < 10) ? 3 : 4; |
2dc766da | 104 | cpu_reg_names_size -= (i < 10) ? 3 : 4; |
2dc766da | 105 | snprintf(p, cpu_reg_names_size, "r%dH", i); |
e1ccc054 | 106 | cpu_gprh[i] = tcg_global_mem_new(cpu_env, |
13b6a455 | 107 | offsetof(CPUPPCState, gprh[i]), p); |
f78fb44e | 108 | p += (i < 10) ? 4 : 5; |
2dc766da | 109 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
1d542695 | 110 | |
2dc766da | 111 | snprintf(p, cpu_reg_names_size, "fp%d", i); |
e1ccc054 | 112 | cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, |
1328c2bf | 113 | offsetof(CPUPPCState, fpr[i]), p); |
ec1ac72d | 114 | p += (i < 10) ? 4 : 5; |
2dc766da | 115 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
a5e26afa | 116 | |
2dc766da | 117 | snprintf(p, cpu_reg_names_size, "avr%dH", i); |
e2542fe2 | 118 | #ifdef HOST_WORDS_BIGENDIAN |
e1ccc054 | 119 | cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env, |
1328c2bf | 120 | offsetof(CPUPPCState, avr[i].u64[0]), p); |
fe1e5c53 | 121 | #else |
e1ccc054 | 122 | cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env, |
1328c2bf | 123 | offsetof(CPUPPCState, avr[i].u64[1]), p); |
fe1e5c53 | 124 | #endif |
1d542695 | 125 | p += (i < 10) ? 6 : 7; |
2dc766da | 126 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
ec1ac72d | 127 | |
2dc766da | 128 | snprintf(p, cpu_reg_names_size, "avr%dL", i); |
e2542fe2 | 129 | #ifdef HOST_WORDS_BIGENDIAN |
e1ccc054 | 130 | cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env, |
1328c2bf | 131 | offsetof(CPUPPCState, avr[i].u64[1]), p); |
fe1e5c53 | 132 | #else |
e1ccc054 | 133 | cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env, |
1328c2bf | 134 | offsetof(CPUPPCState, avr[i].u64[0]), p); |
fe1e5c53 | 135 | #endif |
1d542695 | 136 | p += (i < 10) ? 6 : 7; |
2dc766da | 137 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
472b24ce | 138 | snprintf(p, cpu_reg_names_size, "vsr%d", i); |
e1ccc054 RH |
139 | cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env, |
140 | offsetof(CPUPPCState, vsr[i]), p); | |
472b24ce TM |
141 | p += (i < 10) ? 5 : 6; |
142 | cpu_reg_names_size -= (i < 10) ? 5 : 6; | |
f78fb44e | 143 | } |
f10dc08e | 144 | |
e1ccc054 | 145 | cpu_nip = tcg_global_mem_new(cpu_env, |
1328c2bf | 146 | offsetof(CPUPPCState, nip), "nip"); |
bd568f18 | 147 | |
e1ccc054 | 148 | cpu_msr = tcg_global_mem_new(cpu_env, |
1328c2bf | 149 | offsetof(CPUPPCState, msr), "msr"); |
6527f6ea | 150 | |
e1ccc054 | 151 | cpu_ctr = tcg_global_mem_new(cpu_env, |
1328c2bf | 152 | offsetof(CPUPPCState, ctr), "ctr"); |
cfdcd37a | 153 | |
e1ccc054 | 154 | cpu_lr = tcg_global_mem_new(cpu_env, |
1328c2bf | 155 | offsetof(CPUPPCState, lr), "lr"); |
cfdcd37a | 156 | |
697ab892 | 157 | #if defined(TARGET_PPC64) |
e1ccc054 | 158 | cpu_cfar = tcg_global_mem_new(cpu_env, |
1328c2bf | 159 | offsetof(CPUPPCState, cfar), "cfar"); |
697ab892 DG |
160 | #endif |
161 | ||
e1ccc054 | 162 | cpu_xer = tcg_global_mem_new(cpu_env, |
1328c2bf | 163 | offsetof(CPUPPCState, xer), "xer"); |
e1ccc054 | 164 | cpu_so = tcg_global_mem_new(cpu_env, |
da91a00f | 165 | offsetof(CPUPPCState, so), "SO"); |
e1ccc054 | 166 | cpu_ov = tcg_global_mem_new(cpu_env, |
da91a00f | 167 | offsetof(CPUPPCState, ov), "OV"); |
e1ccc054 | 168 | cpu_ca = tcg_global_mem_new(cpu_env, |
da91a00f | 169 | offsetof(CPUPPCState, ca), "CA"); |
dd09c361 ND |
170 | cpu_ov32 = tcg_global_mem_new(cpu_env, |
171 | offsetof(CPUPPCState, ov32), "OV32"); | |
172 | cpu_ca32 = tcg_global_mem_new(cpu_env, | |
173 | offsetof(CPUPPCState, ca32), "CA32"); | |
3d7b417e | 174 | |
e1ccc054 | 175 | cpu_reserve = tcg_global_mem_new(cpu_env, |
1328c2bf | 176 | offsetof(CPUPPCState, reserve_addr), |
18b21a2f | 177 | "reserve_addr"); |
253ce7b2 ND |
178 | cpu_reserve_val = tcg_global_mem_new(cpu_env, |
179 | offsetof(CPUPPCState, reserve_val), | |
180 | "reserve_val"); | |
cf360a32 | 181 | |
e1ccc054 | 182 | cpu_fpscr = tcg_global_mem_new(cpu_env, |
30304420 | 183 | offsetof(CPUPPCState, fpscr), "fpscr"); |
e1571908 | 184 | |
e1ccc054 | 185 | cpu_access_type = tcg_global_mem_new_i32(cpu_env, |
1328c2bf | 186 | offsetof(CPUPPCState, access_type), "access_type"); |
2e70f6ef PB |
187 | } |
188 | ||
79aceca5 | 189 | /* internal defines */ |
69b058c8 | 190 | struct DisasContext { |
b6bac4bc | 191 | DisasContextBase base; |
79aceca5 | 192 | uint32_t opcode; |
9a64fbe4 | 193 | uint32_t exception; |
3cc62370 | 194 | /* Routine used to access memory */ |
5c3ae929 | 195 | bool pr, hv, dr, le_mode; |
c5a8d8f3 | 196 | bool lazy_tlb_flush; |
5f2a6254 | 197 | bool need_access_type; |
3cc62370 | 198 | int mem_idx; |
76db3ba4 | 199 | int access_type; |
3cc62370 | 200 | /* Translation flags */ |
e22c357b | 201 | TCGMemOp default_tcg_memop_mask; |
d9bce9d9 | 202 | #if defined(TARGET_PPC64) |
5c3ae929 BH |
203 | bool sf_mode; |
204 | bool has_cfar; | |
9a64fbe4 | 205 | #endif |
5c3ae929 BH |
206 | bool fpu_enabled; |
207 | bool altivec_enabled; | |
208 | bool vsx_enabled; | |
209 | bool spe_enabled; | |
210 | bool tm_enabled; | |
c6fd28fd | 211 | bool gtse; |
c227f099 | 212 | ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ |
ea4e754f | 213 | int singlestep_enabled; |
7d08d856 AJ |
214 | uint64_t insns_flags; |
215 | uint64_t insns_flags2; | |
69b058c8 | 216 | }; |
79aceca5 | 217 | |
e22c357b DK |
218 | /* Return true iff byteswap is needed in a scalar memop */ |
219 | static inline bool need_byteswap(const DisasContext *ctx) | |
220 | { | |
221 | #if defined(TARGET_WORDS_BIGENDIAN) | |
222 | return ctx->le_mode; | |
223 | #else | |
224 | return !ctx->le_mode; | |
225 | #endif | |
226 | } | |
227 | ||
79482e5a RH |
228 | /* True when active word size < size of target_long. */ |
229 | #ifdef TARGET_PPC64 | |
230 | # define NARROW_MODE(C) (!(C)->sf_mode) | |
231 | #else | |
232 | # define NARROW_MODE(C) 0 | |
233 | #endif | |
234 | ||
c227f099 | 235 | struct opc_handler_t { |
70560da7 FC |
236 | /* invalid bits for instruction 1 (Rc(opcode) == 0) */ |
237 | uint32_t inval1; | |
238 | /* invalid bits for instruction 2 (Rc(opcode) == 1) */ | |
239 | uint32_t inval2; | |
9a64fbe4 | 240 | /* instruction type */ |
0487d6a8 | 241 | uint64_t type; |
a5858d7a AG |
242 | /* extended instruction type */ |
243 | uint64_t type2; | |
79aceca5 FB |
244 | /* handler */ |
245 | void (*handler)(DisasContext *ctx); | |
a750fc0b | 246 | #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) |
b55266b5 | 247 | const char *oname; |
a750fc0b JM |
248 | #endif |
249 | #if defined(DO_PPC_STATISTICS) | |
76a66253 JM |
250 | uint64_t count; |
251 | #endif | |
3fc6c082 | 252 | }; |
79aceca5 | 253 | |
636aa200 | 254 | static inline void gen_set_access_type(DisasContext *ctx, int access_type) |
a7859e89 | 255 | { |
5f2a6254 | 256 | if (ctx->need_access_type && ctx->access_type != access_type) { |
76db3ba4 AJ |
257 | tcg_gen_movi_i32(cpu_access_type, access_type); |
258 | ctx->access_type = access_type; | |
259 | } | |
a7859e89 AJ |
260 | } |
261 | ||
636aa200 | 262 | static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) |
d9bce9d9 | 263 | { |
e0c8f9ce RH |
264 | if (NARROW_MODE(ctx)) { |
265 | nip = (uint32_t)nip; | |
266 | } | |
267 | tcg_gen_movi_tl(cpu_nip, nip); | |
d9bce9d9 JM |
268 | } |
269 | ||
b9971cc5 | 270 | static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) |
e06fcd75 AJ |
271 | { |
272 | TCGv_i32 t0, t1; | |
bd6fefe7 BH |
273 | |
274 | /* These are all synchronous exceptions, we set the PC back to | |
275 | * the faulting instruction | |
276 | */ | |
e06fcd75 | 277 | if (ctx->exception == POWERPC_EXCP_NONE) { |
b6bac4bc | 278 | gen_update_nip(ctx, ctx->base.pc_next - 4); |
e06fcd75 AJ |
279 | } |
280 | t0 = tcg_const_i32(excp); | |
281 | t1 = tcg_const_i32(error); | |
e5f17ac6 | 282 | gen_helper_raise_exception_err(cpu_env, t0, t1); |
e06fcd75 AJ |
283 | tcg_temp_free_i32(t0); |
284 | tcg_temp_free_i32(t1); | |
285 | ctx->exception = (excp); | |
286 | } | |
e1833e1f | 287 | |
b9971cc5 | 288 | static void gen_exception(DisasContext *ctx, uint32_t excp) |
e06fcd75 AJ |
289 | { |
290 | TCGv_i32 t0; | |
bd6fefe7 BH |
291 | |
292 | /* These are all synchronous exceptions, we set the PC back to | |
293 | * the faulting instruction | |
294 | */ | |
e06fcd75 | 295 | if (ctx->exception == POWERPC_EXCP_NONE) { |
b6bac4bc | 296 | gen_update_nip(ctx, ctx->base.pc_next - 4); |
e06fcd75 AJ |
297 | } |
298 | t0 = tcg_const_i32(excp); | |
e5f17ac6 | 299 | gen_helper_raise_exception(cpu_env, t0); |
e06fcd75 AJ |
300 | tcg_temp_free_i32(t0); |
301 | ctx->exception = (excp); | |
302 | } | |
e1833e1f | 303 | |
bd6fefe7 BH |
304 | static void gen_exception_nip(DisasContext *ctx, uint32_t excp, |
305 | target_ulong nip) | |
306 | { | |
307 | TCGv_i32 t0; | |
308 | ||
309 | gen_update_nip(ctx, nip); | |
310 | t0 = tcg_const_i32(excp); | |
311 | gen_helper_raise_exception(cpu_env, t0); | |
312 | tcg_temp_free_i32(t0); | |
313 | ctx->exception = (excp); | |
314 | } | |
315 | ||
b9971cc5 | 316 | static void gen_debug_exception(DisasContext *ctx) |
e06fcd75 AJ |
317 | { |
318 | TCGv_i32 t0; | |
5518f3a6 | 319 | |
bd6fefe7 BH |
320 | /* These are all synchronous exceptions, we set the PC back to |
321 | * the faulting instruction | |
322 | */ | |
ee2b3994 SB |
323 | if ((ctx->exception != POWERPC_EXCP_BRANCH) && |
324 | (ctx->exception != POWERPC_EXCP_SYNC)) { | |
b6bac4bc | 325 | gen_update_nip(ctx, ctx->base.pc_next); |
ee2b3994 | 326 | } |
e06fcd75 | 327 | t0 = tcg_const_i32(EXCP_DEBUG); |
e5f17ac6 | 328 | gen_helper_raise_exception(cpu_env, t0); |
e06fcd75 AJ |
329 | tcg_temp_free_i32(t0); |
330 | } | |
9a64fbe4 | 331 | |
636aa200 | 332 | static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) |
e06fcd75 | 333 | { |
9b2fadda BH |
334 | /* Will be converted to program check if needed */ |
335 | gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); | |
336 | } | |
337 | ||
338 | static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) | |
339 | { | |
340 | gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); | |
341 | } | |
342 | ||
343 | static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) | |
344 | { | |
345 | /* Will be converted to program check if needed */ | |
346 | gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); | |
e06fcd75 | 347 | } |
a9d9eb8f | 348 | |
f24e5695 | 349 | /* Stop translation */ |
636aa200 | 350 | static inline void gen_stop_exception(DisasContext *ctx) |
3fc6c082 | 351 | { |
b6bac4bc | 352 | gen_update_nip(ctx, ctx->base.pc_next); |
e1833e1f | 353 | ctx->exception = POWERPC_EXCP_STOP; |
3fc6c082 FB |
354 | } |
355 | ||
466976d9 | 356 | #ifndef CONFIG_USER_ONLY |
f24e5695 | 357 | /* No need to update nip here, as execution flow will change */ |
636aa200 | 358 | static inline void gen_sync_exception(DisasContext *ctx) |
2be0071f | 359 | { |
e1833e1f | 360 | ctx->exception = POWERPC_EXCP_SYNC; |
2be0071f | 361 | } |
466976d9 | 362 | #endif |
2be0071f | 363 | |
79aceca5 | 364 | #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ |
a5858d7a AG |
365 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) |
366 | ||
367 | #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ | |
368 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) | |
79aceca5 | 369 | |
c7697e1f | 370 | #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ |
a5858d7a AG |
371 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) |
372 | ||
373 | #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ | |
374 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) | |
c7697e1f | 375 | |
323ad19b ND |
376 | #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ |
377 | GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) | |
378 | ||
14fd8ab2 ND |
379 | #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ |
380 | GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) | |
381 | ||
c227f099 | 382 | typedef struct opcode_t { |
323ad19b | 383 | unsigned char opc1, opc2, opc3, opc4; |
1235fc06 | 384 | #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ |
323ad19b | 385 | unsigned char pad[4]; |
18fba28c | 386 | #endif |
c227f099 | 387 | opc_handler_t handler; |
b55266b5 | 388 | const char *oname; |
c227f099 | 389 | } opcode_t; |
79aceca5 | 390 | |
9b2fadda BH |
391 | /* Helpers for priv. check */ |
392 | #define GEN_PRIV \ | |
393 | do { \ | |
394 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ | |
395 | } while (0) | |
396 | ||
397 | #if defined(CONFIG_USER_ONLY) | |
398 | #define CHK_HV GEN_PRIV | |
399 | #define CHK_SV GEN_PRIV | |
b7815375 | 400 | #define CHK_HVRM GEN_PRIV |
9b2fadda BH |
401 | #else |
402 | #define CHK_HV \ | |
403 | do { \ | |
404 | if (unlikely(ctx->pr || !ctx->hv)) { \ | |
405 | GEN_PRIV; \ | |
406 | } \ | |
407 | } while (0) | |
408 | #define CHK_SV \ | |
409 | do { \ | |
410 | if (unlikely(ctx->pr)) { \ | |
411 | GEN_PRIV; \ | |
412 | } \ | |
413 | } while (0) | |
b7815375 BH |
414 | #define CHK_HVRM \ |
415 | do { \ | |
416 | if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ | |
417 | GEN_PRIV; \ | |
418 | } \ | |
419 | } while (0) | |
9b2fadda BH |
420 | #endif |
421 | ||
422 | #define CHK_NONE | |
423 | ||
a750fc0b | 424 | /*****************************************************************************/ |
a750fc0b | 425 | /* PowerPC instructions table */ |
933dc6eb | 426 | |
76a66253 | 427 | #if defined(DO_PPC_STATISTICS) |
a5858d7a | 428 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 429 | { \ |
79aceca5 FB |
430 | .opc1 = op1, \ |
431 | .opc2 = op2, \ | |
432 | .opc3 = op3, \ | |
323ad19b | 433 | .opc4 = 0xff, \ |
79aceca5 | 434 | .handler = { \ |
70560da7 FC |
435 | .inval1 = invl, \ |
436 | .type = _typ, \ | |
437 | .type2 = _typ2, \ | |
438 | .handler = &gen_##name, \ | |
439 | .oname = stringify(name), \ | |
440 | }, \ | |
441 | .oname = stringify(name), \ | |
442 | } | |
443 | #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ | |
444 | { \ | |
445 | .opc1 = op1, \ | |
446 | .opc2 = op2, \ | |
447 | .opc3 = op3, \ | |
323ad19b | 448 | .opc4 = 0xff, \ |
70560da7 FC |
449 | .handler = { \ |
450 | .inval1 = invl1, \ | |
451 | .inval2 = invl2, \ | |
9a64fbe4 | 452 | .type = _typ, \ |
a5858d7a | 453 | .type2 = _typ2, \ |
79aceca5 | 454 | .handler = &gen_##name, \ |
76a66253 | 455 | .oname = stringify(name), \ |
79aceca5 | 456 | }, \ |
3fc6c082 | 457 | .oname = stringify(name), \ |
79aceca5 | 458 | } |
a5858d7a | 459 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 460 | { \ |
c7697e1f JM |
461 | .opc1 = op1, \ |
462 | .opc2 = op2, \ | |
463 | .opc3 = op3, \ | |
323ad19b | 464 | .opc4 = 0xff, \ |
c7697e1f | 465 | .handler = { \ |
70560da7 | 466 | .inval1 = invl, \ |
c7697e1f | 467 | .type = _typ, \ |
a5858d7a | 468 | .type2 = _typ2, \ |
c7697e1f JM |
469 | .handler = &gen_##name, \ |
470 | .oname = onam, \ | |
471 | }, \ | |
472 | .oname = onam, \ | |
473 | } | |
323ad19b ND |
474 | #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ |
475 | { \ | |
476 | .opc1 = op1, \ | |
477 | .opc2 = op2, \ | |
478 | .opc3 = op3, \ | |
479 | .opc4 = op4, \ | |
480 | .handler = { \ | |
481 | .inval1 = invl, \ | |
482 | .type = _typ, \ | |
483 | .type2 = _typ2, \ | |
484 | .handler = &gen_##name, \ | |
485 | .oname = stringify(name), \ | |
486 | }, \ | |
487 | .oname = stringify(name), \ | |
488 | } | |
14fd8ab2 ND |
489 | #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ |
490 | { \ | |
491 | .opc1 = op1, \ | |
492 | .opc2 = op2, \ | |
493 | .opc3 = op3, \ | |
494 | .opc4 = op4, \ | |
495 | .handler = { \ | |
496 | .inval1 = invl, \ | |
497 | .type = _typ, \ | |
498 | .type2 = _typ2, \ | |
499 | .handler = &gen_##name, \ | |
500 | .oname = onam, \ | |
501 | }, \ | |
502 | .oname = onam, \ | |
503 | } | |
76a66253 | 504 | #else |
a5858d7a | 505 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 506 | { \ |
c7697e1f JM |
507 | .opc1 = op1, \ |
508 | .opc2 = op2, \ | |
509 | .opc3 = op3, \ | |
323ad19b | 510 | .opc4 = 0xff, \ |
c7697e1f | 511 | .handler = { \ |
70560da7 FC |
512 | .inval1 = invl, \ |
513 | .type = _typ, \ | |
514 | .type2 = _typ2, \ | |
515 | .handler = &gen_##name, \ | |
516 | }, \ | |
517 | .oname = stringify(name), \ | |
518 | } | |
519 | #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ | |
520 | { \ | |
521 | .opc1 = op1, \ | |
522 | .opc2 = op2, \ | |
523 | .opc3 = op3, \ | |
323ad19b | 524 | .opc4 = 0xff, \ |
70560da7 FC |
525 | .handler = { \ |
526 | .inval1 = invl1, \ | |
527 | .inval2 = invl2, \ | |
c7697e1f | 528 | .type = _typ, \ |
a5858d7a | 529 | .type2 = _typ2, \ |
c7697e1f | 530 | .handler = &gen_##name, \ |
5c55ff99 BS |
531 | }, \ |
532 | .oname = stringify(name), \ | |
533 | } | |
a5858d7a | 534 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 BS |
535 | { \ |
536 | .opc1 = op1, \ | |
537 | .opc2 = op2, \ | |
538 | .opc3 = op3, \ | |
323ad19b | 539 | .opc4 = 0xff, \ |
5c55ff99 | 540 | .handler = { \ |
70560da7 | 541 | .inval1 = invl, \ |
5c55ff99 | 542 | .type = _typ, \ |
a5858d7a | 543 | .type2 = _typ2, \ |
5c55ff99 BS |
544 | .handler = &gen_##name, \ |
545 | }, \ | |
546 | .oname = onam, \ | |
547 | } | |
323ad19b ND |
548 | #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ |
549 | { \ | |
550 | .opc1 = op1, \ | |
551 | .opc2 = op2, \ | |
552 | .opc3 = op3, \ | |
553 | .opc4 = op4, \ | |
554 | .handler = { \ | |
555 | .inval1 = invl, \ | |
556 | .type = _typ, \ | |
557 | .type2 = _typ2, \ | |
558 | .handler = &gen_##name, \ | |
559 | }, \ | |
560 | .oname = stringify(name), \ | |
561 | } | |
14fd8ab2 ND |
562 | #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ |
563 | { \ | |
564 | .opc1 = op1, \ | |
565 | .opc2 = op2, \ | |
566 | .opc3 = op3, \ | |
567 | .opc4 = op4, \ | |
568 | .handler = { \ | |
569 | .inval1 = invl, \ | |
570 | .type = _typ, \ | |
571 | .type2 = _typ2, \ | |
572 | .handler = &gen_##name, \ | |
573 | }, \ | |
574 | .oname = onam, \ | |
575 | } | |
5c55ff99 | 576 | #endif |
2e610050 | 577 | |
5c55ff99 | 578 | /* SPR load/store helpers */ |
636aa200 | 579 | static inline void gen_load_spr(TCGv t, int reg) |
5c55ff99 | 580 | { |
1328c2bf | 581 | tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); |
5c55ff99 | 582 | } |
2e610050 | 583 | |
636aa200 | 584 | static inline void gen_store_spr(int reg, TCGv t) |
5c55ff99 | 585 | { |
1328c2bf | 586 | tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); |
5c55ff99 | 587 | } |
2e610050 | 588 | |
54623277 | 589 | /* Invalid instruction */ |
99e300ef | 590 | static void gen_invalid(DisasContext *ctx) |
9a64fbe4 | 591 | { |
e06fcd75 | 592 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
9a64fbe4 FB |
593 | } |
594 | ||
c227f099 | 595 | static opc_handler_t invalid_handler = { |
70560da7 FC |
596 | .inval1 = 0xFFFFFFFF, |
597 | .inval2 = 0xFFFFFFFF, | |
9a64fbe4 | 598 | .type = PPC_NONE, |
a5858d7a | 599 | .type2 = PPC_NONE, |
79aceca5 FB |
600 | .handler = gen_invalid, |
601 | }; | |
602 | ||
e1571908 AJ |
603 | /*** Integer comparison ***/ |
604 | ||
636aa200 | 605 | static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) |
e1571908 | 606 | { |
2fdcb629 | 607 | TCGv t0 = tcg_temp_new(); |
b62b3686 PB |
608 | TCGv t1 = tcg_temp_new(); |
609 | TCGv_i32 t = tcg_temp_new_i32(); | |
e1571908 | 610 | |
b62b3686 PB |
611 | tcg_gen_movi_tl(t0, CRF_EQ); |
612 | tcg_gen_movi_tl(t1, CRF_LT); | |
613 | tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), t0, arg0, arg1, t1, t0); | |
614 | tcg_gen_movi_tl(t1, CRF_GT); | |
615 | tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), t0, arg0, arg1, t1, t0); | |
2fdcb629 | 616 | |
b62b3686 PB |
617 | tcg_gen_trunc_tl_i32(t, t0); |
618 | tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); | |
619 | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); | |
2fdcb629 RH |
620 | |
621 | tcg_temp_free(t0); | |
b62b3686 PB |
622 | tcg_temp_free(t1); |
623 | tcg_temp_free_i32(t); | |
e1571908 AJ |
624 | } |
625 | ||
636aa200 | 626 | static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) |
e1571908 | 627 | { |
2fdcb629 | 628 | TCGv t0 = tcg_const_tl(arg1); |
ea363694 AJ |
629 | gen_op_cmp(arg0, t0, s, crf); |
630 | tcg_temp_free(t0); | |
e1571908 AJ |
631 | } |
632 | ||
636aa200 | 633 | static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) |
e1571908 | 634 | { |
ea363694 | 635 | TCGv t0, t1; |
2fdcb629 RH |
636 | t0 = tcg_temp_new(); |
637 | t1 = tcg_temp_new(); | |
e1571908 | 638 | if (s) { |
ea363694 AJ |
639 | tcg_gen_ext32s_tl(t0, arg0); |
640 | tcg_gen_ext32s_tl(t1, arg1); | |
e1571908 | 641 | } else { |
ea363694 AJ |
642 | tcg_gen_ext32u_tl(t0, arg0); |
643 | tcg_gen_ext32u_tl(t1, arg1); | |
e1571908 | 644 | } |
ea363694 AJ |
645 | gen_op_cmp(t0, t1, s, crf); |
646 | tcg_temp_free(t1); | |
647 | tcg_temp_free(t0); | |
e1571908 AJ |
648 | } |
649 | ||
636aa200 | 650 | static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) |
e1571908 | 651 | { |
2fdcb629 | 652 | TCGv t0 = tcg_const_tl(arg1); |
ea363694 AJ |
653 | gen_op_cmp32(arg0, t0, s, crf); |
654 | tcg_temp_free(t0); | |
e1571908 | 655 | } |
e1571908 | 656 | |
636aa200 | 657 | static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) |
e1571908 | 658 | { |
02765534 | 659 | if (NARROW_MODE(ctx)) { |
e1571908 | 660 | gen_op_cmpi32(reg, 0, 1, 0); |
02765534 | 661 | } else { |
e1571908 | 662 | gen_op_cmpi(reg, 0, 1, 0); |
02765534 | 663 | } |
e1571908 AJ |
664 | } |
665 | ||
666 | /* cmp */ | |
99e300ef | 667 | static void gen_cmp(DisasContext *ctx) |
e1571908 | 668 | { |
36f48d9c | 669 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
670 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
671 | 1, crfD(ctx->opcode)); | |
36f48d9c AG |
672 | } else { |
673 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
674 | 1, crfD(ctx->opcode)); | |
02765534 | 675 | } |
e1571908 AJ |
676 | } |
677 | ||
678 | /* cmpi */ | |
99e300ef | 679 | static void gen_cmpi(DisasContext *ctx) |
e1571908 | 680 | { |
36f48d9c | 681 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
682 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), |
683 | 1, crfD(ctx->opcode)); | |
36f48d9c AG |
684 | } else { |
685 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), | |
686 | 1, crfD(ctx->opcode)); | |
02765534 | 687 | } |
e1571908 AJ |
688 | } |
689 | ||
690 | /* cmpl */ | |
99e300ef | 691 | static void gen_cmpl(DisasContext *ctx) |
e1571908 | 692 | { |
36f48d9c | 693 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
694 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
695 | 0, crfD(ctx->opcode)); | |
36f48d9c AG |
696 | } else { |
697 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
698 | 0, crfD(ctx->opcode)); | |
02765534 | 699 | } |
e1571908 AJ |
700 | } |
701 | ||
702 | /* cmpli */ | |
99e300ef | 703 | static void gen_cmpli(DisasContext *ctx) |
e1571908 | 704 | { |
36f48d9c | 705 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
706 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), |
707 | 0, crfD(ctx->opcode)); | |
36f48d9c AG |
708 | } else { |
709 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), | |
710 | 0, crfD(ctx->opcode)); | |
02765534 | 711 | } |
e1571908 AJ |
712 | } |
713 | ||
f2442ef9 ND |
714 | /* cmprb - range comparison: isupper, isaplha, islower*/ |
715 | static void gen_cmprb(DisasContext *ctx) | |
716 | { | |
717 | TCGv_i32 src1 = tcg_temp_new_i32(); | |
718 | TCGv_i32 src2 = tcg_temp_new_i32(); | |
719 | TCGv_i32 src2lo = tcg_temp_new_i32(); | |
720 | TCGv_i32 src2hi = tcg_temp_new_i32(); | |
721 | TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; | |
722 | ||
723 | tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); | |
724 | tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); | |
725 | ||
726 | tcg_gen_andi_i32(src1, src1, 0xFF); | |
727 | tcg_gen_ext8u_i32(src2lo, src2); | |
728 | tcg_gen_shri_i32(src2, src2, 8); | |
729 | tcg_gen_ext8u_i32(src2hi, src2); | |
730 | ||
731 | tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); | |
732 | tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); | |
733 | tcg_gen_and_i32(crf, src2lo, src2hi); | |
734 | ||
735 | if (ctx->opcode & 0x00200000) { | |
736 | tcg_gen_shri_i32(src2, src2, 8); | |
737 | tcg_gen_ext8u_i32(src2lo, src2); | |
738 | tcg_gen_shri_i32(src2, src2, 8); | |
739 | tcg_gen_ext8u_i32(src2hi, src2); | |
740 | tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); | |
741 | tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); | |
742 | tcg_gen_and_i32(src2lo, src2lo, src2hi); | |
743 | tcg_gen_or_i32(crf, crf, src2lo); | |
744 | } | |
efa73196 | 745 | tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); |
f2442ef9 ND |
746 | tcg_temp_free_i32(src1); |
747 | tcg_temp_free_i32(src2); | |
748 | tcg_temp_free_i32(src2lo); | |
749 | tcg_temp_free_i32(src2hi); | |
750 | } | |
751 | ||
082ce330 ND |
752 | #if defined(TARGET_PPC64) |
753 | /* cmpeqb */ | |
754 | static void gen_cmpeqb(DisasContext *ctx) | |
755 | { | |
756 | gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
757 | cpu_gpr[rB(ctx->opcode)]); | |
758 | } | |
759 | #endif | |
760 | ||
e1571908 | 761 | /* isel (PowerPC 2.03 specification) */ |
99e300ef | 762 | static void gen_isel(DisasContext *ctx) |
e1571908 | 763 | { |
e1571908 | 764 | uint32_t bi = rC(ctx->opcode); |
24f9cd95 RH |
765 | uint32_t mask = 0x08 >> (bi & 0x03); |
766 | TCGv t0 = tcg_temp_new(); | |
767 | TCGv zr; | |
e1571908 | 768 | |
24f9cd95 RH |
769 | tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); |
770 | tcg_gen_andi_tl(t0, t0, mask); | |
771 | ||
772 | zr = tcg_const_tl(0); | |
773 | tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, | |
774 | rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, | |
775 | cpu_gpr[rB(ctx->opcode)]); | |
776 | tcg_temp_free(zr); | |
777 | tcg_temp_free(t0); | |
e1571908 AJ |
778 | } |
779 | ||
fcfda20f AJ |
780 | /* cmpb: PowerPC 2.05 specification */ |
781 | static void gen_cmpb(DisasContext *ctx) | |
782 | { | |
783 | gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], | |
784 | cpu_gpr[rB(ctx->opcode)]); | |
785 | } | |
786 | ||
79aceca5 | 787 | /*** Integer arithmetic ***/ |
79aceca5 | 788 | |
636aa200 BS |
789 | static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, |
790 | TCGv arg1, TCGv arg2, int sub) | |
74637406 | 791 | { |
ffe30937 | 792 | TCGv t0 = tcg_temp_new(); |
79aceca5 | 793 | |
8e7a6db9 | 794 | tcg_gen_xor_tl(cpu_ov, arg0, arg2); |
74637406 | 795 | tcg_gen_xor_tl(t0, arg1, arg2); |
ffe30937 RH |
796 | if (sub) { |
797 | tcg_gen_and_tl(cpu_ov, cpu_ov, t0); | |
798 | } else { | |
799 | tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); | |
800 | } | |
801 | tcg_temp_free(t0); | |
02765534 | 802 | if (NARROW_MODE(ctx)) { |
dc0ad844 ND |
803 | tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); |
804 | if (is_isa300(ctx)) { | |
805 | tcg_gen_mov_tl(cpu_ov32, cpu_ov); | |
806 | } | |
807 | } else { | |
808 | if (is_isa300(ctx)) { | |
809 | tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); | |
810 | } | |
38a61d34 | 811 | tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); |
ffe30937 | 812 | } |
ffe30937 | 813 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); |
79aceca5 FB |
814 | } |
815 | ||
6b10d008 ND |
816 | static inline void gen_op_arith_compute_ca32(DisasContext *ctx, |
817 | TCGv res, TCGv arg0, TCGv arg1, | |
818 | int sub) | |
819 | { | |
820 | TCGv t0; | |
821 | ||
822 | if (!is_isa300(ctx)) { | |
823 | return; | |
824 | } | |
825 | ||
826 | t0 = tcg_temp_new(); | |
33903d0a ND |
827 | if (sub) { |
828 | tcg_gen_eqv_tl(t0, arg0, arg1); | |
829 | } else { | |
830 | tcg_gen_xor_tl(t0, arg0, arg1); | |
831 | } | |
6b10d008 ND |
832 | tcg_gen_xor_tl(t0, t0, res); |
833 | tcg_gen_extract_tl(cpu_ca32, t0, 32, 1); | |
834 | tcg_temp_free(t0); | |
835 | } | |
836 | ||
74637406 | 837 | /* Common add function */ |
636aa200 | 838 | static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
b5a73f8d RH |
839 | TCGv arg2, bool add_ca, bool compute_ca, |
840 | bool compute_ov, bool compute_rc0) | |
74637406 | 841 | { |
b5a73f8d | 842 | TCGv t0 = ret; |
d9bce9d9 | 843 | |
752d634e | 844 | if (compute_ca || compute_ov) { |
146de60d | 845 | t0 = tcg_temp_new(); |
74637406 | 846 | } |
79aceca5 | 847 | |
da91a00f | 848 | if (compute_ca) { |
79482e5a | 849 | if (NARROW_MODE(ctx)) { |
752d634e RH |
850 | /* Caution: a non-obvious corner case of the spec is that we |
851 | must produce the *entire* 64-bit addition, but produce the | |
852 | carry into bit 32. */ | |
79482e5a | 853 | TCGv t1 = tcg_temp_new(); |
752d634e RH |
854 | tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ |
855 | tcg_gen_add_tl(t0, arg1, arg2); | |
79482e5a RH |
856 | if (add_ca) { |
857 | tcg_gen_add_tl(t0, t0, cpu_ca); | |
858 | } | |
752d634e RH |
859 | tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */ |
860 | tcg_temp_free(t1); | |
e2622073 | 861 | tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); |
6b10d008 ND |
862 | if (is_isa300(ctx)) { |
863 | tcg_gen_mov_tl(cpu_ca32, cpu_ca); | |
864 | } | |
b5a73f8d | 865 | } else { |
79482e5a RH |
866 | TCGv zero = tcg_const_tl(0); |
867 | if (add_ca) { | |
868 | tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero); | |
869 | tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero); | |
870 | } else { | |
871 | tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero); | |
872 | } | |
6b10d008 | 873 | gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 0); |
79482e5a | 874 | tcg_temp_free(zero); |
b5a73f8d | 875 | } |
b5a73f8d RH |
876 | } else { |
877 | tcg_gen_add_tl(t0, arg1, arg2); | |
878 | if (add_ca) { | |
879 | tcg_gen_add_tl(t0, t0, cpu_ca); | |
880 | } | |
da91a00f | 881 | } |
79aceca5 | 882 | |
74637406 AJ |
883 | if (compute_ov) { |
884 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); | |
885 | } | |
b5a73f8d | 886 | if (unlikely(compute_rc0)) { |
74637406 | 887 | gen_set_Rc0(ctx, t0); |
b5a73f8d | 888 | } |
74637406 | 889 | |
11f4e8f8 | 890 | if (t0 != ret) { |
74637406 AJ |
891 | tcg_gen_mov_tl(ret, t0); |
892 | tcg_temp_free(t0); | |
893 | } | |
39dd32ee | 894 | } |
74637406 AJ |
895 | /* Add functions with two operands */ |
896 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 897 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
898 | { \ |
899 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
900 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
b5a73f8d | 901 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
902 | } |
903 | /* Add functions with one operand and one immediate */ | |
904 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ | |
905 | add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 906 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 907 | { \ |
b5a73f8d | 908 | TCGv t0 = tcg_const_tl(const_val); \ |
74637406 AJ |
909 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ |
910 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
b5a73f8d | 911 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
912 | tcg_temp_free(t0); \ |
913 | } | |
914 | ||
915 | /* add add. addo addo. */ | |
916 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) | |
917 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) | |
918 | /* addc addc. addco addco. */ | |
919 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) | |
920 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) | |
921 | /* adde adde. addeo addeo. */ | |
922 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) | |
923 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) | |
924 | /* addme addme. addmeo addmeo. */ | |
925 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) | |
926 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) | |
927 | /* addze addze. addzeo addzeo.*/ | |
928 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) | |
929 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) | |
930 | /* addi */ | |
99e300ef | 931 | static void gen_addi(DisasContext *ctx) |
d9bce9d9 | 932 | { |
74637406 AJ |
933 | target_long simm = SIMM(ctx->opcode); |
934 | ||
935 | if (rA(ctx->opcode) == 0) { | |
936 | /* li case */ | |
937 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); | |
938 | } else { | |
b5a73f8d RH |
939 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], |
940 | cpu_gpr[rA(ctx->opcode)], simm); | |
74637406 | 941 | } |
d9bce9d9 | 942 | } |
74637406 | 943 | /* addic addic.*/ |
b5a73f8d | 944 | static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) |
d9bce9d9 | 945 | { |
b5a73f8d RH |
946 | TCGv c = tcg_const_tl(SIMM(ctx->opcode)); |
947 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
948 | c, 0, 1, 0, compute_rc0); | |
949 | tcg_temp_free(c); | |
d9bce9d9 | 950 | } |
99e300ef BS |
951 | |
952 | static void gen_addic(DisasContext *ctx) | |
d9bce9d9 | 953 | { |
b5a73f8d | 954 | gen_op_addic(ctx, 0); |
d9bce9d9 | 955 | } |
e8eaa2c0 BS |
956 | |
957 | static void gen_addic_(DisasContext *ctx) | |
d9bce9d9 | 958 | { |
b5a73f8d | 959 | gen_op_addic(ctx, 1); |
d9bce9d9 | 960 | } |
99e300ef | 961 | |
54623277 | 962 | /* addis */ |
99e300ef | 963 | static void gen_addis(DisasContext *ctx) |
d9bce9d9 | 964 | { |
74637406 AJ |
965 | target_long simm = SIMM(ctx->opcode); |
966 | ||
967 | if (rA(ctx->opcode) == 0) { | |
968 | /* lis case */ | |
969 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); | |
970 | } else { | |
b5a73f8d RH |
971 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], |
972 | cpu_gpr[rA(ctx->opcode)], simm << 16); | |
74637406 | 973 | } |
d9bce9d9 | 974 | } |
74637406 | 975 | |
c5b2b9ce ND |
976 | /* addpcis */ |
977 | static void gen_addpcis(DisasContext *ctx) | |
978 | { | |
979 | target_long d = DX(ctx->opcode); | |
980 | ||
b6bac4bc | 981 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16)); |
c5b2b9ce ND |
982 | } |
983 | ||
636aa200 BS |
984 | static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, |
985 | TCGv arg2, int sign, int compute_ov) | |
d9bce9d9 | 986 | { |
b07c32dc ND |
987 | TCGv_i32 t0 = tcg_temp_new_i32(); |
988 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
989 | TCGv_i32 t2 = tcg_temp_new_i32(); | |
990 | TCGv_i32 t3 = tcg_temp_new_i32(); | |
74637406 | 991 | |
2ef1b120 AJ |
992 | tcg_gen_trunc_tl_i32(t0, arg1); |
993 | tcg_gen_trunc_tl_i32(t1, arg2); | |
74637406 | 994 | if (sign) { |
b07c32dc ND |
995 | tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); |
996 | tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); | |
997 | tcg_gen_and_i32(t2, t2, t3); | |
998 | tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); | |
999 | tcg_gen_or_i32(t2, t2, t3); | |
1000 | tcg_gen_movi_i32(t3, 0); | |
1001 | tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1002 | tcg_gen_div_i32(t3, t0, t1); | |
1003 | tcg_gen_extu_i32_tl(ret, t3); | |
74637406 | 1004 | } else { |
b07c32dc ND |
1005 | tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); |
1006 | tcg_gen_movi_i32(t3, 0); | |
1007 | tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1008 | tcg_gen_divu_i32(t3, t0, t1); | |
1009 | tcg_gen_extu_i32_tl(ret, t3); | |
74637406 AJ |
1010 | } |
1011 | if (compute_ov) { | |
b07c32dc | 1012 | tcg_gen_extu_i32_tl(cpu_ov, t2); |
c44027ff ND |
1013 | if (is_isa300(ctx)) { |
1014 | tcg_gen_extu_i32_tl(cpu_ov32, t2); | |
1015 | } | |
b07c32dc | 1016 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); |
74637406 | 1017 | } |
a7812ae4 PB |
1018 | tcg_temp_free_i32(t0); |
1019 | tcg_temp_free_i32(t1); | |
b07c32dc ND |
1020 | tcg_temp_free_i32(t2); |
1021 | tcg_temp_free_i32(t3); | |
1022 | ||
74637406 AJ |
1023 | if (unlikely(Rc(ctx->opcode) != 0)) |
1024 | gen_set_Rc0(ctx, ret); | |
d9bce9d9 | 1025 | } |
74637406 AJ |
1026 | /* Div functions */ |
1027 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ | |
99e300ef | 1028 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
1029 | { \ |
1030 | gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1031 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1032 | sign, compute_ov); \ | |
1033 | } | |
1034 | /* divwu divwu. divwuo divwuo. */ | |
1035 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); | |
1036 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); | |
1037 | /* divw divw. divwo divwo. */ | |
1038 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); | |
1039 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); | |
98d1eb27 TM |
1040 | |
1041 | /* div[wd]eu[o][.] */ | |
1042 | #define GEN_DIVE(name, hlpr, compute_ov) \ | |
1043 | static void gen_##name(DisasContext *ctx) \ | |
1044 | { \ | |
1045 | TCGv_i32 t0 = tcg_const_i32(compute_ov); \ | |
1046 | gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ | |
1047 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ | |
1048 | tcg_temp_free_i32(t0); \ | |
1049 | if (unlikely(Rc(ctx->opcode) != 0)) { \ | |
1050 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ | |
1051 | } \ | |
1052 | } | |
1053 | ||
6a4fda33 TM |
1054 | GEN_DIVE(divweu, divweu, 0); |
1055 | GEN_DIVE(divweuo, divweu, 1); | |
a98eb9e9 TM |
1056 | GEN_DIVE(divwe, divwe, 0); |
1057 | GEN_DIVE(divweo, divwe, 1); | |
6a4fda33 | 1058 | |
d9bce9d9 | 1059 | #if defined(TARGET_PPC64) |
636aa200 BS |
1060 | static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, |
1061 | TCGv arg2, int sign, int compute_ov) | |
d9bce9d9 | 1062 | { |
4110b586 ND |
1063 | TCGv_i64 t0 = tcg_temp_new_i64(); |
1064 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1065 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1066 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
74637406 | 1067 | |
4110b586 ND |
1068 | tcg_gen_mov_i64(t0, arg1); |
1069 | tcg_gen_mov_i64(t1, arg2); | |
74637406 | 1070 | if (sign) { |
4110b586 ND |
1071 | tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); |
1072 | tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); | |
1073 | tcg_gen_and_i64(t2, t2, t3); | |
1074 | tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); | |
1075 | tcg_gen_or_i64(t2, t2, t3); | |
1076 | tcg_gen_movi_i64(t3, 0); | |
1077 | tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1078 | tcg_gen_div_i64(ret, t0, t1); | |
74637406 | 1079 | } else { |
4110b586 ND |
1080 | tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); |
1081 | tcg_gen_movi_i64(t3, 0); | |
1082 | tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1083 | tcg_gen_divu_i64(ret, t0, t1); | |
74637406 AJ |
1084 | } |
1085 | if (compute_ov) { | |
4110b586 | 1086 | tcg_gen_mov_tl(cpu_ov, t2); |
c44027ff ND |
1087 | if (is_isa300(ctx)) { |
1088 | tcg_gen_mov_tl(cpu_ov32, t2); | |
1089 | } | |
4110b586 | 1090 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); |
74637406 | 1091 | } |
4110b586 ND |
1092 | tcg_temp_free_i64(t0); |
1093 | tcg_temp_free_i64(t1); | |
1094 | tcg_temp_free_i64(t2); | |
1095 | tcg_temp_free_i64(t3); | |
1096 | ||
74637406 AJ |
1097 | if (unlikely(Rc(ctx->opcode) != 0)) |
1098 | gen_set_Rc0(ctx, ret); | |
d9bce9d9 | 1099 | } |
4110b586 | 1100 | |
74637406 | 1101 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ |
99e300ef | 1102 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 1103 | { \ |
2ef1b120 AJ |
1104 | gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1105 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1106 | sign, compute_ov); \ | |
74637406 | 1107 | } |
c44027ff | 1108 | /* divdu divdu. divduo divduo. */ |
74637406 AJ |
1109 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); |
1110 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); | |
c44027ff | 1111 | /* divd divd. divdo divdo. */ |
74637406 AJ |
1112 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); |
1113 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); | |
98d1eb27 TM |
1114 | |
1115 | GEN_DIVE(divdeu, divdeu, 0); | |
1116 | GEN_DIVE(divdeuo, divdeu, 1); | |
e44259b6 TM |
1117 | GEN_DIVE(divde, divde, 0); |
1118 | GEN_DIVE(divdeo, divde, 1); | |
d9bce9d9 | 1119 | #endif |
74637406 | 1120 | |
af2c6620 ND |
1121 | static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, |
1122 | TCGv arg2, int sign) | |
1123 | { | |
1124 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
1125 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
1126 | ||
1127 | tcg_gen_trunc_tl_i32(t0, arg1); | |
1128 | tcg_gen_trunc_tl_i32(t1, arg2); | |
1129 | if (sign) { | |
1130 | TCGv_i32 t2 = tcg_temp_new_i32(); | |
1131 | TCGv_i32 t3 = tcg_temp_new_i32(); | |
1132 | tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); | |
1133 | tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); | |
1134 | tcg_gen_and_i32(t2, t2, t3); | |
1135 | tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); | |
1136 | tcg_gen_or_i32(t2, t2, t3); | |
1137 | tcg_gen_movi_i32(t3, 0); | |
1138 | tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1139 | tcg_gen_rem_i32(t3, t0, t1); | |
1140 | tcg_gen_ext_i32_tl(ret, t3); | |
1141 | tcg_temp_free_i32(t2); | |
1142 | tcg_temp_free_i32(t3); | |
1143 | } else { | |
1144 | TCGv_i32 t2 = tcg_const_i32(1); | |
1145 | TCGv_i32 t3 = tcg_const_i32(0); | |
1146 | tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); | |
1147 | tcg_gen_remu_i32(t3, t0, t1); | |
1148 | tcg_gen_extu_i32_tl(ret, t3); | |
1149 | tcg_temp_free_i32(t2); | |
1150 | tcg_temp_free_i32(t3); | |
1151 | } | |
1152 | tcg_temp_free_i32(t0); | |
1153 | tcg_temp_free_i32(t1); | |
1154 | } | |
1155 | ||
1156 | #define GEN_INT_ARITH_MODW(name, opc3, sign) \ | |
1157 | static void glue(gen_, name)(DisasContext *ctx) \ | |
1158 | { \ | |
1159 | gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1160 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1161 | sign); \ | |
1162 | } | |
1163 | ||
1164 | GEN_INT_ARITH_MODW(moduw, 0x08, 0); | |
1165 | GEN_INT_ARITH_MODW(modsw, 0x18, 1); | |
1166 | ||
063cf14f ND |
1167 | #if defined(TARGET_PPC64) |
1168 | static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, | |
1169 | TCGv arg2, int sign) | |
1170 | { | |
1171 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
1172 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1173 | ||
1174 | tcg_gen_mov_i64(t0, arg1); | |
1175 | tcg_gen_mov_i64(t1, arg2); | |
1176 | if (sign) { | |
1177 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1178 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
1179 | tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); | |
1180 | tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); | |
1181 | tcg_gen_and_i64(t2, t2, t3); | |
1182 | tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); | |
1183 | tcg_gen_or_i64(t2, t2, t3); | |
1184 | tcg_gen_movi_i64(t3, 0); | |
1185 | tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1186 | tcg_gen_rem_i64(ret, t0, t1); | |
1187 | tcg_temp_free_i64(t2); | |
1188 | tcg_temp_free_i64(t3); | |
1189 | } else { | |
1190 | TCGv_i64 t2 = tcg_const_i64(1); | |
1191 | TCGv_i64 t3 = tcg_const_i64(0); | |
1192 | tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); | |
1193 | tcg_gen_remu_i64(ret, t0, t1); | |
1194 | tcg_temp_free_i64(t2); | |
1195 | tcg_temp_free_i64(t3); | |
1196 | } | |
1197 | tcg_temp_free_i64(t0); | |
1198 | tcg_temp_free_i64(t1); | |
1199 | } | |
1200 | ||
1201 | #define GEN_INT_ARITH_MODD(name, opc3, sign) \ | |
1202 | static void glue(gen_, name)(DisasContext *ctx) \ | |
1203 | { \ | |
1204 | gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1205 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1206 | sign); \ | |
1207 | } | |
1208 | ||
1209 | GEN_INT_ARITH_MODD(modud, 0x08, 0); | |
1210 | GEN_INT_ARITH_MODD(modsd, 0x18, 1); | |
1211 | #endif | |
1212 | ||
74637406 | 1213 | /* mulhw mulhw. */ |
99e300ef | 1214 | static void gen_mulhw(DisasContext *ctx) |
d9bce9d9 | 1215 | { |
23ad1d5d RH |
1216 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1217 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1218 | |
23ad1d5d RH |
1219 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1220 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1221 | tcg_gen_muls2_i32(t0, t1, t0, t1); | |
1222 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
1223 | tcg_temp_free_i32(t0); | |
1224 | tcg_temp_free_i32(t1); | |
74637406 AJ |
1225 | if (unlikely(Rc(ctx->opcode) != 0)) |
1226 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1227 | } |
99e300ef | 1228 | |
54623277 | 1229 | /* mulhwu mulhwu. */ |
99e300ef | 1230 | static void gen_mulhwu(DisasContext *ctx) |
d9bce9d9 | 1231 | { |
23ad1d5d RH |
1232 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1233 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1234 | |
23ad1d5d RH |
1235 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1236 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1237 | tcg_gen_mulu2_i32(t0, t1, t0, t1); | |
1238 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
1239 | tcg_temp_free_i32(t0); | |
1240 | tcg_temp_free_i32(t1); | |
74637406 AJ |
1241 | if (unlikely(Rc(ctx->opcode) != 0)) |
1242 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1243 | } |
99e300ef | 1244 | |
54623277 | 1245 | /* mullw mullw. */ |
99e300ef | 1246 | static void gen_mullw(DisasContext *ctx) |
d9bce9d9 | 1247 | { |
1fa74845 TM |
1248 | #if defined(TARGET_PPC64) |
1249 | TCGv_i64 t0, t1; | |
1250 | t0 = tcg_temp_new_i64(); | |
1251 | t1 = tcg_temp_new_i64(); | |
1252 | tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); | |
1253 | tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); | |
1254 | tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
1255 | tcg_temp_free(t0); | |
1256 | tcg_temp_free(t1); | |
1257 | #else | |
03039e5e TM |
1258 | tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1259 | cpu_gpr[rB(ctx->opcode)]); | |
1fa74845 | 1260 | #endif |
74637406 AJ |
1261 | if (unlikely(Rc(ctx->opcode) != 0)) |
1262 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1263 | } |
99e300ef | 1264 | |
54623277 | 1265 | /* mullwo mullwo. */ |
99e300ef | 1266 | static void gen_mullwo(DisasContext *ctx) |
d9bce9d9 | 1267 | { |
e4a2c846 RH |
1268 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1269 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1270 | |
e4a2c846 RH |
1271 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1272 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1273 | tcg_gen_muls2_i32(t0, t1, t0, t1); | |
f11ebbf8 | 1274 | #if defined(TARGET_PPC64) |
26977876 TM |
1275 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); |
1276 | #else | |
1277 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); | |
f11ebbf8 | 1278 | #endif |
e4a2c846 RH |
1279 | |
1280 | tcg_gen_sari_i32(t0, t0, 31); | |
1281 | tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); | |
1282 | tcg_gen_extu_i32_tl(cpu_ov, t0); | |
61aa9a69 ND |
1283 | if (is_isa300(ctx)) { |
1284 | tcg_gen_mov_tl(cpu_ov32, cpu_ov); | |
1285 | } | |
e4a2c846 RH |
1286 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); |
1287 | ||
1288 | tcg_temp_free_i32(t0); | |
1289 | tcg_temp_free_i32(t1); | |
74637406 AJ |
1290 | if (unlikely(Rc(ctx->opcode) != 0)) |
1291 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1292 | } |
99e300ef | 1293 | |
54623277 | 1294 | /* mulli */ |
99e300ef | 1295 | static void gen_mulli(DisasContext *ctx) |
d9bce9d9 | 1296 | { |
74637406 AJ |
1297 | tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1298 | SIMM(ctx->opcode)); | |
d9bce9d9 | 1299 | } |
23ad1d5d | 1300 | |
d9bce9d9 | 1301 | #if defined(TARGET_PPC64) |
74637406 | 1302 | /* mulhd mulhd. */ |
23ad1d5d RH |
1303 | static void gen_mulhd(DisasContext *ctx) |
1304 | { | |
1305 | TCGv lo = tcg_temp_new(); | |
1306 | tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], | |
1307 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1308 | tcg_temp_free(lo); | |
1309 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1310 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1311 | } | |
1312 | } | |
1313 | ||
74637406 | 1314 | /* mulhdu mulhdu. */ |
23ad1d5d RH |
1315 | static void gen_mulhdu(DisasContext *ctx) |
1316 | { | |
1317 | TCGv lo = tcg_temp_new(); | |
1318 | tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], | |
1319 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1320 | tcg_temp_free(lo); | |
1321 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1322 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1323 | } | |
1324 | } | |
99e300ef | 1325 | |
54623277 | 1326 | /* mulld mulld. */ |
99e300ef | 1327 | static void gen_mulld(DisasContext *ctx) |
d9bce9d9 | 1328 | { |
74637406 AJ |
1329 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1330 | cpu_gpr[rB(ctx->opcode)]); | |
1331 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1332 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1333 | } |
d15f74fb | 1334 | |
74637406 | 1335 | /* mulldo mulldo. */ |
d15f74fb BS |
1336 | static void gen_mulldo(DisasContext *ctx) |
1337 | { | |
22ffad31 TM |
1338 | TCGv_i64 t0 = tcg_temp_new_i64(); |
1339 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1340 | ||
1341 | tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], | |
1342 | cpu_gpr[rB(ctx->opcode)]); | |
1343 | tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); | |
1344 | ||
1345 | tcg_gen_sari_i64(t0, t0, 63); | |
1346 | tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); | |
61aa9a69 ND |
1347 | if (is_isa300(ctx)) { |
1348 | tcg_gen_mov_tl(cpu_ov32, cpu_ov); | |
1349 | } | |
22ffad31 TM |
1350 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); |
1351 | ||
1352 | tcg_temp_free_i64(t0); | |
1353 | tcg_temp_free_i64(t1); | |
1354 | ||
d15f74fb BS |
1355 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1356 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1357 | } | |
1358 | } | |
d9bce9d9 | 1359 | #endif |
74637406 | 1360 | |
74637406 | 1361 | /* Common subf function */ |
636aa200 | 1362 | static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, |
b5a73f8d RH |
1363 | TCGv arg2, bool add_ca, bool compute_ca, |
1364 | bool compute_ov, bool compute_rc0) | |
79aceca5 | 1365 | { |
b5a73f8d | 1366 | TCGv t0 = ret; |
79aceca5 | 1367 | |
752d634e | 1368 | if (compute_ca || compute_ov) { |
b5a73f8d | 1369 | t0 = tcg_temp_new(); |
da91a00f | 1370 | } |
74637406 | 1371 | |
79482e5a RH |
1372 | if (compute_ca) { |
1373 | /* dest = ~arg1 + arg2 [+ ca]. */ | |
1374 | if (NARROW_MODE(ctx)) { | |
752d634e RH |
1375 | /* Caution: a non-obvious corner case of the spec is that we |
1376 | must produce the *entire* 64-bit addition, but produce the | |
1377 | carry into bit 32. */ | |
79482e5a | 1378 | TCGv inv1 = tcg_temp_new(); |
752d634e | 1379 | TCGv t1 = tcg_temp_new(); |
79482e5a | 1380 | tcg_gen_not_tl(inv1, arg1); |
79482e5a | 1381 | if (add_ca) { |
752d634e | 1382 | tcg_gen_add_tl(t0, arg2, cpu_ca); |
79482e5a | 1383 | } else { |
752d634e | 1384 | tcg_gen_addi_tl(t0, arg2, 1); |
79482e5a | 1385 | } |
752d634e | 1386 | tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ |
79482e5a | 1387 | tcg_gen_add_tl(t0, t0, inv1); |
c80d1df5 | 1388 | tcg_temp_free(inv1); |
752d634e RH |
1389 | tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ |
1390 | tcg_temp_free(t1); | |
e2622073 | 1391 | tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); |
33903d0a ND |
1392 | if (is_isa300(ctx)) { |
1393 | tcg_gen_mov_tl(cpu_ca32, cpu_ca); | |
1394 | } | |
79482e5a | 1395 | } else if (add_ca) { |
08f4a0f7 RH |
1396 | TCGv zero, inv1 = tcg_temp_new(); |
1397 | tcg_gen_not_tl(inv1, arg1); | |
b5a73f8d RH |
1398 | zero = tcg_const_tl(0); |
1399 | tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); | |
08f4a0f7 | 1400 | tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); |
33903d0a | 1401 | gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, 0); |
b5a73f8d | 1402 | tcg_temp_free(zero); |
08f4a0f7 | 1403 | tcg_temp_free(inv1); |
b5a73f8d | 1404 | } else { |
79482e5a | 1405 | tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); |
b5a73f8d | 1406 | tcg_gen_sub_tl(t0, arg2, arg1); |
33903d0a | 1407 | gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 1); |
b5a73f8d | 1408 | } |
79482e5a RH |
1409 | } else if (add_ca) { |
1410 | /* Since we're ignoring carry-out, we can simplify the | |
1411 | standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */ | |
1412 | tcg_gen_sub_tl(t0, arg2, arg1); | |
1413 | tcg_gen_add_tl(t0, t0, cpu_ca); | |
1414 | tcg_gen_subi_tl(t0, t0, 1); | |
79aceca5 | 1415 | } else { |
b5a73f8d | 1416 | tcg_gen_sub_tl(t0, arg2, arg1); |
74637406 | 1417 | } |
b5a73f8d | 1418 | |
74637406 AJ |
1419 | if (compute_ov) { |
1420 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); | |
1421 | } | |
b5a73f8d | 1422 | if (unlikely(compute_rc0)) { |
74637406 | 1423 | gen_set_Rc0(ctx, t0); |
b5a73f8d | 1424 | } |
74637406 | 1425 | |
11f4e8f8 | 1426 | if (t0 != ret) { |
74637406 AJ |
1427 | tcg_gen_mov_tl(ret, t0); |
1428 | tcg_temp_free(t0); | |
79aceca5 | 1429 | } |
79aceca5 | 1430 | } |
74637406 AJ |
1431 | /* Sub functions with Two operands functions */ |
1432 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 1433 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
1434 | { \ |
1435 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1436 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
b5a73f8d | 1437 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
1438 | } |
1439 | /* Sub functions with one operand and one immediate */ | |
1440 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ | |
1441 | add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 1442 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 1443 | { \ |
b5a73f8d | 1444 | TCGv t0 = tcg_const_tl(const_val); \ |
74637406 AJ |
1445 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1446 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
b5a73f8d | 1447 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
1448 | tcg_temp_free(t0); \ |
1449 | } | |
1450 | /* subf subf. subfo subfo. */ | |
1451 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) | |
1452 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) | |
1453 | /* subfc subfc. subfco subfco. */ | |
1454 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) | |
1455 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) | |
1456 | /* subfe subfe. subfeo subfo. */ | |
1457 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) | |
1458 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) | |
1459 | /* subfme subfme. subfmeo subfmeo. */ | |
1460 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) | |
1461 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) | |
1462 | /* subfze subfze. subfzeo subfzeo.*/ | |
1463 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) | |
1464 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) | |
99e300ef | 1465 | |
54623277 | 1466 | /* subfic */ |
99e300ef | 1467 | static void gen_subfic(DisasContext *ctx) |
79aceca5 | 1468 | { |
b5a73f8d RH |
1469 | TCGv c = tcg_const_tl(SIMM(ctx->opcode)); |
1470 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
1471 | c, 0, 1, 0, 0); | |
1472 | tcg_temp_free(c); | |
79aceca5 FB |
1473 | } |
1474 | ||
fd3f0081 RH |
1475 | /* neg neg. nego nego. */ |
1476 | static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) | |
1477 | { | |
1478 | TCGv zero = tcg_const_tl(0); | |
1479 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
1480 | zero, 0, 0, compute_ov, Rc(ctx->opcode)); | |
1481 | tcg_temp_free(zero); | |
1482 | } | |
1483 | ||
1484 | static void gen_neg(DisasContext *ctx) | |
1485 | { | |
1480d71c ND |
1486 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
1487 | if (unlikely(Rc(ctx->opcode))) { | |
1488 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1489 | } | |
fd3f0081 RH |
1490 | } |
1491 | ||
1492 | static void gen_nego(DisasContext *ctx) | |
1493 | { | |
1494 | gen_op_arith_neg(ctx, 1); | |
1495 | } | |
1496 | ||
79aceca5 | 1497 | /*** Integer logical ***/ |
26d67362 | 1498 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ |
99e300ef | 1499 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 1500 | { \ |
26d67362 AJ |
1501 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ |
1502 | cpu_gpr[rB(ctx->opcode)]); \ | |
76a66253 | 1503 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
26d67362 | 1504 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
79aceca5 | 1505 | } |
79aceca5 | 1506 | |
26d67362 | 1507 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ |
99e300ef | 1508 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 1509 | { \ |
26d67362 | 1510 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ |
76a66253 | 1511 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
26d67362 | 1512 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
79aceca5 FB |
1513 | } |
1514 | ||
1515 | /* and & and. */ | |
26d67362 | 1516 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); |
79aceca5 | 1517 | /* andc & andc. */ |
26d67362 | 1518 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); |
e8eaa2c0 | 1519 | |
54623277 | 1520 | /* andi. */ |
e8eaa2c0 | 1521 | static void gen_andi_(DisasContext *ctx) |
79aceca5 | 1522 | { |
26d67362 AJ |
1523 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode)); |
1524 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
79aceca5 | 1525 | } |
e8eaa2c0 | 1526 | |
54623277 | 1527 | /* andis. */ |
e8eaa2c0 | 1528 | static void gen_andis_(DisasContext *ctx) |
79aceca5 | 1529 | { |
26d67362 AJ |
1530 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16); |
1531 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
79aceca5 | 1532 | } |
99e300ef | 1533 | |
54623277 | 1534 | /* cntlzw */ |
99e300ef | 1535 | static void gen_cntlzw(DisasContext *ctx) |
26d67362 | 1536 | { |
9b8514e5 RH |
1537 | TCGv_i32 t = tcg_temp_new_i32(); |
1538 | ||
1539 | tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); | |
1540 | tcg_gen_clzi_i32(t, t, 32); | |
1541 | tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); | |
1542 | tcg_temp_free_i32(t); | |
1543 | ||
26d67362 | 1544 | if (unlikely(Rc(ctx->opcode) != 0)) |
2e31f5d3 | 1545 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
26d67362 | 1546 | } |
b35344e4 ND |
1547 | |
1548 | /* cnttzw */ | |
1549 | static void gen_cnttzw(DisasContext *ctx) | |
1550 | { | |
9b8514e5 RH |
1551 | TCGv_i32 t = tcg_temp_new_i32(); |
1552 | ||
1553 | tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); | |
1554 | tcg_gen_ctzi_i32(t, t, 32); | |
1555 | tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); | |
1556 | tcg_temp_free_i32(t); | |
1557 | ||
b35344e4 ND |
1558 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1559 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1560 | } | |
1561 | } | |
1562 | ||
79aceca5 | 1563 | /* eqv & eqv. */ |
26d67362 | 1564 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); |
79aceca5 | 1565 | /* extsb & extsb. */ |
26d67362 | 1566 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); |
79aceca5 | 1567 | /* extsh & extsh. */ |
26d67362 | 1568 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); |
79aceca5 | 1569 | /* nand & nand. */ |
26d67362 | 1570 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); |
79aceca5 | 1571 | /* nor & nor. */ |
26d67362 | 1572 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); |
99e300ef | 1573 | |
7f2b1744 | 1574 | #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) |
b68e60e6 BH |
1575 | static void gen_pause(DisasContext *ctx) |
1576 | { | |
1577 | TCGv_i32 t0 = tcg_const_i32(0); | |
1578 | tcg_gen_st_i32(t0, cpu_env, | |
1579 | -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); | |
1580 | tcg_temp_free_i32(t0); | |
1581 | ||
1582 | /* Stop translation, this gives other CPUs a chance to run */ | |
b6bac4bc | 1583 | gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); |
b68e60e6 BH |
1584 | } |
1585 | #endif /* defined(TARGET_PPC64) */ | |
1586 | ||
54623277 | 1587 | /* or & or. */ |
99e300ef | 1588 | static void gen_or(DisasContext *ctx) |
9a64fbe4 | 1589 | { |
76a66253 JM |
1590 | int rs, ra, rb; |
1591 | ||
1592 | rs = rS(ctx->opcode); | |
1593 | ra = rA(ctx->opcode); | |
1594 | rb = rB(ctx->opcode); | |
1595 | /* Optimisation for mr. ri case */ | |
1596 | if (rs != ra || rs != rb) { | |
26d67362 AJ |
1597 | if (rs != rb) |
1598 | tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); | |
1599 | else | |
1600 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); | |
76a66253 | 1601 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 1602 | gen_set_Rc0(ctx, cpu_gpr[ra]); |
76a66253 | 1603 | } else if (unlikely(Rc(ctx->opcode) != 0)) { |
26d67362 | 1604 | gen_set_Rc0(ctx, cpu_gpr[rs]); |
c80f84e3 | 1605 | #if defined(TARGET_PPC64) |
9e196938 | 1606 | } else if (rs != 0) { /* 0 is nop */ |
26d67362 AJ |
1607 | int prio = 0; |
1608 | ||
c80f84e3 JM |
1609 | switch (rs) { |
1610 | case 1: | |
1611 | /* Set process priority to low */ | |
26d67362 | 1612 | prio = 2; |
c80f84e3 JM |
1613 | break; |
1614 | case 6: | |
1615 | /* Set process priority to medium-low */ | |
26d67362 | 1616 | prio = 3; |
c80f84e3 JM |
1617 | break; |
1618 | case 2: | |
1619 | /* Set process priority to normal */ | |
26d67362 | 1620 | prio = 4; |
c80f84e3 | 1621 | break; |
be147d08 JM |
1622 | #if !defined(CONFIG_USER_ONLY) |
1623 | case 31: | |
c47493f2 | 1624 | if (!ctx->pr) { |
be147d08 | 1625 | /* Set process priority to very low */ |
26d67362 | 1626 | prio = 1; |
be147d08 JM |
1627 | } |
1628 | break; | |
1629 | case 5: | |
c47493f2 | 1630 | if (!ctx->pr) { |
be147d08 | 1631 | /* Set process priority to medium-hight */ |
26d67362 | 1632 | prio = 5; |
be147d08 JM |
1633 | } |
1634 | break; | |
1635 | case 3: | |
c47493f2 | 1636 | if (!ctx->pr) { |
be147d08 | 1637 | /* Set process priority to high */ |
26d67362 | 1638 | prio = 6; |
be147d08 JM |
1639 | } |
1640 | break; | |
be147d08 | 1641 | case 7: |
b68e60e6 | 1642 | if (ctx->hv && !ctx->pr) { |
be147d08 | 1643 | /* Set process priority to very high */ |
26d67362 | 1644 | prio = 7; |
be147d08 JM |
1645 | } |
1646 | break; | |
be147d08 | 1647 | #endif |
c80f84e3 | 1648 | default: |
c80f84e3 JM |
1649 | break; |
1650 | } | |
26d67362 | 1651 | if (prio) { |
a7812ae4 | 1652 | TCGv t0 = tcg_temp_new(); |
54cdcae6 | 1653 | gen_load_spr(t0, SPR_PPR); |
ea363694 AJ |
1654 | tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); |
1655 | tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); | |
54cdcae6 | 1656 | gen_store_spr(SPR_PPR, t0); |
ea363694 | 1657 | tcg_temp_free(t0); |
9e196938 | 1658 | } |
7f2b1744 | 1659 | #if !defined(CONFIG_USER_ONLY) |
9e196938 AL |
1660 | /* Pause out of TCG otherwise spin loops with smt_low eat too much |
1661 | * CPU and the kernel hangs. This applies to all encodings other | |
1662 | * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30), | |
1663 | * and all currently undefined. | |
1664 | */ | |
1665 | gen_pause(ctx); | |
7f2b1744 | 1666 | #endif |
c80f84e3 | 1667 | #endif |
9a64fbe4 | 1668 | } |
9a64fbe4 | 1669 | } |
79aceca5 | 1670 | /* orc & orc. */ |
26d67362 | 1671 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); |
99e300ef | 1672 | |
54623277 | 1673 | /* xor & xor. */ |
99e300ef | 1674 | static void gen_xor(DisasContext *ctx) |
9a64fbe4 | 1675 | { |
9a64fbe4 | 1676 | /* Optimisation for "set to zero" case */ |
26d67362 | 1677 | if (rS(ctx->opcode) != rB(ctx->opcode)) |
312179c4 | 1678 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
1679 | else |
1680 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
76a66253 | 1681 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 1682 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
9a64fbe4 | 1683 | } |
99e300ef | 1684 | |
54623277 | 1685 | /* ori */ |
99e300ef | 1686 | static void gen_ori(DisasContext *ctx) |
79aceca5 | 1687 | { |
76a66253 | 1688 | target_ulong uimm = UIMM(ctx->opcode); |
79aceca5 | 1689 | |
9a64fbe4 | 1690 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
9a64fbe4 | 1691 | return; |
76a66253 | 1692 | } |
26d67362 | 1693 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
79aceca5 | 1694 | } |
99e300ef | 1695 | |
54623277 | 1696 | /* oris */ |
99e300ef | 1697 | static void gen_oris(DisasContext *ctx) |
79aceca5 | 1698 | { |
76a66253 | 1699 | target_ulong uimm = UIMM(ctx->opcode); |
79aceca5 | 1700 | |
9a64fbe4 FB |
1701 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1702 | /* NOP */ | |
1703 | return; | |
76a66253 | 1704 | } |
26d67362 | 1705 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); |
79aceca5 | 1706 | } |
99e300ef | 1707 | |
54623277 | 1708 | /* xori */ |
99e300ef | 1709 | static void gen_xori(DisasContext *ctx) |
79aceca5 | 1710 | { |
76a66253 | 1711 | target_ulong uimm = UIMM(ctx->opcode); |
9a64fbe4 FB |
1712 | |
1713 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
1714 | /* NOP */ | |
1715 | return; | |
1716 | } | |
26d67362 | 1717 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
79aceca5 | 1718 | } |
99e300ef | 1719 | |
54623277 | 1720 | /* xoris */ |
99e300ef | 1721 | static void gen_xoris(DisasContext *ctx) |
79aceca5 | 1722 | { |
76a66253 | 1723 | target_ulong uimm = UIMM(ctx->opcode); |
9a64fbe4 FB |
1724 | |
1725 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
1726 | /* NOP */ | |
1727 | return; | |
1728 | } | |
26d67362 | 1729 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); |
79aceca5 | 1730 | } |
99e300ef | 1731 | |
54623277 | 1732 | /* popcntb : PowerPC 2.03 specification */ |
99e300ef | 1733 | static void gen_popcntb(DisasContext *ctx) |
d9bce9d9 | 1734 | { |
eaabeef2 DG |
1735 | gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1736 | } | |
1737 | ||
1738 | static void gen_popcntw(DisasContext *ctx) | |
1739 | { | |
79770002 | 1740 | #if defined(TARGET_PPC64) |
eaabeef2 | 1741 | gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
79770002 RH |
1742 | #else |
1743 | tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1744 | #endif | |
eaabeef2 DG |
1745 | } |
1746 | ||
d9bce9d9 | 1747 | #if defined(TARGET_PPC64) |
eaabeef2 DG |
1748 | /* popcntd: PowerPC 2.06 specification */ |
1749 | static void gen_popcntd(DisasContext *ctx) | |
1750 | { | |
79770002 | 1751 | tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
d9bce9d9 | 1752 | } |
eaabeef2 | 1753 | #endif |
d9bce9d9 | 1754 | |
725bcec2 AJ |
1755 | /* prtyw: PowerPC 2.05 specification */ |
1756 | static void gen_prtyw(DisasContext *ctx) | |
1757 | { | |
1758 | TCGv ra = cpu_gpr[rA(ctx->opcode)]; | |
1759 | TCGv rs = cpu_gpr[rS(ctx->opcode)]; | |
1760 | TCGv t0 = tcg_temp_new(); | |
1761 | tcg_gen_shri_tl(t0, rs, 16); | |
1762 | tcg_gen_xor_tl(ra, rs, t0); | |
1763 | tcg_gen_shri_tl(t0, ra, 8); | |
1764 | tcg_gen_xor_tl(ra, ra, t0); | |
1765 | tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); | |
1766 | tcg_temp_free(t0); | |
1767 | } | |
1768 | ||
1769 | #if defined(TARGET_PPC64) | |
1770 | /* prtyd: PowerPC 2.05 specification */ | |
1771 | static void gen_prtyd(DisasContext *ctx) | |
1772 | { | |
1773 | TCGv ra = cpu_gpr[rA(ctx->opcode)]; | |
1774 | TCGv rs = cpu_gpr[rS(ctx->opcode)]; | |
1775 | TCGv t0 = tcg_temp_new(); | |
1776 | tcg_gen_shri_tl(t0, rs, 32); | |
1777 | tcg_gen_xor_tl(ra, rs, t0); | |
1778 | tcg_gen_shri_tl(t0, ra, 16); | |
1779 | tcg_gen_xor_tl(ra, ra, t0); | |
1780 | tcg_gen_shri_tl(t0, ra, 8); | |
1781 | tcg_gen_xor_tl(ra, ra, t0); | |
1782 | tcg_gen_andi_tl(ra, ra, 1); | |
1783 | tcg_temp_free(t0); | |
1784 | } | |
1785 | #endif | |
1786 | ||
86ba37ed TM |
1787 | #if defined(TARGET_PPC64) |
1788 | /* bpermd */ | |
1789 | static void gen_bpermd(DisasContext *ctx) | |
1790 | { | |
1791 | gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], | |
1792 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1793 | } | |
1794 | #endif | |
1795 | ||
d9bce9d9 JM |
1796 | #if defined(TARGET_PPC64) |
1797 | /* extsw & extsw. */ | |
26d67362 | 1798 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); |
99e300ef | 1799 | |
54623277 | 1800 | /* cntlzd */ |
99e300ef | 1801 | static void gen_cntlzd(DisasContext *ctx) |
26d67362 | 1802 | { |
9b8514e5 | 1803 | tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); |
26d67362 AJ |
1804 | if (unlikely(Rc(ctx->opcode) != 0)) |
1805 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1806 | } | |
e91d95b2 SD |
1807 | |
1808 | /* cnttzd */ | |
1809 | static void gen_cnttzd(DisasContext *ctx) | |
1810 | { | |
9b8514e5 | 1811 | tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); |
e91d95b2 SD |
1812 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1813 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1814 | } | |
1815 | } | |
fec5c62a RB |
1816 | |
1817 | /* darn */ | |
1818 | static void gen_darn(DisasContext *ctx) | |
1819 | { | |
1820 | int l = L(ctx->opcode); | |
1821 | ||
1822 | if (l == 0) { | |
1823 | gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); | |
1824 | } else if (l <= 2) { | |
1825 | /* Return 64-bit random for both CRN and RRN */ | |
1826 | gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); | |
1827 | } else { | |
1828 | tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); | |
1829 | } | |
1830 | } | |
d9bce9d9 JM |
1831 | #endif |
1832 | ||
79aceca5 | 1833 | /*** Integer rotate ***/ |
99e300ef | 1834 | |
54623277 | 1835 | /* rlwimi & rlwimi. */ |
99e300ef | 1836 | static void gen_rlwimi(DisasContext *ctx) |
79aceca5 | 1837 | { |
63ae0915 RH |
1838 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
1839 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
1840 | uint32_t sh = SH(ctx->opcode); | |
1841 | uint32_t mb = MB(ctx->opcode); | |
1842 | uint32_t me = ME(ctx->opcode); | |
1843 | ||
1844 | if (sh == (31-me) && mb <= me) { | |
1845 | tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); | |
d03ef511 | 1846 | } else { |
d03ef511 | 1847 | target_ulong mask; |
a7812ae4 | 1848 | TCGv t1; |
63ae0915 | 1849 | |
76a66253 | 1850 | #if defined(TARGET_PPC64) |
d03ef511 AJ |
1851 | mb += 32; |
1852 | me += 32; | |
76a66253 | 1853 | #endif |
d03ef511 | 1854 | mask = MASK(mb, me); |
63ae0915 | 1855 | |
a7812ae4 | 1856 | t1 = tcg_temp_new(); |
2e11b15d RH |
1857 | if (mask <= 0xffffffffu) { |
1858 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
1859 | tcg_gen_trunc_tl_i32(t0, t_rs); | |
1860 | tcg_gen_rotli_i32(t0, t0, sh); | |
1861 | tcg_gen_extu_i32_tl(t1, t0); | |
1862 | tcg_temp_free_i32(t0); | |
1863 | } else { | |
1864 | #if defined(TARGET_PPC64) | |
1865 | tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); | |
1866 | tcg_gen_rotli_i64(t1, t1, sh); | |
1867 | #else | |
1868 | g_assert_not_reached(); | |
1869 | #endif | |
1870 | } | |
63ae0915 RH |
1871 | |
1872 | tcg_gen_andi_tl(t1, t1, mask); | |
1873 | tcg_gen_andi_tl(t_ra, t_ra, ~mask); | |
1874 | tcg_gen_or_tl(t_ra, t_ra, t1); | |
d03ef511 AJ |
1875 | tcg_temp_free(t1); |
1876 | } | |
63ae0915 RH |
1877 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1878 | gen_set_Rc0(ctx, t_ra); | |
1879 | } | |
79aceca5 | 1880 | } |
99e300ef | 1881 | |
54623277 | 1882 | /* rlwinm & rlwinm. */ |
99e300ef | 1883 | static void gen_rlwinm(DisasContext *ctx) |
79aceca5 | 1884 | { |
63ae0915 RH |
1885 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
1886 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
7b4d326f RH |
1887 | int sh = SH(ctx->opcode); |
1888 | int mb = MB(ctx->opcode); | |
1889 | int me = ME(ctx->opcode); | |
1890 | int len = me - mb + 1; | |
1891 | int rsh = (32 - sh) & 31; | |
1892 | ||
1893 | if (sh != 0 && len > 0 && me == (31 - sh)) { | |
1894 | tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); | |
1895 | } else if (me == 31 && rsh + len <= 32) { | |
1896 | tcg_gen_extract_tl(t_ra, t_rs, rsh, len); | |
d03ef511 | 1897 | } else { |
2e11b15d | 1898 | target_ulong mask; |
76a66253 | 1899 | #if defined(TARGET_PPC64) |
d03ef511 AJ |
1900 | mb += 32; |
1901 | me += 32; | |
76a66253 | 1902 | #endif |
2e11b15d | 1903 | mask = MASK(mb, me); |
7b4d326f RH |
1904 | if (sh == 0) { |
1905 | tcg_gen_andi_tl(t_ra, t_rs, mask); | |
1906 | } else if (mask <= 0xffffffffu) { | |
63ae0915 | 1907 | TCGv_i32 t0 = tcg_temp_new_i32(); |
63ae0915 RH |
1908 | tcg_gen_trunc_tl_i32(t0, t_rs); |
1909 | tcg_gen_rotli_i32(t0, t0, sh); | |
2e11b15d | 1910 | tcg_gen_andi_i32(t0, t0, mask); |
63ae0915 RH |
1911 | tcg_gen_extu_i32_tl(t_ra, t0); |
1912 | tcg_temp_free_i32(t0); | |
2e11b15d RH |
1913 | } else { |
1914 | #if defined(TARGET_PPC64) | |
1915 | tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); | |
1916 | tcg_gen_rotli_i64(t_ra, t_ra, sh); | |
1917 | tcg_gen_andi_i64(t_ra, t_ra, mask); | |
1918 | #else | |
1919 | g_assert_not_reached(); | |
1920 | #endif | |
63ae0915 RH |
1921 | } |
1922 | } | |
1923 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1924 | gen_set_Rc0(ctx, t_ra); | |
d03ef511 | 1925 | } |
79aceca5 | 1926 | } |
99e300ef | 1927 | |
54623277 | 1928 | /* rlwnm & rlwnm. */ |
99e300ef | 1929 | static void gen_rlwnm(DisasContext *ctx) |
79aceca5 | 1930 | { |
63ae0915 RH |
1931 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
1932 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
1933 | TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; | |
1934 | uint32_t mb = MB(ctx->opcode); | |
1935 | uint32_t me = ME(ctx->opcode); | |
2e11b15d | 1936 | target_ulong mask; |
57fca134 | 1937 | |
54843a58 | 1938 | #if defined(TARGET_PPC64) |
63ae0915 RH |
1939 | mb += 32; |
1940 | me += 32; | |
54843a58 | 1941 | #endif |
2e11b15d RH |
1942 | mask = MASK(mb, me); |
1943 | ||
1944 | if (mask <= 0xffffffffu) { | |
1945 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
1946 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
1947 | tcg_gen_trunc_tl_i32(t0, t_rb); | |
1948 | tcg_gen_trunc_tl_i32(t1, t_rs); | |
1949 | tcg_gen_andi_i32(t0, t0, 0x1f); | |
1950 | tcg_gen_rotl_i32(t1, t1, t0); | |
1951 | tcg_gen_extu_i32_tl(t_ra, t1); | |
1952 | tcg_temp_free_i32(t0); | |
1953 | tcg_temp_free_i32(t1); | |
1954 | } else { | |
1955 | #if defined(TARGET_PPC64) | |
1956 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
1957 | tcg_gen_andi_i64(t0, t_rb, 0x1f); | |
1958 | tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); | |
1959 | tcg_gen_rotl_i64(t_ra, t_ra, t0); | |
1960 | tcg_temp_free_i64(t0); | |
1961 | #else | |
1962 | g_assert_not_reached(); | |
1963 | #endif | |
1964 | } | |
57fca134 | 1965 | |
2e11b15d | 1966 | tcg_gen_andi_tl(t_ra, t_ra, mask); |
63ae0915 RH |
1967 | |
1968 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1969 | gen_set_Rc0(ctx, t_ra); | |
79aceca5 | 1970 | } |
79aceca5 FB |
1971 | } |
1972 | ||
d9bce9d9 JM |
1973 | #if defined(TARGET_PPC64) |
1974 | #define GEN_PPC64_R2(name, opc1, opc2) \ | |
e8eaa2c0 | 1975 | static void glue(gen_, name##0)(DisasContext *ctx) \ |
d9bce9d9 JM |
1976 | { \ |
1977 | gen_##name(ctx, 0); \ | |
1978 | } \ | |
e8eaa2c0 BS |
1979 | \ |
1980 | static void glue(gen_, name##1)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1981 | { \ |
1982 | gen_##name(ctx, 1); \ | |
1983 | } | |
1984 | #define GEN_PPC64_R4(name, opc1, opc2) \ | |
e8eaa2c0 | 1985 | static void glue(gen_, name##0)(DisasContext *ctx) \ |
d9bce9d9 JM |
1986 | { \ |
1987 | gen_##name(ctx, 0, 0); \ | |
1988 | } \ | |
e8eaa2c0 BS |
1989 | \ |
1990 | static void glue(gen_, name##1)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1991 | { \ |
1992 | gen_##name(ctx, 0, 1); \ | |
1993 | } \ | |
e8eaa2c0 BS |
1994 | \ |
1995 | static void glue(gen_, name##2)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1996 | { \ |
1997 | gen_##name(ctx, 1, 0); \ | |
1998 | } \ | |
e8eaa2c0 BS |
1999 | \ |
2000 | static void glue(gen_, name##3)(DisasContext *ctx) \ | |
d9bce9d9 JM |
2001 | { \ |
2002 | gen_##name(ctx, 1, 1); \ | |
2003 | } | |
51789c41 | 2004 | |
a7b2c8b9 | 2005 | static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) |
51789c41 | 2006 | { |
a7b2c8b9 RH |
2007 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
2008 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
7b4d326f RH |
2009 | int len = me - mb + 1; |
2010 | int rsh = (64 - sh) & 63; | |
a7b2c8b9 | 2011 | |
7b4d326f RH |
2012 | if (sh != 0 && len > 0 && me == (63 - sh)) { |
2013 | tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); | |
2014 | } else if (me == 63 && rsh + len <= 64) { | |
2015 | tcg_gen_extract_tl(t_ra, t_rs, rsh, len); | |
d03ef511 | 2016 | } else { |
a7b2c8b9 RH |
2017 | tcg_gen_rotli_tl(t_ra, t_rs, sh); |
2018 | tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); | |
2019 | } | |
2020 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2021 | gen_set_Rc0(ctx, t_ra); | |
51789c41 | 2022 | } |
51789c41 | 2023 | } |
a7b2c8b9 | 2024 | |
d9bce9d9 | 2025 | /* rldicl - rldicl. */ |
636aa200 | 2026 | static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 2027 | { |
51789c41 | 2028 | uint32_t sh, mb; |
d9bce9d9 | 2029 | |
9d53c753 JM |
2030 | sh = SH(ctx->opcode) | (shn << 5); |
2031 | mb = MB(ctx->opcode) | (mbn << 5); | |
51789c41 | 2032 | gen_rldinm(ctx, mb, 63, sh); |
d9bce9d9 | 2033 | } |
51789c41 | 2034 | GEN_PPC64_R4(rldicl, 0x1E, 0x00); |
a7b2c8b9 | 2035 | |
d9bce9d9 | 2036 | /* rldicr - rldicr. */ |
636aa200 | 2037 | static inline void gen_rldicr(DisasContext *ctx, int men, int shn) |
d9bce9d9 | 2038 | { |
51789c41 | 2039 | uint32_t sh, me; |
d9bce9d9 | 2040 | |
9d53c753 JM |
2041 | sh = SH(ctx->opcode) | (shn << 5); |
2042 | me = MB(ctx->opcode) | (men << 5); | |
51789c41 | 2043 | gen_rldinm(ctx, 0, me, sh); |
d9bce9d9 | 2044 | } |
51789c41 | 2045 | GEN_PPC64_R4(rldicr, 0x1E, 0x02); |
a7b2c8b9 | 2046 | |
d9bce9d9 | 2047 | /* rldic - rldic. */ |
636aa200 | 2048 | static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 2049 | { |
51789c41 | 2050 | uint32_t sh, mb; |
d9bce9d9 | 2051 | |
9d53c753 JM |
2052 | sh = SH(ctx->opcode) | (shn << 5); |
2053 | mb = MB(ctx->opcode) | (mbn << 5); | |
51789c41 JM |
2054 | gen_rldinm(ctx, mb, 63 - sh, sh); |
2055 | } | |
2056 | GEN_PPC64_R4(rldic, 0x1E, 0x04); | |
2057 | ||
a7b2c8b9 | 2058 | static void gen_rldnm(DisasContext *ctx, int mb, int me) |
51789c41 | 2059 | { |
a7b2c8b9 RH |
2060 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
2061 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
2062 | TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; | |
54843a58 | 2063 | TCGv t0; |
d03ef511 | 2064 | |
a7812ae4 | 2065 | t0 = tcg_temp_new(); |
a7b2c8b9 RH |
2066 | tcg_gen_andi_tl(t0, t_rb, 0x3f); |
2067 | tcg_gen_rotl_tl(t_ra, t_rs, t0); | |
54843a58 | 2068 | tcg_temp_free(t0); |
a7b2c8b9 RH |
2069 | |
2070 | tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); | |
2071 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2072 | gen_set_Rc0(ctx, t_ra); | |
2073 | } | |
d9bce9d9 | 2074 | } |
51789c41 | 2075 | |
d9bce9d9 | 2076 | /* rldcl - rldcl. */ |
636aa200 | 2077 | static inline void gen_rldcl(DisasContext *ctx, int mbn) |
d9bce9d9 | 2078 | { |
51789c41 | 2079 | uint32_t mb; |
d9bce9d9 | 2080 | |
9d53c753 | 2081 | mb = MB(ctx->opcode) | (mbn << 5); |
51789c41 | 2082 | gen_rldnm(ctx, mb, 63); |
d9bce9d9 | 2083 | } |
36081602 | 2084 | GEN_PPC64_R2(rldcl, 0x1E, 0x08); |
a7b2c8b9 | 2085 | |
d9bce9d9 | 2086 | /* rldcr - rldcr. */ |
636aa200 | 2087 | static inline void gen_rldcr(DisasContext *ctx, int men) |
d9bce9d9 | 2088 | { |
51789c41 | 2089 | uint32_t me; |
d9bce9d9 | 2090 | |
9d53c753 | 2091 | me = MB(ctx->opcode) | (men << 5); |
51789c41 | 2092 | gen_rldnm(ctx, 0, me); |
d9bce9d9 | 2093 | } |
36081602 | 2094 | GEN_PPC64_R2(rldcr, 0x1E, 0x09); |
a7b2c8b9 | 2095 | |
d9bce9d9 | 2096 | /* rldimi - rldimi. */ |
a7b2c8b9 | 2097 | static void gen_rldimi(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 2098 | { |
a7b2c8b9 RH |
2099 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
2100 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
2101 | uint32_t sh = SH(ctx->opcode) | (shn << 5); | |
2102 | uint32_t mb = MB(ctx->opcode) | (mbn << 5); | |
2103 | uint32_t me = 63 - sh; | |
d9bce9d9 | 2104 | |
a7b2c8b9 RH |
2105 | if (mb <= me) { |
2106 | tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); | |
d03ef511 | 2107 | } else { |
a7b2c8b9 RH |
2108 | target_ulong mask = MASK(mb, me); |
2109 | TCGv t1 = tcg_temp_new(); | |
d03ef511 | 2110 | |
a7b2c8b9 RH |
2111 | tcg_gen_rotli_tl(t1, t_rs, sh); |
2112 | tcg_gen_andi_tl(t1, t1, mask); | |
2113 | tcg_gen_andi_tl(t_ra, t_ra, ~mask); | |
2114 | tcg_gen_or_tl(t_ra, t_ra, t1); | |
d03ef511 | 2115 | tcg_temp_free(t1); |
51789c41 | 2116 | } |
a7b2c8b9 RH |
2117 | if (unlikely(Rc(ctx->opcode) != 0)) { |
2118 | gen_set_Rc0(ctx, t_ra); | |
2119 | } | |
d9bce9d9 | 2120 | } |
36081602 | 2121 | GEN_PPC64_R4(rldimi, 0x1E, 0x06); |
d9bce9d9 JM |
2122 | #endif |
2123 | ||
79aceca5 | 2124 | /*** Integer shift ***/ |
99e300ef | 2125 | |
54623277 | 2126 | /* slw & slw. */ |
99e300ef | 2127 | static void gen_slw(DisasContext *ctx) |
26d67362 | 2128 | { |
7fd6bf7d | 2129 | TCGv t0, t1; |
26d67362 | 2130 | |
7fd6bf7d AJ |
2131 | t0 = tcg_temp_new(); |
2132 | /* AND rS with a mask that is 0 when rB >= 0x20 */ | |
2133 | #if defined(TARGET_PPC64) | |
2134 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); | |
2135 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
2136 | #else | |
2137 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); | |
2138 | tcg_gen_sari_tl(t0, t0, 0x1f); | |
2139 | #endif | |
2140 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
2141 | t1 = tcg_temp_new(); | |
2142 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); | |
2143 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
2144 | tcg_temp_free(t1); | |
fea0c503 | 2145 | tcg_temp_free(t0); |
7fd6bf7d | 2146 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
26d67362 AJ |
2147 | if (unlikely(Rc(ctx->opcode) != 0)) |
2148 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2149 | } | |
99e300ef | 2150 | |
54623277 | 2151 | /* sraw & sraw. */ |
99e300ef | 2152 | static void gen_sraw(DisasContext *ctx) |
26d67362 | 2153 | { |
d15f74fb | 2154 | gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, |
a7812ae4 | 2155 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
2156 | if (unlikely(Rc(ctx->opcode) != 0)) |
2157 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2158 | } | |
99e300ef | 2159 | |
54623277 | 2160 | /* srawi & srawi. */ |
99e300ef | 2161 | static void gen_srawi(DisasContext *ctx) |
79aceca5 | 2162 | { |
26d67362 | 2163 | int sh = SH(ctx->opcode); |
ba4af3e4 RH |
2164 | TCGv dst = cpu_gpr[rA(ctx->opcode)]; |
2165 | TCGv src = cpu_gpr[rS(ctx->opcode)]; | |
2166 | if (sh == 0) { | |
34a0fad1 | 2167 | tcg_gen_ext32s_tl(dst, src); |
da91a00f | 2168 | tcg_gen_movi_tl(cpu_ca, 0); |
af1c259f SD |
2169 | if (is_isa300(ctx)) { |
2170 | tcg_gen_movi_tl(cpu_ca32, 0); | |
2171 | } | |
26d67362 | 2172 | } else { |
ba4af3e4 RH |
2173 | TCGv t0; |
2174 | tcg_gen_ext32s_tl(dst, src); | |
2175 | tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); | |
2176 | t0 = tcg_temp_new(); | |
2177 | tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); | |
2178 | tcg_gen_and_tl(cpu_ca, cpu_ca, t0); | |
2179 | tcg_temp_free(t0); | |
2180 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); | |
af1c259f SD |
2181 | if (is_isa300(ctx)) { |
2182 | tcg_gen_mov_tl(cpu_ca32, cpu_ca); | |
2183 | } | |
ba4af3e4 RH |
2184 | tcg_gen_sari_tl(dst, dst, sh); |
2185 | } | |
2186 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2187 | gen_set_Rc0(ctx, dst); | |
d9bce9d9 | 2188 | } |
79aceca5 | 2189 | } |
99e300ef | 2190 | |
54623277 | 2191 | /* srw & srw. */ |
99e300ef | 2192 | static void gen_srw(DisasContext *ctx) |
26d67362 | 2193 | { |
fea0c503 | 2194 | TCGv t0, t1; |
d9bce9d9 | 2195 | |
7fd6bf7d AJ |
2196 | t0 = tcg_temp_new(); |
2197 | /* AND rS with a mask that is 0 when rB >= 0x20 */ | |
2198 | #if defined(TARGET_PPC64) | |
2199 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); | |
2200 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
2201 | #else | |
2202 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); | |
2203 | tcg_gen_sari_tl(t0, t0, 0x1f); | |
2204 | #endif | |
2205 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
2206 | tcg_gen_ext32u_tl(t0, t0); | |
a7812ae4 | 2207 | t1 = tcg_temp_new(); |
7fd6bf7d AJ |
2208 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); |
2209 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
fea0c503 | 2210 | tcg_temp_free(t1); |
fea0c503 | 2211 | tcg_temp_free(t0); |
26d67362 AJ |
2212 | if (unlikely(Rc(ctx->opcode) != 0)) |
2213 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2214 | } | |
54623277 | 2215 | |
d9bce9d9 JM |
2216 | #if defined(TARGET_PPC64) |
2217 | /* sld & sld. */ | |
99e300ef | 2218 | static void gen_sld(DisasContext *ctx) |
26d67362 | 2219 | { |
7fd6bf7d | 2220 | TCGv t0, t1; |
26d67362 | 2221 | |
7fd6bf7d AJ |
2222 | t0 = tcg_temp_new(); |
2223 | /* AND rS with a mask that is 0 when rB >= 0x40 */ | |
2224 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); | |
2225 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
2226 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
2227 | t1 = tcg_temp_new(); | |
2228 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); | |
2229 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
2230 | tcg_temp_free(t1); | |
fea0c503 | 2231 | tcg_temp_free(t0); |
26d67362 AJ |
2232 | if (unlikely(Rc(ctx->opcode) != 0)) |
2233 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2234 | } | |
99e300ef | 2235 | |
54623277 | 2236 | /* srad & srad. */ |
99e300ef | 2237 | static void gen_srad(DisasContext *ctx) |
26d67362 | 2238 | { |
d15f74fb | 2239 | gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, |
a7812ae4 | 2240 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
2241 | if (unlikely(Rc(ctx->opcode) != 0)) |
2242 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2243 | } | |
d9bce9d9 | 2244 | /* sradi & sradi. */ |
636aa200 | 2245 | static inline void gen_sradi(DisasContext *ctx, int n) |
d9bce9d9 | 2246 | { |
26d67362 | 2247 | int sh = SH(ctx->opcode) + (n << 5); |
ba4af3e4 RH |
2248 | TCGv dst = cpu_gpr[rA(ctx->opcode)]; |
2249 | TCGv src = cpu_gpr[rS(ctx->opcode)]; | |
2250 | if (sh == 0) { | |
2251 | tcg_gen_mov_tl(dst, src); | |
da91a00f | 2252 | tcg_gen_movi_tl(cpu_ca, 0); |
af1c259f SD |
2253 | if (is_isa300(ctx)) { |
2254 | tcg_gen_movi_tl(cpu_ca32, 0); | |
2255 | } | |
26d67362 | 2256 | } else { |
ba4af3e4 RH |
2257 | TCGv t0; |
2258 | tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); | |
2259 | t0 = tcg_temp_new(); | |
2260 | tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); | |
2261 | tcg_gen_and_tl(cpu_ca, cpu_ca, t0); | |
2262 | tcg_temp_free(t0); | |
2263 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); | |
af1c259f SD |
2264 | if (is_isa300(ctx)) { |
2265 | tcg_gen_mov_tl(cpu_ca32, cpu_ca); | |
2266 | } | |
ba4af3e4 RH |
2267 | tcg_gen_sari_tl(dst, src, sh); |
2268 | } | |
2269 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2270 | gen_set_Rc0(ctx, dst); | |
d9bce9d9 | 2271 | } |
d9bce9d9 | 2272 | } |
e8eaa2c0 BS |
2273 | |
2274 | static void gen_sradi0(DisasContext *ctx) | |
d9bce9d9 JM |
2275 | { |
2276 | gen_sradi(ctx, 0); | |
2277 | } | |
e8eaa2c0 BS |
2278 | |
2279 | static void gen_sradi1(DisasContext *ctx) | |
d9bce9d9 JM |
2280 | { |
2281 | gen_sradi(ctx, 1); | |
2282 | } | |
99e300ef | 2283 | |
787bbe37 ND |
2284 | /* extswsli & extswsli. */ |
2285 | static inline void gen_extswsli(DisasContext *ctx, int n) | |
2286 | { | |
2287 | int sh = SH(ctx->opcode) + (n << 5); | |
2288 | TCGv dst = cpu_gpr[rA(ctx->opcode)]; | |
2289 | TCGv src = cpu_gpr[rS(ctx->opcode)]; | |
2290 | ||
2291 | tcg_gen_ext32s_tl(dst, src); | |
2292 | tcg_gen_shli_tl(dst, dst, sh); | |
2293 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2294 | gen_set_Rc0(ctx, dst); | |
2295 | } | |
2296 | } | |
2297 | ||
2298 | static void gen_extswsli0(DisasContext *ctx) | |
2299 | { | |
2300 | gen_extswsli(ctx, 0); | |
2301 | } | |
2302 | ||
2303 | static void gen_extswsli1(DisasContext *ctx) | |
2304 | { | |
2305 | gen_extswsli(ctx, 1); | |
2306 | } | |
2307 | ||
54623277 | 2308 | /* srd & srd. */ |
99e300ef | 2309 | static void gen_srd(DisasContext *ctx) |
26d67362 | 2310 | { |
7fd6bf7d | 2311 | TCGv t0, t1; |
26d67362 | 2312 | |
7fd6bf7d AJ |
2313 | t0 = tcg_temp_new(); |
2314 | /* AND rS with a mask that is 0 when rB >= 0x40 */ | |
2315 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); | |
2316 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
2317 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
2318 | t1 = tcg_temp_new(); | |
2319 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); | |
2320 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
2321 | tcg_temp_free(t1); | |
fea0c503 | 2322 | tcg_temp_free(t0); |
26d67362 AJ |
2323 | if (unlikely(Rc(ctx->opcode) != 0)) |
2324 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2325 | } | |
d9bce9d9 | 2326 | #endif |
79aceca5 | 2327 | |
76a66253 JM |
2328 | /*** Addressing modes ***/ |
2329 | /* Register indirect with immediate index : EA = (rA|0) + SIMM */ | |
636aa200 BS |
2330 | static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, |
2331 | target_long maskl) | |
76a66253 JM |
2332 | { |
2333 | target_long simm = SIMM(ctx->opcode); | |
2334 | ||
be147d08 | 2335 | simm &= ~maskl; |
76db3ba4 | 2336 | if (rA(ctx->opcode) == 0) { |
c791fe84 RH |
2337 | if (NARROW_MODE(ctx)) { |
2338 | simm = (uint32_t)simm; | |
2339 | } | |
e2be8d8d | 2340 | tcg_gen_movi_tl(EA, simm); |
76db3ba4 | 2341 | } else if (likely(simm != 0)) { |
e2be8d8d | 2342 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); |
c791fe84 | 2343 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
2344 | tcg_gen_ext32u_tl(EA, EA); |
2345 | } | |
76db3ba4 | 2346 | } else { |
c791fe84 | 2347 | if (NARROW_MODE(ctx)) { |
76db3ba4 | 2348 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
c791fe84 RH |
2349 | } else { |
2350 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
2351 | } | |
76db3ba4 | 2352 | } |
76a66253 JM |
2353 | } |
2354 | ||
636aa200 | 2355 | static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) |
76a66253 | 2356 | { |
76db3ba4 | 2357 | if (rA(ctx->opcode) == 0) { |
c791fe84 | 2358 | if (NARROW_MODE(ctx)) { |
76db3ba4 | 2359 | tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); |
c791fe84 RH |
2360 | } else { |
2361 | tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); | |
2362 | } | |
76db3ba4 | 2363 | } else { |
e2be8d8d | 2364 | tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
c791fe84 | 2365 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
2366 | tcg_gen_ext32u_tl(EA, EA); |
2367 | } | |
76db3ba4 | 2368 | } |
76a66253 JM |
2369 | } |
2370 | ||
636aa200 | 2371 | static inline void gen_addr_register(DisasContext *ctx, TCGv EA) |
76a66253 | 2372 | { |
76db3ba4 | 2373 | if (rA(ctx->opcode) == 0) { |
e2be8d8d | 2374 | tcg_gen_movi_tl(EA, 0); |
c791fe84 RH |
2375 | } else if (NARROW_MODE(ctx)) { |
2376 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
76db3ba4 | 2377 | } else { |
c791fe84 | 2378 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
76db3ba4 AJ |
2379 | } |
2380 | } | |
2381 | ||
636aa200 BS |
2382 | static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
2383 | target_long val) | |
76db3ba4 AJ |
2384 | { |
2385 | tcg_gen_addi_tl(ret, arg1, val); | |
c791fe84 | 2386 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
2387 | tcg_gen_ext32u_tl(ret, ret); |
2388 | } | |
76a66253 JM |
2389 | } |
2390 | ||
65f2475f BH |
2391 | static inline void gen_align_no_le(DisasContext *ctx) |
2392 | { | |
2393 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, | |
2394 | (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); | |
2395 | } | |
2396 | ||
7863667f | 2397 | /*** Integer load ***/ |
09bfe50d | 2398 | #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) |
ff5f3981 | 2399 | #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) |
b61f2753 | 2400 | |
09bfe50d ND |
2401 | #define GEN_QEMU_LOAD_TL(ldop, op) \ |
2402 | static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ | |
2403 | TCGv val, \ | |
2404 | TCGv addr) \ | |
2405 | { \ | |
2406 | tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ | |
b61f2753 AJ |
2407 | } |
2408 | ||
09bfe50d ND |
2409 | GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) |
2410 | GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) | |
2411 | GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) | |
2412 | GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) | |
2413 | GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) | |
f976b09e | 2414 | |
ff5f3981 ND |
2415 | GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) |
2416 | GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) | |
2417 | ||
09bfe50d ND |
2418 | #define GEN_QEMU_LOAD_64(ldop, op) \ |
2419 | static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ | |
2420 | TCGv_i64 val, \ | |
2421 | TCGv addr) \ | |
2422 | { \ | |
2423 | tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ | |
b61f2753 AJ |
2424 | } |
2425 | ||
740ae9a2 ND |
2426 | GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) |
2427 | GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) | |
09bfe50d ND |
2428 | GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) |
2429 | GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) | |
4f364fe7 | 2430 | GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) |
b61f2753 | 2431 | |
ff5f3981 ND |
2432 | #if defined(TARGET_PPC64) |
2433 | GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) | |
2434 | #endif | |
2435 | ||
761a89c6 ND |
2436 | #define GEN_QEMU_STORE_TL(stop, op) \ |
2437 | static void glue(gen_qemu_, stop)(DisasContext *ctx, \ | |
2438 | TCGv val, \ | |
2439 | TCGv addr) \ | |
2440 | { \ | |
2441 | tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ | |
b61f2753 AJ |
2442 | } |
2443 | ||
761a89c6 ND |
2444 | GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) |
2445 | GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) | |
2446 | GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) | |
b61f2753 | 2447 | |
804108aa ND |
2448 | GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) |
2449 | GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) | |
2450 | ||
761a89c6 ND |
2451 | #define GEN_QEMU_STORE_64(stop, op) \ |
2452 | static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ | |
2453 | TCGv_i64 val, \ | |
2454 | TCGv addr) \ | |
2455 | { \ | |
2456 | tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ | |
b61f2753 AJ |
2457 | } |
2458 | ||
ddb9ac50 ND |
2459 | GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) |
2460 | GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) | |
761a89c6 | 2461 | GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) |
2468f23d | 2462 | GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) |
b61f2753 | 2463 | |
804108aa ND |
2464 | #if defined(TARGET_PPC64) |
2465 | GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) | |
2466 | #endif | |
2467 | ||
0c8aacd4 | 2468 | #define GEN_LD(name, ldop, opc, type) \ |
99e300ef | 2469 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 2470 | { \ |
76db3ba4 AJ |
2471 | TCGv EA; \ |
2472 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2473 | EA = tcg_temp_new(); \ | |
2474 | gen_addr_imm_index(ctx, EA, 0); \ | |
2475 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 | 2476 | tcg_temp_free(EA); \ |
79aceca5 FB |
2477 | } |
2478 | ||
0c8aacd4 | 2479 | #define GEN_LDU(name, ldop, opc, type) \ |
99e300ef | 2480 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
79aceca5 | 2481 | { \ |
b61f2753 | 2482 | TCGv EA; \ |
76a66253 JM |
2483 | if (unlikely(rA(ctx->opcode) == 0 || \ |
2484 | rA(ctx->opcode) == rD(ctx->opcode))) { \ | |
e06fcd75 | 2485 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2486 | return; \ |
9a64fbe4 | 2487 | } \ |
76db3ba4 | 2488 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2489 | EA = tcg_temp_new(); \ |
9d53c753 | 2490 | if (type == PPC_64B) \ |
76db3ba4 | 2491 | gen_addr_imm_index(ctx, EA, 0x03); \ |
9d53c753 | 2492 | else \ |
76db3ba4 AJ |
2493 | gen_addr_imm_index(ctx, EA, 0); \ |
2494 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2495 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2496 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2497 | } |
2498 | ||
0c8aacd4 | 2499 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \ |
99e300ef | 2500 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 2501 | { \ |
b61f2753 | 2502 | TCGv EA; \ |
76a66253 JM |
2503 | if (unlikely(rA(ctx->opcode) == 0 || \ |
2504 | rA(ctx->opcode) == rD(ctx->opcode))) { \ | |
e06fcd75 | 2505 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2506 | return; \ |
9a64fbe4 | 2507 | } \ |
76db3ba4 | 2508 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2509 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
2510 | gen_addr_reg_index(ctx, EA); \ |
2511 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2512 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2513 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2514 | } |
2515 | ||
b7815375 | 2516 | #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ |
99e300ef | 2517 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 2518 | { \ |
76db3ba4 | 2519 | TCGv EA; \ |
b7815375 | 2520 | chk; \ |
76db3ba4 AJ |
2521 | gen_set_access_type(ctx, ACCESS_INT); \ |
2522 | EA = tcg_temp_new(); \ | |
2523 | gen_addr_reg_index(ctx, EA); \ | |
2524 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 | 2525 | tcg_temp_free(EA); \ |
79aceca5 | 2526 | } |
b7815375 | 2527 | |
cd6e9320 | 2528 | #define GEN_LDX(name, ldop, opc2, opc3, type) \ |
b7815375 BH |
2529 | GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) |
2530 | ||
2531 | #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ | |
2532 | GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) | |
79aceca5 | 2533 | |
0c8aacd4 AJ |
2534 | #define GEN_LDS(name, ldop, op, type) \ |
2535 | GEN_LD(name, ldop, op | 0x20, type); \ | |
2536 | GEN_LDU(name, ldop, op | 0x21, type); \ | |
2537 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ | |
2538 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) | |
79aceca5 FB |
2539 | |
2540 | /* lbz lbzu lbzux lbzx */ | |
0c8aacd4 | 2541 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); |
79aceca5 | 2542 | /* lha lhau lhaux lhax */ |
0c8aacd4 | 2543 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); |
79aceca5 | 2544 | /* lhz lhzu lhzux lhzx */ |
0c8aacd4 | 2545 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); |
79aceca5 | 2546 | /* lwz lwzu lwzux lwzx */ |
0c8aacd4 | 2547 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); |
d9bce9d9 | 2548 | #if defined(TARGET_PPC64) |
d9bce9d9 | 2549 | /* lwaux */ |
0c8aacd4 | 2550 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); |
d9bce9d9 | 2551 | /* lwax */ |
0c8aacd4 | 2552 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); |
d9bce9d9 | 2553 | /* ldux */ |
4f364fe7 | 2554 | GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B); |
d9bce9d9 | 2555 | /* ldx */ |
4f364fe7 | 2556 | GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B); |
99e300ef | 2557 | |
b7815375 | 2558 | /* CI load/store variants */ |
4f364fe7 | 2559 | GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) |
b7815375 BH |
2560 | GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) |
2561 | GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) | |
2562 | GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) | |
2563 | ||
99e300ef | 2564 | static void gen_ld(DisasContext *ctx) |
d9bce9d9 | 2565 | { |
b61f2753 | 2566 | TCGv EA; |
d9bce9d9 JM |
2567 | if (Rc(ctx->opcode)) { |
2568 | if (unlikely(rA(ctx->opcode) == 0 || | |
2569 | rA(ctx->opcode) == rD(ctx->opcode))) { | |
e06fcd75 | 2570 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
d9bce9d9 JM |
2571 | return; |
2572 | } | |
2573 | } | |
76db3ba4 | 2574 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2575 | EA = tcg_temp_new(); |
76db3ba4 | 2576 | gen_addr_imm_index(ctx, EA, 0x03); |
d9bce9d9 JM |
2577 | if (ctx->opcode & 0x02) { |
2578 | /* lwa (lwau is undefined) */ | |
76db3ba4 | 2579 | gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
d9bce9d9 JM |
2580 | } else { |
2581 | /* ld - ldu */ | |
4f364fe7 | 2582 | gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
d9bce9d9 | 2583 | } |
d9bce9d9 | 2584 | if (Rc(ctx->opcode)) |
b61f2753 AJ |
2585 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
2586 | tcg_temp_free(EA); | |
d9bce9d9 | 2587 | } |
99e300ef | 2588 | |
54623277 | 2589 | /* lq */ |
99e300ef | 2590 | static void gen_lq(DisasContext *ctx) |
be147d08 | 2591 | { |
be147d08 | 2592 | int ra, rd; |
94bf2658 | 2593 | TCGv EA, hi, lo; |
be147d08 | 2594 | |
e0498daa TM |
2595 | /* lq is a legal user mode instruction starting in ISA 2.07 */ |
2596 | bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; | |
2597 | bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; | |
2598 | ||
c47493f2 | 2599 | if (!legal_in_user_mode && ctx->pr) { |
9b2fadda | 2600 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2601 | return; |
2602 | } | |
e0498daa TM |
2603 | |
2604 | if (!le_is_supported && ctx->le_mode) { | |
65f2475f | 2605 | gen_align_no_le(ctx); |
e0498daa TM |
2606 | return; |
2607 | } | |
be147d08 JM |
2608 | ra = rA(ctx->opcode); |
2609 | rd = rD(ctx->opcode); | |
2610 | if (unlikely((rd & 1) || rd == ra)) { | |
e06fcd75 | 2611 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
be147d08 JM |
2612 | return; |
2613 | } | |
e0498daa | 2614 | |
76db3ba4 | 2615 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2616 | EA = tcg_temp_new(); |
76db3ba4 | 2617 | gen_addr_imm_index(ctx, EA, 0x0F); |
e0498daa | 2618 | |
94bf2658 RH |
2619 | /* Note that the low part is always in RD+1, even in LE mode. */ |
2620 | lo = cpu_gpr[rd + 1]; | |
2621 | hi = cpu_gpr[rd]; | |
2622 | ||
2623 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { | |
2624 | #ifdef CONFIG_ATOMIC128 | |
2625 | TCGv_i32 oi = tcg_temp_new_i32(); | |
2626 | if (ctx->le_mode) { | |
2627 | tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); | |
2628 | gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); | |
2629 | } else { | |
2630 | tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); | |
2631 | gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); | |
2632 | } | |
2633 | tcg_temp_free_i32(oi); | |
2634 | tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); | |
2635 | #else | |
2636 | /* Restart with exclusive lock. */ | |
2637 | gen_helper_exit_atomic(cpu_env); | |
2638 | ctx->base.is_jmp = DISAS_NORETURN; | |
2639 | #endif | |
2640 | } else if (ctx->le_mode) { | |
2641 | tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ); | |
e0498daa | 2642 | gen_addr_add(ctx, EA, EA, 8); |
94bf2658 | 2643 | tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); |
e0498daa | 2644 | } else { |
94bf2658 | 2645 | tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ); |
e0498daa | 2646 | gen_addr_add(ctx, EA, EA, 8); |
94bf2658 | 2647 | tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); |
e0498daa | 2648 | } |
b61f2753 | 2649 | tcg_temp_free(EA); |
be147d08 | 2650 | } |
d9bce9d9 | 2651 | #endif |
79aceca5 FB |
2652 | |
2653 | /*** Integer store ***/ | |
0c8aacd4 | 2654 | #define GEN_ST(name, stop, opc, type) \ |
99e300ef | 2655 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 2656 | { \ |
76db3ba4 AJ |
2657 | TCGv EA; \ |
2658 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2659 | EA = tcg_temp_new(); \ | |
2660 | gen_addr_imm_index(ctx, EA, 0); \ | |
2661 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 | 2662 | tcg_temp_free(EA); \ |
79aceca5 FB |
2663 | } |
2664 | ||
0c8aacd4 | 2665 | #define GEN_STU(name, stop, opc, type) \ |
99e300ef | 2666 | static void glue(gen_, stop##u)(DisasContext *ctx) \ |
79aceca5 | 2667 | { \ |
b61f2753 | 2668 | TCGv EA; \ |
76a66253 | 2669 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 2670 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2671 | return; \ |
9a64fbe4 | 2672 | } \ |
76db3ba4 | 2673 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2674 | EA = tcg_temp_new(); \ |
9d53c753 | 2675 | if (type == PPC_64B) \ |
76db3ba4 | 2676 | gen_addr_imm_index(ctx, EA, 0x03); \ |
9d53c753 | 2677 | else \ |
76db3ba4 AJ |
2678 | gen_addr_imm_index(ctx, EA, 0); \ |
2679 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2680 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2681 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2682 | } |
2683 | ||
0c8aacd4 | 2684 | #define GEN_STUX(name, stop, opc2, opc3, type) \ |
99e300ef | 2685 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 2686 | { \ |
b61f2753 | 2687 | TCGv EA; \ |
76a66253 | 2688 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 2689 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2690 | return; \ |
9a64fbe4 | 2691 | } \ |
76db3ba4 | 2692 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2693 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
2694 | gen_addr_reg_index(ctx, EA); \ |
2695 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2696 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2697 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2698 | } |
2699 | ||
b7815375 | 2700 | #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ |
cd6e9320 | 2701 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 2702 | { \ |
76db3ba4 | 2703 | TCGv EA; \ |
b7815375 | 2704 | chk; \ |
76db3ba4 AJ |
2705 | gen_set_access_type(ctx, ACCESS_INT); \ |
2706 | EA = tcg_temp_new(); \ | |
2707 | gen_addr_reg_index(ctx, EA); \ | |
2708 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 | 2709 | tcg_temp_free(EA); \ |
79aceca5 | 2710 | } |
cd6e9320 | 2711 | #define GEN_STX(name, stop, opc2, opc3, type) \ |
b7815375 BH |
2712 | GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) |
2713 | ||
2714 | #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ | |
2715 | GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) | |
79aceca5 | 2716 | |
0c8aacd4 AJ |
2717 | #define GEN_STS(name, stop, op, type) \ |
2718 | GEN_ST(name, stop, op | 0x20, type); \ | |
2719 | GEN_STU(name, stop, op | 0x21, type); \ | |
2720 | GEN_STUX(name, stop, 0x17, op | 0x01, type); \ | |
2721 | GEN_STX(name, stop, 0x17, op | 0x00, type) | |
79aceca5 FB |
2722 | |
2723 | /* stb stbu stbux stbx */ | |
0c8aacd4 | 2724 | GEN_STS(stb, st8, 0x06, PPC_INTEGER); |
79aceca5 | 2725 | /* sth sthu sthux sthx */ |
0c8aacd4 | 2726 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER); |
79aceca5 | 2727 | /* stw stwu stwux stwx */ |
0c8aacd4 | 2728 | GEN_STS(stw, st32, 0x04, PPC_INTEGER); |
d9bce9d9 | 2729 | #if defined(TARGET_PPC64) |
2468f23d ND |
2730 | GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B); |
2731 | GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B); | |
2732 | GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) | |
b7815375 BH |
2733 | GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) |
2734 | GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) | |
2735 | GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) | |
99e300ef BS |
2736 | |
2737 | static void gen_std(DisasContext *ctx) | |
d9bce9d9 | 2738 | { |
be147d08 | 2739 | int rs; |
b61f2753 | 2740 | TCGv EA; |
be147d08 JM |
2741 | |
2742 | rs = rS(ctx->opcode); | |
84cab1e2 | 2743 | if ((ctx->opcode & 0x3) == 0x2) { /* stq */ |
84cab1e2 TM |
2744 | bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; |
2745 | bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; | |
f89ced5f | 2746 | TCGv hi, lo; |
84cab1e2 | 2747 | |
dfdd3e43 BH |
2748 | if (!(ctx->insns_flags & PPC_64BX)) { |
2749 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
2750 | } | |
2751 | ||
c47493f2 | 2752 | if (!legal_in_user_mode && ctx->pr) { |
9b2fadda | 2753 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2754 | return; |
2755 | } | |
84cab1e2 TM |
2756 | |
2757 | if (!le_is_supported && ctx->le_mode) { | |
65f2475f | 2758 | gen_align_no_le(ctx); |
d9bce9d9 JM |
2759 | return; |
2760 | } | |
84cab1e2 TM |
2761 | |
2762 | if (unlikely(rs & 1)) { | |
2763 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
be147d08 JM |
2764 | return; |
2765 | } | |
76db3ba4 | 2766 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2767 | EA = tcg_temp_new(); |
76db3ba4 | 2768 | gen_addr_imm_index(ctx, EA, 0x03); |
84cab1e2 | 2769 | |
f89ced5f RH |
2770 | /* Note that the low part is always in RS+1, even in LE mode. */ |
2771 | lo = cpu_gpr[rs + 1]; | |
2772 | hi = cpu_gpr[rs]; | |
2773 | ||
2774 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { | |
2775 | #ifdef CONFIG_ATOMIC128 | |
2776 | TCGv_i32 oi = tcg_temp_new_i32(); | |
2777 | if (ctx->le_mode) { | |
2778 | tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); | |
2779 | gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi); | |
2780 | } else { | |
2781 | tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); | |
2782 | gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi); | |
2783 | } | |
2784 | tcg_temp_free_i32(oi); | |
2785 | #else | |
2786 | /* Restart with exclusive lock. */ | |
2787 | gen_helper_exit_atomic(cpu_env); | |
2788 | ctx->base.is_jmp = DISAS_NORETURN; | |
2789 | #endif | |
2790 | } else if (ctx->le_mode) { | |
2791 | tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ); | |
84cab1e2 | 2792 | gen_addr_add(ctx, EA, EA, 8); |
f89ced5f | 2793 | tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ); |
84cab1e2 | 2794 | } else { |
f89ced5f | 2795 | tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ); |
84cab1e2 | 2796 | gen_addr_add(ctx, EA, EA, 8); |
f89ced5f | 2797 | tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ); |
84cab1e2 | 2798 | } |
b61f2753 | 2799 | tcg_temp_free(EA); |
be147d08 | 2800 | } else { |
f89ced5f | 2801 | /* std / stdu */ |
be147d08 JM |
2802 | if (Rc(ctx->opcode)) { |
2803 | if (unlikely(rA(ctx->opcode) == 0)) { | |
e06fcd75 | 2804 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
be147d08 JM |
2805 | return; |
2806 | } | |
2807 | } | |
76db3ba4 | 2808 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2809 | EA = tcg_temp_new(); |
76db3ba4 | 2810 | gen_addr_imm_index(ctx, EA, 0x03); |
2468f23d | 2811 | gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); |
be147d08 | 2812 | if (Rc(ctx->opcode)) |
b61f2753 AJ |
2813 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
2814 | tcg_temp_free(EA); | |
d9bce9d9 | 2815 | } |
d9bce9d9 JM |
2816 | } |
2817 | #endif | |
79aceca5 | 2818 | /*** Integer load and store with byte reverse ***/ |
e22c357b | 2819 | |
79aceca5 | 2820 | /* lhbrx */ |
0c8aacd4 | 2821 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); |
b61f2753 | 2822 | |
79aceca5 | 2823 | /* lwbrx */ |
0c8aacd4 | 2824 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); |
b61f2753 | 2825 | |
cd6e9320 TH |
2826 | #if defined(TARGET_PPC64) |
2827 | /* ldbrx */ | |
ff5f3981 | 2828 | GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); |
804108aa ND |
2829 | /* stdbrx */ |
2830 | GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); | |
cd6e9320 TH |
2831 | #endif /* TARGET_PPC64 */ |
2832 | ||
79aceca5 | 2833 | /* sthbrx */ |
0c8aacd4 | 2834 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); |
79aceca5 | 2835 | /* stwbrx */ |
0c8aacd4 | 2836 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); |
79aceca5 FB |
2837 | |
2838 | /*** Integer load and store multiple ***/ | |
99e300ef | 2839 | |
54623277 | 2840 | /* lmw */ |
99e300ef | 2841 | static void gen_lmw(DisasContext *ctx) |
79aceca5 | 2842 | { |
76db3ba4 AJ |
2843 | TCGv t0; |
2844 | TCGv_i32 t1; | |
5817355e BH |
2845 | |
2846 | if (ctx->le_mode) { | |
2847 | gen_align_no_le(ctx); | |
2848 | return; | |
2849 | } | |
76db3ba4 | 2850 | gen_set_access_type(ctx, ACCESS_INT); |
76db3ba4 AJ |
2851 | t0 = tcg_temp_new(); |
2852 | t1 = tcg_const_i32(rD(ctx->opcode)); | |
2853 | gen_addr_imm_index(ctx, t0, 0); | |
2f5a189c | 2854 | gen_helper_lmw(cpu_env, t0, t1); |
ff4a62cd AJ |
2855 | tcg_temp_free(t0); |
2856 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
2857 | } |
2858 | ||
2859 | /* stmw */ | |
99e300ef | 2860 | static void gen_stmw(DisasContext *ctx) |
79aceca5 | 2861 | { |
76db3ba4 AJ |
2862 | TCGv t0; |
2863 | TCGv_i32 t1; | |
5817355e BH |
2864 | |
2865 | if (ctx->le_mode) { | |
2866 | gen_align_no_le(ctx); | |
2867 | return; | |
2868 | } | |
76db3ba4 | 2869 | gen_set_access_type(ctx, ACCESS_INT); |
76db3ba4 AJ |
2870 | t0 = tcg_temp_new(); |
2871 | t1 = tcg_const_i32(rS(ctx->opcode)); | |
2872 | gen_addr_imm_index(ctx, t0, 0); | |
2f5a189c | 2873 | gen_helper_stmw(cpu_env, t0, t1); |
ff4a62cd AJ |
2874 | tcg_temp_free(t0); |
2875 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
2876 | } |
2877 | ||
2878 | /*** Integer load and store strings ***/ | |
54623277 | 2879 | |
79aceca5 | 2880 | /* lswi */ |
3fc6c082 | 2881 | /* PowerPC32 specification says we must generate an exception if |
9a64fbe4 FB |
2882 | * rA is in the range of registers to be loaded. |
2883 | * In an other hand, IBM says this is valid, but rA won't be loaded. | |
2884 | * For now, I'll follow the spec... | |
2885 | */ | |
99e300ef | 2886 | static void gen_lswi(DisasContext *ctx) |
79aceca5 | 2887 | { |
dfbc799d AJ |
2888 | TCGv t0; |
2889 | TCGv_i32 t1, t2; | |
79aceca5 FB |
2890 | int nb = NB(ctx->opcode); |
2891 | int start = rD(ctx->opcode); | |
9a64fbe4 | 2892 | int ra = rA(ctx->opcode); |
79aceca5 FB |
2893 | int nr; |
2894 | ||
5817355e BH |
2895 | if (ctx->le_mode) { |
2896 | gen_align_no_le(ctx); | |
2897 | return; | |
2898 | } | |
79aceca5 FB |
2899 | if (nb == 0) |
2900 | nb = 32; | |
f0704d78 | 2901 | nr = DIV_ROUND_UP(nb, 4); |
afbee712 | 2902 | if (unlikely(lsw_reg_in_range(start, nr, ra))) { |
e06fcd75 | 2903 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); |
9fddaa0c | 2904 | return; |
297d8e62 | 2905 | } |
76db3ba4 | 2906 | gen_set_access_type(ctx, ACCESS_INT); |
dfbc799d | 2907 | t0 = tcg_temp_new(); |
76db3ba4 | 2908 | gen_addr_register(ctx, t0); |
dfbc799d AJ |
2909 | t1 = tcg_const_i32(nb); |
2910 | t2 = tcg_const_i32(start); | |
2f5a189c | 2911 | gen_helper_lsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
2912 | tcg_temp_free(t0); |
2913 | tcg_temp_free_i32(t1); | |
2914 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
2915 | } |
2916 | ||
2917 | /* lswx */ | |
99e300ef | 2918 | static void gen_lswx(DisasContext *ctx) |
79aceca5 | 2919 | { |
76db3ba4 AJ |
2920 | TCGv t0; |
2921 | TCGv_i32 t1, t2, t3; | |
5817355e BH |
2922 | |
2923 | if (ctx->le_mode) { | |
2924 | gen_align_no_le(ctx); | |
2925 | return; | |
2926 | } | |
76db3ba4 | 2927 | gen_set_access_type(ctx, ACCESS_INT); |
76db3ba4 AJ |
2928 | t0 = tcg_temp_new(); |
2929 | gen_addr_reg_index(ctx, t0); | |
2930 | t1 = tcg_const_i32(rD(ctx->opcode)); | |
2931 | t2 = tcg_const_i32(rA(ctx->opcode)); | |
2932 | t3 = tcg_const_i32(rB(ctx->opcode)); | |
2f5a189c | 2933 | gen_helper_lswx(cpu_env, t0, t1, t2, t3); |
dfbc799d AJ |
2934 | tcg_temp_free(t0); |
2935 | tcg_temp_free_i32(t1); | |
2936 | tcg_temp_free_i32(t2); | |
2937 | tcg_temp_free_i32(t3); | |
79aceca5 FB |
2938 | } |
2939 | ||
2940 | /* stswi */ | |
99e300ef | 2941 | static void gen_stswi(DisasContext *ctx) |
79aceca5 | 2942 | { |
76db3ba4 AJ |
2943 | TCGv t0; |
2944 | TCGv_i32 t1, t2; | |
4b3686fa | 2945 | int nb = NB(ctx->opcode); |
5817355e BH |
2946 | |
2947 | if (ctx->le_mode) { | |
2948 | gen_align_no_le(ctx); | |
2949 | return; | |
2950 | } | |
76db3ba4 | 2951 | gen_set_access_type(ctx, ACCESS_INT); |
76db3ba4 AJ |
2952 | t0 = tcg_temp_new(); |
2953 | gen_addr_register(ctx, t0); | |
4b3686fa FB |
2954 | if (nb == 0) |
2955 | nb = 32; | |
dfbc799d | 2956 | t1 = tcg_const_i32(nb); |
76db3ba4 | 2957 | t2 = tcg_const_i32(rS(ctx->opcode)); |
2f5a189c | 2958 | gen_helper_stsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
2959 | tcg_temp_free(t0); |
2960 | tcg_temp_free_i32(t1); | |
2961 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
2962 | } |
2963 | ||
2964 | /* stswx */ | |
99e300ef | 2965 | static void gen_stswx(DisasContext *ctx) |
79aceca5 | 2966 | { |
76db3ba4 AJ |
2967 | TCGv t0; |
2968 | TCGv_i32 t1, t2; | |
5817355e BH |
2969 | |
2970 | if (ctx->le_mode) { | |
2971 | gen_align_no_le(ctx); | |
2972 | return; | |
2973 | } | |
76db3ba4 | 2974 | gen_set_access_type(ctx, ACCESS_INT); |
76db3ba4 AJ |
2975 | t0 = tcg_temp_new(); |
2976 | gen_addr_reg_index(ctx, t0); | |
2977 | t1 = tcg_temp_new_i32(); | |
dfbc799d AJ |
2978 | tcg_gen_trunc_tl_i32(t1, cpu_xer); |
2979 | tcg_gen_andi_i32(t1, t1, 0x7F); | |
76db3ba4 | 2980 | t2 = tcg_const_i32(rS(ctx->opcode)); |
2f5a189c | 2981 | gen_helper_stsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
2982 | tcg_temp_free(t0); |
2983 | tcg_temp_free_i32(t1); | |
2984 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
2985 | } |
2986 | ||
2987 | /*** Memory synchronisation ***/ | |
2988 | /* eieio */ | |
99e300ef | 2989 | static void gen_eieio(DisasContext *ctx) |
79aceca5 | 2990 | { |
c8fd8373 CLG |
2991 | TCGBar bar = TCG_MO_LD_ST; |
2992 | ||
2993 | /* | |
2994 | * POWER9 has a eieio instruction variant using bit 6 as a hint to | |
2995 | * tell the CPU it is a store-forwarding barrier. | |
2996 | */ | |
2997 | if (ctx->opcode & 0x2000000) { | |
2998 | /* | |
2999 | * ISA says that "Reserved fields in instructions are ignored | |
3000 | * by the processor". So ignore the bit 6 on non-POWER9 CPU but | |
3001 | * as this is not an instruction software should be using, | |
3002 | * complain to the user. | |
3003 | */ | |
3004 | if (!(ctx->insns_flags2 & PPC2_ISA300)) { | |
3005 | qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" | |
3006 | TARGET_FMT_lx "\n", ctx->base.pc_next - 4); | |
3007 | } else { | |
3008 | bar = TCG_MO_ST_LD; | |
3009 | } | |
3010 | } | |
3011 | ||
3012 | tcg_gen_mb(bar | TCG_BAR_SC); | |
79aceca5 FB |
3013 | } |
3014 | ||
c5a8d8f3 | 3015 | #if !defined(CONFIG_USER_ONLY) |
e3cffe6f | 3016 | static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) |
cd0c6f47 | 3017 | { |
c5a8d8f3 BH |
3018 | TCGv_i32 t; |
3019 | TCGLabel *l; | |
cd0c6f47 | 3020 | |
c5a8d8f3 BH |
3021 | if (!ctx->lazy_tlb_flush) { |
3022 | return; | |
3023 | } | |
3024 | l = gen_new_label(); | |
3025 | t = tcg_temp_new_i32(); | |
cd0c6f47 BH |
3026 | tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); |
3027 | tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); | |
e3cffe6f ND |
3028 | if (global) { |
3029 | gen_helper_check_tlb_flush_global(cpu_env); | |
3030 | } else { | |
3031 | gen_helper_check_tlb_flush_local(cpu_env); | |
3032 | } | |
cd0c6f47 BH |
3033 | gen_set_label(l); |
3034 | tcg_temp_free_i32(t); | |
3035 | } | |
3036 | #else | |
e3cffe6f | 3037 | static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } |
cd0c6f47 BH |
3038 | #endif |
3039 | ||
79aceca5 | 3040 | /* isync */ |
99e300ef | 3041 | static void gen_isync(DisasContext *ctx) |
79aceca5 | 3042 | { |
cd0c6f47 BH |
3043 | /* |
3044 | * We need to check for a pending TLB flush. This can only happen in | |
3045 | * kernel mode however so check MSR_PR | |
3046 | */ | |
3047 | if (!ctx->pr) { | |
e3cffe6f | 3048 | gen_check_tlb_flush(ctx, false); |
cd0c6f47 | 3049 | } |
4771df23 | 3050 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); |
e06fcd75 | 3051 | gen_stop_exception(ctx); |
79aceca5 FB |
3052 | } |
3053 | ||
48793c95 ND |
3054 | #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) |
3055 | ||
2a4e6c1b RH |
3056 | static void gen_load_locked(DisasContext *ctx, TCGMemOp memop) |
3057 | { | |
3058 | TCGv gpr = cpu_gpr[rD(ctx->opcode)]; | |
3059 | TCGv t0 = tcg_temp_new(); | |
3060 | ||
3061 | gen_set_access_type(ctx, ACCESS_RES); | |
3062 | gen_addr_reg_index(ctx, t0); | |
3063 | tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); | |
3064 | tcg_gen_mov_tl(cpu_reserve, t0); | |
3065 | tcg_gen_mov_tl(cpu_reserve_val, gpr); | |
3066 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | |
3067 | tcg_temp_free(t0); | |
3068 | } | |
3069 | ||
3070 | #define LARX(name, memop) \ | |
3071 | static void gen_##name(DisasContext *ctx) \ | |
3072 | { \ | |
3073 | gen_load_locked(ctx, memop); \ | |
79aceca5 FB |
3074 | } |
3075 | ||
5c77a786 | 3076 | /* lwarx */ |
48793c95 ND |
3077 | LARX(lbarx, DEF_MEMOP(MO_UB)) |
3078 | LARX(lharx, DEF_MEMOP(MO_UW)) | |
3079 | LARX(lwarx, DEF_MEMOP(MO_UL)) | |
5c77a786 | 3080 | |
20ba8504 RH |
3081 | static void gen_ld_atomic(DisasContext *ctx, TCGMemOp memop) |
3082 | { | |
3083 | uint32_t gpr_FC = FC(ctx->opcode); | |
3084 | TCGv EA = tcg_temp_new(); | |
3085 | TCGv src, dst; | |
3086 | ||
3087 | gen_addr_register(ctx, EA); | |
3088 | dst = cpu_gpr[rD(ctx->opcode)]; | |
3089 | src = cpu_gpr[rD(ctx->opcode) + 1]; | |
3090 | ||
3091 | memop |= MO_ALIGN; | |
3092 | switch (gpr_FC) { | |
3093 | case 0: /* Fetch and add */ | |
3094 | tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); | |
3095 | break; | |
3096 | case 1: /* Fetch and xor */ | |
3097 | tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); | |
3098 | break; | |
3099 | case 2: /* Fetch and or */ | |
3100 | tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); | |
3101 | break; | |
3102 | case 3: /* Fetch and 'and' */ | |
3103 | tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); | |
3104 | break; | |
20ba8504 | 3105 | case 4: /* Fetch and max unsigned */ |
b8ce0f86 RH |
3106 | tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); |
3107 | break; | |
20ba8504 | 3108 | case 5: /* Fetch and max signed */ |
b8ce0f86 RH |
3109 | tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); |
3110 | break; | |
20ba8504 | 3111 | case 6: /* Fetch and min unsigned */ |
b8ce0f86 RH |
3112 | tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); |
3113 | break; | |
20ba8504 | 3114 | case 7: /* Fetch and min signed */ |
b8ce0f86 RH |
3115 | tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); |
3116 | break; | |
3117 | case 8: /* Swap */ | |
3118 | tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); | |
3119 | break; | |
20ba8504 RH |
3120 | case 16: /* compare and swap not equal */ |
3121 | case 24: /* Fetch and increment bounded */ | |
3122 | case 25: /* Fetch and increment equal */ | |
3123 | case 28: /* Fetch and decrement bounded */ | |
3124 | gen_invalid(ctx); | |
3125 | break; | |
3126 | default: | |
3127 | /* invoke data storage error handler */ | |
3128 | gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); | |
3129 | } | |
3130 | tcg_temp_free(EA); | |
3131 | } | |
3132 | ||
3133 | static void gen_lwat(DisasContext *ctx) | |
3134 | { | |
3135 | gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); | |
3136 | } | |
3137 | ||
3138 | #ifdef TARGET_PPC64 | |
3139 | static void gen_ldat(DisasContext *ctx) | |
3140 | { | |
3141 | gen_ld_atomic(ctx, DEF_MEMOP(MO_Q)); | |
3142 | } | |
a68a6146 B |
3143 | #endif |
3144 | ||
9deb041c RH |
3145 | static void gen_st_atomic(DisasContext *ctx, TCGMemOp memop) |
3146 | { | |
3147 | uint32_t gpr_FC = FC(ctx->opcode); | |
3148 | TCGv EA = tcg_temp_new(); | |
3149 | TCGv src, discard; | |
3150 | ||
3151 | gen_addr_register(ctx, EA); | |
3152 | src = cpu_gpr[rD(ctx->opcode)]; | |
3153 | discard = tcg_temp_new(); | |
3154 | ||
3155 | memop |= MO_ALIGN; | |
3156 | switch (gpr_FC) { | |
3157 | case 0: /* add and Store */ | |
3158 | tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); | |
3159 | break; | |
3160 | case 1: /* xor and Store */ | |
3161 | tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); | |
3162 | break; | |
3163 | case 2: /* Or and Store */ | |
3164 | tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); | |
3165 | break; | |
3166 | case 3: /* 'and' and Store */ | |
3167 | tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); | |
3168 | break; | |
3169 | case 4: /* Store max unsigned */ | |
b8ce0f86 RH |
3170 | tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); |
3171 | break; | |
9deb041c | 3172 | case 5: /* Store max signed */ |
b8ce0f86 RH |
3173 | tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); |
3174 | break; | |
9deb041c | 3175 | case 6: /* Store min unsigned */ |
b8ce0f86 RH |
3176 | tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); |
3177 | break; | |
9deb041c | 3178 | case 7: /* Store min signed */ |
b8ce0f86 RH |
3179 | tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); |
3180 | break; | |
9deb041c RH |
3181 | case 24: /* Store twin */ |
3182 | gen_invalid(ctx); | |
3183 | break; | |
3184 | default: | |
3185 | /* invoke data storage error handler */ | |
3186 | gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); | |
3187 | } | |
3188 | tcg_temp_free(discard); | |
3189 | tcg_temp_free(EA); | |
3190 | } | |
3191 | ||
3192 | static void gen_stwat(DisasContext *ctx) | |
3193 | { | |
3194 | gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); | |
3195 | } | |
3196 | ||
3197 | #ifdef TARGET_PPC64 | |
3198 | static void gen_stdat(DisasContext *ctx) | |
3199 | { | |
3200 | gen_st_atomic(ctx, DEF_MEMOP(MO_Q)); | |
3201 | } | |
a3401188 B |
3202 | #endif |
3203 | ||
d8b86898 | 3204 | static void gen_conditional_store(DisasContext *ctx, TCGMemOp memop) |
587c51f7 | 3205 | { |
253ce7b2 ND |
3206 | TCGLabel *l1 = gen_new_label(); |
3207 | TCGLabel *l2 = gen_new_label(); | |
d8b86898 RH |
3208 | TCGv t0 = tcg_temp_new(); |
3209 | int reg = rS(ctx->opcode); | |
4425265b | 3210 | |
d8b86898 RH |
3211 | gen_set_access_type(ctx, ACCESS_RES); |
3212 | gen_addr_reg_index(ctx, t0); | |
3213 | tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); | |
3214 | tcg_temp_free(t0); | |
253ce7b2 ND |
3215 | |
3216 | t0 = tcg_temp_new(); | |
3217 | tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, | |
3218 | cpu_gpr[reg], ctx->mem_idx, | |
3219 | DEF_MEMOP(memop) | MO_ALIGN); | |
3220 | tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); | |
3221 | tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); | |
3222 | tcg_gen_or_tl(t0, t0, cpu_so); | |
3223 | tcg_gen_trunc_tl_i32(cpu_crf[0], t0); | |
3224 | tcg_temp_free(t0); | |
3225 | tcg_gen_br(l2); | |
3226 | ||
587c51f7 | 3227 | gen_set_label(l1); |
4771df23 ND |
3228 | |
3229 | /* Address mismatch implies failure. But we still need to provide the | |
3230 | memory barrier semantics of the instruction. */ | |
3231 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | |
253ce7b2 ND |
3232 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
3233 | ||
3234 | gen_set_label(l2); | |
587c51f7 TM |
3235 | tcg_gen_movi_tl(cpu_reserve, -1); |
3236 | } | |
587c51f7 | 3237 | |
d8b86898 RH |
3238 | #define STCX(name, memop) \ |
3239 | static void gen_##name(DisasContext *ctx) \ | |
3240 | { \ | |
3241 | gen_conditional_store(ctx, memop); \ | |
2391b357 ND |
3242 | } |
3243 | ||
3244 | STCX(stbcx_, DEF_MEMOP(MO_UB)) | |
3245 | STCX(sthcx_, DEF_MEMOP(MO_UW)) | |
3246 | STCX(stwcx_, DEF_MEMOP(MO_UL)) | |
587c51f7 | 3247 | |
426613db | 3248 | #if defined(TARGET_PPC64) |
426613db | 3249 | /* ldarx */ |
48793c95 | 3250 | LARX(ldarx, DEF_MEMOP(MO_Q)) |
2391b357 ND |
3251 | /* stdcx. */ |
3252 | STCX(stdcx_, DEF_MEMOP(MO_Q)) | |
426613db | 3253 | |
9c294d5a TM |
3254 | /* lqarx */ |
3255 | static void gen_lqarx(DisasContext *ctx) | |
3256 | { | |
9c294d5a | 3257 | int rd = rD(ctx->opcode); |
94bf2658 | 3258 | TCGv EA, hi, lo; |
9c294d5a TM |
3259 | |
3260 | if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || | |
3261 | (rd == rB(ctx->opcode)))) { | |
3262 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
3263 | return; | |
3264 | } | |
3265 | ||
3266 | gen_set_access_type(ctx, ACCESS_RES); | |
94bf2658 | 3267 | EA = tcg_temp_new(); |
9c294d5a | 3268 | gen_addr_reg_index(ctx, EA); |
94bf2658 RH |
3269 | |
3270 | /* Note that the low part is always in RD+1, even in LE mode. */ | |
3271 | lo = cpu_gpr[rd + 1]; | |
3272 | hi = cpu_gpr[rd]; | |
3273 | ||
3274 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { | |
3275 | #ifdef CONFIG_ATOMIC128 | |
3276 | TCGv_i32 oi = tcg_temp_new_i32(); | |
3277 | if (ctx->le_mode) { | |
3278 | tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16, | |
3279 | ctx->mem_idx)); | |
3280 | gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); | |
3281 | } else { | |
3282 | tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16, | |
3283 | ctx->mem_idx)); | |
3284 | gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); | |
3285 | } | |
3286 | tcg_temp_free_i32(oi); | |
3287 | tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); | |
3288 | #else | |
3289 | /* Restart with exclusive lock. */ | |
3290 | gen_helper_exit_atomic(cpu_env); | |
3291 | ctx->base.is_jmp = DISAS_NORETURN; | |
3292 | tcg_temp_free(EA); | |
3293 | return; | |
3294 | #endif | |
3295 | } else if (ctx->le_mode) { | |
3296 | tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16); | |
3297 | tcg_gen_mov_tl(cpu_reserve, EA); | |
3298 | gen_addr_add(ctx, EA, EA, 8); | |
3299 | tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); | |
9c294d5a | 3300 | } else { |
94bf2658 RH |
3301 | tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16); |
3302 | tcg_gen_mov_tl(cpu_reserve, EA); | |
3303 | gen_addr_add(ctx, EA, EA, 8); | |
3304 | tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); | |
9c294d5a | 3305 | } |
9c294d5a | 3306 | tcg_temp_free(EA); |
94bf2658 RH |
3307 | |
3308 | tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); | |
3309 | tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); | |
9c294d5a TM |
3310 | } |
3311 | ||
aa2008af ND |
3312 | /* stqcx. */ |
3313 | static void gen_stqcx_(DisasContext *ctx) | |
3314 | { | |
4a9b3c5d RH |
3315 | int rs = rS(ctx->opcode); |
3316 | TCGv EA, hi, lo; | |
aa2008af | 3317 | |
4a9b3c5d | 3318 | if (unlikely(rs & 1)) { |
aa2008af ND |
3319 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
3320 | return; | |
3321 | } | |
4a9b3c5d | 3322 | |
aa2008af | 3323 | gen_set_access_type(ctx, ACCESS_RES); |
4a9b3c5d | 3324 | EA = tcg_temp_new(); |
aa2008af | 3325 | gen_addr_reg_index(ctx, EA); |
aa2008af | 3326 | |
4a9b3c5d RH |
3327 | /* Note that the low part is always in RS+1, even in LE mode. */ |
3328 | lo = cpu_gpr[rs + 1]; | |
3329 | hi = cpu_gpr[rs]; | |
aa2008af | 3330 | |
4a9b3c5d RH |
3331 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { |
3332 | TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16); | |
3333 | #ifdef CONFIG_ATOMIC128 | |
3334 | if (ctx->le_mode) { | |
3335 | gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, EA, lo, hi, oi); | |
3336 | } else { | |
3337 | gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, EA, lo, hi, oi); | |
3338 | } | |
3339 | #else | |
3340 | /* Restart with exclusive lock. */ | |
3341 | gen_helper_exit_atomic(cpu_env); | |
3342 | ctx->base.is_jmp = DISAS_NORETURN; | |
3343 | #endif | |
3344 | tcg_temp_free(EA); | |
3345 | tcg_temp_free_i32(oi); | |
aa2008af | 3346 | } else { |
4a9b3c5d RH |
3347 | TCGLabel *lab_fail = gen_new_label(); |
3348 | TCGLabel *lab_over = gen_new_label(); | |
3349 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
3350 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
aa2008af | 3351 | |
4a9b3c5d RH |
3352 | tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); |
3353 | tcg_temp_free(EA); | |
aa2008af | 3354 | |
4a9b3c5d RH |
3355 | gen_qemu_ld64_i64(ctx, t0, cpu_reserve); |
3356 | tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode | |
3357 | ? offsetof(CPUPPCState, reserve_val2) | |
3358 | : offsetof(CPUPPCState, reserve_val))); | |
3359 | tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); | |
3360 | ||
3361 | tcg_gen_addi_i64(t0, cpu_reserve, 8); | |
3362 | gen_qemu_ld64_i64(ctx, t0, t0); | |
3363 | tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode | |
3364 | ? offsetof(CPUPPCState, reserve_val) | |
3365 | : offsetof(CPUPPCState, reserve_val2))); | |
3366 | tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); | |
3367 | ||
3368 | /* Success */ | |
3369 | gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve); | |
3370 | tcg_gen_addi_i64(t0, cpu_reserve, 8); | |
3371 | gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0); | |
3372 | ||
3373 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); | |
3374 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); | |
3375 | tcg_gen_br(lab_over); | |
3376 | ||
3377 | gen_set_label(lab_fail); | |
3378 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); | |
3379 | ||
3380 | gen_set_label(lab_over); | |
3381 | tcg_gen_movi_tl(cpu_reserve, -1); | |
3382 | tcg_temp_free_i64(t0); | |
3383 | tcg_temp_free_i64(t1); | |
3384 | } | |
3385 | } | |
426613db JM |
3386 | #endif /* defined(TARGET_PPC64) */ |
3387 | ||
79aceca5 | 3388 | /* sync */ |
99e300ef | 3389 | static void gen_sync(DisasContext *ctx) |
79aceca5 | 3390 | { |
cd0c6f47 BH |
3391 | uint32_t l = (ctx->opcode >> 21) & 3; |
3392 | ||
3393 | /* | |
c5a8d8f3 BH |
3394 | * We may need to check for a pending TLB flush. |
3395 | * | |
3396 | * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. | |
3397 | * | |
3398 | * Additionally, this can only happen in kernel mode however so | |
3399 | * check MSR_PR as well. | |
cd0c6f47 | 3400 | */ |
c5a8d8f3 | 3401 | if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { |
e3cffe6f | 3402 | gen_check_tlb_flush(ctx, true); |
cd0c6f47 | 3403 | } |
4771df23 | 3404 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); |
79aceca5 FB |
3405 | } |
3406 | ||
0db1b20e | 3407 | /* wait */ |
99e300ef | 3408 | static void gen_wait(DisasContext *ctx) |
0db1b20e | 3409 | { |
35b5066e | 3410 | TCGv_i32 t0 = tcg_const_i32(1); |
259186a7 AF |
3411 | tcg_gen_st_i32(t0, cpu_env, |
3412 | -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); | |
931ff272 | 3413 | tcg_temp_free_i32(t0); |
0db1b20e | 3414 | /* Stop translation, as the CPU is supposed to sleep from now */ |
b6bac4bc | 3415 | gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); |
0db1b20e JM |
3416 | } |
3417 | ||
7778a575 BH |
3418 | #if defined(TARGET_PPC64) |
3419 | static void gen_doze(DisasContext *ctx) | |
3420 | { | |
3421 | #if defined(CONFIG_USER_ONLY) | |
3422 | GEN_PRIV; | |
3423 | #else | |
3424 | TCGv_i32 t; | |
3425 | ||
3426 | CHK_HV; | |
3427 | t = tcg_const_i32(PPC_PM_DOZE); | |
3428 | gen_helper_pminsn(cpu_env, t); | |
3429 | tcg_temp_free_i32(t); | |
3430 | gen_stop_exception(ctx); | |
3431 | #endif /* defined(CONFIG_USER_ONLY) */ | |
3432 | } | |
3433 | ||
3434 | static void gen_nap(DisasContext *ctx) | |
3435 | { | |
3436 | #if defined(CONFIG_USER_ONLY) | |
3437 | GEN_PRIV; | |
3438 | #else | |
3439 | TCGv_i32 t; | |
3440 | ||
3441 | CHK_HV; | |
3442 | t = tcg_const_i32(PPC_PM_NAP); | |
3443 | gen_helper_pminsn(cpu_env, t); | |
3444 | tcg_temp_free_i32(t); | |
3445 | gen_stop_exception(ctx); | |
3446 | #endif /* defined(CONFIG_USER_ONLY) */ | |
3447 | } | |
3448 | ||
cdee0e72 ND |
3449 | static void gen_stop(DisasContext *ctx) |
3450 | { | |
3451 | gen_nap(ctx); | |
3452 | } | |
3453 | ||
7778a575 BH |
3454 | static void gen_sleep(DisasContext *ctx) |
3455 | { | |
3456 | #if defined(CONFIG_USER_ONLY) | |
3457 | GEN_PRIV; | |
3458 | #else | |
3459 | TCGv_i32 t; | |
3460 | ||
3461 | CHK_HV; | |
3462 | t = tcg_const_i32(PPC_PM_SLEEP); | |
3463 | gen_helper_pminsn(cpu_env, t); | |
3464 | tcg_temp_free_i32(t); | |
3465 | gen_stop_exception(ctx); | |
3466 | #endif /* defined(CONFIG_USER_ONLY) */ | |
3467 | } | |
3468 | ||
3469 | static void gen_rvwinkle(DisasContext *ctx) | |
3470 | { | |
3471 | #if defined(CONFIG_USER_ONLY) | |
3472 | GEN_PRIV; | |
3473 | #else | |
3474 | TCGv_i32 t; | |
3475 | ||
3476 | CHK_HV; | |
3477 | t = tcg_const_i32(PPC_PM_RVWINKLE); | |
3478 | gen_helper_pminsn(cpu_env, t); | |
3479 | tcg_temp_free_i32(t); | |
3480 | gen_stop_exception(ctx); | |
3481 | #endif /* defined(CONFIG_USER_ONLY) */ | |
3482 | } | |
3483 | #endif /* #if defined(TARGET_PPC64) */ | |
3484 | ||
697ab892 DG |
3485 | static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) |
3486 | { | |
3487 | #if defined(TARGET_PPC64) | |
3488 | if (ctx->has_cfar) | |
3489 | tcg_gen_movi_tl(cpu_cfar, nip); | |
3490 | #endif | |
3491 | } | |
3492 | ||
90aa39a1 SF |
3493 | static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) |
3494 | { | |
3495 | if (unlikely(ctx->singlestep_enabled)) { | |
3496 | return false; | |
3497 | } | |
3498 | ||
3499 | #ifndef CONFIG_USER_ONLY | |
b6bac4bc | 3500 | return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); |
90aa39a1 SF |
3501 | #else |
3502 | return true; | |
3503 | #endif | |
3504 | } | |
3505 | ||
79aceca5 | 3506 | /*** Branch ***/ |
c4a2e3a9 | 3507 | static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) |
c1942362 | 3508 | { |
e0c8f9ce | 3509 | if (NARROW_MODE(ctx)) { |
a2ffb812 | 3510 | dest = (uint32_t) dest; |
e0c8f9ce | 3511 | } |
90aa39a1 | 3512 | if (use_goto_tb(ctx, dest)) { |
57fec1fe | 3513 | tcg_gen_goto_tb(n); |
a2ffb812 | 3514 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
07ea28b4 | 3515 | tcg_gen_exit_tb(ctx->base.tb, n); |
c1942362 | 3516 | } else { |
a2ffb812 | 3517 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
8cbcb4fa AJ |
3518 | if (unlikely(ctx->singlestep_enabled)) { |
3519 | if ((ctx->singlestep_enabled & | |
bdc4e053 | 3520 | (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) && |
f0cc4aa8 JG |
3521 | (ctx->exception == POWERPC_EXCP_BRANCH || |
3522 | ctx->exception == POWERPC_EXCP_TRACE)) { | |
bd6fefe7 | 3523 | gen_exception_nip(ctx, POWERPC_EXCP_TRACE, dest); |
8cbcb4fa AJ |
3524 | } |
3525 | if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) { | |
e06fcd75 | 3526 | gen_debug_exception(ctx); |
8cbcb4fa AJ |
3527 | } |
3528 | } | |
c4a2e3a9 | 3529 | tcg_gen_lookup_and_goto_ptr(); |
c1942362 | 3530 | } |
c53be334 FB |
3531 | } |
3532 | ||
636aa200 | 3533 | static inline void gen_setlr(DisasContext *ctx, target_ulong nip) |
e1833e1f | 3534 | { |
e0c8f9ce RH |
3535 | if (NARROW_MODE(ctx)) { |
3536 | nip = (uint32_t)nip; | |
3537 | } | |
3538 | tcg_gen_movi_tl(cpu_lr, nip); | |
e1833e1f JM |
3539 | } |
3540 | ||
79aceca5 | 3541 | /* b ba bl bla */ |
99e300ef | 3542 | static void gen_b(DisasContext *ctx) |
79aceca5 | 3543 | { |
76a66253 | 3544 | target_ulong li, target; |
38a64f9d | 3545 | |
8cbcb4fa | 3546 | ctx->exception = POWERPC_EXCP_BRANCH; |
38a64f9d | 3547 | /* sign extend LI */ |
e0c8f9ce RH |
3548 | li = LI(ctx->opcode); |
3549 | li = (li ^ 0x02000000) - 0x02000000; | |
3550 | if (likely(AA(ctx->opcode) == 0)) { | |
b6bac4bc | 3551 | target = ctx->base.pc_next + li - 4; |
e0c8f9ce | 3552 | } else { |
9a64fbe4 | 3553 | target = li; |
e0c8f9ce RH |
3554 | } |
3555 | if (LK(ctx->opcode)) { | |
b6bac4bc | 3556 | gen_setlr(ctx, ctx->base.pc_next); |
e0c8f9ce | 3557 | } |
b6bac4bc | 3558 | gen_update_cfar(ctx, ctx->base.pc_next - 4); |
c1942362 | 3559 | gen_goto_tb(ctx, 0, target); |
79aceca5 FB |
3560 | } |
3561 | ||
e98a6e40 FB |
3562 | #define BCOND_IM 0 |
3563 | #define BCOND_LR 1 | |
3564 | #define BCOND_CTR 2 | |
52a4984d | 3565 | #define BCOND_TAR 3 |
e98a6e40 | 3566 | |
c4a2e3a9 | 3567 | static void gen_bcond(DisasContext *ctx, int type) |
d9bce9d9 | 3568 | { |
d9bce9d9 | 3569 | uint32_t bo = BO(ctx->opcode); |
42a268c2 | 3570 | TCGLabel *l1; |
a2ffb812 | 3571 | TCGv target; |
e98a6e40 | 3572 | |
8cbcb4fa | 3573 | ctx->exception = POWERPC_EXCP_BRANCH; |
52a4984d | 3574 | if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { |
a7812ae4 | 3575 | target = tcg_temp_local_new(); |
a2ffb812 AJ |
3576 | if (type == BCOND_CTR) |
3577 | tcg_gen_mov_tl(target, cpu_ctr); | |
52a4984d TM |
3578 | else if (type == BCOND_TAR) |
3579 | gen_load_spr(target, SPR_TAR); | |
a2ffb812 AJ |
3580 | else |
3581 | tcg_gen_mov_tl(target, cpu_lr); | |
d2e9fd8f | 3582 | } else { |
f764718d | 3583 | target = NULL; |
e98a6e40 | 3584 | } |
e1833e1f | 3585 | if (LK(ctx->opcode)) |
b6bac4bc | 3586 | gen_setlr(ctx, ctx->base.pc_next); |
a2ffb812 AJ |
3587 | l1 = gen_new_label(); |
3588 | if ((bo & 0x4) == 0) { | |
3589 | /* Decrement and test CTR */ | |
a7812ae4 | 3590 | TCGv temp = tcg_temp_new(); |
a2ffb812 | 3591 | if (unlikely(type == BCOND_CTR)) { |
e06fcd75 | 3592 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
a2ffb812 AJ |
3593 | return; |
3594 | } | |
3595 | tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); | |
e0c8f9ce | 3596 | if (NARROW_MODE(ctx)) { |
a2ffb812 | 3597 | tcg_gen_ext32u_tl(temp, cpu_ctr); |
e0c8f9ce | 3598 | } else { |
a2ffb812 | 3599 | tcg_gen_mov_tl(temp, cpu_ctr); |
e0c8f9ce | 3600 | } |
a2ffb812 AJ |
3601 | if (bo & 0x2) { |
3602 | tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); | |
3603 | } else { | |
3604 | tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); | |
e98a6e40 | 3605 | } |
a7812ae4 | 3606 | tcg_temp_free(temp); |
a2ffb812 AJ |
3607 | } |
3608 | if ((bo & 0x10) == 0) { | |
3609 | /* Test CR */ | |
3610 | uint32_t bi = BI(ctx->opcode); | |
8f9fb7ac | 3611 | uint32_t mask = 0x08 >> (bi & 0x03); |
a7812ae4 | 3612 | TCGv_i32 temp = tcg_temp_new_i32(); |
a2ffb812 | 3613 | |
d9bce9d9 | 3614 | if (bo & 0x8) { |
a2ffb812 AJ |
3615 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
3616 | tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); | |
d9bce9d9 | 3617 | } else { |
a2ffb812 AJ |
3618 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
3619 | tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); | |
d9bce9d9 | 3620 | } |
a7812ae4 | 3621 | tcg_temp_free_i32(temp); |
d9bce9d9 | 3622 | } |
b6bac4bc | 3623 | gen_update_cfar(ctx, ctx->base.pc_next - 4); |
e98a6e40 | 3624 | if (type == BCOND_IM) { |
a2ffb812 AJ |
3625 | target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); |
3626 | if (likely(AA(ctx->opcode) == 0)) { | |
b6bac4bc | 3627 | gen_goto_tb(ctx, 0, ctx->base.pc_next + li - 4); |
a2ffb812 AJ |
3628 | } else { |
3629 | gen_goto_tb(ctx, 0, li); | |
3630 | } | |
e98a6e40 | 3631 | } else { |
e0c8f9ce | 3632 | if (NARROW_MODE(ctx)) { |
a2ffb812 | 3633 | tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); |
e0c8f9ce | 3634 | } else { |
a2ffb812 | 3635 | tcg_gen_andi_tl(cpu_nip, target, ~3); |
e0c8f9ce | 3636 | } |
c4a2e3a9 | 3637 | tcg_gen_lookup_and_goto_ptr(); |
c80d1df5 AG |
3638 | tcg_temp_free(target); |
3639 | } | |
c4a2e3a9 RH |
3640 | if ((bo & 0x14) != 0x14) { |
3641 | gen_set_label(l1); | |
b6bac4bc | 3642 | gen_goto_tb(ctx, 1, ctx->base.pc_next); |
c4a2e3a9 | 3643 | } |
e98a6e40 FB |
3644 | } |
3645 | ||
99e300ef | 3646 | static void gen_bc(DisasContext *ctx) |
3b46e624 | 3647 | { |
e98a6e40 FB |
3648 | gen_bcond(ctx, BCOND_IM); |
3649 | } | |
3650 | ||
99e300ef | 3651 | static void gen_bcctr(DisasContext *ctx) |
3b46e624 | 3652 | { |
e98a6e40 FB |
3653 | gen_bcond(ctx, BCOND_CTR); |
3654 | } | |
3655 | ||
99e300ef | 3656 | static void gen_bclr(DisasContext *ctx) |
3b46e624 | 3657 | { |
e98a6e40 FB |
3658 | gen_bcond(ctx, BCOND_LR); |
3659 | } | |
79aceca5 | 3660 | |
52a4984d TM |
3661 | static void gen_bctar(DisasContext *ctx) |
3662 | { | |
3663 | gen_bcond(ctx, BCOND_TAR); | |
3664 | } | |
3665 | ||
79aceca5 | 3666 | /*** Condition register logical ***/ |
e1571908 | 3667 | #define GEN_CRLOGIC(name, tcg_op, opc) \ |
99e300ef | 3668 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 3669 | { \ |
fc0d441e JM |
3670 | uint8_t bitmask; \ |
3671 | int sh; \ | |
a7812ae4 | 3672 | TCGv_i32 t0, t1; \ |
fc0d441e | 3673 | sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ |
a7812ae4 | 3674 | t0 = tcg_temp_new_i32(); \ |
fc0d441e | 3675 | if (sh > 0) \ |
fea0c503 | 3676 | tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ |
fc0d441e | 3677 | else if (sh < 0) \ |
fea0c503 | 3678 | tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ |
e1571908 | 3679 | else \ |
fea0c503 | 3680 | tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ |
a7812ae4 | 3681 | t1 = tcg_temp_new_i32(); \ |
fc0d441e JM |
3682 | sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ |
3683 | if (sh > 0) \ | |
fea0c503 | 3684 | tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ |
fc0d441e | 3685 | else if (sh < 0) \ |
fea0c503 | 3686 | tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ |
e1571908 | 3687 | else \ |
fea0c503 AJ |
3688 | tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ |
3689 | tcg_op(t0, t0, t1); \ | |
8f9fb7ac | 3690 | bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ |
fea0c503 AJ |
3691 | tcg_gen_andi_i32(t0, t0, bitmask); \ |
3692 | tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ | |
3693 | tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ | |
a7812ae4 PB |
3694 | tcg_temp_free_i32(t0); \ |
3695 | tcg_temp_free_i32(t1); \ | |
79aceca5 FB |
3696 | } |
3697 | ||
3698 | /* crand */ | |
e1571908 | 3699 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); |
79aceca5 | 3700 | /* crandc */ |
e1571908 | 3701 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); |
79aceca5 | 3702 | /* creqv */ |
e1571908 | 3703 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); |
79aceca5 | 3704 | /* crnand */ |
e1571908 | 3705 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); |
79aceca5 | 3706 | /* crnor */ |
e1571908 | 3707 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); |
79aceca5 | 3708 | /* cror */ |
e1571908 | 3709 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); |
79aceca5 | 3710 | /* crorc */ |
e1571908 | 3711 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); |
79aceca5 | 3712 | /* crxor */ |
e1571908 | 3713 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); |
99e300ef | 3714 | |
54623277 | 3715 | /* mcrf */ |
99e300ef | 3716 | static void gen_mcrf(DisasContext *ctx) |
79aceca5 | 3717 | { |
47e4661c | 3718 | tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); |
79aceca5 FB |
3719 | } |
3720 | ||
3721 | /*** System linkage ***/ | |
99e300ef | 3722 | |
c47493f2 | 3723 | /* rfi (supervisor only) */ |
99e300ef | 3724 | static void gen_rfi(DisasContext *ctx) |
79aceca5 | 3725 | { |
9a64fbe4 | 3726 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 3727 | GEN_PRIV; |
9a64fbe4 | 3728 | #else |
6ca038c2 BH |
3729 | /* This instruction doesn't exist anymore on 64-bit server |
3730 | * processors compliant with arch 2.x | |
a2e71b28 | 3731 | */ |
6ca038c2 BH |
3732 | if (ctx->insns_flags & PPC_SEGMENT_64B) { |
3733 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
3734 | return; | |
3735 | } | |
9a64fbe4 | 3736 | /* Restore CPU state */ |
9b2fadda | 3737 | CHK_SV; |
b6bac4bc | 3738 | gen_update_cfar(ctx, ctx->base.pc_next - 4); |
e5f17ac6 | 3739 | gen_helper_rfi(cpu_env); |
e06fcd75 | 3740 | gen_sync_exception(ctx); |
9a64fbe4 | 3741 | #endif |
79aceca5 FB |
3742 | } |
3743 | ||
426613db | 3744 | #if defined(TARGET_PPC64) |
99e300ef | 3745 | static void gen_rfid(DisasContext *ctx) |
426613db JM |
3746 | { |
3747 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 3748 | GEN_PRIV; |
426613db JM |
3749 | #else |
3750 | /* Restore CPU state */ | |
9b2fadda | 3751 | CHK_SV; |
b6bac4bc | 3752 | gen_update_cfar(ctx, ctx->base.pc_next - 4); |
e5f17ac6 | 3753 | gen_helper_rfid(cpu_env); |
e06fcd75 | 3754 | gen_sync_exception(ctx); |
426613db JM |
3755 | #endif |
3756 | } | |
426613db | 3757 | |
99e300ef | 3758 | static void gen_hrfid(DisasContext *ctx) |
be147d08 JM |
3759 | { |
3760 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 3761 | GEN_PRIV; |
be147d08 JM |
3762 | #else |
3763 | /* Restore CPU state */ | |
9b2fadda | 3764 | CHK_HV; |
e5f17ac6 | 3765 | gen_helper_hrfid(cpu_env); |
e06fcd75 | 3766 | gen_sync_exception(ctx); |
be147d08 JM |
3767 | #endif |
3768 | } | |
3769 | #endif | |
3770 | ||
79aceca5 | 3771 | /* sc */ |
417bf010 JM |
3772 | #if defined(CONFIG_USER_ONLY) |
3773 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER | |
3774 | #else | |
3775 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL | |
3776 | #endif | |
99e300ef | 3777 | static void gen_sc(DisasContext *ctx) |
79aceca5 | 3778 | { |
e1833e1f JM |
3779 | uint32_t lev; |
3780 | ||
3781 | lev = (ctx->opcode >> 5) & 0x7F; | |
e06fcd75 | 3782 | gen_exception_err(ctx, POWERPC_SYSCALL, lev); |
79aceca5 FB |
3783 | } |
3784 | ||
3785 | /*** Trap ***/ | |
99e300ef | 3786 | |
22b56ee5 BH |
3787 | /* Check for unconditional traps (always or never) */ |
3788 | static bool check_unconditional_trap(DisasContext *ctx) | |
3789 | { | |
3790 | /* Trap never */ | |
3791 | if (TO(ctx->opcode) == 0) { | |
3792 | return true; | |
3793 | } | |
3794 | /* Trap always */ | |
3795 | if (TO(ctx->opcode) == 31) { | |
3796 | gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); | |
3797 | return true; | |
3798 | } | |
3799 | return false; | |
3800 | } | |
3801 | ||
54623277 | 3802 | /* tw */ |
99e300ef | 3803 | static void gen_tw(DisasContext *ctx) |
79aceca5 | 3804 | { |
22b56ee5 BH |
3805 | TCGv_i32 t0; |
3806 | ||
3807 | if (check_unconditional_trap(ctx)) { | |
3808 | return; | |
3809 | } | |
3810 | t0 = tcg_const_i32(TO(ctx->opcode)); | |
e5f17ac6 BS |
3811 | gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
3812 | t0); | |
cab3bee2 | 3813 | tcg_temp_free_i32(t0); |
79aceca5 FB |
3814 | } |
3815 | ||
3816 | /* twi */ | |
99e300ef | 3817 | static void gen_twi(DisasContext *ctx) |
79aceca5 | 3818 | { |
22b56ee5 BH |
3819 | TCGv t0; |
3820 | TCGv_i32 t1; | |
3821 | ||
3822 | if (check_unconditional_trap(ctx)) { | |
3823 | return; | |
3824 | } | |
3825 | t0 = tcg_const_tl(SIMM(ctx->opcode)); | |
3826 | t1 = tcg_const_i32(TO(ctx->opcode)); | |
e5f17ac6 | 3827 | gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); |
cab3bee2 AJ |
3828 | tcg_temp_free(t0); |
3829 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
3830 | } |
3831 | ||
d9bce9d9 JM |
3832 | #if defined(TARGET_PPC64) |
3833 | /* td */ | |
99e300ef | 3834 | static void gen_td(DisasContext *ctx) |
d9bce9d9 | 3835 | { |
22b56ee5 BH |
3836 | TCGv_i32 t0; |
3837 | ||
3838 | if (check_unconditional_trap(ctx)) { | |
3839 | return; | |
3840 | } | |
3841 | t0 = tcg_const_i32(TO(ctx->opcode)); | |
e5f17ac6 BS |
3842 | gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
3843 | t0); | |
cab3bee2 | 3844 | tcg_temp_free_i32(t0); |
d9bce9d9 JM |
3845 | } |
3846 | ||
3847 | /* tdi */ | |
99e300ef | 3848 | static void gen_tdi(DisasContext *ctx) |
d9bce9d9 | 3849 | { |
22b56ee5 BH |
3850 | TCGv t0; |
3851 | TCGv_i32 t1; | |
3852 | ||
3853 | if (check_unconditional_trap(ctx)) { | |
3854 | return; | |
3855 | } | |
3856 | t0 = tcg_const_tl(SIMM(ctx->opcode)); | |
3857 | t1 = tcg_const_i32(TO(ctx->opcode)); | |
e5f17ac6 | 3858 | gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); |
cab3bee2 AJ |
3859 | tcg_temp_free(t0); |
3860 | tcg_temp_free_i32(t1); | |
d9bce9d9 JM |
3861 | } |
3862 | #endif | |
3863 | ||
79aceca5 | 3864 | /*** Processor control ***/ |
99e300ef | 3865 | |
dd09c361 | 3866 | static void gen_read_xer(DisasContext *ctx, TCGv dst) |
da91a00f RH |
3867 | { |
3868 | TCGv t0 = tcg_temp_new(); | |
3869 | TCGv t1 = tcg_temp_new(); | |
3870 | TCGv t2 = tcg_temp_new(); | |
3871 | tcg_gen_mov_tl(dst, cpu_xer); | |
3872 | tcg_gen_shli_tl(t0, cpu_so, XER_SO); | |
3873 | tcg_gen_shli_tl(t1, cpu_ov, XER_OV); | |
3874 | tcg_gen_shli_tl(t2, cpu_ca, XER_CA); | |
3875 | tcg_gen_or_tl(t0, t0, t1); | |
3876 | tcg_gen_or_tl(dst, dst, t2); | |
3877 | tcg_gen_or_tl(dst, dst, t0); | |
dd09c361 ND |
3878 | if (is_isa300(ctx)) { |
3879 | tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); | |
3880 | tcg_gen_or_tl(dst, dst, t0); | |
3881 | tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); | |
3882 | tcg_gen_or_tl(dst, dst, t0); | |
3883 | } | |
da91a00f RH |
3884 | tcg_temp_free(t0); |
3885 | tcg_temp_free(t1); | |
3886 | tcg_temp_free(t2); | |
3887 | } | |
3888 | ||
3889 | static void gen_write_xer(TCGv src) | |
3890 | { | |
dd09c361 | 3891 | /* Write all flags, while reading back check for isa300 */ |
da91a00f | 3892 | tcg_gen_andi_tl(cpu_xer, src, |
dd09c361 ND |
3893 | ~((1u << XER_SO) | |
3894 | (1u << XER_OV) | (1u << XER_OV32) | | |
3895 | (1u << XER_CA) | (1u << XER_CA32))); | |
3896 | tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); | |
3897 | tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); | |
1bd33d0d ND |
3898 | tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); |
3899 | tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); | |
3900 | tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); | |
da91a00f RH |
3901 | } |
3902 | ||
54623277 | 3903 | /* mcrxr */ |
99e300ef | 3904 | static void gen_mcrxr(DisasContext *ctx) |
79aceca5 | 3905 | { |
da91a00f RH |
3906 | TCGv_i32 t0 = tcg_temp_new_i32(); |
3907 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
3908 | TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; | |
3909 | ||
3910 | tcg_gen_trunc_tl_i32(t0, cpu_so); | |
3911 | tcg_gen_trunc_tl_i32(t1, cpu_ov); | |
3912 | tcg_gen_trunc_tl_i32(dst, cpu_ca); | |
294d1292 SB |
3913 | tcg_gen_shli_i32(t0, t0, 3); |
3914 | tcg_gen_shli_i32(t1, t1, 2); | |
3915 | tcg_gen_shli_i32(dst, dst, 1); | |
da91a00f RH |
3916 | tcg_gen_or_i32(dst, dst, t0); |
3917 | tcg_gen_or_i32(dst, dst, t1); | |
3918 | tcg_temp_free_i32(t0); | |
3919 | tcg_temp_free_i32(t1); | |
3920 | ||
3921 | tcg_gen_movi_tl(cpu_so, 0); | |
3922 | tcg_gen_movi_tl(cpu_ov, 0); | |
3923 | tcg_gen_movi_tl(cpu_ca, 0); | |
79aceca5 FB |
3924 | } |
3925 | ||
b63d0434 ND |
3926 | #ifdef TARGET_PPC64 |
3927 | /* mcrxrx */ | |
3928 | static void gen_mcrxrx(DisasContext *ctx) | |
3929 | { | |
3930 | TCGv t0 = tcg_temp_new(); | |
3931 | TCGv t1 = tcg_temp_new(); | |
3932 | TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; | |
3933 | ||
3934 | /* copy OV and OV32 */ | |
3935 | tcg_gen_shli_tl(t0, cpu_ov, 1); | |
3936 | tcg_gen_or_tl(t0, t0, cpu_ov32); | |
3937 | tcg_gen_shli_tl(t0, t0, 2); | |
3938 | /* copy CA and CA32 */ | |
3939 | tcg_gen_shli_tl(t1, cpu_ca, 1); | |
3940 | tcg_gen_or_tl(t1, t1, cpu_ca32); | |
3941 | tcg_gen_or_tl(t0, t0, t1); | |
3942 | tcg_gen_trunc_tl_i32(dst, t0); | |
3943 | tcg_temp_free(t0); | |
3944 | tcg_temp_free(t1); | |
3945 | } | |
3946 | #endif | |
3947 | ||
0cfe11ea | 3948 | /* mfcr mfocrf */ |
99e300ef | 3949 | static void gen_mfcr(DisasContext *ctx) |
79aceca5 | 3950 | { |
76a66253 | 3951 | uint32_t crm, crn; |
3b46e624 | 3952 | |
76a66253 JM |
3953 | if (likely(ctx->opcode & 0x00100000)) { |
3954 | crm = CRM(ctx->opcode); | |
8dd640e4 | 3955 | if (likely(crm && ((crm & (crm - 1)) == 0))) { |
0cfe11ea | 3956 | crn = ctz32 (crm); |
e1571908 | 3957 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); |
0497d2f4 AJ |
3958 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], |
3959 | cpu_gpr[rD(ctx->opcode)], crn * 4); | |
76a66253 | 3960 | } |
d9bce9d9 | 3961 | } else { |
651721b2 AJ |
3962 | TCGv_i32 t0 = tcg_temp_new_i32(); |
3963 | tcg_gen_mov_i32(t0, cpu_crf[0]); | |
3964 | tcg_gen_shli_i32(t0, t0, 4); | |
3965 | tcg_gen_or_i32(t0, t0, cpu_crf[1]); | |
3966 | tcg_gen_shli_i32(t0, t0, 4); | |
3967 | tcg_gen_or_i32(t0, t0, cpu_crf[2]); | |
3968 | tcg_gen_shli_i32(t0, t0, 4); | |
3969 | tcg_gen_or_i32(t0, t0, cpu_crf[3]); | |
3970 | tcg_gen_shli_i32(t0, t0, 4); | |
3971 | tcg_gen_or_i32(t0, t0, cpu_crf[4]); | |
3972 | tcg_gen_shli_i32(t0, t0, 4); | |
3973 | tcg_gen_or_i32(t0, t0, cpu_crf[5]); | |
3974 | tcg_gen_shli_i32(t0, t0, 4); | |
3975 | tcg_gen_or_i32(t0, t0, cpu_crf[6]); | |
3976 | tcg_gen_shli_i32(t0, t0, 4); | |
3977 | tcg_gen_or_i32(t0, t0, cpu_crf[7]); | |
3978 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
3979 | tcg_temp_free_i32(t0); | |
d9bce9d9 | 3980 | } |
79aceca5 FB |
3981 | } |
3982 | ||
3983 | /* mfmsr */ | |
99e300ef | 3984 | static void gen_mfmsr(DisasContext *ctx) |
79aceca5 | 3985 | { |
9b2fadda | 3986 | CHK_SV; |
6527f6ea | 3987 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); |
79aceca5 FB |
3988 | } |
3989 | ||
69b058c8 | 3990 | static void spr_noaccess(DisasContext *ctx, int gprn, int sprn) |
3fc6c082 | 3991 | { |
7b13448f | 3992 | #if 0 |
3fc6c082 FB |
3993 | sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); |
3994 | printf("ERROR: try to access SPR %d !\n", sprn); | |
7b13448f | 3995 | #endif |
3fc6c082 FB |
3996 | } |
3997 | #define SPR_NOACCESS (&spr_noaccess) | |
3fc6c082 | 3998 | |
79aceca5 | 3999 | /* mfspr */ |
636aa200 | 4000 | static inline void gen_op_mfspr(DisasContext *ctx) |
79aceca5 | 4001 | { |
69b058c8 | 4002 | void (*read_cb)(DisasContext *ctx, int gprn, int sprn); |
79aceca5 FB |
4003 | uint32_t sprn = SPR(ctx->opcode); |
4004 | ||
eb94268e BH |
4005 | #if defined(CONFIG_USER_ONLY) |
4006 | read_cb = ctx->spr_cb[sprn].uea_read; | |
4007 | #else | |
4008 | if (ctx->pr) { | |
4009 | read_cb = ctx->spr_cb[sprn].uea_read; | |
4010 | } else if (ctx->hv) { | |
be147d08 | 4011 | read_cb = ctx->spr_cb[sprn].hea_read; |
eb94268e | 4012 | } else { |
3fc6c082 | 4013 | read_cb = ctx->spr_cb[sprn].oea_read; |
eb94268e | 4014 | } |
9a64fbe4 | 4015 | #endif |
76a66253 JM |
4016 | if (likely(read_cb != NULL)) { |
4017 | if (likely(read_cb != SPR_NOACCESS)) { | |
45d827d2 | 4018 | (*read_cb)(ctx, rD(ctx->opcode), sprn); |
3fc6c082 FB |
4019 | } else { |
4020 | /* Privilege exception */ | |
9fceefa7 JM |
4021 | /* This is a hack to avoid warnings when running Linux: |
4022 | * this OS breaks the PowerPC virtualisation model, | |
4023 | * allowing userland application to read the PVR | |
4024 | */ | |
4025 | if (sprn != SPR_PVR) { | |
31085338 TH |
4026 | qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " |
4027 | "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, | |
4028 | ctx->base.pc_next - 4); | |
f24e5695 | 4029 | } |
9b2fadda | 4030 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); |
79aceca5 | 4031 | } |
3fc6c082 | 4032 | } else { |
9b2fadda BH |
4033 | /* ISA 2.07 defines these as no-ops */ |
4034 | if ((ctx->insns_flags2 & PPC2_ISA207S) && | |
4035 | (sprn >= 808 && sprn <= 811)) { | |
4036 | /* This is a nop */ | |
4037 | return; | |
4038 | } | |
3fc6c082 | 4039 | /* Not defined */ |
31085338 TH |
4040 | qemu_log_mask(LOG_GUEST_ERROR, |
4041 | "Trying to read invalid spr %d (0x%03x) at " | |
4042 | TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4); | |
9b2fadda BH |
4043 | |
4044 | /* The behaviour depends on MSR:PR and SPR# bit 0x10, | |
4045 | * it can generate a priv, a hv emu or a no-op | |
4046 | */ | |
4047 | if (sprn & 0x10) { | |
4048 | if (ctx->pr) { | |
4049 | gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); | |
4050 | } | |
4051 | } else { | |
4052 | if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { | |
4053 | gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); | |
4054 | } | |
4d6a0680 | 4055 | } |
79aceca5 | 4056 | } |
79aceca5 FB |
4057 | } |
4058 | ||
99e300ef | 4059 | static void gen_mfspr(DisasContext *ctx) |
79aceca5 | 4060 | { |
3fc6c082 | 4061 | gen_op_mfspr(ctx); |
76a66253 | 4062 | } |
3fc6c082 FB |
4063 | |
4064 | /* mftb */ | |
99e300ef | 4065 | static void gen_mftb(DisasContext *ctx) |
3fc6c082 FB |
4066 | { |
4067 | gen_op_mfspr(ctx); | |
79aceca5 FB |
4068 | } |
4069 | ||
0cfe11ea | 4070 | /* mtcrf mtocrf*/ |
99e300ef | 4071 | static void gen_mtcrf(DisasContext *ctx) |
79aceca5 | 4072 | { |
76a66253 | 4073 | uint32_t crm, crn; |
3b46e624 | 4074 | |
76a66253 | 4075 | crm = CRM(ctx->opcode); |
8dd640e4 | 4076 | if (likely((ctx->opcode & 0x00100000))) { |
4077 | if (crm && ((crm & (crm - 1)) == 0)) { | |
4078 | TCGv_i32 temp = tcg_temp_new_i32(); | |
0cfe11ea | 4079 | crn = ctz32 (crm); |
8dd640e4 | 4080 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); |
0cfe11ea AJ |
4081 | tcg_gen_shri_i32(temp, temp, crn * 4); |
4082 | tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); | |
8dd640e4 | 4083 | tcg_temp_free_i32(temp); |
4084 | } | |
76a66253 | 4085 | } else { |
651721b2 AJ |
4086 | TCGv_i32 temp = tcg_temp_new_i32(); |
4087 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); | |
4088 | for (crn = 0 ; crn < 8 ; crn++) { | |
4089 | if (crm & (1 << crn)) { | |
4090 | tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); | |
4091 | tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); | |
4092 | } | |
4093 | } | |
a7812ae4 | 4094 | tcg_temp_free_i32(temp); |
76a66253 | 4095 | } |
79aceca5 FB |
4096 | } |
4097 | ||
4098 | /* mtmsr */ | |
426613db | 4099 | #if defined(TARGET_PPC64) |
99e300ef | 4100 | static void gen_mtmsrd(DisasContext *ctx) |
426613db | 4101 | { |
9b2fadda BH |
4102 | CHK_SV; |
4103 | ||
4104 | #if !defined(CONFIG_USER_ONLY) | |
be147d08 JM |
4105 | if (ctx->opcode & 0x00010000) { |
4106 | /* Special form that does not need any synchronisation */ | |
6527f6ea AJ |
4107 | TCGv t0 = tcg_temp_new(); |
4108 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); | |
c409bc5d | 4109 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); |
6527f6ea AJ |
4110 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); |
4111 | tcg_temp_free(t0); | |
be147d08 | 4112 | } else { |
056b05f8 JM |
4113 | /* XXX: we need to update nip before the store |
4114 | * if we enter power saving mode, we will exit the loop | |
4115 | * directly from ppc_store_msr | |
4116 | */ | |
b6bac4bc | 4117 | gen_update_nip(ctx, ctx->base.pc_next); |
e5f17ac6 | 4118 | gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); |
be147d08 JM |
4119 | /* Must stop the translation as machine state (may have) changed */ |
4120 | /* Note that mtmsr is not always defined as context-synchronizing */ | |
e06fcd75 | 4121 | gen_stop_exception(ctx); |
be147d08 | 4122 | } |
9b2fadda | 4123 | #endif /* !defined(CONFIG_USER_ONLY) */ |
426613db | 4124 | } |
9b2fadda | 4125 | #endif /* defined(TARGET_PPC64) */ |
426613db | 4126 | |
99e300ef | 4127 | static void gen_mtmsr(DisasContext *ctx) |
79aceca5 | 4128 | { |
9b2fadda BH |
4129 | CHK_SV; |
4130 | ||
4131 | #if !defined(CONFIG_USER_ONLY) | |
4132 | if (ctx->opcode & 0x00010000) { | |
be147d08 | 4133 | /* Special form that does not need any synchronisation */ |
6527f6ea AJ |
4134 | TCGv t0 = tcg_temp_new(); |
4135 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); | |
c409bc5d | 4136 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); |
6527f6ea AJ |
4137 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); |
4138 | tcg_temp_free(t0); | |
be147d08 | 4139 | } else { |
8018dc63 AG |
4140 | TCGv msr = tcg_temp_new(); |
4141 | ||
056b05f8 JM |
4142 | /* XXX: we need to update nip before the store |
4143 | * if we enter power saving mode, we will exit the loop | |
4144 | * directly from ppc_store_msr | |
4145 | */ | |
b6bac4bc | 4146 | gen_update_nip(ctx, ctx->base.pc_next); |
d9bce9d9 | 4147 | #if defined(TARGET_PPC64) |
8018dc63 AG |
4148 | tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); |
4149 | #else | |
4150 | tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); | |
d9bce9d9 | 4151 | #endif |
e5f17ac6 | 4152 | gen_helper_store_msr(cpu_env, msr); |
c80d1df5 | 4153 | tcg_temp_free(msr); |
be147d08 | 4154 | /* Must stop the translation as machine state (may have) changed */ |
6527f6ea | 4155 | /* Note that mtmsr is not always defined as context-synchronizing */ |
e06fcd75 | 4156 | gen_stop_exception(ctx); |
be147d08 | 4157 | } |
9a64fbe4 | 4158 | #endif |
79aceca5 FB |
4159 | } |
4160 | ||
4161 | /* mtspr */ | |
99e300ef | 4162 | static void gen_mtspr(DisasContext *ctx) |
79aceca5 | 4163 | { |
69b058c8 | 4164 | void (*write_cb)(DisasContext *ctx, int sprn, int gprn); |
79aceca5 FB |
4165 | uint32_t sprn = SPR(ctx->opcode); |
4166 | ||
eb94268e BH |
4167 | #if defined(CONFIG_USER_ONLY) |
4168 | write_cb = ctx->spr_cb[sprn].uea_write; | |
4169 | #else | |
4170 | if (ctx->pr) { | |
4171 | write_cb = ctx->spr_cb[sprn].uea_write; | |
4172 | } else if (ctx->hv) { | |
be147d08 | 4173 | write_cb = ctx->spr_cb[sprn].hea_write; |
eb94268e | 4174 | } else { |
3fc6c082 | 4175 | write_cb = ctx->spr_cb[sprn].oea_write; |
eb94268e | 4176 | } |
9a64fbe4 | 4177 | #endif |
76a66253 JM |
4178 | if (likely(write_cb != NULL)) { |
4179 | if (likely(write_cb != SPR_NOACCESS)) { | |
45d827d2 | 4180 | (*write_cb)(ctx, sprn, rS(ctx->opcode)); |
3fc6c082 FB |
4181 | } else { |
4182 | /* Privilege exception */ | |
31085338 TH |
4183 | qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " |
4184 | "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, | |
4185 | ctx->base.pc_next - 4); | |
9b2fadda | 4186 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 4187 | } |
3fc6c082 | 4188 | } else { |
9b2fadda BH |
4189 | /* ISA 2.07 defines these as no-ops */ |
4190 | if ((ctx->insns_flags2 & PPC2_ISA207S) && | |
4191 | (sprn >= 808 && sprn <= 811)) { | |
4192 | /* This is a nop */ | |
4193 | return; | |
4194 | } | |
4195 | ||
3fc6c082 | 4196 | /* Not defined */ |
31085338 TH |
4197 | qemu_log_mask(LOG_GUEST_ERROR, |
4198 | "Trying to write invalid spr %d (0x%03x) at " | |
4199 | TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4); | |
4d6a0680 | 4200 | |
9b2fadda BH |
4201 | |
4202 | /* The behaviour depends on MSR:PR and SPR# bit 0x10, | |
4203 | * it can generate a priv, a hv emu or a no-op | |
4204 | */ | |
4205 | if (sprn & 0x10) { | |
4206 | if (ctx->pr) { | |
4207 | gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); | |
4208 | } | |
4209 | } else { | |
4210 | if (ctx->pr || sprn == 0) { | |
4211 | gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); | |
4212 | } | |
4d6a0680 | 4213 | } |
79aceca5 | 4214 | } |
79aceca5 FB |
4215 | } |
4216 | ||
dc2ee038 VAS |
4217 | #if defined(TARGET_PPC64) |
4218 | /* setb */ | |
4219 | static void gen_setb(DisasContext *ctx) | |
4220 | { | |
4221 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
4222 | TCGv_i32 t8 = tcg_temp_new_i32(); | |
4223 | TCGv_i32 tm1 = tcg_temp_new_i32(); | |
4224 | int crf = crfS(ctx->opcode); | |
4225 | ||
4226 | tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); | |
4227 | tcg_gen_movi_i32(t8, 8); | |
4228 | tcg_gen_movi_i32(tm1, -1); | |
4229 | tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); | |
4230 | tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
4231 | ||
4232 | tcg_temp_free_i32(t0); | |
4233 | tcg_temp_free_i32(t8); | |
4234 | tcg_temp_free_i32(tm1); | |
4235 | } | |
4236 | #endif | |
4237 | ||
79aceca5 | 4238 | /*** Cache management ***/ |
99e300ef | 4239 | |
54623277 | 4240 | /* dcbf */ |
99e300ef | 4241 | static void gen_dcbf(DisasContext *ctx) |
79aceca5 | 4242 | { |
dac454af | 4243 | /* XXX: specification says this is treated as a load by the MMU */ |
76db3ba4 AJ |
4244 | TCGv t0; |
4245 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4246 | t0 = tcg_temp_new(); | |
4247 | gen_addr_reg_index(ctx, t0); | |
4248 | gen_qemu_ld8u(ctx, t0, t0); | |
fea0c503 | 4249 | tcg_temp_free(t0); |
79aceca5 FB |
4250 | } |
4251 | ||
4252 | /* dcbi (Supervisor only) */ | |
99e300ef | 4253 | static void gen_dcbi(DisasContext *ctx) |
79aceca5 | 4254 | { |
a541f297 | 4255 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4256 | GEN_PRIV; |
a541f297 | 4257 | #else |
b61f2753 | 4258 | TCGv EA, val; |
9b2fadda BH |
4259 | |
4260 | CHK_SV; | |
a7812ae4 | 4261 | EA = tcg_temp_new(); |
76db3ba4 AJ |
4262 | gen_set_access_type(ctx, ACCESS_CACHE); |
4263 | gen_addr_reg_index(ctx, EA); | |
a7812ae4 | 4264 | val = tcg_temp_new(); |
76a66253 | 4265 | /* XXX: specification says this should be treated as a store by the MMU */ |
76db3ba4 AJ |
4266 | gen_qemu_ld8u(ctx, val, EA); |
4267 | gen_qemu_st8(ctx, val, EA); | |
b61f2753 AJ |
4268 | tcg_temp_free(val); |
4269 | tcg_temp_free(EA); | |
9b2fadda | 4270 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4271 | } |
4272 | ||
4273 | /* dcdst */ | |
99e300ef | 4274 | static void gen_dcbst(DisasContext *ctx) |
79aceca5 | 4275 | { |
76a66253 | 4276 | /* XXX: specification say this is treated as a load by the MMU */ |
76db3ba4 AJ |
4277 | TCGv t0; |
4278 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4279 | t0 = tcg_temp_new(); | |
4280 | gen_addr_reg_index(ctx, t0); | |
4281 | gen_qemu_ld8u(ctx, t0, t0); | |
fea0c503 | 4282 | tcg_temp_free(t0); |
79aceca5 FB |
4283 | } |
4284 | ||
4285 | /* dcbt */ | |
99e300ef | 4286 | static void gen_dcbt(DisasContext *ctx) |
79aceca5 | 4287 | { |
0db1b20e | 4288 | /* interpreted as no-op */ |
76a66253 JM |
4289 | /* XXX: specification say this is treated as a load by the MMU |
4290 | * but does not generate any exception | |
4291 | */ | |
79aceca5 FB |
4292 | } |
4293 | ||
4294 | /* dcbtst */ | |
99e300ef | 4295 | static void gen_dcbtst(DisasContext *ctx) |
79aceca5 | 4296 | { |
0db1b20e | 4297 | /* interpreted as no-op */ |
76a66253 JM |
4298 | /* XXX: specification say this is treated as a load by the MMU |
4299 | * but does not generate any exception | |
4300 | */ | |
79aceca5 FB |
4301 | } |
4302 | ||
4d09d529 AG |
4303 | /* dcbtls */ |
4304 | static void gen_dcbtls(DisasContext *ctx) | |
4305 | { | |
4306 | /* Always fails locking the cache */ | |
4307 | TCGv t0 = tcg_temp_new(); | |
4308 | gen_load_spr(t0, SPR_Exxx_L1CSR0); | |
4309 | tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); | |
4310 | gen_store_spr(SPR_Exxx_L1CSR0, t0); | |
4311 | tcg_temp_free(t0); | |
4312 | } | |
4313 | ||
79aceca5 | 4314 | /* dcbz */ |
99e300ef | 4315 | static void gen_dcbz(DisasContext *ctx) |
79aceca5 | 4316 | { |
8e33944f | 4317 | TCGv tcgv_addr; |
c9f82d01 | 4318 | TCGv_i32 tcgv_op; |
d63001d1 | 4319 | |
76db3ba4 | 4320 | gen_set_access_type(ctx, ACCESS_CACHE); |
8e33944f | 4321 | tcgv_addr = tcg_temp_new(); |
c9f82d01 | 4322 | tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); |
8e33944f | 4323 | gen_addr_reg_index(ctx, tcgv_addr); |
c9f82d01 | 4324 | gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); |
8e33944f | 4325 | tcg_temp_free(tcgv_addr); |
c9f82d01 | 4326 | tcg_temp_free_i32(tcgv_op); |
79aceca5 FB |
4327 | } |
4328 | ||
ae1c1a3d | 4329 | /* dst / dstt */ |
99e300ef | 4330 | static void gen_dst(DisasContext *ctx) |
ae1c1a3d AJ |
4331 | { |
4332 | if (rA(ctx->opcode) == 0) { | |
e41029b3 | 4333 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
ae1c1a3d AJ |
4334 | } else { |
4335 | /* interpreted as no-op */ | |
4336 | } | |
4337 | } | |
4338 | ||
4339 | /* dstst /dststt */ | |
99e300ef | 4340 | static void gen_dstst(DisasContext *ctx) |
ae1c1a3d AJ |
4341 | { |
4342 | if (rA(ctx->opcode) == 0) { | |
e41029b3 | 4343 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
ae1c1a3d AJ |
4344 | } else { |
4345 | /* interpreted as no-op */ | |
4346 | } | |
4347 | ||
4348 | } | |
4349 | ||
4350 | /* dss / dssall */ | |
99e300ef | 4351 | static void gen_dss(DisasContext *ctx) |
ae1c1a3d AJ |
4352 | { |
4353 | /* interpreted as no-op */ | |
4354 | } | |
4355 | ||
79aceca5 | 4356 | /* icbi */ |
99e300ef | 4357 | static void gen_icbi(DisasContext *ctx) |
79aceca5 | 4358 | { |
76db3ba4 AJ |
4359 | TCGv t0; |
4360 | gen_set_access_type(ctx, ACCESS_CACHE); | |
76db3ba4 AJ |
4361 | t0 = tcg_temp_new(); |
4362 | gen_addr_reg_index(ctx, t0); | |
2f5a189c | 4363 | gen_helper_icbi(cpu_env, t0); |
37d269df | 4364 | tcg_temp_free(t0); |
79aceca5 FB |
4365 | } |
4366 | ||
4367 | /* Optional: */ | |
4368 | /* dcba */ | |
99e300ef | 4369 | static void gen_dcba(DisasContext *ctx) |
79aceca5 | 4370 | { |
0db1b20e JM |
4371 | /* interpreted as no-op */ |
4372 | /* XXX: specification say this is treated as a store by the MMU | |
4373 | * but does not generate any exception | |
4374 | */ | |
79aceca5 FB |
4375 | } |
4376 | ||
4377 | /*** Segment register manipulation ***/ | |
4378 | /* Supervisor only: */ | |
99e300ef | 4379 | |
54623277 | 4380 | /* mfsr */ |
99e300ef | 4381 | static void gen_mfsr(DisasContext *ctx) |
79aceca5 | 4382 | { |
9a64fbe4 | 4383 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4384 | GEN_PRIV; |
9a64fbe4 | 4385 | #else |
74d37793 | 4386 | TCGv t0; |
9b2fadda BH |
4387 | |
4388 | CHK_SV; | |
74d37793 | 4389 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4390 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4391 | tcg_temp_free(t0); |
9b2fadda | 4392 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4393 | } |
4394 | ||
4395 | /* mfsrin */ | |
99e300ef | 4396 | static void gen_mfsrin(DisasContext *ctx) |
79aceca5 | 4397 | { |
9a64fbe4 | 4398 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4399 | GEN_PRIV; |
9a64fbe4 | 4400 | #else |
74d37793 | 4401 | TCGv t0; |
9b2fadda BH |
4402 | |
4403 | CHK_SV; | |
74d37793 | 4404 | t0 = tcg_temp_new(); |
e2622073 | 4405 | tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); |
c6c7cf05 | 4406 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4407 | tcg_temp_free(t0); |
9b2fadda | 4408 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4409 | } |
4410 | ||
4411 | /* mtsr */ | |
99e300ef | 4412 | static void gen_mtsr(DisasContext *ctx) |
79aceca5 | 4413 | { |
9a64fbe4 | 4414 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4415 | GEN_PRIV; |
9a64fbe4 | 4416 | #else |
74d37793 | 4417 | TCGv t0; |
9b2fadda BH |
4418 | |
4419 | CHK_SV; | |
74d37793 | 4420 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4421 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4422 | tcg_temp_free(t0); |
9b2fadda | 4423 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4424 | } |
4425 | ||
4426 | /* mtsrin */ | |
99e300ef | 4427 | static void gen_mtsrin(DisasContext *ctx) |
79aceca5 | 4428 | { |
9a64fbe4 | 4429 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4430 | GEN_PRIV; |
9a64fbe4 | 4431 | #else |
74d37793 | 4432 | TCGv t0; |
9b2fadda BH |
4433 | CHK_SV; |
4434 | ||
74d37793 | 4435 | t0 = tcg_temp_new(); |
e2622073 | 4436 | tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); |
c6c7cf05 | 4437 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); |
74d37793 | 4438 | tcg_temp_free(t0); |
9b2fadda | 4439 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4440 | } |
4441 | ||
12de9a39 JM |
4442 | #if defined(TARGET_PPC64) |
4443 | /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ | |
e8eaa2c0 | 4444 | |
54623277 | 4445 | /* mfsr */ |
e8eaa2c0 | 4446 | static void gen_mfsr_64b(DisasContext *ctx) |
12de9a39 JM |
4447 | { |
4448 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4449 | GEN_PRIV; |
12de9a39 | 4450 | #else |
74d37793 | 4451 | TCGv t0; |
9b2fadda BH |
4452 | |
4453 | CHK_SV; | |
74d37793 | 4454 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4455 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4456 | tcg_temp_free(t0); |
9b2fadda | 4457 | #endif /* defined(CONFIG_USER_ONLY) */ |
12de9a39 JM |
4458 | } |
4459 | ||
4460 | /* mfsrin */ | |
e8eaa2c0 | 4461 | static void gen_mfsrin_64b(DisasContext *ctx) |
12de9a39 JM |
4462 | { |
4463 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4464 | GEN_PRIV; |
12de9a39 | 4465 | #else |
74d37793 | 4466 | TCGv t0; |
9b2fadda BH |
4467 | |
4468 | CHK_SV; | |
74d37793 | 4469 | t0 = tcg_temp_new(); |
e2622073 | 4470 | tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); |
c6c7cf05 | 4471 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4472 | tcg_temp_free(t0); |
9b2fadda | 4473 | #endif /* defined(CONFIG_USER_ONLY) */ |
12de9a39 JM |
4474 | } |
4475 | ||
4476 | /* mtsr */ | |
e8eaa2c0 | 4477 | static void gen_mtsr_64b(DisasContext *ctx) |
12de9a39 JM |
4478 | { |
4479 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4480 | GEN_PRIV; |
12de9a39 | 4481 | #else |
74d37793 | 4482 | TCGv t0; |
9b2fadda BH |
4483 | |
4484 | CHK_SV; | |
74d37793 | 4485 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4486 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4487 | tcg_temp_free(t0); |
9b2fadda | 4488 | #endif /* defined(CONFIG_USER_ONLY) */ |
12de9a39 JM |
4489 | } |
4490 | ||
4491 | /* mtsrin */ | |
e8eaa2c0 | 4492 | static void gen_mtsrin_64b(DisasContext *ctx) |
12de9a39 JM |
4493 | { |
4494 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4495 | GEN_PRIV; |
12de9a39 | 4496 | #else |
74d37793 | 4497 | TCGv t0; |
9b2fadda BH |
4498 | |
4499 | CHK_SV; | |
74d37793 | 4500 | t0 = tcg_temp_new(); |
e2622073 | 4501 | tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); |
c6c7cf05 | 4502 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4503 | tcg_temp_free(t0); |
9b2fadda | 4504 | #endif /* defined(CONFIG_USER_ONLY) */ |
12de9a39 | 4505 | } |
f6b868fc BS |
4506 | |
4507 | /* slbmte */ | |
e8eaa2c0 | 4508 | static void gen_slbmte(DisasContext *ctx) |
f6b868fc BS |
4509 | { |
4510 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4511 | GEN_PRIV; |
f6b868fc | 4512 | #else |
9b2fadda BH |
4513 | CHK_SV; |
4514 | ||
c6c7cf05 BS |
4515 | gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], |
4516 | cpu_gpr[rS(ctx->opcode)]); | |
9b2fadda | 4517 | #endif /* defined(CONFIG_USER_ONLY) */ |
f6b868fc BS |
4518 | } |
4519 | ||
efdef95f DG |
4520 | static void gen_slbmfee(DisasContext *ctx) |
4521 | { | |
4522 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4523 | GEN_PRIV; |
efdef95f | 4524 | #else |
9b2fadda BH |
4525 | CHK_SV; |
4526 | ||
c6c7cf05 | 4527 | gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, |
efdef95f | 4528 | cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 4529 | #endif /* defined(CONFIG_USER_ONLY) */ |
efdef95f DG |
4530 | } |
4531 | ||
4532 | static void gen_slbmfev(DisasContext *ctx) | |
4533 | { | |
4534 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4535 | GEN_PRIV; |
efdef95f | 4536 | #else |
9b2fadda BH |
4537 | CHK_SV; |
4538 | ||
c6c7cf05 | 4539 | gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, |
efdef95f | 4540 | cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 4541 | #endif /* defined(CONFIG_USER_ONLY) */ |
efdef95f | 4542 | } |
c76c22d5 BH |
4543 | |
4544 | static void gen_slbfee_(DisasContext *ctx) | |
4545 | { | |
4546 | #if defined(CONFIG_USER_ONLY) | |
4547 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4548 | #else | |
4549 | TCGLabel *l1, *l2; | |
4550 | ||
4551 | if (unlikely(ctx->pr)) { | |
4552 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4553 | return; | |
4554 | } | |
4555 | gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, | |
4556 | cpu_gpr[rB(ctx->opcode)]); | |
4557 | l1 = gen_new_label(); | |
4558 | l2 = gen_new_label(); | |
4559 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); | |
4560 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); | |
efa73196 | 4561 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); |
c76c22d5 BH |
4562 | tcg_gen_br(l2); |
4563 | gen_set_label(l1); | |
4564 | tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); | |
4565 | gen_set_label(l2); | |
4566 | #endif | |
4567 | } | |
12de9a39 JM |
4568 | #endif /* defined(TARGET_PPC64) */ |
4569 | ||
79aceca5 | 4570 | /*** Lookaside buffer management ***/ |
c47493f2 | 4571 | /* Optional & supervisor only: */ |
99e300ef | 4572 | |
54623277 | 4573 | /* tlbia */ |
99e300ef | 4574 | static void gen_tlbia(DisasContext *ctx) |
79aceca5 | 4575 | { |
9a64fbe4 | 4576 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4577 | GEN_PRIV; |
9a64fbe4 | 4578 | #else |
9b2fadda BH |
4579 | CHK_HV; |
4580 | ||
c6c7cf05 | 4581 | gen_helper_tlbia(cpu_env); |
9b2fadda | 4582 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4583 | } |
4584 | ||
bf14b1ce | 4585 | /* tlbiel */ |
99e300ef | 4586 | static void gen_tlbiel(DisasContext *ctx) |
bf14b1ce BS |
4587 | { |
4588 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4589 | GEN_PRIV; |
bf14b1ce | 4590 | #else |
9b2fadda BH |
4591 | CHK_SV; |
4592 | ||
c6c7cf05 | 4593 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 4594 | #endif /* defined(CONFIG_USER_ONLY) */ |
bf14b1ce BS |
4595 | } |
4596 | ||
79aceca5 | 4597 | /* tlbie */ |
99e300ef | 4598 | static void gen_tlbie(DisasContext *ctx) |
79aceca5 | 4599 | { |
9a64fbe4 | 4600 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4601 | GEN_PRIV; |
9a64fbe4 | 4602 | #else |
d76ab5e1 | 4603 | TCGv_i32 t1; |
c6fd28fd SJS |
4604 | |
4605 | if (ctx->gtse) { | |
91c60f12 | 4606 | CHK_SV; /* If gtse is set then tlbie is supervisor privileged */ |
c6fd28fd SJS |
4607 | } else { |
4608 | CHK_HV; /* Else hypervisor privileged */ | |
4609 | } | |
9b2fadda | 4610 | |
9ca3f7f3 | 4611 | if (NARROW_MODE(ctx)) { |
74d37793 AJ |
4612 | TCGv t0 = tcg_temp_new(); |
4613 | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); | |
c6c7cf05 | 4614 | gen_helper_tlbie(cpu_env, t0); |
74d37793 | 4615 | tcg_temp_free(t0); |
9ca3f7f3 | 4616 | } else { |
c6c7cf05 | 4617 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9ca3f7f3 | 4618 | } |
d76ab5e1 ND |
4619 | t1 = tcg_temp_new_i32(); |
4620 | tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); | |
4621 | tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); | |
4622 | tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); | |
4623 | tcg_temp_free_i32(t1); | |
9b2fadda | 4624 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4625 | } |
4626 | ||
4627 | /* tlbsync */ | |
99e300ef | 4628 | static void gen_tlbsync(DisasContext *ctx) |
79aceca5 | 4629 | { |
9a64fbe4 | 4630 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4631 | GEN_PRIV; |
9a64fbe4 | 4632 | #else |
91c60f12 CLG |
4633 | |
4634 | if (ctx->gtse) { | |
4635 | CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */ | |
4636 | } else { | |
4637 | CHK_HV; /* Else hypervisor privileged */ | |
4638 | } | |
9b2fadda | 4639 | |
e3cffe6f ND |
4640 | /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ |
4641 | if (ctx->insns_flags & PPC_BOOKE) { | |
4642 | gen_check_tlb_flush(ctx, true); | |
4643 | } | |
9b2fadda | 4644 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4645 | } |
4646 | ||
426613db JM |
4647 | #if defined(TARGET_PPC64) |
4648 | /* slbia */ | |
99e300ef | 4649 | static void gen_slbia(DisasContext *ctx) |
426613db JM |
4650 | { |
4651 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4652 | GEN_PRIV; |
426613db | 4653 | #else |
9b2fadda BH |
4654 | CHK_SV; |
4655 | ||
c6c7cf05 | 4656 | gen_helper_slbia(cpu_env); |
9b2fadda | 4657 | #endif /* defined(CONFIG_USER_ONLY) */ |
426613db JM |
4658 | } |
4659 | ||
4660 | /* slbie */ | |
99e300ef | 4661 | static void gen_slbie(DisasContext *ctx) |
426613db JM |
4662 | { |
4663 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4664 | GEN_PRIV; |
426613db | 4665 | #else |
9b2fadda BH |
4666 | CHK_SV; |
4667 | ||
c6c7cf05 | 4668 | gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 4669 | #endif /* defined(CONFIG_USER_ONLY) */ |
426613db | 4670 | } |
a63f1dfc ND |
4671 | |
4672 | /* slbieg */ | |
4673 | static void gen_slbieg(DisasContext *ctx) | |
4674 | { | |
4675 | #if defined(CONFIG_USER_ONLY) | |
4676 | GEN_PRIV; | |
4677 | #else | |
4678 | CHK_SV; | |
4679 | ||
4680 | gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]); | |
4681 | #endif /* defined(CONFIG_USER_ONLY) */ | |
4682 | } | |
4683 | ||
62d897ca ND |
4684 | /* slbsync */ |
4685 | static void gen_slbsync(DisasContext *ctx) | |
4686 | { | |
4687 | #if defined(CONFIG_USER_ONLY) | |
4688 | GEN_PRIV; | |
4689 | #else | |
4690 | CHK_SV; | |
4691 | gen_check_tlb_flush(ctx, true); | |
4692 | #endif /* defined(CONFIG_USER_ONLY) */ | |
4693 | } | |
4694 | ||
9b2fadda | 4695 | #endif /* defined(TARGET_PPC64) */ |
426613db | 4696 | |
79aceca5 FB |
4697 | /*** External control ***/ |
4698 | /* Optional: */ | |
99e300ef | 4699 | |
54623277 | 4700 | /* eciwx */ |
99e300ef | 4701 | static void gen_eciwx(DisasContext *ctx) |
79aceca5 | 4702 | { |
76db3ba4 | 4703 | TCGv t0; |
fa407c03 | 4704 | /* Should check EAR[E] ! */ |
76db3ba4 AJ |
4705 | gen_set_access_type(ctx, ACCESS_EXT); |
4706 | t0 = tcg_temp_new(); | |
4707 | gen_addr_reg_index(ctx, t0); | |
c674a983 RH |
4708 | tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, |
4709 | DEF_MEMOP(MO_UL | MO_ALIGN)); | |
fa407c03 | 4710 | tcg_temp_free(t0); |
76a66253 JM |
4711 | } |
4712 | ||
4713 | /* ecowx */ | |
99e300ef | 4714 | static void gen_ecowx(DisasContext *ctx) |
76a66253 | 4715 | { |
76db3ba4 | 4716 | TCGv t0; |
fa407c03 | 4717 | /* Should check EAR[E] ! */ |
76db3ba4 AJ |
4718 | gen_set_access_type(ctx, ACCESS_EXT); |
4719 | t0 = tcg_temp_new(); | |
4720 | gen_addr_reg_index(ctx, t0); | |
c674a983 RH |
4721 | tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, |
4722 | DEF_MEMOP(MO_UL | MO_ALIGN)); | |
fa407c03 | 4723 | tcg_temp_free(t0); |
76a66253 JM |
4724 | } |
4725 | ||
4726 | /* PowerPC 601 specific instructions */ | |
99e300ef | 4727 | |
54623277 | 4728 | /* abs - abs. */ |
99e300ef | 4729 | static void gen_abs(DisasContext *ctx) |
76a66253 | 4730 | { |
42a268c2 RH |
4731 | TCGLabel *l1 = gen_new_label(); |
4732 | TCGLabel *l2 = gen_new_label(); | |
22e0e173 AJ |
4733 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1); |
4734 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4735 | tcg_gen_br(l2); | |
4736 | gen_set_label(l1); | |
4737 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4738 | gen_set_label(l2); | |
76a66253 | 4739 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4740 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4741 | } |
4742 | ||
4743 | /* abso - abso. */ | |
99e300ef | 4744 | static void gen_abso(DisasContext *ctx) |
76a66253 | 4745 | { |
42a268c2 RH |
4746 | TCGLabel *l1 = gen_new_label(); |
4747 | TCGLabel *l2 = gen_new_label(); | |
4748 | TCGLabel *l3 = gen_new_label(); | |
22e0e173 | 4749 | /* Start with XER OV disabled, the most likely case */ |
da91a00f | 4750 | tcg_gen_movi_tl(cpu_ov, 0); |
22e0e173 AJ |
4751 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2); |
4752 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1); | |
da91a00f RH |
4753 | tcg_gen_movi_tl(cpu_ov, 1); |
4754 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
4755 | tcg_gen_br(l2); |
4756 | gen_set_label(l1); | |
4757 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4758 | tcg_gen_br(l3); | |
4759 | gen_set_label(l2); | |
4760 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4761 | gen_set_label(l3); | |
76a66253 | 4762 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4763 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4764 | } |
4765 | ||
4766 | /* clcs */ | |
99e300ef | 4767 | static void gen_clcs(DisasContext *ctx) |
76a66253 | 4768 | { |
22e0e173 | 4769 | TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); |
d523dd00 | 4770 | gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
22e0e173 | 4771 | tcg_temp_free_i32(t0); |
c7697e1f | 4772 | /* Rc=1 sets CR0 to an undefined state */ |
76a66253 JM |
4773 | } |
4774 | ||
4775 | /* div - div. */ | |
99e300ef | 4776 | static void gen_div(DisasContext *ctx) |
76a66253 | 4777 | { |
d15f74fb BS |
4778 | gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
4779 | cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4780 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4781 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4782 | } |
4783 | ||
4784 | /* divo - divo. */ | |
99e300ef | 4785 | static void gen_divo(DisasContext *ctx) |
76a66253 | 4786 | { |
d15f74fb BS |
4787 | gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
4788 | cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4789 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4790 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4791 | } |
4792 | ||
4793 | /* divs - divs. */ | |
99e300ef | 4794 | static void gen_divs(DisasContext *ctx) |
76a66253 | 4795 | { |
d15f74fb BS |
4796 | gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
4797 | cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4798 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4799 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4800 | } |
4801 | ||
4802 | /* divso - divso. */ | |
99e300ef | 4803 | static void gen_divso(DisasContext *ctx) |
76a66253 | 4804 | { |
d15f74fb BS |
4805 | gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, |
4806 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4807 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4808 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4809 | } |
4810 | ||
4811 | /* doz - doz. */ | |
99e300ef | 4812 | static void gen_doz(DisasContext *ctx) |
76a66253 | 4813 | { |
42a268c2 RH |
4814 | TCGLabel *l1 = gen_new_label(); |
4815 | TCGLabel *l2 = gen_new_label(); | |
22e0e173 AJ |
4816 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); |
4817 | tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4818 | tcg_gen_br(l2); | |
4819 | gen_set_label(l1); | |
4820 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4821 | gen_set_label(l2); | |
76a66253 | 4822 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4823 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4824 | } |
4825 | ||
4826 | /* dozo - dozo. */ | |
99e300ef | 4827 | static void gen_dozo(DisasContext *ctx) |
76a66253 | 4828 | { |
42a268c2 RH |
4829 | TCGLabel *l1 = gen_new_label(); |
4830 | TCGLabel *l2 = gen_new_label(); | |
22e0e173 AJ |
4831 | TCGv t0 = tcg_temp_new(); |
4832 | TCGv t1 = tcg_temp_new(); | |
4833 | TCGv t2 = tcg_temp_new(); | |
4834 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 4835 | tcg_gen_movi_tl(cpu_ov, 0); |
22e0e173 AJ |
4836 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); |
4837 | tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4838 | tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4839 | tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); | |
4840 | tcg_gen_andc_tl(t1, t1, t2); | |
4841 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
4842 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); | |
da91a00f RH |
4843 | tcg_gen_movi_tl(cpu_ov, 1); |
4844 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
4845 | tcg_gen_br(l2); |
4846 | gen_set_label(l1); | |
4847 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4848 | gen_set_label(l2); | |
4849 | tcg_temp_free(t0); | |
4850 | tcg_temp_free(t1); | |
4851 | tcg_temp_free(t2); | |
76a66253 | 4852 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4853 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4854 | } |
4855 | ||
4856 | /* dozi */ | |
99e300ef | 4857 | static void gen_dozi(DisasContext *ctx) |
76a66253 | 4858 | { |
22e0e173 | 4859 | target_long simm = SIMM(ctx->opcode); |
42a268c2 RH |
4860 | TCGLabel *l1 = gen_new_label(); |
4861 | TCGLabel *l2 = gen_new_label(); | |
22e0e173 AJ |
4862 | tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); |
4863 | tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); | |
4864 | tcg_gen_br(l2); | |
4865 | gen_set_label(l1); | |
4866 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4867 | gen_set_label(l2); | |
4868 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4869 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
76a66253 JM |
4870 | } |
4871 | ||
76a66253 | 4872 | /* lscbx - lscbx. */ |
99e300ef | 4873 | static void gen_lscbx(DisasContext *ctx) |
76a66253 | 4874 | { |
bdb4b689 AJ |
4875 | TCGv t0 = tcg_temp_new(); |
4876 | TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); | |
4877 | TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); | |
4878 | TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); | |
76a66253 | 4879 | |
76db3ba4 | 4880 | gen_addr_reg_index(ctx, t0); |
2f5a189c | 4881 | gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); |
bdb4b689 AJ |
4882 | tcg_temp_free_i32(t1); |
4883 | tcg_temp_free_i32(t2); | |
4884 | tcg_temp_free_i32(t3); | |
3d7b417e | 4885 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); |
bdb4b689 | 4886 | tcg_gen_or_tl(cpu_xer, cpu_xer, t0); |
76a66253 | 4887 | if (unlikely(Rc(ctx->opcode) != 0)) |
bdb4b689 AJ |
4888 | gen_set_Rc0(ctx, t0); |
4889 | tcg_temp_free(t0); | |
76a66253 JM |
4890 | } |
4891 | ||
4892 | /* maskg - maskg. */ | |
99e300ef | 4893 | static void gen_maskg(DisasContext *ctx) |
76a66253 | 4894 | { |
42a268c2 | 4895 | TCGLabel *l1 = gen_new_label(); |
22e0e173 AJ |
4896 | TCGv t0 = tcg_temp_new(); |
4897 | TCGv t1 = tcg_temp_new(); | |
4898 | TCGv t2 = tcg_temp_new(); | |
4899 | TCGv t3 = tcg_temp_new(); | |
4900 | tcg_gen_movi_tl(t3, 0xFFFFFFFF); | |
4901 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4902 | tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); | |
4903 | tcg_gen_addi_tl(t2, t0, 1); | |
4904 | tcg_gen_shr_tl(t2, t3, t2); | |
4905 | tcg_gen_shr_tl(t3, t3, t1); | |
4906 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); | |
4907 | tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); | |
4908 | tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4909 | gen_set_label(l1); | |
4910 | tcg_temp_free(t0); | |
4911 | tcg_temp_free(t1); | |
4912 | tcg_temp_free(t2); | |
4913 | tcg_temp_free(t3); | |
76a66253 | 4914 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4915 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4916 | } |
4917 | ||
4918 | /* maskir - maskir. */ | |
99e300ef | 4919 | static void gen_maskir(DisasContext *ctx) |
76a66253 | 4920 | { |
22e0e173 AJ |
4921 | TCGv t0 = tcg_temp_new(); |
4922 | TCGv t1 = tcg_temp_new(); | |
4923 | tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
4924 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
4925 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4926 | tcg_temp_free(t0); | |
4927 | tcg_temp_free(t1); | |
76a66253 | 4928 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4929 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4930 | } |
4931 | ||
4932 | /* mul - mul. */ | |
99e300ef | 4933 | static void gen_mul(DisasContext *ctx) |
76a66253 | 4934 | { |
22e0e173 AJ |
4935 | TCGv_i64 t0 = tcg_temp_new_i64(); |
4936 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
4937 | TCGv t2 = tcg_temp_new(); | |
4938 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
4939 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
4940 | tcg_gen_mul_i64(t0, t0, t1); | |
4941 | tcg_gen_trunc_i64_tl(t2, t0); | |
4942 | gen_store_spr(SPR_MQ, t2); | |
4943 | tcg_gen_shri_i64(t1, t0, 32); | |
4944 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
4945 | tcg_temp_free_i64(t0); | |
4946 | tcg_temp_free_i64(t1); | |
4947 | tcg_temp_free(t2); | |
76a66253 | 4948 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4949 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4950 | } |
4951 | ||
4952 | /* mulo - mulo. */ | |
99e300ef | 4953 | static void gen_mulo(DisasContext *ctx) |
76a66253 | 4954 | { |
42a268c2 | 4955 | TCGLabel *l1 = gen_new_label(); |
22e0e173 AJ |
4956 | TCGv_i64 t0 = tcg_temp_new_i64(); |
4957 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
4958 | TCGv t2 = tcg_temp_new(); | |
4959 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 4960 | tcg_gen_movi_tl(cpu_ov, 0); |
22e0e173 AJ |
4961 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
4962 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
4963 | tcg_gen_mul_i64(t0, t0, t1); | |
4964 | tcg_gen_trunc_i64_tl(t2, t0); | |
4965 | gen_store_spr(SPR_MQ, t2); | |
4966 | tcg_gen_shri_i64(t1, t0, 32); | |
4967 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
4968 | tcg_gen_ext32s_i64(t1, t0); | |
4969 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); | |
da91a00f RH |
4970 | tcg_gen_movi_tl(cpu_ov, 1); |
4971 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
4972 | gen_set_label(l1); |
4973 | tcg_temp_free_i64(t0); | |
4974 | tcg_temp_free_i64(t1); | |
4975 | tcg_temp_free(t2); | |
76a66253 | 4976 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4977 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4978 | } |
4979 | ||
4980 | /* nabs - nabs. */ | |
99e300ef | 4981 | static void gen_nabs(DisasContext *ctx) |
76a66253 | 4982 | { |
42a268c2 RH |
4983 | TCGLabel *l1 = gen_new_label(); |
4984 | TCGLabel *l2 = gen_new_label(); | |
22e0e173 AJ |
4985 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); |
4986 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4987 | tcg_gen_br(l2); | |
4988 | gen_set_label(l1); | |
4989 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4990 | gen_set_label(l2); | |
76a66253 | 4991 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4992 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4993 | } |
4994 | ||
4995 | /* nabso - nabso. */ | |
99e300ef | 4996 | static void gen_nabso(DisasContext *ctx) |
76a66253 | 4997 | { |
42a268c2 RH |
4998 | TCGLabel *l1 = gen_new_label(); |
4999 | TCGLabel *l2 = gen_new_label(); | |
22e0e173 AJ |
5000 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); |
5001 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
5002 | tcg_gen_br(l2); | |
5003 | gen_set_label(l1); | |
5004 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
5005 | gen_set_label(l2); | |
5006 | /* nabs never overflows */ | |
da91a00f | 5007 | tcg_gen_movi_tl(cpu_ov, 0); |
76a66253 | 5008 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 5009 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
5010 | } |
5011 | ||
5012 | /* rlmi - rlmi. */ | |
99e300ef | 5013 | static void gen_rlmi(DisasContext *ctx) |
76a66253 | 5014 | { |
7487953d AJ |
5015 | uint32_t mb = MB(ctx->opcode); |
5016 | uint32_t me = ME(ctx->opcode); | |
5017 | TCGv t0 = tcg_temp_new(); | |
5018 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5019 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
5020 | tcg_gen_andi_tl(t0, t0, MASK(mb, me)); | |
5021 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me)); | |
5022 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); | |
5023 | tcg_temp_free(t0); | |
76a66253 | 5024 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5025 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5026 | } |
5027 | ||
5028 | /* rrib - rrib. */ | |
99e300ef | 5029 | static void gen_rrib(DisasContext *ctx) |
76a66253 | 5030 | { |
7487953d AJ |
5031 | TCGv t0 = tcg_temp_new(); |
5032 | TCGv t1 = tcg_temp_new(); | |
5033 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5034 | tcg_gen_movi_tl(t1, 0x80000000); | |
5035 | tcg_gen_shr_tl(t1, t1, t0); | |
5036 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
5037 | tcg_gen_and_tl(t0, t0, t1); | |
5038 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); | |
5039 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5040 | tcg_temp_free(t0); | |
5041 | tcg_temp_free(t1); | |
76a66253 | 5042 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5043 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5044 | } |
5045 | ||
5046 | /* sle - sle. */ | |
99e300ef | 5047 | static void gen_sle(DisasContext *ctx) |
76a66253 | 5048 | { |
7487953d AJ |
5049 | TCGv t0 = tcg_temp_new(); |
5050 | TCGv t1 = tcg_temp_new(); | |
5051 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5052 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5053 | tcg_gen_subfi_tl(t1, 32, t1); | |
5054 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5055 | tcg_gen_or_tl(t1, t0, t1); | |
5056 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5057 | gen_store_spr(SPR_MQ, t1); | |
5058 | tcg_temp_free(t0); | |
5059 | tcg_temp_free(t1); | |
76a66253 | 5060 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5061 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5062 | } |
5063 | ||
5064 | /* sleq - sleq. */ | |
99e300ef | 5065 | static void gen_sleq(DisasContext *ctx) |
76a66253 | 5066 | { |
7487953d AJ |
5067 | TCGv t0 = tcg_temp_new(); |
5068 | TCGv t1 = tcg_temp_new(); | |
5069 | TCGv t2 = tcg_temp_new(); | |
5070 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5071 | tcg_gen_movi_tl(t2, 0xFFFFFFFF); | |
5072 | tcg_gen_shl_tl(t2, t2, t0); | |
5073 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
5074 | gen_load_spr(t1, SPR_MQ); | |
5075 | gen_store_spr(SPR_MQ, t0); | |
5076 | tcg_gen_and_tl(t0, t0, t2); | |
5077 | tcg_gen_andc_tl(t1, t1, t2); | |
5078 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5079 | tcg_temp_free(t0); | |
5080 | tcg_temp_free(t1); | |
5081 | tcg_temp_free(t2); | |
76a66253 | 5082 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5083 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5084 | } |
5085 | ||
5086 | /* sliq - sliq. */ | |
99e300ef | 5087 | static void gen_sliq(DisasContext *ctx) |
76a66253 | 5088 | { |
7487953d AJ |
5089 | int sh = SH(ctx->opcode); |
5090 | TCGv t0 = tcg_temp_new(); | |
5091 | TCGv t1 = tcg_temp_new(); | |
5092 | tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5093 | tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
5094 | tcg_gen_or_tl(t1, t0, t1); | |
5095 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5096 | gen_store_spr(SPR_MQ, t1); | |
5097 | tcg_temp_free(t0); | |
5098 | tcg_temp_free(t1); | |
76a66253 | 5099 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5100 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5101 | } |
5102 | ||
5103 | /* slliq - slliq. */ | |
99e300ef | 5104 | static void gen_slliq(DisasContext *ctx) |
76a66253 | 5105 | { |
7487953d AJ |
5106 | int sh = SH(ctx->opcode); |
5107 | TCGv t0 = tcg_temp_new(); | |
5108 | TCGv t1 = tcg_temp_new(); | |
5109 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5110 | gen_load_spr(t1, SPR_MQ); | |
5111 | gen_store_spr(SPR_MQ, t0); | |
5112 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); | |
5113 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); | |
5114 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5115 | tcg_temp_free(t0); | |
5116 | tcg_temp_free(t1); | |
76a66253 | 5117 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5118 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5119 | } |
5120 | ||
5121 | /* sllq - sllq. */ | |
99e300ef | 5122 | static void gen_sllq(DisasContext *ctx) |
76a66253 | 5123 | { |
42a268c2 RH |
5124 | TCGLabel *l1 = gen_new_label(); |
5125 | TCGLabel *l2 = gen_new_label(); | |
7487953d AJ |
5126 | TCGv t0 = tcg_temp_local_new(); |
5127 | TCGv t1 = tcg_temp_local_new(); | |
5128 | TCGv t2 = tcg_temp_local_new(); | |
5129 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5130 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5131 | tcg_gen_shl_tl(t1, t1, t2); | |
5132 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5133 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5134 | gen_load_spr(t0, SPR_MQ); | |
5135 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5136 | tcg_gen_br(l2); | |
5137 | gen_set_label(l1); | |
5138 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
5139 | gen_load_spr(t2, SPR_MQ); | |
5140 | tcg_gen_andc_tl(t1, t2, t1); | |
5141 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5142 | gen_set_label(l2); | |
5143 | tcg_temp_free(t0); | |
5144 | tcg_temp_free(t1); | |
5145 | tcg_temp_free(t2); | |
76a66253 | 5146 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5147 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5148 | } |
5149 | ||
5150 | /* slq - slq. */ | |
99e300ef | 5151 | static void gen_slq(DisasContext *ctx) |
76a66253 | 5152 | { |
42a268c2 | 5153 | TCGLabel *l1 = gen_new_label(); |
7487953d AJ |
5154 | TCGv t0 = tcg_temp_new(); |
5155 | TCGv t1 = tcg_temp_new(); | |
5156 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5157 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5158 | tcg_gen_subfi_tl(t1, 32, t1); | |
5159 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5160 | tcg_gen_or_tl(t1, t0, t1); | |
5161 | gen_store_spr(SPR_MQ, t1); | |
5162 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5163 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5164 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); | |
5165 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
5166 | gen_set_label(l1); | |
5167 | tcg_temp_free(t0); | |
5168 | tcg_temp_free(t1); | |
76a66253 | 5169 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5170 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5171 | } |
5172 | ||
d9bce9d9 | 5173 | /* sraiq - sraiq. */ |
99e300ef | 5174 | static void gen_sraiq(DisasContext *ctx) |
76a66253 | 5175 | { |
7487953d | 5176 | int sh = SH(ctx->opcode); |
42a268c2 | 5177 | TCGLabel *l1 = gen_new_label(); |
7487953d AJ |
5178 | TCGv t0 = tcg_temp_new(); |
5179 | TCGv t1 = tcg_temp_new(); | |
5180 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5181 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
5182 | tcg_gen_or_tl(t0, t0, t1); | |
5183 | gen_store_spr(SPR_MQ, t0); | |
da91a00f | 5184 | tcg_gen_movi_tl(cpu_ca, 0); |
7487953d AJ |
5185 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); |
5186 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); | |
da91a00f | 5187 | tcg_gen_movi_tl(cpu_ca, 1); |
7487953d AJ |
5188 | gen_set_label(l1); |
5189 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); | |
5190 | tcg_temp_free(t0); | |
5191 | tcg_temp_free(t1); | |
76a66253 | 5192 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5193 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5194 | } |
5195 | ||
5196 | /* sraq - sraq. */ | |
99e300ef | 5197 | static void gen_sraq(DisasContext *ctx) |
76a66253 | 5198 | { |
42a268c2 RH |
5199 | TCGLabel *l1 = gen_new_label(); |
5200 | TCGLabel *l2 = gen_new_label(); | |
7487953d AJ |
5201 | TCGv t0 = tcg_temp_new(); |
5202 | TCGv t1 = tcg_temp_local_new(); | |
5203 | TCGv t2 = tcg_temp_local_new(); | |
5204 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5205 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
5206 | tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); | |
5207 | tcg_gen_subfi_tl(t2, 32, t2); | |
5208 | tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); | |
5209 | tcg_gen_or_tl(t0, t0, t2); | |
5210 | gen_store_spr(SPR_MQ, t0); | |
5211 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5212 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); | |
5213 | tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); | |
5214 | tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); | |
5215 | gen_set_label(l1); | |
5216 | tcg_temp_free(t0); | |
5217 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); | |
da91a00f | 5218 | tcg_gen_movi_tl(cpu_ca, 0); |
7487953d AJ |
5219 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); |
5220 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); | |
da91a00f | 5221 | tcg_gen_movi_tl(cpu_ca, 1); |
7487953d AJ |
5222 | gen_set_label(l2); |
5223 | tcg_temp_free(t1); | |
5224 | tcg_temp_free(t2); | |
76a66253 | 5225 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5226 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5227 | } |
5228 | ||
5229 | /* sre - sre. */ | |
99e300ef | 5230 | static void gen_sre(DisasContext *ctx) |
76a66253 | 5231 | { |
7487953d AJ |
5232 | TCGv t0 = tcg_temp_new(); |
5233 | TCGv t1 = tcg_temp_new(); | |
5234 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5235 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5236 | tcg_gen_subfi_tl(t1, 32, t1); | |
5237 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5238 | tcg_gen_or_tl(t1, t0, t1); | |
5239 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5240 | gen_store_spr(SPR_MQ, t1); | |
5241 | tcg_temp_free(t0); | |
5242 | tcg_temp_free(t1); | |
76a66253 | 5243 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5244 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5245 | } |
5246 | ||
5247 | /* srea - srea. */ | |
99e300ef | 5248 | static void gen_srea(DisasContext *ctx) |
76a66253 | 5249 | { |
7487953d AJ |
5250 | TCGv t0 = tcg_temp_new(); |
5251 | TCGv t1 = tcg_temp_new(); | |
5252 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5253 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5254 | gen_store_spr(SPR_MQ, t0); | |
5255 | tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); | |
5256 | tcg_temp_free(t0); | |
5257 | tcg_temp_free(t1); | |
76a66253 | 5258 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5259 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5260 | } |
5261 | ||
5262 | /* sreq */ | |
99e300ef | 5263 | static void gen_sreq(DisasContext *ctx) |
76a66253 | 5264 | { |
7487953d AJ |
5265 | TCGv t0 = tcg_temp_new(); |
5266 | TCGv t1 = tcg_temp_new(); | |
5267 | TCGv t2 = tcg_temp_new(); | |
5268 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5269 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5270 | tcg_gen_shr_tl(t1, t1, t0); | |
5271 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
5272 | gen_load_spr(t2, SPR_MQ); | |
5273 | gen_store_spr(SPR_MQ, t0); | |
5274 | tcg_gen_and_tl(t0, t0, t1); | |
5275 | tcg_gen_andc_tl(t2, t2, t1); | |
5276 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); | |
5277 | tcg_temp_free(t0); | |
5278 | tcg_temp_free(t1); | |
5279 | tcg_temp_free(t2); | |
76a66253 | 5280 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5281 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5282 | } |
5283 | ||
5284 | /* sriq */ | |
99e300ef | 5285 | static void gen_sriq(DisasContext *ctx) |
76a66253 | 5286 | { |
7487953d AJ |
5287 | int sh = SH(ctx->opcode); |
5288 | TCGv t0 = tcg_temp_new(); | |
5289 | TCGv t1 = tcg_temp_new(); | |
5290 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5291 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
5292 | tcg_gen_or_tl(t1, t0, t1); | |
5293 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5294 | gen_store_spr(SPR_MQ, t1); | |
5295 | tcg_temp_free(t0); | |
5296 | tcg_temp_free(t1); | |
76a66253 | 5297 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5298 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5299 | } |
5300 | ||
5301 | /* srliq */ | |
99e300ef | 5302 | static void gen_srliq(DisasContext *ctx) |
76a66253 | 5303 | { |
7487953d AJ |
5304 | int sh = SH(ctx->opcode); |
5305 | TCGv t0 = tcg_temp_new(); | |
5306 | TCGv t1 = tcg_temp_new(); | |
5307 | tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5308 | gen_load_spr(t1, SPR_MQ); | |
5309 | gen_store_spr(SPR_MQ, t0); | |
5310 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); | |
5311 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); | |
5312 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5313 | tcg_temp_free(t0); | |
5314 | tcg_temp_free(t1); | |
76a66253 | 5315 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5316 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5317 | } |
5318 | ||
5319 | /* srlq */ | |
99e300ef | 5320 | static void gen_srlq(DisasContext *ctx) |
76a66253 | 5321 | { |
42a268c2 RH |
5322 | TCGLabel *l1 = gen_new_label(); |
5323 | TCGLabel *l2 = gen_new_label(); | |
7487953d AJ |
5324 | TCGv t0 = tcg_temp_local_new(); |
5325 | TCGv t1 = tcg_temp_local_new(); | |
5326 | TCGv t2 = tcg_temp_local_new(); | |
5327 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5328 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5329 | tcg_gen_shr_tl(t2, t1, t2); | |
5330 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5331 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5332 | gen_load_spr(t0, SPR_MQ); | |
5333 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); | |
5334 | tcg_gen_br(l2); | |
5335 | gen_set_label(l1); | |
5336 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
5337 | tcg_gen_and_tl(t0, t0, t2); | |
5338 | gen_load_spr(t1, SPR_MQ); | |
5339 | tcg_gen_andc_tl(t1, t1, t2); | |
5340 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5341 | gen_set_label(l2); | |
5342 | tcg_temp_free(t0); | |
5343 | tcg_temp_free(t1); | |
5344 | tcg_temp_free(t2); | |
76a66253 | 5345 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5346 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5347 | } |
5348 | ||
5349 | /* srq */ | |
99e300ef | 5350 | static void gen_srq(DisasContext *ctx) |
76a66253 | 5351 | { |
42a268c2 | 5352 | TCGLabel *l1 = gen_new_label(); |
7487953d AJ |
5353 | TCGv t0 = tcg_temp_new(); |
5354 | TCGv t1 = tcg_temp_new(); | |
5355 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5356 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5357 | tcg_gen_subfi_tl(t1, 32, t1); | |
5358 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5359 | tcg_gen_or_tl(t1, t0, t1); | |
5360 | gen_store_spr(SPR_MQ, t1); | |
5361 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5362 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5363 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5364 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
5365 | gen_set_label(l1); | |
5366 | tcg_temp_free(t0); | |
5367 | tcg_temp_free(t1); | |
76a66253 | 5368 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5369 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5370 | } |
5371 | ||
5372 | /* PowerPC 602 specific instructions */ | |
99e300ef | 5373 | |
54623277 | 5374 | /* dsa */ |
99e300ef | 5375 | static void gen_dsa(DisasContext *ctx) |
76a66253 JM |
5376 | { |
5377 | /* XXX: TODO */ | |
e06fcd75 | 5378 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5379 | } |
5380 | ||
5381 | /* esa */ | |
99e300ef | 5382 | static void gen_esa(DisasContext *ctx) |
76a66253 JM |
5383 | { |
5384 | /* XXX: TODO */ | |
e06fcd75 | 5385 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5386 | } |
5387 | ||
5388 | /* mfrom */ | |
99e300ef | 5389 | static void gen_mfrom(DisasContext *ctx) |
76a66253 JM |
5390 | { |
5391 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5392 | GEN_PRIV; |
76a66253 | 5393 | #else |
9b2fadda | 5394 | CHK_SV; |
cf02a65c | 5395 | gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
9b2fadda | 5396 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5397 | } |
5398 | ||
5399 | /* 602 - 603 - G2 TLB management */ | |
e8eaa2c0 | 5400 | |
54623277 | 5401 | /* tlbld */ |
e8eaa2c0 | 5402 | static void gen_tlbld_6xx(DisasContext *ctx) |
76a66253 JM |
5403 | { |
5404 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5405 | GEN_PRIV; |
76a66253 | 5406 | #else |
9b2fadda | 5407 | CHK_SV; |
c6c7cf05 | 5408 | gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 5409 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5410 | } |
5411 | ||
5412 | /* tlbli */ | |
e8eaa2c0 | 5413 | static void gen_tlbli_6xx(DisasContext *ctx) |
76a66253 JM |
5414 | { |
5415 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5416 | GEN_PRIV; |
76a66253 | 5417 | #else |
9b2fadda | 5418 | CHK_SV; |
c6c7cf05 | 5419 | gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 5420 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5421 | } |
5422 | ||
7dbe11ac | 5423 | /* 74xx TLB management */ |
e8eaa2c0 | 5424 | |
54623277 | 5425 | /* tlbld */ |
e8eaa2c0 | 5426 | static void gen_tlbld_74xx(DisasContext *ctx) |
7dbe11ac JM |
5427 | { |
5428 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5429 | GEN_PRIV; |
7dbe11ac | 5430 | #else |
9b2fadda | 5431 | CHK_SV; |
c6c7cf05 | 5432 | gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 5433 | #endif /* defined(CONFIG_USER_ONLY) */ |
7dbe11ac JM |
5434 | } |
5435 | ||
5436 | /* tlbli */ | |
e8eaa2c0 | 5437 | static void gen_tlbli_74xx(DisasContext *ctx) |
7dbe11ac JM |
5438 | { |
5439 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5440 | GEN_PRIV; |
7dbe11ac | 5441 | #else |
9b2fadda | 5442 | CHK_SV; |
c6c7cf05 | 5443 | gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 5444 | #endif /* defined(CONFIG_USER_ONLY) */ |
7dbe11ac JM |
5445 | } |
5446 | ||
76a66253 | 5447 | /* POWER instructions not in PowerPC 601 */ |
99e300ef | 5448 | |
54623277 | 5449 | /* clf */ |
99e300ef | 5450 | static void gen_clf(DisasContext *ctx) |
76a66253 JM |
5451 | { |
5452 | /* Cache line flush: implemented as no-op */ | |
5453 | } | |
5454 | ||
5455 | /* cli */ | |
99e300ef | 5456 | static void gen_cli(DisasContext *ctx) |
76a66253 | 5457 | { |
76a66253 | 5458 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 5459 | GEN_PRIV; |
76a66253 | 5460 | #else |
9b2fadda BH |
5461 | /* Cache line invalidate: privileged and treated as no-op */ |
5462 | CHK_SV; | |
5463 | #endif /* defined(CONFIG_USER_ONLY) */ | |
76a66253 JM |
5464 | } |
5465 | ||
5466 | /* dclst */ | |
99e300ef | 5467 | static void gen_dclst(DisasContext *ctx) |
76a66253 JM |
5468 | { |
5469 | /* Data cache line store: treated as no-op */ | |
5470 | } | |
5471 | ||
99e300ef | 5472 | static void gen_mfsri(DisasContext *ctx) |
76a66253 JM |
5473 | { |
5474 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5475 | GEN_PRIV; |
76a66253 | 5476 | #else |
74d37793 AJ |
5477 | int ra = rA(ctx->opcode); |
5478 | int rd = rD(ctx->opcode); | |
5479 | TCGv t0; | |
9b2fadda BH |
5480 | |
5481 | CHK_SV; | |
74d37793 | 5482 | t0 = tcg_temp_new(); |
76db3ba4 | 5483 | gen_addr_reg_index(ctx, t0); |
e2622073 | 5484 | tcg_gen_extract_tl(t0, t0, 28, 4); |
c6c7cf05 | 5485 | gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); |
74d37793 | 5486 | tcg_temp_free(t0); |
76a66253 | 5487 | if (ra != 0 && ra != rd) |
74d37793 | 5488 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); |
9b2fadda | 5489 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5490 | } |
5491 | ||
99e300ef | 5492 | static void gen_rac(DisasContext *ctx) |
76a66253 JM |
5493 | { |
5494 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5495 | GEN_PRIV; |
76a66253 | 5496 | #else |
22e0e173 | 5497 | TCGv t0; |
9b2fadda BH |
5498 | |
5499 | CHK_SV; | |
22e0e173 | 5500 | t0 = tcg_temp_new(); |
76db3ba4 | 5501 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 5502 | gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
22e0e173 | 5503 | tcg_temp_free(t0); |
9b2fadda | 5504 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5505 | } |
5506 | ||
99e300ef | 5507 | static void gen_rfsvc(DisasContext *ctx) |
76a66253 JM |
5508 | { |
5509 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5510 | GEN_PRIV; |
76a66253 | 5511 | #else |
9b2fadda BH |
5512 | CHK_SV; |
5513 | ||
e5f17ac6 | 5514 | gen_helper_rfsvc(cpu_env); |
e06fcd75 | 5515 | gen_sync_exception(ctx); |
9b2fadda | 5516 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5517 | } |
5518 | ||
f9651121 | 5519 | /* svc is not implemented for now */ |
76a66253 JM |
5520 | |
5521 | /* BookE specific instructions */ | |
99e300ef | 5522 | |
54623277 | 5523 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5524 | static void gen_mfapidi(DisasContext *ctx) |
76a66253 JM |
5525 | { |
5526 | /* XXX: TODO */ | |
e06fcd75 | 5527 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5528 | } |
5529 | ||
2662a059 | 5530 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5531 | static void gen_tlbiva(DisasContext *ctx) |
76a66253 JM |
5532 | { |
5533 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5534 | GEN_PRIV; |
76a66253 | 5535 | #else |
74d37793 | 5536 | TCGv t0; |
9b2fadda BH |
5537 | |
5538 | CHK_SV; | |
ec72e276 | 5539 | t0 = tcg_temp_new(); |
76db3ba4 | 5540 | gen_addr_reg_index(ctx, t0); |
4693364f | 5541 | gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
74d37793 | 5542 | tcg_temp_free(t0); |
9b2fadda | 5543 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5544 | } |
5545 | ||
5546 | /* All 405 MAC instructions are translated here */ | |
636aa200 BS |
5547 | static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, |
5548 | int ra, int rb, int rt, int Rc) | |
76a66253 | 5549 | { |
182608d4 AJ |
5550 | TCGv t0, t1; |
5551 | ||
a7812ae4 PB |
5552 | t0 = tcg_temp_local_new(); |
5553 | t1 = tcg_temp_local_new(); | |
182608d4 | 5554 | |
76a66253 JM |
5555 | switch (opc3 & 0x0D) { |
5556 | case 0x05: | |
5557 | /* macchw - macchw. - macchwo - macchwo. */ | |
5558 | /* macchws - macchws. - macchwso - macchwso. */ | |
5559 | /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ | |
5560 | /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ | |
5561 | /* mulchw - mulchw. */ | |
182608d4 AJ |
5562 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5563 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5564 | tcg_gen_ext16s_tl(t1, t1); | |
76a66253 JM |
5565 | break; |
5566 | case 0x04: | |
5567 | /* macchwu - macchwu. - macchwuo - macchwuo. */ | |
5568 | /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ | |
5569 | /* mulchwu - mulchwu. */ | |
182608d4 AJ |
5570 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5571 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5572 | tcg_gen_ext16u_tl(t1, t1); | |
76a66253 JM |
5573 | break; |
5574 | case 0x01: | |
5575 | /* machhw - machhw. - machhwo - machhwo. */ | |
5576 | /* machhws - machhws. - machhwso - machhwso. */ | |
5577 | /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ | |
5578 | /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ | |
5579 | /* mulhhw - mulhhw. */ | |
182608d4 AJ |
5580 | tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); |
5581 | tcg_gen_ext16s_tl(t0, t0); | |
5582 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5583 | tcg_gen_ext16s_tl(t1, t1); | |
76a66253 JM |
5584 | break; |
5585 | case 0x00: | |
5586 | /* machhwu - machhwu. - machhwuo - machhwuo. */ | |
5587 | /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ | |
5588 | /* mulhhwu - mulhhwu. */ | |
182608d4 AJ |
5589 | tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); |
5590 | tcg_gen_ext16u_tl(t0, t0); | |
5591 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5592 | tcg_gen_ext16u_tl(t1, t1); | |
76a66253 JM |
5593 | break; |
5594 | case 0x0D: | |
5595 | /* maclhw - maclhw. - maclhwo - maclhwo. */ | |
5596 | /* maclhws - maclhws. - maclhwso - maclhwso. */ | |
5597 | /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ | |
5598 | /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ | |
5599 | /* mullhw - mullhw. */ | |
182608d4 AJ |
5600 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5601 | tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); | |
76a66253 JM |
5602 | break; |
5603 | case 0x0C: | |
5604 | /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ | |
5605 | /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ | |
5606 | /* mullhwu - mullhwu. */ | |
182608d4 AJ |
5607 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5608 | tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); | |
76a66253 JM |
5609 | break; |
5610 | } | |
76a66253 | 5611 | if (opc2 & 0x04) { |
182608d4 AJ |
5612 | /* (n)multiply-and-accumulate (0x0C / 0x0E) */ |
5613 | tcg_gen_mul_tl(t1, t0, t1); | |
5614 | if (opc2 & 0x02) { | |
5615 | /* nmultiply-and-accumulate (0x0E) */ | |
5616 | tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); | |
5617 | } else { | |
5618 | /* multiply-and-accumulate (0x0C) */ | |
5619 | tcg_gen_add_tl(t0, cpu_gpr[rt], t1); | |
5620 | } | |
5621 | ||
5622 | if (opc3 & 0x12) { | |
5623 | /* Check overflow and/or saturate */ | |
42a268c2 | 5624 | TCGLabel *l1 = gen_new_label(); |
182608d4 AJ |
5625 | |
5626 | if (opc3 & 0x10) { | |
5627 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 5628 | tcg_gen_movi_tl(cpu_ov, 0); |
182608d4 AJ |
5629 | } |
5630 | if (opc3 & 0x01) { | |
5631 | /* Signed */ | |
5632 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); | |
5633 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); | |
5634 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); | |
5635 | tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); | |
bdc4e053 | 5636 | if (opc3 & 0x02) { |
182608d4 AJ |
5637 | /* Saturate */ |
5638 | tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); | |
5639 | tcg_gen_xori_tl(t0, t0, 0x7fffffff); | |
5640 | } | |
5641 | } else { | |
5642 | /* Unsigned */ | |
5643 | tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); | |
bdc4e053 | 5644 | if (opc3 & 0x02) { |
182608d4 AJ |
5645 | /* Saturate */ |
5646 | tcg_gen_movi_tl(t0, UINT32_MAX); | |
5647 | } | |
5648 | } | |
5649 | if (opc3 & 0x10) { | |
5650 | /* Check overflow */ | |
da91a00f RH |
5651 | tcg_gen_movi_tl(cpu_ov, 1); |
5652 | tcg_gen_movi_tl(cpu_so, 1); | |
182608d4 AJ |
5653 | } |
5654 | gen_set_label(l1); | |
5655 | tcg_gen_mov_tl(cpu_gpr[rt], t0); | |
5656 | } | |
5657 | } else { | |
5658 | tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); | |
76a66253 | 5659 | } |
182608d4 AJ |
5660 | tcg_temp_free(t0); |
5661 | tcg_temp_free(t1); | |
76a66253 JM |
5662 | if (unlikely(Rc) != 0) { |
5663 | /* Update Rc0 */ | |
182608d4 | 5664 | gen_set_Rc0(ctx, cpu_gpr[rt]); |
76a66253 JM |
5665 | } |
5666 | } | |
5667 | ||
a750fc0b | 5668 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ |
99e300ef | 5669 | static void glue(gen_, name)(DisasContext *ctx) \ |
76a66253 JM |
5670 | { \ |
5671 | gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ | |
5672 | rD(ctx->opcode), Rc(ctx->opcode)); \ | |
5673 | } | |
5674 | ||
5675 | /* macchw - macchw. */ | |
a750fc0b | 5676 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05); |
76a66253 | 5677 | /* macchwo - macchwo. */ |
a750fc0b | 5678 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); |
76a66253 | 5679 | /* macchws - macchws. */ |
a750fc0b | 5680 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07); |
76a66253 | 5681 | /* macchwso - macchwso. */ |
a750fc0b | 5682 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); |
76a66253 | 5683 | /* macchwsu - macchwsu. */ |
a750fc0b | 5684 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); |
76a66253 | 5685 | /* macchwsuo - macchwsuo. */ |
a750fc0b | 5686 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); |
76a66253 | 5687 | /* macchwu - macchwu. */ |
a750fc0b | 5688 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); |
76a66253 | 5689 | /* macchwuo - macchwuo. */ |
a750fc0b | 5690 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); |
76a66253 | 5691 | /* machhw - machhw. */ |
a750fc0b | 5692 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01); |
76a66253 | 5693 | /* machhwo - machhwo. */ |
a750fc0b | 5694 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); |
76a66253 | 5695 | /* machhws - machhws. */ |
a750fc0b | 5696 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03); |
76a66253 | 5697 | /* machhwso - machhwso. */ |
a750fc0b | 5698 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); |
76a66253 | 5699 | /* machhwsu - machhwsu. */ |
a750fc0b | 5700 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); |
76a66253 | 5701 | /* machhwsuo - machhwsuo. */ |
a750fc0b | 5702 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); |
76a66253 | 5703 | /* machhwu - machhwu. */ |
a750fc0b | 5704 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); |
76a66253 | 5705 | /* machhwuo - machhwuo. */ |
a750fc0b | 5706 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); |
76a66253 | 5707 | /* maclhw - maclhw. */ |
a750fc0b | 5708 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); |
76a66253 | 5709 | /* maclhwo - maclhwo. */ |
a750fc0b | 5710 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); |
76a66253 | 5711 | /* maclhws - maclhws. */ |
a750fc0b | 5712 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); |
76a66253 | 5713 | /* maclhwso - maclhwso. */ |
a750fc0b | 5714 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); |
76a66253 | 5715 | /* maclhwu - maclhwu. */ |
a750fc0b | 5716 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); |
76a66253 | 5717 | /* maclhwuo - maclhwuo. */ |
a750fc0b | 5718 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); |
76a66253 | 5719 | /* maclhwsu - maclhwsu. */ |
a750fc0b | 5720 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); |
76a66253 | 5721 | /* maclhwsuo - maclhwsuo. */ |
a750fc0b | 5722 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); |
76a66253 | 5723 | /* nmacchw - nmacchw. */ |
a750fc0b | 5724 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); |
76a66253 | 5725 | /* nmacchwo - nmacchwo. */ |
a750fc0b | 5726 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); |
76a66253 | 5727 | /* nmacchws - nmacchws. */ |
a750fc0b | 5728 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); |
76a66253 | 5729 | /* nmacchwso - nmacchwso. */ |
a750fc0b | 5730 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); |
76a66253 | 5731 | /* nmachhw - nmachhw. */ |
a750fc0b | 5732 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); |
76a66253 | 5733 | /* nmachhwo - nmachhwo. */ |
a750fc0b | 5734 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); |
76a66253 | 5735 | /* nmachhws - nmachhws. */ |
a750fc0b | 5736 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); |
76a66253 | 5737 | /* nmachhwso - nmachhwso. */ |
a750fc0b | 5738 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); |
76a66253 | 5739 | /* nmaclhw - nmaclhw. */ |
a750fc0b | 5740 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); |
76a66253 | 5741 | /* nmaclhwo - nmaclhwo. */ |
a750fc0b | 5742 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); |
76a66253 | 5743 | /* nmaclhws - nmaclhws. */ |
a750fc0b | 5744 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); |
76a66253 | 5745 | /* nmaclhwso - nmaclhwso. */ |
a750fc0b | 5746 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); |
76a66253 JM |
5747 | |
5748 | /* mulchw - mulchw. */ | |
a750fc0b | 5749 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05); |
76a66253 | 5750 | /* mulchwu - mulchwu. */ |
a750fc0b | 5751 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); |
76a66253 | 5752 | /* mulhhw - mulhhw. */ |
a750fc0b | 5753 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); |
76a66253 | 5754 | /* mulhhwu - mulhhwu. */ |
a750fc0b | 5755 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); |
76a66253 | 5756 | /* mullhw - mullhw. */ |
a750fc0b | 5757 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); |
76a66253 | 5758 | /* mullhwu - mullhwu. */ |
a750fc0b | 5759 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); |
76a66253 JM |
5760 | |
5761 | /* mfdcr */ | |
99e300ef | 5762 | static void gen_mfdcr(DisasContext *ctx) |
76a66253 JM |
5763 | { |
5764 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5765 | GEN_PRIV; |
76a66253 | 5766 | #else |
06dca6a7 | 5767 | TCGv dcrn; |
9b2fadda BH |
5768 | |
5769 | CHK_SV; | |
06dca6a7 | 5770 | dcrn = tcg_const_tl(SPR(ctx->opcode)); |
d0f1562d | 5771 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); |
06dca6a7 | 5772 | tcg_temp_free(dcrn); |
9b2fadda | 5773 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5774 | } |
5775 | ||
5776 | /* mtdcr */ | |
99e300ef | 5777 | static void gen_mtdcr(DisasContext *ctx) |
76a66253 JM |
5778 | { |
5779 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5780 | GEN_PRIV; |
76a66253 | 5781 | #else |
06dca6a7 | 5782 | TCGv dcrn; |
9b2fadda BH |
5783 | |
5784 | CHK_SV; | |
06dca6a7 | 5785 | dcrn = tcg_const_tl(SPR(ctx->opcode)); |
d0f1562d | 5786 | gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); |
06dca6a7 | 5787 | tcg_temp_free(dcrn); |
9b2fadda | 5788 | #endif /* defined(CONFIG_USER_ONLY) */ |
a42bd6cc JM |
5789 | } |
5790 | ||
5791 | /* mfdcrx */ | |
2662a059 | 5792 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5793 | static void gen_mfdcrx(DisasContext *ctx) |
a42bd6cc JM |
5794 | { |
5795 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5796 | GEN_PRIV; |
a42bd6cc | 5797 | #else |
9b2fadda | 5798 | CHK_SV; |
d0f1562d BS |
5799 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5800 | cpu_gpr[rA(ctx->opcode)]); | |
a750fc0b | 5801 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
9b2fadda | 5802 | #endif /* defined(CONFIG_USER_ONLY) */ |
a42bd6cc JM |
5803 | } |
5804 | ||
5805 | /* mtdcrx */ | |
2662a059 | 5806 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5807 | static void gen_mtdcrx(DisasContext *ctx) |
a42bd6cc JM |
5808 | { |
5809 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5810 | GEN_PRIV; |
a42bd6cc | 5811 | #else |
9b2fadda | 5812 | CHK_SV; |
d0f1562d BS |
5813 | gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], |
5814 | cpu_gpr[rS(ctx->opcode)]); | |
a750fc0b | 5815 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
9b2fadda | 5816 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5817 | } |
5818 | ||
a750fc0b | 5819 | /* mfdcrux (PPC 460) : user-mode access to DCR */ |
99e300ef | 5820 | static void gen_mfdcrux(DisasContext *ctx) |
a750fc0b | 5821 | { |
d0f1562d BS |
5822 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5823 | cpu_gpr[rA(ctx->opcode)]); | |
a750fc0b JM |
5824 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
5825 | } | |
5826 | ||
5827 | /* mtdcrux (PPC 460) : user-mode access to DCR */ | |
99e300ef | 5828 | static void gen_mtdcrux(DisasContext *ctx) |
a750fc0b | 5829 | { |
975e5463 | 5830 | gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], |
d0f1562d | 5831 | cpu_gpr[rS(ctx->opcode)]); |
a750fc0b JM |
5832 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
5833 | } | |
5834 | ||
76a66253 | 5835 | /* dccci */ |
99e300ef | 5836 | static void gen_dccci(DisasContext *ctx) |
76a66253 | 5837 | { |
9b2fadda | 5838 | CHK_SV; |
76a66253 | 5839 | /* interpreted as no-op */ |
76a66253 JM |
5840 | } |
5841 | ||
5842 | /* dcread */ | |
99e300ef | 5843 | static void gen_dcread(DisasContext *ctx) |
76a66253 JM |
5844 | { |
5845 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5846 | GEN_PRIV; |
76a66253 | 5847 | #else |
b61f2753 | 5848 | TCGv EA, val; |
9b2fadda BH |
5849 | |
5850 | CHK_SV; | |
76db3ba4 | 5851 | gen_set_access_type(ctx, ACCESS_CACHE); |
a7812ae4 | 5852 | EA = tcg_temp_new(); |
76db3ba4 | 5853 | gen_addr_reg_index(ctx, EA); |
a7812ae4 | 5854 | val = tcg_temp_new(); |
76db3ba4 | 5855 | gen_qemu_ld32u(ctx, val, EA); |
b61f2753 AJ |
5856 | tcg_temp_free(val); |
5857 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); | |
5858 | tcg_temp_free(EA); | |
9b2fadda | 5859 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5860 | } |
5861 | ||
5862 | /* icbt */ | |
e8eaa2c0 | 5863 | static void gen_icbt_40x(DisasContext *ctx) |
76a66253 JM |
5864 | { |
5865 | /* interpreted as no-op */ | |
5866 | /* XXX: specification say this is treated as a load by the MMU | |
5867 | * but does not generate any exception | |
5868 | */ | |
5869 | } | |
5870 | ||
5871 | /* iccci */ | |
99e300ef | 5872 | static void gen_iccci(DisasContext *ctx) |
76a66253 | 5873 | { |
9b2fadda | 5874 | CHK_SV; |
76a66253 | 5875 | /* interpreted as no-op */ |
76a66253 JM |
5876 | } |
5877 | ||
5878 | /* icread */ | |
99e300ef | 5879 | static void gen_icread(DisasContext *ctx) |
76a66253 | 5880 | { |
9b2fadda | 5881 | CHK_SV; |
76a66253 | 5882 | /* interpreted as no-op */ |
76a66253 JM |
5883 | } |
5884 | ||
c47493f2 | 5885 | /* rfci (supervisor only) */ |
e8eaa2c0 | 5886 | static void gen_rfci_40x(DisasContext *ctx) |
a42bd6cc JM |
5887 | { |
5888 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5889 | GEN_PRIV; |
a42bd6cc | 5890 | #else |
9b2fadda | 5891 | CHK_SV; |
a42bd6cc | 5892 | /* Restore CPU state */ |
e5f17ac6 | 5893 | gen_helper_40x_rfci(cpu_env); |
e06fcd75 | 5894 | gen_sync_exception(ctx); |
9b2fadda | 5895 | #endif /* defined(CONFIG_USER_ONLY) */ |
a42bd6cc JM |
5896 | } |
5897 | ||
99e300ef | 5898 | static void gen_rfci(DisasContext *ctx) |
a42bd6cc JM |
5899 | { |
5900 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5901 | GEN_PRIV; |
a42bd6cc | 5902 | #else |
9b2fadda | 5903 | CHK_SV; |
a42bd6cc | 5904 | /* Restore CPU state */ |
e5f17ac6 | 5905 | gen_helper_rfci(cpu_env); |
e06fcd75 | 5906 | gen_sync_exception(ctx); |
9b2fadda | 5907 | #endif /* defined(CONFIG_USER_ONLY) */ |
a42bd6cc JM |
5908 | } |
5909 | ||
5910 | /* BookE specific */ | |
99e300ef | 5911 | |
54623277 | 5912 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5913 | static void gen_rfdi(DisasContext *ctx) |
76a66253 JM |
5914 | { |
5915 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5916 | GEN_PRIV; |
76a66253 | 5917 | #else |
9b2fadda | 5918 | CHK_SV; |
76a66253 | 5919 | /* Restore CPU state */ |
e5f17ac6 | 5920 | gen_helper_rfdi(cpu_env); |
e06fcd75 | 5921 | gen_sync_exception(ctx); |
9b2fadda | 5922 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5923 | } |
5924 | ||
2662a059 | 5925 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5926 | static void gen_rfmci(DisasContext *ctx) |
a42bd6cc JM |
5927 | { |
5928 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5929 | GEN_PRIV; |
a42bd6cc | 5930 | #else |
9b2fadda | 5931 | CHK_SV; |
a42bd6cc | 5932 | /* Restore CPU state */ |
e5f17ac6 | 5933 | gen_helper_rfmci(cpu_env); |
e06fcd75 | 5934 | gen_sync_exception(ctx); |
9b2fadda | 5935 | #endif /* defined(CONFIG_USER_ONLY) */ |
a42bd6cc | 5936 | } |
5eb7995e | 5937 | |
d9bce9d9 | 5938 | /* TLB management - PowerPC 405 implementation */ |
e8eaa2c0 | 5939 | |
54623277 | 5940 | /* tlbre */ |
e8eaa2c0 | 5941 | static void gen_tlbre_40x(DisasContext *ctx) |
76a66253 JM |
5942 | { |
5943 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5944 | GEN_PRIV; |
76a66253 | 5945 | #else |
9b2fadda | 5946 | CHK_SV; |
76a66253 JM |
5947 | switch (rB(ctx->opcode)) { |
5948 | case 0: | |
c6c7cf05 BS |
5949 | gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5950 | cpu_gpr[rA(ctx->opcode)]); | |
76a66253 JM |
5951 | break; |
5952 | case 1: | |
c6c7cf05 BS |
5953 | gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5954 | cpu_gpr[rA(ctx->opcode)]); | |
76a66253 JM |
5955 | break; |
5956 | default: | |
e06fcd75 | 5957 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 | 5958 | break; |
9a64fbe4 | 5959 | } |
9b2fadda | 5960 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5961 | } |
5962 | ||
d9bce9d9 | 5963 | /* tlbsx - tlbsx. */ |
e8eaa2c0 | 5964 | static void gen_tlbsx_40x(DisasContext *ctx) |
76a66253 JM |
5965 | { |
5966 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5967 | GEN_PRIV; |
76a66253 | 5968 | #else |
74d37793 | 5969 | TCGv t0; |
9b2fadda BH |
5970 | |
5971 | CHK_SV; | |
74d37793 | 5972 | t0 = tcg_temp_new(); |
76db3ba4 | 5973 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 5974 | gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 AJ |
5975 | tcg_temp_free(t0); |
5976 | if (Rc(ctx->opcode)) { | |
42a268c2 | 5977 | TCGLabel *l1 = gen_new_label(); |
da91a00f | 5978 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
74d37793 AJ |
5979 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); |
5980 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); | |
5981 | gen_set_label(l1); | |
5982 | } | |
9b2fadda | 5983 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
5984 | } |
5985 | ||
76a66253 | 5986 | /* tlbwe */ |
e8eaa2c0 | 5987 | static void gen_tlbwe_40x(DisasContext *ctx) |
79aceca5 | 5988 | { |
76a66253 | 5989 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 5990 | GEN_PRIV; |
76a66253 | 5991 | #else |
9b2fadda BH |
5992 | CHK_SV; |
5993 | ||
76a66253 JM |
5994 | switch (rB(ctx->opcode)) { |
5995 | case 0: | |
c6c7cf05 BS |
5996 | gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], |
5997 | cpu_gpr[rS(ctx->opcode)]); | |
76a66253 JM |
5998 | break; |
5999 | case 1: | |
c6c7cf05 BS |
6000 | gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], |
6001 | cpu_gpr[rS(ctx->opcode)]); | |
76a66253 JM |
6002 | break; |
6003 | default: | |
e06fcd75 | 6004 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 | 6005 | break; |
9a64fbe4 | 6006 | } |
9b2fadda | 6007 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
6008 | } |
6009 | ||
a4bb6c3e | 6010 | /* TLB management - PowerPC 440 implementation */ |
e8eaa2c0 | 6011 | |
54623277 | 6012 | /* tlbre */ |
e8eaa2c0 | 6013 | static void gen_tlbre_440(DisasContext *ctx) |
5eb7995e JM |
6014 | { |
6015 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6016 | GEN_PRIV; |
5eb7995e | 6017 | #else |
9b2fadda BH |
6018 | CHK_SV; |
6019 | ||
5eb7995e JM |
6020 | switch (rB(ctx->opcode)) { |
6021 | case 0: | |
5eb7995e | 6022 | case 1: |
5eb7995e | 6023 | case 2: |
74d37793 AJ |
6024 | { |
6025 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); | |
c6c7cf05 BS |
6026 | gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6027 | t0, cpu_gpr[rA(ctx->opcode)]); | |
74d37793 AJ |
6028 | tcg_temp_free_i32(t0); |
6029 | } | |
5eb7995e JM |
6030 | break; |
6031 | default: | |
e06fcd75 | 6032 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5eb7995e JM |
6033 | break; |
6034 | } | |
9b2fadda | 6035 | #endif /* defined(CONFIG_USER_ONLY) */ |
5eb7995e JM |
6036 | } |
6037 | ||
6038 | /* tlbsx - tlbsx. */ | |
e8eaa2c0 | 6039 | static void gen_tlbsx_440(DisasContext *ctx) |
5eb7995e JM |
6040 | { |
6041 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6042 | GEN_PRIV; |
5eb7995e | 6043 | #else |
74d37793 | 6044 | TCGv t0; |
9b2fadda BH |
6045 | |
6046 | CHK_SV; | |
74d37793 | 6047 | t0 = tcg_temp_new(); |
76db3ba4 | 6048 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 6049 | gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 AJ |
6050 | tcg_temp_free(t0); |
6051 | if (Rc(ctx->opcode)) { | |
42a268c2 | 6052 | TCGLabel *l1 = gen_new_label(); |
da91a00f | 6053 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
74d37793 AJ |
6054 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); |
6055 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); | |
6056 | gen_set_label(l1); | |
6057 | } | |
9b2fadda | 6058 | #endif /* defined(CONFIG_USER_ONLY) */ |
5eb7995e JM |
6059 | } |
6060 | ||
6061 | /* tlbwe */ | |
e8eaa2c0 | 6062 | static void gen_tlbwe_440(DisasContext *ctx) |
5eb7995e JM |
6063 | { |
6064 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6065 | GEN_PRIV; |
5eb7995e | 6066 | #else |
9b2fadda | 6067 | CHK_SV; |
5eb7995e JM |
6068 | switch (rB(ctx->opcode)) { |
6069 | case 0: | |
5eb7995e | 6070 | case 1: |
5eb7995e | 6071 | case 2: |
74d37793 AJ |
6072 | { |
6073 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); | |
c6c7cf05 BS |
6074 | gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], |
6075 | cpu_gpr[rS(ctx->opcode)]); | |
74d37793 AJ |
6076 | tcg_temp_free_i32(t0); |
6077 | } | |
5eb7995e JM |
6078 | break; |
6079 | default: | |
e06fcd75 | 6080 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5eb7995e JM |
6081 | break; |
6082 | } | |
9b2fadda | 6083 | #endif /* defined(CONFIG_USER_ONLY) */ |
5eb7995e JM |
6084 | } |
6085 | ||
01662f3e AG |
6086 | /* TLB management - PowerPC BookE 2.06 implementation */ |
6087 | ||
6088 | /* tlbre */ | |
6089 | static void gen_tlbre_booke206(DisasContext *ctx) | |
6090 | { | |
9b2fadda BH |
6091 | #if defined(CONFIG_USER_ONLY) |
6092 | GEN_PRIV; | |
01662f3e | 6093 | #else |
9b2fadda | 6094 | CHK_SV; |
c6c7cf05 | 6095 | gen_helper_booke206_tlbre(cpu_env); |
9b2fadda | 6096 | #endif /* defined(CONFIG_USER_ONLY) */ |
01662f3e AG |
6097 | } |
6098 | ||
6099 | /* tlbsx - tlbsx. */ | |
6100 | static void gen_tlbsx_booke206(DisasContext *ctx) | |
6101 | { | |
6102 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6103 | GEN_PRIV; |
01662f3e AG |
6104 | #else |
6105 | TCGv t0; | |
01662f3e | 6106 | |
9b2fadda | 6107 | CHK_SV; |
01662f3e AG |
6108 | if (rA(ctx->opcode)) { |
6109 | t0 = tcg_temp_new(); | |
6110 | tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); | |
6111 | } else { | |
6112 | t0 = tcg_const_tl(0); | |
6113 | } | |
6114 | ||
6115 | tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); | |
c6c7cf05 | 6116 | gen_helper_booke206_tlbsx(cpu_env, t0); |
c80d1df5 | 6117 | tcg_temp_free(t0); |
9b2fadda | 6118 | #endif /* defined(CONFIG_USER_ONLY) */ |
01662f3e AG |
6119 | } |
6120 | ||
6121 | /* tlbwe */ | |
6122 | static void gen_tlbwe_booke206(DisasContext *ctx) | |
6123 | { | |
6124 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6125 | GEN_PRIV; |
01662f3e | 6126 | #else |
9b2fadda | 6127 | CHK_SV; |
c6c7cf05 | 6128 | gen_helper_booke206_tlbwe(cpu_env); |
9b2fadda | 6129 | #endif /* defined(CONFIG_USER_ONLY) */ |
01662f3e AG |
6130 | } |
6131 | ||
6132 | static void gen_tlbivax_booke206(DisasContext *ctx) | |
6133 | { | |
6134 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6135 | GEN_PRIV; |
01662f3e AG |
6136 | #else |
6137 | TCGv t0; | |
01662f3e | 6138 | |
9b2fadda | 6139 | CHK_SV; |
01662f3e AG |
6140 | t0 = tcg_temp_new(); |
6141 | gen_addr_reg_index(ctx, t0); | |
c6c7cf05 | 6142 | gen_helper_booke206_tlbivax(cpu_env, t0); |
c80d1df5 | 6143 | tcg_temp_free(t0); |
9b2fadda | 6144 | #endif /* defined(CONFIG_USER_ONLY) */ |
01662f3e AG |
6145 | } |
6146 | ||
6d3db821 AG |
6147 | static void gen_tlbilx_booke206(DisasContext *ctx) |
6148 | { | |
6149 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6150 | GEN_PRIV; |
6d3db821 AG |
6151 | #else |
6152 | TCGv t0; | |
6d3db821 | 6153 | |
9b2fadda | 6154 | CHK_SV; |
6d3db821 AG |
6155 | t0 = tcg_temp_new(); |
6156 | gen_addr_reg_index(ctx, t0); | |
6157 | ||
6158 | switch((ctx->opcode >> 21) & 0x3) { | |
6159 | case 0: | |
c6c7cf05 | 6160 | gen_helper_booke206_tlbilx0(cpu_env, t0); |
6d3db821 AG |
6161 | break; |
6162 | case 1: | |
c6c7cf05 | 6163 | gen_helper_booke206_tlbilx1(cpu_env, t0); |
6d3db821 AG |
6164 | break; |
6165 | case 3: | |
c6c7cf05 | 6166 | gen_helper_booke206_tlbilx3(cpu_env, t0); |
6d3db821 AG |
6167 | break; |
6168 | default: | |
6169 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
6170 | break; | |
6171 | } | |
6172 | ||
6173 | tcg_temp_free(t0); | |
9b2fadda | 6174 | #endif /* defined(CONFIG_USER_ONLY) */ |
6d3db821 AG |
6175 | } |
6176 | ||
01662f3e | 6177 | |
76a66253 | 6178 | /* wrtee */ |
99e300ef | 6179 | static void gen_wrtee(DisasContext *ctx) |
76a66253 JM |
6180 | { |
6181 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6182 | GEN_PRIV; |
76a66253 | 6183 | #else |
6527f6ea | 6184 | TCGv t0; |
9b2fadda BH |
6185 | |
6186 | CHK_SV; | |
6527f6ea AJ |
6187 | t0 = tcg_temp_new(); |
6188 | tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); | |
6189 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); | |
6190 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
6191 | tcg_temp_free(t0); | |
dee96f6c JM |
6192 | /* Stop translation to have a chance to raise an exception |
6193 | * if we just set msr_ee to 1 | |
6194 | */ | |
e06fcd75 | 6195 | gen_stop_exception(ctx); |
9b2fadda | 6196 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
6197 | } |
6198 | ||
6199 | /* wrteei */ | |
99e300ef | 6200 | static void gen_wrteei(DisasContext *ctx) |
76a66253 JM |
6201 | { |
6202 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6203 | GEN_PRIV; |
76a66253 | 6204 | #else |
9b2fadda | 6205 | CHK_SV; |
fbe73008 | 6206 | if (ctx->opcode & 0x00008000) { |
6527f6ea AJ |
6207 | tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); |
6208 | /* Stop translation to have a chance to raise an exception */ | |
e06fcd75 | 6209 | gen_stop_exception(ctx); |
6527f6ea | 6210 | } else { |
1b6e5f99 | 6211 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); |
6527f6ea | 6212 | } |
9b2fadda | 6213 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
6214 | } |
6215 | ||
08e46e54 | 6216 | /* PowerPC 440 specific instructions */ |
99e300ef | 6217 | |
54623277 | 6218 | /* dlmzb */ |
99e300ef | 6219 | static void gen_dlmzb(DisasContext *ctx) |
76a66253 | 6220 | { |
ef0d51af | 6221 | TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); |
d15f74fb BS |
6222 | gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, |
6223 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); | |
ef0d51af | 6224 | tcg_temp_free_i32(t0); |
76a66253 JM |
6225 | } |
6226 | ||
6227 | /* mbar replaces eieio on 440 */ | |
99e300ef | 6228 | static void gen_mbar(DisasContext *ctx) |
76a66253 JM |
6229 | { |
6230 | /* interpreted as no-op */ | |
6231 | } | |
6232 | ||
6233 | /* msync replaces sync on 440 */ | |
dcb2b9e1 | 6234 | static void gen_msync_4xx(DisasContext *ctx) |
76a66253 JM |
6235 | { |
6236 | /* interpreted as no-op */ | |
6237 | } | |
6238 | ||
6239 | /* icbt */ | |
e8eaa2c0 | 6240 | static void gen_icbt_440(DisasContext *ctx) |
76a66253 JM |
6241 | { |
6242 | /* interpreted as no-op */ | |
6243 | /* XXX: specification say this is treated as a load by the MMU | |
6244 | * but does not generate any exception | |
6245 | */ | |
79aceca5 FB |
6246 | } |
6247 | ||
9e0b5cb1 AG |
6248 | /* Embedded.Processor Control */ |
6249 | ||
6250 | static void gen_msgclr(DisasContext *ctx) | |
6251 | { | |
6252 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6253 | GEN_PRIV; |
9e0b5cb1 | 6254 | #else |
ebca5e6d | 6255 | CHK_HV; |
7af1e7b0 CLG |
6256 | /* 64-bit server processors compliant with arch 2.x */ |
6257 | if (ctx->insns_flags & PPC_SEGMENT_64B) { | |
6258 | gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); | |
6259 | } else { | |
6260 | gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); | |
6261 | } | |
9b2fadda | 6262 | #endif /* defined(CONFIG_USER_ONLY) */ |
9e0b5cb1 AG |
6263 | } |
6264 | ||
d5d11a39 AG |
6265 | static void gen_msgsnd(DisasContext *ctx) |
6266 | { | |
6267 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6268 | GEN_PRIV; |
d5d11a39 | 6269 | #else |
ebca5e6d | 6270 | CHK_HV; |
7af1e7b0 CLG |
6271 | /* 64-bit server processors compliant with arch 2.x */ |
6272 | if (ctx->insns_flags & PPC_SEGMENT_64B) { | |
6273 | gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]); | |
6274 | } else { | |
6275 | gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); | |
6276 | } | |
9b2fadda | 6277 | #endif /* defined(CONFIG_USER_ONLY) */ |
d5d11a39 AG |
6278 | } |
6279 | ||
7af1e7b0 CLG |
6280 | static void gen_msgsync(DisasContext *ctx) |
6281 | { | |
6282 | #if defined(CONFIG_USER_ONLY) | |
6283 | GEN_PRIV; | |
6284 | #else | |
6285 | CHK_HV; | |
6286 | #endif /* defined(CONFIG_USER_ONLY) */ | |
6287 | /* interpreted as no-op */ | |
6288 | } | |
b04ae981 | 6289 | |
aeeb044c ND |
6290 | #if defined(TARGET_PPC64) |
6291 | static void gen_maddld(DisasContext *ctx) | |
6292 | { | |
6293 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
6294 | ||
6295 | tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
6296 | tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); | |
6297 | tcg_temp_free_i64(t1); | |
6298 | } | |
5f29cc82 ND |
6299 | |
6300 | /* maddhd maddhdu */ | |
6301 | static void gen_maddhd_maddhdu(DisasContext *ctx) | |
6302 | { | |
6303 | TCGv_i64 lo = tcg_temp_new_i64(); | |
6304 | TCGv_i64 hi = tcg_temp_new_i64(); | |
6305 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
6306 | ||
6307 | if (Rc(ctx->opcode)) { | |
6308 | tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], | |
6309 | cpu_gpr[rB(ctx->opcode)]); | |
6310 | tcg_gen_movi_i64(t1, 0); | |
6311 | } else { | |
6312 | tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], | |
6313 | cpu_gpr[rB(ctx->opcode)]); | |
6314 | tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); | |
6315 | } | |
6316 | tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, | |
6317 | cpu_gpr[rC(ctx->opcode)], t1); | |
6318 | tcg_temp_free_i64(lo); | |
6319 | tcg_temp_free_i64(hi); | |
6320 | tcg_temp_free_i64(t1); | |
6321 | } | |
aeeb044c ND |
6322 | #endif /* defined(TARGET_PPC64) */ |
6323 | ||
0ff93d11 TM |
6324 | static void gen_tbegin(DisasContext *ctx) |
6325 | { | |
6326 | if (unlikely(!ctx->tm_enabled)) { | |
6327 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); | |
6328 | return; | |
6329 | } | |
6330 | gen_helper_tbegin(cpu_env); | |
6331 | } | |
6332 | ||
56a84615 TM |
6333 | #define GEN_TM_NOOP(name) \ |
6334 | static inline void gen_##name(DisasContext *ctx) \ | |
6335 | { \ | |
6336 | if (unlikely(!ctx->tm_enabled)) { \ | |
6337 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ | |
6338 | return; \ | |
6339 | } \ | |
6340 | /* Because tbegin always fails in QEMU, these user \ | |
6341 | * space instructions all have a simple implementation: \ | |
6342 | * \ | |
6343 | * CR[0] = 0b0 || MSR[TS] || 0b0 \ | |
6344 | * = 0b0 || 0b00 || 0b0 \ | |
6345 | */ \ | |
6346 | tcg_gen_movi_i32(cpu_crf[0], 0); \ | |
6347 | } | |
6348 | ||
6349 | GEN_TM_NOOP(tend); | |
6350 | GEN_TM_NOOP(tabort); | |
6351 | GEN_TM_NOOP(tabortwc); | |
6352 | GEN_TM_NOOP(tabortwci); | |
6353 | GEN_TM_NOOP(tabortdc); | |
6354 | GEN_TM_NOOP(tabortdci); | |
6355 | GEN_TM_NOOP(tsr); | |
b8b4576e SJS |
6356 | static inline void gen_cp_abort(DisasContext *ctx) |
6357 | { | |
6358 | // Do Nothing | |
6359 | } | |
56a84615 | 6360 | |
80b8c1ee ND |
6361 | #define GEN_CP_PASTE_NOOP(name) \ |
6362 | static inline void gen_##name(DisasContext *ctx) \ | |
6363 | { \ | |
6364 | /* Generate invalid exception until \ | |
6365 | * we have an implementation of the copy \ | |
6366 | * paste facility \ | |
6367 | */ \ | |
6368 | gen_invalid(ctx); \ | |
6369 | } | |
6370 | ||
6371 | GEN_CP_PASTE_NOOP(copy) | |
6372 | GEN_CP_PASTE_NOOP(paste) | |
6373 | ||
aeedd582 TM |
6374 | static void gen_tcheck(DisasContext *ctx) |
6375 | { | |
6376 | if (unlikely(!ctx->tm_enabled)) { | |
6377 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); | |
6378 | return; | |
6379 | } | |
6380 | /* Because tbegin always fails, the tcheck implementation | |
6381 | * is simple: | |
6382 | * | |
6383 | * CR[CRF] = TDOOMED || MSR[TS] || 0b0 | |
6384 | * = 0b1 || 0b00 || 0b0 | |
6385 | */ | |
6386 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); | |
6387 | } | |
6388 | ||
f83c2378 TM |
6389 | #if defined(CONFIG_USER_ONLY) |
6390 | #define GEN_TM_PRIV_NOOP(name) \ | |
6391 | static inline void gen_##name(DisasContext *ctx) \ | |
6392 | { \ | |
9b2fadda | 6393 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ |
f83c2378 TM |
6394 | } |
6395 | ||
6396 | #else | |
6397 | ||
6398 | #define GEN_TM_PRIV_NOOP(name) \ | |
6399 | static inline void gen_##name(DisasContext *ctx) \ | |
6400 | { \ | |
9b2fadda | 6401 | CHK_SV; \ |
f83c2378 TM |
6402 | if (unlikely(!ctx->tm_enabled)) { \ |
6403 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ | |
6404 | return; \ | |
6405 | } \ | |
6406 | /* Because tbegin always fails, the implementation is \ | |
6407 | * simple: \ | |
6408 | * \ | |
6409 | * CR[0] = 0b0 || MSR[TS] || 0b0 \ | |
6410 | * = 0b0 || 0b00 | 0b0 \ | |
6411 | */ \ | |
6412 | tcg_gen_movi_i32(cpu_crf[0], 0); \ | |
6413 | } | |
6414 | ||
6415 | #endif | |
6416 | ||
6417 | GEN_TM_PRIV_NOOP(treclaim); | |
6418 | GEN_TM_PRIV_NOOP(trechkpt); | |
6419 | ||
15848410 BH |
6420 | #include "translate/fp-impl.inc.c" |
6421 | ||
6422 | #include "translate/vmx-impl.inc.c" | |
6423 | ||
6424 | #include "translate/vsx-impl.inc.c" | |
6425 | ||
6426 | #include "translate/dfp-impl.inc.c" | |
6427 | ||
6428 | #include "translate/spe-impl.inc.c" | |
6429 | ||
5cb091a4 ND |
6430 | /* Handles lfdp, lxsd, lxssp */ |
6431 | static void gen_dform39(DisasContext *ctx) | |
6432 | { | |
6433 | switch (ctx->opcode & 0x3) { | |
6434 | case 0: /* lfdp */ | |
6435 | if (ctx->insns_flags2 & PPC2_ISA205) { | |
6436 | return gen_lfdp(ctx); | |
6437 | } | |
6438 | break; | |
6439 | case 2: /* lxsd */ | |
6440 | if (ctx->insns_flags2 & PPC2_ISA300) { | |
6441 | return gen_lxsd(ctx); | |
6442 | } | |
6443 | break; | |
6444 | case 3: /* lxssp */ | |
6445 | if (ctx->insns_flags2 & PPC2_ISA300) { | |
6446 | return gen_lxssp(ctx); | |
6447 | } | |
6448 | break; | |
6449 | } | |
6450 | return gen_invalid(ctx); | |
6451 | } | |
6452 | ||
d59ba583 | 6453 | /* handles stfdp, lxv, stxsd, stxssp lxvx */ |
e3001664 ND |
6454 | static void gen_dform3D(DisasContext *ctx) |
6455 | { | |
6456 | if ((ctx->opcode & 3) == 1) { /* DQ-FORM */ | |
6457 | switch (ctx->opcode & 0x7) { | |
6458 | case 1: /* lxv */ | |
d59ba583 ND |
6459 | if (ctx->insns_flags2 & PPC2_ISA300) { |
6460 | return gen_lxv(ctx); | |
6461 | } | |
e3001664 ND |
6462 | break; |
6463 | case 5: /* stxv */ | |
d59ba583 ND |
6464 | if (ctx->insns_flags2 & PPC2_ISA300) { |
6465 | return gen_stxv(ctx); | |
6466 | } | |
e3001664 ND |
6467 | break; |
6468 | } | |
6469 | } else { /* DS-FORM */ | |
6470 | switch (ctx->opcode & 0x3) { | |
6471 | case 0: /* stfdp */ | |
6472 | if (ctx->insns_flags2 & PPC2_ISA205) { | |
6473 | return gen_stfdp(ctx); | |
6474 | } | |
6475 | break; | |
6476 | case 2: /* stxsd */ | |
6477 | if (ctx->insns_flags2 & PPC2_ISA300) { | |
6478 | return gen_stxsd(ctx); | |
6479 | } | |
6480 | break; | |
6481 | case 3: /* stxssp */ | |
6482 | if (ctx->insns_flags2 & PPC2_ISA300) { | |
6483 | return gen_stxssp(ctx); | |
6484 | } | |
6485 | break; | |
6486 | } | |
6487 | } | |
6488 | return gen_invalid(ctx); | |
6489 | } | |
6490 | ||
c227f099 | 6491 | static opcode_t opcodes[] = { |
5c55ff99 BS |
6492 | GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), |
6493 | GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), | |
6494 | GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), | |
4aaefd93 | 6495 | GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER), |
5c55ff99 | 6496 | GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), |
082ce330 ND |
6497 | #if defined(TARGET_PPC64) |
6498 | GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), | |
6499 | #endif | |
fcfda20f | 6500 | GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), |
f2442ef9 | 6501 | GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), |
5c55ff99 BS |
6502 | GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), |
6503 | GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6504 | GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6505 | GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6506 | GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
c5b2b9ce | 6507 | GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), |
5c55ff99 BS |
6508 | GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), |
6509 | GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), | |
6510 | GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), | |
6511 | GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), | |
6512 | GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6513 | #if defined(TARGET_PPC64) | |
6514 | GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), | |
6515 | #endif | |
6516 | GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), | |
6517 | GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), | |
6518 | GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6519 | GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6520 | GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6521 | GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), | |
b35344e4 | 6522 | GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), |
80b8c1ee | 6523 | GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), |
b8b4576e | 6524 | GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), |
80b8c1ee | 6525 | GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), |
5c55ff99 BS |
6526 | GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), |
6527 | GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), | |
6528 | GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6529 | GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6530 | GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6531 | GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6ab39b1b | 6532 | GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), |
eaabeef2 | 6533 | GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), |
725bcec2 | 6534 | GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), |
5c55ff99 | 6535 | #if defined(TARGET_PPC64) |
eaabeef2 | 6536 | GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), |
5c55ff99 | 6537 | GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), |
e91d95b2 | 6538 | GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), |
fec5c62a | 6539 | GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), |
725bcec2 | 6540 | GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), |
86ba37ed | 6541 | GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), |
5c55ff99 BS |
6542 | #endif |
6543 | GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6544 | GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6545 | GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6546 | GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), | |
6547 | GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), | |
6548 | GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), | |
6549 | GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), | |
6550 | #if defined(TARGET_PPC64) | |
6551 | GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), | |
6552 | GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), | |
6553 | GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), | |
6554 | GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), | |
6555 | GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), | |
787bbe37 ND |
6556 | GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, |
6557 | PPC_NONE, PPC2_ISA300), | |
6558 | GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, | |
6559 | PPC_NONE, PPC2_ISA300), | |
5c55ff99 | 6560 | #endif |
5c55ff99 BS |
6561 | #if defined(TARGET_PPC64) |
6562 | GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
6563 | GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), | |
6564 | GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
6565 | #endif | |
5cb091a4 ND |
6566 | /* handles lfdp, lxsd, lxssp */ |
6567 | GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), | |
d59ba583 | 6568 | /* handles stfdp, lxv, stxsd, stxssp, stxv */ |
e3001664 | 6569 | GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), |
5c55ff99 BS |
6570 | GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
6571 | GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6572 | GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), | |
6573 | GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), | |
6574 | GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), | |
6575 | GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), | |
c8fd8373 | 6576 | GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), |
5c55ff99 | 6577 | GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), |
5c77a786 TM |
6578 | GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), |
6579 | GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), | |
f844c817 | 6580 | GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), |
a68a6146 | 6581 | GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), |
a3401188 | 6582 | GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), |
587c51f7 TM |
6583 | GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), |
6584 | GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), | |
5c55ff99 BS |
6585 | GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), |
6586 | #if defined(TARGET_PPC64) | |
a68a6146 | 6587 | GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), |
a3401188 | 6588 | GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), |
f844c817 | 6589 | GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), |
9c294d5a | 6590 | GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), |
5c55ff99 | 6591 | GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), |
27b95bfe | 6592 | GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), |
5c55ff99 BS |
6593 | #endif |
6594 | GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), | |
6595 | GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), | |
c09cec68 | 6596 | GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300), |
5c55ff99 BS |
6597 | GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), |
6598 | GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
6599 | GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), | |
6600 | GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), | |
4aaefd93 | 6601 | GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), |
5c55ff99 BS |
6602 | GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), |
6603 | GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), | |
6604 | #if defined(TARGET_PPC64) | |
6605 | GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), | |
cdee0e72 | 6606 | GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), |
7778a575 BH |
6607 | GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), |
6608 | GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), | |
6609 | GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), | |
6610 | GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), | |
5c55ff99 BS |
6611 | GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), |
6612 | #endif | |
6613 | GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW), | |
6614 | GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), | |
6615 | GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
6616 | #if defined(TARGET_PPC64) | |
6617 | GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), | |
6618 | GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
6619 | #endif | |
6620 | GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), | |
6621 | GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), | |
6622 | GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), | |
6623 | GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), | |
6624 | GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), | |
6625 | GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), | |
6626 | #if defined(TARGET_PPC64) | |
6627 | GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), | |
dc2ee038 | 6628 | GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), |
b63d0434 | 6629 | GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), |
5c55ff99 | 6630 | #endif |
5e31867f | 6631 | GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), |
4248b336 | 6632 | GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), |
5c55ff99 BS |
6633 | GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), |
6634 | GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), | |
6635 | GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), | |
3f34cf91 CLG |
6636 | GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), |
6637 | GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), | |
4d09d529 | 6638 | GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), |
8e33944f | 6639 | GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), |
5c55ff99 | 6640 | GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), |
99d45f8f | 6641 | GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), |
5c55ff99 BS |
6642 | GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), |
6643 | GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), | |
6644 | GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), | |
6645 | GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), | |
6646 | GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), | |
6647 | GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), | |
6648 | GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), | |
6649 | #if defined(TARGET_PPC64) | |
6650 | GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), | |
6651 | GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, | |
6652 | PPC_SEGMENT_64B), | |
6653 | GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), | |
6654 | GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, | |
6655 | PPC_SEGMENT_64B), | |
efdef95f DG |
6656 | GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), |
6657 | GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), | |
6658 | GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), | |
c76c22d5 | 6659 | GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), |
5c55ff99 BS |
6660 | #endif |
6661 | GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), | |
f9ef0527 BH |
6662 | /* XXX Those instructions will need to be handled differently for |
6663 | * different ISA versions */ | |
6664 | GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), | |
6665 | GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), | |
c8830502 SJS |
6666 | GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300), |
6667 | GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300), | |
5c55ff99 BS |
6668 | GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), |
6669 | #if defined(TARGET_PPC64) | |
2f9254d9 | 6670 | GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), |
5c55ff99 | 6671 | GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), |
a63f1dfc | 6672 | GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300), |
62d897ca | 6673 | GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300), |
5c55ff99 BS |
6674 | #endif |
6675 | GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), | |
6676 | GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), | |
6677 | GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), | |
6678 | GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), | |
6679 | GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), | |
6680 | GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), | |
6681 | GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), | |
6682 | GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), | |
6683 | GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), | |
6684 | GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), | |
6685 | GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), | |
6686 | GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), | |
6687 | GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), | |
6688 | GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), | |
6689 | GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), | |
6690 | GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), | |
6691 | GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), | |
6692 | GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), | |
6693 | GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), | |
6694 | GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), | |
6695 | GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), | |
6696 | GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), | |
6697 | GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), | |
6698 | GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), | |
6699 | GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), | |
6700 | GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), | |
6701 | GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), | |
6702 | GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), | |
6703 | GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), | |
6704 | GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), | |
6705 | GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), | |
6706 | GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), | |
6707 | GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), | |
6708 | GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), | |
6709 | GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), | |
6710 | GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), | |
6711 | GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), | |
6712 | GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), | |
6713 | GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), | |
6714 | GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), | |
6715 | GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), | |
6716 | GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), | |
6717 | GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), | |
6718 | GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), | |
6719 | GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), | |
6720 | GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), | |
6721 | GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), | |
6722 | GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), | |
6723 | GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), | |
6724 | GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
6725 | GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
6726 | GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), | |
6727 | GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), | |
6728 | GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
6729 | GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
6730 | GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), | |
6731 | GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), | |
6732 | GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), | |
6733 | GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), | |
6734 | GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), | |
6735 | GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), | |
6736 | GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), | |
6737 | GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), | |
6738 | GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), | |
6739 | GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), | |
6740 | GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), | |
6741 | GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), | |
6742 | GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), | |
6743 | GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), | |
6744 | GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), | |
6745 | GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), | |
01662f3e | 6746 | GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), |
5c55ff99 BS |
6747 | GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), |
6748 | GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), | |
6749 | GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), | |
6750 | GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), | |
6751 | GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), | |
6752 | GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), | |
6753 | GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), | |
6754 | GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), | |
01662f3e AG |
6755 | GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, |
6756 | PPC_NONE, PPC2_BOOKE206), | |
6757 | GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, | |
6758 | PPC_NONE, PPC2_BOOKE206), | |
6759 | GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, | |
6760 | PPC_NONE, PPC2_BOOKE206), | |
6761 | GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, | |
6762 | PPC_NONE, PPC2_BOOKE206), | |
6d3db821 AG |
6763 | GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, |
6764 | PPC_NONE, PPC2_BOOKE206), | |
d5d11a39 AG |
6765 | GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, |
6766 | PPC_NONE, PPC2_PRCNTL), | |
9e0b5cb1 AG |
6767 | GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, |
6768 | PPC_NONE, PPC2_PRCNTL), | |
7af1e7b0 CLG |
6769 | GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000, |
6770 | PPC_NONE, PPC2_PRCNTL), | |
5c55ff99 | 6771 | GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), |
fbe73008 | 6772 | GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), |
5c55ff99 | 6773 | GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), |
01662f3e AG |
6774 | GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, |
6775 | PPC_BOOKE, PPC2_BOOKE206), | |
dcb2b9e1 | 6776 | GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE), |
01662f3e AG |
6777 | GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, |
6778 | PPC_BOOKE, PPC2_BOOKE206), | |
0c8d8c8b BZ |
6779 | GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, |
6780 | PPC_440_SPEC), | |
5c55ff99 BS |
6781 | GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), |
6782 | GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), | |
6783 | GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), | |
6784 | GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), | |
5c55ff99 | 6785 | GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), |
aeeb044c | 6786 | #if defined(TARGET_PPC64) |
5f29cc82 ND |
6787 | GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, |
6788 | PPC2_ISA300), | |
aeeb044c ND |
6789 | GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), |
6790 | #endif | |
5c55ff99 BS |
6791 | |
6792 | #undef GEN_INT_ARITH_ADD | |
6793 | #undef GEN_INT_ARITH_ADD_CONST | |
6794 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ | |
6795 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), | |
6796 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ | |
6797 | add_ca, compute_ca, compute_ov) \ | |
6798 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), | |
6799 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) | |
6800 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) | |
6801 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) | |
6802 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) | |
6803 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) | |
6804 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) | |
6805 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) | |
6806 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) | |
6807 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) | |
6808 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) | |
6809 | ||
6810 | #undef GEN_INT_ARITH_DIVW | |
6811 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ | |
6812 | GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) | |
6813 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), | |
6814 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), | |
6815 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), | |
6816 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), | |
a98eb9e9 TM |
6817 | GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), |
6818 | GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
6a4fda33 TM |
6819 | GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), |
6820 | GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
af2c6620 ND |
6821 | GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), |
6822 | GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), | |
5c55ff99 BS |
6823 | |
6824 | #if defined(TARGET_PPC64) | |
6825 | #undef GEN_INT_ARITH_DIVD | |
6826 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ | |
6827 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) | |
6828 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), | |
6829 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), | |
6830 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), | |
6831 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), | |
6832 | ||
98d1eb27 TM |
6833 | GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), |
6834 | GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
e44259b6 TM |
6835 | GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), |
6836 | GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
063cf14f ND |
6837 | GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), |
6838 | GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), | |
98d1eb27 | 6839 | |
5c55ff99 BS |
6840 | #undef GEN_INT_ARITH_MUL_HELPER |
6841 | #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ | |
6842 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) | |
6843 | GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), | |
6844 | GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), | |
6845 | GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), | |
6846 | #endif | |
6847 | ||
6848 | #undef GEN_INT_ARITH_SUBF | |
6849 | #undef GEN_INT_ARITH_SUBF_CONST | |
6850 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ | |
6851 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), | |
6852 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ | |
6853 | add_ca, compute_ca, compute_ov) \ | |
6854 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), | |
6855 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) | |
6856 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) | |
6857 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) | |
6858 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) | |
6859 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) | |
6860 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) | |
6861 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) | |
6862 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) | |
6863 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) | |
6864 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) | |
6865 | ||
6866 | #undef GEN_LOGICAL1 | |
6867 | #undef GEN_LOGICAL2 | |
6868 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ | |
6869 | GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) | |
6870 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ | |
6871 | GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) | |
6872 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), | |
6873 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), | |
6874 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), | |
6875 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), | |
6876 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), | |
6877 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), | |
6878 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), | |
6879 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), | |
6880 | #if defined(TARGET_PPC64) | |
6881 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), | |
6882 | #endif | |
6883 | ||
6884 | #if defined(TARGET_PPC64) | |
6885 | #undef GEN_PPC64_R2 | |
6886 | #undef GEN_PPC64_R4 | |
6887 | #define GEN_PPC64_R2(name, opc1, opc2) \ | |
6888 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ | |
6889 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ | |
6890 | PPC_64B) | |
6891 | #define GEN_PPC64_R4(name, opc1, opc2) \ | |
6892 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ | |
6893 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ | |
6894 | PPC_64B), \ | |
6895 | GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ | |
6896 | PPC_64B), \ | |
6897 | GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ | |
6898 | PPC_64B) | |
6899 | GEN_PPC64_R4(rldicl, 0x1E, 0x00), | |
6900 | GEN_PPC64_R4(rldicr, 0x1E, 0x02), | |
6901 | GEN_PPC64_R4(rldic, 0x1E, 0x04), | |
6902 | GEN_PPC64_R2(rldcl, 0x1E, 0x08), | |
6903 | GEN_PPC64_R2(rldcr, 0x1E, 0x09), | |
6904 | GEN_PPC64_R4(rldimi, 0x1E, 0x06), | |
6905 | #endif | |
6906 | ||
5c55ff99 BS |
6907 | #undef GEN_LD |
6908 | #undef GEN_LDU | |
6909 | #undef GEN_LDUX | |
cd6e9320 | 6910 | #undef GEN_LDX_E |
5c55ff99 BS |
6911 | #undef GEN_LDS |
6912 | #define GEN_LD(name, ldop, opc, type) \ | |
6913 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
6914 | #define GEN_LDU(name, ldop, opc, type) \ | |
6915 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
6916 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \ | |
6917 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), | |
b7815375 | 6918 | #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ |
cd6e9320 | 6919 | GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), |
5c55ff99 BS |
6920 | #define GEN_LDS(name, ldop, op, type) \ |
6921 | GEN_LD(name, ldop, op | 0x20, type) \ | |
6922 | GEN_LDU(name, ldop, op | 0x21, type) \ | |
6923 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ | |
6924 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) | |
6925 | ||
6926 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) | |
6927 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) | |
6928 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) | |
6929 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) | |
6930 | #if defined(TARGET_PPC64) | |
6931 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) | |
6932 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) | |
4f364fe7 ND |
6933 | GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B) |
6934 | GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B) | |
ff5f3981 | 6935 | GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) |
b7815375 BH |
6936 | |
6937 | /* HV/P7 and later only */ | |
4f364fe7 | 6938 | GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) |
b7815375 BH |
6939 | GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) |
6940 | GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) | |
6941 | GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) | |
5c55ff99 BS |
6942 | #endif |
6943 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) | |
6944 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) | |
6945 | ||
6946 | #undef GEN_ST | |
6947 | #undef GEN_STU | |
6948 | #undef GEN_STUX | |
cd6e9320 | 6949 | #undef GEN_STX_E |
5c55ff99 BS |
6950 | #undef GEN_STS |
6951 | #define GEN_ST(name, stop, opc, type) \ | |
6952 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
6953 | #define GEN_STU(name, stop, opc, type) \ | |
6954 | GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
6955 | #define GEN_STUX(name, stop, opc2, opc3, type) \ | |
6956 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), | |
b7815375 | 6957 | #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ |
cd6e9320 | 6958 | GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), |
5c55ff99 BS |
6959 | #define GEN_STS(name, stop, op, type) \ |
6960 | GEN_ST(name, stop, op | 0x20, type) \ | |
6961 | GEN_STU(name, stop, op | 0x21, type) \ | |
6962 | GEN_STUX(name, stop, 0x17, op | 0x01, type) \ | |
6963 | GEN_STX(name, stop, 0x17, op | 0x00, type) | |
6964 | ||
6965 | GEN_STS(stb, st8, 0x06, PPC_INTEGER) | |
6966 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER) | |
6967 | GEN_STS(stw, st32, 0x04, PPC_INTEGER) | |
6968 | #if defined(TARGET_PPC64) | |
2468f23d ND |
6969 | GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B) |
6970 | GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B) | |
804108aa | 6971 | GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) |
2468f23d | 6972 | GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) |
b7815375 BH |
6973 | GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) |
6974 | GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) | |
6975 | GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) | |
5c55ff99 BS |
6976 | #endif |
6977 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) | |
6978 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) | |
6979 | ||
5c55ff99 BS |
6980 | #undef GEN_CRLOGIC |
6981 | #define GEN_CRLOGIC(name, tcg_op, opc) \ | |
6982 | GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) | |
6983 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), | |
6984 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), | |
6985 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), | |
6986 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), | |
6987 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), | |
6988 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), | |
6989 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), | |
6990 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), | |
6991 | ||
6992 | #undef GEN_MAC_HANDLER | |
6993 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ | |
6994 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) | |
6995 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05), | |
6996 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), | |
6997 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07), | |
6998 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), | |
6999 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), | |
7000 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), | |
7001 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), | |
7002 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), | |
7003 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01), | |
7004 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), | |
7005 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03), | |
7006 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), | |
7007 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), | |
7008 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), | |
7009 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), | |
7010 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), | |
7011 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), | |
7012 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), | |
7013 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), | |
7014 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), | |
7015 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), | |
7016 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), | |
7017 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), | |
7018 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), | |
7019 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), | |
7020 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), | |
7021 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), | |
7022 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), | |
7023 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), | |
7024 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), | |
7025 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), | |
7026 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), | |
7027 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), | |
7028 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), | |
7029 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), | |
7030 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), | |
7031 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05), | |
7032 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), | |
7033 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), | |
7034 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), | |
7035 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), | |
7036 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), | |
7037 | ||
0ff93d11 TM |
7038 | GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ |
7039 | PPC_NONE, PPC2_TM), | |
56a84615 TM |
7040 | GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ |
7041 | PPC_NONE, PPC2_TM), | |
7042 | GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ | |
7043 | PPC_NONE, PPC2_TM), | |
7044 | GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ | |
7045 | PPC_NONE, PPC2_TM), | |
7046 | GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ | |
7047 | PPC_NONE, PPC2_TM), | |
7048 | GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ | |
7049 | PPC_NONE, PPC2_TM), | |
7050 | GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ | |
7051 | PPC_NONE, PPC2_TM), | |
7052 | GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ | |
7053 | PPC_NONE, PPC2_TM), | |
aeedd582 TM |
7054 | GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ |
7055 | PPC_NONE, PPC2_TM), | |
f83c2378 TM |
7056 | GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ |
7057 | PPC_NONE, PPC2_TM), | |
7058 | GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ | |
7059 | PPC_NONE, PPC2_TM), | |
15848410 BH |
7060 | |
7061 | #include "translate/fp-ops.inc.c" | |
7062 | ||
7063 | #include "translate/vmx-ops.inc.c" | |
7064 | ||
7065 | #include "translate/vsx-ops.inc.c" | |
7066 | ||
7067 | #include "translate/dfp-ops.inc.c" | |
7068 | ||
7069 | #include "translate/spe-ops.inc.c" | |
5c55ff99 BS |
7070 | }; |
7071 | ||
0411a972 | 7072 | #include "helper_regs.h" |
5b27a92d | 7073 | #include "translate_init.inc.c" |
79aceca5 | 7074 | |
9a64fbe4 | 7075 | /*****************************************************************************/ |
3fc6c082 | 7076 | /* Misc PowerPC helpers */ |
878096ee AF |
7077 | void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, |
7078 | int flags) | |
79aceca5 | 7079 | { |
3fc6c082 FB |
7080 | #define RGPL 4 |
7081 | #define RFPL 4 | |
3fc6c082 | 7082 | |
878096ee AF |
7083 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
7084 | CPUPPCState *env = &cpu->env; | |
79aceca5 FB |
7085 | int i; |
7086 | ||
90e189ec | 7087 | cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " |
21e5d28a TG |
7088 | TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", |
7089 | env->nip, env->lr, env->ctr, cpu_read_xer(env), | |
7090 | cs->cpu_index); | |
90e189ec | 7091 | cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " |
9fb04491 BH |
7092 | TARGET_FMT_lx " iidx %d didx %d\n", |
7093 | env->msr, env->spr[SPR_HID0], | |
7094 | env->hflags, env->immu_idx, env->dmmu_idx); | |
d9bce9d9 | 7095 | #if !defined(NO_TIMER_DUMP) |
9a78eead | 7096 | cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 |
76a66253 | 7097 | #if !defined(CONFIG_USER_ONLY) |
9a78eead | 7098 | " DECR %08" PRIu32 |
76a66253 JM |
7099 | #endif |
7100 | "\n", | |
077fc206 | 7101 | cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) |
76a66253 JM |
7102 | #if !defined(CONFIG_USER_ONLY) |
7103 | , cpu_ppc_load_decr(env) | |
7104 | #endif | |
7105 | ); | |
077fc206 | 7106 | #endif |
76a66253 | 7107 | for (i = 0; i < 32; i++) { |
3fc6c082 FB |
7108 | if ((i & (RGPL - 1)) == 0) |
7109 | cpu_fprintf(f, "GPR%02d", i); | |
b11ebf64 | 7110 | cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); |
3fc6c082 | 7111 | if ((i & (RGPL - 1)) == (RGPL - 1)) |
7fe48483 | 7112 | cpu_fprintf(f, "\n"); |
76a66253 | 7113 | } |
3fc6c082 | 7114 | cpu_fprintf(f, "CR "); |
76a66253 | 7115 | for (i = 0; i < 8; i++) |
7fe48483 FB |
7116 | cpu_fprintf(f, "%01x", env->crf[i]); |
7117 | cpu_fprintf(f, " ["); | |
76a66253 JM |
7118 | for (i = 0; i < 8; i++) { |
7119 | char a = '-'; | |
7120 | if (env->crf[i] & 0x08) | |
7121 | a = 'L'; | |
7122 | else if (env->crf[i] & 0x04) | |
7123 | a = 'G'; | |
7124 | else if (env->crf[i] & 0x02) | |
7125 | a = 'E'; | |
7fe48483 | 7126 | cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); |
76a66253 | 7127 | } |
90e189ec BS |
7128 | cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", |
7129 | env->reserve_addr); | |
685f1ce2 RH |
7130 | |
7131 | if (flags & CPU_DUMP_FPU) { | |
7132 | for (i = 0; i < 32; i++) { | |
7133 | if ((i & (RFPL - 1)) == 0) { | |
7134 | cpu_fprintf(f, "FPR%02d", i); | |
7135 | } | |
7136 | cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i])); | |
7137 | if ((i & (RFPL - 1)) == (RFPL - 1)) { | |
7138 | cpu_fprintf(f, "\n"); | |
7139 | } | |
7140 | } | |
7141 | cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); | |
79aceca5 | 7142 | } |
685f1ce2 | 7143 | |
f2e63a42 | 7144 | #if !defined(CONFIG_USER_ONLY) |
90dc8812 SW |
7145 | cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx |
7146 | " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", | |
7147 | env->spr[SPR_SRR0], env->spr[SPR_SRR1], | |
7148 | env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); | |
7149 | ||
7150 | cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx | |
7151 | " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", | |
7152 | env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], | |
7153 | env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); | |
7154 | ||
7155 | cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx | |
7156 | " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", | |
7157 | env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], | |
7158 | env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); | |
7159 | ||
f2b70fde BH |
7160 | #if defined(TARGET_PPC64) |
7161 | if (env->excp_model == POWERPC_EXCP_POWER7 || | |
7162 | env->excp_model == POWERPC_EXCP_POWER8) { | |
7163 | cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", | |
7164 | env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); | |
7165 | } | |
7166 | #endif | |
90dc8812 SW |
7167 | if (env->excp_model == POWERPC_EXCP_BOOKE) { |
7168 | cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx | |
7169 | " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", | |
7170 | env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], | |
7171 | env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); | |
7172 | ||
7173 | cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx | |
7174 | " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", | |
7175 | env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], | |
7176 | env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); | |
7177 | ||
7178 | cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx | |
7179 | " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", | |
7180 | env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], | |
7181 | env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); | |
7182 | ||
7183 | cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx | |
7184 | " EPR " TARGET_FMT_lx "\n", | |
7185 | env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], | |
7186 | env->spr[SPR_BOOKE_EPR]); | |
7187 | ||
7188 | /* FSL-specific */ | |
7189 | cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx | |
7190 | " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", | |
7191 | env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], | |
7192 | env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); | |
7193 | ||
7194 | /* | |
7195 | * IVORs are left out as they are large and do not change often -- | |
7196 | * they can be read with "p $ivor0", "p $ivor1", etc. | |
7197 | */ | |
7198 | } | |
7199 | ||
697ab892 DG |
7200 | #if defined(TARGET_PPC64) |
7201 | if (env->flags & POWERPC_FLAG_CFAR) { | |
7202 | cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); | |
7203 | } | |
7204 | #endif | |
7205 | ||
d801a61e SJS |
7206 | if (env->spr_cb[SPR_LPCR].name) |
7207 | cpu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); | |
7208 | ||
0941d728 | 7209 | switch (env->mmu_model) { |
90dc8812 SW |
7210 | case POWERPC_MMU_32B: |
7211 | case POWERPC_MMU_601: | |
7212 | case POWERPC_MMU_SOFT_6xx: | |
7213 | case POWERPC_MMU_SOFT_74xx: | |
7214 | #if defined(TARGET_PPC64) | |
0941d728 DG |
7215 | case POWERPC_MMU_64B: |
7216 | case POWERPC_MMU_2_03: | |
7217 | case POWERPC_MMU_2_06: | |
7218 | case POWERPC_MMU_2_07: | |
7219 | case POWERPC_MMU_3_00: | |
90dc8812 | 7220 | #endif |
4f4f28ff SJS |
7221 | if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ |
7222 | cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); | |
7223 | } | |
4a7518e0 CLG |
7224 | if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ |
7225 | cpu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); | |
7226 | } | |
4f4f28ff | 7227 | cpu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", |
ca480de6 | 7228 | env->spr[SPR_DAR], env->spr[SPR_DSISR]); |
90dc8812 | 7229 | break; |
01662f3e | 7230 | case POWERPC_MMU_BOOKE206: |
90dc8812 SW |
7231 | cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx |
7232 | " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", | |
7233 | env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], | |
7234 | env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); | |
7235 | ||
7236 | cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx | |
7237 | " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", | |
7238 | env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], | |
7239 | env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); | |
7240 | ||
7241 | cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx | |
7242 | " TLB1CFG " TARGET_FMT_lx "\n", | |
7243 | env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], | |
7244 | env->spr[SPR_BOOKE_TLB1CFG]); | |
7245 | break; | |
7246 | default: | |
7247 | break; | |
7248 | } | |
f2e63a42 | 7249 | #endif |
79aceca5 | 7250 | |
3fc6c082 FB |
7251 | #undef RGPL |
7252 | #undef RFPL | |
79aceca5 FB |
7253 | } |
7254 | ||
878096ee AF |
7255 | void ppc_cpu_dump_statistics(CPUState *cs, FILE*f, |
7256 | fprintf_function cpu_fprintf, int flags) | |
76a66253 JM |
7257 | { |
7258 | #if defined(DO_PPC_STATISTICS) | |
878096ee | 7259 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
c227f099 | 7260 | opc_handler_t **t1, **t2, **t3, *handler; |
76a66253 JM |
7261 | int op1, op2, op3; |
7262 | ||
878096ee | 7263 | t1 = cpu->env.opcodes; |
76a66253 JM |
7264 | for (op1 = 0; op1 < 64; op1++) { |
7265 | handler = t1[op1]; | |
7266 | if (is_indirect_opcode(handler)) { | |
7267 | t2 = ind_table(handler); | |
7268 | for (op2 = 0; op2 < 32; op2++) { | |
7269 | handler = t2[op2]; | |
7270 | if (is_indirect_opcode(handler)) { | |
7271 | t3 = ind_table(handler); | |
7272 | for (op3 = 0; op3 < 32; op3++) { | |
7273 | handler = t3[op3]; | |
7274 | if (handler->count == 0) | |
7275 | continue; | |
7276 | cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: " | |
0bfcd599 | 7277 | "%016" PRIx64 " %" PRId64 "\n", |
76a66253 JM |
7278 | op1, op2, op3, op1, (op3 << 5) | op2, |
7279 | handler->oname, | |
7280 | handler->count, handler->count); | |
7281 | } | |
7282 | } else { | |
7283 | if (handler->count == 0) | |
7284 | continue; | |
7285 | cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: " | |
0bfcd599 | 7286 | "%016" PRIx64 " %" PRId64 "\n", |
76a66253 JM |
7287 | op1, op2, op1, op2, handler->oname, |
7288 | handler->count, handler->count); | |
7289 | } | |
7290 | } | |
7291 | } else { | |
7292 | if (handler->count == 0) | |
7293 | continue; | |
0bfcd599 BS |
7294 | cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64 |
7295 | " %" PRId64 "\n", | |
76a66253 JM |
7296 | op1, op1, handler->oname, |
7297 | handler->count, handler->count); | |
7298 | } | |
7299 | } | |
7300 | #endif | |
7301 | } | |
7302 | ||
b542683d | 7303 | static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) |
79aceca5 | 7304 | { |
b0c2d521 | 7305 | DisasContext *ctx = container_of(dcbase, DisasContext, base); |
9c489ea6 | 7306 | CPUPPCState *env = cs->env_ptr; |
b0c2d521 EC |
7307 | int bound; |
7308 | ||
7309 | ctx->exception = POWERPC_EXCP_NONE; | |
7310 | ctx->spr_cb = env->spr_cb; | |
7311 | ctx->pr = msr_pr; | |
7312 | ctx->mem_idx = env->dmmu_idx; | |
7313 | ctx->dr = msr_dr; | |
932ccbdd | 7314 | #if !defined(CONFIG_USER_ONLY) |
b0c2d521 | 7315 | ctx->hv = msr_hv || !env->has_hv_mode; |
932ccbdd | 7316 | #endif |
b0c2d521 EC |
7317 | ctx->insns_flags = env->insns_flags; |
7318 | ctx->insns_flags2 = env->insns_flags2; | |
7319 | ctx->access_type = -1; | |
7320 | ctx->need_access_type = !(env->mmu_model & POWERPC_MMU_64B); | |
7321 | ctx->le_mode = !!(env->hflags & (1 << MSR_LE)); | |
7322 | ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; | |
d9bce9d9 | 7323 | #if defined(TARGET_PPC64) |
b0c2d521 EC |
7324 | ctx->sf_mode = msr_is_64bit(env, env->msr); |
7325 | ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); | |
9a64fbe4 | 7326 | #endif |
e69ba2b4 DG |
7327 | ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B |
7328 | || env->mmu_model == POWERPC_MMU_601 | |
7329 | || (env->mmu_model & POWERPC_MMU_64B); | |
c5a8d8f3 | 7330 | |
b0c2d521 | 7331 | ctx->fpu_enabled = !!msr_fp; |
a9d9eb8f | 7332 | if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) |
b0c2d521 | 7333 | ctx->spe_enabled = !!msr_spe; |
d26bfc9a | 7334 | else |
b0c2d521 | 7335 | ctx->spe_enabled = false; |
a9d9eb8f | 7336 | if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) |
b0c2d521 | 7337 | ctx->altivec_enabled = !!msr_vr; |
a9d9eb8f | 7338 | else |
b0c2d521 | 7339 | ctx->altivec_enabled = false; |
1f29871c | 7340 | if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) { |
b0c2d521 | 7341 | ctx->vsx_enabled = !!msr_vsx; |
1f29871c | 7342 | } else { |
b0c2d521 | 7343 | ctx->vsx_enabled = false; |
1f29871c | 7344 | } |
69d1a937 TM |
7345 | #if defined(TARGET_PPC64) |
7346 | if ((env->flags & POWERPC_FLAG_TM) && msr_tm) { | |
b0c2d521 | 7347 | ctx->tm_enabled = !!msr_tm; |
69d1a937 | 7348 | } else { |
b0c2d521 | 7349 | ctx->tm_enabled = false; |
69d1a937 TM |
7350 | } |
7351 | #endif | |
b0c2d521 | 7352 | ctx->gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE); |
d26bfc9a | 7353 | if ((env->flags & POWERPC_FLAG_SE) && msr_se) |
b0c2d521 | 7354 | ctx->singlestep_enabled = CPU_SINGLE_STEP; |
d26bfc9a | 7355 | else |
b0c2d521 | 7356 | ctx->singlestep_enabled = 0; |
d26bfc9a | 7357 | if ((env->flags & POWERPC_FLAG_BE) && msr_be) |
b0c2d521 EC |
7358 | ctx->singlestep_enabled |= CPU_BRANCH_STEP; |
7359 | if (unlikely(ctx->base.singlestep_enabled)) { | |
7360 | ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP; | |
ed2803da | 7361 | } |
3fc6c082 | 7362 | #if defined (DO_SINGLE_STEP) && 0 |
9a64fbe4 FB |
7363 | /* Single step trace mode */ |
7364 | msr_se = 1; | |
7365 | #endif | |
b933066a | 7366 | |
b0c2d521 | 7367 | bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; |
b542683d | 7368 | ctx->base.max_insns = MIN(ctx->base.max_insns, bound); |
b0c2d521 EC |
7369 | } |
7370 | ||
7371 | static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) | |
7372 | { | |
7373 | } | |
7374 | ||
7375 | static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) | |
7376 | { | |
7377 | tcg_gen_insn_start(dcbase->pc_next); | |
7378 | } | |
7379 | ||
7380 | static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, | |
7381 | const CPUBreakpoint *bp) | |
7382 | { | |
7383 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
7384 | ||
7385 | gen_debug_exception(ctx); | |
7386 | /* The address covered by the breakpoint must be included in | |
7387 | [tb->pc, tb->pc + tb->size) in order to for it to be | |
7388 | properly cleared -- thus we increment the PC here so that | |
7389 | the logic setting tb->size below does the right thing. */ | |
7390 | ctx->base.pc_next += 4; | |
7391 | return true; | |
7392 | } | |
7393 | ||
7394 | static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) | |
7395 | { | |
7396 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
7397 | CPUPPCState *env = cs->env_ptr; | |
7398 | opc_handler_t **table, *handler; | |
7399 | ||
7400 | LOG_DISAS("----------------\n"); | |
7401 | LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", | |
7402 | ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); | |
7403 | ||
7404 | if (unlikely(need_byteswap(ctx))) { | |
7405 | ctx->opcode = bswap32(cpu_ldl_code(env, ctx->base.pc_next)); | |
7406 | } else { | |
7407 | ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next); | |
7408 | } | |
7409 | LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", | |
7410 | ctx->opcode, opc1(ctx->opcode), opc2(ctx->opcode), | |
7411 | opc3(ctx->opcode), opc4(ctx->opcode), | |
7412 | ctx->le_mode ? "little" : "big"); | |
7413 | ctx->base.pc_next += 4; | |
7414 | table = env->opcodes; | |
7415 | handler = table[opc1(ctx->opcode)]; | |
7416 | if (is_indirect_opcode(handler)) { | |
7417 | table = ind_table(handler); | |
7418 | handler = table[opc2(ctx->opcode)]; | |
79aceca5 FB |
7419 | if (is_indirect_opcode(handler)) { |
7420 | table = ind_table(handler); | |
b0c2d521 | 7421 | handler = table[opc3(ctx->opcode)]; |
79aceca5 FB |
7422 | if (is_indirect_opcode(handler)) { |
7423 | table = ind_table(handler); | |
b0c2d521 | 7424 | handler = table[opc4(ctx->opcode)]; |
79aceca5 FB |
7425 | } |
7426 | } | |
b0c2d521 EC |
7427 | } |
7428 | /* Is opcode *REALLY* valid ? */ | |
7429 | if (unlikely(handler->handler == &gen_invalid)) { | |
7430 | qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " | |
7431 | "%02x - %02x - %02x - %02x (%08x) " | |
7432 | TARGET_FMT_lx " %d\n", | |
7433 | opc1(ctx->opcode), opc2(ctx->opcode), | |
7434 | opc3(ctx->opcode), opc4(ctx->opcode), | |
7435 | ctx->opcode, ctx->base.pc_next - 4, (int)msr_ir); | |
7436 | } else { | |
7437 | uint32_t inval; | |
70560da7 | 7438 | |
b0c2d521 EC |
7439 | if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) |
7440 | && Rc(ctx->opcode))) { | |
7441 | inval = handler->inval2; | |
7442 | } else { | |
7443 | inval = handler->inval1; | |
7444 | } | |
70560da7 | 7445 | |
b0c2d521 EC |
7446 | if (unlikely((ctx->opcode & inval) != 0)) { |
7447 | qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " | |
7448 | "%02x - %02x - %02x - %02x (%08x) " | |
7449 | TARGET_FMT_lx "\n", ctx->opcode & inval, | |
7450 | opc1(ctx->opcode), opc2(ctx->opcode), | |
7451 | opc3(ctx->opcode), opc4(ctx->opcode), | |
7452 | ctx->opcode, ctx->base.pc_next - 4); | |
7453 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
7454 | ctx->base.is_jmp = DISAS_NORETURN; | |
7455 | return; | |
79aceca5 | 7456 | } |
b0c2d521 EC |
7457 | } |
7458 | (*(handler->handler))(ctx); | |
76a66253 | 7459 | #if defined(DO_PPC_STATISTICS) |
b0c2d521 | 7460 | handler->count++; |
76a66253 | 7461 | #endif |
b0c2d521 EC |
7462 | /* Check trace mode exceptions */ |
7463 | if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP && | |
7464 | (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) && | |
7465 | ctx->exception != POWERPC_SYSCALL && | |
7466 | ctx->exception != POWERPC_EXCP_TRAP && | |
7467 | ctx->exception != POWERPC_EXCP_BRANCH)) { | |
7468 | gen_exception_nip(ctx, POWERPC_EXCP_TRACE, ctx->base.pc_next); | |
7469 | } | |
7470 | ||
7471 | if (tcg_check_temp_count()) { | |
7472 | qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked " | |
7473 | "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode), | |
7474 | opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode); | |
3fc6c082 | 7475 | } |
b0c2d521 EC |
7476 | |
7477 | ctx->base.is_jmp = ctx->exception == POWERPC_EXCP_NONE ? | |
7478 | DISAS_NEXT : DISAS_NORETURN; | |
7479 | } | |
7480 | ||
7481 | static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) | |
7482 | { | |
7483 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
7484 | ||
7485 | if (ctx->exception == POWERPC_EXCP_NONE) { | |
7486 | gen_goto_tb(ctx, 0, ctx->base.pc_next); | |
7487 | } else if (ctx->exception != POWERPC_EXCP_BRANCH) { | |
7488 | if (unlikely(ctx->base.singlestep_enabled)) { | |
7489 | gen_debug_exception(ctx); | |
8cbcb4fa | 7490 | } |
76a66253 | 7491 | /* Generate the return instruction */ |
07ea28b4 | 7492 | tcg_gen_exit_tb(NULL, 0); |
9a64fbe4 | 7493 | } |
b0c2d521 EC |
7494 | } |
7495 | ||
7496 | static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) | |
7497 | { | |
7498 | qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); | |
7499 | log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); | |
7500 | } | |
0a7df5da | 7501 | |
b0c2d521 EC |
7502 | static const TranslatorOps ppc_tr_ops = { |
7503 | .init_disas_context = ppc_tr_init_disas_context, | |
7504 | .tb_start = ppc_tr_tb_start, | |
7505 | .insn_start = ppc_tr_insn_start, | |
7506 | .breakpoint_check = ppc_tr_breakpoint_check, | |
7507 | .translate_insn = ppc_tr_translate_insn, | |
7508 | .tb_stop = ppc_tr_tb_stop, | |
7509 | .disas_log = ppc_tr_disas_log, | |
7510 | }; | |
4e5e1215 | 7511 | |
b0c2d521 EC |
7512 | void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) |
7513 | { | |
7514 | DisasContext ctx; | |
7515 | ||
7516 | translator_loop(&ppc_tr_ops, &ctx.base, cs, tb); | |
79aceca5 FB |
7517 | } |
7518 | ||
bad729e2 RH |
7519 | void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, |
7520 | target_ulong *data) | |
d2856f1a | 7521 | { |
bad729e2 | 7522 | env->nip = data[0]; |
d2856f1a | 7523 | } |