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ppc/ppc405: Fix timer initialization
[mirror_qemu.git] / target / ppc / translate.c
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79aceca5 1/*
3fc6c082 2 * PowerPC emulation for qemu: main translation routines.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
90dc8812 5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
79aceca5
FB		 6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
6bd039cd 10 * version 2.1 of the License, or (at your option) any later version.
79aceca5
FB		 11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
8167ee88 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
79aceca5 19 */
c6a1c22b 20
0d75590d 21#include "qemu/osdep.h"
79aceca5 22#include "cpu.h"
3e00884f 23#include "internal.h"
76cad711 24#include "disas/disas.h"
63c91552 25#include "exec/exec-all.h"
dcb32f1d
PMD		 26#include "tcg/tcg-op.h"
27#include "tcg/tcg-op-gvec.h"
1de7afc9 28#include "qemu/host-utils.h"
db725815 29#include "qemu/main-loop.h"
f08b6170 30#include "exec/cpu_ldst.h"
79aceca5 31
2ef6175a
RH		 32#include "exec/helper-proto.h"
33#include "exec/helper-gen.h"
a7812ae4 34
b6bac4bc 35#include "exec/translator.h"
508127e2 36#include "exec/log.h"
f34ec0f6 37#include "qemu/atomic128.h"
a829cec3 38#include "spr_tcg.h"
a7e30d84 39
3e770bf7
BL		 40#include "qemu/qemu-print.h"
41#include "qapi/error.h"
a7e30d84 42
8cbcb4fa
AJ		 43#define CPU_SINGLE_STEP 0x1
44#define CPU_BRANCH_STEP 0x2
8cbcb4fa 45
a750fc0b 46/* Include definitions for instructions classes and implementations flags */
efe843d8 47/* #define PPC_DEBUG_DISAS */
79aceca5 48
d12d51d5 49#ifdef PPC_DEBUG_DISAS
93fcfe39 50# define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
d12d51d5
AL		 51#else
52# define LOG_DISAS(...) do { } while (0)
53#endif
a750fc0b
JM		 54/*****************************************************************************/
55/* Code translation helpers */
c53be334 56
f78fb44e 57/* global register indexes */
efe843d8
DG		 58static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */
59 + 10 * 4 + 22 * 5 /* SPE GPRh */
60 + 8 * 5 /* CRF */];
f78fb44e 61static TCGv cpu_gpr[32];
f78fb44e 62static TCGv cpu_gprh[32];
a7812ae4 63static TCGv_i32 cpu_crf[8];
bd568f18 64static TCGv cpu_nip;
6527f6ea 65static TCGv cpu_msr;
cfdcd37a
AJ		 66static TCGv cpu_ctr;
67static TCGv cpu_lr;
697ab892
DG		 68#if defined(TARGET_PPC64)
69static TCGv cpu_cfar;
70#endif
dd09c361 71static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32;
cf360a32 72static TCGv cpu_reserve;
253ce7b2 73static TCGv cpu_reserve_val;
30304420 74static TCGv cpu_fpscr;
a7859e89 75static TCGv_i32 cpu_access_type;
f78fb44e 76
022c62cb 77#include "exec/gen-icount.h"
2e70f6ef
PB		 78
79void ppc_translate_init(void)
80{
f78fb44e 81 int i;
efe843d8 82 char *p;
2dc766da 83 size_t cpu_reg_names_size;
f78fb44e 84
f78fb44e 85 p = cpu_reg_names;
2dc766da 86 cpu_reg_names_size = sizeof(cpu_reg_names);
47e4661c
AJ		 87
88 for (i = 0; i < 8; i++) {
2dc766da 89 snprintf(p, cpu_reg_names_size, "crf%d", i);
e1ccc054 90 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
1328c2bf 91 offsetof(CPUPPCState, crf[i]), p);
47e4661c 92 p += 5;
2dc766da 93 cpu_reg_names_size -= 5;
47e4661c
AJ		 94 }
95
f78fb44e 96 for (i = 0; i < 32; i++) {
2dc766da 97 snprintf(p, cpu_reg_names_size, "r%d", i);
e1ccc054 98 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
1328c2bf 99 offsetof(CPUPPCState, gpr[i]), p);
f78fb44e 100 p += (i < 10) ? 3 : 4;
2dc766da 101 cpu_reg_names_size -= (i < 10) ? 3 : 4;
2dc766da 102 snprintf(p, cpu_reg_names_size, "r%dH", i);
e1ccc054 103 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
13b6a455 104 offsetof(CPUPPCState, gprh[i]), p);
f78fb44e 105 p += (i < 10) ? 4 : 5;
2dc766da 106 cpu_reg_names_size -= (i < 10) ? 4 : 5;
f78fb44e 107 }
f10dc08e 108
e1ccc054 109 cpu_nip = tcg_global_mem_new(cpu_env,
1328c2bf 110 offsetof(CPUPPCState, nip), "nip");
bd568f18 111
e1ccc054 112 cpu_msr = tcg_global_mem_new(cpu_env,
1328c2bf 113 offsetof(CPUPPCState, msr), "msr");
6527f6ea 114
e1ccc054 115 cpu_ctr = tcg_global_mem_new(cpu_env,
1328c2bf 116 offsetof(CPUPPCState, ctr), "ctr");
cfdcd37a 117
e1ccc054 118 cpu_lr = tcg_global_mem_new(cpu_env,
1328c2bf 119 offsetof(CPUPPCState, lr), "lr");
cfdcd37a 120
697ab892 121#if defined(TARGET_PPC64)
e1ccc054 122 cpu_cfar = tcg_global_mem_new(cpu_env,
1328c2bf 123 offsetof(CPUPPCState, cfar), "cfar");
697ab892
DG		 124#endif
125
e1ccc054 126 cpu_xer = tcg_global_mem_new(cpu_env,
1328c2bf 127 offsetof(CPUPPCState, xer), "xer");
e1ccc054 128 cpu_so = tcg_global_mem_new(cpu_env,
da91a00f 129 offsetof(CPUPPCState, so), "SO");
e1ccc054 130 cpu_ov = tcg_global_mem_new(cpu_env,
da91a00f 131 offsetof(CPUPPCState, ov), "OV");
e1ccc054 132 cpu_ca = tcg_global_mem_new(cpu_env,
da91a00f 133 offsetof(CPUPPCState, ca), "CA");
dd09c361
ND		 134 cpu_ov32 = tcg_global_mem_new(cpu_env,
135 offsetof(CPUPPCState, ov32), "OV32");
136 cpu_ca32 = tcg_global_mem_new(cpu_env,
137 offsetof(CPUPPCState, ca32), "CA32");
3d7b417e 138
e1ccc054 139 cpu_reserve = tcg_global_mem_new(cpu_env,
1328c2bf 140 offsetof(CPUPPCState, reserve_addr),
18b21a2f 141 "reserve_addr");
253ce7b2
ND		 142 cpu_reserve_val = tcg_global_mem_new(cpu_env,
143 offsetof(CPUPPCState, reserve_val),
144 "reserve_val");
cf360a32 145
e1ccc054 146 cpu_fpscr = tcg_global_mem_new(cpu_env,
30304420 147 offsetof(CPUPPCState, fpscr), "fpscr");
e1571908 148
e1ccc054 149 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
efe843d8
DG		 150 offsetof(CPUPPCState, access_type),
151 "access_type");
2e70f6ef
PB		 152}
153
79aceca5 154/* internal defines */
69b058c8 155struct DisasContext {
b6bac4bc 156 DisasContextBase base;
2c2bcb1b 157 target_ulong cia; /* current instruction address */
79aceca5 158 uint32_t opcode;
3cc62370 159 /* Routine used to access memory */
5c3ae929 160 bool pr, hv, dr, le_mode;
c5a8d8f3 161 bool lazy_tlb_flush;
5f2a6254 162 bool need_access_type;
3cc62370 163 int mem_idx;
76db3ba4 164 int access_type;
3cc62370 165 /* Translation flags */
14776ab5 166 MemOp default_tcg_memop_mask;
d9bce9d9 167#if defined(TARGET_PPC64)
5c3ae929
BH		 168 bool sf_mode;
169 bool has_cfar;
9a64fbe4 170#endif
5c3ae929
BH		 171 bool fpu_enabled;
172 bool altivec_enabled;
173 bool vsx_enabled;
174 bool spe_enabled;
175 bool tm_enabled;
c6fd28fd 176 bool gtse;
1db3632a 177 bool hr;
f7460df2
DHB		 178 bool mmcr0_pmcc0;
179 bool mmcr0_pmcc1;
46d396bd 180 bool pmu_insn_cnt;
c227f099 181 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
ea4e754f 182 int singlestep_enabled;
0e3bf489 183 uint32_t flags;
7d08d856
AJ		 184 uint64_t insns_flags;
185 uint64_t insns_flags2;
69b058c8 186};
79aceca5 187
a9b5b3d0
RH		 188#define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */
189#define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */
190#define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */
191#define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */
192
e22c357b
DK		 193/* Return true iff byteswap is needed in a scalar memop */
194static inline bool need_byteswap(const DisasContext *ctx)
195{
196#if defined(TARGET_WORDS_BIGENDIAN)
197 return ctx->le_mode;
198#else
199 return !ctx->le_mode;
200#endif
201}
202
79482e5a
RH		 203/* True when active word size < size of target_long. */
204#ifdef TARGET_PPC64
205# define NARROW_MODE(C) (!(C)->sf_mode)
206#else
207# define NARROW_MODE(C) 0
208#endif
209
c227f099 210struct opc_handler_t {
70560da7
FC		 211 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
212 uint32_t inval1;
213 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
214 uint32_t inval2;
9a64fbe4 215 /* instruction type */
0487d6a8 216 uint64_t type;
a5858d7a
AG		 217 /* extended instruction type */
218 uint64_t type2;
79aceca5
FB		 219 /* handler */
220 void (*handler)(DisasContext *ctx);
3fc6c082 221};
79aceca5 222
0e3bf489
RK		 223/* SPR load/store helpers */
224static inline void gen_load_spr(TCGv t, int reg)
225{
226 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
227}
228
229static inline void gen_store_spr(int reg, TCGv t)
230{
231 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
232}
233
636aa200 234static inline void gen_set_access_type(DisasContext *ctx, int access_type)
a7859e89 235{
5f2a6254 236 if (ctx->need_access_type && ctx->access_type != access_type) {
76db3ba4
AJ		 237 tcg_gen_movi_i32(cpu_access_type, access_type);
238 ctx->access_type = access_type;
239 }
a7859e89
AJ		 240}
241
636aa200 242static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
d9bce9d9 243{
e0c8f9ce
RH		 244 if (NARROW_MODE(ctx)) {
245 nip = (uint32_t)nip;
246 }
247 tcg_gen_movi_tl(cpu_nip, nip);
d9bce9d9
JM		 248}
249
b9971cc5 250static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
e06fcd75
AJ		 251{
252 TCGv_i32 t0, t1;
bd6fefe7 253
efe843d8
DG		 254 /*
255 * These are all synchronous exceptions, we set the PC back to the
256 * faulting instruction
bd6fefe7 257 */
7a3fe174 258 gen_update_nip(ctx, ctx->cia);
e06fcd75
AJ		 259 t0 = tcg_const_i32(excp);
260 t1 = tcg_const_i32(error);
e5f17ac6 261 gen_helper_raise_exception_err(cpu_env, t0, t1);
e06fcd75
AJ		 262 tcg_temp_free_i32(t0);
263 tcg_temp_free_i32(t1);
3d8a5b69 264 ctx->base.is_jmp = DISAS_NORETURN;
e06fcd75 265}
e1833e1f 266
b9971cc5 267static void gen_exception(DisasContext *ctx, uint32_t excp)
e06fcd75
AJ		 268{
269 TCGv_i32 t0;
bd6fefe7 270
efe843d8
DG		 271 /*
272 * These are all synchronous exceptions, we set the PC back to the
273 * faulting instruction
bd6fefe7 274 */
7a3fe174 275 gen_update_nip(ctx, ctx->cia);
e06fcd75 276 t0 = tcg_const_i32(excp);
e5f17ac6 277 gen_helper_raise_exception(cpu_env, t0);
e06fcd75 278 tcg_temp_free_i32(t0);
3d8a5b69 279 ctx->base.is_jmp = DISAS_NORETURN;
e06fcd75 280}
e1833e1f 281
bd6fefe7
BH		 282static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
283 target_ulong nip)
284{
285 TCGv_i32 t0;
286
287 gen_update_nip(ctx, nip);
288 t0 = tcg_const_i32(excp);
289 gen_helper_raise_exception(cpu_env, t0);
290 tcg_temp_free_i32(t0);
3d8a5b69 291 ctx->base.is_jmp = DISAS_NORETURN;
bd6fefe7
BH		 292}
293
f5b6daac
RH		 294static void gen_icount_io_start(DisasContext *ctx)
295{
296 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
297 gen_io_start();
298 /*
299 * An I/O instruction must be last in the TB.
300 * Chain to the next TB, and let the code from gen_tb_start
301 * decide if we need to return to the main loop.
302 * Doing this first also allows this value to be overridden.
303 */
304 ctx->base.is_jmp = DISAS_TOO_MANY;
305 }
306}
307
e150ac89
RK		 308/*
309 * Tells the caller what is the appropriate exception to generate and prepares
310 * SPR registers for this exception.
311 *
312 * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or
313 * POWERPC_EXCP_DEBUG (on BookE).
0e3bf489 314 */
e150ac89 315static uint32_t gen_prep_dbgex(DisasContext *ctx)
0e3bf489 316{
0e3bf489
RK		 317 if (ctx->flags & POWERPC_FLAG_DE) {
318 target_ulong dbsr = 0;
e150ac89 319 if (ctx->singlestep_enabled & CPU_SINGLE_STEP) {
0e3bf489 320 dbsr = DBCR0_ICMP;
e150ac89
RK		 321 } else {
322 /* Must have been branch */
0e3bf489 323 dbsr = DBCR0_BRT;
0e3bf489
RK		 324 }
325 TCGv t0 = tcg_temp_new();
326 gen_load_spr(t0, SPR_BOOKE_DBSR);
327 tcg_gen_ori_tl(t0, t0, dbsr);
328 gen_store_spr(SPR_BOOKE_DBSR, t0);
329 tcg_temp_free(t0);
330 return POWERPC_EXCP_DEBUG;
331 } else {
e150ac89 332 return POWERPC_EXCP_TRACE;
0e3bf489
RK		 333 }
334}
335
b9971cc5 336static void gen_debug_exception(DisasContext *ctx)
e06fcd75 337{
9498d103 338 gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx)));
3d8a5b69 339 ctx->base.is_jmp = DISAS_NORETURN;
e06fcd75 340}
9a64fbe4 341
636aa200 342static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
e06fcd75 343{
9b2fadda
BH		 344 /* Will be converted to program check if needed */
345 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error);
346}
347
348static inline void gen_priv_exception(DisasContext *ctx, uint32_t error)
349{
350 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error);
351}
352
353static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
354{
355 /* Will be converted to program check if needed */
356 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
e06fcd75 357}
a9d9eb8f 358
37f219c8
BL		 359/*****************************************************************************/
360/* SPR READ/WRITE CALLBACKS */
361
a829cec3 362void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
37f219c8
BL		 363{
364#if 0
365 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
366 printf("ERROR: try to access SPR %d !\n", sprn);
367#endif
368}
37f219c8
BL		 369
370/* #define PPC_DUMP_SPR_ACCESSES */
371
372/*
373 * Generic callbacks:
374 * do nothing but store/retrieve spr value
375 */
376static void spr_load_dump_spr(int sprn)
377{
378#ifdef PPC_DUMP_SPR_ACCESSES
379 TCGv_i32 t0 = tcg_const_i32(sprn);
380 gen_helper_load_dump_spr(cpu_env, t0);
381 tcg_temp_free_i32(t0);
382#endif
383}
384
a829cec3 385void spr_read_generic(DisasContext *ctx, int gprn, int sprn)
37f219c8
BL		 386{
387 gen_load_spr(cpu_gpr[gprn], sprn);
388 spr_load_dump_spr(sprn);
389}
390
391static void spr_store_dump_spr(int sprn)
392{
393#ifdef PPC_DUMP_SPR_ACCESSES
394 TCGv_i32 t0 = tcg_const_i32(sprn);
395 gen_helper_store_dump_spr(cpu_env, t0);
396 tcg_temp_free_i32(t0);
397#endif
398}
399
a829cec3 400void spr_write_generic(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 401{
402 gen_store_spr(sprn, cpu_gpr[gprn]);
403 spr_store_dump_spr(sprn);
404}
405
7aeac354
DHB		 406void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn)
407{
408 spr_write_generic(ctx, sprn, gprn);
409
410 /*
411 * SPR_CTRL writes must force a new translation block,
412 * allowing the PMU to calculate the run latch events with
413 * more accuracy.
414 */
415 ctx->base.is_jmp = DISAS_EXIT_UPDATE;
416}
417
37f219c8 418#if !defined(CONFIG_USER_ONLY)
a829cec3 419void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 420{
421#ifdef TARGET_PPC64
422 TCGv t0 = tcg_temp_new();
423 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
424 gen_store_spr(sprn, t0);
425 tcg_temp_free(t0);
426 spr_store_dump_spr(sprn);
427#else
428 spr_write_generic(ctx, sprn, gprn);
429#endif
430}
431
a829cec3 432void spr_write_clear(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 433{
434 TCGv t0 = tcg_temp_new();
435 TCGv t1 = tcg_temp_new();
436 gen_load_spr(t0, sprn);
437 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
438 tcg_gen_and_tl(t0, t0, t1);
439 gen_store_spr(sprn, t0);
440 tcg_temp_free(t0);
441 tcg_temp_free(t1);
442}
443
a829cec3 444void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 445{
446}
447
448#endif
449
450/* SPR common to all PowerPC */
451/* XER */
a829cec3 452void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
37f219c8
BL		 453{
454 TCGv dst = cpu_gpr[gprn];
455 TCGv t0 = tcg_temp_new();
456 TCGv t1 = tcg_temp_new();
457 TCGv t2 = tcg_temp_new();
458 tcg_gen_mov_tl(dst, cpu_xer);
459 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
460 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
461 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
462 tcg_gen_or_tl(t0, t0, t1);
463 tcg_gen_or_tl(dst, dst, t2);
464 tcg_gen_or_tl(dst, dst, t0);
465 if (is_isa300(ctx)) {
466 tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
467 tcg_gen_or_tl(dst, dst, t0);
468 tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
469 tcg_gen_or_tl(dst, dst, t0);
470 }
471 tcg_temp_free(t0);
472 tcg_temp_free(t1);
473 tcg_temp_free(t2);
474}
475
a829cec3 476void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 477{
478 TCGv src = cpu_gpr[gprn];
479 /* Write all flags, while reading back check for isa300 */
480 tcg_gen_andi_tl(cpu_xer, src,
481 ~((1u << XER_SO) |
482 (1u << XER_OV) | (1u << XER_OV32) |
483 (1u << XER_CA) | (1u << XER_CA32)));
484 tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1);
485 tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1);
486 tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
487 tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
488 tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
489}
490
491/* LR */
a829cec3 492void spr_read_lr(DisasContext *ctx, int gprn, int sprn)
37f219c8
BL		 493{
494 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
495}
496
a829cec3 497void spr_write_lr(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 498{
499 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
500}
501
502/* CFAR */
503#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
a829cec3 504void spr_read_cfar(DisasContext *ctx, int gprn, int sprn)
37f219c8
BL		 505{
506 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
507}
508
a829cec3 509void spr_write_cfar(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 510{
511 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
512}
513#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
514
515/* CTR */
a829cec3 516void spr_read_ctr(DisasContext *ctx, int gprn, int sprn)
37f219c8
BL		 517{
518 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
519}
520
a829cec3 521void spr_write_ctr(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 522{
523 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
524}
525
526/* User read access to SPR */
527/* USPRx */
528/* UMMCRx */
529/* UPMCx */
530/* USIA */
531/* UDECR */
a829cec3 532void spr_read_ureg(DisasContext *ctx, int gprn, int sprn)
37f219c8
BL		 533{
534 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
535}
536
537#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
a829cec3 538void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 539{
540 gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
541}
542#endif
543
544/* SPR common to all non-embedded PowerPC */
545/* DECR */
546#if !defined(CONFIG_USER_ONLY)
a829cec3 547void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
37f219c8 548{
f5b6daac 549 gen_icount_io_start(ctx);
37f219c8 550 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
37f219c8
BL		 551}
552
a829cec3 553void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
37f219c8 554{
f5b6daac 555 gen_icount_io_start(ctx);
37f219c8 556 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
37f219c8
BL		 557}
558#endif
559
560/* SPR common to all non-embedded PowerPC, except 601 */
561/* Time base */
a829cec3 562void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
37f219c8 563{
f5b6daac 564 gen_icount_io_start(ctx);
37f219c8 565 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
37f219c8
BL		 566}
567
a829cec3 568void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
37f219c8 569{
f5b6daac 570 gen_icount_io_start(ctx);
37f219c8 571 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
37f219c8
BL		 572}
573
a829cec3 574void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
37f219c8
BL		 575{
576 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
577}
578
a829cec3 579void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
37f219c8
BL		 580{
581 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
582}
583
584#if !defined(CONFIG_USER_ONLY)
a829cec3 585void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
37f219c8 586{
f5b6daac 587 gen_icount_io_start(ctx);
37f219c8 588 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
37f219c8
BL		 589}
590
a829cec3 591void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
37f219c8 592{
f5b6daac 593 gen_icount_io_start(ctx);
37f219c8 594 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
37f219c8
BL		 595}
596
a829cec3 597void spr_write_atbl(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 598{
599 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
600}
601
a829cec3 602void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 603{
604 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
605}
606
607#if defined(TARGET_PPC64)
a829cec3 608void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
37f219c8 609{
f5b6daac 610 gen_icount_io_start(ctx);
37f219c8 611 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
37f219c8
BL		 612}
613
a829cec3 614void spr_write_purr(DisasContext *ctx, int sprn, int gprn)
37f219c8 615{
f5b6daac 616 gen_icount_io_start(ctx);
37f219c8 617 gen_helper_store_purr(cpu_env, cpu_gpr[gprn]);
37f219c8
BL		 618}
619
620/* HDECR */
a829cec3 621void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
37f219c8 622{
f5b6daac 623 gen_icount_io_start(ctx);
37f219c8 624 gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
37f219c8
BL		 625}
626
a829cec3 627void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
37f219c8 628{
f5b6daac 629 gen_icount_io_start(ctx);
37f219c8 630 gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
37f219c8
BL		 631}
632
a829cec3 633void spr_read_vtb(DisasContext *ctx, int gprn, int sprn)
37f219c8 634{
f5b6daac 635 gen_icount_io_start(ctx);
37f219c8 636 gen_helper_load_vtb(cpu_gpr[gprn], cpu_env);
37f219c8
BL		 637}
638
a829cec3 639void spr_write_vtb(DisasContext *ctx, int sprn, int gprn)
37f219c8 640{
f5b6daac 641 gen_icount_io_start(ctx);
37f219c8 642 gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]);
37f219c8
BL		 643}
644
a829cec3 645void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
37f219c8 646{
f5b6daac 647 gen_icount_io_start(ctx);
37f219c8 648 gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]);
37f219c8
BL		 649}
650
651#endif
652#endif
653
654#if !defined(CONFIG_USER_ONLY)
655/* IBAT0U...IBAT0U */
656/* IBAT0L...IBAT7L */
a829cec3 657void spr_read_ibat(DisasContext *ctx, int gprn, int sprn)
37f219c8
BL		 658{
659 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
660 offsetof(CPUPPCState,
661 IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
662}
663
a829cec3 664void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn)
37f219c8
BL		 665{
666 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
667 offsetof(CPUPPCState,
668 IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
669}
670
a829cec3 671void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 672{
673 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
674 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
675 tcg_temp_free_i32(t0);
676}
677
a829cec3 678void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 679{
680 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
681 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
682 tcg_temp_free_i32(t0);
683}
684
a829cec3 685void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 686{
687 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
688 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
689 tcg_temp_free_i32(t0);
690}
691
a829cec3 692void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 693{
694 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
695 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
696 tcg_temp_free_i32(t0);
697}
698
699/* DBAT0U...DBAT7U */
700/* DBAT0L...DBAT7L */
a829cec3 701void spr_read_dbat(DisasContext *ctx, int gprn, int sprn)
37f219c8
BL		 702{
703 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
704 offsetof(CPUPPCState,
705 DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
706}
707
a829cec3 708void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn)
37f219c8
BL		 709{
710 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
711 offsetof(CPUPPCState,
712 DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
713}
714
a829cec3 715void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 716{
717 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
718 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
719 tcg_temp_free_i32(t0);
720}
721
a829cec3 722void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 723{
724 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
725 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
726 tcg_temp_free_i32(t0);
727}
728
a829cec3 729void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 730{
731 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
732 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
733 tcg_temp_free_i32(t0);
734}
735
a829cec3 736void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 737{
738 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
739 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
740 tcg_temp_free_i32(t0);
741}
742
743/* SDR1 */
a829cec3 744void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 745{
746 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
747}
748
749#if defined(TARGET_PPC64)
750/* 64 bits PowerPC specific SPRs */
751/* PIDR */
a829cec3 752void spr_write_pidr(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 753{
754 gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]);
755}
756
a829cec3 757void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 758{
759 gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]);
760}
761
a829cec3 762void spr_read_hior(DisasContext *ctx, int gprn, int sprn)
37f219c8
BL		 763{
764 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
765}
766
a829cec3 767void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 768{
769 TCGv t0 = tcg_temp_new();
770 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
771 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
772 tcg_temp_free(t0);
773}
a829cec3 774void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 775{
776 gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]);
777}
778
a829cec3 779void spr_write_pcr(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 780{
781 gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]);
782}
783
784/* DPDES */
a829cec3 785void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn)
37f219c8
BL		 786{
787 gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env);
788}
789
a829cec3 790void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 791{
792 gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]);
793}
794#endif
795#endif
796
797/* PowerPC 601 specific registers */
798/* RTC */
a829cec3 799void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn)
37f219c8
BL		 800{
801 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
802}
803
a829cec3 804void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn)
37f219c8
BL		 805{
806 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
807}
808
809#if !defined(CONFIG_USER_ONLY)
a829cec3 810void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 811{
812 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
813}
814
a829cec3 815void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 816{
817 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
818}
819
a829cec3 820void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 821{
822 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
823 /* Must stop the translation as endianness may have changed */
d736de8f 824 ctx->base.is_jmp = DISAS_EXIT_UPDATE;
37f219c8
BL		 825}
826#endif
827
828/* Unified bats */
829#if !defined(CONFIG_USER_ONLY)
a829cec3 830void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn)
37f219c8
BL		 831{
832 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
833 offsetof(CPUPPCState,
834 IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
835}
836
a829cec3 837void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 838{
839 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
840 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
841 tcg_temp_free_i32(t0);
842}
843
a829cec3 844void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 845{
846 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
847 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
848 tcg_temp_free_i32(t0);
849}
850#endif
851
852/* PowerPC 40x specific registers */
853#if !defined(CONFIG_USER_ONLY)
a829cec3 854void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
37f219c8 855{
f5b6daac 856 gen_icount_io_start(ctx);
37f219c8 857 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
37f219c8
BL		 858}
859
a829cec3 860void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
37f219c8 861{
f5b6daac 862 gen_icount_io_start(ctx);
37f219c8 863 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
37f219c8
BL		 864}
865
a829cec3 866void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
37f219c8 867{
f5b6daac 868 gen_icount_io_start(ctx);
37f219c8
BL		 869 gen_store_spr(sprn, cpu_gpr[gprn]);
870 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
871 /* We must stop translation as we may have rebooted */
d736de8f 872 ctx->base.is_jmp = DISAS_EXIT_UPDATE;
37f219c8
BL		 873}
874
a829cec3 875void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
37f219c8 876{
f5b6daac 877 gen_icount_io_start(ctx);
37f219c8 878 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
37f219c8
BL		 879}
880
cbd8f17d
CLG		 881void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn)
882{
883 gen_icount_io_start(ctx);
884 gen_helper_store_40x_tcr(cpu_env, cpu_gpr[gprn]);
885}
886
887void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn)
888{
889 gen_icount_io_start(ctx);
890 gen_helper_store_40x_tsr(cpu_env, cpu_gpr[gprn]);
891}
892
a829cec3 893void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
37f219c8 894{
f5b6daac 895 gen_icount_io_start(ctx);
37f219c8 896 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
37f219c8
BL		 897}
898
a829cec3 899void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
37f219c8 900{
f5b6daac 901 gen_icount_io_start(ctx);
37f219c8 902 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
37f219c8
BL		 903}
904#endif
905
906/* PowerPC 403 specific registers */
907/* PBL1 / PBU1 / PBL2 / PBU2 */
908#if !defined(CONFIG_USER_ONLY)
a829cec3 909void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn)
37f219c8
BL		 910{
911 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
912 offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
913}
914
a829cec3 915void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 916{
917 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
918 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
919 tcg_temp_free_i32(t0);
920}
921
a829cec3 922void spr_write_pir(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 923{
924 TCGv t0 = tcg_temp_new();
925 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
926 gen_store_spr(SPR_PIR, t0);
927 tcg_temp_free(t0);
928}
929#endif
930
931/* SPE specific registers */
a829cec3 932void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn)
37f219c8
BL		 933{
934 TCGv_i32 t0 = tcg_temp_new_i32();
935 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
936 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
937 tcg_temp_free_i32(t0);
938}
939
a829cec3 940void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 941{
942 TCGv_i32 t0 = tcg_temp_new_i32();
943 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
944 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
945 tcg_temp_free_i32(t0);
946}
947
948#if !defined(CONFIG_USER_ONLY)
949/* Callback used to write the exception vector base */
a829cec3 950void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 951{
952 TCGv t0 = tcg_temp_new();
953 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
954 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
955 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
956 gen_store_spr(sprn, t0);
957 tcg_temp_free(t0);
958}
959
a829cec3 960void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 961{
962 int sprn_offs;
963
964 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
965 sprn_offs = sprn - SPR_BOOKE_IVOR0;
966 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
967 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
968 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
969 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
970 } else {
971 printf("Trying to write an unknown exception vector %d %03x\n",
972 sprn, sprn);
973 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
974 return;
975 }
976
977 TCGv t0 = tcg_temp_new();
978 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
979 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
980 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
981 gen_store_spr(sprn, t0);
982 tcg_temp_free(t0);
983}
984#endif
985
986#ifdef TARGET_PPC64
987#ifndef CONFIG_USER_ONLY
a829cec3 988void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 989{
990 TCGv t0 = tcg_temp_new();
991 TCGv t1 = tcg_temp_new();
992 TCGv t2 = tcg_temp_new();
993
994 /*
995 * Note, the HV=1 PR=0 case is handled earlier by simply using
996 * spr_write_generic for HV mode in the SPR table
997 */
998
999 /* Build insertion mask into t1 based on context */
1000 if (ctx->pr) {
1001 gen_load_spr(t1, SPR_UAMOR);
1002 } else {
1003 gen_load_spr(t1, SPR_AMOR);
1004 }
1005
1006 /* Mask new bits into t2 */
1007 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1008
1009 /* Load AMR and clear new bits in t0 */
1010 gen_load_spr(t0, SPR_AMR);
1011 tcg_gen_andc_tl(t0, t0, t1);
1012
1013 /* Or'in new bits and write it out */
1014 tcg_gen_or_tl(t0, t0, t2);
1015 gen_store_spr(SPR_AMR, t0);
1016 spr_store_dump_spr(SPR_AMR);
1017
1018 tcg_temp_free(t0);
1019 tcg_temp_free(t1);
1020 tcg_temp_free(t2);
1021}
1022
a829cec3 1023void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 1024{
1025 TCGv t0 = tcg_temp_new();
1026 TCGv t1 = tcg_temp_new();
1027 TCGv t2 = tcg_temp_new();
1028
1029 /*
1030 * Note, the HV=1 case is handled earlier by simply using
1031 * spr_write_generic for HV mode in the SPR table
1032 */
1033
1034 /* Build insertion mask into t1 based on context */
1035 gen_load_spr(t1, SPR_AMOR);
1036
1037 /* Mask new bits into t2 */
1038 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1039
1040 /* Load AMR and clear new bits in t0 */
1041 gen_load_spr(t0, SPR_UAMOR);
1042 tcg_gen_andc_tl(t0, t0, t1);
1043
1044 /* Or'in new bits and write it out */
1045 tcg_gen_or_tl(t0, t0, t2);
1046 gen_store_spr(SPR_UAMOR, t0);
1047 spr_store_dump_spr(SPR_UAMOR);
1048
1049 tcg_temp_free(t0);
1050 tcg_temp_free(t1);
1051 tcg_temp_free(t2);
1052}
1053
a829cec3 1054void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 1055{
1056 TCGv t0 = tcg_temp_new();
1057 TCGv t1 = tcg_temp_new();
1058 TCGv t2 = tcg_temp_new();
1059
1060 /*
1061 * Note, the HV=1 case is handled earlier by simply using
1062 * spr_write_generic for HV mode in the SPR table
1063 */
1064
1065 /* Build insertion mask into t1 based on context */
1066 gen_load_spr(t1, SPR_AMOR);
1067
1068 /* Mask new bits into t2 */
1069 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1070
1071 /* Load AMR and clear new bits in t0 */
1072 gen_load_spr(t0, SPR_IAMR);
1073 tcg_gen_andc_tl(t0, t0, t1);
1074
1075 /* Or'in new bits and write it out */
1076 tcg_gen_or_tl(t0, t0, t2);
1077 gen_store_spr(SPR_IAMR, t0);
1078 spr_store_dump_spr(SPR_IAMR);
1079
1080 tcg_temp_free(t0);
1081 tcg_temp_free(t1);
1082 tcg_temp_free(t2);
1083}
1084#endif
1085#endif
1086
1087#ifndef CONFIG_USER_ONLY
a829cec3 1088void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
37f219c8
BL		 1089{
1090 gen_helper_fixup_thrm(cpu_env);
1091 gen_load_spr(cpu_gpr[gprn], sprn);
1092 spr_load_dump_spr(sprn);
1093}
1094#endif /* !CONFIG_USER_ONLY */
1095
1096#if !defined(CONFIG_USER_ONLY)
a829cec3 1097void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 1098{
1099 TCGv t0 = tcg_temp_new();
1100
1101 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
1102 gen_store_spr(sprn, t0);
1103 tcg_temp_free(t0);
1104}
1105
a829cec3 1106void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 1107{
1108 TCGv t0 = tcg_temp_new();
1109
1110 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
1111 gen_store_spr(sprn, t0);
1112 tcg_temp_free(t0);
1113}
1114
a829cec3 1115void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 1116{
1117 TCGv t0 = tcg_temp_new();
1118
1119 tcg_gen_andi_tl(t0, cpu_gpr[gprn],
1120 ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC));
1121 gen_store_spr(sprn, t0);
1122 tcg_temp_free(t0);
1123}
1124
a829cec3 1125void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 1126{
1127 gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
1128}
1129
a829cec3 1130void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 1131{
1132 TCGv_i32 t0 = tcg_const_i32(sprn);
1133 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1134 tcg_temp_free_i32(t0);
1135}
a829cec3 1136void spr_write_eplc(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 1137{
1138 gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]);
1139}
a829cec3 1140void spr_write_epsc(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 1141{
1142 gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]);
1143}
1144
1145#endif
1146
1147#if !defined(CONFIG_USER_ONLY)
a829cec3 1148void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 1149{
1150 TCGv val = tcg_temp_new();
1151 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
1152 gen_store_spr(SPR_BOOKE_MAS3, val);
1153 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
1154 gen_store_spr(SPR_BOOKE_MAS7, val);
1155 tcg_temp_free(val);
1156}
1157
a829cec3 1158void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
37f219c8
BL		 1159{
1160 TCGv mas7 = tcg_temp_new();
1161 TCGv mas3 = tcg_temp_new();
1162 gen_load_spr(mas7, SPR_BOOKE_MAS7);
1163 tcg_gen_shli_tl(mas7, mas7, 32);
1164 gen_load_spr(mas3, SPR_BOOKE_MAS3);
1165 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
1166 tcg_temp_free(mas3);
1167 tcg_temp_free(mas7);
1168}
1169
1170#endif
1171
1172#ifdef TARGET_PPC64
1173static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
1174 int bit, int sprn, int cause)
1175{
1176 TCGv_i32 t1 = tcg_const_i32(bit);
1177 TCGv_i32 t2 = tcg_const_i32(sprn);
1178 TCGv_i32 t3 = tcg_const_i32(cause);
1179
1180 gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
1181
1182 tcg_temp_free_i32(t3);
1183 tcg_temp_free_i32(t2);
1184 tcg_temp_free_i32(t1);
1185}
1186
1187static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
1188 int bit, int sprn, int cause)
1189{
1190 TCGv_i32 t1 = tcg_const_i32(bit);
1191 TCGv_i32 t2 = tcg_const_i32(sprn);
1192 TCGv_i32 t3 = tcg_const_i32(cause);
1193
1194 gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
1195
1196 tcg_temp_free_i32(t3);
1197 tcg_temp_free_i32(t2);
1198 tcg_temp_free_i32(t1);
1199}
1200
a829cec3 1201void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn)
37f219c8
BL		 1202{
1203 TCGv spr_up = tcg_temp_new();
1204 TCGv spr = tcg_temp_new();
1205
1206 gen_load_spr(spr, sprn - 1);
1207 tcg_gen_shri_tl(spr_up, spr, 32);
1208 tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up);
1209
1210 tcg_temp_free(spr);
1211 tcg_temp_free(spr_up);
1212}
1213
a829cec3 1214void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 1215{
1216 TCGv spr = tcg_temp_new();
1217
1218 gen_load_spr(spr, sprn - 1);
1219 tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32);
1220 gen_store_spr(sprn - 1, spr);
1221
1222 tcg_temp_free(spr);
1223}
1224
1225#if !defined(CONFIG_USER_ONLY)
a829cec3 1226void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 1227{
1228 TCGv hmer = tcg_temp_new();
1229
1230 gen_load_spr(hmer, sprn);
1231 tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer);
1232 gen_store_spr(sprn, hmer);
1233 spr_store_dump_spr(sprn);
1234 tcg_temp_free(hmer);
1235}
1236
a829cec3 1237void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 1238{
1239 gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
1240}
1241#endif /* !defined(CONFIG_USER_ONLY) */
1242
a829cec3 1243void spr_read_tar(DisasContext *ctx, int gprn, int sprn)
37f219c8
BL		 1244{
1245 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
1246 spr_read_generic(ctx, gprn, sprn);
1247}
1248
a829cec3 1249void spr_write_tar(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 1250{
1251 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
1252 spr_write_generic(ctx, sprn, gprn);
1253}
1254
a829cec3 1255void spr_read_tm(DisasContext *ctx, int gprn, int sprn)
37f219c8
BL		 1256{
1257 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
1258 spr_read_generic(ctx, gprn, sprn);
1259}
1260
a829cec3 1261void spr_write_tm(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 1262{
1263 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
1264 spr_write_generic(ctx, sprn, gprn);
1265}
1266
a829cec3 1267void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn)
37f219c8
BL		 1268{
1269 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
1270 spr_read_prev_upper32(ctx, gprn, sprn);
1271}
1272
a829cec3 1273void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 1274{
1275 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
1276 spr_write_prev_upper32(ctx, sprn, gprn);
1277}
1278
a829cec3 1279void spr_read_ebb(DisasContext *ctx, int gprn, int sprn)
37f219c8
BL		 1280{
1281 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
1282 spr_read_generic(ctx, gprn, sprn);
1283}
1284
a829cec3 1285void spr_write_ebb(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 1286{
1287 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
1288 spr_write_generic(ctx, sprn, gprn);
1289}
1290
a829cec3 1291void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn)
37f219c8
BL		 1292{
1293 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
1294 spr_read_prev_upper32(ctx, gprn, sprn);
1295}
1296
a829cec3 1297void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn)
37f219c8
BL		 1298{
1299 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
1300 spr_write_prev_upper32(ctx, sprn, gprn);
1301}
1302#endif
1303
79aceca5 1304#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
a5858d7a
AG		 1305GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
1306
1307#define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
1308GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
79aceca5 1309
c7697e1f 1310#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
a5858d7a
AG		 1311GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
1312
1313#define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
1314GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
c7697e1f 1315
323ad19b
ND		 1316#define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
1317GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
1318
14fd8ab2
ND		 1319#define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \
1320GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2)
1321
c227f099 1322typedef struct opcode_t {
323ad19b 1323 unsigned char opc1, opc2, opc3, opc4;
1235fc06 1324#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
323ad19b 1325 unsigned char pad[4];
18fba28c 1326#endif
c227f099 1327 opc_handler_t handler;
b55266b5 1328 const char *oname;
c227f099 1329} opcode_t;
79aceca5 1330
9b2fadda
BH		 1331/* Helpers for priv. check */
1332#define GEN_PRIV \
1333 do { \
1334 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
1335 } while (0)
1336
1337#if defined(CONFIG_USER_ONLY)
1338#define CHK_HV GEN_PRIV
1339#define CHK_SV GEN_PRIV
b7815375 1340#define CHK_HVRM GEN_PRIV
9b2fadda
BH		 1341#else
1342#define CHK_HV \
1343 do { \
1344 if (unlikely(ctx->pr || !ctx->hv)) { \
1345 GEN_PRIV; \
1346 } \
1347 } while (0)
1348#define CHK_SV \
1349 do { \
1350 if (unlikely(ctx->pr)) { \
1351 GEN_PRIV; \
1352 } \
1353 } while (0)
b7815375
BH		 1354#define CHK_HVRM \
1355 do { \
1356 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
1357 GEN_PRIV; \
1358 } \
1359 } while (0)
9b2fadda
BH		 1360#endif
1361
1362#define CHK_NONE
1363
a750fc0b 1364/*****************************************************************************/
a750fc0b 1365/* PowerPC instructions table */
933dc6eb 1366
a5858d7a 1367#define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
5c55ff99 1368{ \
79aceca5
FB		 1369 .opc1 = op1, \
1370 .opc2 = op2, \
1371 .opc3 = op3, \
323ad19b 1372 .opc4 = 0xff, \
79aceca5 1373 .handler = { \
70560da7
FC		 1374 .inval1 = invl, \
1375 .type = _typ, \
1376 .type2 = _typ2, \
1377 .handler = &gen_##name, \
70560da7
FC		 1378 }, \
1379 .oname = stringify(name), \
1380}
1381#define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
1382{ \
1383 .opc1 = op1, \
1384 .opc2 = op2, \
1385 .opc3 = op3, \
323ad19b 1386 .opc4 = 0xff, \
70560da7
FC		 1387 .handler = { \
1388 .inval1 = invl1, \
1389 .inval2 = invl2, \
9a64fbe4 1390 .type = _typ, \
a5858d7a 1391 .type2 = _typ2, \
79aceca5
FB		 1392 .handler = &gen_##name, \
1393 }, \
3fc6c082 1394 .oname = stringify(name), \
79aceca5 1395}
a5858d7a 1396#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
5c55ff99 1397{ \
c7697e1f
JM		 1398 .opc1 = op1, \
1399 .opc2 = op2, \
1400 .opc3 = op3, \
323ad19b 1401 .opc4 = 0xff, \
c7697e1f 1402 .handler = { \
70560da7 1403 .inval1 = invl, \
c7697e1f 1404 .type = _typ, \
a5858d7a 1405 .type2 = _typ2, \
c7697e1f 1406 .handler = &gen_##name, \
c7697e1f
JM		 1407 }, \
1408 .oname = onam, \
1409}
323ad19b
ND		 1410#define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
1411{ \
1412 .opc1 = op1, \
1413 .opc2 = op2, \
1414 .opc3 = op3, \
1415 .opc4 = op4, \
1416 .handler = { \
1417 .inval1 = invl, \
1418 .type = _typ, \
1419 .type2 = _typ2, \
1420 .handler = &gen_##name, \
323ad19b
ND		 1421 }, \
1422 .oname = stringify(name), \
1423}
14fd8ab2
ND		 1424#define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
1425{ \
1426 .opc1 = op1, \
1427 .opc2 = op2, \
1428 .opc3 = op3, \
1429 .opc4 = op4, \
1430 .handler = { \
1431 .inval1 = invl, \
1432 .type = _typ, \
1433 .type2 = _typ2, \
1434 .handler = &gen_##name, \
14fd8ab2
ND		 1435 }, \
1436 .oname = onam, \
1437}
2e610050 1438
54623277 1439/* Invalid instruction */
99e300ef 1440static void gen_invalid(DisasContext *ctx)
9a64fbe4 1441{
e06fcd75 1442 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
9a64fbe4
FB		 1443}
1444
c227f099 1445static opc_handler_t invalid_handler = {
70560da7
FC		 1446 .inval1 = 0xFFFFFFFF,
1447 .inval2 = 0xFFFFFFFF,
9a64fbe4 1448 .type = PPC_NONE,
a5858d7a 1449 .type2 = PPC_NONE,
79aceca5
FB		 1450 .handler = gen_invalid,
1451};
1452
e1571908
AJ		 1453/*** Integer comparison ***/
1454
636aa200 1455static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
e1571908 1456{
2fdcb629 1457 TCGv t0 = tcg_temp_new();
b62b3686
PB		 1458 TCGv t1 = tcg_temp_new();
1459 TCGv_i32 t = tcg_temp_new_i32();
e1571908 1460
b62b3686
PB		 1461 tcg_gen_movi_tl(t0, CRF_EQ);
1462 tcg_gen_movi_tl(t1, CRF_LT);
efe843d8
DG		 1463 tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU),
1464 t0, arg0, arg1, t1, t0);
b62b3686 1465 tcg_gen_movi_tl(t1, CRF_GT);
efe843d8
DG		 1466 tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU),
1467 t0, arg0, arg1, t1, t0);
2fdcb629 1468
b62b3686
PB		 1469 tcg_gen_trunc_tl_i32(t, t0);
1470 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
1471 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t);
2fdcb629
RH		 1472
1473 tcg_temp_free(t0);
b62b3686
PB		 1474 tcg_temp_free(t1);
1475 tcg_temp_free_i32(t);
e1571908
AJ		 1476}
1477
636aa200 1478static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 1479{
2fdcb629 1480 TCGv t0 = tcg_const_tl(arg1);
ea363694
AJ		 1481 gen_op_cmp(arg0, t0, s, crf);
1482 tcg_temp_free(t0);
e1571908
AJ		 1483}
1484
636aa200 1485static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
e1571908 1486{
ea363694 1487 TCGv t0, t1;
2fdcb629
RH		 1488 t0 = tcg_temp_new();
1489 t1 = tcg_temp_new();
e1571908 1490 if (s) {
ea363694
AJ		 1491 tcg_gen_ext32s_tl(t0, arg0);
1492 tcg_gen_ext32s_tl(t1, arg1);
e1571908 1493 } else {
ea363694
AJ		 1494 tcg_gen_ext32u_tl(t0, arg0);
1495 tcg_gen_ext32u_tl(t1, arg1);
e1571908 1496 }
ea363694
AJ		 1497 gen_op_cmp(t0, t1, s, crf);
1498 tcg_temp_free(t1);
1499 tcg_temp_free(t0);
e1571908
AJ		 1500}
1501
636aa200 1502static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 1503{
2fdcb629 1504 TCGv t0 = tcg_const_tl(arg1);
ea363694
AJ		 1505 gen_op_cmp32(arg0, t0, s, crf);
1506 tcg_temp_free(t0);
e1571908 1507}
e1571908 1508
636aa200 1509static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
e1571908 1510{
02765534 1511 if (NARROW_MODE(ctx)) {
e1571908 1512 gen_op_cmpi32(reg, 0, 1, 0);
02765534 1513 } else {
e1571908 1514 gen_op_cmpi(reg, 0, 1, 0);
02765534 1515 }
e1571908
AJ		 1516}
1517
f2442ef9
ND		 1518/* cmprb - range comparison: isupper, isaplha, islower*/
1519static void gen_cmprb(DisasContext *ctx)
1520{
1521 TCGv_i32 src1 = tcg_temp_new_i32();
1522 TCGv_i32 src2 = tcg_temp_new_i32();
1523 TCGv_i32 src2lo = tcg_temp_new_i32();
1524 TCGv_i32 src2hi = tcg_temp_new_i32();
1525 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)];
1526
1527 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]);
1528 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]);
1529
1530 tcg_gen_andi_i32(src1, src1, 0xFF);
1531 tcg_gen_ext8u_i32(src2lo, src2);
1532 tcg_gen_shri_i32(src2, src2, 8);
1533 tcg_gen_ext8u_i32(src2hi, src2);
1534
1535 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
1536 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
1537 tcg_gen_and_i32(crf, src2lo, src2hi);
1538
1539 if (ctx->opcode & 0x00200000) {
1540 tcg_gen_shri_i32(src2, src2, 8);
1541 tcg_gen_ext8u_i32(src2lo, src2);
1542 tcg_gen_shri_i32(src2, src2, 8);
1543 tcg_gen_ext8u_i32(src2hi, src2);
1544 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
1545 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
1546 tcg_gen_and_i32(src2lo, src2lo, src2hi);
1547 tcg_gen_or_i32(crf, crf, src2lo);
1548 }
efa73196 1549 tcg_gen_shli_i32(crf, crf, CRF_GT_BIT);
f2442ef9
ND		 1550 tcg_temp_free_i32(src1);
1551 tcg_temp_free_i32(src2);
1552 tcg_temp_free_i32(src2lo);
1553 tcg_temp_free_i32(src2hi);
1554}
1555
082ce330
ND		 1556#if defined(TARGET_PPC64)
1557/* cmpeqb */
1558static void gen_cmpeqb(DisasContext *ctx)
1559{
1560 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1561 cpu_gpr[rB(ctx->opcode)]);
1562}
1563#endif
1564
e1571908 1565/* isel (PowerPC 2.03 specification) */
99e300ef 1566static void gen_isel(DisasContext *ctx)
e1571908 1567{
e1571908 1568 uint32_t bi = rC(ctx->opcode);
24f9cd95
RH		 1569 uint32_t mask = 0x08 >> (bi & 0x03);
1570 TCGv t0 = tcg_temp_new();
1571 TCGv zr;
e1571908 1572
24f9cd95
RH		 1573 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
1574 tcg_gen_andi_tl(t0, t0, mask);
1575
1576 zr = tcg_const_tl(0);
1577 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
1578 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
1579 cpu_gpr[rB(ctx->opcode)]);
1580 tcg_temp_free(zr);
1581 tcg_temp_free(t0);
e1571908
AJ		 1582}
1583
fcfda20f
AJ		 1584/* cmpb: PowerPC 2.05 specification */
1585static void gen_cmpb(DisasContext *ctx)
1586{
1587 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
1588 cpu_gpr[rB(ctx->opcode)]);
1589}
1590
79aceca5 1591/*** Integer arithmetic ***/
79aceca5 1592
636aa200
BS		 1593static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
1594 TCGv arg1, TCGv arg2, int sub)
74637406 1595{
ffe30937 1596 TCGv t0 = tcg_temp_new();
79aceca5 1597
8e7a6db9 1598 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
74637406 1599 tcg_gen_xor_tl(t0, arg1, arg2);
ffe30937
RH		 1600 if (sub) {
1601 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
1602 } else {
1603 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
1604 }
1605 tcg_temp_free(t0);
02765534 1606 if (NARROW_MODE(ctx)) {
dc0ad844
ND		 1607 tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1);
1608 if (is_isa300(ctx)) {
1609 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
1610 }
1611 } else {
1612 if (is_isa300(ctx)) {
1613 tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1);
1614 }
38a61d34 1615 tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1);
ffe30937 1616 }
ffe30937 1617 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
79aceca5
FB		 1618}
1619
6b10d008
ND		 1620static inline void gen_op_arith_compute_ca32(DisasContext *ctx,
1621 TCGv res, TCGv arg0, TCGv arg1,
4c5920af 1622 TCGv ca32, int sub)
6b10d008
ND		 1623{
1624 TCGv t0;
1625
1626 if (!is_isa300(ctx)) {
1627 return;
1628 }
1629
1630 t0 = tcg_temp_new();
33903d0a
ND		 1631 if (sub) {
1632 tcg_gen_eqv_tl(t0, arg0, arg1);
1633 } else {
1634 tcg_gen_xor_tl(t0, arg0, arg1);
1635 }
6b10d008 1636 tcg_gen_xor_tl(t0, t0, res);
4c5920af 1637 tcg_gen_extract_tl(ca32, t0, 32, 1);
6b10d008
ND		 1638 tcg_temp_free(t0);
1639}
1640
74637406 1641/* Common add function */
636aa200 1642static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
4c5920af
SJS		 1643 TCGv arg2, TCGv ca, TCGv ca32,
1644 bool add_ca, bool compute_ca,
b5a73f8d 1645 bool compute_ov, bool compute_rc0)
74637406 1646{
b5a73f8d 1647 TCGv t0 = ret;
d9bce9d9 1648
752d634e 1649 if (compute_ca || compute_ov) {
146de60d 1650 t0 = tcg_temp_new();
74637406 1651 }
79aceca5 1652
da91a00f 1653 if (compute_ca) {
79482e5a 1654 if (NARROW_MODE(ctx)) {
efe843d8
DG		 1655 /*
1656 * Caution: a non-obvious corner case of the spec is that
1657 * we must produce the *entire* 64-bit addition, but
1658 * produce the carry into bit 32.
1659 */
79482e5a 1660 TCGv t1 = tcg_temp_new();
752d634e
RH		 1661 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
1662 tcg_gen_add_tl(t0, arg1, arg2);
79482e5a 1663 if (add_ca) {
4c5920af 1664 tcg_gen_add_tl(t0, t0, ca);
79482e5a 1665 }
4c5920af 1666 tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */
752d634e 1667 tcg_temp_free(t1);
4c5920af 1668 tcg_gen_extract_tl(ca, ca, 32, 1);
6b10d008 1669 if (is_isa300(ctx)) {
4c5920af 1670 tcg_gen_mov_tl(ca32, ca);
6b10d008 1671 }
b5a73f8d 1672 } else {
79482e5a
RH		 1673 TCGv zero = tcg_const_tl(0);
1674 if (add_ca) {
4c5920af
SJS		 1675 tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero);
1676 tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero);
79482e5a 1677 } else {
4c5920af 1678 tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero);
79482e5a 1679 }
4c5920af 1680 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0);
79482e5a 1681 tcg_temp_free(zero);
b5a73f8d 1682 }
b5a73f8d
RH		 1683 } else {
1684 tcg_gen_add_tl(t0, arg1, arg2);
1685 if (add_ca) {
4c5920af 1686 tcg_gen_add_tl(t0, t0, ca);
b5a73f8d 1687 }
da91a00f 1688 }
79aceca5 1689
74637406
AJ		 1690 if (compute_ov) {
1691 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
1692 }
b5a73f8d 1693 if (unlikely(compute_rc0)) {
74637406 1694 gen_set_Rc0(ctx, t0);
b5a73f8d 1695 }
74637406 1696
11f4e8f8 1697 if (t0 != ret) {
74637406
AJ		 1698 tcg_gen_mov_tl(ret, t0);
1699 tcg_temp_free(t0);
1700 }
39dd32ee 1701}
74637406 1702/* Add functions with two operands */
4c5920af 1703#define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \
b5a73f8d 1704static void glue(gen_, name)(DisasContext *ctx) \
74637406
AJ		 1705{ \
1706 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
1707 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
4c5920af 1708 ca, glue(ca, 32), \
b5a73f8d 1709 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
74637406
AJ		 1710}
1711/* Add functions with one operand and one immediate */
4c5920af 1712#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \
74637406 1713 add_ca, compute_ca, compute_ov) \
b5a73f8d 1714static void glue(gen_, name)(DisasContext *ctx) \
74637406 1715{ \
b5a73f8d 1716 TCGv t0 = tcg_const_tl(const_val); \
74637406
AJ		 1717 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
1718 cpu_gpr[rA(ctx->opcode)], t0, \
4c5920af 1719 ca, glue(ca, 32), \
b5a73f8d 1720 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
74637406
AJ		 1721 tcg_temp_free(t0); \
1722}
1723
1724/* add add. addo addo. */
4c5920af
SJS		 1725GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0)
1726GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1)
74637406 1727/* addc addc. addco addco. */
4c5920af
SJS		 1728GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0)
1729GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1)
74637406 1730/* adde adde. addeo addeo. */
4c5920af
SJS		 1731GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0)
1732GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1)
74637406 1733/* addme addme. addmeo addmeo. */
4c5920af
SJS		 1734GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0)
1735GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1)
1736/* addex */
1737GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0);
74637406 1738/* addze addze. addzeo addzeo.*/
4c5920af
SJS		 1739GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0)
1740GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1)
74637406 1741/* addic addic.*/
b5a73f8d 1742static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
d9bce9d9 1743{
b5a73f8d
RH		 1744 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1745 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
4c5920af 1746 c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0);
b5a73f8d 1747 tcg_temp_free(c);
d9bce9d9 1748}
99e300ef
BS		 1749
1750static void gen_addic(DisasContext *ctx)
d9bce9d9 1751{
b5a73f8d 1752 gen_op_addic(ctx, 0);
d9bce9d9 1753}
e8eaa2c0
BS		 1754
1755static void gen_addic_(DisasContext *ctx)
d9bce9d9 1756{
b5a73f8d 1757 gen_op_addic(ctx, 1);
d9bce9d9 1758}
99e300ef 1759
636aa200
BS		 1760static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
1761 TCGv arg2, int sign, int compute_ov)
d9bce9d9 1762{
b07c32dc
ND		 1763 TCGv_i32 t0 = tcg_temp_new_i32();
1764 TCGv_i32 t1 = tcg_temp_new_i32();
1765 TCGv_i32 t2 = tcg_temp_new_i32();
1766 TCGv_i32 t3 = tcg_temp_new_i32();
74637406 1767
2ef1b120
AJ		 1768 tcg_gen_trunc_tl_i32(t0, arg1);
1769 tcg_gen_trunc_tl_i32(t1, arg2);
74637406 1770 if (sign) {
b07c32dc
ND		 1771 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1772 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1773 tcg_gen_and_i32(t2, t2, t3);
1774 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1775 tcg_gen_or_i32(t2, t2, t3);
1776 tcg_gen_movi_i32(t3, 0);
1777 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1778 tcg_gen_div_i32(t3, t0, t1);
1779 tcg_gen_extu_i32_tl(ret, t3);
74637406 1780 } else {
b07c32dc
ND		 1781 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0);
1782 tcg_gen_movi_i32(t3, 0);
1783 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1784 tcg_gen_divu_i32(t3, t0, t1);
1785 tcg_gen_extu_i32_tl(ret, t3);
74637406
AJ		 1786 }
1787 if (compute_ov) {
b07c32dc 1788 tcg_gen_extu_i32_tl(cpu_ov, t2);
c44027ff
ND		 1789 if (is_isa300(ctx)) {
1790 tcg_gen_extu_i32_tl(cpu_ov32, t2);
1791 }
b07c32dc 1792 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
74637406 1793 }
a7812ae4
PB		 1794 tcg_temp_free_i32(t0);
1795 tcg_temp_free_i32(t1);
b07c32dc
ND		 1796 tcg_temp_free_i32(t2);
1797 tcg_temp_free_i32(t3);
1798
efe843d8 1799 if (unlikely(Rc(ctx->opcode) != 0)) {
74637406 1800 gen_set_Rc0(ctx, ret);
efe843d8 1801 }
d9bce9d9 1802}
74637406
AJ		 1803/* Div functions */
1804#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
efe843d8 1805static void glue(gen_, name)(DisasContext *ctx) \
74637406
AJ		 1806{ \
1807 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1808 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1809 sign, compute_ov); \
1810}
1811/* divwu divwu. divwuo divwuo. */
1812GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1813GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1814/* divw divw. divwo divwo. */
1815GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1816GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
98d1eb27
TM		 1817
1818/* div[wd]eu[o][.] */
1819#define GEN_DIVE(name, hlpr, compute_ov) \
1820static void gen_##name(DisasContext *ctx) \
1821{ \
1822 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1823 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1824 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1825 tcg_temp_free_i32(t0); \
1826 if (unlikely(Rc(ctx->opcode) != 0)) { \
1827 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1828 } \
1829}
1830
6a4fda33
TM		 1831GEN_DIVE(divweu, divweu, 0);
1832GEN_DIVE(divweuo, divweu, 1);
a98eb9e9
TM		 1833GEN_DIVE(divwe, divwe, 0);
1834GEN_DIVE(divweo, divwe, 1);
6a4fda33 1835
d9bce9d9 1836#if defined(TARGET_PPC64)
636aa200
BS		 1837static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1838 TCGv arg2, int sign, int compute_ov)
d9bce9d9 1839{
4110b586
ND		 1840 TCGv_i64 t0 = tcg_temp_new_i64();
1841 TCGv_i64 t1 = tcg_temp_new_i64();
1842 TCGv_i64 t2 = tcg_temp_new_i64();
1843 TCGv_i64 t3 = tcg_temp_new_i64();
74637406 1844
4110b586
ND		 1845 tcg_gen_mov_i64(t0, arg1);
1846 tcg_gen_mov_i64(t1, arg2);
74637406 1847 if (sign) {
4110b586
ND		 1848 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1849 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1850 tcg_gen_and_i64(t2, t2, t3);
1851 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1852 tcg_gen_or_i64(t2, t2, t3);
1853 tcg_gen_movi_i64(t3, 0);
1854 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1855 tcg_gen_div_i64(ret, t0, t1);
74637406 1856 } else {
4110b586
ND		 1857 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0);
1858 tcg_gen_movi_i64(t3, 0);
1859 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1860 tcg_gen_divu_i64(ret, t0, t1);
74637406
AJ		 1861 }
1862 if (compute_ov) {
4110b586 1863 tcg_gen_mov_tl(cpu_ov, t2);
c44027ff
ND		 1864 if (is_isa300(ctx)) {
1865 tcg_gen_mov_tl(cpu_ov32, t2);
1866 }
4110b586 1867 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
74637406 1868 }
4110b586
ND		 1869 tcg_temp_free_i64(t0);
1870 tcg_temp_free_i64(t1);
1871 tcg_temp_free_i64(t2);
1872 tcg_temp_free_i64(t3);
1873
efe843d8 1874 if (unlikely(Rc(ctx->opcode) != 0)) {
74637406 1875 gen_set_Rc0(ctx, ret);
efe843d8 1876 }
d9bce9d9 1877}
4110b586 1878
74637406 1879#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
efe843d8 1880static void glue(gen_, name)(DisasContext *ctx) \
74637406 1881{ \
2ef1b120
AJ		 1882 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1883 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1884 sign, compute_ov); \
74637406 1885}
c44027ff 1886/* divdu divdu. divduo divduo. */
74637406
AJ		 1887GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1888GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
c44027ff 1889/* divd divd. divdo divdo. */
74637406
AJ		 1890GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1891GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
98d1eb27
TM		 1892
1893GEN_DIVE(divdeu, divdeu, 0);
1894GEN_DIVE(divdeuo, divdeu, 1);
e44259b6
TM		 1895GEN_DIVE(divde, divde, 0);
1896GEN_DIVE(divdeo, divde, 1);
d9bce9d9 1897#endif
74637406 1898
af2c6620
ND		 1899static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
1900 TCGv arg2, int sign)
1901{
1902 TCGv_i32 t0 = tcg_temp_new_i32();
1903 TCGv_i32 t1 = tcg_temp_new_i32();
1904
1905 tcg_gen_trunc_tl_i32(t0, arg1);
1906 tcg_gen_trunc_tl_i32(t1, arg2);
1907 if (sign) {
1908 TCGv_i32 t2 = tcg_temp_new_i32();
1909 TCGv_i32 t3 = tcg_temp_new_i32();
1910 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1911 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1912 tcg_gen_and_i32(t2, t2, t3);
1913 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1914 tcg_gen_or_i32(t2, t2, t3);
1915 tcg_gen_movi_i32(t3, 0);
1916 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1917 tcg_gen_rem_i32(t3, t0, t1);
1918 tcg_gen_ext_i32_tl(ret, t3);
1919 tcg_temp_free_i32(t2);
1920 tcg_temp_free_i32(t3);
1921 } else {
1922 TCGv_i32 t2 = tcg_const_i32(1);
1923 TCGv_i32 t3 = tcg_const_i32(0);
1924 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
1925 tcg_gen_remu_i32(t3, t0, t1);
1926 tcg_gen_extu_i32_tl(ret, t3);
1927 tcg_temp_free_i32(t2);
1928 tcg_temp_free_i32(t3);
1929 }
1930 tcg_temp_free_i32(t0);
1931 tcg_temp_free_i32(t1);
1932}
1933
1934#define GEN_INT_ARITH_MODW(name, opc3, sign) \
1935static void glue(gen_, name)(DisasContext *ctx) \
1936{ \
1937 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
1938 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1939 sign); \
1940}
1941
1942GEN_INT_ARITH_MODW(moduw, 0x08, 0);
1943GEN_INT_ARITH_MODW(modsw, 0x18, 1);
1944
063cf14f
ND		 1945#if defined(TARGET_PPC64)
1946static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
1947 TCGv arg2, int sign)
1948{
1949 TCGv_i64 t0 = tcg_temp_new_i64();
1950 TCGv_i64 t1 = tcg_temp_new_i64();
1951
1952 tcg_gen_mov_i64(t0, arg1);
1953 tcg_gen_mov_i64(t1, arg2);
1954 if (sign) {
1955 TCGv_i64 t2 = tcg_temp_new_i64();
1956 TCGv_i64 t3 = tcg_temp_new_i64();
1957 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1958 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1959 tcg_gen_and_i64(t2, t2, t3);
1960 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1961 tcg_gen_or_i64(t2, t2, t3);
1962 tcg_gen_movi_i64(t3, 0);
1963 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1964 tcg_gen_rem_i64(ret, t0, t1);
1965 tcg_temp_free_i64(t2);
1966 tcg_temp_free_i64(t3);
1967 } else {
1968 TCGv_i64 t2 = tcg_const_i64(1);
1969 TCGv_i64 t3 = tcg_const_i64(0);
1970 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
1971 tcg_gen_remu_i64(ret, t0, t1);
1972 tcg_temp_free_i64(t2);
1973 tcg_temp_free_i64(t3);
1974 }
1975 tcg_temp_free_i64(t0);
1976 tcg_temp_free_i64(t1);
1977}
1978
1979#define GEN_INT_ARITH_MODD(name, opc3, sign) \
1980static void glue(gen_, name)(DisasContext *ctx) \
1981{ \
1982 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
1983 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1984 sign); \
1985}
1986
1987GEN_INT_ARITH_MODD(modud, 0x08, 0);
1988GEN_INT_ARITH_MODD(modsd, 0x18, 1);
1989#endif
1990
74637406 1991/* mulhw mulhw. */
99e300ef 1992static void gen_mulhw(DisasContext *ctx)
d9bce9d9 1993{
23ad1d5d
RH		 1994 TCGv_i32 t0 = tcg_temp_new_i32();
1995 TCGv_i32 t1 = tcg_temp_new_i32();
74637406 1996
23ad1d5d
RH		 1997 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1998 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1999 tcg_gen_muls2_i32(t0, t1, t0, t1);
2000 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
2001 tcg_temp_free_i32(t0);
2002 tcg_temp_free_i32(t1);
efe843d8 2003 if (unlikely(Rc(ctx->opcode) != 0)) {
74637406 2004 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
efe843d8 2005 }
d9bce9d9 2006}
99e300ef 2007
54623277 2008/* mulhwu mulhwu. */
99e300ef 2009static void gen_mulhwu(DisasContext *ctx)
d9bce9d9 2010{
23ad1d5d
RH		 2011 TCGv_i32 t0 = tcg_temp_new_i32();
2012 TCGv_i32 t1 = tcg_temp_new_i32();
74637406 2013
23ad1d5d
RH		 2014 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
2015 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
2016 tcg_gen_mulu2_i32(t0, t1, t0, t1);
2017 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
2018 tcg_temp_free_i32(t0);
2019 tcg_temp_free_i32(t1);
efe843d8 2020 if (unlikely(Rc(ctx->opcode) != 0)) {
74637406 2021 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
efe843d8 2022 }
d9bce9d9 2023}
99e300ef 2024
54623277 2025/* mullw mullw. */
99e300ef 2026static void gen_mullw(DisasContext *ctx)
d9bce9d9 2027{
1fa74845
TM		 2028#if defined(TARGET_PPC64)
2029 TCGv_i64 t0, t1;
2030 t0 = tcg_temp_new_i64();
2031 t1 = tcg_temp_new_i64();
2032 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
2033 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
2034 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
2035 tcg_temp_free(t0);
2036 tcg_temp_free(t1);
2037#else
03039e5e
TM		 2038 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
2039 cpu_gpr[rB(ctx->opcode)]);
1fa74845 2040#endif
efe843d8 2041 if (unlikely(Rc(ctx->opcode) != 0)) {
74637406 2042 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
efe843d8 2043 }
d9bce9d9 2044}
99e300ef 2045
54623277 2046/* mullwo mullwo. */
99e300ef 2047static void gen_mullwo(DisasContext *ctx)
d9bce9d9 2048{
e4a2c846
RH		 2049 TCGv_i32 t0 = tcg_temp_new_i32();
2050 TCGv_i32 t1 = tcg_temp_new_i32();
74637406 2051
e4a2c846
RH		 2052 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
2053 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
2054 tcg_gen_muls2_i32(t0, t1, t0, t1);
f11ebbf8 2055#if defined(TARGET_PPC64)
26977876
TM		 2056 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
2057#else
2058 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
f11ebbf8 2059#endif
e4a2c846
RH		 2060
2061 tcg_gen_sari_i32(t0, t0, 31);
2062 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
2063 tcg_gen_extu_i32_tl(cpu_ov, t0);
61aa9a69
ND		 2064 if (is_isa300(ctx)) {
2065 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
2066 }
e4a2c846
RH		 2067 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
2068
2069 tcg_temp_free_i32(t0);
2070 tcg_temp_free_i32(t1);
efe843d8 2071 if (unlikely(Rc(ctx->opcode) != 0)) {
74637406 2072 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
efe843d8 2073 }
d9bce9d9 2074}
99e300ef 2075
54623277 2076/* mulli */
99e300ef 2077static void gen_mulli(DisasContext *ctx)
d9bce9d9 2078{
74637406
AJ		 2079 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
2080 SIMM(ctx->opcode));
d9bce9d9 2081}
23ad1d5d 2082
d9bce9d9 2083#if defined(TARGET_PPC64)
74637406 2084/* mulhd mulhd. */
23ad1d5d
RH		 2085static void gen_mulhd(DisasContext *ctx)
2086{
2087 TCGv lo = tcg_temp_new();
2088 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
2089 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2090 tcg_temp_free(lo);
2091 if (unlikely(Rc(ctx->opcode) != 0)) {
2092 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2093 }
2094}
2095
74637406 2096/* mulhdu mulhdu. */
23ad1d5d
RH		 2097static void gen_mulhdu(DisasContext *ctx)
2098{
2099 TCGv lo = tcg_temp_new();
2100 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
2101 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2102 tcg_temp_free(lo);
2103 if (unlikely(Rc(ctx->opcode) != 0)) {
2104 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2105 }
2106}
99e300ef 2107
54623277 2108/* mulld mulld. */
99e300ef 2109static void gen_mulld(DisasContext *ctx)
d9bce9d9 2110{
74637406
AJ		 2111 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
2112 cpu_gpr[rB(ctx->opcode)]);
efe843d8 2113 if (unlikely(Rc(ctx->opcode) != 0)) {
74637406 2114 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
efe843d8 2115 }
d9bce9d9 2116}
d15f74fb 2117
74637406 2118/* mulldo mulldo. */
d15f74fb
BS		 2119static void gen_mulldo(DisasContext *ctx)
2120{
22ffad31
TM		 2121 TCGv_i64 t0 = tcg_temp_new_i64();
2122 TCGv_i64 t1 = tcg_temp_new_i64();
2123
2124 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
2125 cpu_gpr[rB(ctx->opcode)]);
2126 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
2127
2128 tcg_gen_sari_i64(t0, t0, 63);
2129 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
61aa9a69
ND		 2130 if (is_isa300(ctx)) {
2131 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
2132 }
22ffad31
TM		 2133 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
2134
2135 tcg_temp_free_i64(t0);
2136 tcg_temp_free_i64(t1);
2137
d15f74fb
BS		 2138 if (unlikely(Rc(ctx->opcode) != 0)) {
2139 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2140 }
2141}
d9bce9d9 2142#endif
74637406 2143
74637406 2144/* Common subf function */
636aa200 2145static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
b5a73f8d
RH		 2146 TCGv arg2, bool add_ca, bool compute_ca,
2147 bool compute_ov, bool compute_rc0)
79aceca5 2148{
b5a73f8d 2149 TCGv t0 = ret;
79aceca5 2150
752d634e 2151 if (compute_ca || compute_ov) {
b5a73f8d 2152 t0 = tcg_temp_new();
da91a00f 2153 }
74637406 2154
79482e5a
RH		 2155 if (compute_ca) {
2156 /* dest = ~arg1 + arg2 [+ ca]. */
2157 if (NARROW_MODE(ctx)) {
efe843d8
DG		 2158 /*
2159 * Caution: a non-obvious corner case of the spec is that
2160 * we must produce the *entire* 64-bit addition, but
2161 * produce the carry into bit 32.
2162 */
79482e5a 2163 TCGv inv1 = tcg_temp_new();
752d634e 2164 TCGv t1 = tcg_temp_new();
79482e5a 2165 tcg_gen_not_tl(inv1, arg1);
79482e5a 2166 if (add_ca) {
752d634e 2167 tcg_gen_add_tl(t0, arg2, cpu_ca);
79482e5a 2168 } else {
752d634e 2169 tcg_gen_addi_tl(t0, arg2, 1);
79482e5a 2170 }
752d634e 2171 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
79482e5a 2172 tcg_gen_add_tl(t0, t0, inv1);
c80d1df5 2173 tcg_temp_free(inv1);
752d634e
RH		 2174 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
2175 tcg_temp_free(t1);
e2622073 2176 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1);
33903d0a
ND		 2177 if (is_isa300(ctx)) {
2178 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
2179 }
79482e5a 2180 } else if (add_ca) {
08f4a0f7
RH		 2181 TCGv zero, inv1 = tcg_temp_new();
2182 tcg_gen_not_tl(inv1, arg1);
b5a73f8d
RH		 2183 zero = tcg_const_tl(0);
2184 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
08f4a0f7 2185 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
4c5920af 2186 gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0);
b5a73f8d 2187 tcg_temp_free(zero);
08f4a0f7 2188 tcg_temp_free(inv1);
b5a73f8d 2189 } else {
79482e5a 2190 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
b5a73f8d 2191 tcg_gen_sub_tl(t0, arg2, arg1);
4c5920af 2192 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1);
b5a73f8d 2193 }
79482e5a 2194 } else if (add_ca) {
efe843d8
DG		 2195 /*
2196 * Since we're ignoring carry-out, we can simplify the
2197 * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1.
2198 */
79482e5a
RH		 2199 tcg_gen_sub_tl(t0, arg2, arg1);
2200 tcg_gen_add_tl(t0, t0, cpu_ca);
2201 tcg_gen_subi_tl(t0, t0, 1);
79aceca5 2202 } else {
b5a73f8d 2203 tcg_gen_sub_tl(t0, arg2, arg1);
74637406 2204 }
b5a73f8d 2205
74637406
AJ		 2206 if (compute_ov) {
2207 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
2208 }
b5a73f8d 2209 if (unlikely(compute_rc0)) {
74637406 2210 gen_set_Rc0(ctx, t0);
b5a73f8d 2211 }
74637406 2212
11f4e8f8 2213 if (t0 != ret) {
74637406
AJ		 2214 tcg_gen_mov_tl(ret, t0);
2215 tcg_temp_free(t0);
79aceca5 2216 }
79aceca5 2217}
74637406
AJ		 2218/* Sub functions with Two operands functions */
2219#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
b5a73f8d 2220static void glue(gen_, name)(DisasContext *ctx) \
74637406
AJ		 2221{ \
2222 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
2223 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
b5a73f8d 2224 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
74637406
AJ		 2225}
2226/* Sub functions with one operand and one immediate */
2227#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
2228 add_ca, compute_ca, compute_ov) \
b5a73f8d 2229static void glue(gen_, name)(DisasContext *ctx) \
74637406 2230{ \
b5a73f8d 2231 TCGv t0 = tcg_const_tl(const_val); \
74637406
AJ		 2232 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
2233 cpu_gpr[rA(ctx->opcode)], t0, \
b5a73f8d 2234 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
74637406
AJ		 2235 tcg_temp_free(t0); \
2236}
2237/* subf subf. subfo subfo. */
2238GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
2239GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
2240/* subfc subfc. subfco subfco. */
2241GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
2242GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
2243/* subfe subfe. subfeo subfo. */
2244GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
2245GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
2246/* subfme subfme. subfmeo subfmeo. */
2247GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
2248GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
2249/* subfze subfze. subfzeo subfzeo.*/
2250GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
2251GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
99e300ef 2252
54623277 2253/* subfic */
99e300ef 2254static void gen_subfic(DisasContext *ctx)
79aceca5 2255{
b5a73f8d
RH		 2256 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
2257 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
2258 c, 0, 1, 0, 0);
2259 tcg_temp_free(c);
79aceca5
FB		 2260}
2261
fd3f0081
RH		 2262/* neg neg. nego nego. */
2263static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
2264{
2265 TCGv zero = tcg_const_tl(0);
2266 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
2267 zero, 0, 0, compute_ov, Rc(ctx->opcode));
2268 tcg_temp_free(zero);
2269}
2270
2271static void gen_neg(DisasContext *ctx)
2272{
1480d71c
ND		 2273 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
2274 if (unlikely(Rc(ctx->opcode))) {
2275 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2276 }
fd3f0081
RH		 2277}
2278
2279static void gen_nego(DisasContext *ctx)
2280{
2281 gen_op_arith_neg(ctx, 1);
2282}
2283
79aceca5 2284/*** Integer logical ***/
26d67362 2285#define GEN_LOGICAL2(name, tcg_op, opc, type) \
efe843d8 2286static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 2287{ \
26d67362
AJ		 2288 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
2289 cpu_gpr[rB(ctx->opcode)]); \
76a66253 2290 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 2291 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5 2292}
79aceca5 2293
26d67362 2294#define GEN_LOGICAL1(name, tcg_op, opc, type) \
efe843d8 2295static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 2296{ \
26d67362 2297 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
76a66253 2298 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 2299 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5
FB		 2300}
2301
2302/* and & and. */
26d67362 2303GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
79aceca5 2304/* andc & andc. */
26d67362 2305GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
e8eaa2c0 2306
54623277 2307/* andi. */
e8eaa2c0 2308static void gen_andi_(DisasContext *ctx)
79aceca5 2309{
efe843d8
DG		 2310 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
2311 UIMM(ctx->opcode));
26d67362 2312 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 2313}
e8eaa2c0 2314
54623277 2315/* andis. */
e8eaa2c0 2316static void gen_andis_(DisasContext *ctx)
79aceca5 2317{
efe843d8
DG		 2318 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
2319 UIMM(ctx->opcode) << 16);
26d67362 2320 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 2321}
99e300ef 2322
54623277 2323/* cntlzw */
99e300ef 2324static void gen_cntlzw(DisasContext *ctx)
26d67362 2325{
9b8514e5
RH		 2326 TCGv_i32 t = tcg_temp_new_i32();
2327
2328 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
2329 tcg_gen_clzi_i32(t, t, 32);
2330 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
2331 tcg_temp_free_i32(t);
2332
efe843d8 2333 if (unlikely(Rc(ctx->opcode) != 0)) {
2e31f5d3 2334 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
efe843d8 2335 }
26d67362 2336}
b35344e4
ND		 2337
2338/* cnttzw */
2339static void gen_cnttzw(DisasContext *ctx)
2340{
9b8514e5
RH		 2341 TCGv_i32 t = tcg_temp_new_i32();
2342
2343 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
2344 tcg_gen_ctzi_i32(t, t, 32);
2345 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
2346 tcg_temp_free_i32(t);
2347
b35344e4
ND		 2348 if (unlikely(Rc(ctx->opcode) != 0)) {
2349 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2350 }
2351}
2352
79aceca5 2353/* eqv & eqv. */
26d67362 2354GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
79aceca5 2355/* extsb & extsb. */
26d67362 2356GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
79aceca5 2357/* extsh & extsh. */
26d67362 2358GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
79aceca5 2359/* nand & nand. */
26d67362 2360GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
79aceca5 2361/* nor & nor. */
26d67362 2362GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
99e300ef 2363
7f2b1744 2364#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
b68e60e6
BH		 2365static void gen_pause(DisasContext *ctx)
2366{
2367 TCGv_i32 t0 = tcg_const_i32(0);
2368 tcg_gen_st_i32(t0, cpu_env,
2369 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
2370 tcg_temp_free_i32(t0);
2371
2372 /* Stop translation, this gives other CPUs a chance to run */
b6bac4bc 2373 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
b68e60e6
BH		 2374}
2375#endif /* defined(TARGET_PPC64) */
2376
54623277 2377/* or & or. */
99e300ef 2378static void gen_or(DisasContext *ctx)
9a64fbe4 2379{
76a66253
JM		 2380 int rs, ra, rb;
2381
2382 rs = rS(ctx->opcode);
2383 ra = rA(ctx->opcode);
2384 rb = rB(ctx->opcode);
2385 /* Optimisation for mr. ri case */
2386 if (rs != ra || rs != rb) {
efe843d8 2387 if (rs != rb) {
26d67362 2388 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
efe843d8 2389 } else {
26d67362 2390 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
efe843d8
DG		 2391 }
2392 if (unlikely(Rc(ctx->opcode) != 0)) {
26d67362 2393 gen_set_Rc0(ctx, cpu_gpr[ra]);
efe843d8 2394 }
76a66253 2395 } else if (unlikely(Rc(ctx->opcode) != 0)) {
26d67362 2396 gen_set_Rc0(ctx, cpu_gpr[rs]);
c80f84e3 2397#if defined(TARGET_PPC64)
9e196938 2398 } else if (rs != 0) { /* 0 is nop */
26d67362
AJ		 2399 int prio = 0;
2400
c80f84e3
JM		 2401 switch (rs) {
2402 case 1:
2403 /* Set process priority to low */
26d67362 2404 prio = 2;
c80f84e3
JM		 2405 break;
2406 case 6:
2407 /* Set process priority to medium-low */
26d67362 2408 prio = 3;
c80f84e3
JM		 2409 break;
2410 case 2:
2411 /* Set process priority to normal */
26d67362 2412 prio = 4;
c80f84e3 2413 break;
be147d08
JM		 2414#if !defined(CONFIG_USER_ONLY)
2415 case 31:
c47493f2 2416 if (!ctx->pr) {
be147d08 2417 /* Set process priority to very low */
26d67362 2418 prio = 1;
be147d08
JM		 2419 }
2420 break;
2421 case 5:
c47493f2 2422 if (!ctx->pr) {
be147d08 2423 /* Set process priority to medium-hight */
26d67362 2424 prio = 5;
be147d08
JM		 2425 }
2426 break;
2427 case 3:
c47493f2 2428 if (!ctx->pr) {
be147d08 2429 /* Set process priority to high */
26d67362 2430 prio = 6;
be147d08
JM		 2431 }
2432 break;
be147d08 2433 case 7:
b68e60e6 2434 if (ctx->hv && !ctx->pr) {
be147d08 2435 /* Set process priority to very high */
26d67362 2436 prio = 7;
be147d08
JM		 2437 }
2438 break;
be147d08 2439#endif
c80f84e3 2440 default:
c80f84e3
JM		 2441 break;
2442 }
26d67362 2443 if (prio) {
a7812ae4 2444 TCGv t0 = tcg_temp_new();
54cdcae6 2445 gen_load_spr(t0, SPR_PPR);
ea363694
AJ		 2446 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
2447 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
54cdcae6 2448 gen_store_spr(SPR_PPR, t0);
ea363694 2449 tcg_temp_free(t0);
9e196938 2450 }
7f2b1744 2451#if !defined(CONFIG_USER_ONLY)
efe843d8
DG		 2452 /*
2453 * Pause out of TCG otherwise spin loops with smt_low eat too
2454 * much CPU and the kernel hangs. This applies to all
2455 * encodings other than no-op, e.g., miso(rs=26), yield(27),
2456 * mdoio(29), mdoom(30), and all currently undefined.
9e196938
AL		 2457 */
2458 gen_pause(ctx);
7f2b1744 2459#endif
c80f84e3 2460#endif
9a64fbe4 2461 }
9a64fbe4 2462}
79aceca5 2463/* orc & orc. */
26d67362 2464GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
99e300ef 2465
54623277 2466/* xor & xor. */
99e300ef 2467static void gen_xor(DisasContext *ctx)
9a64fbe4 2468{
9a64fbe4 2469 /* Optimisation for "set to zero" case */
efe843d8
DG		 2470 if (rS(ctx->opcode) != rB(ctx->opcode)) {
2471 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
2472 cpu_gpr[rB(ctx->opcode)]);
2473 } else {
26d67362 2474 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
efe843d8
DG		 2475 }
2476 if (unlikely(Rc(ctx->opcode) != 0)) {
26d67362 2477 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
efe843d8 2478 }
9a64fbe4 2479}
99e300ef 2480
54623277 2481/* ori */
99e300ef 2482static void gen_ori(DisasContext *ctx)
79aceca5 2483{
76a66253 2484 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 2485
9a64fbe4 2486 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
9a64fbe4 2487 return;
76a66253 2488 }
26d67362 2489 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5 2490}
99e300ef 2491
54623277 2492/* oris */
99e300ef 2493static void gen_oris(DisasContext *ctx)
79aceca5 2494{
76a66253 2495 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 2496
9a64fbe4
FB		 2497 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
2498 /* NOP */
2499 return;
76a66253 2500 }
efe843d8
DG		 2501 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
2502 uimm << 16);
79aceca5 2503}
99e300ef 2504
54623277 2505/* xori */
99e300ef 2506static void gen_xori(DisasContext *ctx)
79aceca5 2507{
76a66253 2508 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 2509
2510 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
2511 /* NOP */
2512 return;
2513 }
26d67362 2514 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5 2515}
99e300ef 2516
54623277 2517/* xoris */
99e300ef 2518static void gen_xoris(DisasContext *ctx)
79aceca5 2519{
76a66253 2520 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 2521
2522 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
2523 /* NOP */
2524 return;
2525 }
efe843d8
DG		 2526 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
2527 uimm << 16);
79aceca5 2528}
99e300ef 2529
54623277 2530/* popcntb : PowerPC 2.03 specification */
99e300ef 2531static void gen_popcntb(DisasContext *ctx)
d9bce9d9 2532{
eaabeef2
DG		 2533 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2534}
2535
2536static void gen_popcntw(DisasContext *ctx)
2537{
79770002 2538#if defined(TARGET_PPC64)
eaabeef2 2539 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
79770002
RH		 2540#else
2541 tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2542#endif
eaabeef2
DG		 2543}
2544
d9bce9d9 2545#if defined(TARGET_PPC64)
eaabeef2
DG		 2546/* popcntd: PowerPC 2.06 specification */
2547static void gen_popcntd(DisasContext *ctx)
2548{
79770002 2549 tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9 2550}
eaabeef2 2551#endif
d9bce9d9 2552
725bcec2
AJ		 2553/* prtyw: PowerPC 2.05 specification */
2554static void gen_prtyw(DisasContext *ctx)
2555{
2556 TCGv ra = cpu_gpr[rA(ctx->opcode)];
2557 TCGv rs = cpu_gpr[rS(ctx->opcode)];
2558 TCGv t0 = tcg_temp_new();
2559 tcg_gen_shri_tl(t0, rs, 16);
2560 tcg_gen_xor_tl(ra, rs, t0);
2561 tcg_gen_shri_tl(t0, ra, 8);
2562 tcg_gen_xor_tl(ra, ra, t0);
2563 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
2564 tcg_temp_free(t0);
2565}
2566
2567#if defined(TARGET_PPC64)
2568/* prtyd: PowerPC 2.05 specification */
2569static void gen_prtyd(DisasContext *ctx)
2570{
2571 TCGv ra = cpu_gpr[rA(ctx->opcode)];
2572 TCGv rs = cpu_gpr[rS(ctx->opcode)];
2573 TCGv t0 = tcg_temp_new();
2574 tcg_gen_shri_tl(t0, rs, 32);
2575 tcg_gen_xor_tl(ra, rs, t0);
2576 tcg_gen_shri_tl(t0, ra, 16);
2577 tcg_gen_xor_tl(ra, ra, t0);
2578 tcg_gen_shri_tl(t0, ra, 8);
2579 tcg_gen_xor_tl(ra, ra, t0);
2580 tcg_gen_andi_tl(ra, ra, 1);
2581 tcg_temp_free(t0);
2582}
2583#endif
2584
86ba37ed
TM		 2585#if defined(TARGET_PPC64)
2586/* bpermd */
2587static void gen_bpermd(DisasContext *ctx)
2588{
2589 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
2590 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2591}
2592#endif
2593
d9bce9d9
JM		 2594#if defined(TARGET_PPC64)
2595/* extsw & extsw. */
26d67362 2596GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
99e300ef 2597
54623277 2598/* cntlzd */
99e300ef 2599static void gen_cntlzd(DisasContext *ctx)
26d67362 2600{
9b8514e5 2601 tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
efe843d8 2602 if (unlikely(Rc(ctx->opcode) != 0)) {
26d67362 2603 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
efe843d8 2604 }
26d67362 2605}
e91d95b2
SD		 2606
2607/* cnttzd */
2608static void gen_cnttzd(DisasContext *ctx)
2609{
9b8514e5 2610 tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
e91d95b2
SD		 2611 if (unlikely(Rc(ctx->opcode) != 0)) {
2612 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2613 }
2614}
fec5c62a
RB		 2615
2616/* darn */
2617static void gen_darn(DisasContext *ctx)
2618{
2619 int l = L(ctx->opcode);
2620
7e4357f6 2621 if (l > 2) {
fec5c62a 2622 tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1);
7e4357f6 2623 } else {
f5b6daac 2624 gen_icount_io_start(ctx);
7e4357f6
RH		 2625 if (l == 0) {
2626 gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]);
2627 } else {
2628 /* Return 64-bit random for both CRN and RRN */
2629 gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]);
2630 }
fec5c62a
RB		 2631 }
2632}
d9bce9d9
JM		 2633#endif
2634
79aceca5 2635/*** Integer rotate ***/
99e300ef 2636
54623277 2637/* rlwimi & rlwimi. */
99e300ef 2638static void gen_rlwimi(DisasContext *ctx)
79aceca5 2639{
63ae0915
RH		 2640 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2641 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2642 uint32_t sh = SH(ctx->opcode);
2643 uint32_t mb = MB(ctx->opcode);
2644 uint32_t me = ME(ctx->opcode);
2645
efe843d8 2646 if (sh == (31 - me) && mb <= me) {
63ae0915 2647 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
d03ef511 2648 } else {
d03ef511 2649 target_ulong mask;
c4f6a4a3 2650 bool mask_in_32b = true;
a7812ae4 2651 TCGv t1;
63ae0915 2652
76a66253 2653#if defined(TARGET_PPC64)
d03ef511
AJ		 2654 mb += 32;
2655 me += 32;
76a66253 2656#endif
d03ef511 2657 mask = MASK(mb, me);
63ae0915 2658
c4f6a4a3
DB		 2659#if defined(TARGET_PPC64)
2660 if (mask > 0xffffffffu) {
2661 mask_in_32b = false;
2662 }
2663#endif
a7812ae4 2664 t1 = tcg_temp_new();
c4f6a4a3 2665 if (mask_in_32b) {
2e11b15d
RH		 2666 TCGv_i32 t0 = tcg_temp_new_i32();
2667 tcg_gen_trunc_tl_i32(t0, t_rs);
2668 tcg_gen_rotli_i32(t0, t0, sh);
2669 tcg_gen_extu_i32_tl(t1, t0);
2670 tcg_temp_free_i32(t0);
2671 } else {
2672#if defined(TARGET_PPC64)
2673 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
2674 tcg_gen_rotli_i64(t1, t1, sh);
2675#else
2676 g_assert_not_reached();
2677#endif
2678 }
63ae0915
RH		 2679
2680 tcg_gen_andi_tl(t1, t1, mask);
2681 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2682 tcg_gen_or_tl(t_ra, t_ra, t1);
d03ef511
AJ		 2683 tcg_temp_free(t1);
2684 }
63ae0915
RH		 2685 if (unlikely(Rc(ctx->opcode) != 0)) {
2686 gen_set_Rc0(ctx, t_ra);
2687 }
79aceca5 2688}
99e300ef 2689
54623277 2690/* rlwinm & rlwinm. */
99e300ef 2691static void gen_rlwinm(DisasContext *ctx)
79aceca5 2692{
63ae0915
RH		 2693 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2694 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
7b4d326f
RH		 2695 int sh = SH(ctx->opcode);
2696 int mb = MB(ctx->opcode);
2697 int me = ME(ctx->opcode);
2698 int len = me - mb + 1;
2699 int rsh = (32 - sh) & 31;
2700
2701 if (sh != 0 && len > 0 && me == (31 - sh)) {
2702 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
2703 } else if (me == 31 && rsh + len <= 32) {
2704 tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
d03ef511 2705 } else {
2e11b15d 2706 target_ulong mask;
c4f6a4a3 2707 bool mask_in_32b = true;
76a66253 2708#if defined(TARGET_PPC64)
d03ef511
AJ		 2709 mb += 32;
2710 me += 32;
76a66253 2711#endif
2e11b15d 2712 mask = MASK(mb, me);
c4f6a4a3
DB		 2713#if defined(TARGET_PPC64)
2714 if (mask > 0xffffffffu) {
2715 mask_in_32b = false;
2716 }
2717#endif
2718 if (mask_in_32b) {
94f040aa
VC		 2719 if (sh == 0) {
2720 tcg_gen_andi_tl(t_ra, t_rs, mask);
2721 } else {
2722 TCGv_i32 t0 = tcg_temp_new_i32();
2723 tcg_gen_trunc_tl_i32(t0, t_rs);
2724 tcg_gen_rotli_i32(t0, t0, sh);
2725 tcg_gen_andi_i32(t0, t0, mask);
2726 tcg_gen_extu_i32_tl(t_ra, t0);
2727 tcg_temp_free_i32(t0);
2728 }
2e11b15d
RH		 2729 } else {
2730#if defined(TARGET_PPC64)
2731 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
2732 tcg_gen_rotli_i64(t_ra, t_ra, sh);
2733 tcg_gen_andi_i64(t_ra, t_ra, mask);
2734#else
2735 g_assert_not_reached();
2736#endif
63ae0915
RH		 2737 }
2738 }
2739 if (unlikely(Rc(ctx->opcode) != 0)) {
2740 gen_set_Rc0(ctx, t_ra);
d03ef511 2741 }
79aceca5 2742}
99e300ef 2743
54623277 2744/* rlwnm & rlwnm. */
99e300ef 2745static void gen_rlwnm(DisasContext *ctx)
79aceca5 2746{
63ae0915
RH		 2747 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2748 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2749 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
2750 uint32_t mb = MB(ctx->opcode);
2751 uint32_t me = ME(ctx->opcode);
2e11b15d 2752 target_ulong mask;
c4f6a4a3 2753 bool mask_in_32b = true;
57fca134 2754
54843a58 2755#if defined(TARGET_PPC64)
63ae0915
RH		 2756 mb += 32;
2757 me += 32;
54843a58 2758#endif
2e11b15d
RH		 2759 mask = MASK(mb, me);
2760
c4f6a4a3
DB		 2761#if defined(TARGET_PPC64)
2762 if (mask > 0xffffffffu) {
2763 mask_in_32b = false;
2764 }
2765#endif
2766 if (mask_in_32b) {
2e11b15d
RH		 2767 TCGv_i32 t0 = tcg_temp_new_i32();
2768 TCGv_i32 t1 = tcg_temp_new_i32();
2769 tcg_gen_trunc_tl_i32(t0, t_rb);
2770 tcg_gen_trunc_tl_i32(t1, t_rs);
2771 tcg_gen_andi_i32(t0, t0, 0x1f);
2772 tcg_gen_rotl_i32(t1, t1, t0);
2773 tcg_gen_extu_i32_tl(t_ra, t1);
2774 tcg_temp_free_i32(t0);
2775 tcg_temp_free_i32(t1);
2776 } else {
2777#if defined(TARGET_PPC64)
2778 TCGv_i64 t0 = tcg_temp_new_i64();
2779 tcg_gen_andi_i64(t0, t_rb, 0x1f);
2780 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
2781 tcg_gen_rotl_i64(t_ra, t_ra, t0);
2782 tcg_temp_free_i64(t0);
2783#else
2784 g_assert_not_reached();
2785#endif
2786 }
57fca134 2787
2e11b15d 2788 tcg_gen_andi_tl(t_ra, t_ra, mask);
63ae0915
RH		 2789
2790 if (unlikely(Rc(ctx->opcode) != 0)) {
2791 gen_set_Rc0(ctx, t_ra);
79aceca5 2792 }
79aceca5
FB		 2793}
2794
d9bce9d9
JM		 2795#if defined(TARGET_PPC64)
2796#define GEN_PPC64_R2(name, opc1, opc2) \
e8eaa2c0 2797static void glue(gen_, name##0)(DisasContext *ctx) \
d9bce9d9
JM		 2798{ \
2799 gen_##name(ctx, 0); \
2800} \
e8eaa2c0
BS		 2801 \
2802static void glue(gen_, name##1)(DisasContext *ctx) \
d9bce9d9
JM		 2803{ \
2804 gen_##name(ctx, 1); \
2805}
2806#define GEN_PPC64_R4(name, opc1, opc2) \
e8eaa2c0 2807static void glue(gen_, name##0)(DisasContext *ctx) \
d9bce9d9
JM		 2808{ \
2809 gen_##name(ctx, 0, 0); \
2810} \
e8eaa2c0
BS		 2811 \
2812static void glue(gen_, name##1)(DisasContext *ctx) \
d9bce9d9
JM		 2813{ \
2814 gen_##name(ctx, 0, 1); \
2815} \
e8eaa2c0
BS		 2816 \
2817static void glue(gen_, name##2)(DisasContext *ctx) \
d9bce9d9
JM		 2818{ \
2819 gen_##name(ctx, 1, 0); \
2820} \
e8eaa2c0
BS		 2821 \
2822static void glue(gen_, name##3)(DisasContext *ctx) \
d9bce9d9
JM		 2823{ \
2824 gen_##name(ctx, 1, 1); \
2825}
51789c41 2826
a7b2c8b9 2827static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
51789c41 2828{
a7b2c8b9
RH		 2829 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2830 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
7b4d326f
RH		 2831 int len = me - mb + 1;
2832 int rsh = (64 - sh) & 63;
a7b2c8b9 2833
7b4d326f
RH		 2834 if (sh != 0 && len > 0 && me == (63 - sh)) {
2835 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
2836 } else if (me == 63 && rsh + len <= 64) {
2837 tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
d03ef511 2838 } else {
a7b2c8b9
RH		 2839 tcg_gen_rotli_tl(t_ra, t_rs, sh);
2840 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2841 }
2842 if (unlikely(Rc(ctx->opcode) != 0)) {
2843 gen_set_Rc0(ctx, t_ra);
51789c41 2844 }
51789c41 2845}
a7b2c8b9 2846
d9bce9d9 2847/* rldicl - rldicl. */
636aa200 2848static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
d9bce9d9 2849{
51789c41 2850 uint32_t sh, mb;
d9bce9d9 2851
9d53c753
JM		 2852 sh = SH(ctx->opcode) | (shn << 5);
2853 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 2854 gen_rldinm(ctx, mb, 63, sh);
d9bce9d9 2855}
51789c41 2856GEN_PPC64_R4(rldicl, 0x1E, 0x00);
a7b2c8b9 2857
d9bce9d9 2858/* rldicr - rldicr. */
636aa200 2859static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
d9bce9d9 2860{
51789c41 2861 uint32_t sh, me;
d9bce9d9 2862
9d53c753
JM		 2863 sh = SH(ctx->opcode) | (shn << 5);
2864 me = MB(ctx->opcode) | (men << 5);
51789c41 2865 gen_rldinm(ctx, 0, me, sh);
d9bce9d9 2866}
51789c41 2867GEN_PPC64_R4(rldicr, 0x1E, 0x02);
a7b2c8b9 2868
d9bce9d9 2869/* rldic - rldic. */
636aa200 2870static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
d9bce9d9 2871{
51789c41 2872 uint32_t sh, mb;
d9bce9d9 2873
9d53c753
JM		 2874 sh = SH(ctx->opcode) | (shn << 5);
2875 mb = MB(ctx->opcode) | (mbn << 5);
51789c41
JM		 2876 gen_rldinm(ctx, mb, 63 - sh, sh);
2877}
2878GEN_PPC64_R4(rldic, 0x1E, 0x04);
2879
a7b2c8b9 2880static void gen_rldnm(DisasContext *ctx, int mb, int me)
51789c41 2881{
a7b2c8b9
RH		 2882 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2883 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2884 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
54843a58 2885 TCGv t0;
d03ef511 2886
a7812ae4 2887 t0 = tcg_temp_new();
a7b2c8b9
RH		 2888 tcg_gen_andi_tl(t0, t_rb, 0x3f);
2889 tcg_gen_rotl_tl(t_ra, t_rs, t0);
54843a58 2890 tcg_temp_free(t0);
a7b2c8b9
RH		 2891
2892 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2893 if (unlikely(Rc(ctx->opcode) != 0)) {
2894 gen_set_Rc0(ctx, t_ra);
2895 }
d9bce9d9 2896}
51789c41 2897
d9bce9d9 2898/* rldcl - rldcl. */
636aa200 2899static inline void gen_rldcl(DisasContext *ctx, int mbn)
d9bce9d9 2900{
51789c41 2901 uint32_t mb;
d9bce9d9 2902
9d53c753 2903 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 2904 gen_rldnm(ctx, mb, 63);
d9bce9d9 2905}
36081602 2906GEN_PPC64_R2(rldcl, 0x1E, 0x08);
a7b2c8b9 2907
d9bce9d9 2908/* rldcr - rldcr. */
636aa200 2909static inline void gen_rldcr(DisasContext *ctx, int men)
d9bce9d9 2910{
51789c41 2911 uint32_t me;
d9bce9d9 2912
9d53c753 2913 me = MB(ctx->opcode) | (men << 5);
51789c41 2914 gen_rldnm(ctx, 0, me);
d9bce9d9 2915}
36081602 2916GEN_PPC64_R2(rldcr, 0x1E, 0x09);
a7b2c8b9 2917
d9bce9d9 2918/* rldimi - rldimi. */
a7b2c8b9 2919static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
d9bce9d9 2920{
a7b2c8b9
RH		 2921 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2922 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2923 uint32_t sh = SH(ctx->opcode) | (shn << 5);
2924 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
2925 uint32_t me = 63 - sh;
d9bce9d9 2926
a7b2c8b9
RH		 2927 if (mb <= me) {
2928 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
d03ef511 2929 } else {
a7b2c8b9
RH		 2930 target_ulong mask = MASK(mb, me);
2931 TCGv t1 = tcg_temp_new();
d03ef511 2932
a7b2c8b9
RH		 2933 tcg_gen_rotli_tl(t1, t_rs, sh);
2934 tcg_gen_andi_tl(t1, t1, mask);
2935 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2936 tcg_gen_or_tl(t_ra, t_ra, t1);
d03ef511 2937 tcg_temp_free(t1);
51789c41 2938 }
a7b2c8b9
RH		 2939 if (unlikely(Rc(ctx->opcode) != 0)) {
2940 gen_set_Rc0(ctx, t_ra);
2941 }
d9bce9d9 2942}
36081602 2943GEN_PPC64_R4(rldimi, 0x1E, 0x06);
d9bce9d9
JM		 2944#endif
2945
79aceca5 2946/*** Integer shift ***/
99e300ef 2947
54623277 2948/* slw & slw. */
99e300ef 2949static void gen_slw(DisasContext *ctx)
26d67362 2950{
7fd6bf7d 2951 TCGv t0, t1;
26d67362 2952
7fd6bf7d
AJ		 2953 t0 = tcg_temp_new();
2954 /* AND rS with a mask that is 0 when rB >= 0x20 */
2955#if defined(TARGET_PPC64)
2956 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2957 tcg_gen_sari_tl(t0, t0, 0x3f);
2958#else
2959 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2960 tcg_gen_sari_tl(t0, t0, 0x1f);
2961#endif
2962 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2963 t1 = tcg_temp_new();
2964 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2965 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2966 tcg_temp_free(t1);
fea0c503 2967 tcg_temp_free(t0);
7fd6bf7d 2968 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
efe843d8 2969 if (unlikely(Rc(ctx->opcode) != 0)) {
26d67362 2970 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
efe843d8 2971 }
26d67362 2972}
99e300ef 2973
54623277 2974/* sraw & sraw. */
99e300ef 2975static void gen_sraw(DisasContext *ctx)
26d67362 2976{
d15f74fb 2977 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
a7812ae4 2978 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
efe843d8 2979 if (unlikely(Rc(ctx->opcode) != 0)) {
26d67362 2980 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
efe843d8 2981 }
26d67362 2982}
99e300ef 2983
54623277 2984/* srawi & srawi. */
99e300ef 2985static void gen_srawi(DisasContext *ctx)
79aceca5 2986{
26d67362 2987 int sh = SH(ctx->opcode);
ba4af3e4
RH		 2988 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2989 TCGv src = cpu_gpr[rS(ctx->opcode)];
2990 if (sh == 0) {
34a0fad1 2991 tcg_gen_ext32s_tl(dst, src);
da91a00f 2992 tcg_gen_movi_tl(cpu_ca, 0);
af1c259f
SD		 2993 if (is_isa300(ctx)) {
2994 tcg_gen_movi_tl(cpu_ca32, 0);
2995 }
26d67362 2996 } else {
ba4af3e4
RH		 2997 TCGv t0;
2998 tcg_gen_ext32s_tl(dst, src);
2999 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
3000 t0 = tcg_temp_new();
3001 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
3002 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
3003 tcg_temp_free(t0);
3004 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
af1c259f
SD		 3005 if (is_isa300(ctx)) {
3006 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
3007 }
ba4af3e4
RH		 3008 tcg_gen_sari_tl(dst, dst, sh);
3009 }
3010 if (unlikely(Rc(ctx->opcode) != 0)) {
3011 gen_set_Rc0(ctx, dst);
d9bce9d9 3012 }
79aceca5 3013}
99e300ef 3014
54623277 3015/* srw & srw. */
99e300ef 3016static void gen_srw(DisasContext *ctx)
26d67362 3017{
fea0c503 3018 TCGv t0, t1;
d9bce9d9 3019
7fd6bf7d
AJ		 3020 t0 = tcg_temp_new();
3021 /* AND rS with a mask that is 0 when rB >= 0x20 */
3022#if defined(TARGET_PPC64)
3023 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
3024 tcg_gen_sari_tl(t0, t0, 0x3f);
3025#else
3026 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
3027 tcg_gen_sari_tl(t0, t0, 0x1f);
3028#endif
3029 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
3030 tcg_gen_ext32u_tl(t0, t0);
a7812ae4 3031 t1 = tcg_temp_new();
7fd6bf7d
AJ		 3032 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
3033 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
fea0c503 3034 tcg_temp_free(t1);
fea0c503 3035 tcg_temp_free(t0);
efe843d8 3036 if (unlikely(Rc(ctx->opcode) != 0)) {
26d67362 3037 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
efe843d8 3038 }
26d67362 3039}
54623277 3040
d9bce9d9
JM		 3041#if defined(TARGET_PPC64)
3042/* sld & sld. */
99e300ef 3043static void gen_sld(DisasContext *ctx)
26d67362 3044{
7fd6bf7d 3045 TCGv t0, t1;
26d67362 3046
7fd6bf7d
AJ		 3047 t0 = tcg_temp_new();
3048 /* AND rS with a mask that is 0 when rB >= 0x40 */
3049 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
3050 tcg_gen_sari_tl(t0, t0, 0x3f);
3051 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
3052 t1 = tcg_temp_new();
3053 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
3054 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
3055 tcg_temp_free(t1);
fea0c503 3056 tcg_temp_free(t0);
efe843d8 3057 if (unlikely(Rc(ctx->opcode) != 0)) {
26d67362 3058 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
efe843d8 3059 }
26d67362 3060}
99e300ef 3061
54623277 3062/* srad & srad. */
99e300ef 3063static void gen_srad(DisasContext *ctx)
26d67362 3064{
d15f74fb 3065 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
a7812ae4 3066 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
efe843d8 3067 if (unlikely(Rc(ctx->opcode) != 0)) {
26d67362 3068 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
efe843d8 3069 }
26d67362 3070}
d9bce9d9 3071/* sradi & sradi. */
636aa200 3072static inline void gen_sradi(DisasContext *ctx, int n)
d9bce9d9 3073{
26d67362 3074 int sh = SH(ctx->opcode) + (n << 5);
ba4af3e4
RH		 3075 TCGv dst = cpu_gpr[rA(ctx->opcode)];
3076 TCGv src = cpu_gpr[rS(ctx->opcode)];
3077 if (sh == 0) {
3078 tcg_gen_mov_tl(dst, src);
da91a00f 3079 tcg_gen_movi_tl(cpu_ca, 0);
af1c259f
SD		 3080 if (is_isa300(ctx)) {
3081 tcg_gen_movi_tl(cpu_ca32, 0);
3082 }
26d67362 3083 } else {
ba4af3e4
RH		 3084 TCGv t0;
3085 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
3086 t0 = tcg_temp_new();
3087 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
3088 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
3089 tcg_temp_free(t0);
3090 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
af1c259f
SD		 3091 if (is_isa300(ctx)) {
3092 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
3093 }
ba4af3e4
RH		 3094 tcg_gen_sari_tl(dst, src, sh);
3095 }
3096 if (unlikely(Rc(ctx->opcode) != 0)) {
3097 gen_set_Rc0(ctx, dst);
d9bce9d9 3098 }
d9bce9d9 3099}
e8eaa2c0
BS		 3100
3101static void gen_sradi0(DisasContext *ctx)
d9bce9d9
JM		 3102{
3103 gen_sradi(ctx, 0);
3104}
e8eaa2c0
BS		 3105
3106static void gen_sradi1(DisasContext *ctx)
d9bce9d9
JM		 3107{
3108 gen_sradi(ctx, 1);
3109}
99e300ef 3110
787bbe37
ND		 3111/* extswsli & extswsli. */
3112static inline void gen_extswsli(DisasContext *ctx, int n)
3113{
3114 int sh = SH(ctx->opcode) + (n << 5);
3115 TCGv dst = cpu_gpr[rA(ctx->opcode)];
3116 TCGv src = cpu_gpr[rS(ctx->opcode)];
3117
3118 tcg_gen_ext32s_tl(dst, src);
3119 tcg_gen_shli_tl(dst, dst, sh);
3120 if (unlikely(Rc(ctx->opcode) != 0)) {
3121 gen_set_Rc0(ctx, dst);
3122 }
3123}
3124
3125static void gen_extswsli0(DisasContext *ctx)
3126{
3127 gen_extswsli(ctx, 0);
3128}
3129
3130static void gen_extswsli1(DisasContext *ctx)
3131{
3132 gen_extswsli(ctx, 1);
3133}
3134
54623277 3135/* srd & srd. */
99e300ef 3136static void gen_srd(DisasContext *ctx)
26d67362 3137{
7fd6bf7d 3138 TCGv t0, t1;
26d67362 3139
7fd6bf7d
AJ		 3140 t0 = tcg_temp_new();
3141 /* AND rS with a mask that is 0 when rB >= 0x40 */
3142 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
3143 tcg_gen_sari_tl(t0, t0, 0x3f);
3144 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
3145 t1 = tcg_temp_new();
3146 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
3147 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
3148 tcg_temp_free(t1);
fea0c503 3149 tcg_temp_free(t0);
efe843d8 3150 if (unlikely(Rc(ctx->opcode) != 0)) {
26d67362 3151 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
efe843d8 3152 }
26d67362 3153}
d9bce9d9 3154#endif
79aceca5 3155
76a66253
JM		 3156/*** Addressing modes ***/
3157/* Register indirect with immediate index : EA = (rA|0) + SIMM */
636aa200
BS		 3158static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
3159 target_long maskl)
76a66253
JM		 3160{
3161 target_long simm = SIMM(ctx->opcode);
3162
be147d08 3163 simm &= ~maskl;
76db3ba4 3164 if (rA(ctx->opcode) == 0) {
c791fe84
RH		 3165 if (NARROW_MODE(ctx)) {
3166 simm = (uint32_t)simm;
3167 }
e2be8d8d 3168 tcg_gen_movi_tl(EA, simm);
76db3ba4 3169 } else if (likely(simm != 0)) {
e2be8d8d 3170 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
c791fe84 3171 if (NARROW_MODE(ctx)) {
76db3ba4
AJ		 3172 tcg_gen_ext32u_tl(EA, EA);
3173 }
76db3ba4 3174 } else {
c791fe84 3175 if (NARROW_MODE(ctx)) {
76db3ba4 3176 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
c791fe84
RH		 3177 } else {
3178 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
3179 }
76db3ba4 3180 }
76a66253
JM		 3181}
3182
636aa200 3183static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
76a66253 3184{
76db3ba4 3185 if (rA(ctx->opcode) == 0) {
c791fe84 3186 if (NARROW_MODE(ctx)) {
76db3ba4 3187 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
c791fe84
RH		 3188 } else {
3189 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
3190 }
76db3ba4 3191 } else {
e2be8d8d 3192 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
c791fe84 3193 if (NARROW_MODE(ctx)) {
76db3ba4
AJ		 3194 tcg_gen_ext32u_tl(EA, EA);
3195 }
76db3ba4 3196 }
76a66253
JM		 3197}
3198
636aa200 3199static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
76a66253 3200{
76db3ba4 3201 if (rA(ctx->opcode) == 0) {
e2be8d8d 3202 tcg_gen_movi_tl(EA, 0);
c791fe84
RH		 3203 } else if (NARROW_MODE(ctx)) {
3204 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76db3ba4 3205 } else {
c791fe84 3206 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76db3ba4
AJ		 3207 }
3208}
3209
636aa200
BS		 3210static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
3211 target_long val)
76db3ba4
AJ		 3212{
3213 tcg_gen_addi_tl(ret, arg1, val);
c791fe84 3214 if (NARROW_MODE(ctx)) {
76db3ba4
AJ		 3215 tcg_gen_ext32u_tl(ret, ret);
3216 }
76a66253
JM		 3217}
3218
65f2475f
BH		 3219static inline void gen_align_no_le(DisasContext *ctx)
3220{
3221 gen_exception_err(ctx, POWERPC_EXCP_ALIGN,
3222 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE);
3223}
3224
eb63efd9
FEV		 3225static TCGv do_ea_calc(DisasContext *ctx, int ra, TCGv displ)
3226{
3227 TCGv ea = tcg_temp_new();
3228 if (ra) {
3229 tcg_gen_add_tl(ea, cpu_gpr[ra], displ);
3230 } else {
3231 tcg_gen_mov_tl(ea, displ);
3232 }
3233 if (NARROW_MODE(ctx)) {
3234 tcg_gen_ext32u_tl(ea, ea);
3235 }
3236 return ea;
3237}
3238
7863667f 3239/*** Integer load ***/
09bfe50d 3240#define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask)
ff5f3981 3241#define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP))
b61f2753 3242
09bfe50d
ND		 3243#define GEN_QEMU_LOAD_TL(ldop, op) \
3244static void glue(gen_qemu_, ldop)(DisasContext *ctx, \
3245 TCGv val, \
3246 TCGv addr) \
3247{ \
3248 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \
b61f2753
AJ		 3249}
3250
09bfe50d
ND		 3251GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB))
3252GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW))
3253GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW))
3254GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL))
3255GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL))
f976b09e 3256
ff5f3981
ND		 3257GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW))
3258GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL))
3259
09bfe50d
ND		 3260#define GEN_QEMU_LOAD_64(ldop, op) \
3261static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \
3262 TCGv_i64 val, \
3263 TCGv addr) \
3264{ \
3265 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \
b61f2753
AJ		 3266}
3267
740ae9a2
ND		 3268GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB))
3269GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW))
09bfe50d
ND		 3270GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL))
3271GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL))
4f364fe7 3272GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q))
b61f2753 3273
ff5f3981
ND		 3274#if defined(TARGET_PPC64)
3275GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q))
3276#endif
3277
761a89c6
ND		 3278#define GEN_QEMU_STORE_TL(stop, op) \
3279static void glue(gen_qemu_, stop)(DisasContext *ctx, \
3280 TCGv val, \
3281 TCGv addr) \
3282{ \
3283 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
b61f2753
AJ		 3284}
3285
e8f4c8d6 3286#if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY)
761a89c6 3287GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB))
e8f4c8d6 3288#endif
761a89c6
ND		 3289GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW))
3290GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL))
b61f2753 3291
804108aa
ND		 3292GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW))
3293GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL))
3294
761a89c6
ND		 3295#define GEN_QEMU_STORE_64(stop, op) \
3296static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \
3297 TCGv_i64 val, \
3298 TCGv addr) \
3299{ \
3300 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \
b61f2753
AJ		 3301}
3302
ddb9ac50
ND		 3303GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB))
3304GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW))
761a89c6 3305GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL))
2468f23d 3306GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q))
b61f2753 3307
804108aa
ND		 3308#if defined(TARGET_PPC64)
3309GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q))
3310#endif
3311
b7815375 3312#define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
99e300ef 3313static void glue(gen_, name##x)(DisasContext *ctx) \
79aceca5 3314{ \
76db3ba4 3315 TCGv EA; \
b7815375 3316 chk; \
76db3ba4
AJ		 3317 gen_set_access_type(ctx, ACCESS_INT); \
3318 EA = tcg_temp_new(); \
3319 gen_addr_reg_index(ctx, EA); \
3320 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753 3321 tcg_temp_free(EA); \
79aceca5 3322}
b7815375 3323
cd6e9320 3324#define GEN_LDX(name, ldop, opc2, opc3, type) \
b7815375
BH		 3325 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
3326
3327#define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
3328 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
79aceca5 3329
50728199
RK		 3330#define GEN_LDEPX(name, ldop, opc2, opc3) \
3331static void glue(gen_, name##epx)(DisasContext *ctx) \
3332{ \
3333 TCGv EA; \
3334 CHK_SV; \
3335 gen_set_access_type(ctx, ACCESS_INT); \
3336 EA = tcg_temp_new(); \
3337 gen_addr_reg_index(ctx, EA); \
3338 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\
3339 tcg_temp_free(EA); \
3340}
3341
3342GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02)
3343GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08)
3344GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00)
3345#if defined(TARGET_PPC64)
3346GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00)
3347#endif
3348
d9bce9d9 3349#if defined(TARGET_PPC64)
b7815375 3350/* CI load/store variants */
4f364fe7 3351GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
b7815375
BH		 3352GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
3353GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
3354GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
d9bce9d9 3355#endif
79aceca5
FB		 3356
3357/*** Integer store ***/
b7815375 3358#define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
cd6e9320 3359static void glue(gen_, name##x)(DisasContext *ctx) \
79aceca5 3360{ \
76db3ba4 3361 TCGv EA; \
b7815375 3362 chk; \
76db3ba4
AJ		 3363 gen_set_access_type(ctx, ACCESS_INT); \
3364 EA = tcg_temp_new(); \
3365 gen_addr_reg_index(ctx, EA); \
3366 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753 3367 tcg_temp_free(EA); \
79aceca5 3368}
cd6e9320 3369#define GEN_STX(name, stop, opc2, opc3, type) \
b7815375
BH		 3370 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
3371
3372#define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
3373 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
79aceca5 3374
50728199
RK		 3375#define GEN_STEPX(name, stop, opc2, opc3) \
3376static void glue(gen_, name##epx)(DisasContext *ctx) \
3377{ \
3378 TCGv EA; \
3379 CHK_SV; \
3380 gen_set_access_type(ctx, ACCESS_INT); \
3381 EA = tcg_temp_new(); \
3382 gen_addr_reg_index(ctx, EA); \
3383 tcg_gen_qemu_st_tl( \
3384 cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \
3385 tcg_temp_free(EA); \
3386}
3387
3388GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06)
3389GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C)
3390GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04)
3391#if defined(TARGET_PPC64)
3392GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04)
3393#endif
3394
d9bce9d9 3395#if defined(TARGET_PPC64)
2468f23d 3396GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
b7815375
BH		 3397GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
3398GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
3399GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
d9bce9d9 3400#endif
79aceca5 3401/*** Integer load and store with byte reverse ***/
e22c357b 3402
79aceca5 3403/* lhbrx */
0c8aacd4 3404GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
b61f2753 3405
79aceca5 3406/* lwbrx */
0c8aacd4 3407GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
b61f2753 3408
cd6e9320
TH		 3409#if defined(TARGET_PPC64)
3410/* ldbrx */
ff5f3981 3411GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
804108aa
ND		 3412/* stdbrx */
3413GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
cd6e9320
TH		 3414#endif /* TARGET_PPC64 */
3415
79aceca5 3416/* sthbrx */
0c8aacd4 3417GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
79aceca5 3418/* stwbrx */
0c8aacd4 3419GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
79aceca5
FB		 3420
3421/*** Integer load and store multiple ***/
99e300ef 3422
54623277 3423/* lmw */
99e300ef 3424static void gen_lmw(DisasContext *ctx)
79aceca5 3425{
76db3ba4
AJ		 3426 TCGv t0;
3427 TCGv_i32 t1;
5817355e
BH		 3428
3429 if (ctx->le_mode) {
3430 gen_align_no_le(ctx);
3431 return;
3432 }
76db3ba4 3433 gen_set_access_type(ctx, ACCESS_INT);
76db3ba4
AJ		 3434 t0 = tcg_temp_new();
3435 t1 = tcg_const_i32(rD(ctx->opcode));
3436 gen_addr_imm_index(ctx, t0, 0);
2f5a189c 3437 gen_helper_lmw(cpu_env, t0, t1);
ff4a62cd
AJ		 3438 tcg_temp_free(t0);
3439 tcg_temp_free_i32(t1);
79aceca5
FB		 3440}
3441
3442/* stmw */
99e300ef 3443static void gen_stmw(DisasContext *ctx)
79aceca5 3444{
76db3ba4
AJ		 3445 TCGv t0;
3446 TCGv_i32 t1;
5817355e
BH		 3447
3448 if (ctx->le_mode) {
3449 gen_align_no_le(ctx);
3450 return;
3451 }
76db3ba4 3452 gen_set_access_type(ctx, ACCESS_INT);
76db3ba4
AJ		 3453 t0 = tcg_temp_new();
3454 t1 = tcg_const_i32(rS(ctx->opcode));
3455 gen_addr_imm_index(ctx, t0, 0);
2f5a189c 3456 gen_helper_stmw(cpu_env, t0, t1);
ff4a62cd
AJ		 3457 tcg_temp_free(t0);
3458 tcg_temp_free_i32(t1);
79aceca5
FB		 3459}
3460
3461/*** Integer load and store strings ***/
54623277 3462
79aceca5 3463/* lswi */
efe843d8
DG		 3464/*
3465 * PowerPC32 specification says we must generate an exception if rA is
3466 * in the range of registers to be loaded. In an other hand, IBM says
3467 * this is valid, but rA won't be loaded. For now, I'll follow the
3468 * spec...
9a64fbe4 3469 */
99e300ef 3470static void gen_lswi(DisasContext *ctx)
79aceca5 3471{
dfbc799d
AJ		 3472 TCGv t0;
3473 TCGv_i32 t1, t2;
79aceca5
FB		 3474 int nb = NB(ctx->opcode);
3475 int start = rD(ctx->opcode);
9a64fbe4 3476 int ra = rA(ctx->opcode);
79aceca5
FB		 3477 int nr;
3478
5817355e
BH		 3479 if (ctx->le_mode) {
3480 gen_align_no_le(ctx);
3481 return;
3482 }
efe843d8 3483 if (nb == 0) {
79aceca5 3484 nb = 32;
efe843d8 3485 }
f0704d78 3486 nr = DIV_ROUND_UP(nb, 4);
afbee712 3487 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
e06fcd75 3488 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
9fddaa0c 3489 return;
297d8e62 3490 }
76db3ba4 3491 gen_set_access_type(ctx, ACCESS_INT);
dfbc799d 3492 t0 = tcg_temp_new();
76db3ba4 3493 gen_addr_register(ctx, t0);
dfbc799d
AJ		 3494 t1 = tcg_const_i32(nb);
3495 t2 = tcg_const_i32(start);
2f5a189c 3496 gen_helper_lsw(cpu_env, t0, t1, t2);
dfbc799d
AJ		 3497 tcg_temp_free(t0);
3498 tcg_temp_free_i32(t1);
3499 tcg_temp_free_i32(t2);
79aceca5
FB		 3500}
3501
3502/* lswx */
99e300ef 3503static void gen_lswx(DisasContext *ctx)
79aceca5 3504{
76db3ba4
AJ		 3505 TCGv t0;
3506 TCGv_i32 t1, t2, t3;
5817355e
BH		 3507
3508 if (ctx->le_mode) {
3509 gen_align_no_le(ctx);
3510 return;
3511 }
76db3ba4 3512 gen_set_access_type(ctx, ACCESS_INT);
76db3ba4
AJ		 3513 t0 = tcg_temp_new();
3514 gen_addr_reg_index(ctx, t0);
3515 t1 = tcg_const_i32(rD(ctx->opcode));
3516 t2 = tcg_const_i32(rA(ctx->opcode));
3517 t3 = tcg_const_i32(rB(ctx->opcode));
2f5a189c 3518 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
dfbc799d
AJ		 3519 tcg_temp_free(t0);
3520 tcg_temp_free_i32(t1);
3521 tcg_temp_free_i32(t2);
3522 tcg_temp_free_i32(t3);
79aceca5
FB		 3523}
3524
3525/* stswi */
99e300ef 3526static void gen_stswi(DisasContext *ctx)
79aceca5 3527{
76db3ba4
AJ		 3528 TCGv t0;
3529 TCGv_i32 t1, t2;
4b3686fa 3530 int nb = NB(ctx->opcode);
5817355e
BH		 3531
3532 if (ctx->le_mode) {
3533 gen_align_no_le(ctx);
3534 return;
3535 }
76db3ba4 3536 gen_set_access_type(ctx, ACCESS_INT);
76db3ba4
AJ		 3537 t0 = tcg_temp_new();
3538 gen_addr_register(ctx, t0);
efe843d8 3539 if (nb == 0) {
4b3686fa 3540 nb = 32;
efe843d8 3541 }
dfbc799d 3542 t1 = tcg_const_i32(nb);
76db3ba4 3543 t2 = tcg_const_i32(rS(ctx->opcode));
2f5a189c 3544 gen_helper_stsw(cpu_env, t0, t1, t2);
dfbc799d
AJ		 3545 tcg_temp_free(t0);
3546 tcg_temp_free_i32(t1);
3547 tcg_temp_free_i32(t2);
79aceca5
FB		 3548}
3549
3550/* stswx */
99e300ef 3551static void gen_stswx(DisasContext *ctx)
79aceca5 3552{
76db3ba4
AJ		 3553 TCGv t0;
3554 TCGv_i32 t1, t2;
5817355e
BH		 3555
3556 if (ctx->le_mode) {
3557 gen_align_no_le(ctx);
3558 return;
3559 }
76db3ba4 3560 gen_set_access_type(ctx, ACCESS_INT);
76db3ba4
AJ		 3561 t0 = tcg_temp_new();
3562 gen_addr_reg_index(ctx, t0);
3563 t1 = tcg_temp_new_i32();
dfbc799d
AJ		 3564 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3565 tcg_gen_andi_i32(t1, t1, 0x7F);
76db3ba4 3566 t2 = tcg_const_i32(rS(ctx->opcode));
2f5a189c 3567 gen_helper_stsw(cpu_env, t0, t1, t2);
dfbc799d
AJ		 3568 tcg_temp_free(t0);
3569 tcg_temp_free_i32(t1);
3570 tcg_temp_free_i32(t2);
79aceca5
FB		 3571}
3572
3573/*** Memory synchronisation ***/
3574/* eieio */
99e300ef 3575static void gen_eieio(DisasContext *ctx)
79aceca5 3576{
c8fd8373
CLG		 3577 TCGBar bar = TCG_MO_LD_ST;
3578
3579 /*
3580 * POWER9 has a eieio instruction variant using bit 6 as a hint to
3581 * tell the CPU it is a store-forwarding barrier.
3582 */
3583 if (ctx->opcode & 0x2000000) {
3584 /*
3585 * ISA says that "Reserved fields in instructions are ignored
3586 * by the processor". So ignore the bit 6 on non-POWER9 CPU but
3587 * as this is not an instruction software should be using,
3588 * complain to the user.
3589 */
3590 if (!(ctx->insns_flags2 & PPC2_ISA300)) {
3591 qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @"
2c2bcb1b 3592 TARGET_FMT_lx "\n", ctx->cia);
c8fd8373
CLG		 3593 } else {
3594 bar = TCG_MO_ST_LD;
3595 }
3596 }
3597
3598 tcg_gen_mb(bar | TCG_BAR_SC);
79aceca5
FB		 3599}
3600
c5a8d8f3 3601#if !defined(CONFIG_USER_ONLY)
e3cffe6f 3602static inline void gen_check_tlb_flush(DisasContext *ctx, bool global)
cd0c6f47 3603{
c5a8d8f3
BH		 3604 TCGv_i32 t;
3605 TCGLabel *l;
cd0c6f47 3606
c5a8d8f3
BH		 3607 if (!ctx->lazy_tlb_flush) {
3608 return;
3609 }
3610 l = gen_new_label();
3611 t = tcg_temp_new_i32();
cd0c6f47
BH		 3612 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
3613 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
e3cffe6f
ND		 3614 if (global) {
3615 gen_helper_check_tlb_flush_global(cpu_env);
3616 } else {
3617 gen_helper_check_tlb_flush_local(cpu_env);
3618 }
cd0c6f47
BH		 3619 gen_set_label(l);
3620 tcg_temp_free_i32(t);
3621}
3622#else
e3cffe6f 3623static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { }
cd0c6f47
BH		 3624#endif
3625
79aceca5 3626/* isync */
99e300ef 3627static void gen_isync(DisasContext *ctx)
79aceca5 3628{
cd0c6f47
BH		 3629 /*
3630 * We need to check for a pending TLB flush. This can only happen in
3631 * kernel mode however so check MSR_PR
3632 */
3633 if (!ctx->pr) {
e3cffe6f 3634 gen_check_tlb_flush(ctx, false);
cd0c6f47 3635 }
4771df23 3636 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
d736de8f 3637 ctx->base.is_jmp = DISAS_EXIT_UPDATE;
79aceca5
FB		 3638}
3639
48793c95
ND		 3640#define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE))
3641
14776ab5 3642static void gen_load_locked(DisasContext *ctx, MemOp memop)
2a4e6c1b
RH		 3643{
3644 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3645 TCGv t0 = tcg_temp_new();
3646
3647 gen_set_access_type(ctx, ACCESS_RES);
3648 gen_addr_reg_index(ctx, t0);
3649 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN);
3650 tcg_gen_mov_tl(cpu_reserve, t0);
3651 tcg_gen_mov_tl(cpu_reserve_val, gpr);
3652 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
3653 tcg_temp_free(t0);
3654}
3655
3656#define LARX(name, memop) \
3657static void gen_##name(DisasContext *ctx) \
3658{ \
3659 gen_load_locked(ctx, memop); \
79aceca5
FB		 3660}
3661
5c77a786 3662/* lwarx */
48793c95
ND		 3663LARX(lbarx, DEF_MEMOP(MO_UB))
3664LARX(lharx, DEF_MEMOP(MO_UW))
3665LARX(lwarx, DEF_MEMOP(MO_UL))
5c77a786 3666
14776ab5 3667static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop,
20923c1d
RH		 3668 TCGv EA, TCGCond cond, int addend)
3669{
3670 TCGv t = tcg_temp_new();
3671 TCGv t2 = tcg_temp_new();
3672 TCGv u = tcg_temp_new();
3673
3674 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
3675 tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop));
3676 tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop);
3677 tcg_gen_addi_tl(u, t, addend);
3678
3679 /* E.g. for fetch and increment bounded... */
3680 /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */
3681 tcg_gen_movcond_tl(cond, u, t, t2, u, t);
3682 tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop);
3683
3684 /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */
3685 tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1));
3686 tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u);
3687
3688 tcg_temp_free(t);
3689 tcg_temp_free(t2);
3690 tcg_temp_free(u);
3691}
3692
14776ab5 3693static void gen_ld_atomic(DisasContext *ctx, MemOp memop)
20ba8504
RH		 3694{
3695 uint32_t gpr_FC = FC(ctx->opcode);
3696 TCGv EA = tcg_temp_new();
20923c1d
RH		 3697 int rt = rD(ctx->opcode);
3698 bool need_serial;
20ba8504
RH		 3699 TCGv src, dst;
3700
3701 gen_addr_register(ctx, EA);
20923c1d
RH		 3702 dst = cpu_gpr[rt];
3703 src = cpu_gpr[(rt + 1) & 31];
20ba8504 3704
20923c1d 3705 need_serial = false;
20ba8504
RH		 3706 memop |= MO_ALIGN;
3707 switch (gpr_FC) {
3708 case 0: /* Fetch and add */
3709 tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop);
3710 break;
3711 case 1: /* Fetch and xor */
3712 tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop);
3713 break;
3714 case 2: /* Fetch and or */
3715 tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop);
3716 break;
3717 case 3: /* Fetch and 'and' */
3718 tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop);
3719 break;
20ba8504 3720 case 4: /* Fetch and max unsigned */
b8ce0f86
RH		 3721 tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop);
3722 break;
20ba8504 3723 case 5: /* Fetch and max signed */
b8ce0f86
RH		 3724 tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop);
3725 break;
20ba8504 3726 case 6: /* Fetch and min unsigned */
b8ce0f86
RH		 3727 tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop);
3728 break;
20ba8504 3729 case 7: /* Fetch and min signed */
b8ce0f86
RH		 3730 tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop);
3731 break;
3732 case 8: /* Swap */
3733 tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop);
3734 break;
20923c1d
RH		 3735
3736 case 16: /* Compare and swap not equal */
3737 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3738 need_serial = true;
3739 } else {
3740 TCGv t0 = tcg_temp_new();
3741 TCGv t1 = tcg_temp_new();
3742
3743 tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop);
3744 if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) {
3745 tcg_gen_mov_tl(t1, src);
3746 } else {
3747 tcg_gen_ext32u_tl(t1, src);
3748 }
3749 tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1,
3750 cpu_gpr[(rt + 2) & 31], t0);
3751 tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop);
3752 tcg_gen_mov_tl(dst, t0);
3753
3754 tcg_temp_free(t0);
3755 tcg_temp_free(t1);
3756 }
3757 break;
3758
20ba8504 3759 case 24: /* Fetch and increment bounded */
20923c1d
RH		 3760 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3761 need_serial = true;
3762 } else {
3763 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1);
3764 }
3765 break;
20ba8504 3766 case 25: /* Fetch and increment equal */
20923c1d
RH		 3767 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3768 need_serial = true;
3769 } else {
3770 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1);
3771 }
3772 break;
20ba8504 3773 case 28: /* Fetch and decrement bounded */
20923c1d
RH		 3774 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3775 need_serial = true;
3776 } else {
3777 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1);
3778 }
20ba8504 3779 break;
20923c1d 3780
20ba8504
RH		 3781 default:
3782 /* invoke data storage error handler */
3783 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
3784 }
3785 tcg_temp_free(EA);
20923c1d
RH		 3786
3787 if (need_serial) {
3788 /* Restart with exclusive lock. */
3789 gen_helper_exit_atomic(cpu_env);
3790 ctx->base.is_jmp = DISAS_NORETURN;
3791 }
20ba8504
RH		 3792}
3793
3794static void gen_lwat(DisasContext *ctx)
3795{
3796 gen_ld_atomic(ctx, DEF_MEMOP(MO_UL));
3797}
3798
3799#ifdef TARGET_PPC64
3800static void gen_ldat(DisasContext *ctx)
3801{
3802 gen_ld_atomic(ctx, DEF_MEMOP(MO_Q));
3803}
a68a6146
B		 3804#endif
3805
14776ab5 3806static void gen_st_atomic(DisasContext *ctx, MemOp memop)
9deb041c
RH		 3807{
3808 uint32_t gpr_FC = FC(ctx->opcode);
3809 TCGv EA = tcg_temp_new();
3810 TCGv src, discard;
3811
3812 gen_addr_register(ctx, EA);
3813 src = cpu_gpr[rD(ctx->opcode)];
3814 discard = tcg_temp_new();
3815
3816 memop |= MO_ALIGN;
3817 switch (gpr_FC) {
3818 case 0: /* add and Store */
3819 tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3820 break;
3821 case 1: /* xor and Store */
3822 tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3823 break;
3824 case 2: /* Or and Store */
3825 tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3826 break;
3827 case 3: /* 'and' and Store */
3828 tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3829 break;
3830 case 4: /* Store max unsigned */
b8ce0f86
RH		 3831 tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3832 break;
9deb041c 3833 case 5: /* Store max signed */
b8ce0f86
RH		 3834 tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3835 break;
9deb041c 3836 case 6: /* Store min unsigned */
b8ce0f86
RH		 3837 tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3838 break;
9deb041c 3839 case 7: /* Store min signed */
b8ce0f86
RH		 3840 tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3841 break;
9deb041c 3842 case 24: /* Store twin */
7fbc2b20
RH		 3843 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3844 /* Restart with exclusive lock. */
3845 gen_helper_exit_atomic(cpu_env);
3846 ctx->base.is_jmp = DISAS_NORETURN;
3847 } else {
3848 TCGv t = tcg_temp_new();
3849 TCGv t2 = tcg_temp_new();
3850 TCGv s = tcg_temp_new();
3851 TCGv s2 = tcg_temp_new();
3852 TCGv ea_plus_s = tcg_temp_new();
3853
3854 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
3855 tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop));
3856 tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop);
3857 tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t);
3858 tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2);
3859 tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop);
3860 tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop);
3861
3862 tcg_temp_free(ea_plus_s);
3863 tcg_temp_free(s2);
3864 tcg_temp_free(s);
3865 tcg_temp_free(t2);
3866 tcg_temp_free(t);
3867 }
9deb041c
RH		 3868 break;
3869 default:
3870 /* invoke data storage error handler */
3871 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
3872 }
3873 tcg_temp_free(discard);
3874 tcg_temp_free(EA);
3875}
3876
3877static void gen_stwat(DisasContext *ctx)
3878{
3879 gen_st_atomic(ctx, DEF_MEMOP(MO_UL));
3880}
3881
3882#ifdef TARGET_PPC64
3883static void gen_stdat(DisasContext *ctx)
3884{
3885 gen_st_atomic(ctx, DEF_MEMOP(MO_Q));
3886}
a3401188
B		 3887#endif
3888
14776ab5 3889static void gen_conditional_store(DisasContext *ctx, MemOp memop)
587c51f7 3890{
253ce7b2
ND		 3891 TCGLabel *l1 = gen_new_label();
3892 TCGLabel *l2 = gen_new_label();
d8b86898
RH		 3893 TCGv t0 = tcg_temp_new();
3894 int reg = rS(ctx->opcode);
4425265b 3895
d8b86898
RH		 3896 gen_set_access_type(ctx, ACCESS_RES);
3897 gen_addr_reg_index(ctx, t0);
3898 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3899 tcg_temp_free(t0);
253ce7b2
ND		 3900
3901 t0 = tcg_temp_new();
3902 tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val,
3903 cpu_gpr[reg], ctx->mem_idx,
3904 DEF_MEMOP(memop) | MO_ALIGN);
3905 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val);
3906 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT);
3907 tcg_gen_or_tl(t0, t0, cpu_so);
3908 tcg_gen_trunc_tl_i32(cpu_crf[0], t0);
3909 tcg_temp_free(t0);
3910 tcg_gen_br(l2);
3911
587c51f7 3912 gen_set_label(l1);
4771df23 3913
efe843d8
DG		 3914 /*
3915 * Address mismatch implies failure. But we still need to provide
3916 * the memory barrier semantics of the instruction.
3917 */
4771df23 3918 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
253ce7b2
ND		 3919 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3920
3921 gen_set_label(l2);
587c51f7
TM		 3922 tcg_gen_movi_tl(cpu_reserve, -1);
3923}
587c51f7 3924
d8b86898
RH		 3925#define STCX(name, memop) \
3926static void gen_##name(DisasContext *ctx) \
3927{ \
3928 gen_conditional_store(ctx, memop); \
2391b357
ND		 3929}
3930
3931STCX(stbcx_, DEF_MEMOP(MO_UB))
3932STCX(sthcx_, DEF_MEMOP(MO_UW))
3933STCX(stwcx_, DEF_MEMOP(MO_UL))
587c51f7 3934
426613db 3935#if defined(TARGET_PPC64)
426613db 3936/* ldarx */
48793c95 3937LARX(ldarx, DEF_MEMOP(MO_Q))
2391b357
ND		 3938/* stdcx. */
3939STCX(stdcx_, DEF_MEMOP(MO_Q))
426613db 3940
9c294d5a
TM		 3941/* lqarx */
3942static void gen_lqarx(DisasContext *ctx)
3943{
9c294d5a 3944 int rd = rD(ctx->opcode);
94bf2658 3945 TCGv EA, hi, lo;
9c294d5a
TM		 3946
3947 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3948 (rd == rB(ctx->opcode)))) {
3949 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3950 return;
3951 }
3952
3953 gen_set_access_type(ctx, ACCESS_RES);
94bf2658 3954 EA = tcg_temp_new();
9c294d5a 3955 gen_addr_reg_index(ctx, EA);
94bf2658
RH		 3956
3957 /* Note that the low part is always in RD+1, even in LE mode. */
3958 lo = cpu_gpr[rd + 1];
3959 hi = cpu_gpr[rd];
3960
3961 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
f34ec0f6
RH		 3962 if (HAVE_ATOMIC128) {
3963 TCGv_i32 oi = tcg_temp_new_i32();
3964 if (ctx->le_mode) {
68e33d86 3965 tcg_gen_movi_i32(oi, make_memop_idx(MO_LE | MO_128 | MO_ALIGN,
f34ec0f6
RH		 3966 ctx->mem_idx));
3967 gen_helper_lq_le_parallel(lo, cpu_env, EA, oi);
3968 } else {
68e33d86 3969 tcg_gen_movi_i32(oi, make_memop_idx(MO_BE | MO_128 | MO_ALIGN,
f34ec0f6
RH		 3970 ctx->mem_idx));
3971 gen_helper_lq_be_parallel(lo, cpu_env, EA, oi);
3972 }
3973 tcg_temp_free_i32(oi);
3974 tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh));
94bf2658 3975 } else {
f34ec0f6
RH		 3976 /* Restart with exclusive lock. */
3977 gen_helper_exit_atomic(cpu_env);
3978 ctx->base.is_jmp = DISAS_NORETURN;
3979 tcg_temp_free(EA);
3980 return;
94bf2658 3981 }
94bf2658
RH		 3982 } else if (ctx->le_mode) {
3983 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16);
3984 tcg_gen_mov_tl(cpu_reserve, EA);
3985 gen_addr_add(ctx, EA, EA, 8);
3986 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ);
9c294d5a 3987 } else {
94bf2658
RH		 3988 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16);
3989 tcg_gen_mov_tl(cpu_reserve, EA);
3990 gen_addr_add(ctx, EA, EA, 8);
3991 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ);
9c294d5a 3992 }
9c294d5a 3993 tcg_temp_free(EA);
94bf2658
RH		 3994
3995 tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val));
3996 tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2));
9c294d5a
TM		 3997}
3998
aa2008af
ND		 3999/* stqcx. */
4000static void gen_stqcx_(DisasContext *ctx)
4001{
4a9b3c5d
RH		 4002 int rs = rS(ctx->opcode);
4003 TCGv EA, hi, lo;
aa2008af 4004
4a9b3c5d 4005 if (unlikely(rs & 1)) {
aa2008af
ND		 4006 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4007 return;
4008 }
4a9b3c5d 4009
aa2008af 4010 gen_set_access_type(ctx, ACCESS_RES);
4a9b3c5d 4011 EA = tcg_temp_new();
aa2008af 4012 gen_addr_reg_index(ctx, EA);
aa2008af 4013
4a9b3c5d
RH		 4014 /* Note that the low part is always in RS+1, even in LE mode. */
4015 lo = cpu_gpr[rs + 1];
4016 hi = cpu_gpr[rs];
aa2008af 4017
4a9b3c5d 4018 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
f34ec0f6 4019 if (HAVE_CMPXCHG128) {
68e33d86 4020 TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_128) | MO_ALIGN);
f34ec0f6
RH		 4021 if (ctx->le_mode) {
4022 gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env,
4023 EA, lo, hi, oi);
4024 } else {
4025 gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env,
4026 EA, lo, hi, oi);
4027 }
4028 tcg_temp_free_i32(oi);
4a9b3c5d 4029 } else {
f34ec0f6
RH		 4030 /* Restart with exclusive lock. */
4031 gen_helper_exit_atomic(cpu_env);
4032 ctx->base.is_jmp = DISAS_NORETURN;
4a9b3c5d 4033 }
4a9b3c5d 4034 tcg_temp_free(EA);
aa2008af 4035 } else {
4a9b3c5d
RH		 4036 TCGLabel *lab_fail = gen_new_label();
4037 TCGLabel *lab_over = gen_new_label();
4038 TCGv_i64 t0 = tcg_temp_new_i64();
4039 TCGv_i64 t1 = tcg_temp_new_i64();
aa2008af 4040
4a9b3c5d
RH		 4041 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail);
4042 tcg_temp_free(EA);
aa2008af 4043
4a9b3c5d
RH		 4044 gen_qemu_ld64_i64(ctx, t0, cpu_reserve);
4045 tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode
4046 ? offsetof(CPUPPCState, reserve_val2)
4047 : offsetof(CPUPPCState, reserve_val)));
4048 tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail);
4049
4050 tcg_gen_addi_i64(t0, cpu_reserve, 8);
4051 gen_qemu_ld64_i64(ctx, t0, t0);
4052 tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode
4053 ? offsetof(CPUPPCState, reserve_val)
4054 : offsetof(CPUPPCState, reserve_val2)));
4055 tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail);
4056
4057 /* Success */
4058 gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve);
4059 tcg_gen_addi_i64(t0, cpu_reserve, 8);
4060 gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0);
4061
4062 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4063 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
4064 tcg_gen_br(lab_over);
4065
4066 gen_set_label(lab_fail);
4067 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4068
4069 gen_set_label(lab_over);
4070 tcg_gen_movi_tl(cpu_reserve, -1);
4071 tcg_temp_free_i64(t0);
4072 tcg_temp_free_i64(t1);
4073 }
4074}
426613db
JM		 4075#endif /* defined(TARGET_PPC64) */
4076
79aceca5 4077/* sync */
99e300ef 4078static void gen_sync(DisasContext *ctx)
79aceca5 4079{
cd0c6f47
BH		 4080 uint32_t l = (ctx->opcode >> 21) & 3;
4081
4082 /*
c5a8d8f3
BH		 4083 * We may need to check for a pending TLB flush.
4084 *
4085 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
4086 *
4087 * Additionally, this can only happen in kernel mode however so
4088 * check MSR_PR as well.
cd0c6f47 4089 */
c5a8d8f3 4090 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
e3cffe6f 4091 gen_check_tlb_flush(ctx, true);
cd0c6f47 4092 }
4771df23 4093 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
79aceca5
FB		 4094}
4095
0db1b20e 4096/* wait */
99e300ef 4097static void gen_wait(DisasContext *ctx)
0db1b20e 4098{
35b5066e 4099 TCGv_i32 t0 = tcg_const_i32(1);
259186a7
AF		 4100 tcg_gen_st_i32(t0, cpu_env,
4101 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
931ff272 4102 tcg_temp_free_i32(t0);
0db1b20e 4103 /* Stop translation, as the CPU is supposed to sleep from now */
b6bac4bc 4104 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
0db1b20e
JM		 4105}
4106
7778a575
BH		 4107#if defined(TARGET_PPC64)
4108static void gen_doze(DisasContext *ctx)
4109{
4110#if defined(CONFIG_USER_ONLY)
4111 GEN_PRIV;
4112#else
4113 TCGv_i32 t;
4114
4115 CHK_HV;
4116 t = tcg_const_i32(PPC_PM_DOZE);
4117 gen_helper_pminsn(cpu_env, t);
4118 tcg_temp_free_i32(t);
154c69f2
BH		 4119 /* Stop translation, as the CPU is supposed to sleep from now */
4120 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
7778a575
BH		 4121#endif /* defined(CONFIG_USER_ONLY) */
4122}
4123
4124static void gen_nap(DisasContext *ctx)
4125{
4126#if defined(CONFIG_USER_ONLY)
4127 GEN_PRIV;
4128#else
4129 TCGv_i32 t;
4130
4131 CHK_HV;
4132 t = tcg_const_i32(PPC_PM_NAP);
4133 gen_helper_pminsn(cpu_env, t);
4134 tcg_temp_free_i32(t);
154c69f2
BH		 4135 /* Stop translation, as the CPU is supposed to sleep from now */
4136 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
7778a575
BH		 4137#endif /* defined(CONFIG_USER_ONLY) */
4138}
4139
cdee0e72
ND		 4140static void gen_stop(DisasContext *ctx)
4141{
21c0d66a
BH		 4142#if defined(CONFIG_USER_ONLY)
4143 GEN_PRIV;
4144#else
4145 TCGv_i32 t;
4146
4147 CHK_HV;
4148 t = tcg_const_i32(PPC_PM_STOP);
4149 gen_helper_pminsn(cpu_env, t);
4150 tcg_temp_free_i32(t);
4151 /* Stop translation, as the CPU is supposed to sleep from now */
4152 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
4153#endif /* defined(CONFIG_USER_ONLY) */
cdee0e72
ND		 4154}
4155
7778a575
BH		 4156static void gen_sleep(DisasContext *ctx)
4157{
4158#if defined(CONFIG_USER_ONLY)
4159 GEN_PRIV;
4160#else
4161 TCGv_i32 t;
4162
4163 CHK_HV;
4164 t = tcg_const_i32(PPC_PM_SLEEP);
4165 gen_helper_pminsn(cpu_env, t);
4166 tcg_temp_free_i32(t);
154c69f2
BH		 4167 /* Stop translation, as the CPU is supposed to sleep from now */
4168 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
7778a575
BH		 4169#endif /* defined(CONFIG_USER_ONLY) */
4170}
4171
4172static void gen_rvwinkle(DisasContext *ctx)
4173{
4174#if defined(CONFIG_USER_ONLY)
4175 GEN_PRIV;
4176#else
4177 TCGv_i32 t;
4178
4179 CHK_HV;
4180 t = tcg_const_i32(PPC_PM_RVWINKLE);
4181 gen_helper_pminsn(cpu_env, t);
4182 tcg_temp_free_i32(t);
154c69f2
BH		 4183 /* Stop translation, as the CPU is supposed to sleep from now */
4184 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
7778a575
BH		 4185#endif /* defined(CONFIG_USER_ONLY) */
4186}
4187#endif /* #if defined(TARGET_PPC64) */
4188
697ab892
DG		 4189static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
4190{
4191#if defined(TARGET_PPC64)
efe843d8 4192 if (ctx->has_cfar) {
697ab892 4193 tcg_gen_movi_tl(cpu_cfar, nip);
efe843d8 4194 }
697ab892
DG		 4195#endif
4196}
4197
46d396bd
DHB		 4198#if defined(TARGET_PPC64)
4199static void pmu_count_insns(DisasContext *ctx)
4200{
4201 /*
4202 * Do not bother calling the helper if the PMU isn't counting
4203 * instructions.
4204 */
4205 if (!ctx->pmu_insn_cnt) {
4206 return;
4207 }
4208
4209 #if !defined(CONFIG_USER_ONLY)
4210 /*
4211 * The PMU insns_inc() helper stops the internal PMU timer if a
4212 * counter overflows happens. In that case, if the guest is
4213 * running with icount and we do not handle it beforehand,
4214 * the helper can trigger a 'bad icount read'.
4215 */
4216 gen_icount_io_start(ctx);
4217
4218 gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns));
4219#else
4220 /*
4221 * User mode can read (but not write) PMC5 and start/stop
4222 * the PMU via MMCR0_FC. In this case just increment
4223 * PMC5 with base.num_insns.
4224 */
4225 TCGv t0 = tcg_temp_new();
4226
4227 gen_load_spr(t0, SPR_POWER_PMC5);
4228 tcg_gen_addi_tl(t0, t0, ctx->base.num_insns);
4229 gen_store_spr(SPR_POWER_PMC5, t0);
4230
4231 tcg_temp_free(t0);
4232#endif /* #if !defined(CONFIG_USER_ONLY) */
4233}
4234#else
4235static void pmu_count_insns(DisasContext *ctx)
4236{
4237 return;
4238}
4239#endif /* #if defined(TARGET_PPC64) */
4240
90aa39a1
SF		 4241static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
4242{
6e9cc373 4243 return translator_use_goto_tb(&ctx->base, dest);
90aa39a1
SF		 4244}
4245
0e3bf489
RK		 4246static void gen_lookup_and_goto_ptr(DisasContext *ctx)
4247{
9498d103
RH		 4248 if (unlikely(ctx->singlestep_enabled)) {
4249 gen_debug_exception(ctx);
0e3bf489 4250 } else {
46d396bd
DHB		 4251 /*
4252 * tcg_gen_lookup_and_goto_ptr will exit the TB if
4253 * CF_NO_GOTO_PTR is set. Count insns now.
4254 */
4255 if (ctx->base.tb->flags & CF_NO_GOTO_PTR) {
4256 pmu_count_insns(ctx);
4257 }
4258
0e3bf489
RK		 4259 tcg_gen_lookup_and_goto_ptr();
4260 }
4261}
4262
79aceca5 4263/*** Branch ***/
c4a2e3a9 4264static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
c1942362 4265{
e0c8f9ce 4266 if (NARROW_MODE(ctx)) {
a2ffb812 4267 dest = (uint32_t) dest;
e0c8f9ce 4268 }
90aa39a1 4269 if (use_goto_tb(ctx, dest)) {
46d396bd 4270 pmu_count_insns(ctx);
57fec1fe 4271 tcg_gen_goto_tb(n);
a2ffb812 4272 tcg_gen_movi_tl(cpu_nip, dest & ~3);
07ea28b4 4273 tcg_gen_exit_tb(ctx->base.tb, n);
c1942362 4274 } else {
a2ffb812 4275 tcg_gen_movi_tl(cpu_nip, dest & ~3);
0e3bf489 4276 gen_lookup_and_goto_ptr(ctx);
c1942362 4277 }
c53be334
FB		 4278}
4279
636aa200 4280static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
e1833e1f 4281{
e0c8f9ce
RH		 4282 if (NARROW_MODE(ctx)) {
4283 nip = (uint32_t)nip;
4284 }
4285 tcg_gen_movi_tl(cpu_lr, nip);
e1833e1f
JM		 4286}
4287
79aceca5 4288/* b ba bl bla */
99e300ef 4289static void gen_b(DisasContext *ctx)
79aceca5 4290{
76a66253 4291 target_ulong li, target;
38a64f9d
FB		 4292
4293 /* sign extend LI */
e0c8f9ce
RH		 4294 li = LI(ctx->opcode);
4295 li = (li ^ 0x02000000) - 0x02000000;
4296 if (likely(AA(ctx->opcode) == 0)) {
2c2bcb1b 4297 target = ctx->cia + li;
e0c8f9ce 4298 } else {
9a64fbe4 4299 target = li;
e0c8f9ce
RH		 4300 }
4301 if (LK(ctx->opcode)) {
b6bac4bc 4302 gen_setlr(ctx, ctx->base.pc_next);
e0c8f9ce 4303 }
2c2bcb1b 4304 gen_update_cfar(ctx, ctx->cia);
c1942362 4305 gen_goto_tb(ctx, 0, target);
6086c751 4306 ctx->base.is_jmp = DISAS_NORETURN;
79aceca5
FB		 4307}
4308
e98a6e40
FB		 4309#define BCOND_IM 0
4310#define BCOND_LR 1
4311#define BCOND_CTR 2
52a4984d 4312#define BCOND_TAR 3
e98a6e40 4313
c4a2e3a9 4314static void gen_bcond(DisasContext *ctx, int type)
d9bce9d9 4315{
d9bce9d9 4316 uint32_t bo = BO(ctx->opcode);
42a268c2 4317 TCGLabel *l1;
a2ffb812 4318 TCGv target;
0e3bf489 4319
52a4984d 4320 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
a7812ae4 4321 target = tcg_temp_local_new();
efe843d8 4322 if (type == BCOND_CTR) {
a2ffb812 4323 tcg_gen_mov_tl(target, cpu_ctr);
efe843d8 4324 } else if (type == BCOND_TAR) {
52a4984d 4325 gen_load_spr(target, SPR_TAR);
efe843d8 4326 } else {
a2ffb812 4327 tcg_gen_mov_tl(target, cpu_lr);
efe843d8 4328 }
d2e9fd8f 4329 } else {
f764718d 4330 target = NULL;
e98a6e40 4331 }
efe843d8 4332 if (LK(ctx->opcode)) {
b6bac4bc 4333 gen_setlr(ctx, ctx->base.pc_next);
efe843d8 4334 }
a2ffb812
AJ		 4335 l1 = gen_new_label();
4336 if ((bo & 0x4) == 0) {
4337 /* Decrement and test CTR */
a7812ae4 4338 TCGv temp = tcg_temp_new();
fa200c95
GK		 4339
4340 if (type == BCOND_CTR) {
4341 /*
4342 * All ISAs up to v3 describe this form of bcctr as invalid but
4343 * some processors, ie. 64-bit server processors compliant with
4344 * arch 2.x, do implement a "test and decrement" logic instead,
15d68c5e
GK		 4345 * as described in their respective UMs. This logic involves CTR
4346 * to act as both the branch target and a counter, which makes
4347 * it basically useless and thus never used in real code.
4348 *
4349 * This form was hence chosen to trigger extra micro-architectural
4350 * side-effect on real HW needed for the Spectre v2 workaround.
4351 * It is up to guests that implement such workaround, ie. linux, to
4352 * use this form in a way it just triggers the side-effect without
4353 * doing anything else harmful.
fa200c95 4354 */
d0db7cad 4355 if (unlikely(!is_book3s_arch2x(ctx))) {
fa200c95
GK		 4356 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4357 tcg_temp_free(temp);
4358 tcg_temp_free(target);
4359 return;
4360 }
4361
4362 if (NARROW_MODE(ctx)) {
4363 tcg_gen_ext32u_tl(temp, cpu_ctr);
4364 } else {
4365 tcg_gen_mov_tl(temp, cpu_ctr);
4366 }
4367 if (bo & 0x2) {
4368 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
4369 } else {
4370 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
4371 }
4372 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
a2ffb812 4373 } else {
fa200c95
GK		 4374 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
4375 if (NARROW_MODE(ctx)) {
4376 tcg_gen_ext32u_tl(temp, cpu_ctr);
4377 } else {
4378 tcg_gen_mov_tl(temp, cpu_ctr);
4379 }
4380 if (bo & 0x2) {
4381 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
4382 } else {
4383 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
4384 }
e98a6e40 4385 }
a7812ae4 4386 tcg_temp_free(temp);
a2ffb812
AJ		 4387 }
4388 if ((bo & 0x10) == 0) {
4389 /* Test CR */
4390 uint32_t bi = BI(ctx->opcode);
8f9fb7ac 4391 uint32_t mask = 0x08 >> (bi & 0x03);
a7812ae4 4392 TCGv_i32 temp = tcg_temp_new_i32();
a2ffb812 4393
d9bce9d9 4394 if (bo & 0x8) {
a2ffb812
AJ		 4395 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
4396 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
d9bce9d9 4397 } else {
a2ffb812
AJ		 4398 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
4399 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
d9bce9d9 4400 }
a7812ae4 4401 tcg_temp_free_i32(temp);
d9bce9d9 4402 }
2c2bcb1b 4403 gen_update_cfar(ctx, ctx->cia);
e98a6e40 4404 if (type == BCOND_IM) {
a2ffb812
AJ		 4405 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
4406 if (likely(AA(ctx->opcode) == 0)) {
2c2bcb1b 4407 gen_goto_tb(ctx, 0, ctx->cia + li);
a2ffb812
AJ		 4408 } else {
4409 gen_goto_tb(ctx, 0, li);
4410 }
e98a6e40 4411 } else {
e0c8f9ce 4412 if (NARROW_MODE(ctx)) {
a2ffb812 4413 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
e0c8f9ce 4414 } else {
a2ffb812 4415 tcg_gen_andi_tl(cpu_nip, target, ~3);
e0c8f9ce 4416 }
0e3bf489 4417 gen_lookup_and_goto_ptr(ctx);
c80d1df5
AG		 4418 tcg_temp_free(target);
4419 }
c4a2e3a9 4420 if ((bo & 0x14) != 0x14) {
0e3bf489 4421 /* fallthrough case */
c4a2e3a9 4422 gen_set_label(l1);
b6bac4bc 4423 gen_goto_tb(ctx, 1, ctx->base.pc_next);
c4a2e3a9 4424 }
6086c751 4425 ctx->base.is_jmp = DISAS_NORETURN;
e98a6e40
FB		 4426}
4427
99e300ef 4428static void gen_bc(DisasContext *ctx)
3b46e624 4429{
e98a6e40
FB		 4430 gen_bcond(ctx, BCOND_IM);
4431}
4432
99e300ef 4433static void gen_bcctr(DisasContext *ctx)
3b46e624 4434{
e98a6e40
FB		 4435 gen_bcond(ctx, BCOND_CTR);
4436}
4437
99e300ef 4438static void gen_bclr(DisasContext *ctx)
3b46e624 4439{
e98a6e40
FB		 4440 gen_bcond(ctx, BCOND_LR);
4441}
79aceca5 4442
52a4984d
TM		 4443static void gen_bctar(DisasContext *ctx)
4444{
4445 gen_bcond(ctx, BCOND_TAR);
4446}
4447
79aceca5 4448/*** Condition register logical ***/
e1571908 4449#define GEN_CRLOGIC(name, tcg_op, opc) \
efe843d8 4450static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 4451{ \
fc0d441e
JM		 4452 uint8_t bitmask; \
4453 int sh; \
a7812ae4 4454 TCGv_i32 t0, t1; \
fc0d441e 4455 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
a7812ae4 4456 t0 = tcg_temp_new_i32(); \
fc0d441e 4457 if (sh > 0) \
fea0c503 4458 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
fc0d441e 4459 else if (sh < 0) \
fea0c503 4460 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
e1571908 4461 else \
fea0c503 4462 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
a7812ae4 4463 t1 = tcg_temp_new_i32(); \
fc0d441e
JM		 4464 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
4465 if (sh > 0) \
fea0c503 4466 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
fc0d441e 4467 else if (sh < 0) \
fea0c503 4468 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
e1571908 4469 else \
fea0c503
AJ		 4470 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
4471 tcg_op(t0, t0, t1); \
8f9fb7ac 4472 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
fea0c503
AJ		 4473 tcg_gen_andi_i32(t0, t0, bitmask); \
4474 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
4475 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
a7812ae4
PB		 4476 tcg_temp_free_i32(t0); \
4477 tcg_temp_free_i32(t1); \
79aceca5
FB		 4478}
4479
4480/* crand */
e1571908 4481GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
79aceca5 4482/* crandc */
e1571908 4483GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
79aceca5 4484/* creqv */
e1571908 4485GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
79aceca5 4486/* crnand */
e1571908 4487GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
79aceca5 4488/* crnor */
e1571908 4489GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
79aceca5 4490/* cror */
e1571908 4491GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
79aceca5 4492/* crorc */
e1571908 4493GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
79aceca5 4494/* crxor */
e1571908 4495GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
99e300ef 4496
54623277 4497/* mcrf */
99e300ef 4498static void gen_mcrf(DisasContext *ctx)
79aceca5 4499{
47e4661c 4500 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
79aceca5
FB		 4501}
4502
4503/*** System linkage ***/
99e300ef 4504
c47493f2 4505/* rfi (supervisor only) */
99e300ef 4506static void gen_rfi(DisasContext *ctx)
79aceca5 4507{
9a64fbe4 4508#if defined(CONFIG_USER_ONLY)
9b2fadda 4509 GEN_PRIV;
9a64fbe4 4510#else
efe843d8
DG		 4511 /*
4512 * This instruction doesn't exist anymore on 64-bit server
6ca038c2 4513 * processors compliant with arch 2.x
a2e71b28 4514 */
d0db7cad 4515 if (is_book3s_arch2x(ctx)) {
6ca038c2
BH		 4516 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4517 return;
4518 }
9a64fbe4 4519 /* Restore CPU state */
9b2fadda 4520 CHK_SV;
f5b6daac 4521 gen_icount_io_start(ctx);
2c2bcb1b 4522 gen_update_cfar(ctx, ctx->cia);
e5f17ac6 4523 gen_helper_rfi(cpu_env);
59bf23fa 4524 ctx->base.is_jmp = DISAS_EXIT;
9a64fbe4 4525#endif
79aceca5
FB		 4526}
4527
426613db 4528#if defined(TARGET_PPC64)
99e300ef 4529static void gen_rfid(DisasContext *ctx)
426613db
JM		 4530{
4531#if defined(CONFIG_USER_ONLY)
9b2fadda 4532 GEN_PRIV;
426613db
JM		 4533#else
4534 /* Restore CPU state */
9b2fadda 4535 CHK_SV;
f5b6daac 4536 gen_icount_io_start(ctx);
2c2bcb1b 4537 gen_update_cfar(ctx, ctx->cia);
e5f17ac6 4538 gen_helper_rfid(cpu_env);
59bf23fa 4539 ctx->base.is_jmp = DISAS_EXIT;
426613db
JM		 4540#endif
4541}
426613db 4542
3c89b8d6
NP		 4543#if !defined(CONFIG_USER_ONLY)
4544static void gen_rfscv(DisasContext *ctx)
4545{
4546#if defined(CONFIG_USER_ONLY)
4547 GEN_PRIV;
4548#else
4549 /* Restore CPU state */
4550 CHK_SV;
f5b6daac 4551 gen_icount_io_start(ctx);
2c2bcb1b 4552 gen_update_cfar(ctx, ctx->cia);
3c89b8d6 4553 gen_helper_rfscv(cpu_env);
59bf23fa 4554 ctx->base.is_jmp = DISAS_EXIT;
3c89b8d6
NP		 4555#endif
4556}
4557#endif
4558
99e300ef 4559static void gen_hrfid(DisasContext *ctx)
be147d08
JM		 4560{
4561#if defined(CONFIG_USER_ONLY)
9b2fadda 4562 GEN_PRIV;
be147d08
JM		 4563#else
4564 /* Restore CPU state */
9b2fadda 4565 CHK_HV;
e5f17ac6 4566 gen_helper_hrfid(cpu_env);
59bf23fa 4567 ctx->base.is_jmp = DISAS_EXIT;
be147d08
JM		 4568#endif
4569}
4570#endif
4571
79aceca5 4572/* sc */
417bf010
JM		 4573#if defined(CONFIG_USER_ONLY)
4574#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4575#else
4576#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3c89b8d6 4577#define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED
417bf010 4578#endif
99e300ef 4579static void gen_sc(DisasContext *ctx)
79aceca5 4580{
e1833e1f
JM		 4581 uint32_t lev;
4582
4583 lev = (ctx->opcode >> 5) & 0x7F;
e06fcd75 4584 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
79aceca5
FB		 4585}
4586
3c89b8d6
NP		 4587#if defined(TARGET_PPC64)
4588#if !defined(CONFIG_USER_ONLY)
4589static void gen_scv(DisasContext *ctx)
4590{
f43520e5 4591 uint32_t lev = (ctx->opcode >> 5) & 0x7F;
3c89b8d6 4592
f43520e5 4593 /* Set the PC back to the faulting instruction. */
7a3fe174 4594 gen_update_nip(ctx, ctx->cia);
f43520e5 4595 gen_helper_scv(cpu_env, tcg_constant_i32(lev));
3c89b8d6 4596
7a3fe174 4597 ctx->base.is_jmp = DISAS_NORETURN;
3c89b8d6
NP		 4598}
4599#endif
4600#endif
4601
79aceca5 4602/*** Trap ***/
99e300ef 4603
22b56ee5
BH		 4604/* Check for unconditional traps (always or never) */
4605static bool check_unconditional_trap(DisasContext *ctx)
4606{
4607 /* Trap never */
4608 if (TO(ctx->opcode) == 0) {
4609 return true;
4610 }
4611 /* Trap always */
4612 if (TO(ctx->opcode) == 31) {
4613 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
4614 return true;
4615 }
4616 return false;
4617}
4618
54623277 4619/* tw */
99e300ef 4620static void gen_tw(DisasContext *ctx)
79aceca5 4621{
22b56ee5
BH		 4622 TCGv_i32 t0;
4623
4624 if (check_unconditional_trap(ctx)) {
4625 return;
4626 }
4627 t0 = tcg_const_i32(TO(ctx->opcode));
e5f17ac6
BS		 4628 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4629 t0);
cab3bee2 4630 tcg_temp_free_i32(t0);
79aceca5
FB		 4631}
4632
4633/* twi */
99e300ef 4634static void gen_twi(DisasContext *ctx)
79aceca5 4635{
22b56ee5
BH		 4636 TCGv t0;
4637 TCGv_i32 t1;
4638
4639 if (check_unconditional_trap(ctx)) {
4640 return;
4641 }
4642 t0 = tcg_const_tl(SIMM(ctx->opcode));
4643 t1 = tcg_const_i32(TO(ctx->opcode));
e5f17ac6 4644 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
cab3bee2
AJ		 4645 tcg_temp_free(t0);
4646 tcg_temp_free_i32(t1);
79aceca5
FB		 4647}
4648
d9bce9d9
JM		 4649#if defined(TARGET_PPC64)
4650/* td */
99e300ef 4651static void gen_td(DisasContext *ctx)
d9bce9d9 4652{
22b56ee5
BH		 4653 TCGv_i32 t0;
4654
4655 if (check_unconditional_trap(ctx)) {
4656 return;
4657 }
4658 t0 = tcg_const_i32(TO(ctx->opcode));
e5f17ac6
BS		 4659 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4660 t0);
cab3bee2 4661 tcg_temp_free_i32(t0);
d9bce9d9
JM		 4662}
4663
4664/* tdi */
99e300ef 4665static void gen_tdi(DisasContext *ctx)
d9bce9d9 4666{
22b56ee5
BH		 4667 TCGv t0;
4668 TCGv_i32 t1;
4669
4670 if (check_unconditional_trap(ctx)) {
4671 return;
4672 }
4673 t0 = tcg_const_tl(SIMM(ctx->opcode));
4674 t1 = tcg_const_i32(TO(ctx->opcode));
e5f17ac6 4675 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
cab3bee2
AJ		 4676 tcg_temp_free(t0);
4677 tcg_temp_free_i32(t1);
d9bce9d9
JM		 4678}
4679#endif
4680
79aceca5 4681/*** Processor control ***/
99e300ef 4682
54623277 4683/* mcrxr */
99e300ef 4684static void gen_mcrxr(DisasContext *ctx)
79aceca5 4685{
da91a00f
RH		 4686 TCGv_i32 t0 = tcg_temp_new_i32();
4687 TCGv_i32 t1 = tcg_temp_new_i32();
4688 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4689
4690 tcg_gen_trunc_tl_i32(t0, cpu_so);
4691 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4692 tcg_gen_trunc_tl_i32(dst, cpu_ca);
294d1292
SB		 4693 tcg_gen_shli_i32(t0, t0, 3);
4694 tcg_gen_shli_i32(t1, t1, 2);
4695 tcg_gen_shli_i32(dst, dst, 1);
da91a00f
RH		 4696 tcg_gen_or_i32(dst, dst, t0);
4697 tcg_gen_or_i32(dst, dst, t1);
4698 tcg_temp_free_i32(t0);
4699 tcg_temp_free_i32(t1);
4700
4701 tcg_gen_movi_tl(cpu_so, 0);
4702 tcg_gen_movi_tl(cpu_ov, 0);
4703 tcg_gen_movi_tl(cpu_ca, 0);
79aceca5
FB		 4704}
4705
b63d0434
ND		 4706#ifdef TARGET_PPC64
4707/* mcrxrx */
4708static void gen_mcrxrx(DisasContext *ctx)
4709{
4710 TCGv t0 = tcg_temp_new();
4711 TCGv t1 = tcg_temp_new();
4712 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4713
4714 /* copy OV and OV32 */
4715 tcg_gen_shli_tl(t0, cpu_ov, 1);
4716 tcg_gen_or_tl(t0, t0, cpu_ov32);
4717 tcg_gen_shli_tl(t0, t0, 2);
4718 /* copy CA and CA32 */
4719 tcg_gen_shli_tl(t1, cpu_ca, 1);
4720 tcg_gen_or_tl(t1, t1, cpu_ca32);
4721 tcg_gen_or_tl(t0, t0, t1);
4722 tcg_gen_trunc_tl_i32(dst, t0);
4723 tcg_temp_free(t0);
4724 tcg_temp_free(t1);
4725}
4726#endif
4727
0cfe11ea 4728/* mfcr mfocrf */
99e300ef 4729static void gen_mfcr(DisasContext *ctx)
79aceca5 4730{
76a66253 4731 uint32_t crm, crn;
3b46e624 4732
76a66253
JM		 4733 if (likely(ctx->opcode & 0x00100000)) {
4734 crm = CRM(ctx->opcode);
8dd640e4 4735 if (likely(crm && ((crm & (crm - 1)) == 0))) {
efe843d8 4736 crn = ctz32(crm);
e1571908 4737 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
0497d2f4
AJ		 4738 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4739 cpu_gpr[rD(ctx->opcode)], crn * 4);
76a66253 4740 }
d9bce9d9 4741 } else {
651721b2
AJ		 4742 TCGv_i32 t0 = tcg_temp_new_i32();
4743 tcg_gen_mov_i32(t0, cpu_crf[0]);
4744 tcg_gen_shli_i32(t0, t0, 4);
4745 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4746 tcg_gen_shli_i32(t0, t0, 4);
4747 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4748 tcg_gen_shli_i32(t0, t0, 4);
4749 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4750 tcg_gen_shli_i32(t0, t0, 4);
4751 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4752 tcg_gen_shli_i32(t0, t0, 4);
4753 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4754 tcg_gen_shli_i32(t0, t0, 4);
4755 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4756 tcg_gen_shli_i32(t0, t0, 4);
4757 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4758 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4759 tcg_temp_free_i32(t0);
d9bce9d9 4760 }
79aceca5
FB		 4761}
4762
4763/* mfmsr */
99e300ef 4764static void gen_mfmsr(DisasContext *ctx)
79aceca5 4765{
9b2fadda 4766 CHK_SV;
6527f6ea 4767 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
79aceca5
FB		 4768}
4769
4770/* mfspr */
636aa200 4771static inline void gen_op_mfspr(DisasContext *ctx)
79aceca5 4772{
69b058c8 4773 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
79aceca5
FB		 4774 uint32_t sprn = SPR(ctx->opcode);
4775
eb94268e
BH		 4776#if defined(CONFIG_USER_ONLY)
4777 read_cb = ctx->spr_cb[sprn].uea_read;
4778#else
4779 if (ctx->pr) {
4780 read_cb = ctx->spr_cb[sprn].uea_read;
4781 } else if (ctx->hv) {
be147d08 4782 read_cb = ctx->spr_cb[sprn].hea_read;
eb94268e 4783 } else {
3fc6c082 4784 read_cb = ctx->spr_cb[sprn].oea_read;
eb94268e 4785 }
9a64fbe4 4786#endif
76a66253
JM		 4787 if (likely(read_cb != NULL)) {
4788 if (likely(read_cb != SPR_NOACCESS)) {
45d827d2 4789 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3fc6c082
FB		 4790 } else {
4791 /* Privilege exception */
efe843d8
DG		 4792 /*
4793 * This is a hack to avoid warnings when running Linux:
9fceefa7
JM		 4794 * this OS breaks the PowerPC virtualisation model,
4795 * allowing userland application to read the PVR
4796 */
4797 if (sprn != SPR_PVR) {
31085338
TH		 4798 qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr "
4799 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn,
2c2bcb1b 4800 ctx->cia);
f24e5695 4801 }
9b2fadda 4802 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
79aceca5 4803 }
3fc6c082 4804 } else {
9b2fadda
BH		 4805 /* ISA 2.07 defines these as no-ops */
4806 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4807 (sprn >= 808 && sprn <= 811)) {
4808 /* This is a nop */
4809 return;
4810 }
3fc6c082 4811 /* Not defined */
31085338
TH		 4812 qemu_log_mask(LOG_GUEST_ERROR,
4813 "Trying to read invalid spr %d (0x%03x) at "
2c2bcb1b 4814 TARGET_FMT_lx "\n", sprn, sprn, ctx->cia);
9b2fadda 4815
efe843d8
DG		 4816 /*
4817 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can
4818 * generate a priv, a hv emu or a no-op
9b2fadda
BH		 4819 */
4820 if (sprn & 0x10) {
4821 if (ctx->pr) {
4822 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4823 }
4824 } else {
4825 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) {
4826 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4827 }
4d6a0680 4828 }
79aceca5 4829 }
79aceca5
FB		 4830}
4831
99e300ef 4832static void gen_mfspr(DisasContext *ctx)
79aceca5 4833{
3fc6c082 4834 gen_op_mfspr(ctx);
76a66253 4835}
3fc6c082
FB		 4836
4837/* mftb */
99e300ef 4838static void gen_mftb(DisasContext *ctx)
3fc6c082
FB		 4839{
4840 gen_op_mfspr(ctx);
79aceca5
FB		 4841}
4842
0cfe11ea 4843/* mtcrf mtocrf*/
99e300ef 4844static void gen_mtcrf(DisasContext *ctx)
79aceca5 4845{
76a66253 4846 uint32_t crm, crn;
3b46e624 4847
76a66253 4848 crm = CRM(ctx->opcode);
8dd640e4 4849 if (likely((ctx->opcode & 0x00100000))) {
4850 if (crm && ((crm & (crm - 1)) == 0)) {
4851 TCGv_i32 temp = tcg_temp_new_i32();
efe843d8 4852 crn = ctz32(crm);
8dd640e4 4853 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
0cfe11ea
AJ		 4854 tcg_gen_shri_i32(temp, temp, crn * 4);
4855 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
8dd640e4 4856 tcg_temp_free_i32(temp);
4857 }
76a66253 4858 } else {
651721b2
AJ		 4859 TCGv_i32 temp = tcg_temp_new_i32();
4860 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4861 for (crn = 0 ; crn < 8 ; crn++) {
4862 if (crm & (1 << crn)) {
4863 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4864 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4865 }
4866 }
a7812ae4 4867 tcg_temp_free_i32(temp);
76a66253 4868 }
79aceca5
FB		 4869}
4870
4871/* mtmsr */
426613db 4872#if defined(TARGET_PPC64)
99e300ef 4873static void gen_mtmsrd(DisasContext *ctx)
426613db 4874{
caf590dd
NP		 4875 if (unlikely(!is_book3s_arch2x(ctx))) {
4876 gen_invalid(ctx);
4877 return;
4878 }
4879
9b2fadda
BH		 4880 CHK_SV;
4881
4882#if !defined(CONFIG_USER_ONLY)
6fa5726b
MF		 4883 TCGv t0, t1;
4884 target_ulong mask;
4885
4886 t0 = tcg_temp_new();
4887 t1 = tcg_temp_new();
4888
f5b6daac 4889 gen_icount_io_start(ctx);
6fa5726b 4890
be147d08 4891 if (ctx->opcode & 0x00010000) {
5ed19506 4892 /* L=1 form only updates EE and RI */
6fa5726b 4893 mask = (1ULL << MSR_RI) | (1ULL << MSR_EE);
be147d08 4894 } else {
6fa5726b
MF		 4895 /* mtmsrd does not alter HV, S, ME, or LE */
4896 mask = ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) |
4897 (1ULL << MSR_HV));
efe843d8
DG		 4898 /*
4899 * XXX: we need to update nip before the store if we enter
4900 * power saving mode, we will exit the loop directly from
4901 * ppc_store_msr
056b05f8 4902 */
b6bac4bc 4903 gen_update_nip(ctx, ctx->base.pc_next);
be147d08 4904 }
6fa5726b
MF		 4905
4906 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask);
4907 tcg_gen_andi_tl(t1, cpu_msr, ~mask);
4908 tcg_gen_or_tl(t0, t0, t1);
4909
4910 gen_helper_store_msr(cpu_env, t0);
4911
5ed19506 4912 /* Must stop the translation as machine state (may have) changed */
d736de8f 4913 ctx->base.is_jmp = DISAS_EXIT_UPDATE;
6fa5726b
MF		 4914
4915 tcg_temp_free(t0);
4916 tcg_temp_free(t1);
9b2fadda 4917#endif /* !defined(CONFIG_USER_ONLY) */
426613db 4918}
9b2fadda 4919#endif /* defined(TARGET_PPC64) */
426613db 4920
99e300ef 4921static void gen_mtmsr(DisasContext *ctx)
79aceca5 4922{
9b2fadda
BH		 4923 CHK_SV;
4924
4925#if !defined(CONFIG_USER_ONLY)
6fa5726b
MF		 4926 TCGv t0, t1;
4927 target_ulong mask = 0xFFFFFFFF;
4928
4929 t0 = tcg_temp_new();
4930 t1 = tcg_temp_new();
4931
f5b6daac 4932 gen_icount_io_start(ctx);
5ed19506
NP		 4933 if (ctx->opcode & 0x00010000) {
4934 /* L=1 form only updates EE and RI */
6fa5726b 4935 mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE);
be147d08 4936 } else {
6fa5726b
MF		 4937 /* mtmsr does not alter S, ME, or LE */
4938 mask &= ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S));
8018dc63 4939
efe843d8
DG		 4940 /*
4941 * XXX: we need to update nip before the store if we enter
4942 * power saving mode, we will exit the loop directly from
4943 * ppc_store_msr
056b05f8 4944 */
b6bac4bc 4945 gen_update_nip(ctx, ctx->base.pc_next);
be147d08 4946 }
6fa5726b
MF		 4947
4948 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask);
4949 tcg_gen_andi_tl(t1, cpu_msr, ~mask);
4950 tcg_gen_or_tl(t0, t0, t1);
4951
4952 gen_helper_store_msr(cpu_env, t0);
4953
5ed19506 4954 /* Must stop the translation as machine state (may have) changed */
d736de8f 4955 ctx->base.is_jmp = DISAS_EXIT_UPDATE;
6fa5726b
MF		 4956
4957 tcg_temp_free(t0);
4958 tcg_temp_free(t1);
9a64fbe4 4959#endif
79aceca5
FB		 4960}
4961
4962/* mtspr */
99e300ef 4963static void gen_mtspr(DisasContext *ctx)
79aceca5 4964{
69b058c8 4965 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
79aceca5
FB		 4966 uint32_t sprn = SPR(ctx->opcode);
4967
eb94268e
BH		 4968#if defined(CONFIG_USER_ONLY)
4969 write_cb = ctx->spr_cb[sprn].uea_write;
4970#else
4971 if (ctx->pr) {
4972 write_cb = ctx->spr_cb[sprn].uea_write;
4973 } else if (ctx->hv) {
be147d08 4974 write_cb = ctx->spr_cb[sprn].hea_write;
eb94268e 4975 } else {
3fc6c082 4976 write_cb = ctx->spr_cb[sprn].oea_write;
eb94268e 4977 }
9a64fbe4 4978#endif
76a66253
JM		 4979 if (likely(write_cb != NULL)) {
4980 if (likely(write_cb != SPR_NOACCESS)) {
45d827d2 4981 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3fc6c082
FB		 4982 } else {
4983 /* Privilege exception */
31085338
TH		 4984 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr "
4985 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn,
2c2bcb1b 4986 ctx->cia);
9b2fadda 4987 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 4988 }
3fc6c082 4989 } else {
9b2fadda
BH		 4990 /* ISA 2.07 defines these as no-ops */
4991 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4992 (sprn >= 808 && sprn <= 811)) {
4993 /* This is a nop */
4994 return;
4995 }
4996
3fc6c082 4997 /* Not defined */
31085338
TH		 4998 qemu_log_mask(LOG_GUEST_ERROR,
4999 "Trying to write invalid spr %d (0x%03x) at "
2c2bcb1b 5000 TARGET_FMT_lx "\n", sprn, sprn, ctx->cia);
4d6a0680 5001
9b2fadda 5002
efe843d8
DG		 5003 /*
5004 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can
5005 * generate a priv, a hv emu or a no-op
9b2fadda
BH		 5006 */
5007 if (sprn & 0x10) {
5008 if (ctx->pr) {
5009 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
5010 }
5011 } else {
5012 if (ctx->pr || sprn == 0) {
5013 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
5014 }
4d6a0680 5015 }
79aceca5 5016 }
79aceca5
FB		 5017}
5018
dc2ee038
VAS		 5019#if defined(TARGET_PPC64)
5020/* setb */
5021static void gen_setb(DisasContext *ctx)
5022{
5023 TCGv_i32 t0 = tcg_temp_new_i32();
6f4912a4
PMD		 5024 TCGv_i32 t8 = tcg_constant_i32(8);
5025 TCGv_i32 tm1 = tcg_constant_i32(-1);
dc2ee038
VAS		 5026 int crf = crfS(ctx->opcode);
5027
5028 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4);
dc2ee038
VAS		 5029 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0);
5030 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
5031
5032 tcg_temp_free_i32(t0);
dc2ee038
VAS		 5033}
5034#endif
5035
79aceca5 5036/*** Cache management ***/
99e300ef 5037
54623277 5038/* dcbf */
99e300ef 5039static void gen_dcbf(DisasContext *ctx)
79aceca5 5040{
dac454af 5041 /* XXX: specification says this is treated as a load by the MMU */
76db3ba4
AJ		 5042 TCGv t0;
5043 gen_set_access_type(ctx, ACCESS_CACHE);
5044 t0 = tcg_temp_new();
5045 gen_addr_reg_index(ctx, t0);
5046 gen_qemu_ld8u(ctx, t0, t0);
fea0c503 5047 tcg_temp_free(t0);
79aceca5
FB		 5048}
5049
50728199
RK		 5050/* dcbfep (external PID dcbf) */
5051static void gen_dcbfep(DisasContext *ctx)
5052{
5053 /* XXX: specification says this is treated as a load by the MMU */
5054 TCGv t0;
5055 CHK_SV;
5056 gen_set_access_type(ctx, ACCESS_CACHE);
5057 t0 = tcg_temp_new();
5058 gen_addr_reg_index(ctx, t0);
5059 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB));
5060 tcg_temp_free(t0);
5061}
5062
79aceca5 5063/* dcbi (Supervisor only) */
99e300ef 5064static void gen_dcbi(DisasContext *ctx)
79aceca5 5065{
a541f297 5066#if defined(CONFIG_USER_ONLY)
9b2fadda 5067 GEN_PRIV;
a541f297 5068#else
b61f2753 5069 TCGv EA, val;
9b2fadda
BH		 5070
5071 CHK_SV;
a7812ae4 5072 EA = tcg_temp_new();
76db3ba4
AJ		 5073 gen_set_access_type(ctx, ACCESS_CACHE);
5074 gen_addr_reg_index(ctx, EA);
a7812ae4 5075 val = tcg_temp_new();
76a66253 5076 /* XXX: specification says this should be treated as a store by the MMU */
76db3ba4
AJ		 5077 gen_qemu_ld8u(ctx, val, EA);
5078 gen_qemu_st8(ctx, val, EA);
b61f2753
AJ		 5079 tcg_temp_free(val);
5080 tcg_temp_free(EA);
9b2fadda 5081#endif /* defined(CONFIG_USER_ONLY) */
79aceca5
FB		 5082}
5083
5084/* dcdst */
99e300ef 5085static void gen_dcbst(DisasContext *ctx)
79aceca5 5086{
76a66253 5087 /* XXX: specification say this is treated as a load by the MMU */
76db3ba4
AJ		 5088 TCGv t0;
5089 gen_set_access_type(ctx, ACCESS_CACHE);
5090 t0 = tcg_temp_new();
5091 gen_addr_reg_index(ctx, t0);
5092 gen_qemu_ld8u(ctx, t0, t0);
fea0c503 5093 tcg_temp_free(t0);
79aceca5
FB		 5094}
5095
50728199
RK		 5096/* dcbstep (dcbstep External PID version) */
5097static void gen_dcbstep(DisasContext *ctx)
5098{
5099 /* XXX: specification say this is treated as a load by the MMU */
5100 TCGv t0;
5101 gen_set_access_type(ctx, ACCESS_CACHE);
5102 t0 = tcg_temp_new();
5103 gen_addr_reg_index(ctx, t0);
5104 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB));
5105 tcg_temp_free(t0);
5106}
5107
79aceca5 5108/* dcbt */
99e300ef 5109static void gen_dcbt(DisasContext *ctx)
79aceca5 5110{
efe843d8
DG		 5111 /*
5112 * interpreted as no-op
5113 * XXX: specification say this is treated as a load by the MMU but
5114 * does not generate any exception
76a66253 5115 */
79aceca5
FB		 5116}
5117
50728199
RK		 5118/* dcbtep */
5119static void gen_dcbtep(DisasContext *ctx)
5120{
efe843d8
DG		 5121 /*
5122 * interpreted as no-op
5123 * XXX: specification say this is treated as a load by the MMU but
5124 * does not generate any exception
50728199
RK		 5125 */
5126}
5127
79aceca5 5128/* dcbtst */
99e300ef 5129static void gen_dcbtst(DisasContext *ctx)
79aceca5 5130{
efe843d8
DG		 5131 /*
5132 * interpreted as no-op
5133 * XXX: specification say this is treated as a load by the MMU but
5134 * does not generate any exception
76a66253 5135 */
79aceca5
FB		 5136}
5137
50728199
RK		 5138/* dcbtstep */
5139static void gen_dcbtstep(DisasContext *ctx)
5140{
efe843d8
DG		 5141 /*
5142 * interpreted as no-op
5143 * XXX: specification say this is treated as a load by the MMU but
5144 * does not generate any exception
50728199
RK		 5145 */
5146}
5147
4d09d529
AG		 5148/* dcbtls */
5149static void gen_dcbtls(DisasContext *ctx)
5150{
5151 /* Always fails locking the cache */
5152 TCGv t0 = tcg_temp_new();
5153 gen_load_spr(t0, SPR_Exxx_L1CSR0);
5154 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
5155 gen_store_spr(SPR_Exxx_L1CSR0, t0);
5156 tcg_temp_free(t0);
5157}
5158
79aceca5 5159/* dcbz */
99e300ef 5160static void gen_dcbz(DisasContext *ctx)
79aceca5 5161{
8e33944f 5162 TCGv tcgv_addr;
c9f82d01 5163 TCGv_i32 tcgv_op;
d63001d1 5164
76db3ba4 5165 gen_set_access_type(ctx, ACCESS_CACHE);
8e33944f 5166 tcgv_addr = tcg_temp_new();
c9f82d01 5167 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
8e33944f 5168 gen_addr_reg_index(ctx, tcgv_addr);
c9f82d01 5169 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op);
8e33944f 5170 tcg_temp_free(tcgv_addr);
c9f82d01 5171 tcg_temp_free_i32(tcgv_op);
79aceca5
FB		 5172}
5173
50728199
RK		 5174/* dcbzep */
5175static void gen_dcbzep(DisasContext *ctx)
5176{
5177 TCGv tcgv_addr;
5178 TCGv_i32 tcgv_op;
5179
5180 gen_set_access_type(ctx, ACCESS_CACHE);
5181 tcgv_addr = tcg_temp_new();
5182 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
5183 gen_addr_reg_index(ctx, tcgv_addr);
5184 gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op);
5185 tcg_temp_free(tcgv_addr);
5186 tcg_temp_free_i32(tcgv_op);
5187}
5188
ae1c1a3d 5189/* dst / dstt */
99e300ef 5190static void gen_dst(DisasContext *ctx)
ae1c1a3d
AJ		 5191{
5192 if (rA(ctx->opcode) == 0) {
e41029b3 5193 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
ae1c1a3d
AJ		 5194 } else {
5195 /* interpreted as no-op */
5196 }
5197}
5198
5199/* dstst /dststt */
99e300ef 5200static void gen_dstst(DisasContext *ctx)
ae1c1a3d
AJ		 5201{
5202 if (rA(ctx->opcode) == 0) {
e41029b3 5203 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
ae1c1a3d
AJ		 5204 } else {
5205 /* interpreted as no-op */
5206 }
5207
5208}
5209
5210/* dss / dssall */
99e300ef 5211static void gen_dss(DisasContext *ctx)
ae1c1a3d
AJ		 5212{
5213 /* interpreted as no-op */
5214}
5215
79aceca5 5216/* icbi */
99e300ef 5217static void gen_icbi(DisasContext *ctx)
79aceca5 5218{
76db3ba4
AJ		 5219 TCGv t0;
5220 gen_set_access_type(ctx, ACCESS_CACHE);
76db3ba4
AJ		 5221 t0 = tcg_temp_new();
5222 gen_addr_reg_index(ctx, t0);
2f5a189c 5223 gen_helper_icbi(cpu_env, t0);
37d269df 5224 tcg_temp_free(t0);
79aceca5
FB		 5225}
5226
50728199
RK		 5227/* icbiep */
5228static void gen_icbiep(DisasContext *ctx)
5229{
5230 TCGv t0;
5231 gen_set_access_type(ctx, ACCESS_CACHE);
5232 t0 = tcg_temp_new();
5233 gen_addr_reg_index(ctx, t0);
5234 gen_helper_icbiep(cpu_env, t0);
5235 tcg_temp_free(t0);
5236}
5237
79aceca5
FB		 5238/* Optional: */
5239/* dcba */
99e300ef 5240static void gen_dcba(DisasContext *ctx)
79aceca5 5241{
efe843d8
DG		 5242 /*
5243 * interpreted as no-op
5244 * XXX: specification say this is treated as a store by the MMU
0db1b20e
JM		 5245 * but does not generate any exception
5246 */
79aceca5
FB		 5247}
5248
5249/*** Segment register manipulation ***/
5250/* Supervisor only: */
99e300ef 5251
54623277 5252/* mfsr */
99e300ef 5253static void gen_mfsr(DisasContext *ctx)
79aceca5 5254{
9a64fbe4 5255#if defined(CONFIG_USER_ONLY)
9b2fadda 5256 GEN_PRIV;
9a64fbe4 5257#else
74d37793 5258 TCGv t0;
9b2fadda
BH		 5259
5260 CHK_SV;
74d37793 5261 t0 = tcg_const_tl(SR(ctx->opcode));
c6c7cf05 5262 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793 5263 tcg_temp_free(t0);
9b2fadda 5264#endif /* defined(CONFIG_USER_ONLY) */
79aceca5
FB		 5265}
5266
5267/* mfsrin */
99e300ef 5268static void gen_mfsrin(DisasContext *ctx)
79aceca5 5269{
9a64fbe4 5270#if defined(CONFIG_USER_ONLY)
9b2fadda 5271 GEN_PRIV;
9a64fbe4 5272#else
74d37793 5273 TCGv t0;
9b2fadda
BH		 5274
5275 CHK_SV;
74d37793 5276 t0 = tcg_temp_new();
e2622073 5277 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
c6c7cf05 5278 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793 5279 tcg_temp_free(t0);
9b2fadda 5280#endif /* defined(CONFIG_USER_ONLY) */
79aceca5
FB		 5281}
5282
5283/* mtsr */
99e300ef 5284static void gen_mtsr(DisasContext *ctx)
79aceca5 5285{
9a64fbe4 5286#if defined(CONFIG_USER_ONLY)
9b2fadda 5287 GEN_PRIV;
9a64fbe4 5288#else
74d37793 5289 TCGv t0;
9b2fadda
BH		 5290
5291 CHK_SV;
74d37793 5292 t0 = tcg_const_tl(SR(ctx->opcode));
c6c7cf05 5293 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
74d37793 5294 tcg_temp_free(t0);
9b2fadda 5295#endif /* defined(CONFIG_USER_ONLY) */
79aceca5
FB		 5296}
5297
5298/* mtsrin */
99e300ef 5299static void gen_mtsrin(DisasContext *ctx)
79aceca5 5300{
9a64fbe4 5301#if defined(CONFIG_USER_ONLY)
9b2fadda 5302 GEN_PRIV;
9a64fbe4 5303#else
74d37793 5304 TCGv t0;
9b2fadda
BH		 5305 CHK_SV;
5306
74d37793 5307 t0 = tcg_temp_new();
e2622073 5308 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
c6c7cf05 5309 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
74d37793 5310 tcg_temp_free(t0);
9b2fadda 5311#endif /* defined(CONFIG_USER_ONLY) */
79aceca5
FB		 5312}
5313
12de9a39
JM		 5314#if defined(TARGET_PPC64)
5315/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
e8eaa2c0 5316
54623277 5317/* mfsr */
e8eaa2c0 5318static void gen_mfsr_64b(DisasContext *ctx)
12de9a39
JM		 5319{
5320#if defined(CONFIG_USER_ONLY)
9b2fadda 5321 GEN_PRIV;
12de9a39 5322#else
74d37793 5323 TCGv t0;
9b2fadda
BH		 5324
5325 CHK_SV;
74d37793 5326 t0 = tcg_const_tl(SR(ctx->opcode));
c6c7cf05 5327 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793 5328 tcg_temp_free(t0);
9b2fadda 5329#endif /* defined(CONFIG_USER_ONLY) */
12de9a39
JM		 5330}
5331
5332/* mfsrin */
e8eaa2c0 5333static void gen_mfsrin_64b(DisasContext *ctx)
12de9a39
JM		 5334{
5335#if defined(CONFIG_USER_ONLY)
9b2fadda 5336 GEN_PRIV;
12de9a39 5337#else
74d37793 5338 TCGv t0;
9b2fadda
BH		 5339
5340 CHK_SV;
74d37793 5341 t0 = tcg_temp_new();
e2622073 5342 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
c6c7cf05 5343 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793 5344 tcg_temp_free(t0);
9b2fadda 5345#endif /* defined(CONFIG_USER_ONLY) */
12de9a39
JM		 5346}
5347
5348/* mtsr */
e8eaa2c0 5349static void gen_mtsr_64b(DisasContext *ctx)
12de9a39
JM		 5350{
5351#if defined(CONFIG_USER_ONLY)
9b2fadda 5352 GEN_PRIV;
12de9a39 5353#else
74d37793 5354 TCGv t0;
9b2fadda
BH		 5355
5356 CHK_SV;
74d37793 5357 t0 = tcg_const_tl(SR(ctx->opcode));
c6c7cf05 5358 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
74d37793 5359 tcg_temp_free(t0);
9b2fadda 5360#endif /* defined(CONFIG_USER_ONLY) */
12de9a39
JM		 5361}
5362
5363/* mtsrin */
e8eaa2c0 5364static void gen_mtsrin_64b(DisasContext *ctx)
12de9a39
JM		 5365{
5366#if defined(CONFIG_USER_ONLY)
9b2fadda 5367 GEN_PRIV;
12de9a39 5368#else
74d37793 5369 TCGv t0;
9b2fadda
BH		 5370
5371 CHK_SV;
74d37793 5372 t0 = tcg_temp_new();
e2622073 5373 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
c6c7cf05 5374 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
74d37793 5375 tcg_temp_free(t0);
9b2fadda 5376#endif /* defined(CONFIG_USER_ONLY) */
12de9a39 5377}
f6b868fc
BS		 5378
5379/* slbmte */
e8eaa2c0 5380static void gen_slbmte(DisasContext *ctx)
f6b868fc
BS		 5381{
5382#if defined(CONFIG_USER_ONLY)
9b2fadda 5383 GEN_PRIV;
f6b868fc 5384#else
9b2fadda
BH		 5385 CHK_SV;
5386
c6c7cf05
BS		 5387 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
5388 cpu_gpr[rS(ctx->opcode)]);
9b2fadda 5389#endif /* defined(CONFIG_USER_ONLY) */
f6b868fc
BS		 5390}
5391
efdef95f
DG		 5392static void gen_slbmfee(DisasContext *ctx)
5393{
5394#if defined(CONFIG_USER_ONLY)
9b2fadda 5395 GEN_PRIV;
efdef95f 5396#else
9b2fadda
BH		 5397 CHK_SV;
5398
c6c7cf05 5399 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
efdef95f 5400 cpu_gpr[rB(ctx->opcode)]);
9b2fadda 5401#endif /* defined(CONFIG_USER_ONLY) */
efdef95f
DG		 5402}
5403
5404static void gen_slbmfev(DisasContext *ctx)
5405{
5406#if defined(CONFIG_USER_ONLY)
9b2fadda 5407 GEN_PRIV;
efdef95f 5408#else
9b2fadda
BH		 5409 CHK_SV;
5410
c6c7cf05 5411 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
efdef95f 5412 cpu_gpr[rB(ctx->opcode)]);
9b2fadda 5413#endif /* defined(CONFIG_USER_ONLY) */
efdef95f 5414}
c76c22d5
BH		 5415
5416static void gen_slbfee_(DisasContext *ctx)
5417{
5418#if defined(CONFIG_USER_ONLY)
5419 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5420#else
5421 TCGLabel *l1, *l2;
5422
5423 if (unlikely(ctx->pr)) {
5424 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5425 return;
5426 }
5427 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
5428 cpu_gpr[rB(ctx->opcode)]);
5429 l1 = gen_new_label();
5430 l2 = gen_new_label();
5431 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5432 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
efa73196 5433 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
c76c22d5
BH		 5434 tcg_gen_br(l2);
5435 gen_set_label(l1);
5436 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
5437 gen_set_label(l2);
5438#endif
5439}
12de9a39
JM		 5440#endif /* defined(TARGET_PPC64) */
5441
79aceca5 5442/*** Lookaside buffer management ***/
c47493f2 5443/* Optional & supervisor only: */
99e300ef 5444
54623277 5445/* tlbia */
99e300ef 5446static void gen_tlbia(DisasContext *ctx)
79aceca5 5447{
9a64fbe4 5448#if defined(CONFIG_USER_ONLY)
9b2fadda 5449 GEN_PRIV;
9a64fbe4 5450#else
9b2fadda
BH		 5451 CHK_HV;
5452
c6c7cf05 5453 gen_helper_tlbia(cpu_env);
9b2fadda 5454#endif /* defined(CONFIG_USER_ONLY) */
79aceca5
FB		 5455}
5456
bf14b1ce 5457/* tlbiel */
99e300ef 5458static void gen_tlbiel(DisasContext *ctx)
bf14b1ce
BS		 5459{
5460#if defined(CONFIG_USER_ONLY)
9b2fadda 5461 GEN_PRIV;
bf14b1ce 5462#else
92fb92d3
MF		 5463 bool psr = (ctx->opcode >> 17) & 0x1;
5464
5465 if (ctx->pr || (!ctx->hv && !psr && ctx->hr)) {
5466 /*
5467 * tlbiel is privileged except when PSR=0 and HR=1, making it
5468 * hypervisor privileged.
5469 */
5470 GEN_PRIV;
5471 }
9b2fadda 5472
c6c7cf05 5473 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
9b2fadda 5474#endif /* defined(CONFIG_USER_ONLY) */
bf14b1ce
BS		 5475}
5476
79aceca5 5477/* tlbie */
99e300ef 5478static void gen_tlbie(DisasContext *ctx)
79aceca5 5479{
9a64fbe4 5480#if defined(CONFIG_USER_ONLY)
9b2fadda 5481 GEN_PRIV;
9a64fbe4 5482#else
92fb92d3 5483 bool psr = (ctx->opcode >> 17) & 0x1;
d76ab5e1 5484 TCGv_i32 t1;
c6fd28fd 5485
92fb92d3
MF		 5486 if (ctx->pr) {
5487 /* tlbie is privileged... */
5488 GEN_PRIV;
5489 } else if (!ctx->hv) {
5490 if (!ctx->gtse || (!psr && ctx->hr)) {
5491 /*
5492 * ... except when GTSE=0 or when PSR=0 and HR=1, making it
5493 * hypervisor privileged.
5494 */
5495 GEN_PRIV;
5496 }
c6fd28fd 5497 }
9b2fadda 5498
9ca3f7f3 5499 if (NARROW_MODE(ctx)) {
74d37793
AJ		 5500 TCGv t0 = tcg_temp_new();
5501 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
c6c7cf05 5502 gen_helper_tlbie(cpu_env, t0);
74d37793 5503 tcg_temp_free(t0);
9ca3f7f3 5504 } else {
c6c7cf05 5505 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
9ca3f7f3 5506 }
d76ab5e1
ND		 5507 t1 = tcg_temp_new_i32();
5508 tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
5509 tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH);
5510 tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
5511 tcg_temp_free_i32(t1);
9b2fadda 5512#endif /* defined(CONFIG_USER_ONLY) */
79aceca5
FB		 5513}
5514
5515/* tlbsync */
99e300ef 5516static void gen_tlbsync(DisasContext *ctx)
79aceca5 5517{
9a64fbe4 5518#if defined(CONFIG_USER_ONLY)
9b2fadda 5519 GEN_PRIV;
9a64fbe4 5520#else
91c60f12
CLG		 5521
5522 if (ctx->gtse) {
5523 CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */
5524 } else {
5525 CHK_HV; /* Else hypervisor privileged */
5526 }
9b2fadda 5527
e3cffe6f
ND		 5528 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */
5529 if (ctx->insns_flags & PPC_BOOKE) {
5530 gen_check_tlb_flush(ctx, true);
5531 }
9b2fadda 5532#endif /* defined(CONFIG_USER_ONLY) */
79aceca5
FB		 5533}
5534
426613db
JM		 5535#if defined(TARGET_PPC64)
5536/* slbia */
99e300ef 5537static void gen_slbia(DisasContext *ctx)
426613db
JM		 5538{
5539#if defined(CONFIG_USER_ONLY)
9b2fadda 5540 GEN_PRIV;
426613db 5541#else
0418bf78
NP		 5542 uint32_t ih = (ctx->opcode >> 21) & 0x7;
5543 TCGv_i32 t0 = tcg_const_i32(ih);
5544
9b2fadda
BH		 5545 CHK_SV;
5546
0418bf78 5547 gen_helper_slbia(cpu_env, t0);
3119154d 5548 tcg_temp_free_i32(t0);
9b2fadda 5549#endif /* defined(CONFIG_USER_ONLY) */
426613db
JM		 5550}
5551
5552/* slbie */
99e300ef 5553static void gen_slbie(DisasContext *ctx)
426613db
JM		 5554{
5555#if defined(CONFIG_USER_ONLY)
9b2fadda 5556 GEN_PRIV;
426613db 5557#else
9b2fadda
BH		 5558 CHK_SV;
5559
c6c7cf05 5560 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
9b2fadda 5561#endif /* defined(CONFIG_USER_ONLY) */
426613db 5562}
a63f1dfc
ND		 5563
5564/* slbieg */
5565static void gen_slbieg(DisasContext *ctx)
5566{
5567#if defined(CONFIG_USER_ONLY)
5568 GEN_PRIV;
5569#else
5570 CHK_SV;
5571
5572 gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5573#endif /* defined(CONFIG_USER_ONLY) */
5574}
5575
62d897ca
ND		 5576/* slbsync */
5577static void gen_slbsync(DisasContext *ctx)
5578{
5579#if defined(CONFIG_USER_ONLY)
5580 GEN_PRIV;
5581#else
5582 CHK_SV;
5583 gen_check_tlb_flush(ctx, true);
5584#endif /* defined(CONFIG_USER_ONLY) */
5585}
5586
9b2fadda 5587#endif /* defined(TARGET_PPC64) */
426613db 5588
79aceca5
FB		 5589/*** External control ***/
5590/* Optional: */
99e300ef 5591
54623277 5592/* eciwx */
99e300ef 5593static void gen_eciwx(DisasContext *ctx)
79aceca5 5594{
76db3ba4 5595 TCGv t0;
fa407c03 5596 /* Should check EAR[E] ! */
76db3ba4
AJ		 5597 gen_set_access_type(ctx, ACCESS_EXT);
5598 t0 = tcg_temp_new();
5599 gen_addr_reg_index(ctx, t0);
c674a983
RH		 5600 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx,
5601 DEF_MEMOP(MO_UL | MO_ALIGN));
fa407c03 5602 tcg_temp_free(t0);
76a66253
JM		 5603}
5604
5605/* ecowx */
99e300ef 5606static void gen_ecowx(DisasContext *ctx)
76a66253 5607{
76db3ba4 5608 TCGv t0;
fa407c03 5609 /* Should check EAR[E] ! */
76db3ba4
AJ		 5610 gen_set_access_type(ctx, ACCESS_EXT);
5611 t0 = tcg_temp_new();
5612 gen_addr_reg_index(ctx, t0);
c674a983
RH		 5613 tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx,
5614 DEF_MEMOP(MO_UL | MO_ALIGN));
fa407c03 5615 tcg_temp_free(t0);
76a66253
JM		 5616}
5617
5618/* PowerPC 601 specific instructions */
99e300ef 5619
54623277 5620/* abs - abs. */
99e300ef 5621static void gen_abs(DisasContext *ctx)
76a66253 5622{
fe21b785
RH		 5623 TCGv d = cpu_gpr[rD(ctx->opcode)];
5624 TCGv a = cpu_gpr[rA(ctx->opcode)];
5625
5626 tcg_gen_abs_tl(d, a);
efe843d8 5627 if (unlikely(Rc(ctx->opcode) != 0)) {
fe21b785 5628 gen_set_Rc0(ctx, d);
efe843d8 5629 }
76a66253
JM		 5630}
5631
5632/* abso - abso. */
99e300ef 5633static void gen_abso(DisasContext *ctx)
76a66253 5634{
fe21b785
RH		 5635 TCGv d = cpu_gpr[rD(ctx->opcode)];
5636 TCGv a = cpu_gpr[rA(ctx->opcode)];
5637
5638 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_ov, a, 0x80000000);
5639 tcg_gen_abs_tl(d, a);
5640 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
efe843d8 5641 if (unlikely(Rc(ctx->opcode) != 0)) {
fe21b785 5642 gen_set_Rc0(ctx, d);
efe843d8 5643 }
76a66253
JM		 5644}
5645
5646/* clcs */
99e300ef 5647static void gen_clcs(DisasContext *ctx)
76a66253 5648{
22e0e173 5649 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
d523dd00 5650 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
22e0e173 5651 tcg_temp_free_i32(t0);
c7697e1f 5652 /* Rc=1 sets CR0 to an undefined state */
76a66253
JM		 5653}
5654
5655/* div - div. */
99e300ef 5656static void gen_div(DisasContext *ctx)
76a66253 5657{
d15f74fb
BS		 5658 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5659 cpu_gpr[rB(ctx->opcode)]);
efe843d8 5660 if (unlikely(Rc(ctx->opcode) != 0)) {
22e0e173 5661 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
efe843d8 5662 }
76a66253
JM		 5663}
5664
5665/* divo - divo. */
99e300ef 5666static void gen_divo(DisasContext *ctx)
76a66253 5667{
d15f74fb
BS		 5668 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5669 cpu_gpr[rB(ctx->opcode)]);
efe843d8 5670 if (unlikely(Rc(ctx->opcode) != 0)) {
22e0e173 5671 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
efe843d8 5672 }
76a66253
JM		 5673}
5674
5675/* divs - divs. */
99e300ef 5676static void gen_divs(DisasContext *ctx)
76a66253 5677{
d15f74fb
BS		 5678 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5679 cpu_gpr[rB(ctx->opcode)]);
efe843d8 5680 if (unlikely(Rc(ctx->opcode) != 0)) {
22e0e173 5681 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
efe843d8 5682 }
76a66253
JM		 5683}
5684
5685/* divso - divso. */
99e300ef 5686static void gen_divso(DisasContext *ctx)
76a66253 5687{
d15f74fb
BS		 5688 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
5689 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
efe843d8 5690 if (unlikely(Rc(ctx->opcode) != 0)) {
22e0e173 5691 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
efe843d8 5692 }
76a66253
JM		 5693}
5694
5695/* doz - doz. */
99e300ef 5696static void gen_doz(DisasContext *ctx)
76a66253 5697{
42a268c2
RH		 5698 TCGLabel *l1 = gen_new_label();
5699 TCGLabel *l2 = gen_new_label();
efe843d8
DG		 5700 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)],
5701 cpu_gpr[rA(ctx->opcode)], l1);
5702 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
5703 cpu_gpr[rA(ctx->opcode)]);
22e0e173
AJ		 5704 tcg_gen_br(l2);
5705 gen_set_label(l1);
5706 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5707 gen_set_label(l2);
efe843d8 5708 if (unlikely(Rc(ctx->opcode) != 0)) {
22e0e173 5709 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
efe843d8 5710 }
76a66253
JM		 5711}
5712
5713/* dozo - dozo. */
99e300ef 5714static void gen_dozo(DisasContext *ctx)
76a66253 5715{
42a268c2
RH		 5716 TCGLabel *l1 = gen_new_label();
5717 TCGLabel *l2 = gen_new_label();
22e0e173
AJ		 5718 TCGv t0 = tcg_temp_new();
5719 TCGv t1 = tcg_temp_new();
5720 TCGv t2 = tcg_temp_new();
5721 /* Start with XER OV disabled, the most likely case */
da91a00f 5722 tcg_gen_movi_tl(cpu_ov, 0);
efe843d8
DG		 5723 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)],
5724 cpu_gpr[rA(ctx->opcode)], l1);
22e0e173
AJ		 5725 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5726 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5727 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
5728 tcg_gen_andc_tl(t1, t1, t2);
5729 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
5730 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
da91a00f
RH		 5731 tcg_gen_movi_tl(cpu_ov, 1);
5732 tcg_gen_movi_tl(cpu_so, 1);
22e0e173
AJ		 5733 tcg_gen_br(l2);
5734 gen_set_label(l1);
5735 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5736 gen_set_label(l2);
5737 tcg_temp_free(t0);
5738 tcg_temp_free(t1);
5739 tcg_temp_free(t2);
efe843d8 5740 if (unlikely(Rc(ctx->opcode) != 0)) {
22e0e173 5741 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
efe843d8 5742 }
76a66253
JM		 5743}
5744
5745/* dozi */
99e300ef 5746static void gen_dozi(DisasContext *ctx)
76a66253 5747{
22e0e173 5748 target_long simm = SIMM(ctx->opcode);
42a268c2
RH		 5749 TCGLabel *l1 = gen_new_label();
5750 TCGLabel *l2 = gen_new_label();
22e0e173
AJ		 5751 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
5752 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
5753 tcg_gen_br(l2);
5754 gen_set_label(l1);
5755 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5756 gen_set_label(l2);
efe843d8 5757 if (unlikely(Rc(ctx->opcode) != 0)) {
22e0e173 5758 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
efe843d8 5759 }
76a66253
JM		 5760}
5761
76a66253 5762/* lscbx - lscbx. */
99e300ef 5763static void gen_lscbx(DisasContext *ctx)
76a66253 5764{
bdb4b689
AJ		 5765 TCGv t0 = tcg_temp_new();
5766 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
5767 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
5768 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
76a66253 5769
76db3ba4 5770 gen_addr_reg_index(ctx, t0);
2f5a189c 5771 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
bdb4b689
AJ		 5772 tcg_temp_free_i32(t1);
5773 tcg_temp_free_i32(t2);
5774 tcg_temp_free_i32(t3);
3d7b417e 5775 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
bdb4b689 5776 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
efe843d8 5777 if (unlikely(Rc(ctx->opcode) != 0)) {
bdb4b689 5778 gen_set_Rc0(ctx, t0);
efe843d8 5779 }
bdb4b689 5780 tcg_temp_free(t0);
76a66253
JM		 5781}
5782
5783/* maskg - maskg. */
99e300ef 5784static void gen_maskg(DisasContext *ctx)
76a66253 5785{
42a268c2 5786 TCGLabel *l1 = gen_new_label();
22e0e173
AJ		 5787 TCGv t0 = tcg_temp_new();
5788 TCGv t1 = tcg_temp_new();
5789 TCGv t2 = tcg_temp_new();
5790 TCGv t3 = tcg_temp_new();
5791 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
5792 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5793 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
5794 tcg_gen_addi_tl(t2, t0, 1);
5795 tcg_gen_shr_tl(t2, t3, t2);
5796 tcg_gen_shr_tl(t3, t3, t1);
5797 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
5798 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5799 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5800 gen_set_label(l1);
5801 tcg_temp_free(t0);
5802 tcg_temp_free(t1);
5803 tcg_temp_free(t2);
5804 tcg_temp_free(t3);
efe843d8 5805 if (unlikely(Rc(ctx->opcode) != 0)) {
22e0e173 5806 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
efe843d8 5807 }
76a66253
JM		 5808}
5809
5810/* maskir - maskir. */
99e300ef 5811static void gen_maskir(DisasContext *ctx)
76a66253 5812{
22e0e173
AJ		 5813 TCGv t0 = tcg_temp_new();
5814 TCGv t1 = tcg_temp_new();
5815 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5816 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5817 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5818 tcg_temp_free(t0);
5819 tcg_temp_free(t1);
efe843d8 5820 if (unlikely(Rc(ctx->opcode) != 0)) {
22e0e173 5821 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
efe843d8 5822 }
76a66253
JM		 5823}
5824
5825/* mul - mul. */
99e300ef 5826static void gen_mul(DisasContext *ctx)
76a66253 5827{
22e0e173
AJ		 5828 TCGv_i64 t0 = tcg_temp_new_i64();
5829 TCGv_i64 t1 = tcg_temp_new_i64();
5830 TCGv t2 = tcg_temp_new();
5831 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5832 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5833 tcg_gen_mul_i64(t0, t0, t1);
5834 tcg_gen_trunc_i64_tl(t2, t0);
5835 gen_store_spr(SPR_MQ, t2);
5836 tcg_gen_shri_i64(t1, t0, 32);
5837 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5838 tcg_temp_free_i64(t0);
5839 tcg_temp_free_i64(t1);
5840 tcg_temp_free(t2);
efe843d8 5841 if (unlikely(Rc(ctx->opcode) != 0)) {
22e0e173 5842 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
efe843d8 5843 }
76a66253
JM		 5844}
5845
5846/* mulo - mulo. */
99e300ef 5847static void gen_mulo(DisasContext *ctx)
76a66253 5848{
42a268c2 5849 TCGLabel *l1 = gen_new_label();
22e0e173
AJ		 5850 TCGv_i64 t0 = tcg_temp_new_i64();
5851 TCGv_i64 t1 = tcg_temp_new_i64();
5852 TCGv t2 = tcg_temp_new();
5853 /* Start with XER OV disabled, the most likely case */
da91a00f 5854 tcg_gen_movi_tl(cpu_ov, 0);
22e0e173
AJ		 5855 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5856 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5857 tcg_gen_mul_i64(t0, t0, t1);
5858 tcg_gen_trunc_i64_tl(t2, t0);
5859 gen_store_spr(SPR_MQ, t2);
5860 tcg_gen_shri_i64(t1, t0, 32);
5861 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5862 tcg_gen_ext32s_i64(t1, t0);
5863 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
da91a00f
RH		 5864 tcg_gen_movi_tl(cpu_ov, 1);
5865 tcg_gen_movi_tl(cpu_so, 1);
22e0e173
AJ		 5866 gen_set_label(l1);
5867 tcg_temp_free_i64(t0);
5868 tcg_temp_free_i64(t1);
5869 tcg_temp_free(t2);
efe843d8 5870 if (unlikely(Rc(ctx->opcode) != 0)) {
22e0e173 5871 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
efe843d8 5872 }
76a66253
JM		 5873}
5874
5875/* nabs - nabs. */
99e300ef 5876static void gen_nabs(DisasContext *ctx)
76a66253 5877{
fe21b785
RH		 5878 TCGv d = cpu_gpr[rD(ctx->opcode)];
5879 TCGv a = cpu_gpr[rA(ctx->opcode)];
5880
5881 tcg_gen_abs_tl(d, a);
5882 tcg_gen_neg_tl(d, d);
efe843d8 5883 if (unlikely(Rc(ctx->opcode) != 0)) {
fe21b785 5884 gen_set_Rc0(ctx, d);
efe843d8 5885 }
76a66253
JM		 5886}
5887
5888/* nabso - nabso. */
99e300ef 5889static void gen_nabso(DisasContext *ctx)
76a66253 5890{
fe21b785
RH		 5891 TCGv d = cpu_gpr[rD(ctx->opcode)];
5892 TCGv a = cpu_gpr[rA(ctx->opcode)];
5893
5894 tcg_gen_abs_tl(d, a);
5895 tcg_gen_neg_tl(d, d);
22e0e173 5896 /* nabs never overflows */
da91a00f 5897 tcg_gen_movi_tl(cpu_ov, 0);
efe843d8 5898 if (unlikely(Rc(ctx->opcode) != 0)) {
fe21b785 5899 gen_set_Rc0(ctx, d);
efe843d8 5900 }
76a66253
JM		 5901}
5902
5903/* rlmi - rlmi. */
99e300ef 5904static void gen_rlmi(DisasContext *ctx)
76a66253 5905{
7487953d
AJ		 5906 uint32_t mb = MB(ctx->opcode);
5907 uint32_t me = ME(ctx->opcode);
5908 TCGv t0 = tcg_temp_new();
5909 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5910 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5911 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
efe843d8
DG		 5912 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
5913 ~MASK(mb, me));
7487953d
AJ		 5914 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5915 tcg_temp_free(t0);
efe843d8 5916 if (unlikely(Rc(ctx->opcode) != 0)) {
7487953d 5917 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
efe843d8 5918 }
76a66253
JM		 5919}
5920
5921/* rrib - rrib. */
99e300ef 5922static void gen_rrib(DisasContext *ctx)
76a66253 5923{
7487953d
AJ		 5924 TCGv t0 = tcg_temp_new();
5925 TCGv t1 = tcg_temp_new();
5926 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5927 tcg_gen_movi_tl(t1, 0x80000000);
5928 tcg_gen_shr_tl(t1, t1, t0);
5929 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5930 tcg_gen_and_tl(t0, t0, t1);
5931 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5932 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5933 tcg_temp_free(t0);
5934 tcg_temp_free(t1);
efe843d8 5935 if (unlikely(Rc(ctx->opcode) != 0)) {
7487953d 5936 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
efe843d8 5937 }
76a66253
JM		 5938}
5939
5940/* sle - sle. */
99e300ef 5941static void gen_sle(DisasContext *ctx)
76a66253 5942{
7487953d
AJ		 5943 TCGv t0 = tcg_temp_new();
5944 TCGv t1 = tcg_temp_new();
5945 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5946 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5947 tcg_gen_subfi_tl(t1, 32, t1);
5948 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5949 tcg_gen_or_tl(t1, t0, t1);
5950 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5951 gen_store_spr(SPR_MQ, t1);
5952 tcg_temp_free(t0);
5953 tcg_temp_free(t1);
efe843d8 5954 if (unlikely(Rc(ctx->opcode) != 0)) {
7487953d 5955 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
efe843d8 5956 }
76a66253
JM		 5957}
5958
5959/* sleq - sleq. */
99e300ef 5960static void gen_sleq(DisasContext *ctx)
76a66253 5961{
7487953d
AJ		 5962 TCGv t0 = tcg_temp_new();
5963 TCGv t1 = tcg_temp_new();
5964 TCGv t2 = tcg_temp_new();
5965 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5966 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5967 tcg_gen_shl_tl(t2, t2, t0);
5968 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5969 gen_load_spr(t1, SPR_MQ);
5970 gen_store_spr(SPR_MQ, t0);
5971 tcg_gen_and_tl(t0, t0, t2);
5972 tcg_gen_andc_tl(t1, t1, t2);
5973 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5974 tcg_temp_free(t0);
5975 tcg_temp_free(t1);
5976 tcg_temp_free(t2);
efe843d8 5977 if (unlikely(Rc(ctx->opcode) != 0)) {
7487953d 5978 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
efe843d8 5979 }
76a66253
JM		 5980}
5981
5982/* sliq - sliq. */
99e300ef 5983static void gen_sliq(DisasContext *ctx)
76a66253 5984{
7487953d
AJ		 5985 int sh = SH(ctx->opcode);
5986 TCGv t0 = tcg_temp_new();
5987 TCGv t1 = tcg_temp_new();
5988 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5989 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5990 tcg_gen_or_tl(t1, t0, t1);
5991 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5992 gen_store_spr(SPR_MQ, t1);
5993 tcg_temp_free(t0);
5994 tcg_temp_free(t1);
efe843d8 5995 if (unlikely(Rc(ctx->opcode) != 0)) {
7487953d 5996 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
efe843d8 5997 }
76a66253
JM		 5998}
5999
6000/* slliq - slliq. */
99e300ef 6001static void gen_slliq(DisasContext *ctx)
76a66253 6002{
7487953d
AJ		 6003 int sh = SH(ctx->opcode);
6004 TCGv t0 = tcg_temp_new();
6005 TCGv t1 = tcg_temp_new();
6006 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
6007 gen_load_spr(t1, SPR_MQ);
6008 gen_store_spr(SPR_MQ, t0);
6009 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
6010 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
6011 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
6012 tcg_temp_free(t0);
6013 tcg_temp_free(t1);
efe843d8 6014 if (unlikely(Rc(ctx->opcode) != 0)) {
7487953d 6015 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
efe843d8 6016 }
76a66253
JM		 6017}
6018
6019/* sllq - sllq. */
99e300ef 6020static void gen_sllq(DisasContext *ctx)
76a66253 6021{
42a268c2
RH		 6022 TCGLabel *l1 = gen_new_label();
6023 TCGLabel *l2 = gen_new_label();
7487953d
AJ		 6024 TCGv t0 = tcg_temp_local_new();
6025 TCGv t1 = tcg_temp_local_new();
6026 TCGv t2 = tcg_temp_local_new();
6027 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
6028 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
6029 tcg_gen_shl_tl(t1, t1, t2);
6030 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
6031 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
6032 gen_load_spr(t0, SPR_MQ);
6033 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
6034 tcg_gen_br(l2);
6035 gen_set_label(l1);
6036 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
6037 gen_load_spr(t2, SPR_MQ);
6038 tcg_gen_andc_tl(t1, t2, t1);
6039 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
6040 gen_set_label(l2);
6041 tcg_temp_free(t0);
6042 tcg_temp_free(t1);
6043 tcg_temp_free(t2);
efe843d8 6044 if (unlikely(Rc(ctx->opcode) != 0)) {
7487953d 6045 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
efe843d8 6046 }
76a66253
JM		 6047}
6048
6049/* slq - slq. */
99e300ef 6050static void gen_slq(DisasContext *ctx)
76a66253 6051{
42a268c2 6052 TCGLabel *l1 = gen_new_label();
7487953d
AJ		 6053 TCGv t0 = tcg_temp_new();
6054 TCGv t1 = tcg_temp_new();
6055 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
6056 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
6057 tcg_gen_subfi_tl(t1, 32, t1);
6058 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
6059 tcg_gen_or_tl(t1, t0, t1);
6060 gen_store_spr(SPR_MQ, t1);
6061 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
6062 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
6063 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
6064 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
6065 gen_set_label(l1);
6066 tcg_temp_free(t0);
6067 tcg_temp_free(t1);
efe843d8 6068 if (unlikely(Rc(ctx->opcode) != 0)) {
7487953d 6069 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
efe843d8 6070 }
76a66253
JM		 6071}
6072
d9bce9d9 6073/* sraiq - sraiq. */
99e300ef 6074static void gen_sraiq(DisasContext *ctx)
76a66253 6075{
7487953d 6076 int sh = SH(ctx->opcode);
42a268c2 6077 TCGLabel *l1 = gen_new_label();
7487953d
AJ		 6078 TCGv t0 = tcg_temp_new();
6079 TCGv t1 = tcg_temp_new();
6080 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
6081 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
6082 tcg_gen_or_tl(t0, t0, t1);
6083 gen_store_spr(SPR_MQ, t0);
da91a00f 6084 tcg_gen_movi_tl(cpu_ca, 0);
7487953d
AJ		 6085 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
6086 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
da91a00f 6087 tcg_gen_movi_tl(cpu_ca, 1);
7487953d
AJ		 6088 gen_set_label(l1);
6089 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
6090 tcg_temp_free(t0);
6091 tcg_temp_free(t1);
efe843d8 6092 if (unlikely(Rc(ctx->opcode) != 0)) {
7487953d 6093 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
efe843d8 6094 }
76a66253
JM		 6095}
6096
6097/* sraq - sraq. */
99e300ef 6098static void gen_sraq(DisasContext *ctx)
76a66253 6099{
42a268c2
RH		 6100 TCGLabel *l1 = gen_new_label();
6101 TCGLabel *l2 = gen_new_label();
7487953d
AJ		 6102 TCGv t0 = tcg_temp_new();
6103 TCGv t1 = tcg_temp_local_new();
6104 TCGv t2 = tcg_temp_local_new();
6105 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
6106 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
6107 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
6108 tcg_gen_subfi_tl(t2, 32, t2);
6109 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
6110 tcg_gen_or_tl(t0, t0, t2);
6111 gen_store_spr(SPR_MQ, t0);
6112 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
6113 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
6114 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
6115 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
6116 gen_set_label(l1);
6117 tcg_temp_free(t0);
6118 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
da91a00f 6119 tcg_gen_movi_tl(cpu_ca, 0);
7487953d
AJ		 6120 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
6121 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
da91a00f 6122 tcg_gen_movi_tl(cpu_ca, 1);
7487953d
AJ		 6123 gen_set_label(l2);
6124 tcg_temp_free(t1);
6125 tcg_temp_free(t2);
efe843d8 6126 if (unlikely(Rc(ctx->opcode) != 0)) {
7487953d 6127 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
efe843d8 6128 }
76a66253
JM		 6129}
6130
6131/* sre - sre. */
99e300ef 6132static void gen_sre(DisasContext *ctx)
76a66253 6133{
7487953d
AJ		 6134 TCGv t0 = tcg_temp_new();
6135 TCGv t1 = tcg_temp_new();
6136 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
6137 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
6138 tcg_gen_subfi_tl(t1, 32, t1);
6139 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
6140 tcg_gen_or_tl(t1, t0, t1);
6141 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
6142 gen_store_spr(SPR_MQ, t1);
6143 tcg_temp_free(t0);
6144 tcg_temp_free(t1);
efe843d8 6145 if (unlikely(Rc(ctx->opcode) != 0)) {
7487953d 6146 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
efe843d8 6147 }
76a66253
JM		 6148}
6149
6150/* srea - srea. */
99e300ef 6151static void gen_srea(DisasContext *ctx)
76a66253 6152{
7487953d
AJ		 6153 TCGv t0 = tcg_temp_new();
6154 TCGv t1 = tcg_temp_new();
6155 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
6156 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
6157 gen_store_spr(SPR_MQ, t0);
6158 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
6159 tcg_temp_free(t0);
6160 tcg_temp_free(t1);
efe843d8 6161 if (unlikely(Rc(ctx->opcode) != 0)) {
7487953d 6162 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
efe843d8 6163 }
76a66253
JM		 6164}
6165
6166/* sreq */
99e300ef 6167static void gen_sreq(DisasContext *ctx)
76a66253 6168{
7487953d
AJ		 6169 TCGv t0 = tcg_temp_new();
6170 TCGv t1 = tcg_temp_new();
6171 TCGv t2 = tcg_temp_new();
6172 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
6173 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
6174 tcg_gen_shr_tl(t1, t1, t0);
6175 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
6176 gen_load_spr(t2, SPR_MQ);
6177 gen_store_spr(SPR_MQ, t0);
6178 tcg_gen_and_tl(t0, t0, t1);
6179 tcg_gen_andc_tl(t2, t2, t1);
6180 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
6181 tcg_temp_free(t0);
6182 tcg_temp_free(t1);
6183 tcg_temp_free(t2);
efe843d8 6184 if (unlikely(Rc(ctx->opcode) != 0)) {
7487953d 6185 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
efe843d8 6186 }
76a66253
JM		 6187}
6188
6189/* sriq */
99e300ef 6190static void gen_sriq(DisasContext *ctx)
76a66253 6191{
7487953d
AJ		 6192 int sh = SH(ctx->opcode);
6193 TCGv t0 = tcg_temp_new();
6194 TCGv t1 = tcg_temp_new();
6195 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
6196 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
6197 tcg_gen_or_tl(t1, t0, t1);
6198 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
6199 gen_store_spr(SPR_MQ, t1);
6200 tcg_temp_free(t0);
6201 tcg_temp_free(t1);
efe843d8 6202 if (unlikely(Rc(ctx->opcode) != 0)) {
7487953d 6203 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
efe843d8 6204 }
76a66253
JM		 6205}
6206
6207/* srliq */
99e300ef 6208static void gen_srliq(DisasContext *ctx)
76a66253 6209{
7487953d
AJ		 6210 int sh = SH(ctx->opcode);
6211 TCGv t0 = tcg_temp_new();
6212 TCGv t1 = tcg_temp_new();
6213 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
6214 gen_load_spr(t1, SPR_MQ);
6215 gen_store_spr(SPR_MQ, t0);
6216 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
6217 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
6218 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
6219 tcg_temp_free(t0);
6220 tcg_temp_free(t1);
efe843d8 6221 if (unlikely(Rc(ctx->opcode) != 0)) {
7487953d 6222 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
efe843d8 6223 }
76a66253
JM		 6224}
6225
6226/* srlq */
99e300ef 6227static void gen_srlq(DisasContext *ctx)
76a66253 6228{
42a268c2
RH		 6229 TCGLabel *l1 = gen_new_label();
6230 TCGLabel *l2 = gen_new_label();
7487953d
AJ		 6231 TCGv t0 = tcg_temp_local_new();
6232 TCGv t1 = tcg_temp_local_new();
6233 TCGv t2 = tcg_temp_local_new();
6234 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
6235 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
6236 tcg_gen_shr_tl(t2, t1, t2);
6237 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
6238 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
6239 gen_load_spr(t0, SPR_MQ);
6240 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
6241 tcg_gen_br(l2);
6242 gen_set_label(l1);
6243 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
6244 tcg_gen_and_tl(t0, t0, t2);
6245 gen_load_spr(t1, SPR_MQ);
6246 tcg_gen_andc_tl(t1, t1, t2);
6247 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
6248 gen_set_label(l2);
6249 tcg_temp_free(t0);
6250 tcg_temp_free(t1);
6251 tcg_temp_free(t2);
efe843d8 6252 if (unlikely(Rc(ctx->opcode) != 0)) {
7487953d 6253 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
efe843d8 6254 }
76a66253
JM		 6255}
6256
6257/* srq */
99e300ef 6258static void gen_srq(DisasContext *ctx)
76a66253 6259{
42a268c2 6260 TCGLabel *l1 = gen_new_label();
7487953d
AJ		 6261 TCGv t0 = tcg_temp_new();
6262 TCGv t1 = tcg_temp_new();
6263 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
6264 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
6265 tcg_gen_subfi_tl(t1, 32, t1);
6266 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
6267 tcg_gen_or_tl(t1, t0, t1);
6268 gen_store_spr(SPR_MQ, t1);
6269 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
6270 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
6271 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
6272 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
6273 gen_set_label(l1);
6274 tcg_temp_free(t0);
6275 tcg_temp_free(t1);
efe843d8 6276 if (unlikely(Rc(ctx->opcode) != 0)) {
7487953d 6277 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
efe843d8 6278 }
76a66253
JM		 6279}
6280
6281/* PowerPC 602 specific instructions */
99e300ef 6282
54623277 6283/* dsa */
99e300ef 6284static void gen_dsa(DisasContext *ctx)
76a66253
JM		 6285{
6286 /* XXX: TODO */
e06fcd75 6287 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 6288}
6289
6290/* esa */
99e300ef 6291static void gen_esa(DisasContext *ctx)
76a66253
JM		 6292{
6293 /* XXX: TODO */
e06fcd75 6294 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 6295}
6296
6297/* mfrom */
99e300ef 6298static void gen_mfrom(DisasContext *ctx)
76a66253
JM		 6299{
6300#if defined(CONFIG_USER_ONLY)
9b2fadda 6301 GEN_PRIV;
76a66253 6302#else
9b2fadda 6303 CHK_SV;
cf02a65c 6304 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9b2fadda 6305#endif /* defined(CONFIG_USER_ONLY) */
76a66253
JM		 6306}
6307
6308/* 602 - 603 - G2 TLB management */
e8eaa2c0 6309
54623277 6310/* tlbld */
e8eaa2c0 6311static void gen_tlbld_6xx(DisasContext *ctx)
76a66253
JM		 6312{
6313#if defined(CONFIG_USER_ONLY)
9b2fadda 6314 GEN_PRIV;
76a66253 6315#else
9b2fadda 6316 CHK_SV;
c6c7cf05 6317 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
9b2fadda 6318#endif /* defined(CONFIG_USER_ONLY) */
76a66253
JM		 6319}
6320
6321/* tlbli */
e8eaa2c0 6322static void gen_tlbli_6xx(DisasContext *ctx)
76a66253
JM		 6323{
6324#if defined(CONFIG_USER_ONLY)
9b2fadda 6325 GEN_PRIV;
76a66253 6326#else
9b2fadda 6327 CHK_SV;
c6c7cf05 6328 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
9b2fadda 6329#endif /* defined(CONFIG_USER_ONLY) */
76a66253
JM		 6330}
6331
6332/* POWER instructions not in PowerPC 601 */
99e300ef 6333
54623277 6334/* clf */
99e300ef 6335static void gen_clf(DisasContext *ctx)
76a66253
JM		 6336{
6337 /* Cache line flush: implemented as no-op */
6338}
6339
6340/* cli */
99e300ef 6341static void gen_cli(DisasContext *ctx)
76a66253 6342{
76a66253 6343#if defined(CONFIG_USER_ONLY)
9b2fadda 6344 GEN_PRIV;
76a66253 6345#else
9b2fadda
BH		 6346 /* Cache line invalidate: privileged and treated as no-op */
6347 CHK_SV;
6348#endif /* defined(CONFIG_USER_ONLY) */
76a66253
JM		 6349}
6350
6351/* dclst */
99e300ef 6352static void gen_dclst(DisasContext *ctx)
76a66253
JM		 6353{
6354 /* Data cache line store: treated as no-op */
6355}
6356
99e300ef 6357static void gen_mfsri(DisasContext *ctx)
76a66253
JM		 6358{
6359#if defined(CONFIG_USER_ONLY)
9b2fadda 6360 GEN_PRIV;
76a66253 6361#else
74d37793
AJ		 6362 int ra = rA(ctx->opcode);
6363 int rd = rD(ctx->opcode);
6364 TCGv t0;
9b2fadda
BH		 6365
6366 CHK_SV;
74d37793 6367 t0 = tcg_temp_new();
76db3ba4 6368 gen_addr_reg_index(ctx, t0);
e2622073 6369 tcg_gen_extract_tl(t0, t0, 28, 4);
c6c7cf05 6370 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
74d37793 6371 tcg_temp_free(t0);
efe843d8 6372 if (ra != 0 && ra != rd) {
74d37793 6373 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
efe843d8 6374 }
9b2fadda 6375#endif /* defined(CONFIG_USER_ONLY) */
76a66253
JM		 6376}
6377
99e300ef 6378static void gen_rac(DisasContext *ctx)
76a66253
JM		 6379{
6380#if defined(CONFIG_USER_ONLY)
9b2fadda 6381 GEN_PRIV;
76a66253 6382#else
22e0e173 6383 TCGv t0;
9b2fadda
BH		 6384
6385 CHK_SV;
22e0e173 6386 t0 = tcg_temp_new();
76db3ba4 6387 gen_addr_reg_index(ctx, t0);
c6c7cf05 6388 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
22e0e173 6389 tcg_temp_free(t0);
9b2fadda 6390#endif /* defined(CONFIG_USER_ONLY) */
76a66253
JM		 6391}
6392
99e300ef 6393static void gen_rfsvc(DisasContext *ctx)
76a66253
JM		 6394{
6395#if defined(CONFIG_USER_ONLY)
9b2fadda 6396 GEN_PRIV;
76a66253 6397#else
9b2fadda
BH		 6398 CHK_SV;
6399
e5f17ac6 6400 gen_helper_rfsvc(cpu_env);
59bf23fa 6401 ctx->base.is_jmp = DISAS_EXIT;
9b2fadda 6402#endif /* defined(CONFIG_USER_ONLY) */
76a66253
JM		 6403}
6404
f9651121 6405/* svc is not implemented for now */
76a66253
JM		 6406
6407/* BookE specific instructions */
99e300ef 6408
54623277 6409/* XXX: not implemented on 440 ? */
99e300ef 6410static void gen_mfapidi(DisasContext *ctx)
76a66253
JM		 6411{
6412 /* XXX: TODO */
e06fcd75 6413 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 6414}
6415
2662a059 6416/* XXX: not implemented on 440 ? */
99e300ef 6417static void gen_tlbiva(DisasContext *ctx)
76a66253
JM		 6418{
6419#if defined(CONFIG_USER_ONLY)
9b2fadda 6420 GEN_PRIV;
76a66253 6421#else
74d37793 6422 TCGv t0;
9b2fadda
BH		 6423
6424 CHK_SV;
ec72e276 6425 t0 = tcg_temp_new();
76db3ba4 6426 gen_addr_reg_index(ctx, t0);
4693364f 6427 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
74d37793 6428 tcg_temp_free(t0);
9b2fadda 6429#endif /* defined(CONFIG_USER_ONLY) */
76a66253
JM		 6430}
6431
6432/* All 405 MAC instructions are translated here */
636aa200
BS		 6433static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
6434 int ra, int rb, int rt, int Rc)
76a66253 6435{
182608d4
AJ		 6436 TCGv t0, t1;
6437
a7812ae4
PB		 6438 t0 = tcg_temp_local_new();
6439 t1 = tcg_temp_local_new();
182608d4 6440
76a66253
JM		 6441 switch (opc3 & 0x0D) {
6442 case 0x05:
6443 /* macchw - macchw. - macchwo - macchwo. */
6444 /* macchws - macchws. - macchwso - macchwso. */
6445 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
6446 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
6447 /* mulchw - mulchw. */
182608d4
AJ		 6448 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
6449 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
6450 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 6451 break;
6452 case 0x04:
6453 /* macchwu - macchwu. - macchwuo - macchwuo. */
6454 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
6455 /* mulchwu - mulchwu. */
182608d4
AJ		 6456 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
6457 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
6458 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 6459 break;
6460 case 0x01:
6461 /* machhw - machhw. - machhwo - machhwo. */
6462 /* machhws - machhws. - machhwso - machhwso. */
6463 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
6464 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
6465 /* mulhhw - mulhhw. */
182608d4
AJ		 6466 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
6467 tcg_gen_ext16s_tl(t0, t0);
6468 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
6469 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 6470 break;
6471 case 0x00:
6472 /* machhwu - machhwu. - machhwuo - machhwuo. */
6473 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
6474 /* mulhhwu - mulhhwu. */
182608d4
AJ		 6475 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
6476 tcg_gen_ext16u_tl(t0, t0);
6477 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
6478 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 6479 break;
6480 case 0x0D:
6481 /* maclhw - maclhw. - maclhwo - maclhwo. */
6482 /* maclhws - maclhws. - maclhwso - maclhwso. */
6483 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
6484 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
6485 /* mullhw - mullhw. */
182608d4
AJ		 6486 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
6487 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
76a66253
JM		 6488 break;
6489 case 0x0C:
6490 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
6491 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
6492 /* mullhwu - mullhwu. */
182608d4
AJ		 6493 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
6494 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
76a66253
JM		 6495 break;
6496 }
76a66253 6497 if (opc2 & 0x04) {
182608d4
AJ		 6498 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
6499 tcg_gen_mul_tl(t1, t0, t1);
6500 if (opc2 & 0x02) {
6501 /* nmultiply-and-accumulate (0x0E) */
6502 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
6503 } else {
6504 /* multiply-and-accumulate (0x0C) */
6505 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
6506 }
6507
6508 if (opc3 & 0x12) {
6509 /* Check overflow and/or saturate */
42a268c2 6510 TCGLabel *l1 = gen_new_label();
182608d4
AJ		 6511
6512 if (opc3 & 0x10) {
6513 /* Start with XER OV disabled, the most likely case */
da91a00f 6514 tcg_gen_movi_tl(cpu_ov, 0);
182608d4
AJ		 6515 }
6516 if (opc3 & 0x01) {
6517 /* Signed */
6518 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
6519 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
6520 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
6521 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
bdc4e053 6522 if (opc3 & 0x02) {
182608d4
AJ		 6523 /* Saturate */
6524 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
6525 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
6526 }
6527 } else {
6528 /* Unsigned */
6529 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
bdc4e053 6530 if (opc3 & 0x02) {
182608d4
AJ		 6531 /* Saturate */
6532 tcg_gen_movi_tl(t0, UINT32_MAX);
6533 }
6534 }
6535 if (opc3 & 0x10) {
6536 /* Check overflow */
da91a00f
RH		 6537 tcg_gen_movi_tl(cpu_ov, 1);
6538 tcg_gen_movi_tl(cpu_so, 1);
182608d4
AJ		 6539 }
6540 gen_set_label(l1);
6541 tcg_gen_mov_tl(cpu_gpr[rt], t0);
6542 }
6543 } else {
6544 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
76a66253 6545 }
182608d4
AJ		 6546 tcg_temp_free(t0);
6547 tcg_temp_free(t1);
76a66253
JM		 6548 if (unlikely(Rc) != 0) {
6549 /* Update Rc0 */
182608d4 6550 gen_set_Rc0(ctx, cpu_gpr[rt]);
76a66253
JM		 6551 }
6552}
6553
a750fc0b 6554#define GEN_MAC_HANDLER(name, opc2, opc3) \
99e300ef 6555static void glue(gen_, name)(DisasContext *ctx) \
76a66253
JM		 6556{ \
6557 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
6558 rD(ctx->opcode), Rc(ctx->opcode)); \
6559}
6560
6561/* macchw - macchw. */
a750fc0b 6562GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
76a66253 6563/* macchwo - macchwo. */
a750fc0b 6564GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
76a66253 6565/* macchws - macchws. */
a750fc0b 6566GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
76a66253 6567/* macchwso - macchwso. */
a750fc0b 6568GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
76a66253 6569/* macchwsu - macchwsu. */
a750fc0b 6570GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
76a66253 6571/* macchwsuo - macchwsuo. */
a750fc0b 6572GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
76a66253 6573/* macchwu - macchwu. */
a750fc0b 6574GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
76a66253 6575/* macchwuo - macchwuo. */
a750fc0b 6576GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
76a66253 6577/* machhw - machhw. */
a750fc0b 6578GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
76a66253 6579/* machhwo - machhwo. */
a750fc0b 6580GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
76a66253 6581/* machhws - machhws. */
a750fc0b 6582GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
76a66253 6583/* machhwso - machhwso. */
a750fc0b 6584GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
76a66253 6585/* machhwsu - machhwsu. */
a750fc0b 6586GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
76a66253 6587/* machhwsuo - machhwsuo. */
a750fc0b 6588GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
76a66253 6589/* machhwu - machhwu. */
a750fc0b 6590GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
76a66253 6591/* machhwuo - machhwuo. */
a750fc0b 6592GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
76a66253 6593/* maclhw - maclhw. */
a750fc0b 6594GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
76a66253 6595/* maclhwo - maclhwo. */
a750fc0b 6596GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
76a66253 6597/* maclhws - maclhws. */
a750fc0b 6598GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
76a66253 6599/* maclhwso - maclhwso. */
a750fc0b 6600GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
76a66253 6601/* maclhwu - maclhwu. */
a750fc0b 6602GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
76a66253 6603/* maclhwuo - maclhwuo. */
a750fc0b 6604GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
76a66253 6605/* maclhwsu - maclhwsu. */
a750fc0b 6606GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
76a66253 6607/* maclhwsuo - maclhwsuo. */
a750fc0b 6608GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
76a66253 6609/* nmacchw - nmacchw. */
a750fc0b 6610GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
76a66253 6611/* nmacchwo - nmacchwo. */
a750fc0b 6612GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
76a66253 6613/* nmacchws - nmacchws. */
a750fc0b 6614GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
76a66253 6615/* nmacchwso - nmacchwso. */
a750fc0b 6616GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
76a66253 6617/* nmachhw - nmachhw. */
a750fc0b 6618GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
76a66253 6619/* nmachhwo - nmachhwo. */
a750fc0b 6620GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
76a66253 6621/* nmachhws - nmachhws. */
a750fc0b 6622GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
76a66253 6623/* nmachhwso - nmachhwso. */
a750fc0b 6624GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
76a66253 6625/* nmaclhw - nmaclhw. */
a750fc0b 6626GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
76a66253 6627/* nmaclhwo - nmaclhwo. */
a750fc0b 6628GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
76a66253 6629/* nmaclhws - nmaclhws. */
a750fc0b 6630GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
76a66253 6631/* nmaclhwso - nmaclhwso. */
a750fc0b 6632GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
76a66253
JM		 6633
6634/* mulchw - mulchw. */
a750fc0b 6635GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
76a66253 6636/* mulchwu - mulchwu. */
a750fc0b 6637GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
76a66253 6638/* mulhhw - mulhhw. */
a750fc0b 6639GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
76a66253 6640/* mulhhwu - mulhhwu. */
a750fc0b 6641GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
76a66253 6642/* mullhw - mullhw. */
a750fc0b 6643GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
76a66253 6644/* mullhwu - mullhwu. */
a750fc0b 6645GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
76a66253
JM		 6646
6647/* mfdcr */
99e300ef 6648static void gen_mfdcr(DisasContext *ctx)
76a66253
JM		 6649{
6650#if defined(CONFIG_USER_ONLY)
9b2fadda 6651 GEN_PRIV;
76a66253 6652#else
06dca6a7 6653 TCGv dcrn;
9b2fadda
BH		 6654
6655 CHK_SV;
06dca6a7 6656 dcrn = tcg_const_tl(SPR(ctx->opcode));
d0f1562d 6657 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
06dca6a7 6658 tcg_temp_free(dcrn);
9b2fadda 6659#endif /* defined(CONFIG_USER_ONLY) */
76a66253
JM		 6660}
6661
6662/* mtdcr */
99e300ef 6663static void gen_mtdcr(DisasContext *ctx)
76a66253
JM		 6664{
6665#if defined(CONFIG_USER_ONLY)
9b2fadda 6666 GEN_PRIV;
76a66253 6667#else
06dca6a7 6668 TCGv dcrn;
9b2fadda
BH		 6669
6670 CHK_SV;
06dca6a7 6671 dcrn = tcg_const_tl(SPR(ctx->opcode));
d0f1562d 6672 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
06dca6a7 6673 tcg_temp_free(dcrn);
9b2fadda 6674#endif /* defined(CONFIG_USER_ONLY) */
a42bd6cc
JM		 6675}
6676
6677/* mfdcrx */
2662a059 6678/* XXX: not implemented on 440 ? */
99e300ef 6679static void gen_mfdcrx(DisasContext *ctx)
a42bd6cc
JM		 6680{
6681#if defined(CONFIG_USER_ONLY)
9b2fadda 6682 GEN_PRIV;
a42bd6cc 6683#else
9b2fadda 6684 CHK_SV;
d0f1562d
BS		 6685 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6686 cpu_gpr[rA(ctx->opcode)]);
a750fc0b 6687 /* Note: Rc update flag set leads to undefined state of Rc0 */
9b2fadda 6688#endif /* defined(CONFIG_USER_ONLY) */
a42bd6cc
JM		 6689}
6690
6691/* mtdcrx */
2662a059 6692/* XXX: not implemented on 440 ? */
99e300ef 6693static void gen_mtdcrx(DisasContext *ctx)
a42bd6cc
JM		 6694{
6695#if defined(CONFIG_USER_ONLY)
9b2fadda 6696 GEN_PRIV;
a42bd6cc 6697#else
9b2fadda 6698 CHK_SV;
d0f1562d
BS		 6699 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6700 cpu_gpr[rS(ctx->opcode)]);
a750fc0b 6701 /* Note: Rc update flag set leads to undefined state of Rc0 */
9b2fadda 6702#endif /* defined(CONFIG_USER_ONLY) */
76a66253
JM		 6703}
6704
a750fc0b 6705/* mfdcrux (PPC 460) : user-mode access to DCR */
99e300ef 6706static void gen_mfdcrux(DisasContext *ctx)
a750fc0b 6707{
d0f1562d
BS		 6708 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6709 cpu_gpr[rA(ctx->opcode)]);
a750fc0b
JM		 6710 /* Note: Rc update flag set leads to undefined state of Rc0 */
6711}
6712
6713/* mtdcrux (PPC 460) : user-mode access to DCR */
99e300ef 6714static void gen_mtdcrux(DisasContext *ctx)
a750fc0b 6715{
975e5463 6716 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
d0f1562d 6717 cpu_gpr[rS(ctx->opcode)]);
a750fc0b
JM		 6718 /* Note: Rc update flag set leads to undefined state of Rc0 */
6719}
6720
76a66253 6721/* dccci */
99e300ef 6722static void gen_dccci(DisasContext *ctx)
76a66253 6723{
9b2fadda 6724 CHK_SV;
76a66253 6725 /* interpreted as no-op */
76a66253
JM		 6726}
6727
6728/* dcread */
99e300ef 6729static void gen_dcread(DisasContext *ctx)
76a66253
JM		 6730{
6731#if defined(CONFIG_USER_ONLY)
9b2fadda 6732 GEN_PRIV;
76a66253 6733#else
b61f2753 6734 TCGv EA, val;
9b2fadda
BH		 6735
6736 CHK_SV;
76db3ba4 6737 gen_set_access_type(ctx, ACCESS_CACHE);
a7812ae4 6738 EA = tcg_temp_new();
76db3ba4 6739 gen_addr_reg_index(ctx, EA);
a7812ae4 6740 val = tcg_temp_new();
76db3ba4 6741 gen_qemu_ld32u(ctx, val, EA);
b61f2753
AJ		 6742 tcg_temp_free(val);
6743 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6744 tcg_temp_free(EA);
9b2fadda 6745#endif /* defined(CONFIG_USER_ONLY) */
76a66253
JM		 6746}
6747
6748/* icbt */
e8eaa2c0 6749static void gen_icbt_40x(DisasContext *ctx)
76a66253 6750{
efe843d8
DG		 6751 /*
6752 * interpreted as no-op
6753 * XXX: specification say this is treated as a load by the MMU but
6754 * does not generate any exception
76a66253
JM		 6755 */
6756}
6757
6758/* iccci */
99e300ef 6759static void gen_iccci(DisasContext *ctx)
76a66253 6760{
9b2fadda 6761 CHK_SV;
76a66253 6762 /* interpreted as no-op */
76a66253
JM		 6763}
6764
6765/* icread */
99e300ef 6766static void gen_icread(DisasContext *ctx)
76a66253 6767{
9b2fadda 6768 CHK_SV;
76a66253 6769 /* interpreted as no-op */
76a66253
JM		 6770}
6771
c47493f2 6772/* rfci (supervisor only) */
e8eaa2c0 6773static void gen_rfci_40x(DisasContext *ctx)
a42bd6cc
JM		 6774{
6775#if defined(CONFIG_USER_ONLY)
9b2fadda 6776 GEN_PRIV;
a42bd6cc 6777#else
9b2fadda 6778 CHK_SV;
a42bd6cc 6779 /* Restore CPU state */
e5f17ac6 6780 gen_helper_40x_rfci(cpu_env);
59bf23fa 6781 ctx->base.is_jmp = DISAS_EXIT;
9b2fadda 6782#endif /* defined(CONFIG_USER_ONLY) */
a42bd6cc
JM		 6783}
6784
99e300ef 6785static void gen_rfci(DisasContext *ctx)
a42bd6cc
JM		 6786{
6787#if defined(CONFIG_USER_ONLY)
9b2fadda 6788 GEN_PRIV;
a42bd6cc 6789#else
9b2fadda 6790 CHK_SV;
a42bd6cc 6791 /* Restore CPU state */
e5f17ac6 6792 gen_helper_rfci(cpu_env);
59bf23fa 6793 ctx->base.is_jmp = DISAS_EXIT;
9b2fadda 6794#endif /* defined(CONFIG_USER_ONLY) */
a42bd6cc
JM		 6795}
6796
6797/* BookE specific */
99e300ef 6798
54623277 6799/* XXX: not implemented on 440 ? */
99e300ef 6800static void gen_rfdi(DisasContext *ctx)
76a66253
JM		 6801{
6802#if defined(CONFIG_USER_ONLY)
9b2fadda 6803 GEN_PRIV;
76a66253 6804#else
9b2fadda 6805 CHK_SV;
76a66253 6806 /* Restore CPU state */
e5f17ac6 6807 gen_helper_rfdi(cpu_env);
59bf23fa 6808 ctx->base.is_jmp = DISAS_EXIT;
9b2fadda 6809#endif /* defined(CONFIG_USER_ONLY) */
76a66253
JM		 6810}
6811
2662a059 6812/* XXX: not implemented on 440 ? */
99e300ef 6813static void gen_rfmci(DisasContext *ctx)
a42bd6cc
JM		 6814{
6815#if defined(CONFIG_USER_ONLY)
9b2fadda 6816 GEN_PRIV;
a42bd6cc 6817#else
9b2fadda 6818 CHK_SV;
a42bd6cc 6819 /* Restore CPU state */
e5f17ac6 6820 gen_helper_rfmci(cpu_env);
59bf23fa 6821 ctx->base.is_jmp = DISAS_EXIT;
9b2fadda 6822#endif /* defined(CONFIG_USER_ONLY) */
a42bd6cc 6823}
5eb7995e 6824
d9bce9d9 6825/* TLB management - PowerPC 405 implementation */
e8eaa2c0 6826
54623277 6827/* tlbre */
e8eaa2c0 6828static void gen_tlbre_40x(DisasContext *ctx)
76a66253
JM		 6829{
6830#if defined(CONFIG_USER_ONLY)
9b2fadda 6831 GEN_PRIV;
76a66253 6832#else
9b2fadda 6833 CHK_SV;
76a66253
JM		 6834 switch (rB(ctx->opcode)) {
6835 case 0:
c6c7cf05
BS		 6836 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6837 cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 6838 break;
6839 case 1:
c6c7cf05
BS		 6840 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6841 cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 6842 break;
6843 default:
e06fcd75 6844 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253 6845 break;
9a64fbe4 6846 }
9b2fadda 6847#endif /* defined(CONFIG_USER_ONLY) */
76a66253
JM		 6848}
6849
d9bce9d9 6850/* tlbsx - tlbsx. */
e8eaa2c0 6851static void gen_tlbsx_40x(DisasContext *ctx)
76a66253
JM		 6852{
6853#if defined(CONFIG_USER_ONLY)
9b2fadda 6854 GEN_PRIV;
76a66253 6855#else
74d37793 6856 TCGv t0;
9b2fadda
BH		 6857
6858 CHK_SV;
74d37793 6859 t0 = tcg_temp_new();
76db3ba4 6860 gen_addr_reg_index(ctx, t0);
c6c7cf05 6861 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793
AJ		 6862 tcg_temp_free(t0);
6863 if (Rc(ctx->opcode)) {
42a268c2 6864 TCGLabel *l1 = gen_new_label();
da91a00f 6865 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
74d37793
AJ		 6866 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6867 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6868 gen_set_label(l1);
6869 }
9b2fadda 6870#endif /* defined(CONFIG_USER_ONLY) */
79aceca5
FB		 6871}
6872
76a66253 6873/* tlbwe */
e8eaa2c0 6874static void gen_tlbwe_40x(DisasContext *ctx)
79aceca5 6875{
76a66253 6876#if defined(CONFIG_USER_ONLY)
9b2fadda 6877 GEN_PRIV;
76a66253 6878#else
9b2fadda
BH		 6879 CHK_SV;
6880
76a66253
JM		 6881 switch (rB(ctx->opcode)) {
6882 case 0:
c6c7cf05
BS		 6883 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6884 cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 6885 break;
6886 case 1:
c6c7cf05
BS		 6887 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6888 cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 6889 break;
6890 default:
e06fcd75 6891 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253 6892 break;
9a64fbe4 6893 }
9b2fadda 6894#endif /* defined(CONFIG_USER_ONLY) */
76a66253
JM		 6895}
6896
a4bb6c3e 6897/* TLB management - PowerPC 440 implementation */
e8eaa2c0 6898
54623277 6899/* tlbre */
e8eaa2c0 6900static void gen_tlbre_440(DisasContext *ctx)
5eb7995e
JM		 6901{
6902#if defined(CONFIG_USER_ONLY)
9b2fadda 6903 GEN_PRIV;
5eb7995e 6904#else
9b2fadda
BH		 6905 CHK_SV;
6906
5eb7995e
JM		 6907 switch (rB(ctx->opcode)) {
6908 case 0:
5eb7995e 6909 case 1:
5eb7995e 6910 case 2:
74d37793
AJ		 6911 {
6912 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
c6c7cf05
BS		 6913 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6914 t0, cpu_gpr[rA(ctx->opcode)]);
74d37793
AJ		 6915 tcg_temp_free_i32(t0);
6916 }
5eb7995e
JM		 6917 break;
6918 default:
e06fcd75 6919 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5eb7995e
JM		 6920 break;
6921 }
9b2fadda 6922#endif /* defined(CONFIG_USER_ONLY) */
5eb7995e
JM		 6923}
6924
6925/* tlbsx - tlbsx. */
e8eaa2c0 6926static void gen_tlbsx_440(DisasContext *ctx)
5eb7995e
JM		 6927{
6928#if defined(CONFIG_USER_ONLY)
9b2fadda 6929 GEN_PRIV;
5eb7995e 6930#else
74d37793 6931 TCGv t0;
9b2fadda
BH		 6932
6933 CHK_SV;
74d37793 6934 t0 = tcg_temp_new();
76db3ba4 6935 gen_addr_reg_index(ctx, t0);
c6c7cf05 6936 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793
AJ		 6937 tcg_temp_free(t0);
6938 if (Rc(ctx->opcode)) {
42a268c2 6939 TCGLabel *l1 = gen_new_label();
da91a00f 6940 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
74d37793
AJ		 6941 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6942 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6943 gen_set_label(l1);
6944 }
9b2fadda 6945#endif /* defined(CONFIG_USER_ONLY) */
5eb7995e
JM		 6946}
6947
6948/* tlbwe */
e8eaa2c0 6949static void gen_tlbwe_440(DisasContext *ctx)
5eb7995e
JM		 6950{
6951#if defined(CONFIG_USER_ONLY)
9b2fadda 6952 GEN_PRIV;
5eb7995e 6953#else
9b2fadda 6954 CHK_SV;
5eb7995e
JM		 6955 switch (rB(ctx->opcode)) {
6956 case 0:
5eb7995e 6957 case 1:
5eb7995e 6958 case 2:
74d37793
AJ		 6959 {
6960 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
c6c7cf05
BS		 6961 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6962 cpu_gpr[rS(ctx->opcode)]);
74d37793
AJ		 6963 tcg_temp_free_i32(t0);
6964 }
5eb7995e
JM		 6965 break;
6966 default:
e06fcd75 6967 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5eb7995e
JM		 6968 break;
6969 }
9b2fadda 6970#endif /* defined(CONFIG_USER_ONLY) */
5eb7995e
JM		 6971}
6972
01662f3e
AG		 6973/* TLB management - PowerPC BookE 2.06 implementation */
6974
6975/* tlbre */
6976static void gen_tlbre_booke206(DisasContext *ctx)
6977{
9b2fadda
BH		 6978 #if defined(CONFIG_USER_ONLY)
6979 GEN_PRIV;
01662f3e 6980#else
9b2fadda 6981 CHK_SV;
c6c7cf05 6982 gen_helper_booke206_tlbre(cpu_env);
9b2fadda 6983#endif /* defined(CONFIG_USER_ONLY) */
01662f3e
AG		 6984}
6985
6986/* tlbsx - tlbsx. */
6987static void gen_tlbsx_booke206(DisasContext *ctx)
6988{
6989#if defined(CONFIG_USER_ONLY)
9b2fadda 6990 GEN_PRIV;
01662f3e
AG		 6991#else
6992 TCGv t0;
01662f3e 6993
9b2fadda 6994 CHK_SV;
01662f3e
AG		 6995 if (rA(ctx->opcode)) {
6996 t0 = tcg_temp_new();
6997 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6998 } else {
6999 t0 = tcg_const_tl(0);
7000 }
7001
7002 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
c6c7cf05 7003 gen_helper_booke206_tlbsx(cpu_env, t0);
c80d1df5 7004 tcg_temp_free(t0);
9b2fadda 7005#endif /* defined(CONFIG_USER_ONLY) */
01662f3e
AG		 7006}
7007
7008/* tlbwe */
7009static void gen_tlbwe_booke206(DisasContext *ctx)
7010{
7011#if defined(CONFIG_USER_ONLY)
9b2fadda 7012 GEN_PRIV;
01662f3e 7013#else
9b2fadda 7014 CHK_SV;
c6c7cf05 7015 gen_helper_booke206_tlbwe(cpu_env);
9b2fadda 7016#endif /* defined(CONFIG_USER_ONLY) */
01662f3e
AG		 7017}
7018
7019static void gen_tlbivax_booke206(DisasContext *ctx)
7020{
7021#if defined(CONFIG_USER_ONLY)
9b2fadda 7022 GEN_PRIV;
01662f3e
AG		 7023#else
7024 TCGv t0;
01662f3e 7025
9b2fadda 7026 CHK_SV;
01662f3e
AG		 7027 t0 = tcg_temp_new();
7028 gen_addr_reg_index(ctx, t0);
c6c7cf05 7029 gen_helper_booke206_tlbivax(cpu_env, t0);
c80d1df5 7030 tcg_temp_free(t0);
9b2fadda 7031#endif /* defined(CONFIG_USER_ONLY) */
01662f3e
AG		 7032}
7033
6d3db821
AG		 7034static void gen_tlbilx_booke206(DisasContext *ctx)
7035{
7036#if defined(CONFIG_USER_ONLY)
9b2fadda 7037 GEN_PRIV;
6d3db821
AG		 7038#else
7039 TCGv t0;
6d3db821 7040
9b2fadda 7041 CHK_SV;
6d3db821
AG		 7042 t0 = tcg_temp_new();
7043 gen_addr_reg_index(ctx, t0);
7044
efe843d8 7045 switch ((ctx->opcode >> 21) & 0x3) {
6d3db821 7046 case 0:
c6c7cf05 7047 gen_helper_booke206_tlbilx0(cpu_env, t0);
6d3db821
AG		 7048 break;
7049 case 1:
c6c7cf05 7050 gen_helper_booke206_tlbilx1(cpu_env, t0);
6d3db821
AG		 7051 break;
7052 case 3:
c6c7cf05 7053 gen_helper_booke206_tlbilx3(cpu_env, t0);
6d3db821
AG		 7054 break;
7055 default:
7056 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
7057 break;
7058 }
7059
7060 tcg_temp_free(t0);
9b2fadda 7061#endif /* defined(CONFIG_USER_ONLY) */
6d3db821
AG		 7062}
7063
01662f3e 7064
76a66253 7065/* wrtee */
99e300ef 7066static void gen_wrtee(DisasContext *ctx)
76a66253
JM		 7067{
7068#if defined(CONFIG_USER_ONLY)
9b2fadda 7069 GEN_PRIV;
76a66253 7070#else
6527f6ea 7071 TCGv t0;
9b2fadda
BH		 7072
7073 CHK_SV;
6527f6ea
AJ		 7074 t0 = tcg_temp_new();
7075 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
7076 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
7077 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
7078 tcg_temp_free(t0);
efe843d8
DG		 7079 /*
7080 * Stop translation to have a chance to raise an exception if we
7081 * just set msr_ee to 1
dee96f6c 7082 */
d736de8f 7083 ctx->base.is_jmp = DISAS_EXIT_UPDATE;
9b2fadda 7084#endif /* defined(CONFIG_USER_ONLY) */
76a66253
JM		 7085}
7086
7087/* wrteei */
99e300ef 7088static void gen_wrteei(DisasContext *ctx)
76a66253
JM		 7089{
7090#if defined(CONFIG_USER_ONLY)
9b2fadda 7091 GEN_PRIV;
76a66253 7092#else
9b2fadda 7093 CHK_SV;
fbe73008 7094 if (ctx->opcode & 0x00008000) {
6527f6ea
AJ		 7095 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
7096 /* Stop translation to have a chance to raise an exception */
d736de8f 7097 ctx->base.is_jmp = DISAS_EXIT_UPDATE;
6527f6ea 7098 } else {
1b6e5f99 7099 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6527f6ea 7100 }
9b2fadda 7101#endif /* defined(CONFIG_USER_ONLY) */
76a66253
JM		 7102}
7103
08e46e54 7104/* PowerPC 440 specific instructions */
99e300ef 7105
54623277 7106/* dlmzb */
99e300ef 7107static void gen_dlmzb(DisasContext *ctx)
76a66253 7108{
ef0d51af 7109 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
d15f74fb
BS		 7110 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
7111 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
ef0d51af 7112 tcg_temp_free_i32(t0);
76a66253
JM		 7113}
7114
7115/* mbar replaces eieio on 440 */
99e300ef 7116static void gen_mbar(DisasContext *ctx)
76a66253
JM		 7117{
7118 /* interpreted as no-op */
7119}
7120
7121/* msync replaces sync on 440 */
dcb2b9e1 7122static void gen_msync_4xx(DisasContext *ctx)
76a66253 7123{
27a3ea7e
BZ		 7124 /* Only e500 seems to treat reserved bits as invalid */
7125 if ((ctx->insns_flags2 & PPC2_BOOKE206) &&
7126 (ctx->opcode & 0x03FFF801)) {
7127 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
7128 }
7129 /* otherwise interpreted as no-op */
76a66253
JM		 7130}
7131
7132/* icbt */
e8eaa2c0 7133static void gen_icbt_440(DisasContext *ctx)
76a66253 7134{
efe843d8
DG		 7135 /*
7136 * interpreted as no-op
7137 * XXX: specification say this is treated as a load by the MMU but
7138 * does not generate any exception
76a66253 7139 */
79aceca5
FB		 7140}
7141
9e0b5cb1
AG		 7142/* Embedded.Processor Control */
7143
7144static void gen_msgclr(DisasContext *ctx)
7145{
7146#if defined(CONFIG_USER_ONLY)
9b2fadda 7147 GEN_PRIV;
9e0b5cb1 7148#else
ebca5e6d 7149 CHK_HV;
d0db7cad 7150 if (is_book3s_arch2x(ctx)) {
7af1e7b0
CLG		 7151 gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
7152 } else {
7153 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
7154 }
9b2fadda 7155#endif /* defined(CONFIG_USER_ONLY) */
9e0b5cb1
AG		 7156}
7157
d5d11a39
AG		 7158static void gen_msgsnd(DisasContext *ctx)
7159{
7160#if defined(CONFIG_USER_ONLY)
9b2fadda 7161 GEN_PRIV;
d5d11a39 7162#else
ebca5e6d 7163 CHK_HV;
d0db7cad 7164 if (is_book3s_arch2x(ctx)) {
7af1e7b0
CLG		 7165 gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]);
7166 } else {
7167 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
7168 }
9b2fadda 7169#endif /* defined(CONFIG_USER_ONLY) */
d5d11a39
AG		 7170}
7171
5ba7ba1d
CLG		 7172#if defined(TARGET_PPC64)
7173static void gen_msgclrp(DisasContext *ctx)
7174{
7175#if defined(CONFIG_USER_ONLY)
7176 GEN_PRIV;
7177#else
7178 CHK_SV;
7179 gen_helper_book3s_msgclrp(cpu_env, cpu_gpr[rB(ctx->opcode)]);
7180#endif /* defined(CONFIG_USER_ONLY) */
7181}
7182
7183static void gen_msgsndp(DisasContext *ctx)
7184{
7185#if defined(CONFIG_USER_ONLY)
7186 GEN_PRIV;
7187#else
7188 CHK_SV;
7189 gen_helper_book3s_msgsndp(cpu_env, cpu_gpr[rB(ctx->opcode)]);
7190#endif /* defined(CONFIG_USER_ONLY) */
7191}
7192#endif
7193
7af1e7b0
CLG		 7194static void gen_msgsync(DisasContext *ctx)
7195{
7196#if defined(CONFIG_USER_ONLY)
7197 GEN_PRIV;
7198#else
7199 CHK_HV;
7200#endif /* defined(CONFIG_USER_ONLY) */
7201 /* interpreted as no-op */
7202}
b04ae981 7203
aeeb044c
ND		 7204#if defined(TARGET_PPC64)
7205static void gen_maddld(DisasContext *ctx)
7206{
7207 TCGv_i64 t1 = tcg_temp_new_i64();
7208
7209 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7210 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]);
7211 tcg_temp_free_i64(t1);
7212}
5f29cc82
ND		 7213
7214/* maddhd maddhdu */
7215static void gen_maddhd_maddhdu(DisasContext *ctx)
7216{
7217 TCGv_i64 lo = tcg_temp_new_i64();
7218 TCGv_i64 hi = tcg_temp_new_i64();
7219 TCGv_i64 t1 = tcg_temp_new_i64();
7220
7221 if (Rc(ctx->opcode)) {
7222 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
7223 cpu_gpr[rB(ctx->opcode)]);
7224 tcg_gen_movi_i64(t1, 0);
7225 } else {
7226 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
7227 cpu_gpr[rB(ctx->opcode)]);
7228 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63);
7229 }
7230 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi,
7231 cpu_gpr[rC(ctx->opcode)], t1);
7232 tcg_temp_free_i64(lo);
7233 tcg_temp_free_i64(hi);
7234 tcg_temp_free_i64(t1);
7235}
aeeb044c
ND		 7236#endif /* defined(TARGET_PPC64) */
7237
0ff93d11
TM		 7238static void gen_tbegin(DisasContext *ctx)
7239{
7240 if (unlikely(!ctx->tm_enabled)) {
7241 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
7242 return;
7243 }
7244 gen_helper_tbegin(cpu_env);
7245}
7246
56a84615
TM		 7247#define GEN_TM_NOOP(name) \
7248static inline void gen_##name(DisasContext *ctx) \
7249{ \
7250 if (unlikely(!ctx->tm_enabled)) { \
7251 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
7252 return; \
7253 } \
efe843d8
DG		 7254 /* \
7255 * Because tbegin always fails in QEMU, these user \
56a84615
TM		 7256 * space instructions all have a simple implementation: \
7257 * \
7258 * CR[0] = 0b0 || MSR[TS] || 0b0 \
7259 * = 0b0 || 0b00 || 0b0 \
7260 */ \
7261 tcg_gen_movi_i32(cpu_crf[0], 0); \
7262}
7263
7264GEN_TM_NOOP(tend);
7265GEN_TM_NOOP(tabort);
7266GEN_TM_NOOP(tabortwc);
7267GEN_TM_NOOP(tabortwci);
7268GEN_TM_NOOP(tabortdc);
7269GEN_TM_NOOP(tabortdci);
7270GEN_TM_NOOP(tsr);
efe843d8 7271
b8b4576e
SJS		 7272static inline void gen_cp_abort(DisasContext *ctx)
7273{
efe843d8 7274 /* Do Nothing */
b8b4576e 7275}
56a84615 7276
80b8c1ee
ND		 7277#define GEN_CP_PASTE_NOOP(name) \
7278static inline void gen_##name(DisasContext *ctx) \
7279{ \
efe843d8
DG		 7280 /* \
7281 * Generate invalid exception until we have an \
7282 * implementation of the copy paste facility \
80b8c1ee
ND		 7283 */ \
7284 gen_invalid(ctx); \
7285}
7286
7287GEN_CP_PASTE_NOOP(copy)
7288GEN_CP_PASTE_NOOP(paste)
7289
aeedd582
TM		 7290static void gen_tcheck(DisasContext *ctx)
7291{
7292 if (unlikely(!ctx->tm_enabled)) {
7293 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
7294 return;
7295 }
efe843d8
DG		 7296 /*
7297 * Because tbegin always fails, the tcheck implementation is
7298 * simple:
aeedd582
TM		 7299 *
7300 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
7301 * = 0b1 || 0b00 || 0b0
7302 */
7303 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
7304}
7305
f83c2378
TM		 7306#if defined(CONFIG_USER_ONLY)
7307#define GEN_TM_PRIV_NOOP(name) \
7308static inline void gen_##name(DisasContext *ctx) \
7309{ \
efe843d8 7310 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
f83c2378
TM		 7311}
7312
7313#else
7314
7315#define GEN_TM_PRIV_NOOP(name) \
7316static inline void gen_##name(DisasContext *ctx) \
7317{ \
9b2fadda 7318 CHK_SV; \
f83c2378
TM		 7319 if (unlikely(!ctx->tm_enabled)) { \
7320 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
7321 return; \
7322 } \
efe843d8
DG		 7323 /* \
7324 * Because tbegin always fails, the implementation is \
f83c2378
TM		 7325 * simple: \
7326 * \
7327 * CR[0] = 0b0 || MSR[TS] || 0b0 \
7328 * = 0b0 || 0b00 | 0b0 \
7329 */ \
7330 tcg_gen_movi_i32(cpu_crf[0], 0); \
7331}
7332
7333#endif
7334
7335GEN_TM_PRIV_NOOP(treclaim);
7336GEN_TM_PRIV_NOOP(trechkpt);
7337
1a404c91
MCA		 7338static inline void get_fpr(TCGv_i64 dst, int regno)
7339{
e7d3b272 7340 tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno));
1a404c91
MCA		 7341}
7342
7343static inline void set_fpr(int regno, TCGv_i64 src)
7344{
e7d3b272 7345 tcg_gen_st_i64(src, cpu_env, fpr_offset(regno));
1a404c91
MCA		 7346}
7347
c4a18dbf
MCA		 7348static inline void get_avr64(TCGv_i64 dst, int regno, bool high)
7349{
37da91f1 7350 tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high));
c4a18dbf
MCA		 7351}
7352
7353static inline void set_avr64(int regno, TCGv_i64 src, bool high)
7354{
37da91f1 7355 tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high));
c4a18dbf
MCA		 7356}
7357
f2aabda8
RH		 7358/*
7359 * Helpers for decodetree used by !function for decoding arguments.
7360 */
d39b2cc7
LP		 7361static int times_2(DisasContext *ctx, int x)
7362{
7363 return x * 2;
7364}
7365
f2aabda8
RH		 7366static int times_4(DisasContext *ctx, int x)
7367{
7368 return x * 4;
7369}
7370
e10271e1
MF		 7371static int times_16(DisasContext *ctx, int x)
7372{
7373 return x * 16;
7374}
7375
c9826ae9
RH		 7376/*
7377 * Helpers for trans_* functions to check for specific insns flags.
7378 * Use token pasting to ensure that we use the proper flag with the
7379 * proper variable.
7380 */
7381#define REQUIRE_INSNS_FLAGS(CTX, NAME) \
7382 do { \
7383 if (((CTX)->insns_flags & PPC_##NAME) == 0) { \
7384 return false; \
7385 } \
7386 } while (0)
7387
7388#define REQUIRE_INSNS_FLAGS2(CTX, NAME) \
7389 do { \
7390 if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \
7391 return false; \
7392 } \
7393 } while (0)
7394
7395/* Then special-case the check for 64-bit so that we elide code for ppc32. */
7396#if TARGET_LONG_BITS == 32
7397# define REQUIRE_64BIT(CTX) return false
7398#else
7399# define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B)
7400#endif
7401
e2205a46
BL		 7402#define REQUIRE_VECTOR(CTX) \
7403 do { \
7404 if (unlikely(!(CTX)->altivec_enabled)) { \
7405 gen_exception((CTX), POWERPC_EXCP_VPU); \
7406 return true; \
7407 } \
8226cb2d
BL		 7408 } while (0)
7409
7410#define REQUIRE_VSX(CTX) \
7411 do { \
7412 if (unlikely(!(CTX)->vsx_enabled)) { \
7413 gen_exception((CTX), POWERPC_EXCP_VSXU); \
7414 return true; \
7415 } \
e2205a46
BL		 7416 } while (0)
7417
86057426
FV		 7418#define REQUIRE_FPU(ctx) \
7419 do { \
7420 if (unlikely(!(ctx)->fpu_enabled)) { \
7421 gen_exception((ctx), POWERPC_EXCP_FPU); \
7422 return true; \
7423 } \
7424 } while (0)
7425
f2aabda8
RH		 7426/*
7427 * Helpers for implementing sets of trans_* functions.
7428 * Defer the implementation of NAME to FUNC, with optional extra arguments.
7429 */
7430#define TRANS(NAME, FUNC, ...) \
7431 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
7432 { return FUNC(ctx, a, __VA_ARGS__); }
7433
7434#define TRANS64(NAME, FUNC, ...) \
7435 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
7436 { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); }
7437
7438/* TODO: More TRANS* helpers for extra insn_flags checks. */
7439
7440
99082815
RH		 7441#include "decode-insn32.c.inc"
7442#include "decode-insn64.c.inc"
565cb109
GR		 7443#include "power8-pmu-regs.c.inc"
7444
725b2d4d
FEV		 7445/*
7446 * Incorporate CIA into the constant when R=1.
7447 * Validate that when R=1, RA=0.
7448 */
7449static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a)
7450{
7451 d->rt = a->rt;
7452 d->ra = a->ra;
7453 d->si = a->si;
7454 if (a->r) {
7455 if (unlikely(a->ra != 0)) {
7456 gen_invalid(ctx);
7457 return false;
7458 }
7459 d->si += ctx->cia;
7460 }
7461 return true;
7462}
7463
99082815
RH		 7464#include "translate/fixedpoint-impl.c.inc"
7465
139c1837 7466#include "translate/fp-impl.c.inc"
15848410 7467
139c1837 7468#include "translate/vmx-impl.c.inc"
15848410 7469
139c1837 7470#include "translate/vsx-impl.c.inc"
15848410 7471
139c1837 7472#include "translate/dfp-impl.c.inc"
15848410 7473
139c1837 7474#include "translate/spe-impl.c.inc"
15848410 7475
1f26c751
DHB		 7476#include "translate/branch-impl.c.inc"
7477
5cb091a4
ND		 7478/* Handles lfdp, lxsd, lxssp */
7479static void gen_dform39(DisasContext *ctx)
7480{
7481 switch (ctx->opcode & 0x3) {
7482 case 0: /* lfdp */
7483 if (ctx->insns_flags2 & PPC2_ISA205) {
7484 return gen_lfdp(ctx);
7485 }
7486 break;
7487 case 2: /* lxsd */
7488 if (ctx->insns_flags2 & PPC2_ISA300) {
7489 return gen_lxsd(ctx);
7490 }
7491 break;
7492 case 3: /* lxssp */
7493 if (ctx->insns_flags2 & PPC2_ISA300) {
7494 return gen_lxssp(ctx);
7495 }
7496 break;
7497 }
7498 return gen_invalid(ctx);
7499}
7500
d59ba583 7501/* handles stfdp, lxv, stxsd, stxssp lxvx */
e3001664
ND		 7502static void gen_dform3D(DisasContext *ctx)
7503{
72b70d5c 7504 if ((ctx->opcode & 3) != 1) { /* DS-FORM */
e3001664
ND		 7505 switch (ctx->opcode & 0x3) {
7506 case 0: /* stfdp */
7507 if (ctx->insns_flags2 & PPC2_ISA205) {
7508 return gen_stfdp(ctx);
7509 }
7510 break;
7511 case 2: /* stxsd */
7512 if (ctx->insns_flags2 & PPC2_ISA300) {
7513 return gen_stxsd(ctx);
7514 }
7515 break;
7516 case 3: /* stxssp */
7517 if (ctx->insns_flags2 & PPC2_ISA300) {
7518 return gen_stxssp(ctx);
7519 }
7520 break;
7521 }
7522 }
7523 return gen_invalid(ctx);
7524}
7525
9d69cfa2
LP		 7526#if defined(TARGET_PPC64)
7527/* brd */
7528static void gen_brd(DisasContext *ctx)
7529{
7530 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
7531}
7532
7533/* brw */
7534static void gen_brw(DisasContext *ctx)
7535{
7536 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
7537 tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32);
7538
7539}
7540
7541/* brh */
7542static void gen_brh(DisasContext *ctx)
7543{
491b3cca 7544 TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull);
9d69cfa2
LP		 7545 TCGv_i64 t1 = tcg_temp_new_i64();
7546 TCGv_i64 t2 = tcg_temp_new_i64();
7547
9d69cfa2 7548 tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8);
491b3cca
PMD		 7549 tcg_gen_and_i64(t2, t1, mask);
7550 tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask);
9d69cfa2
LP		 7551 tcg_gen_shli_i64(t1, t1, 8);
7552 tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2);
7553
9d69cfa2
LP		 7554 tcg_temp_free_i64(t1);
7555 tcg_temp_free_i64(t2);
7556}
7557#endif
7558
c227f099 7559static opcode_t opcodes[] = {
9d69cfa2
LP		 7560#if defined(TARGET_PPC64)
7561GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310),
7562GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310),
7563GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310),
7564#endif
5c55ff99 7565GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
082ce330
ND		 7566#if defined(TARGET_PPC64)
7567GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
7568#endif
fcfda20f 7569GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
f2442ef9 7570GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
5c55ff99 7571GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
5c55ff99
BS		 7572GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
7573GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
5c55ff99
BS		 7574GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
7575GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
7576GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
7577GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
7578GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
7579#if defined(TARGET_PPC64)
7580GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
7581#endif
7582GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
7583GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
7584GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
7585GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
7586GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
7587GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
b35344e4 7588GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
80b8c1ee 7589GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300),
b8b4576e 7590GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
80b8c1ee 7591GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300),
5c55ff99
BS		 7592GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
7593GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
7594GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
7595GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
7596GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
7597GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6ab39b1b 7598GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
eaabeef2 7599GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
725bcec2 7600GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
5c55ff99 7601#if defined(TARGET_PPC64)
eaabeef2 7602GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
5c55ff99 7603GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
e91d95b2 7604GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300),
fec5c62a 7605GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300),
725bcec2 7606GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
86ba37ed 7607GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
5c55ff99
BS		 7608#endif
7609GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
7610GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
7611GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
7612GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
7613GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
7614GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
7615GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
7616#if defined(TARGET_PPC64)
7617GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
7618GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
7619GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
7620GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
7621GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
787bbe37
ND		 7622GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
7623 PPC_NONE, PPC2_ISA300),
7624GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
7625 PPC_NONE, PPC2_ISA300),
5c55ff99 7626#endif
5cb091a4
ND		 7627/* handles lfdp, lxsd, lxssp */
7628GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
72b70d5c 7629/* handles stfdp, stxsd, stxssp */
e3001664 7630GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
5c55ff99
BS		 7631GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
7632GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
7633GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
7634GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
7635GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
7636GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
c8fd8373 7637GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO),
5c55ff99 7638GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
5c77a786
TM		 7639GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
7640GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
f844c817 7641GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
a68a6146 7642GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300),
a3401188 7643GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300),
587c51f7
TM		 7644GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
7645GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
5c55ff99
BS		 7646GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
7647#if defined(TARGET_PPC64)
a68a6146 7648GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300),
a3401188 7649GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300),
f844c817 7650GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
9c294d5a 7651GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
5c55ff99 7652GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
27b95bfe 7653GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
5c55ff99
BS		 7654#endif
7655GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
7656GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
c09cec68 7657GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300),
5c55ff99
BS		 7658GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
7659GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
7660GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
7661GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
4aaefd93 7662GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207),
5c55ff99
BS		 7663GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
7664GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
7665#if defined(TARGET_PPC64)
7666GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
3c89b8d6
NP		 7667#if !defined(CONFIG_USER_ONLY)
7668/* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */
7669GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300),
7670GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300),
7671GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300),
7672#endif
cdee0e72 7673GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300),
7778a575
BH		 7674GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
7675GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
7676GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
7677GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
5c55ff99
BS		 7678GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
7679#endif
3c89b8d6
NP		 7680/* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */
7681GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW),
7682GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW),
5c55ff99
BS		 7683GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
7684GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
7685#if defined(TARGET_PPC64)
7686GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
7687GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
7688#endif
7689GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
7690GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
7691GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
7692GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
7693GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
7694GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
7695#if defined(TARGET_PPC64)
7696GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
dc2ee038 7697GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
b63d0434 7698GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300),
5c55ff99 7699#endif
5e31867f 7700GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
4248b336 7701GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
5c55ff99 7702GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
50728199 7703GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206),
5c55ff99
BS		 7704GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
7705GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
50728199 7706GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206),
3f34cf91 7707GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
50728199 7708GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206),
3f34cf91 7709GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
50728199 7710GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206),
4d09d529 7711GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
8e33944f 7712GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
50728199 7713GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206),
5c55ff99 7714GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
99d45f8f 7715GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC),
5c55ff99
BS		 7716GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
7717GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
50728199 7718GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206),
5c55ff99
BS		 7719GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
7720GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
7721GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
7722GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
7723GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
7724#if defined(TARGET_PPC64)
7725GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
7726GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
7727 PPC_SEGMENT_64B),
7728GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
7729GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
7730 PPC_SEGMENT_64B),
efdef95f
DG		 7731GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
7732GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
7733GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
c76c22d5 7734GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
5c55ff99
BS		 7735#endif
7736GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
efe843d8
DG		 7737/*
7738 * XXX Those instructions will need to be handled differently for
7739 * different ISA versions
7740 */
f9ef0527
BH		 7741GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
7742GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
c8830502
SJS		 7743GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300),
7744GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300),
5c55ff99
BS		 7745GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
7746#if defined(TARGET_PPC64)
2f9254d9 7747GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
5c55ff99 7748GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
a63f1dfc 7749GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300),
62d897ca 7750GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
5c55ff99
BS		 7751#endif
7752GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
7753GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
7754GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
7755GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
7756GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
7757GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
7758GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
7759GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
7760GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
7761GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
7762GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
7763GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
7764GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
7765GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
7766GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
7767GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
7768GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
7769GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
7770GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
7771GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
7772GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
7773GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
7774GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
7775GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
7776GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
7777GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
7778GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
7779GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
7780GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
7781GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
7782GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
7783GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
7784GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
7785GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
7786GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
7787GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
7788GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
7789GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
7790GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
7791GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
7792GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
5c55ff99
BS		 7793GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
7794GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
7795GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
7796GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
7797GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
7798GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
7799GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
7800GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
7801GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
7802GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
7803GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
7804GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
7805GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
7806GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
7807GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
7808GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
7809GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
7810GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
7811GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
7812GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
7813GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
7814GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
7815GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
7816GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
7817GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
7818GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
7819GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
7820GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
01662f3e 7821GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
5c55ff99
BS		 7822GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
7823GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
7824GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
7825GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
7826GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
7827GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
7828GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
7829GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
01662f3e
AG		 7830GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
7831 PPC_NONE, PPC2_BOOKE206),
7832GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
7833 PPC_NONE, PPC2_BOOKE206),
7834GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
7835 PPC_NONE, PPC2_BOOKE206),
7836GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
7837 PPC_NONE, PPC2_BOOKE206),
6d3db821
AG		 7838GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
7839 PPC_NONE, PPC2_BOOKE206),
d5d11a39
AG		 7840GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
7841 PPC_NONE, PPC2_PRCNTL),
9e0b5cb1
AG		 7842GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
7843 PPC_NONE, PPC2_PRCNTL),
7af1e7b0
CLG		 7844GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000,
7845 PPC_NONE, PPC2_PRCNTL),
5c55ff99 7846GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
fbe73008 7847GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
5c55ff99 7848GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
01662f3e
AG		 7849GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
7850 PPC_BOOKE, PPC2_BOOKE206),
27a3ea7e 7851GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE),
01662f3e
AG		 7852GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
7853 PPC_BOOKE, PPC2_BOOKE206),
0c8d8c8b 7854GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001,
27a3ea7e 7855 PPC_440_SPEC),
5c55ff99
BS		 7856GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
7857GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
7858GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
7859GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
5c55ff99 7860GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
aeeb044c 7861#if defined(TARGET_PPC64)
5f29cc82
ND		 7862GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE,
7863 PPC2_ISA300),
aeeb044c 7864GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
5ba7ba1d
CLG		 7865GEN_HANDLER2_E(msgsndp, "msgsndp", 0x1F, 0x0E, 0x04, 0x03ff0001,
7866 PPC_NONE, PPC2_ISA207S),
7867GEN_HANDLER2_E(msgclrp, "msgclrp", 0x1F, 0x0E, 0x05, 0x03ff0001,
7868 PPC_NONE, PPC2_ISA207S),
aeeb044c 7869#endif
5c55ff99
BS		 7870
7871#undef GEN_INT_ARITH_ADD
7872#undef GEN_INT_ARITH_ADD_CONST
7873#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
7874GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
7875#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
7876 add_ca, compute_ca, compute_ov) \
7877GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
7878GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
7879GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
7880GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
7881GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
7882GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
7883GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
7884GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
7885GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
4c5920af 7886GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300),
5c55ff99
BS		 7887GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
7888GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
7889
7890#undef GEN_INT_ARITH_DIVW
7891#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
7892GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
7893GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
7894GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
7895GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
7896GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
a98eb9e9
TM		 7897GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
7898GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6a4fda33
TM		 7899GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
7900GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
af2c6620
ND		 7901GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
7902GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
5c55ff99
BS		 7903
7904#if defined(TARGET_PPC64)
7905#undef GEN_INT_ARITH_DIVD
7906#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
7907GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
7908GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
7909GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
7910GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
7911GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
7912
98d1eb27
TM		 7913GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
7914GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
e44259b6
TM		 7915GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
7916GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
063cf14f
ND		 7917GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
7918GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
98d1eb27 7919
5c55ff99
BS		 7920#undef GEN_INT_ARITH_MUL_HELPER
7921#define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
7922GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
7923GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
7924GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
7925GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
7926#endif
7927
7928#undef GEN_INT_ARITH_SUBF
7929#undef GEN_INT_ARITH_SUBF_CONST
7930#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
7931GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
7932#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
7933 add_ca, compute_ca, compute_ov) \
7934GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
7935GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
7936GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
7937GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
7938GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
7939GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
7940GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
7941GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
7942GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
7943GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
7944GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
7945
7946#undef GEN_LOGICAL1
7947#undef GEN_LOGICAL2
7948#define GEN_LOGICAL2(name, tcg_op, opc, type) \
7949GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
7950#define GEN_LOGICAL1(name, tcg_op, opc, type) \
7951GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
7952GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
7953GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
7954GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
7955GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
7956GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
7957GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
7958GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
7959GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
7960#if defined(TARGET_PPC64)
7961GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
7962#endif
7963
7964#if defined(TARGET_PPC64)
7965#undef GEN_PPC64_R2
7966#undef GEN_PPC64_R4
7967#define GEN_PPC64_R2(name, opc1, opc2) \
7968GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
7969GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
7970 PPC_64B)
7971#define GEN_PPC64_R4(name, opc1, opc2) \
7972GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
7973GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
7974 PPC_64B), \
7975GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
7976 PPC_64B), \
7977GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
7978 PPC_64B)
7979GEN_PPC64_R4(rldicl, 0x1E, 0x00),
7980GEN_PPC64_R4(rldicr, 0x1E, 0x02),
7981GEN_PPC64_R4(rldic, 0x1E, 0x04),
7982GEN_PPC64_R2(rldcl, 0x1E, 0x08),
7983GEN_PPC64_R2(rldcr, 0x1E, 0x09),
7984GEN_PPC64_R4(rldimi, 0x1E, 0x06),
7985#endif
7986
cd6e9320 7987#undef GEN_LDX_E
b7815375 7988#define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
cd6e9320 7989GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
f2aabda8 7990
5c55ff99 7991#if defined(TARGET_PPC64)
ff5f3981 7992GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
b7815375
BH		 7993
7994/* HV/P7 and later only */
4f364fe7 7995GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
b7815375
BH		 7996GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST)
7997GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
7998GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
5c55ff99
BS		 7999#endif
8000GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
8001GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
8002
50728199
RK		 8003/* External PID based load */
8004#undef GEN_LDEPX
8005#define GEN_LDEPX(name, ldop, opc2, opc3) \
8006GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \
8007 0x00000001, PPC_NONE, PPC2_BOOKE206),
8008
8009GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02)
8010GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08)
8011GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00)
8012#if defined(TARGET_PPC64)
8013GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00)
8014#endif
8015
cd6e9320 8016#undef GEN_STX_E
b7815375 8017#define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
0123d3cb 8018GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2),
e8f4c8d6 8019
5c55ff99 8020#if defined(TARGET_PPC64)
804108aa 8021GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
2468f23d 8022GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
b7815375
BH		 8023GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
8024GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
8025GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
5c55ff99
BS		 8026#endif
8027GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
8028GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
8029
50728199
RK		 8030#undef GEN_STEPX
8031#define GEN_STEPX(name, ldop, opc2, opc3) \
8032GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \
8033 0x00000001, PPC_NONE, PPC2_BOOKE206),
8034
8035GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06)
8036GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C)
8037GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04)
8038#if defined(TARGET_PPC64)
8039GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1D, 0x04)
8040#endif
8041
5c55ff99
BS		 8042#undef GEN_CRLOGIC
8043#define GEN_CRLOGIC(name, tcg_op, opc) \
8044GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
8045GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
8046GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
8047GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
8048GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
8049GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
8050GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
8051GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
8052GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
8053
8054#undef GEN_MAC_HANDLER
8055#define GEN_MAC_HANDLER(name, opc2, opc3) \
8056GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
8057GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
8058GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
8059GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
8060GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
8061GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
8062GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
8063GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
8064GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
8065GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
8066GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
8067GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
8068GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
8069GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
8070GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
8071GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
8072GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
8073GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
8074GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
8075GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
8076GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
8077GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
8078GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
8079GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
8080GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
8081GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
8082GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
8083GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
8084GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
8085GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
8086GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
8087GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
8088GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
8089GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
8090GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
8091GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
8092GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
8093GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
8094GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
8095GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
8096GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
8097GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
8098GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
8099
0ff93d11
TM		 8100GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
8101 PPC_NONE, PPC2_TM),
56a84615
TM		 8102GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
8103 PPC_NONE, PPC2_TM),
8104GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
8105 PPC_NONE, PPC2_TM),
8106GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
8107 PPC_NONE, PPC2_TM),
8108GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
8109 PPC_NONE, PPC2_TM),
8110GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
8111 PPC_NONE, PPC2_TM),
8112GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
8113 PPC_NONE, PPC2_TM),
8114GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
8115 PPC_NONE, PPC2_TM),
aeedd582
TM		 8116GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
8117 PPC_NONE, PPC2_TM),
f83c2378
TM		 8118GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
8119 PPC_NONE, PPC2_TM),
8120GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
8121 PPC_NONE, PPC2_TM),
15848410 8122
139c1837 8123#include "translate/fp-ops.c.inc"
15848410 8124
139c1837 8125#include "translate/vmx-ops.c.inc"
15848410 8126
139c1837 8127#include "translate/vsx-ops.c.inc"
15848410 8128
139c1837 8129#include "translate/spe-ops.c.inc"
5c55ff99
BS		 8130};
8131
7468e2c8
BL		 8132/*****************************************************************************/
8133/* Opcode types */
8134enum {
8135 PPC_DIRECT = 0, /* Opcode routine */
8136 PPC_INDIRECT = 1, /* Indirect opcode table */
8137};
8138
8139#define PPC_OPCODE_MASK 0x3
8140
8141static inline int is_indirect_opcode(void *handler)
8142{
8143 return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT;
8144}
8145
8146static inline opc_handler_t **ind_table(void *handler)
8147{
8148 return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK);
8149}
8150
8151/* Instruction table creation */
8152/* Opcodes tables creation */
8153static void fill_new_table(opc_handler_t **table, int len)
8154{
8155 int i;
8156
8157 for (i = 0; i < len; i++) {
8158 table[i] = &invalid_handler;
8159 }
8160}
8161
8162static int create_new_table(opc_handler_t **table, unsigned char idx)
8163{
8164 opc_handler_t **tmp;
8165
8166 tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN);
8167 fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN);
8168 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
8169
8170 return 0;
8171}
8172
8173static int insert_in_table(opc_handler_t **table, unsigned char idx,
8174 opc_handler_t *handler)
8175{
8176 if (table[idx] != &invalid_handler) {
8177 return -1;
8178 }
8179 table[idx] = handler;
8180
8181 return 0;
8182}
8183
8184static int register_direct_insn(opc_handler_t **ppc_opcodes,
8185 unsigned char idx, opc_handler_t *handler)
8186{
8187 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
8188 printf("*** ERROR: opcode %02x already assigned in main "
8189 "opcode table\n", idx);
7468e2c8
BL		 8190 return -1;
8191 }
8192
8193 return 0;
8194}
8195
8196static int register_ind_in_table(opc_handler_t **table,
8197 unsigned char idx1, unsigned char idx2,
8198 opc_handler_t *handler)
8199{
8200 if (table[idx1] == &invalid_handler) {
8201 if (create_new_table(table, idx1) < 0) {
8202 printf("*** ERROR: unable to create indirect table "
8203 "idx=%02x\n", idx1);
8204 return -1;
8205 }
8206 } else {
8207 if (!is_indirect_opcode(table[idx1])) {
8208 printf("*** ERROR: idx %02x already assigned to a direct "
8209 "opcode\n", idx1);
7468e2c8
BL		 8210 return -1;
8211 }
8212 }
8213 if (handler != NULL &&
8214 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
8215 printf("*** ERROR: opcode %02x already assigned in "
8216 "opcode table %02x\n", idx2, idx1);
7468e2c8
BL		 8217 return -1;
8218 }
8219
8220 return 0;
8221}
8222
8223static int register_ind_insn(opc_handler_t **ppc_opcodes,
8224 unsigned char idx1, unsigned char idx2,
8225 opc_handler_t *handler)
8226{
8227 return register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
8228}
8229
8230static int register_dblind_insn(opc_handler_t **ppc_opcodes,
8231 unsigned char idx1, unsigned char idx2,
8232 unsigned char idx3, opc_handler_t *handler)
8233{
8234 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
8235 printf("*** ERROR: unable to join indirect table idx "
8236 "[%02x-%02x]\n", idx1, idx2);
8237 return -1;
8238 }
8239 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
8240 handler) < 0) {
8241 printf("*** ERROR: unable to insert opcode "
8242 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
8243 return -1;
8244 }
8245
8246 return 0;
8247}
8248
8249static int register_trplind_insn(opc_handler_t **ppc_opcodes,
8250 unsigned char idx1, unsigned char idx2,
8251 unsigned char idx3, unsigned char idx4,
8252 opc_handler_t *handler)
8253{
8254 opc_handler_t **table;
8255
8256 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
8257 printf("*** ERROR: unable to join indirect table idx "
8258 "[%02x-%02x]\n", idx1, idx2);
8259 return -1;
8260 }
8261 table = ind_table(ppc_opcodes[idx1]);
8262 if (register_ind_in_table(table, idx2, idx3, NULL) < 0) {
8263 printf("*** ERROR: unable to join 2nd-level indirect table idx "
8264 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
8265 return -1;
8266 }
8267 table = ind_table(table[idx2]);
8268 if (register_ind_in_table(table, idx3, idx4, handler) < 0) {
8269 printf("*** ERROR: unable to insert opcode "
8270 "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4);
8271 return -1;
8272 }
8273 return 0;
8274}
8275static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn)
8276{
8277 if (insn->opc2 != 0xFF) {
8278 if (insn->opc3 != 0xFF) {
8279 if (insn->opc4 != 0xFF) {
8280 if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2,
8281 insn->opc3, insn->opc4,
8282 &insn->handler) < 0) {
8283 return -1;
8284 }
8285 } else {
8286 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
8287 insn->opc3, &insn->handler) < 0) {
8288 return -1;
8289 }
8290 }
8291 } else {
8292 if (register_ind_insn(ppc_opcodes, insn->opc1,
8293 insn->opc2, &insn->handler) < 0) {
8294 return -1;
8295 }
8296 }
8297 } else {
8298 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) {
8299 return -1;
8300 }
8301 }
8302
8303 return 0;
8304}
8305
8306static int test_opcode_table(opc_handler_t **table, int len)
8307{
8308 int i, count, tmp;
8309
8310 for (i = 0, count = 0; i < len; i++) {
8311 /* Consistency fixup */
8312 if (table[i] == NULL) {
8313 table[i] = &invalid_handler;
8314 }
8315 if (table[i] != &invalid_handler) {
8316 if (is_indirect_opcode(table[i])) {
8317 tmp = test_opcode_table(ind_table(table[i]),
8318 PPC_CPU_INDIRECT_OPCODES_LEN);
8319 if (tmp == 0) {
8320 free(table[i]);
8321 table[i] = &invalid_handler;
8322 } else {
8323 count++;
8324 }
8325 } else {
8326 count++;
8327 }
8328 }
8329 }
8330
8331 return count;
8332}
8333
8334static void fix_opcode_tables(opc_handler_t **ppc_opcodes)
8335{
8336 if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) {
8337 printf("*** WARNING: no opcode defined !\n");
8338 }
8339}
8340
8341/*****************************************************************************/
8342void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
8343{
8344 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8345 opcode_t *opc;
8346
8347 fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN);
8348 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
8349 if (((opc->handler.type & pcc->insns_flags) != 0) ||
8350 ((opc->handler.type2 & pcc->insns_flags2) != 0)) {
8351 if (register_insn(cpu->opcodes, opc) < 0) {
8352 error_setg(errp, "ERROR initializing PowerPC instruction "
8353 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2,
8354 opc->opc3);
8355 return;
8356 }
8357 }
8358 }
8359 fix_opcode_tables(cpu->opcodes);
8360 fflush(stdout);
8361 fflush(stderr);
8362}
8363
8364void destroy_ppc_opcodes(PowerPCCPU *cpu)
8365{
8366 opc_handler_t **table, **table_2;
8367 int i, j, k;
8368
8369 for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) {
8370 if (cpu->opcodes[i] == &invalid_handler) {
8371 continue;
8372 }
8373 if (is_indirect_opcode(cpu->opcodes[i])) {
8374 table = ind_table(cpu->opcodes[i]);
8375 for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) {
8376 if (table[j] == &invalid_handler) {
8377 continue;
8378 }
8379 if (is_indirect_opcode(table[j])) {
8380 table_2 = ind_table(table[j]);
8381 for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) {
8382 if (table_2[k] != &invalid_handler &&
8383 is_indirect_opcode(table_2[k])) {
8384 g_free((opc_handler_t *)((uintptr_t)table_2[k] &
8385 ~PPC_INDIRECT));
8386 }
8387 }
8388 g_free((opc_handler_t *)((uintptr_t)table[j] &
8389 ~PPC_INDIRECT));
8390 }
8391 }
8392 g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] &
8393 ~PPC_INDIRECT));
8394 }
8395 }
8396}
8397
7468e2c8
BL		 8398int ppc_fixup_cpu(PowerPCCPU *cpu)
8399{
8400 CPUPPCState *env = &cpu->env;
8401
8402 /*
8403 * TCG doesn't (yet) emulate some groups of instructions that are
8404 * implemented on some otherwise supported CPUs (e.g. VSX and
8405 * decimal floating point instructions on POWER7). We remove
8406 * unsupported instruction groups from the cpu state's instruction
8407 * masks and hope the guest can cope. For at least the pseries
8408 * machine, the unavailability of these instructions can be
8409 * advertised to the guest via the device tree.
8410 */
8411 if ((env->insns_flags & ~PPC_TCG_INSNS)
8412 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
8413 warn_report("Disabling some instructions which are not "
8414 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")",
8415 env->insns_flags & ~PPC_TCG_INSNS,
8416 env->insns_flags2 & ~PPC_TCG_INSNS2);
8417 }
8418 env->insns_flags &= PPC_TCG_INSNS;
8419 env->insns_flags2 &= PPC_TCG_INSNS2;
8420 return 0;
8421}
8422
624cb07f
RH		 8423static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn)
8424{
8425 opc_handler_t **table, *handler;
8426 uint32_t inval;
8427
8428 ctx->opcode = insn;
8429
8430 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
8431 insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn),
8432 ctx->le_mode ? "little" : "big");
8433
8434 table = cpu->opcodes;
8435 handler = table[opc1(insn)];
8436 if (is_indirect_opcode(handler)) {
8437 table = ind_table(handler);
8438 handler = table[opc2(insn)];
8439 if (is_indirect_opcode(handler)) {
8440 table = ind_table(handler);
8441 handler = table[opc3(insn)];
8442 if (is_indirect_opcode(handler)) {
8443 table = ind_table(handler);
8444 handler = table[opc4(insn)];
8445 }
8446 }
8447 }
8448
8449 /* Is opcode *REALLY* valid ? */
8450 if (unlikely(handler->handler == &gen_invalid)) {
8451 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
8452 "%02x - %02x - %02x - %02x (%08x) "
8453 TARGET_FMT_lx "\n",
8454 opc1(insn), opc2(insn), opc3(insn), opc4(insn),
8455 insn, ctx->cia);
8456 return false;
8457 }
8458
8459 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE)
8460 && Rc(insn))) {
8461 inval = handler->inval2;
8462 } else {
8463 inval = handler->inval1;
8464 }
8465
8466 if (unlikely((insn & inval) != 0)) {
8467 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
8468 "%02x - %02x - %02x - %02x (%08x) "
8469 TARGET_FMT_lx "\n", insn & inval,
8470 opc1(insn), opc2(insn), opc3(insn), opc4(insn),
8471 insn, ctx->cia);
8472 return false;
8473 }
8474
8475 handler->handler(ctx);
8476 return true;
8477}
8478
b542683d 8479static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
79aceca5 8480{
b0c2d521 8481 DisasContext *ctx = container_of(dcbase, DisasContext, base);
9c489ea6 8482 CPUPPCState *env = cs->env_ptr;
2df4fe7a 8483 uint32_t hflags = ctx->base.tb->flags;
b0c2d521 8484
b0c2d521 8485 ctx->spr_cb = env->spr_cb;
2df4fe7a 8486 ctx->pr = (hflags >> HFLAGS_PR) & 1;
d764184d 8487 ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7;
2df4fe7a
RH		 8488 ctx->dr = (hflags >> HFLAGS_DR) & 1;
8489 ctx->hv = (hflags >> HFLAGS_HV) & 1;
b0c2d521
EC		 8490 ctx->insns_flags = env->insns_flags;
8491 ctx->insns_flags2 = env->insns_flags2;
8492 ctx->access_type = -1;
d57d72a8 8493 ctx->need_access_type = !mmu_is_64bit(env->mmu_model);
2df4fe7a 8494 ctx->le_mode = (hflags >> HFLAGS_LE) & 1;
b0c2d521 8495 ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE;
0e3bf489 8496 ctx->flags = env->flags;
d9bce9d9 8497#if defined(TARGET_PPC64)
2df4fe7a 8498 ctx->sf_mode = (hflags >> HFLAGS_64) & 1;
b0c2d521 8499 ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
9a64fbe4 8500#endif
e69ba2b4
DG		 8501 ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B
8502 || env->mmu_model == POWERPC_MMU_601
d55dfd44 8503 || env->mmu_model & POWERPC_MMU_64;
c5a8d8f3 8504
2df4fe7a
RH		 8505 ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1;
8506 ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1;
8507 ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1;
8508 ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1;
2df4fe7a 8509 ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1;
f03de3b4 8510 ctx->gtse = (hflags >> HFLAGS_GTSE) & 1;
1db3632a 8511 ctx->hr = (hflags >> HFLAGS_HR) & 1;
f7460df2
DHB		 8512 ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1;
8513 ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1;
46d396bd 8514 ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1;
2df4fe7a
RH		 8515
8516 ctx->singlestep_enabled = 0;
8517 if ((hflags >> HFLAGS_SE) & 1) {
8518 ctx->singlestep_enabled |= CPU_SINGLE_STEP;
9498d103 8519 ctx->base.max_insns = 1;
efe843d8 8520 }
2df4fe7a 8521 if ((hflags >> HFLAGS_BE) & 1) {
b0c2d521 8522 ctx->singlestep_enabled |= CPU_BRANCH_STEP;
efe843d8 8523 }
b0c2d521
EC		 8524}
8525
8526static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs)
8527{
8528}
8529
8530static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
8531{
8532 tcg_gen_insn_start(dcbase->pc_next);
8533}
8534
99082815
RH		 8535static bool is_prefix_insn(DisasContext *ctx, uint32_t insn)
8536{
8537 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
8538 return opc1(insn) == 1;
8539}
8540
b0c2d521
EC		 8541static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
8542{
8543 DisasContext *ctx = container_of(dcbase, DisasContext, base);
28876bf2 8544 PowerPCCPU *cpu = POWERPC_CPU(cs);
b0c2d521 8545 CPUPPCState *env = cs->env_ptr;
99082815 8546 target_ulong pc;
624cb07f
RH		 8547 uint32_t insn;
8548 bool ok;
b0c2d521
EC		 8549
8550 LOG_DISAS("----------------\n");
8551 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
8552 ctx->base.pc_next, ctx->mem_idx, (int)msr_ir);
8553
99082815 8554 ctx->cia = pc = ctx->base.pc_next;
4e116893 8555 insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx));
99082815 8556 ctx->base.pc_next = pc += 4;
70560da7 8557
99082815
RH		 8558 if (!is_prefix_insn(ctx, insn)) {
8559 ok = (decode_insn32(ctx, insn) ||
8560 decode_legacy(cpu, ctx, insn));
8561 } else if ((pc & 63) == 0) {
8562 /*
8563 * Power v3.1, section 1.9 Exceptions:
8564 * attempt to execute a prefixed instruction that crosses a
8565 * 64-byte address boundary (system alignment error).
8566 */
8567 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN);
8568 ok = true;
8569 } else {
4e116893
IL		 8570 uint32_t insn2 = translator_ldl_swap(env, dcbase, pc,
8571 need_byteswap(ctx));
99082815
RH		 8572 ctx->base.pc_next = pc += 4;
8573 ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn));
8574 }
624cb07f
RH		 8575 if (!ok) {
8576 gen_invalid(ctx);
b0c2d521 8577 }
624cb07f 8578
64a0f644 8579 /* End the TB when crossing a page boundary. */
99082815 8580 if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) {
64a0f644
RH		 8581 ctx->base.is_jmp = DISAS_TOO_MANY;
8582 }
8583
51eb7b1d 8584 translator_loop_temp_check(&ctx->base);
b0c2d521
EC		 8585}
8586
8587static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
8588{
8589 DisasContext *ctx = container_of(dcbase, DisasContext, base);
a9b5b3d0
RH		 8590 DisasJumpType is_jmp = ctx->base.is_jmp;
8591 target_ulong nip = ctx->base.pc_next;
b0c2d521 8592
a9b5b3d0
RH		 8593 if (is_jmp == DISAS_NORETURN) {
8594 /* We have already exited the TB. */
3d8a5b69
RH		 8595 return;
8596 }
8597
a9b5b3d0 8598 /* Honor single stepping. */
9498d103
RH		 8599 if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP)
8600 && (nip <= 0x100 || nip > 0xf00)) {
a9b5b3d0
RH		 8601 switch (is_jmp) {
8602 case DISAS_TOO_MANY:
8603 case DISAS_EXIT_UPDATE:
8604 case DISAS_CHAIN_UPDATE:
8605 gen_update_nip(ctx, nip);
8606 break;
8607 case DISAS_EXIT:
8608 case DISAS_CHAIN:
8609 break;
8610 default:
8611 g_assert_not_reached();
8cbcb4fa 8612 }
13b45575 8613
9498d103
RH		 8614 gen_debug_exception(ctx);
8615 return;
a9b5b3d0
RH		 8616 }
8617
8618 switch (is_jmp) {
8619 case DISAS_TOO_MANY:
8620 if (use_goto_tb(ctx, nip)) {
46d396bd 8621 pmu_count_insns(ctx);
a9b5b3d0
RH		 8622 tcg_gen_goto_tb(0);
8623 gen_update_nip(ctx, nip);
8624 tcg_gen_exit_tb(ctx->base.tb, 0);
8625 break;
8626 }
8627 /* fall through */
8628 case DISAS_CHAIN_UPDATE:
8629 gen_update_nip(ctx, nip);
8630 /* fall through */
8631 case DISAS_CHAIN:
46d396bd
DHB		 8632 /*
8633 * tcg_gen_lookup_and_goto_ptr will exit the TB if
8634 * CF_NO_GOTO_PTR is set. Count insns now.
8635 */
8636 if (ctx->base.tb->flags & CF_NO_GOTO_PTR) {
8637 pmu_count_insns(ctx);
8638 }
8639
a9b5b3d0
RH		 8640 tcg_gen_lookup_and_goto_ptr();
8641 break;
8642
8643 case DISAS_EXIT_UPDATE:
8644 gen_update_nip(ctx, nip);
8645 /* fall through */
8646 case DISAS_EXIT:
46d396bd 8647 pmu_count_insns(ctx);
07ea28b4 8648 tcg_gen_exit_tb(NULL, 0);
a9b5b3d0
RH		 8649 break;
8650
8651 default:
8652 g_assert_not_reached();
9a64fbe4 8653 }
b0c2d521
EC		 8654}
8655
8656static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs)
8657{
8658 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
8659 log_target_disas(cs, dcbase->pc_first, dcbase->tb->size);
8660}
0a7df5da 8661
b0c2d521
EC		 8662static const TranslatorOps ppc_tr_ops = {
8663 .init_disas_context = ppc_tr_init_disas_context,
8664 .tb_start = ppc_tr_tb_start,
8665 .insn_start = ppc_tr_insn_start,
b0c2d521
EC		 8666 .translate_insn = ppc_tr_translate_insn,
8667 .tb_stop = ppc_tr_tb_stop,
8668 .disas_log = ppc_tr_disas_log,
8669};
4e5e1215 8670
8b86d6d2 8671void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
b0c2d521
EC		 8672{
8673 DisasContext ctx;
8674
8b86d6d2 8675 translator_loop(&ppc_tr_ops, &ctx.base, cs, tb, max_insns);
79aceca5
FB		 8676}
8677
bad729e2
RH		 8678void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
8679 target_ulong *data)
d2856f1a 8680{
bad729e2 8681 env->nip = data[0];
d2856f1a 8682}
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