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dc5bd18f MC |
1 | /* |
2 | * QEMU RISC-V CPU | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
0442428a | 21 | #include "qemu/qemu-print.h" |
856dfd8a | 22 | #include "qemu/ctype.h" |
dc5bd18f MC |
23 | #include "qemu/log.h" |
24 | #include "cpu.h" | |
95bd8daa | 25 | #include "cpu_vendorid.h" |
14664483 | 26 | #include "pmu.h" |
f7697f0e | 27 | #include "internals.h" |
43888c2f | 28 | #include "time_helper.h" |
dc5bd18f MC |
29 | #include "exec/exec-all.h" |
30 | #include "qapi/error.h" | |
6f23aaeb | 31 | #include "qapi/visitor.h" |
b55d7d34 | 32 | #include "qemu/error-report.h" |
c4e95030 | 33 | #include "hw/qdev-properties.h" |
dc5bd18f | 34 | #include "migration/vmstate.h" |
135b03cb | 35 | #include "fpu/softfloat-helpers.h" |
ad40be27 YJ |
36 | #include "sysemu/kvm.h" |
37 | #include "kvm_riscv.h" | |
0489d5bd | 38 | #include "tcg/tcg.h" |
dc5bd18f MC |
39 | |
40 | /* RISC-V CPU definitions */ | |
41 | ||
9951ba94 FC |
42 | #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ |
43 | (QEMU_VERSION_MINOR << 8) | \ | |
44 | (QEMU_VERSION_MICRO)) | |
075eeda9 | 45 | #define RISCV_CPU_MIMPID RISCV_CPU_MARCHID |
9951ba94 | 46 | |
0e2c3770 | 47 | static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; |
dc5bd18f | 48 | |
a775398b AP |
49 | struct isa_ext_data { |
50 | const char *name; | |
9a1f054d AP |
51 | bool multi_letter; |
52 | int min_version; | |
53 | int ext_enable_offset; | |
a775398b AP |
54 | }; |
55 | ||
9a1f054d AP |
56 | #define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \ |
57 | {#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} | |
58 | ||
59 | /** | |
60 | * Here are the ordering rules of extension naming defined by RISC-V | |
61 | * specification : | |
62 | * 1. All extensions should be separated from other multi-letter extensions | |
63 | * by an underscore. | |
64 | * 2. The first letter following the 'Z' conventionally indicates the most | |
65 | * closely related alphabetical extension category, IMAFDQLCBKJTPVH. | |
66 | * If multiple 'Z' extensions are named, they should be ordered first | |
67 | * by category, then alphabetically within a category. | |
68 | * 3. Standard supervisor-level extensions (starts with 'S') should be | |
69 | * listed after standard unprivileged extensions. If multiple | |
70 | * supervisor-level extensions are listed, they should be ordered | |
71 | * alphabetically. | |
72 | * 4. Non-standard extensions (starts with 'X') must be listed after all | |
73 | * standard extensions. They must be separated from other multi-letter | |
74 | * extensions by an underscore. | |
75 | */ | |
76 | static const struct isa_ext_data isa_edata_arr[] = { | |
77 | ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h), | |
0e660142 | 78 | ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_10_0, ext_v), |
e05da09b | 79 | ISA_EXT_DATA_ENTRY(zicbom, true, PRIV_VERSION_1_12_0, ext_icbom), |
a939c500 | 80 | ISA_EXT_DATA_ENTRY(zicboz, true, PRIV_VERSION_1_12_0, ext_icboz), |
b8e1f32c | 81 | ISA_EXT_DATA_ENTRY(zicond, true, PRIV_VERSION_1_12_0, ext_zicond), |
9a1f054d AP |
82 | ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr), |
83 | ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei), | |
4696f0ab | 84 | ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause), |
260b594d | 85 | ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs), |
7ad2878c | 86 | ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_11_0, ext_zfh), |
662ed9cc | 87 | ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_11_0, ext_zfhmin), |
9a1f054d AP |
88 | ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx), |
89 | ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx), | |
d364c0ab WL |
90 | ISA_EXT_DATA_ENTRY(zca, true, PRIV_VERSION_1_12_0, ext_zca), |
91 | ISA_EXT_DATA_ENTRY(zcb, true, PRIV_VERSION_1_12_0, ext_zcb), | |
92 | ISA_EXT_DATA_ENTRY(zcf, true, PRIV_VERSION_1_12_0, ext_zcf), | |
93 | ISA_EXT_DATA_ENTRY(zcd, true, PRIV_VERSION_1_12_0, ext_zcd), | |
94 | ISA_EXT_DATA_ENTRY(zcmp, true, PRIV_VERSION_1_12_0, ext_zcmp), | |
95 | ISA_EXT_DATA_ENTRY(zcmt, true, PRIV_VERSION_1_12_0, ext_zcmt), | |
9a1f054d AP |
96 | ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba), |
97 | ISA_EXT_DATA_ENTRY(zbb, true, PRIV_VERSION_1_12_0, ext_zbb), | |
98 | ISA_EXT_DATA_ENTRY(zbc, true, PRIV_VERSION_1_12_0, ext_zbc), | |
99 | ISA_EXT_DATA_ENTRY(zbkb, true, PRIV_VERSION_1_12_0, ext_zbkb), | |
100 | ISA_EXT_DATA_ENTRY(zbkc, true, PRIV_VERSION_1_12_0, ext_zbkc), | |
101 | ISA_EXT_DATA_ENTRY(zbkx, true, PRIV_VERSION_1_12_0, ext_zbkx), | |
102 | ISA_EXT_DATA_ENTRY(zbs, true, PRIV_VERSION_1_12_0, ext_zbs), | |
103 | ISA_EXT_DATA_ENTRY(zk, true, PRIV_VERSION_1_12_0, ext_zk), | |
104 | ISA_EXT_DATA_ENTRY(zkn, true, PRIV_VERSION_1_12_0, ext_zkn), | |
105 | ISA_EXT_DATA_ENTRY(zknd, true, PRIV_VERSION_1_12_0, ext_zknd), | |
106 | ISA_EXT_DATA_ENTRY(zkne, true, PRIV_VERSION_1_12_0, ext_zkne), | |
107 | ISA_EXT_DATA_ENTRY(zknh, true, PRIV_VERSION_1_12_0, ext_zknh), | |
108 | ISA_EXT_DATA_ENTRY(zkr, true, PRIV_VERSION_1_12_0, ext_zkr), | |
109 | ISA_EXT_DATA_ENTRY(zks, true, PRIV_VERSION_1_12_0, ext_zks), | |
110 | ISA_EXT_DATA_ENTRY(zksed, true, PRIV_VERSION_1_12_0, ext_zksed), | |
111 | ISA_EXT_DATA_ENTRY(zksh, true, PRIV_VERSION_1_12_0, ext_zksh), | |
112 | ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt), | |
662ed9cc LZ |
113 | ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_10_0, ext_zve32f), |
114 | ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_10_0, ext_zve64f), | |
115 | ISA_EXT_DATA_ENTRY(zve64d, true, PRIV_VERSION_1_10_0, ext_zve64d), | |
058d9d30 WL |
116 | ISA_EXT_DATA_ENTRY(zvfh, true, PRIV_VERSION_1_12_0, ext_zvfh), |
117 | ISA_EXT_DATA_ENTRY(zvfhmin, true, PRIV_VERSION_1_12_0, ext_zvfhmin), | |
9a1f054d AP |
118 | ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), |
119 | ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), | |
dc9acc9c AP |
120 | ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia), |
121 | ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia), | |
14664483 | 122 | ISA_EXT_DATA_ENTRY(sscofpmf, true, PRIV_VERSION_1_12_0, ext_sscofpmf), |
43888c2f | 123 | ISA_EXT_DATA_ENTRY(sstc, true, PRIV_VERSION_1_12_0, ext_sstc), |
62108f05 | 124 | ISA_EXT_DATA_ENTRY(svadu, true, PRIV_VERSION_1_12_0, ext_svadu), |
9a1f054d AP |
125 | ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), |
126 | ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), | |
127 | ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), | |
c9410a68 | 128 | ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba), |
426c0491 | 129 | ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb), |
fa134585 | 130 | ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs), |
49a7f3aa | 131 | ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), |
32909338 | 132 | ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov), |
d4d90115 | 133 | ISA_EXT_DATA_ENTRY(xtheadfmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadfmemidx), |
578086ba | 134 | ISA_EXT_DATA_ENTRY(xtheadfmv, true, PRIV_VERSION_1_11_0, ext_xtheadfmv), |
b8a5832b | 135 | ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac), |
45f9df86 | 136 | ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadmemidx), |
af99aa72 | 137 | ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xtheadmempair), |
134c3ffa | 138 | ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync), |
e0dea2f5 | 139 | ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), |
9a1f054d AP |
140 | }; |
141 | ||
142 | static bool isa_ext_is_enabled(RISCVCPU *cpu, | |
143 | const struct isa_ext_data *edata) | |
144 | { | |
145 | bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; | |
146 | ||
147 | return *ext_enabled; | |
148 | } | |
149 | ||
150 | static void isa_ext_update_enabled(RISCVCPU *cpu, | |
151 | const struct isa_ext_data *edata, bool en) | |
152 | { | |
153 | bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; | |
154 | ||
155 | *ext_enabled = en; | |
156 | } | |
157 | ||
dc5bd18f | 158 | const char * const riscv_int_regnames[] = { |
a9f37afa AP |
159 | "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", |
160 | "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", | |
161 | "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", | |
162 | "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", | |
163 | "x28/t3", "x29/t4", "x30/t5", "x31/t6" | |
dc5bd18f MC |
164 | }; |
165 | ||
2b547084 FP |
166 | const char * const riscv_int_regnamesh[] = { |
167 | "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", | |
168 | "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", | |
169 | "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", | |
170 | "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", | |
171 | "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", | |
172 | "x30h/t5h", "x31h/t6h" | |
173 | }; | |
174 | ||
dc5bd18f | 175 | const char * const riscv_fpr_regnames[] = { |
a9f37afa AP |
176 | "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", |
177 | "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", | |
178 | "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", | |
179 | "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", | |
180 | "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", | |
181 | "f30/ft10", "f31/ft11" | |
dc5bd18f MC |
182 | }; |
183 | ||
9a575d33 | 184 | static const char * const riscv_excp_names[] = { |
dc5bd18f MC |
185 | "misaligned_fetch", |
186 | "fault_fetch", | |
187 | "illegal_instruction", | |
188 | "breakpoint", | |
189 | "misaligned_load", | |
190 | "fault_load", | |
191 | "misaligned_store", | |
192 | "fault_store", | |
193 | "user_ecall", | |
194 | "supervisor_ecall", | |
195 | "hypervisor_ecall", | |
196 | "machine_ecall", | |
197 | "exec_page_fault", | |
198 | "load_page_fault", | |
199 | "reserved", | |
fd990e86 | 200 | "store_page_fault", |
ab67a1d0 AF |
201 | "reserved", |
202 | "reserved", | |
203 | "reserved", | |
204 | "reserved", | |
205 | "guest_exec_page_fault", | |
206 | "guest_load_page_fault", | |
207 | "reserved", | |
fd990e86 | 208 | "guest_store_page_fault", |
dc5bd18f MC |
209 | }; |
210 | ||
9a575d33 | 211 | static const char * const riscv_intr_names[] = { |
dc5bd18f MC |
212 | "u_software", |
213 | "s_software", | |
205377f8 | 214 | "vs_software", |
dc5bd18f MC |
215 | "m_software", |
216 | "u_timer", | |
217 | "s_timer", | |
205377f8 | 218 | "vs_timer", |
dc5bd18f MC |
219 | "m_timer", |
220 | "u_external", | |
6cfcf775 | 221 | "s_external", |
205377f8 | 222 | "vs_external", |
dc5bd18f | 223 | "m_external", |
426f0348 MC |
224 | "reserved", |
225 | "reserved", | |
226 | "reserved", | |
227 | "reserved" | |
dc5bd18f MC |
228 | }; |
229 | ||
c01756a7 | 230 | static void register_cpu_props(Object *obj); |
26b2bc58 | 231 | |
c51a3f5d YJ |
232 | const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) |
233 | { | |
234 | if (async) { | |
235 | return (cause < ARRAY_SIZE(riscv_intr_names)) ? | |
236 | riscv_intr_names[cause] : "(unknown)"; | |
237 | } else { | |
238 | return (cause < ARRAY_SIZE(riscv_excp_names)) ? | |
239 | riscv_excp_names[cause] : "(unknown)"; | |
240 | } | |
241 | } | |
242 | ||
e91a7227 | 243 | static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) |
dc5bd18f | 244 | { |
e91a7227 RH |
245 | env->misa_mxl_max = env->misa_mxl = mxl; |
246 | env->misa_ext_mask = env->misa_ext = ext; | |
dc5bd18f MC |
247 | } |
248 | ||
c9a73910 | 249 | static void set_priv_version(CPURISCVState *env, int priv_ver) |
dc5bd18f | 250 | { |
dc5bd18f MC |
251 | env->priv_ver = priv_ver; |
252 | } | |
253 | ||
32931383 LZ |
254 | static void set_vext_version(CPURISCVState *env, int vext_ver) |
255 | { | |
256 | env->vext_ver = vext_ver; | |
257 | } | |
258 | ||
6f23aaeb AG |
259 | #ifndef CONFIG_USER_ONLY |
260 | static uint8_t satp_mode_from_str(const char *satp_mode_str) | |
261 | { | |
262 | if (!strncmp(satp_mode_str, "mbare", 5)) { | |
263 | return VM_1_10_MBARE; | |
264 | } | |
265 | ||
266 | if (!strncmp(satp_mode_str, "sv32", 4)) { | |
267 | return VM_1_10_SV32; | |
268 | } | |
269 | ||
270 | if (!strncmp(satp_mode_str, "sv39", 4)) { | |
271 | return VM_1_10_SV39; | |
272 | } | |
273 | ||
274 | if (!strncmp(satp_mode_str, "sv48", 4)) { | |
275 | return VM_1_10_SV48; | |
276 | } | |
277 | ||
278 | if (!strncmp(satp_mode_str, "sv57", 4)) { | |
279 | return VM_1_10_SV57; | |
280 | } | |
281 | ||
282 | if (!strncmp(satp_mode_str, "sv64", 4)) { | |
283 | return VM_1_10_SV64; | |
284 | } | |
285 | ||
286 | g_assert_not_reached(); | |
287 | } | |
288 | ||
289 | uint8_t satp_mode_max_from_map(uint32_t map) | |
290 | { | |
291 | /* map here has at least one bit set, so no problem with clz */ | |
292 | return 31 - __builtin_clz(map); | |
293 | } | |
294 | ||
295 | const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) | |
296 | { | |
297 | if (is_32_bit) { | |
298 | switch (satp_mode) { | |
299 | case VM_1_10_SV32: | |
300 | return "sv32"; | |
301 | case VM_1_10_MBARE: | |
302 | return "none"; | |
303 | } | |
304 | } else { | |
305 | switch (satp_mode) { | |
306 | case VM_1_10_SV64: | |
307 | return "sv64"; | |
308 | case VM_1_10_SV57: | |
309 | return "sv57"; | |
310 | case VM_1_10_SV48: | |
311 | return "sv48"; | |
312 | case VM_1_10_SV39: | |
313 | return "sv39"; | |
314 | case VM_1_10_MBARE: | |
315 | return "none"; | |
316 | } | |
317 | } | |
318 | ||
319 | g_assert_not_reached(); | |
320 | } | |
321 | ||
6df3747a AG |
322 | static void set_satp_mode_max_supported(RISCVCPU *cpu, |
323 | uint8_t satp_mode) | |
6f23aaeb AG |
324 | { |
325 | bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; | |
6df3747a | 326 | const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; |
6f23aaeb | 327 | |
6df3747a AG |
328 | for (int i = 0; i <= satp_mode; ++i) { |
329 | if (valid_vm[i]) { | |
330 | cpu->cfg.satp_mode.supported |= (1 << i); | |
331 | } | |
6f23aaeb AG |
332 | } |
333 | } | |
6df3747a AG |
334 | |
335 | /* Set the satp mode to the max supported */ | |
336 | static void set_satp_mode_default_map(RISCVCPU *cpu) | |
337 | { | |
338 | cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported; | |
339 | } | |
6f23aaeb AG |
340 | #endif |
341 | ||
dc5bd18f MC |
342 | static void riscv_any_cpu_init(Object *obj) |
343 | { | |
344 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
3820602f | 345 | #if defined(TARGET_RISCV32) |
e91a7227 | 346 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); |
3820602f | 347 | #elif defined(TARGET_RISCV64) |
e91a7227 | 348 | set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); |
3820602f | 349 | #endif |
6df3747a AG |
350 | |
351 | #ifndef CONFIG_USER_ONLY | |
352 | set_satp_mode_max_supported(RISCV_CPU(obj), | |
353 | riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ? | |
354 | VM_1_10_SV32 : VM_1_10_SV57); | |
355 | #endif | |
356 | ||
7100fe6c | 357 | set_priv_version(env, PRIV_VERSION_1_12_0); |
c01756a7 | 358 | register_cpu_props(obj); |
dc5bd18f MC |
359 | } |
360 | ||
094b072c AF |
361 | #if defined(TARGET_RISCV64) |
362 | static void rv64_base_cpu_init(Object *obj) | |
8903bf6e AF |
363 | { |
364 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
b55d7d34 | 365 | /* We set this in the realise function */ |
e91a7227 | 366 | set_misa(env, MXL_RV64, 0); |
c01756a7 | 367 | register_cpu_props(obj); |
18800095 AP |
368 | /* Set latest version of privileged specification */ |
369 | set_priv_version(env, PRIV_VERSION_1_12_0); | |
6df3747a AG |
370 | #ifndef CONFIG_USER_ONLY |
371 | set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); | |
372 | #endif | |
8903bf6e AF |
373 | } |
374 | ||
114baaca | 375 | static void rv64_sifive_u_cpu_init(Object *obj) |
dc5bd18f MC |
376 | { |
377 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
e91a7227 | 378 | set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); |
c01756a7 | 379 | register_cpu_props(obj); |
c9a73910 | 380 | set_priv_version(env, PRIV_VERSION_1_10_0); |
6df3747a AG |
381 | #ifndef CONFIG_USER_ONLY |
382 | set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); | |
383 | #endif | |
dc5bd18f MC |
384 | } |
385 | ||
114baaca | 386 | static void rv64_sifive_e_cpu_init(Object *obj) |
36b80ad9 AF |
387 | { |
388 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
26b2bc58 AF |
389 | RISCVCPU *cpu = RISCV_CPU(obj); |
390 | ||
e91a7227 | 391 | set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); |
c01756a7 | 392 | register_cpu_props(obj); |
36b80ad9 | 393 | set_priv_version(env, PRIV_VERSION_1_10_0); |
26b2bc58 | 394 | cpu->cfg.mmu = false; |
6df3747a AG |
395 | #ifndef CONFIG_USER_ONLY |
396 | set_satp_mode_max_supported(cpu, VM_1_10_MBARE); | |
397 | #endif | |
36b80ad9 | 398 | } |
332dab68 | 399 | |
95bd8daa CM |
400 | static void rv64_thead_c906_cpu_init(Object *obj) |
401 | { | |
402 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
403 | RISCVCPU *cpu = RISCV_CPU(obj); | |
404 | ||
405 | set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); | |
406 | set_priv_version(env, PRIV_VERSION_1_11_0); | |
407 | ||
408 | cpu->cfg.ext_g = true; | |
409 | cpu->cfg.ext_c = true; | |
410 | cpu->cfg.ext_u = true; | |
411 | cpu->cfg.ext_s = true; | |
412 | cpu->cfg.ext_icsr = true; | |
413 | cpu->cfg.ext_zfh = true; | |
414 | cpu->cfg.mmu = true; | |
415 | cpu->cfg.ext_xtheadba = true; | |
416 | cpu->cfg.ext_xtheadbb = true; | |
417 | cpu->cfg.ext_xtheadbs = true; | |
418 | cpu->cfg.ext_xtheadcmo = true; | |
419 | cpu->cfg.ext_xtheadcondmov = true; | |
420 | cpu->cfg.ext_xtheadfmemidx = true; | |
421 | cpu->cfg.ext_xtheadmac = true; | |
422 | cpu->cfg.ext_xtheadmemidx = true; | |
423 | cpu->cfg.ext_xtheadmempair = true; | |
424 | cpu->cfg.ext_xtheadsync = true; | |
425 | ||
426 | cpu->cfg.mvendorid = THEAD_VENDOR_ID; | |
6df3747a AG |
427 | #ifndef CONFIG_USER_ONLY |
428 | set_satp_mode_max_supported(cpu, VM_1_10_SV39); | |
429 | #endif | |
95bd8daa CM |
430 | } |
431 | ||
332dab68 FP |
432 | static void rv128_base_cpu_init(Object *obj) |
433 | { | |
434 | if (qemu_tcg_mttcg_enabled()) { | |
435 | /* Missing 128-bit aligned atomics */ | |
436 | error_report("128-bit RISC-V currently does not work with Multi " | |
437 | "Threaded TCG. Please use: -accel tcg,thread=single"); | |
438 | exit(EXIT_FAILURE); | |
439 | } | |
440 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
441 | /* We set this in the realise function */ | |
442 | set_misa(env, MXL_RV128, 0); | |
c01756a7 | 443 | register_cpu_props(obj); |
18800095 AP |
444 | /* Set latest version of privileged specification */ |
445 | set_priv_version(env, PRIV_VERSION_1_12_0); | |
6df3747a AG |
446 | #ifndef CONFIG_USER_ONLY |
447 | set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); | |
448 | #endif | |
332dab68 | 449 | } |
114baaca | 450 | #else |
094b072c AF |
451 | static void rv32_base_cpu_init(Object *obj) |
452 | { | |
453 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
454 | /* We set this in the realise function */ | |
e91a7227 | 455 | set_misa(env, MXL_RV32, 0); |
c01756a7 | 456 | register_cpu_props(obj); |
18800095 AP |
457 | /* Set latest version of privileged specification */ |
458 | set_priv_version(env, PRIV_VERSION_1_12_0); | |
6df3747a AG |
459 | #ifndef CONFIG_USER_ONLY |
460 | set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); | |
461 | #endif | |
094b072c AF |
462 | } |
463 | ||
114baaca AF |
464 | static void rv32_sifive_u_cpu_init(Object *obj) |
465 | { | |
466 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
e91a7227 | 467 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); |
c01756a7 | 468 | register_cpu_props(obj); |
114baaca | 469 | set_priv_version(env, PRIV_VERSION_1_10_0); |
6df3747a AG |
470 | #ifndef CONFIG_USER_ONLY |
471 | set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); | |
472 | #endif | |
114baaca | 473 | } |
36b80ad9 | 474 | |
114baaca AF |
475 | static void rv32_sifive_e_cpu_init(Object *obj) |
476 | { | |
477 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
26b2bc58 AF |
478 | RISCVCPU *cpu = RISCV_CPU(obj); |
479 | ||
e91a7227 | 480 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); |
c01756a7 | 481 | register_cpu_props(obj); |
114baaca | 482 | set_priv_version(env, PRIV_VERSION_1_10_0); |
26b2bc58 | 483 | cpu->cfg.mmu = false; |
6df3747a AG |
484 | #ifndef CONFIG_USER_ONLY |
485 | set_satp_mode_max_supported(cpu, VM_1_10_MBARE); | |
486 | #endif | |
114baaca | 487 | } |
d8e72bd1 | 488 | |
e8905c6c | 489 | static void rv32_ibex_cpu_init(Object *obj) |
dc5bd18f MC |
490 | { |
491 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
26b2bc58 AF |
492 | RISCVCPU *cpu = RISCV_CPU(obj); |
493 | ||
e91a7227 | 494 | set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); |
c01756a7 | 495 | register_cpu_props(obj); |
be2265c7 | 496 | set_priv_version(env, PRIV_VERSION_1_11_0); |
26b2bc58 | 497 | cpu->cfg.mmu = false; |
6df3747a AG |
498 | #ifndef CONFIG_USER_ONLY |
499 | set_satp_mode_max_supported(cpu, VM_1_10_MBARE); | |
500 | #endif | |
26b2bc58 | 501 | cpu->cfg.epmp = true; |
dc5bd18f MC |
502 | } |
503 | ||
2fdd2c09 | 504 | static void rv32_imafcu_nommu_cpu_init(Object *obj) |
d784733b CW |
505 | { |
506 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
26b2bc58 AF |
507 | RISCVCPU *cpu = RISCV_CPU(obj); |
508 | ||
e91a7227 | 509 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); |
c01756a7 | 510 | register_cpu_props(obj); |
d784733b | 511 | set_priv_version(env, PRIV_VERSION_1_10_0); |
26b2bc58 | 512 | cpu->cfg.mmu = false; |
6df3747a AG |
513 | #ifndef CONFIG_USER_ONLY |
514 | set_satp_mode_max_supported(cpu, VM_1_10_MBARE); | |
515 | #endif | |
d784733b | 516 | } |
eab15862 | 517 | #endif |
dc5bd18f | 518 | |
10f1ca27 YJ |
519 | #if defined(CONFIG_KVM) |
520 | static void riscv_host_cpu_init(Object *obj) | |
521 | { | |
522 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
523 | #if defined(TARGET_RISCV32) | |
524 | set_misa(env, MXL_RV32, 0); | |
525 | #elif defined(TARGET_RISCV64) | |
526 | set_misa(env, MXL_RV64, 0); | |
527 | #endif | |
c01756a7 | 528 | register_cpu_props(obj); |
10f1ca27 YJ |
529 | } |
530 | #endif | |
531 | ||
dc5bd18f MC |
532 | static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) |
533 | { | |
534 | ObjectClass *oc; | |
535 | char *typename; | |
536 | char **cpuname; | |
537 | ||
538 | cpuname = g_strsplit(cpu_model, ",", 1); | |
539 | typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); | |
540 | oc = object_class_by_name(typename); | |
541 | g_strfreev(cpuname); | |
542 | g_free(typename); | |
543 | if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || | |
544 | object_class_is_abstract(oc)) { | |
545 | return NULL; | |
546 | } | |
547 | return oc; | |
548 | } | |
549 | ||
90c84c56 | 550 | static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) |
dc5bd18f MC |
551 | { |
552 | RISCVCPU *cpu = RISCV_CPU(cs); | |
553 | CPURISCVState *env = &cpu->env; | |
554 | int i; | |
555 | ||
df30e652 AF |
556 | #if !defined(CONFIG_USER_ONLY) |
557 | if (riscv_has_ext(env, RVH)) { | |
558 | qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); | |
559 | } | |
560 | #endif | |
90c84c56 | 561 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); |
dc5bd18f | 562 | #ifndef CONFIG_USER_ONLY |
665b90d8 RH |
563 | { |
564 | static const int dump_csrs[] = { | |
565 | CSR_MHARTID, | |
566 | CSR_MSTATUS, | |
567 | CSR_MSTATUSH, | |
bc7dca13 BM |
568 | /* |
569 | * CSR_SSTATUS is intentionally omitted here as its value | |
570 | * can be figured out by looking at CSR_MSTATUS | |
571 | */ | |
665b90d8 RH |
572 | CSR_HSTATUS, |
573 | CSR_VSSTATUS, | |
574 | CSR_MIP, | |
575 | CSR_MIE, | |
576 | CSR_MIDELEG, | |
577 | CSR_HIDELEG, | |
578 | CSR_MEDELEG, | |
579 | CSR_HEDELEG, | |
580 | CSR_MTVEC, | |
581 | CSR_STVEC, | |
582 | CSR_VSTVEC, | |
583 | CSR_MEPC, | |
584 | CSR_SEPC, | |
585 | CSR_VSEPC, | |
586 | CSR_MCAUSE, | |
587 | CSR_SCAUSE, | |
588 | CSR_VSCAUSE, | |
589 | CSR_MTVAL, | |
590 | CSR_STVAL, | |
591 | CSR_HTVAL, | |
592 | CSR_MTVAL2, | |
593 | CSR_MSCRATCH, | |
594 | CSR_SSCRATCH, | |
595 | CSR_SATP, | |
bd5594ca AB |
596 | CSR_MMTE, |
597 | CSR_UPMBASE, | |
598 | CSR_UPMMASK, | |
599 | CSR_SPMBASE, | |
600 | CSR_SPMMASK, | |
601 | CSR_MPMBASE, | |
602 | CSR_MPMMASK, | |
665b90d8 RH |
603 | }; |
604 | ||
605 | for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { | |
606 | int csrno = dump_csrs[i]; | |
607 | target_ulong val = 0; | |
608 | RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); | |
609 | ||
610 | /* | |
611 | * Rely on the smode, hmode, etc, predicates within csr.c | |
612 | * to do the filtering of the registers that are present. | |
613 | */ | |
614 | if (res == RISCV_EXCP_NONE) { | |
615 | qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", | |
616 | csr_ops[csrno].name, val); | |
617 | } | |
618 | } | |
df30e652 | 619 | } |
dc5bd18f MC |
620 | #endif |
621 | ||
622 | for (i = 0; i < 32; i++) { | |
e573a7f3 | 623 | qemu_fprintf(f, " %-8s " TARGET_FMT_lx, |
90c84c56 | 624 | riscv_int_regnames[i], env->gpr[i]); |
dc5bd18f | 625 | if ((i & 3) == 3) { |
90c84c56 | 626 | qemu_fprintf(f, "\n"); |
dc5bd18f MC |
627 | } |
628 | } | |
86ea1880 RH |
629 | if (flags & CPU_DUMP_FPU) { |
630 | for (i = 0; i < 32; i++) { | |
e573a7f3 | 631 | qemu_fprintf(f, " %-8s %016" PRIx64, |
90c84c56 | 632 | riscv_fpr_regnames[i], env->fpr[i]); |
86ea1880 | 633 | if ((i & 3) == 3) { |
90c84c56 | 634 | qemu_fprintf(f, "\n"); |
86ea1880 | 635 | } |
dc5bd18f MC |
636 | } |
637 | } | |
638 | } | |
639 | ||
640 | static void riscv_cpu_set_pc(CPUState *cs, vaddr value) | |
641 | { | |
642 | RISCVCPU *cpu = RISCV_CPU(cs); | |
643 | CPURISCVState *env = &cpu->env; | |
bf9e776e LZ |
644 | |
645 | if (env->xl == MXL_RV32) { | |
646 | env->pc = (int32_t)value; | |
647 | } else { | |
648 | env->pc = value; | |
649 | } | |
dc5bd18f MC |
650 | } |
651 | ||
e4fdf9df RH |
652 | static vaddr riscv_cpu_get_pc(CPUState *cs) |
653 | { | |
654 | RISCVCPU *cpu = RISCV_CPU(cs); | |
655 | CPURISCVState *env = &cpu->env; | |
656 | ||
657 | /* Match cpu_get_tb_cpu_state. */ | |
658 | if (env->xl == MXL_RV32) { | |
659 | return env->pc & UINT32_MAX; | |
660 | } | |
661 | return env->pc; | |
662 | } | |
663 | ||
04a37d4c RH |
664 | static void riscv_cpu_synchronize_from_tb(CPUState *cs, |
665 | const TranslationBlock *tb) | |
dc5bd18f MC |
666 | { |
667 | RISCVCPU *cpu = RISCV_CPU(cs); | |
668 | CPURISCVState *env = &cpu->env; | |
bf9e776e LZ |
669 | RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); |
670 | ||
0489d5bd AJ |
671 | tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); |
672 | ||
bf9e776e | 673 | if (xl == MXL_RV32) { |
0489d5bd | 674 | env->pc = (int32_t) tb->pc; |
bf9e776e | 675 | } else { |
0489d5bd | 676 | env->pc = tb->pc; |
bf9e776e | 677 | } |
dc5bd18f MC |
678 | } |
679 | ||
680 | static bool riscv_cpu_has_work(CPUState *cs) | |
681 | { | |
682 | #ifndef CONFIG_USER_ONLY | |
683 | RISCVCPU *cpu = RISCV_CPU(cs); | |
684 | CPURISCVState *env = &cpu->env; | |
685 | /* | |
686 | * Definition of the WFI instruction requires it to ignore the privilege | |
687 | * mode and delegation registers, but respect individual enables | |
688 | */ | |
8f42415f | 689 | return riscv_cpu_all_pending(env) != 0; |
dc5bd18f MC |
690 | #else |
691 | return true; | |
692 | #endif | |
693 | } | |
694 | ||
ad1e84f5 RH |
695 | static void riscv_restore_state_to_opc(CPUState *cs, |
696 | const TranslationBlock *tb, | |
697 | const uint64_t *data) | |
dc5bd18f | 698 | { |
ad1e84f5 RH |
699 | RISCVCPU *cpu = RISCV_CPU(cs); |
700 | CPURISCVState *env = &cpu->env; | |
bf9e776e | 701 | RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); |
ad1e84f5 | 702 | |
bf9e776e LZ |
703 | if (xl == MXL_RV32) { |
704 | env->pc = (int32_t)data[0]; | |
705 | } else { | |
706 | env->pc = data[0]; | |
707 | } | |
62cf0245 | 708 | env->bins = data[1]; |
dc5bd18f MC |
709 | } |
710 | ||
4fa485a7 | 711 | static void riscv_cpu_reset_hold(Object *obj) |
dc5bd18f | 712 | { |
43dc93af AP |
713 | #ifndef CONFIG_USER_ONLY |
714 | uint8_t iprio; | |
715 | int i, irq, rdzero; | |
716 | #endif | |
4fa485a7 | 717 | CPUState *cs = CPU(obj); |
dc5bd18f MC |
718 | RISCVCPU *cpu = RISCV_CPU(cs); |
719 | RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); | |
720 | CPURISCVState *env = &cpu->env; | |
721 | ||
4fa485a7 PM |
722 | if (mcc->parent_phases.hold) { |
723 | mcc->parent_phases.hold(obj); | |
724 | } | |
dc5bd18f | 725 | #ifndef CONFIG_USER_ONLY |
e91a7227 | 726 | env->misa_mxl = env->misa_mxl_max; |
dc5bd18f MC |
727 | env->priv = PRV_M; |
728 | env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); | |
92371bd9 RH |
729 | if (env->misa_mxl > MXL_RV32) { |
730 | /* | |
731 | * The reset status of SXL/UXL is undefined, but mstatus is WARL | |
732 | * and we must ensure that the value after init is valid for read. | |
733 | */ | |
734 | env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); | |
735 | env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); | |
5a2ae235 LZ |
736 | if (riscv_has_ext(env, RVH)) { |
737 | env->vsstatus = set_field(env->vsstatus, | |
738 | MSTATUS64_SXL, env->misa_mxl); | |
739 | env->vsstatus = set_field(env->vsstatus, | |
740 | MSTATUS64_UXL, env->misa_mxl); | |
741 | env->mstatus_hs = set_field(env->mstatus_hs, | |
742 | MSTATUS64_SXL, env->misa_mxl); | |
743 | env->mstatus_hs = set_field(env->mstatus_hs, | |
744 | MSTATUS64_UXL, env->misa_mxl); | |
745 | } | |
92371bd9 | 746 | } |
dc5bd18f | 747 | env->mcause = 0; |
881df35d | 748 | env->miclaim = MIP_SGEIP; |
dc5bd18f | 749 | env->pc = env->resetvec; |
62cf0245 | 750 | env->bins = 0; |
ec352d0c | 751 | env->two_stage_lookup = false; |
43dc93af | 752 | |
0af3f115 WL |
753 | env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) | |
754 | (cpu->cfg.ext_svadu ? MENVCFG_HADE : 0); | |
755 | env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) | | |
756 | (cpu->cfg.ext_svadu ? HENVCFG_HADE : 0); | |
7a6613da | 757 | |
43dc93af AP |
758 | /* Initialized default priorities of local interrupts. */ |
759 | for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { | |
760 | iprio = riscv_cpu_default_priority(i); | |
761 | env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio; | |
762 | env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio; | |
763 | env->hviprio[i] = 0; | |
764 | } | |
765 | i = 0; | |
766 | while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) { | |
767 | if (!rdzero) { | |
768 | env->hviprio[irq] = env->miprio[irq]; | |
769 | } | |
770 | i++; | |
771 | } | |
4bbe8033 AB |
772 | /* mmte is supposed to have pm.current hardwired to 1 */ |
773 | env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); | |
dc5bd18f | 774 | #endif |
440544e1 | 775 | env->xl = riscv_cpu_mxl(env); |
40bfa5f6 | 776 | riscv_cpu_update_mask(env); |
330d2ae3 | 777 | cs->exception_index = RISCV_EXCP_NONE; |
c13b169f | 778 | env->load_res = -1; |
dc5bd18f | 779 | set_default_nan_mode(1, &env->fp_status); |
ad40be27 YJ |
780 | |
781 | #ifndef CONFIG_USER_ONLY | |
cdfb2905 | 782 | if (cpu->cfg.debug) { |
b6092544 BM |
783 | riscv_trigger_init(env); |
784 | } | |
785 | ||
ad40be27 YJ |
786 | if (kvm_enabled()) { |
787 | kvm_riscv_reset_vcpu(cpu); | |
788 | } | |
789 | #endif | |
dc5bd18f MC |
790 | } |
791 | ||
792 | static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) | |
793 | { | |
5c5a47f1 | 794 | RISCVCPU *cpu = RISCV_CPU(s); |
db23e5d9 RH |
795 | |
796 | switch (riscv_cpu_mxl(&cpu->env)) { | |
797 | case MXL_RV32: | |
5c5a47f1 | 798 | info->print_insn = print_insn_riscv32; |
db23e5d9 RH |
799 | break; |
800 | case MXL_RV64: | |
5c5a47f1 | 801 | info->print_insn = print_insn_riscv64; |
db23e5d9 | 802 | break; |
332dab68 FP |
803 | case MXL_RV128: |
804 | info->print_insn = print_insn_riscv128; | |
805 | break; | |
db23e5d9 RH |
806 | default: |
807 | g_assert_not_reached(); | |
5c5a47f1 | 808 | } |
dc5bd18f MC |
809 | } |
810 | ||
5ab10952 DHB |
811 | /* |
812 | * Check consistency between chosen extensions while setting | |
813 | * cpu->cfg accordingly, doing a set_misa() in the end. | |
814 | */ | |
815 | static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) | |
816 | { | |
817 | CPURISCVState *env = &cpu->env; | |
818 | uint32_t ext = 0; | |
819 | ||
820 | /* Do some ISA extension error checking */ | |
821 | if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && | |
822 | cpu->cfg.ext_a && cpu->cfg.ext_f && | |
823 | cpu->cfg.ext_d && | |
824 | cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { | |
825 | warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); | |
826 | cpu->cfg.ext_i = true; | |
827 | cpu->cfg.ext_m = true; | |
828 | cpu->cfg.ext_a = true; | |
829 | cpu->cfg.ext_f = true; | |
830 | cpu->cfg.ext_d = true; | |
831 | cpu->cfg.ext_icsr = true; | |
832 | cpu->cfg.ext_ifencei = true; | |
833 | } | |
834 | ||
835 | if (cpu->cfg.ext_i && cpu->cfg.ext_e) { | |
836 | error_setg(errp, | |
837 | "I and E extensions are incompatible"); | |
838 | return; | |
839 | } | |
840 | ||
841 | if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { | |
842 | error_setg(errp, | |
843 | "Either I or E extension must be set"); | |
844 | return; | |
845 | } | |
846 | ||
847 | if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { | |
848 | error_setg(errp, | |
849 | "Setting S extension without U extension is illegal"); | |
850 | return; | |
851 | } | |
852 | ||
853 | if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { | |
854 | error_setg(errp, | |
855 | "H depends on an I base integer ISA with 32 x registers"); | |
856 | return; | |
857 | } | |
858 | ||
859 | if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { | |
860 | error_setg(errp, "H extension implicitly requires S-mode"); | |
861 | return; | |
862 | } | |
863 | ||
864 | if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { | |
865 | error_setg(errp, "F extension requires Zicsr"); | |
866 | return; | |
867 | } | |
868 | ||
869 | if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { | |
870 | error_setg(errp, "Zawrs extension requires A extension"); | |
871 | return; | |
872 | } | |
873 | ||
1d2cb5a8 WL |
874 | if (cpu->cfg.ext_zfh) { |
875 | cpu->cfg.ext_zfhmin = true; | |
876 | } | |
877 | ||
878 | if (cpu->cfg.ext_zfhmin && !cpu->cfg.ext_f) { | |
5ab10952 DHB |
879 | error_setg(errp, "Zfh/Zfhmin extensions require F extension"); |
880 | return; | |
881 | } | |
882 | ||
883 | if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { | |
884 | error_setg(errp, "D extension requires F extension"); | |
885 | return; | |
886 | } | |
887 | ||
e7f0a803 WL |
888 | /* The V vector extension depends on the Zve64d extension */ |
889 | if (cpu->cfg.ext_v) { | |
890 | cpu->cfg.ext_zve64d = true; | |
891 | } | |
892 | ||
893 | /* The Zve64d extension depends on the Zve64f extension */ | |
894 | if (cpu->cfg.ext_zve64d) { | |
895 | cpu->cfg.ext_zve64f = true; | |
896 | } | |
897 | ||
898 | /* The Zve64f extension depends on the Zve32f extension */ | |
899 | if (cpu->cfg.ext_zve64f) { | |
900 | cpu->cfg.ext_zve32f = true; | |
901 | } | |
902 | ||
903 | if (cpu->cfg.ext_zve64d && !cpu->cfg.ext_d) { | |
904 | error_setg(errp, "Zve64d/V extensions require D extension"); | |
5ab10952 DHB |
905 | return; |
906 | } | |
907 | ||
e7f0a803 | 908 | if (cpu->cfg.ext_zve32f && !cpu->cfg.ext_f) { |
5ab10952 DHB |
909 | error_setg(errp, "Zve32f/Zve64f extensions require F extension"); |
910 | return; | |
911 | } | |
912 | ||
2e60f9ec WL |
913 | if (cpu->cfg.ext_zvfh) { |
914 | cpu->cfg.ext_zvfhmin = true; | |
915 | } | |
916 | ||
917 | if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { | |
918 | error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension"); | |
919 | return; | |
920 | } | |
921 | ||
922 | if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { | |
923 | error_setg(errp, "Zvfh extensions requires Zfhmin extension"); | |
924 | return; | |
925 | } | |
926 | ||
5ab10952 | 927 | /* Set the ISA extensions, checks should have happened above */ |
a0d805f0 WL |
928 | if (cpu->cfg.ext_zhinx) { |
929 | cpu->cfg.ext_zhinxmin = true; | |
930 | } | |
931 | ||
932 | if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) { | |
5ab10952 DHB |
933 | cpu->cfg.ext_zfinx = true; |
934 | } | |
935 | ||
936 | if (cpu->cfg.ext_zfinx) { | |
937 | if (!cpu->cfg.ext_icsr) { | |
938 | error_setg(errp, "Zfinx extension requires Zicsr"); | |
939 | return; | |
940 | } | |
941 | if (cpu->cfg.ext_f) { | |
942 | error_setg(errp, | |
51f33081 | 943 | "Zfinx cannot be supported together with F extension"); |
5ab10952 DHB |
944 | return; |
945 | } | |
946 | } | |
947 | ||
2288a5ce WL |
948 | if (cpu->cfg.ext_c) { |
949 | cpu->cfg.ext_zca = true; | |
950 | if (cpu->cfg.ext_f && env->misa_mxl_max == MXL_RV32) { | |
951 | cpu->cfg.ext_zcf = true; | |
952 | } | |
953 | if (cpu->cfg.ext_d) { | |
954 | cpu->cfg.ext_zcd = true; | |
955 | } | |
956 | } | |
957 | ||
958 | if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { | |
959 | error_setg(errp, "Zcf extension is only relevant to RV32"); | |
960 | return; | |
961 | } | |
962 | ||
963 | if (!cpu->cfg.ext_f && cpu->cfg.ext_zcf) { | |
964 | error_setg(errp, "Zcf extension requires F extension"); | |
965 | return; | |
966 | } | |
967 | ||
968 | if (!cpu->cfg.ext_d && cpu->cfg.ext_zcd) { | |
969 | error_setg(errp, "Zcd extension requires D extension"); | |
970 | return; | |
971 | } | |
972 | ||
973 | if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || | |
974 | cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { | |
975 | error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " | |
976 | "extension"); | |
977 | return; | |
978 | } | |
979 | ||
980 | if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { | |
981 | error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " | |
982 | "Zcd extension"); | |
983 | return; | |
984 | } | |
985 | ||
986 | if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) { | |
987 | error_setg(errp, "Zcmt extension requires Zicsr extension"); | |
988 | return; | |
989 | } | |
990 | ||
5ab10952 DHB |
991 | if (cpu->cfg.ext_zk) { |
992 | cpu->cfg.ext_zkn = true; | |
993 | cpu->cfg.ext_zkr = true; | |
994 | cpu->cfg.ext_zkt = true; | |
995 | } | |
996 | ||
997 | if (cpu->cfg.ext_zkn) { | |
998 | cpu->cfg.ext_zbkb = true; | |
999 | cpu->cfg.ext_zbkc = true; | |
1000 | cpu->cfg.ext_zbkx = true; | |
1001 | cpu->cfg.ext_zkne = true; | |
1002 | cpu->cfg.ext_zknd = true; | |
1003 | cpu->cfg.ext_zknh = true; | |
1004 | } | |
1005 | ||
1006 | if (cpu->cfg.ext_zks) { | |
1007 | cpu->cfg.ext_zbkb = true; | |
1008 | cpu->cfg.ext_zbkc = true; | |
1009 | cpu->cfg.ext_zbkx = true; | |
1010 | cpu->cfg.ext_zksed = true; | |
1011 | cpu->cfg.ext_zksh = true; | |
1012 | } | |
1013 | ||
1014 | if (cpu->cfg.ext_i) { | |
1015 | ext |= RVI; | |
1016 | } | |
1017 | if (cpu->cfg.ext_e) { | |
1018 | ext |= RVE; | |
1019 | } | |
1020 | if (cpu->cfg.ext_m) { | |
1021 | ext |= RVM; | |
1022 | } | |
1023 | if (cpu->cfg.ext_a) { | |
1024 | ext |= RVA; | |
1025 | } | |
1026 | if (cpu->cfg.ext_f) { | |
1027 | ext |= RVF; | |
1028 | } | |
1029 | if (cpu->cfg.ext_d) { | |
1030 | ext |= RVD; | |
1031 | } | |
1032 | if (cpu->cfg.ext_c) { | |
1033 | ext |= RVC; | |
1034 | } | |
1035 | if (cpu->cfg.ext_s) { | |
1036 | ext |= RVS; | |
1037 | } | |
1038 | if (cpu->cfg.ext_u) { | |
1039 | ext |= RVU; | |
1040 | } | |
1041 | if (cpu->cfg.ext_h) { | |
1042 | ext |= RVH; | |
1043 | } | |
1044 | if (cpu->cfg.ext_v) { | |
1045 | int vext_version = VEXT_VERSION_1_00_0; | |
1046 | ext |= RVV; | |
1047 | if (!is_power_of_2(cpu->cfg.vlen)) { | |
1048 | error_setg(errp, | |
51f33081 | 1049 | "Vector extension VLEN must be power of 2"); |
5ab10952 DHB |
1050 | return; |
1051 | } | |
1052 | if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { | |
1053 | error_setg(errp, | |
51f33081 WL |
1054 | "Vector extension implementation only supports VLEN " |
1055 | "in the range [128, %d]", RV_VLEN_MAX); | |
5ab10952 DHB |
1056 | return; |
1057 | } | |
1058 | if (!is_power_of_2(cpu->cfg.elen)) { | |
1059 | error_setg(errp, | |
51f33081 | 1060 | "Vector extension ELEN must be power of 2"); |
5ab10952 DHB |
1061 | return; |
1062 | } | |
51f33081 | 1063 | if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { |
5ab10952 | 1064 | error_setg(errp, |
51f33081 WL |
1065 | "Vector extension implementation only supports ELEN " |
1066 | "in the range [8, 64]"); | |
5ab10952 DHB |
1067 | return; |
1068 | } | |
51f33081 WL |
1069 | if (cpu->cfg.vext_spec) { |
1070 | if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { | |
1071 | vext_version = VEXT_VERSION_1_00_0; | |
1072 | } else { | |
1073 | error_setg(errp, | |
1074 | "Unsupported vector spec version '%s'", | |
1075 | cpu->cfg.vext_spec); | |
1076 | return; | |
1077 | } | |
1078 | } else { | |
1079 | qemu_log("vector version is not specified, " | |
1080 | "use the default value v1.0\n"); | |
1081 | } | |
1082 | set_vext_version(env, vext_version); | |
5ab10952 DHB |
1083 | } |
1084 | if (cpu->cfg.ext_j) { | |
1085 | ext |= RVJ; | |
1086 | } | |
1087 | ||
1088 | set_misa(env, env->misa_mxl, ext); | |
1089 | } | |
1090 | ||
6f23aaeb AG |
1091 | #ifndef CONFIG_USER_ONLY |
1092 | static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) | |
1093 | { | |
1094 | bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; | |
6df3747a AG |
1095 | uint8_t satp_mode_map_max; |
1096 | uint8_t satp_mode_supported_max = | |
1097 | satp_mode_max_from_map(cpu->cfg.satp_mode.supported); | |
6f23aaeb AG |
1098 | |
1099 | if (cpu->cfg.satp_mode.map == 0) { | |
1100 | if (cpu->cfg.satp_mode.init == 0) { | |
1101 | /* If unset by the user, we fallback to the default satp mode. */ | |
1102 | set_satp_mode_default_map(cpu); | |
1103 | } else { | |
1104 | /* | |
1105 | * Find the lowest level that was disabled and then enable the | |
1106 | * first valid level below which can be found in | |
1107 | * valid_vm_1_10_32/64. | |
1108 | */ | |
1109 | for (int i = 1; i < 16; ++i) { | |
6df3747a AG |
1110 | if ((cpu->cfg.satp_mode.init & (1 << i)) && |
1111 | (cpu->cfg.satp_mode.supported & (1 << i))) { | |
6f23aaeb | 1112 | for (int j = i - 1; j >= 0; --j) { |
6df3747a | 1113 | if (cpu->cfg.satp_mode.supported & (1 << j)) { |
6f23aaeb AG |
1114 | cpu->cfg.satp_mode.map |= (1 << j); |
1115 | break; | |
1116 | } | |
1117 | } | |
1118 | break; | |
1119 | } | |
1120 | } | |
1121 | } | |
1122 | } | |
1123 | ||
6df3747a AG |
1124 | satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); |
1125 | ||
1126 | /* Make sure the user asked for a supported configuration (HW and qemu) */ | |
1127 | if (satp_mode_map_max > satp_mode_supported_max) { | |
1128 | error_setg(errp, "satp_mode %s is higher than hw max capability %s", | |
1129 | satp_mode_str(satp_mode_map_max, rv32), | |
1130 | satp_mode_str(satp_mode_supported_max, rv32)); | |
1131 | return; | |
6f23aaeb AG |
1132 | } |
1133 | ||
1134 | /* | |
1135 | * Make sure the user did not ask for an invalid configuration as per | |
1136 | * the specification. | |
1137 | */ | |
6f23aaeb | 1138 | if (!rv32) { |
6df3747a | 1139 | for (int i = satp_mode_map_max - 1; i >= 0; --i) { |
6f23aaeb AG |
1140 | if (!(cpu->cfg.satp_mode.map & (1 << i)) && |
1141 | (cpu->cfg.satp_mode.init & (1 << i)) && | |
6df3747a | 1142 | (cpu->cfg.satp_mode.supported & (1 << i))) { |
6f23aaeb AG |
1143 | error_setg(errp, "cannot disable %s satp mode if %s " |
1144 | "is enabled", satp_mode_str(i, false), | |
6df3747a | 1145 | satp_mode_str(satp_mode_map_max, false)); |
6f23aaeb AG |
1146 | return; |
1147 | } | |
1148 | } | |
1149 | } | |
1150 | ||
1151 | /* Finally expand the map so that all valid modes are set */ | |
6df3747a AG |
1152 | for (int i = satp_mode_map_max - 1; i >= 0; --i) { |
1153 | if (cpu->cfg.satp_mode.supported & (1 << i)) { | |
6f23aaeb AG |
1154 | cpu->cfg.satp_mode.map |= (1 << i); |
1155 | } | |
1156 | } | |
1157 | } | |
1158 | #endif | |
1159 | ||
1160 | static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) | |
1161 | { | |
1162 | #ifndef CONFIG_USER_ONLY | |
1163 | Error *local_err = NULL; | |
1164 | ||
1165 | riscv_cpu_satp_mode_finalize(cpu, &local_err); | |
1166 | if (local_err != NULL) { | |
1167 | error_propagate(errp, local_err); | |
1168 | return; | |
1169 | } | |
1170 | #endif | |
1171 | } | |
1172 | ||
dc5bd18f MC |
1173 | static void riscv_cpu_realize(DeviceState *dev, Error **errp) |
1174 | { | |
1175 | CPUState *cs = CPU(dev); | |
c4e95030 AF |
1176 | RISCVCPU *cpu = RISCV_CPU(dev); |
1177 | CPURISCVState *env = &cpu->env; | |
dc5bd18f | 1178 | RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); |
1191be09 | 1179 | CPUClass *cc = CPU_CLASS(mcc); |
9a1f054d | 1180 | int i, priv_version = -1; |
dc5bd18f MC |
1181 | Error *local_err = NULL; |
1182 | ||
1183 | cpu_exec_realizefn(cs, &local_err); | |
1184 | if (local_err != NULL) { | |
1185 | error_propagate(errp, local_err); | |
1186 | return; | |
1187 | } | |
1188 | ||
c4e95030 | 1189 | if (cpu->cfg.priv_spec) { |
7100fe6c AP |
1190 | if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { |
1191 | priv_version = PRIV_VERSION_1_12_0; | |
1192 | } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { | |
e3147506 AF |
1193 | priv_version = PRIV_VERSION_1_11_0; |
1194 | } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { | |
c4e95030 | 1195 | priv_version = PRIV_VERSION_1_10_0; |
c4e95030 AF |
1196 | } else { |
1197 | error_setg(errp, | |
1198 | "Unsupported privilege spec version '%s'", | |
1199 | cpu->cfg.priv_spec); | |
1200 | return; | |
1201 | } | |
1202 | } | |
1203 | ||
18800095 | 1204 | if (priv_version >= PRIV_VERSION_1_10_0) { |
a8b37120 | 1205 | set_priv_version(env, priv_version); |
a8b37120 | 1206 | } |
c4e95030 | 1207 | |
9a1f054d AP |
1208 | /* Force disable extensions if priv spec version does not match */ |
1209 | for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { | |
1210 | if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && | |
1211 | (env->priv_ver < isa_edata_arr[i].min_version)) { | |
1212 | isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); | |
1213 | #ifndef CONFIG_USER_ONLY | |
877a3a37 BM |
1214 | warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx |
1215 | " because privilege spec version does not match", | |
1216 | isa_edata_arr[i].name, env->mhartid); | |
9a1f054d AP |
1217 | #else |
1218 | warn_report("disabling %s extension because " | |
1219 | "privilege spec version does not match", | |
1220 | isa_edata_arr[i].name); | |
1221 | #endif | |
1222 | } | |
1223 | } | |
1224 | ||
6a3ffda2 | 1225 | if (cpu->cfg.epmp && !cpu->cfg.pmp) { |
5da9514e HW |
1226 | /* |
1227 | * Enhanced PMP should only be available | |
1228 | * on harts with PMP support | |
1229 | */ | |
6a3ffda2 DHB |
1230 | error_setg(errp, "Invalid configuration: EPMP requires PMP support"); |
1231 | return; | |
1acdb3b0 BM |
1232 | } |
1233 | ||
73f6ed97 | 1234 | |
43888c2f AP |
1235 | #ifndef CONFIG_USER_ONLY |
1236 | if (cpu->cfg.ext_sstc) { | |
1237 | riscv_timer_init(cpu); | |
1238 | } | |
1239 | #endif /* CONFIG_USER_ONLY */ | |
1240 | ||
e91a7227 RH |
1241 | /* Validate that MISA_MXL is set properly. */ |
1242 | switch (env->misa_mxl_max) { | |
1243 | #ifdef TARGET_RISCV64 | |
1244 | case MXL_RV64: | |
332dab68 | 1245 | case MXL_RV128: |
6c3a9247 | 1246 | cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; |
332dab68 | 1247 | break; |
e91a7227 RH |
1248 | #endif |
1249 | case MXL_RV32: | |
1191be09 | 1250 | cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; |
e91a7227 RH |
1251 | break; |
1252 | default: | |
1253 | g_assert_not_reached(); | |
1254 | } | |
1255 | assert(env->misa_mxl_max == env->misa_mxl); | |
1256 | ||
5ab10952 DHB |
1257 | riscv_cpu_validate_set_extensions(cpu, &local_err); |
1258 | if (local_err != NULL) { | |
1259 | error_propagate(errp, local_err); | |
1260 | return; | |
b55d7d34 AF |
1261 | } |
1262 | ||
14664483 AP |
1263 | #ifndef CONFIG_USER_ONLY |
1264 | if (cpu->cfg.pmu_num) { | |
1265 | if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { | |
1266 | cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, | |
1267 | riscv_pmu_timer_cb, cpu); | |
1268 | } | |
1269 | } | |
1270 | #endif | |
1271 | ||
6f23aaeb AG |
1272 | riscv_cpu_finalize_features(cpu, &local_err); |
1273 | if (local_err != NULL) { | |
1274 | error_propagate(errp, local_err); | |
1275 | return; | |
1276 | } | |
1277 | ||
5371f5cd JW |
1278 | riscv_cpu_register_gdb_regs_for_features(cs); |
1279 | ||
dc5bd18f MC |
1280 | qemu_init_vcpu(cs); |
1281 | cpu_reset(cs); | |
1282 | ||
1283 | mcc->parent_realize(dev, errp); | |
1284 | } | |
1285 | ||
0f0b70ee | 1286 | #ifndef CONFIG_USER_ONLY |
6f23aaeb AG |
1287 | static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, |
1288 | void *opaque, Error **errp) | |
1289 | { | |
1290 | RISCVSATPMap *satp_map = opaque; | |
1291 | uint8_t satp = satp_mode_from_str(name); | |
1292 | bool value; | |
1293 | ||
1294 | value = satp_map->map & (1 << satp); | |
1295 | ||
1296 | visit_type_bool(v, name, &value, errp); | |
1297 | } | |
1298 | ||
1299 | static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, | |
1300 | void *opaque, Error **errp) | |
1301 | { | |
1302 | RISCVSATPMap *satp_map = opaque; | |
1303 | uint8_t satp = satp_mode_from_str(name); | |
1304 | bool value; | |
1305 | ||
1306 | if (!visit_type_bool(v, name, &value, errp)) { | |
1307 | return; | |
1308 | } | |
1309 | ||
1310 | satp_map->map = deposit32(satp_map->map, satp, 1, value); | |
1311 | satp_map->init |= 1 << satp; | |
1312 | } | |
1313 | ||
1314 | static void riscv_add_satp_mode_properties(Object *obj) | |
1315 | { | |
1316 | RISCVCPU *cpu = RISCV_CPU(obj); | |
1317 | ||
1318 | if (cpu->env.misa_mxl == MXL_RV32) { | |
1319 | object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, | |
1320 | cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); | |
1321 | } else { | |
1322 | object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, | |
1323 | cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); | |
1324 | object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, | |
1325 | cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); | |
1326 | object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, | |
1327 | cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); | |
1328 | object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, | |
1329 | cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); | |
1330 | } | |
1331 | } | |
1332 | ||
0f0b70ee AF |
1333 | static void riscv_cpu_set_irq(void *opaque, int irq, int level) |
1334 | { | |
1335 | RISCVCPU *cpu = RISCV_CPU(opaque); | |
cd032fe7 | 1336 | CPURISCVState *env = &cpu->env; |
0f0b70ee | 1337 | |
cd032fe7 AP |
1338 | if (irq < IRQ_LOCAL_MAX) { |
1339 | switch (irq) { | |
1340 | case IRQ_U_SOFT: | |
1341 | case IRQ_S_SOFT: | |
1342 | case IRQ_VS_SOFT: | |
1343 | case IRQ_M_SOFT: | |
1344 | case IRQ_U_TIMER: | |
1345 | case IRQ_S_TIMER: | |
1346 | case IRQ_VS_TIMER: | |
1347 | case IRQ_M_TIMER: | |
1348 | case IRQ_U_EXT: | |
cd032fe7 AP |
1349 | case IRQ_VS_EXT: |
1350 | case IRQ_M_EXT: | |
8b5c807b | 1351 | if (kvm_enabled()) { |
cd032fe7 | 1352 | kvm_riscv_set_irq(cpu, irq, level); |
8b5c807b | 1353 | } else { |
bbb9fc25 | 1354 | riscv_cpu_update_mip(env, 1 << irq, BOOL_TO_MASK(level)); |
8b5c807b | 1355 | } |
cd032fe7 | 1356 | break; |
33fe584f AF |
1357 | case IRQ_S_EXT: |
1358 | if (kvm_enabled()) { | |
1359 | kvm_riscv_set_irq(cpu, irq, level); | |
1360 | } else { | |
1361 | env->external_seip = level; | |
bbb9fc25 | 1362 | riscv_cpu_update_mip(env, 1 << irq, |
33fe584f AF |
1363 | BOOL_TO_MASK(level | env->software_seip)); |
1364 | } | |
1365 | break; | |
cd032fe7 AP |
1366 | default: |
1367 | g_assert_not_reached(); | |
2b650fbb | 1368 | } |
cd032fe7 AP |
1369 | } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { |
1370 | /* Require H-extension for handling guest local interrupts */ | |
1371 | if (!riscv_has_ext(env, RVH)) { | |
1372 | g_assert_not_reached(); | |
1373 | } | |
1374 | ||
1375 | /* Compute bit position in HGEIP CSR */ | |
1376 | irq = irq - IRQ_LOCAL_MAX + 1; | |
1377 | if (env->geilen < irq) { | |
1378 | g_assert_not_reached(); | |
1379 | } | |
1380 | ||
1381 | /* Update HGEIP CSR */ | |
1382 | env->hgeip &= ~((target_ulong)1 << irq); | |
1383 | if (level) { | |
1384 | env->hgeip |= (target_ulong)1 << irq; | |
1385 | } | |
1386 | ||
1387 | /* Update mip.SGEIP bit */ | |
bbb9fc25 | 1388 | riscv_cpu_update_mip(env, MIP_SGEIP, |
cd032fe7 AP |
1389 | BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); |
1390 | } else { | |
0f0b70ee AF |
1391 | g_assert_not_reached(); |
1392 | } | |
1393 | } | |
1394 | #endif /* CONFIG_USER_ONLY */ | |
1395 | ||
dc5bd18f MC |
1396 | static void riscv_cpu_init(Object *obj) |
1397 | { | |
dc5bd18f MC |
1398 | RISCVCPU *cpu = RISCV_CPU(obj); |
1399 | ||
26b2bc58 AF |
1400 | cpu->cfg.ext_ifencei = true; |
1401 | cpu->cfg.ext_icsr = true; | |
1402 | cpu->cfg.mmu = true; | |
1403 | cpu->cfg.pmp = true; | |
1404 | ||
7506ed90 | 1405 | cpu_set_cpustate_pointers(cpu); |
0f0b70ee AF |
1406 | |
1407 | #ifndef CONFIG_USER_ONLY | |
cd032fe7 AP |
1408 | qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, |
1409 | IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); | |
0f0b70ee | 1410 | #endif /* CONFIG_USER_ONLY */ |
dc5bd18f MC |
1411 | } |
1412 | ||
26b2bc58 | 1413 | static Property riscv_cpu_extensions[] = { |
9d3d60b7 | 1414 | /* Defaults for standard extensions */ |
b55d7d34 AF |
1415 | DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), |
1416 | DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), | |
1d398ab9 | 1417 | DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), |
b55d7d34 AF |
1418 | DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), |
1419 | DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), | |
1420 | DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), | |
1421 | DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), | |
1422 | DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), | |
1423 | DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), | |
1424 | DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), | |
9ec6622d | 1425 | DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), |
07cb270a | 1426 | DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), |
18d6d89e | 1427 | DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), |
14664483 | 1428 | DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), |
9d3d60b7 AF |
1429 | DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), |
1430 | DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), | |
4696f0ab | 1431 | DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), |
260b594d | 1432 | DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), |
13fb8c7b | 1433 | DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), |
e5237730 | 1434 | DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), |
2fc1b44d | 1435 | DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), |
bfefe406 | 1436 | DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), |
058d9d30 | 1437 | DEFINE_PROP_BOOL("Zve64d", RISCVCPU, cfg.ext_zve64d, false), |
9d3d60b7 AF |
1438 | DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), |
1439 | DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), | |
43888c2f | 1440 | DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true), |
9d3d60b7 AF |
1441 | |
1442 | DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), | |
9ec6622d FC |
1443 | DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), |
1444 | DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), | |
1445 | DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), | |
9d3d60b7 | 1446 | |
62108f05 WL |
1447 | DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true), |
1448 | ||
c5d77ddd | 1449 | DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), |
2bacb224 | 1450 | DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), |
bbce8ba8 | 1451 | DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), |
2bacb224 | 1452 | |
0643c12e VG |
1453 | DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), |
1454 | DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), | |
1455 | DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), | |
cf7ed971 WL |
1456 | DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false), |
1457 | DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false), | |
1458 | DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false), | |
0643c12e | 1459 | DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), |
cf7ed971 WL |
1460 | DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false), |
1461 | DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false), | |
1462 | DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false), | |
1463 | DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false), | |
1464 | DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false), | |
1465 | DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false), | |
1466 | DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false), | |
1467 | DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false), | |
1468 | DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), | |
1469 | DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), | |
dfdb46a3 | 1470 | |
6b1accef WL |
1471 | DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), |
1472 | DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), | |
1473 | DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), | |
1474 | DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), | |
1475 | ||
e05da09b CM |
1476 | DEFINE_PROP_BOOL("zicbom", RISCVCPU, cfg.ext_icbom, true), |
1477 | DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64), | |
a939c500 CM |
1478 | DEFINE_PROP_BOOL("zicboz", RISCVCPU, cfg.ext_icboz, true), |
1479 | DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), | |
1480 | ||
6d00ffad WL |
1481 | DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), |
1482 | ||
0d429bd2 | 1483 | /* Vendor-specific custom extensions */ |
c9410a68 | 1484 | DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), |
426c0491 | 1485 | DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), |
fa134585 | 1486 | DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), |
49a7f3aa | 1487 | DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), |
32909338 | 1488 | DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), |
d4d90115 | 1489 | DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false), |
578086ba | 1490 | DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false), |
b8a5832b | 1491 | DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), |
45f9df86 | 1492 | DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false), |
af99aa72 | 1493 | DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false), |
134c3ffa | 1494 | DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), |
0d429bd2 PT |
1495 | DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), |
1496 | ||
dfdb46a3 | 1497 | /* These are experimental so mark with 'x-' */ |
b8e1f32c | 1498 | DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), |
0ee9a4e5 | 1499 | DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), |
d364c0ab WL |
1500 | |
1501 | DEFINE_PROP_BOOL("x-zca", RISCVCPU, cfg.ext_zca, false), | |
1502 | DEFINE_PROP_BOOL("x-zcb", RISCVCPU, cfg.ext_zcb, false), | |
1503 | DEFINE_PROP_BOOL("x-zcd", RISCVCPU, cfg.ext_zcd, false), | |
1504 | DEFINE_PROP_BOOL("x-zcf", RISCVCPU, cfg.ext_zcf, false), | |
1505 | DEFINE_PROP_BOOL("x-zcmp", RISCVCPU, cfg.ext_zcmp, false), | |
1506 | DEFINE_PROP_BOOL("x-zcmt", RISCVCPU, cfg.ext_zcmt, false), | |
1507 | ||
a44da25a | 1508 | /* ePMP 0.9.3 */ |
5da9514e | 1509 | DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), |
dc9acc9c AP |
1510 | DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), |
1511 | DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), | |
5da9514e | 1512 | |
058d9d30 WL |
1513 | DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false), |
1514 | DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false), | |
1515 | ||
26b2bc58 AF |
1516 | DEFINE_PROP_END_OF_LIST(), |
1517 | }; | |
1518 | ||
c66ffcd5 DHB |
1519 | /* |
1520 | * Register CPU props based on env.misa_ext. If a non-zero | |
1521 | * value was set, register only the required cpu->cfg.ext_* | |
1522 | * properties and leave. env.misa_ext = 0 means that we want | |
1523 | * all the default properties to be registered. | |
1524 | */ | |
c01756a7 | 1525 | static void register_cpu_props(Object *obj) |
26b2bc58 | 1526 | { |
c01756a7 | 1527 | RISCVCPU *cpu = RISCV_CPU(obj); |
c66ffcd5 | 1528 | uint32_t misa_ext = cpu->env.misa_ext; |
26b2bc58 | 1529 | Property *prop; |
c01756a7 | 1530 | DeviceState *dev = DEVICE(obj); |
26b2bc58 | 1531 | |
c66ffcd5 DHB |
1532 | /* |
1533 | * If misa_ext is not zero, set cfg properties now to | |
1534 | * allow them to be read during riscv_cpu_realize() | |
1535 | * later on. | |
1536 | */ | |
1537 | if (cpu->env.misa_ext != 0) { | |
1538 | cpu->cfg.ext_i = misa_ext & RVI; | |
1539 | cpu->cfg.ext_e = misa_ext & RVE; | |
1540 | cpu->cfg.ext_m = misa_ext & RVM; | |
1541 | cpu->cfg.ext_a = misa_ext & RVA; | |
1542 | cpu->cfg.ext_f = misa_ext & RVF; | |
1543 | cpu->cfg.ext_d = misa_ext & RVD; | |
1544 | cpu->cfg.ext_v = misa_ext & RVV; | |
1545 | cpu->cfg.ext_c = misa_ext & RVC; | |
1546 | cpu->cfg.ext_s = misa_ext & RVS; | |
1547 | cpu->cfg.ext_u = misa_ext & RVU; | |
1548 | cpu->cfg.ext_h = misa_ext & RVH; | |
1549 | cpu->cfg.ext_j = misa_ext & RVJ; | |
1550 | ||
1551 | /* | |
1552 | * We don't want to set the default riscv_cpu_extensions | |
1553 | * in this case. | |
1554 | */ | |
1555 | return; | |
1556 | } | |
1557 | ||
26b2bc58 AF |
1558 | for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { |
1559 | qdev_property_add_static(dev, prop); | |
1560 | } | |
6f23aaeb AG |
1561 | |
1562 | #ifndef CONFIG_USER_ONLY | |
1563 | riscv_add_satp_mode_properties(obj); | |
1564 | #endif | |
26b2bc58 AF |
1565 | } |
1566 | ||
1567 | static Property riscv_cpu_properties[] = { | |
1568 | DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), | |
1569 | ||
1570 | DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), | |
1571 | DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), | |
1572 | DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), | |
1573 | ||
277b210d AF |
1574 | #ifndef CONFIG_USER_ONLY |
1575 | DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), | |
1576 | #endif | |
a4a9a443 TO |
1577 | |
1578 | DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), | |
b8312675 | 1579 | |
1580 | DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), | |
1ad3f9bd | 1581 | DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), |
54bd9b6e DHB |
1582 | |
1583 | /* | |
1584 | * write_misa() is marked as experimental for now so mark | |
1585 | * it with -x and default to 'false'. | |
1586 | */ | |
1587 | DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false), | |
c4e95030 AF |
1588 | DEFINE_PROP_END_OF_LIST(), |
1589 | }; | |
1590 | ||
edf64786 SP |
1591 | static gchar *riscv_gdb_arch_name(CPUState *cs) |
1592 | { | |
1593 | RISCVCPU *cpu = RISCV_CPU(cs); | |
1594 | CPURISCVState *env = &cpu->env; | |
1595 | ||
db23e5d9 RH |
1596 | switch (riscv_cpu_mxl(env)) { |
1597 | case MXL_RV32: | |
edf64786 | 1598 | return g_strdup("riscv:rv32"); |
db23e5d9 | 1599 | case MXL_RV64: |
332dab68 | 1600 | case MXL_RV128: |
edf64786 | 1601 | return g_strdup("riscv:rv64"); |
db23e5d9 RH |
1602 | default: |
1603 | g_assert_not_reached(); | |
edf64786 SP |
1604 | } |
1605 | } | |
1606 | ||
b93777e1 BM |
1607 | static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) |
1608 | { | |
1609 | RISCVCPU *cpu = RISCV_CPU(cs); | |
1610 | ||
1611 | if (strcmp(xmlname, "riscv-csr.xml") == 0) { | |
1612 | return cpu->dyn_csr_xml; | |
719d3561 HW |
1613 | } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { |
1614 | return cpu->dyn_vreg_xml; | |
b93777e1 BM |
1615 | } |
1616 | ||
1617 | return NULL; | |
1618 | } | |
1619 | ||
8b80bd28 | 1620 | #ifndef CONFIG_USER_ONLY |
f1bd6f8e MC |
1621 | static int64_t riscv_get_arch_id(CPUState *cs) |
1622 | { | |
1623 | RISCVCPU *cpu = RISCV_CPU(cs); | |
1624 | ||
1625 | return cpu->env.mhartid; | |
1626 | } | |
1627 | ||
8b80bd28 PMD |
1628 | #include "hw/core/sysemu-cpu-ops.h" |
1629 | ||
1630 | static const struct SysemuCPUOps riscv_sysemu_ops = { | |
08928c6d | 1631 | .get_phys_page_debug = riscv_cpu_get_phys_page_debug, |
715e3c1a PMD |
1632 | .write_elf64_note = riscv_cpu_write_elf64_note, |
1633 | .write_elf32_note = riscv_cpu_write_elf32_note, | |
feece4d0 | 1634 | .legacy_vmsd = &vmstate_riscv_cpu, |
8b80bd28 PMD |
1635 | }; |
1636 | #endif | |
1637 | ||
78271684 CF |
1638 | #include "hw/core/tcg-cpu-ops.h" |
1639 | ||
11906557 | 1640 | static const struct TCGCPUOps riscv_tcg_ops = { |
78271684 CF |
1641 | .initialize = riscv_translate_init, |
1642 | .synchronize_from_tb = riscv_cpu_synchronize_from_tb, | |
ad1e84f5 | 1643 | .restore_state_to_opc = riscv_restore_state_to_opc, |
78271684 CF |
1644 | |
1645 | #ifndef CONFIG_USER_ONLY | |
263e2ab2 | 1646 | .tlb_fill = riscv_cpu_tlb_fill, |
17b3c353 | 1647 | .cpu_exec_interrupt = riscv_cpu_exec_interrupt, |
78271684 CF |
1648 | .do_interrupt = riscv_cpu_do_interrupt, |
1649 | .do_transaction_failed = riscv_cpu_do_transaction_failed, | |
1650 | .do_unaligned_access = riscv_cpu_do_unaligned_access, | |
b5f6379d BM |
1651 | .debug_excp_handler = riscv_cpu_debug_excp_handler, |
1652 | .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, | |
1653 | .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, | |
78271684 CF |
1654 | #endif /* !CONFIG_USER_ONLY */ |
1655 | }; | |
1656 | ||
dc5bd18f MC |
1657 | static void riscv_cpu_class_init(ObjectClass *c, void *data) |
1658 | { | |
1659 | RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); | |
1660 | CPUClass *cc = CPU_CLASS(c); | |
1661 | DeviceClass *dc = DEVICE_CLASS(c); | |
4fa485a7 | 1662 | ResettableClass *rc = RESETTABLE_CLASS(c); |
dc5bd18f | 1663 | |
41fbbba7 MZ |
1664 | device_class_set_parent_realize(dc, riscv_cpu_realize, |
1665 | &mcc->parent_realize); | |
dc5bd18f | 1666 | |
4fa485a7 PM |
1667 | resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL, |
1668 | &mcc->parent_phases); | |
dc5bd18f MC |
1669 | |
1670 | cc->class_by_name = riscv_cpu_class_by_name; | |
1671 | cc->has_work = riscv_cpu_has_work; | |
dc5bd18f MC |
1672 | cc->dump_state = riscv_cpu_dump_state; |
1673 | cc->set_pc = riscv_cpu_set_pc; | |
e4fdf9df | 1674 | cc->get_pc = riscv_cpu_get_pc; |
dc5bd18f MC |
1675 | cc->gdb_read_register = riscv_cpu_gdb_read_register; |
1676 | cc->gdb_write_register = riscv_cpu_gdb_write_register; | |
5371f5cd | 1677 | cc->gdb_num_core_regs = 33; |
dc5bd18f MC |
1678 | cc->gdb_stop_before_watchpoint = true; |
1679 | cc->disas_set_info = riscv_cpu_disas_set_info; | |
8a4ca3c1 | 1680 | #ifndef CONFIG_USER_ONLY |
8b80bd28 | 1681 | cc->sysemu_ops = &riscv_sysemu_ops; |
f1bd6f8e | 1682 | cc->get_arch_id = riscv_get_arch_id; |
dc5bd18f | 1683 | #endif |
edf64786 | 1684 | cc->gdb_arch_name = riscv_gdb_arch_name; |
b93777e1 | 1685 | cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; |
78271684 | 1686 | cc->tcg_ops = &riscv_tcg_ops; |
6a3d2e7c | 1687 | |
4f67d30b | 1688 | device_class_set_props(dc, riscv_cpu_properties); |
dc5bd18f MC |
1689 | } |
1690 | ||
a775398b AP |
1691 | static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) |
1692 | { | |
1693 | char *old = *isa_str; | |
1694 | char *new = *isa_str; | |
1695 | int i; | |
1696 | ||
a775398b | 1697 | for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { |
9a1f054d AP |
1698 | if (isa_edata_arr[i].multi_letter && |
1699 | isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { | |
a775398b AP |
1700 | new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); |
1701 | g_free(old); | |
1702 | old = new; | |
1703 | } | |
1704 | } | |
1705 | ||
1706 | *isa_str = new; | |
1707 | } | |
1708 | ||
dc5bd18f MC |
1709 | char *riscv_isa_string(RISCVCPU *cpu) |
1710 | { | |
1711 | int i; | |
0e2c3770 | 1712 | const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); |
d1fd31f8 MC |
1713 | char *isa_str = g_new(char, maxlen); |
1714 | char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); | |
0e2c3770 TO |
1715 | for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { |
1716 | if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { | |
1717 | *p++ = qemu_tolower(riscv_single_letter_exts[i]); | |
dc5bd18f MC |
1718 | } |
1719 | } | |
d1fd31f8 | 1720 | *p = '\0'; |
a4a9a443 TO |
1721 | if (!cpu->cfg.short_isa_string) { |
1722 | riscv_isa_string_ext(cpu, &isa_str, maxlen); | |
1723 | } | |
d1fd31f8 | 1724 | return isa_str; |
dc5bd18f MC |
1725 | } |
1726 | ||
eab15862 | 1727 | static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) |
dc5bd18f | 1728 | { |
eab15862 MC |
1729 | ObjectClass *class_a = (ObjectClass *)a; |
1730 | ObjectClass *class_b = (ObjectClass *)b; | |
1731 | const char *name_a, *name_b; | |
dc5bd18f | 1732 | |
eab15862 MC |
1733 | name_a = object_class_get_name(class_a); |
1734 | name_b = object_class_get_name(class_b); | |
1735 | return strcmp(name_a, name_b); | |
dc5bd18f MC |
1736 | } |
1737 | ||
eab15862 | 1738 | static void riscv_cpu_list_entry(gpointer data, gpointer user_data) |
dc5bd18f | 1739 | { |
eab15862 MC |
1740 | const char *typename = object_class_get_name(OBJECT_CLASS(data)); |
1741 | int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); | |
dc5bd18f | 1742 | |
0442428a | 1743 | qemu_printf("%.*s\n", len, typename); |
eab15862 | 1744 | } |
dc5bd18f | 1745 | |
0442428a | 1746 | void riscv_cpu_list(void) |
eab15862 | 1747 | { |
eab15862 MC |
1748 | GSList *list; |
1749 | ||
1750 | list = object_class_get_list(TYPE_RISCV_CPU, false); | |
1751 | list = g_slist_sort(list, riscv_cpu_list_compare); | |
0442428a | 1752 | g_slist_foreach(list, riscv_cpu_list_entry, NULL); |
eab15862 | 1753 | g_slist_free(list); |
dc5bd18f MC |
1754 | } |
1755 | ||
eab15862 MC |
1756 | #define DEFINE_CPU(type_name, initfn) \ |
1757 | { \ | |
1758 | .name = type_name, \ | |
1759 | .parent = TYPE_RISCV_CPU, \ | |
1760 | .instance_init = initfn \ | |
1761 | } | |
1762 | ||
1763 | static const TypeInfo riscv_cpu_type_infos[] = { | |
1764 | { | |
1765 | .name = TYPE_RISCV_CPU, | |
1766 | .parent = TYPE_CPU, | |
1767 | .instance_size = sizeof(RISCVCPU), | |
5de5b99b | 1768 | .instance_align = __alignof__(RISCVCPU), |
eab15862 MC |
1769 | .instance_init = riscv_cpu_init, |
1770 | .abstract = true, | |
1771 | .class_size = sizeof(RISCVCPUClass), | |
1772 | .class_init = riscv_cpu_class_init, | |
1773 | }, | |
1774 | DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), | |
10f1ca27 YJ |
1775 | #if defined(CONFIG_KVM) |
1776 | DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), | |
1777 | #endif | |
eab15862 | 1778 | #if defined(TARGET_RISCV32) |
094b072c | 1779 | DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), |
e8905c6c | 1780 | DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), |
114baaca | 1781 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), |
2fdd2c09 | 1782 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), |
114baaca | 1783 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), |
eab15862 | 1784 | #elif defined(TARGET_RISCV64) |
094b072c | 1785 | DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), |
114baaca AF |
1786 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), |
1787 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), | |
6ddc7069 | 1788 | DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), |
95bd8daa | 1789 | DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), |
332dab68 | 1790 | DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), |
eab15862 MC |
1791 | #endif |
1792 | }; | |
1793 | ||
1794 | DEFINE_TYPES(riscv_cpu_type_infos) |