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dc5bd18f MC |
1 | /* |
2 | * QEMU RISC-V CPU | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
0442428a | 21 | #include "qemu/qemu-print.h" |
856dfd8a | 22 | #include "qemu/ctype.h" |
dc5bd18f MC |
23 | #include "qemu/log.h" |
24 | #include "cpu.h" | |
95bd8daa | 25 | #include "cpu_vendorid.h" |
14664483 | 26 | #include "pmu.h" |
f7697f0e | 27 | #include "internals.h" |
43888c2f | 28 | #include "time_helper.h" |
dc5bd18f MC |
29 | #include "exec/exec-all.h" |
30 | #include "qapi/error.h" | |
b55d7d34 | 31 | #include "qemu/error-report.h" |
c4e95030 | 32 | #include "hw/qdev-properties.h" |
dc5bd18f | 33 | #include "migration/vmstate.h" |
135b03cb | 34 | #include "fpu/softfloat-helpers.h" |
ad40be27 YJ |
35 | #include "sysemu/kvm.h" |
36 | #include "kvm_riscv.h" | |
dc5bd18f MC |
37 | |
38 | /* RISC-V CPU definitions */ | |
39 | ||
9951ba94 FC |
40 | #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ |
41 | (QEMU_VERSION_MINOR << 8) | \ | |
42 | (QEMU_VERSION_MICRO)) | |
075eeda9 | 43 | #define RISCV_CPU_MIMPID RISCV_CPU_MARCHID |
9951ba94 | 44 | |
0e2c3770 | 45 | static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; |
dc5bd18f | 46 | |
a775398b AP |
47 | struct isa_ext_data { |
48 | const char *name; | |
9a1f054d AP |
49 | bool multi_letter; |
50 | int min_version; | |
51 | int ext_enable_offset; | |
a775398b AP |
52 | }; |
53 | ||
9a1f054d AP |
54 | #define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \ |
55 | {#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} | |
56 | ||
57 | /** | |
58 | * Here are the ordering rules of extension naming defined by RISC-V | |
59 | * specification : | |
60 | * 1. All extensions should be separated from other multi-letter extensions | |
61 | * by an underscore. | |
62 | * 2. The first letter following the 'Z' conventionally indicates the most | |
63 | * closely related alphabetical extension category, IMAFDQLCBKJTPVH. | |
64 | * If multiple 'Z' extensions are named, they should be ordered first | |
65 | * by category, then alphabetically within a category. | |
66 | * 3. Standard supervisor-level extensions (starts with 'S') should be | |
67 | * listed after standard unprivileged extensions. If multiple | |
68 | * supervisor-level extensions are listed, they should be ordered | |
69 | * alphabetically. | |
70 | * 4. Non-standard extensions (starts with 'X') must be listed after all | |
71 | * standard extensions. They must be separated from other multi-letter | |
72 | * extensions by an underscore. | |
73 | */ | |
74 | static const struct isa_ext_data isa_edata_arr[] = { | |
75 | ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h), | |
0e660142 | 76 | ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_10_0, ext_v), |
9a1f054d AP |
77 | ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr), |
78 | ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei), | |
4696f0ab | 79 | ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause), |
260b594d | 80 | ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs), |
7ad2878c | 81 | ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_11_0, ext_zfh), |
9a1f054d AP |
82 | ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin), |
83 | ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx), | |
84 | ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx), | |
85 | ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba), | |
86 | ISA_EXT_DATA_ENTRY(zbb, true, PRIV_VERSION_1_12_0, ext_zbb), | |
87 | ISA_EXT_DATA_ENTRY(zbc, true, PRIV_VERSION_1_12_0, ext_zbc), | |
88 | ISA_EXT_DATA_ENTRY(zbkb, true, PRIV_VERSION_1_12_0, ext_zbkb), | |
89 | ISA_EXT_DATA_ENTRY(zbkc, true, PRIV_VERSION_1_12_0, ext_zbkc), | |
90 | ISA_EXT_DATA_ENTRY(zbkx, true, PRIV_VERSION_1_12_0, ext_zbkx), | |
91 | ISA_EXT_DATA_ENTRY(zbs, true, PRIV_VERSION_1_12_0, ext_zbs), | |
92 | ISA_EXT_DATA_ENTRY(zk, true, PRIV_VERSION_1_12_0, ext_zk), | |
93 | ISA_EXT_DATA_ENTRY(zkn, true, PRIV_VERSION_1_12_0, ext_zkn), | |
94 | ISA_EXT_DATA_ENTRY(zknd, true, PRIV_VERSION_1_12_0, ext_zknd), | |
95 | ISA_EXT_DATA_ENTRY(zkne, true, PRIV_VERSION_1_12_0, ext_zkne), | |
96 | ISA_EXT_DATA_ENTRY(zknh, true, PRIV_VERSION_1_12_0, ext_zknh), | |
97 | ISA_EXT_DATA_ENTRY(zkr, true, PRIV_VERSION_1_12_0, ext_zkr), | |
98 | ISA_EXT_DATA_ENTRY(zks, true, PRIV_VERSION_1_12_0, ext_zks), | |
99 | ISA_EXT_DATA_ENTRY(zksed, true, PRIV_VERSION_1_12_0, ext_zksed), | |
100 | ISA_EXT_DATA_ENTRY(zksh, true, PRIV_VERSION_1_12_0, ext_zksh), | |
101 | ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt), | |
102 | ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f), | |
103 | ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f), | |
104 | ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), | |
105 | ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), | |
dc9acc9c AP |
106 | ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia), |
107 | ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia), | |
14664483 | 108 | ISA_EXT_DATA_ENTRY(sscofpmf, true, PRIV_VERSION_1_12_0, ext_sscofpmf), |
43888c2f | 109 | ISA_EXT_DATA_ENTRY(sstc, true, PRIV_VERSION_1_12_0, ext_sstc), |
9a1f054d AP |
110 | ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), |
111 | ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), | |
112 | ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), | |
c9410a68 | 113 | ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba), |
426c0491 | 114 | ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb), |
fa134585 | 115 | ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs), |
49a7f3aa | 116 | ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), |
32909338 | 117 | ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov), |
d4d90115 | 118 | ISA_EXT_DATA_ENTRY(xtheadfmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadfmemidx), |
578086ba | 119 | ISA_EXT_DATA_ENTRY(xtheadfmv, true, PRIV_VERSION_1_11_0, ext_xtheadfmv), |
b8a5832b | 120 | ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac), |
45f9df86 | 121 | ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadmemidx), |
af99aa72 | 122 | ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xtheadmempair), |
134c3ffa | 123 | ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync), |
e0dea2f5 | 124 | ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), |
9a1f054d AP |
125 | }; |
126 | ||
127 | static bool isa_ext_is_enabled(RISCVCPU *cpu, | |
128 | const struct isa_ext_data *edata) | |
129 | { | |
130 | bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; | |
131 | ||
132 | return *ext_enabled; | |
133 | } | |
134 | ||
135 | static void isa_ext_update_enabled(RISCVCPU *cpu, | |
136 | const struct isa_ext_data *edata, bool en) | |
137 | { | |
138 | bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; | |
139 | ||
140 | *ext_enabled = en; | |
141 | } | |
142 | ||
dc5bd18f | 143 | const char * const riscv_int_regnames[] = { |
a9f37afa AP |
144 | "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", |
145 | "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", | |
146 | "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", | |
147 | "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", | |
148 | "x28/t3", "x29/t4", "x30/t5", "x31/t6" | |
dc5bd18f MC |
149 | }; |
150 | ||
2b547084 FP |
151 | const char * const riscv_int_regnamesh[] = { |
152 | "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", | |
153 | "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", | |
154 | "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", | |
155 | "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", | |
156 | "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", | |
157 | "x30h/t5h", "x31h/t6h" | |
158 | }; | |
159 | ||
dc5bd18f | 160 | const char * const riscv_fpr_regnames[] = { |
a9f37afa AP |
161 | "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", |
162 | "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", | |
163 | "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", | |
164 | "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", | |
165 | "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", | |
166 | "f30/ft10", "f31/ft11" | |
dc5bd18f MC |
167 | }; |
168 | ||
9a575d33 | 169 | static const char * const riscv_excp_names[] = { |
dc5bd18f MC |
170 | "misaligned_fetch", |
171 | "fault_fetch", | |
172 | "illegal_instruction", | |
173 | "breakpoint", | |
174 | "misaligned_load", | |
175 | "fault_load", | |
176 | "misaligned_store", | |
177 | "fault_store", | |
178 | "user_ecall", | |
179 | "supervisor_ecall", | |
180 | "hypervisor_ecall", | |
181 | "machine_ecall", | |
182 | "exec_page_fault", | |
183 | "load_page_fault", | |
184 | "reserved", | |
fd990e86 | 185 | "store_page_fault", |
ab67a1d0 AF |
186 | "reserved", |
187 | "reserved", | |
188 | "reserved", | |
189 | "reserved", | |
190 | "guest_exec_page_fault", | |
191 | "guest_load_page_fault", | |
192 | "reserved", | |
fd990e86 | 193 | "guest_store_page_fault", |
dc5bd18f MC |
194 | }; |
195 | ||
9a575d33 | 196 | static const char * const riscv_intr_names[] = { |
dc5bd18f MC |
197 | "u_software", |
198 | "s_software", | |
205377f8 | 199 | "vs_software", |
dc5bd18f MC |
200 | "m_software", |
201 | "u_timer", | |
202 | "s_timer", | |
205377f8 | 203 | "vs_timer", |
dc5bd18f MC |
204 | "m_timer", |
205 | "u_external", | |
6cfcf775 | 206 | "s_external", |
205377f8 | 207 | "vs_external", |
dc5bd18f | 208 | "m_external", |
426f0348 MC |
209 | "reserved", |
210 | "reserved", | |
211 | "reserved", | |
212 | "reserved" | |
dc5bd18f MC |
213 | }; |
214 | ||
26b2bc58 AF |
215 | static void register_cpu_props(DeviceState *dev); |
216 | ||
c51a3f5d YJ |
217 | const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) |
218 | { | |
219 | if (async) { | |
220 | return (cause < ARRAY_SIZE(riscv_intr_names)) ? | |
221 | riscv_intr_names[cause] : "(unknown)"; | |
222 | } else { | |
223 | return (cause < ARRAY_SIZE(riscv_excp_names)) ? | |
224 | riscv_excp_names[cause] : "(unknown)"; | |
225 | } | |
226 | } | |
227 | ||
e91a7227 | 228 | static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) |
dc5bd18f | 229 | { |
e91a7227 RH |
230 | env->misa_mxl_max = env->misa_mxl = mxl; |
231 | env->misa_ext_mask = env->misa_ext = ext; | |
dc5bd18f MC |
232 | } |
233 | ||
c9a73910 | 234 | static void set_priv_version(CPURISCVState *env, int priv_ver) |
dc5bd18f | 235 | { |
dc5bd18f MC |
236 | env->priv_ver = priv_ver; |
237 | } | |
238 | ||
32931383 LZ |
239 | static void set_vext_version(CPURISCVState *env, int vext_ver) |
240 | { | |
241 | env->vext_ver = vext_ver; | |
242 | } | |
243 | ||
dc5bd18f MC |
244 | static void riscv_any_cpu_init(Object *obj) |
245 | { | |
246 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
3820602f | 247 | #if defined(TARGET_RISCV32) |
e91a7227 | 248 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); |
3820602f | 249 | #elif defined(TARGET_RISCV64) |
e91a7227 | 250 | set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); |
3820602f | 251 | #endif |
7100fe6c | 252 | set_priv_version(env, PRIV_VERSION_1_12_0); |
26b2bc58 | 253 | register_cpu_props(DEVICE(obj)); |
dc5bd18f MC |
254 | } |
255 | ||
094b072c AF |
256 | #if defined(TARGET_RISCV64) |
257 | static void rv64_base_cpu_init(Object *obj) | |
8903bf6e AF |
258 | { |
259 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
b55d7d34 | 260 | /* We set this in the realise function */ |
e91a7227 | 261 | set_misa(env, MXL_RV64, 0); |
26b2bc58 | 262 | register_cpu_props(DEVICE(obj)); |
18800095 AP |
263 | /* Set latest version of privileged specification */ |
264 | set_priv_version(env, PRIV_VERSION_1_12_0); | |
8903bf6e AF |
265 | } |
266 | ||
114baaca | 267 | static void rv64_sifive_u_cpu_init(Object *obj) |
dc5bd18f MC |
268 | { |
269 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
e91a7227 | 270 | set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); |
c66ffcd5 | 271 | register_cpu_props(DEVICE(obj)); |
c9a73910 | 272 | set_priv_version(env, PRIV_VERSION_1_10_0); |
dc5bd18f MC |
273 | } |
274 | ||
114baaca | 275 | static void rv64_sifive_e_cpu_init(Object *obj) |
36b80ad9 AF |
276 | { |
277 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
26b2bc58 AF |
278 | RISCVCPU *cpu = RISCV_CPU(obj); |
279 | ||
e91a7227 | 280 | set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); |
c66ffcd5 | 281 | register_cpu_props(DEVICE(obj)); |
36b80ad9 | 282 | set_priv_version(env, PRIV_VERSION_1_10_0); |
26b2bc58 | 283 | cpu->cfg.mmu = false; |
36b80ad9 | 284 | } |
332dab68 | 285 | |
95bd8daa CM |
286 | static void rv64_thead_c906_cpu_init(Object *obj) |
287 | { | |
288 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
289 | RISCVCPU *cpu = RISCV_CPU(obj); | |
290 | ||
291 | set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); | |
292 | set_priv_version(env, PRIV_VERSION_1_11_0); | |
293 | ||
294 | cpu->cfg.ext_g = true; | |
295 | cpu->cfg.ext_c = true; | |
296 | cpu->cfg.ext_u = true; | |
297 | cpu->cfg.ext_s = true; | |
298 | cpu->cfg.ext_icsr = true; | |
299 | cpu->cfg.ext_zfh = true; | |
300 | cpu->cfg.mmu = true; | |
301 | cpu->cfg.ext_xtheadba = true; | |
302 | cpu->cfg.ext_xtheadbb = true; | |
303 | cpu->cfg.ext_xtheadbs = true; | |
304 | cpu->cfg.ext_xtheadcmo = true; | |
305 | cpu->cfg.ext_xtheadcondmov = true; | |
306 | cpu->cfg.ext_xtheadfmemidx = true; | |
307 | cpu->cfg.ext_xtheadmac = true; | |
308 | cpu->cfg.ext_xtheadmemidx = true; | |
309 | cpu->cfg.ext_xtheadmempair = true; | |
310 | cpu->cfg.ext_xtheadsync = true; | |
311 | ||
312 | cpu->cfg.mvendorid = THEAD_VENDOR_ID; | |
313 | } | |
314 | ||
332dab68 FP |
315 | static void rv128_base_cpu_init(Object *obj) |
316 | { | |
317 | if (qemu_tcg_mttcg_enabled()) { | |
318 | /* Missing 128-bit aligned atomics */ | |
319 | error_report("128-bit RISC-V currently does not work with Multi " | |
320 | "Threaded TCG. Please use: -accel tcg,thread=single"); | |
321 | exit(EXIT_FAILURE); | |
322 | } | |
323 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
324 | /* We set this in the realise function */ | |
325 | set_misa(env, MXL_RV128, 0); | |
26b2bc58 | 326 | register_cpu_props(DEVICE(obj)); |
18800095 AP |
327 | /* Set latest version of privileged specification */ |
328 | set_priv_version(env, PRIV_VERSION_1_12_0); | |
332dab68 | 329 | } |
114baaca | 330 | #else |
094b072c AF |
331 | static void rv32_base_cpu_init(Object *obj) |
332 | { | |
333 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
334 | /* We set this in the realise function */ | |
e91a7227 | 335 | set_misa(env, MXL_RV32, 0); |
26b2bc58 | 336 | register_cpu_props(DEVICE(obj)); |
18800095 AP |
337 | /* Set latest version of privileged specification */ |
338 | set_priv_version(env, PRIV_VERSION_1_12_0); | |
094b072c AF |
339 | } |
340 | ||
114baaca AF |
341 | static void rv32_sifive_u_cpu_init(Object *obj) |
342 | { | |
343 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
e91a7227 | 344 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); |
c66ffcd5 | 345 | register_cpu_props(DEVICE(obj)); |
114baaca AF |
346 | set_priv_version(env, PRIV_VERSION_1_10_0); |
347 | } | |
36b80ad9 | 348 | |
114baaca AF |
349 | static void rv32_sifive_e_cpu_init(Object *obj) |
350 | { | |
351 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
26b2bc58 AF |
352 | RISCVCPU *cpu = RISCV_CPU(obj); |
353 | ||
e91a7227 | 354 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); |
c66ffcd5 | 355 | register_cpu_props(DEVICE(obj)); |
114baaca | 356 | set_priv_version(env, PRIV_VERSION_1_10_0); |
26b2bc58 | 357 | cpu->cfg.mmu = false; |
114baaca | 358 | } |
d8e72bd1 | 359 | |
e8905c6c | 360 | static void rv32_ibex_cpu_init(Object *obj) |
dc5bd18f MC |
361 | { |
362 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
26b2bc58 AF |
363 | RISCVCPU *cpu = RISCV_CPU(obj); |
364 | ||
e91a7227 | 365 | set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); |
c66ffcd5 | 366 | register_cpu_props(DEVICE(obj)); |
be2265c7 | 367 | set_priv_version(env, PRIV_VERSION_1_11_0); |
26b2bc58 AF |
368 | cpu->cfg.mmu = false; |
369 | cpu->cfg.epmp = true; | |
dc5bd18f MC |
370 | } |
371 | ||
2fdd2c09 | 372 | static void rv32_imafcu_nommu_cpu_init(Object *obj) |
d784733b CW |
373 | { |
374 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
26b2bc58 AF |
375 | RISCVCPU *cpu = RISCV_CPU(obj); |
376 | ||
e91a7227 | 377 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); |
c66ffcd5 | 378 | register_cpu_props(DEVICE(obj)); |
d784733b | 379 | set_priv_version(env, PRIV_VERSION_1_10_0); |
26b2bc58 | 380 | cpu->cfg.mmu = false; |
d784733b | 381 | } |
eab15862 | 382 | #endif |
dc5bd18f | 383 | |
10f1ca27 YJ |
384 | #if defined(CONFIG_KVM) |
385 | static void riscv_host_cpu_init(Object *obj) | |
386 | { | |
387 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
388 | #if defined(TARGET_RISCV32) | |
389 | set_misa(env, MXL_RV32, 0); | |
390 | #elif defined(TARGET_RISCV64) | |
391 | set_misa(env, MXL_RV64, 0); | |
392 | #endif | |
26b2bc58 | 393 | register_cpu_props(DEVICE(obj)); |
10f1ca27 YJ |
394 | } |
395 | #endif | |
396 | ||
dc5bd18f MC |
397 | static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) |
398 | { | |
399 | ObjectClass *oc; | |
400 | char *typename; | |
401 | char **cpuname; | |
402 | ||
403 | cpuname = g_strsplit(cpu_model, ",", 1); | |
404 | typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); | |
405 | oc = object_class_by_name(typename); | |
406 | g_strfreev(cpuname); | |
407 | g_free(typename); | |
408 | if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || | |
409 | object_class_is_abstract(oc)) { | |
410 | return NULL; | |
411 | } | |
412 | return oc; | |
413 | } | |
414 | ||
90c84c56 | 415 | static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) |
dc5bd18f MC |
416 | { |
417 | RISCVCPU *cpu = RISCV_CPU(cs); | |
418 | CPURISCVState *env = &cpu->env; | |
419 | int i; | |
420 | ||
df30e652 AF |
421 | #if !defined(CONFIG_USER_ONLY) |
422 | if (riscv_has_ext(env, RVH)) { | |
423 | qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); | |
424 | } | |
425 | #endif | |
90c84c56 | 426 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); |
dc5bd18f | 427 | #ifndef CONFIG_USER_ONLY |
665b90d8 RH |
428 | { |
429 | static const int dump_csrs[] = { | |
430 | CSR_MHARTID, | |
431 | CSR_MSTATUS, | |
432 | CSR_MSTATUSH, | |
bc7dca13 BM |
433 | /* |
434 | * CSR_SSTATUS is intentionally omitted here as its value | |
435 | * can be figured out by looking at CSR_MSTATUS | |
436 | */ | |
665b90d8 RH |
437 | CSR_HSTATUS, |
438 | CSR_VSSTATUS, | |
439 | CSR_MIP, | |
440 | CSR_MIE, | |
441 | CSR_MIDELEG, | |
442 | CSR_HIDELEG, | |
443 | CSR_MEDELEG, | |
444 | CSR_HEDELEG, | |
445 | CSR_MTVEC, | |
446 | CSR_STVEC, | |
447 | CSR_VSTVEC, | |
448 | CSR_MEPC, | |
449 | CSR_SEPC, | |
450 | CSR_VSEPC, | |
451 | CSR_MCAUSE, | |
452 | CSR_SCAUSE, | |
453 | CSR_VSCAUSE, | |
454 | CSR_MTVAL, | |
455 | CSR_STVAL, | |
456 | CSR_HTVAL, | |
457 | CSR_MTVAL2, | |
458 | CSR_MSCRATCH, | |
459 | CSR_SSCRATCH, | |
460 | CSR_SATP, | |
bd5594ca AB |
461 | CSR_MMTE, |
462 | CSR_UPMBASE, | |
463 | CSR_UPMMASK, | |
464 | CSR_SPMBASE, | |
465 | CSR_SPMMASK, | |
466 | CSR_MPMBASE, | |
467 | CSR_MPMMASK, | |
665b90d8 RH |
468 | }; |
469 | ||
470 | for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { | |
471 | int csrno = dump_csrs[i]; | |
472 | target_ulong val = 0; | |
473 | RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); | |
474 | ||
475 | /* | |
476 | * Rely on the smode, hmode, etc, predicates within csr.c | |
477 | * to do the filtering of the registers that are present. | |
478 | */ | |
479 | if (res == RISCV_EXCP_NONE) { | |
480 | qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", | |
481 | csr_ops[csrno].name, val); | |
482 | } | |
483 | } | |
df30e652 | 484 | } |
dc5bd18f MC |
485 | #endif |
486 | ||
487 | for (i = 0; i < 32; i++) { | |
e573a7f3 | 488 | qemu_fprintf(f, " %-8s " TARGET_FMT_lx, |
90c84c56 | 489 | riscv_int_regnames[i], env->gpr[i]); |
dc5bd18f | 490 | if ((i & 3) == 3) { |
90c84c56 | 491 | qemu_fprintf(f, "\n"); |
dc5bd18f MC |
492 | } |
493 | } | |
86ea1880 RH |
494 | if (flags & CPU_DUMP_FPU) { |
495 | for (i = 0; i < 32; i++) { | |
e573a7f3 | 496 | qemu_fprintf(f, " %-8s %016" PRIx64, |
90c84c56 | 497 | riscv_fpr_regnames[i], env->fpr[i]); |
86ea1880 | 498 | if ((i & 3) == 3) { |
90c84c56 | 499 | qemu_fprintf(f, "\n"); |
86ea1880 | 500 | } |
dc5bd18f MC |
501 | } |
502 | } | |
503 | } | |
504 | ||
505 | static void riscv_cpu_set_pc(CPUState *cs, vaddr value) | |
506 | { | |
507 | RISCVCPU *cpu = RISCV_CPU(cs); | |
508 | CPURISCVState *env = &cpu->env; | |
bf9e776e LZ |
509 | |
510 | if (env->xl == MXL_RV32) { | |
511 | env->pc = (int32_t)value; | |
512 | } else { | |
513 | env->pc = value; | |
514 | } | |
dc5bd18f MC |
515 | } |
516 | ||
e4fdf9df RH |
517 | static vaddr riscv_cpu_get_pc(CPUState *cs) |
518 | { | |
519 | RISCVCPU *cpu = RISCV_CPU(cs); | |
520 | CPURISCVState *env = &cpu->env; | |
521 | ||
522 | /* Match cpu_get_tb_cpu_state. */ | |
523 | if (env->xl == MXL_RV32) { | |
524 | return env->pc & UINT32_MAX; | |
525 | } | |
526 | return env->pc; | |
527 | } | |
528 | ||
04a37d4c RH |
529 | static void riscv_cpu_synchronize_from_tb(CPUState *cs, |
530 | const TranslationBlock *tb) | |
dc5bd18f MC |
531 | { |
532 | RISCVCPU *cpu = RISCV_CPU(cs); | |
533 | CPURISCVState *env = &cpu->env; | |
bf9e776e LZ |
534 | RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); |
535 | ||
536 | if (xl == MXL_RV32) { | |
fbf59aad | 537 | env->pc = (int32_t)tb_pc(tb); |
bf9e776e | 538 | } else { |
fbf59aad | 539 | env->pc = tb_pc(tb); |
bf9e776e | 540 | } |
dc5bd18f MC |
541 | } |
542 | ||
543 | static bool riscv_cpu_has_work(CPUState *cs) | |
544 | { | |
545 | #ifndef CONFIG_USER_ONLY | |
546 | RISCVCPU *cpu = RISCV_CPU(cs); | |
547 | CPURISCVState *env = &cpu->env; | |
548 | /* | |
549 | * Definition of the WFI instruction requires it to ignore the privilege | |
550 | * mode and delegation registers, but respect individual enables | |
551 | */ | |
8f42415f | 552 | return riscv_cpu_all_pending(env) != 0; |
dc5bd18f MC |
553 | #else |
554 | return true; | |
555 | #endif | |
556 | } | |
557 | ||
ad1e84f5 RH |
558 | static void riscv_restore_state_to_opc(CPUState *cs, |
559 | const TranslationBlock *tb, | |
560 | const uint64_t *data) | |
dc5bd18f | 561 | { |
ad1e84f5 RH |
562 | RISCVCPU *cpu = RISCV_CPU(cs); |
563 | CPURISCVState *env = &cpu->env; | |
bf9e776e | 564 | RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); |
ad1e84f5 | 565 | |
bf9e776e LZ |
566 | if (xl == MXL_RV32) { |
567 | env->pc = (int32_t)data[0]; | |
568 | } else { | |
569 | env->pc = data[0]; | |
570 | } | |
62cf0245 | 571 | env->bins = data[1]; |
dc5bd18f MC |
572 | } |
573 | ||
4fa485a7 | 574 | static void riscv_cpu_reset_hold(Object *obj) |
dc5bd18f | 575 | { |
43dc93af AP |
576 | #ifndef CONFIG_USER_ONLY |
577 | uint8_t iprio; | |
578 | int i, irq, rdzero; | |
579 | #endif | |
4fa485a7 | 580 | CPUState *cs = CPU(obj); |
dc5bd18f MC |
581 | RISCVCPU *cpu = RISCV_CPU(cs); |
582 | RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); | |
583 | CPURISCVState *env = &cpu->env; | |
584 | ||
4fa485a7 PM |
585 | if (mcc->parent_phases.hold) { |
586 | mcc->parent_phases.hold(obj); | |
587 | } | |
dc5bd18f | 588 | #ifndef CONFIG_USER_ONLY |
e91a7227 | 589 | env->misa_mxl = env->misa_mxl_max; |
dc5bd18f MC |
590 | env->priv = PRV_M; |
591 | env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); | |
92371bd9 RH |
592 | if (env->misa_mxl > MXL_RV32) { |
593 | /* | |
594 | * The reset status of SXL/UXL is undefined, but mstatus is WARL | |
595 | * and we must ensure that the value after init is valid for read. | |
596 | */ | |
597 | env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); | |
598 | env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); | |
5a2ae235 LZ |
599 | if (riscv_has_ext(env, RVH)) { |
600 | env->vsstatus = set_field(env->vsstatus, | |
601 | MSTATUS64_SXL, env->misa_mxl); | |
602 | env->vsstatus = set_field(env->vsstatus, | |
603 | MSTATUS64_UXL, env->misa_mxl); | |
604 | env->mstatus_hs = set_field(env->mstatus_hs, | |
605 | MSTATUS64_SXL, env->misa_mxl); | |
606 | env->mstatus_hs = set_field(env->mstatus_hs, | |
607 | MSTATUS64_UXL, env->misa_mxl); | |
608 | } | |
92371bd9 | 609 | } |
dc5bd18f | 610 | env->mcause = 0; |
881df35d | 611 | env->miclaim = MIP_SGEIP; |
dc5bd18f | 612 | env->pc = env->resetvec; |
62cf0245 | 613 | env->bins = 0; |
ec352d0c | 614 | env->two_stage_lookup = false; |
43dc93af AP |
615 | |
616 | /* Initialized default priorities of local interrupts. */ | |
617 | for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { | |
618 | iprio = riscv_cpu_default_priority(i); | |
619 | env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio; | |
620 | env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio; | |
621 | env->hviprio[i] = 0; | |
622 | } | |
623 | i = 0; | |
624 | while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) { | |
625 | if (!rdzero) { | |
626 | env->hviprio[irq] = env->miprio[irq]; | |
627 | } | |
628 | i++; | |
629 | } | |
4bbe8033 AB |
630 | /* mmte is supposed to have pm.current hardwired to 1 */ |
631 | env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); | |
dc5bd18f | 632 | #endif |
440544e1 | 633 | env->xl = riscv_cpu_mxl(env); |
40bfa5f6 | 634 | riscv_cpu_update_mask(env); |
330d2ae3 | 635 | cs->exception_index = RISCV_EXCP_NONE; |
c13b169f | 636 | env->load_res = -1; |
dc5bd18f | 637 | set_default_nan_mode(1, &env->fp_status); |
ad40be27 YJ |
638 | |
639 | #ifndef CONFIG_USER_ONLY | |
b6092544 BM |
640 | if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { |
641 | riscv_trigger_init(env); | |
642 | } | |
643 | ||
ad40be27 YJ |
644 | if (kvm_enabled()) { |
645 | kvm_riscv_reset_vcpu(cpu); | |
646 | } | |
647 | #endif | |
dc5bd18f MC |
648 | } |
649 | ||
650 | static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) | |
651 | { | |
5c5a47f1 | 652 | RISCVCPU *cpu = RISCV_CPU(s); |
db23e5d9 RH |
653 | |
654 | switch (riscv_cpu_mxl(&cpu->env)) { | |
655 | case MXL_RV32: | |
5c5a47f1 | 656 | info->print_insn = print_insn_riscv32; |
db23e5d9 RH |
657 | break; |
658 | case MXL_RV64: | |
5c5a47f1 | 659 | info->print_insn = print_insn_riscv64; |
db23e5d9 | 660 | break; |
332dab68 FP |
661 | case MXL_RV128: |
662 | info->print_insn = print_insn_riscv128; | |
663 | break; | |
db23e5d9 RH |
664 | default: |
665 | g_assert_not_reached(); | |
5c5a47f1 | 666 | } |
dc5bd18f MC |
667 | } |
668 | ||
5ab10952 DHB |
669 | /* |
670 | * Check consistency between chosen extensions while setting | |
671 | * cpu->cfg accordingly, doing a set_misa() in the end. | |
672 | */ | |
673 | static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) | |
674 | { | |
675 | CPURISCVState *env = &cpu->env; | |
676 | uint32_t ext = 0; | |
677 | ||
678 | /* Do some ISA extension error checking */ | |
679 | if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && | |
680 | cpu->cfg.ext_a && cpu->cfg.ext_f && | |
681 | cpu->cfg.ext_d && | |
682 | cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { | |
683 | warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); | |
684 | cpu->cfg.ext_i = true; | |
685 | cpu->cfg.ext_m = true; | |
686 | cpu->cfg.ext_a = true; | |
687 | cpu->cfg.ext_f = true; | |
688 | cpu->cfg.ext_d = true; | |
689 | cpu->cfg.ext_icsr = true; | |
690 | cpu->cfg.ext_ifencei = true; | |
691 | } | |
692 | ||
693 | if (cpu->cfg.ext_i && cpu->cfg.ext_e) { | |
694 | error_setg(errp, | |
695 | "I and E extensions are incompatible"); | |
696 | return; | |
697 | } | |
698 | ||
699 | if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { | |
700 | error_setg(errp, | |
701 | "Either I or E extension must be set"); | |
702 | return; | |
703 | } | |
704 | ||
705 | if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { | |
706 | error_setg(errp, | |
707 | "Setting S extension without U extension is illegal"); | |
708 | return; | |
709 | } | |
710 | ||
711 | if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { | |
712 | error_setg(errp, | |
713 | "H depends on an I base integer ISA with 32 x registers"); | |
714 | return; | |
715 | } | |
716 | ||
717 | if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { | |
718 | error_setg(errp, "H extension implicitly requires S-mode"); | |
719 | return; | |
720 | } | |
721 | ||
722 | if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { | |
723 | error_setg(errp, "F extension requires Zicsr"); | |
724 | return; | |
725 | } | |
726 | ||
727 | if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { | |
728 | error_setg(errp, "Zawrs extension requires A extension"); | |
729 | return; | |
730 | } | |
731 | ||
1d2cb5a8 WL |
732 | if (cpu->cfg.ext_zfh) { |
733 | cpu->cfg.ext_zfhmin = true; | |
734 | } | |
735 | ||
736 | if (cpu->cfg.ext_zfhmin && !cpu->cfg.ext_f) { | |
5ab10952 DHB |
737 | error_setg(errp, "Zfh/Zfhmin extensions require F extension"); |
738 | return; | |
739 | } | |
740 | ||
741 | if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { | |
742 | error_setg(errp, "D extension requires F extension"); | |
743 | return; | |
744 | } | |
745 | ||
e7f0a803 WL |
746 | /* The V vector extension depends on the Zve64d extension */ |
747 | if (cpu->cfg.ext_v) { | |
748 | cpu->cfg.ext_zve64d = true; | |
749 | } | |
750 | ||
751 | /* The Zve64d extension depends on the Zve64f extension */ | |
752 | if (cpu->cfg.ext_zve64d) { | |
753 | cpu->cfg.ext_zve64f = true; | |
754 | } | |
755 | ||
756 | /* The Zve64f extension depends on the Zve32f extension */ | |
757 | if (cpu->cfg.ext_zve64f) { | |
758 | cpu->cfg.ext_zve32f = true; | |
759 | } | |
760 | ||
761 | if (cpu->cfg.ext_zve64d && !cpu->cfg.ext_d) { | |
762 | error_setg(errp, "Zve64d/V extensions require D extension"); | |
5ab10952 DHB |
763 | return; |
764 | } | |
765 | ||
e7f0a803 | 766 | if (cpu->cfg.ext_zve32f && !cpu->cfg.ext_f) { |
5ab10952 DHB |
767 | error_setg(errp, "Zve32f/Zve64f extensions require F extension"); |
768 | return; | |
769 | } | |
770 | ||
2e60f9ec WL |
771 | if (cpu->cfg.ext_zvfh) { |
772 | cpu->cfg.ext_zvfhmin = true; | |
773 | } | |
774 | ||
775 | if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { | |
776 | error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension"); | |
777 | return; | |
778 | } | |
779 | ||
780 | if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { | |
781 | error_setg(errp, "Zvfh extensions requires Zfhmin extension"); | |
782 | return; | |
783 | } | |
784 | ||
5ab10952 | 785 | /* Set the ISA extensions, checks should have happened above */ |
a0d805f0 WL |
786 | if (cpu->cfg.ext_zhinx) { |
787 | cpu->cfg.ext_zhinxmin = true; | |
788 | } | |
789 | ||
790 | if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) { | |
5ab10952 DHB |
791 | cpu->cfg.ext_zfinx = true; |
792 | } | |
793 | ||
794 | if (cpu->cfg.ext_zfinx) { | |
795 | if (!cpu->cfg.ext_icsr) { | |
796 | error_setg(errp, "Zfinx extension requires Zicsr"); | |
797 | return; | |
798 | } | |
799 | if (cpu->cfg.ext_f) { | |
800 | error_setg(errp, | |
801 | "Zfinx cannot be supported together with F extension"); | |
802 | return; | |
803 | } | |
804 | } | |
805 | ||
806 | if (cpu->cfg.ext_zk) { | |
807 | cpu->cfg.ext_zkn = true; | |
808 | cpu->cfg.ext_zkr = true; | |
809 | cpu->cfg.ext_zkt = true; | |
810 | } | |
811 | ||
812 | if (cpu->cfg.ext_zkn) { | |
813 | cpu->cfg.ext_zbkb = true; | |
814 | cpu->cfg.ext_zbkc = true; | |
815 | cpu->cfg.ext_zbkx = true; | |
816 | cpu->cfg.ext_zkne = true; | |
817 | cpu->cfg.ext_zknd = true; | |
818 | cpu->cfg.ext_zknh = true; | |
819 | } | |
820 | ||
821 | if (cpu->cfg.ext_zks) { | |
822 | cpu->cfg.ext_zbkb = true; | |
823 | cpu->cfg.ext_zbkc = true; | |
824 | cpu->cfg.ext_zbkx = true; | |
825 | cpu->cfg.ext_zksed = true; | |
826 | cpu->cfg.ext_zksh = true; | |
827 | } | |
828 | ||
829 | if (cpu->cfg.ext_i) { | |
830 | ext |= RVI; | |
831 | } | |
832 | if (cpu->cfg.ext_e) { | |
833 | ext |= RVE; | |
834 | } | |
835 | if (cpu->cfg.ext_m) { | |
836 | ext |= RVM; | |
837 | } | |
838 | if (cpu->cfg.ext_a) { | |
839 | ext |= RVA; | |
840 | } | |
841 | if (cpu->cfg.ext_f) { | |
842 | ext |= RVF; | |
843 | } | |
844 | if (cpu->cfg.ext_d) { | |
845 | ext |= RVD; | |
846 | } | |
847 | if (cpu->cfg.ext_c) { | |
848 | ext |= RVC; | |
849 | } | |
850 | if (cpu->cfg.ext_s) { | |
851 | ext |= RVS; | |
852 | } | |
853 | if (cpu->cfg.ext_u) { | |
854 | ext |= RVU; | |
855 | } | |
856 | if (cpu->cfg.ext_h) { | |
857 | ext |= RVH; | |
858 | } | |
859 | if (cpu->cfg.ext_v) { | |
860 | int vext_version = VEXT_VERSION_1_00_0; | |
861 | ext |= RVV; | |
862 | if (!is_power_of_2(cpu->cfg.vlen)) { | |
863 | error_setg(errp, | |
864 | "Vector extension VLEN must be power of 2"); | |
865 | return; | |
866 | } | |
867 | if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { | |
868 | error_setg(errp, | |
869 | "Vector extension implementation only supports VLEN " | |
870 | "in the range [128, %d]", RV_VLEN_MAX); | |
871 | return; | |
872 | } | |
873 | if (!is_power_of_2(cpu->cfg.elen)) { | |
874 | error_setg(errp, | |
875 | "Vector extension ELEN must be power of 2"); | |
876 | return; | |
877 | } | |
878 | if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { | |
879 | error_setg(errp, | |
880 | "Vector extension implementation only supports ELEN " | |
881 | "in the range [8, 64]"); | |
882 | return; | |
883 | } | |
884 | if (cpu->cfg.vext_spec) { | |
885 | if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { | |
886 | vext_version = VEXT_VERSION_1_00_0; | |
887 | } else { | |
888 | error_setg(errp, | |
889 | "Unsupported vector spec version '%s'", | |
890 | cpu->cfg.vext_spec); | |
891 | return; | |
892 | } | |
893 | } else { | |
894 | qemu_log("vector version is not specified, " | |
895 | "use the default value v1.0\n"); | |
896 | } | |
897 | set_vext_version(env, vext_version); | |
898 | } | |
899 | if (cpu->cfg.ext_j) { | |
900 | ext |= RVJ; | |
901 | } | |
902 | ||
903 | set_misa(env, env->misa_mxl, ext); | |
904 | } | |
905 | ||
dc5bd18f MC |
906 | static void riscv_cpu_realize(DeviceState *dev, Error **errp) |
907 | { | |
908 | CPUState *cs = CPU(dev); | |
c4e95030 AF |
909 | RISCVCPU *cpu = RISCV_CPU(dev); |
910 | CPURISCVState *env = &cpu->env; | |
dc5bd18f | 911 | RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); |
1191be09 | 912 | CPUClass *cc = CPU_CLASS(mcc); |
9a1f054d | 913 | int i, priv_version = -1; |
dc5bd18f MC |
914 | Error *local_err = NULL; |
915 | ||
916 | cpu_exec_realizefn(cs, &local_err); | |
917 | if (local_err != NULL) { | |
918 | error_propagate(errp, local_err); | |
919 | return; | |
920 | } | |
921 | ||
c4e95030 | 922 | if (cpu->cfg.priv_spec) { |
7100fe6c AP |
923 | if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { |
924 | priv_version = PRIV_VERSION_1_12_0; | |
925 | } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { | |
e3147506 AF |
926 | priv_version = PRIV_VERSION_1_11_0; |
927 | } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { | |
c4e95030 | 928 | priv_version = PRIV_VERSION_1_10_0; |
c4e95030 AF |
929 | } else { |
930 | error_setg(errp, | |
931 | "Unsupported privilege spec version '%s'", | |
932 | cpu->cfg.priv_spec); | |
933 | return; | |
934 | } | |
935 | } | |
936 | ||
18800095 | 937 | if (priv_version >= PRIV_VERSION_1_10_0) { |
a8b37120 | 938 | set_priv_version(env, priv_version); |
a8b37120 | 939 | } |
c4e95030 | 940 | |
9a1f054d AP |
941 | /* Force disable extensions if priv spec version does not match */ |
942 | for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { | |
943 | if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && | |
944 | (env->priv_ver < isa_edata_arr[i].min_version)) { | |
945 | isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); | |
946 | #ifndef CONFIG_USER_ONLY | |
877a3a37 BM |
947 | warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx |
948 | " because privilege spec version does not match", | |
949 | isa_edata_arr[i].name, env->mhartid); | |
9a1f054d AP |
950 | #else |
951 | warn_report("disabling %s extension because " | |
952 | "privilege spec version does not match", | |
953 | isa_edata_arr[i].name); | |
954 | #endif | |
955 | } | |
956 | } | |
957 | ||
c4e95030 | 958 | if (cpu->cfg.mmu) { |
f87adf23 | 959 | riscv_set_feature(env, RISCV_FEATURE_MMU); |
c4e95030 AF |
960 | } |
961 | ||
962 | if (cpu->cfg.pmp) { | |
f87adf23 | 963 | riscv_set_feature(env, RISCV_FEATURE_PMP); |
5da9514e HW |
964 | |
965 | /* | |
966 | * Enhanced PMP should only be available | |
967 | * on harts with PMP support | |
968 | */ | |
969 | if (cpu->cfg.epmp) { | |
f87adf23 | 970 | riscv_set_feature(env, RISCV_FEATURE_EPMP); |
5da9514e | 971 | } |
c4e95030 AF |
972 | } |
973 | ||
1acdb3b0 BM |
974 | if (cpu->cfg.debug) { |
975 | riscv_set_feature(env, RISCV_FEATURE_DEBUG); | |
976 | } | |
977 | ||
73f6ed97 | 978 | |
43888c2f AP |
979 | #ifndef CONFIG_USER_ONLY |
980 | if (cpu->cfg.ext_sstc) { | |
981 | riscv_timer_init(cpu); | |
982 | } | |
983 | #endif /* CONFIG_USER_ONLY */ | |
984 | ||
e91a7227 RH |
985 | /* Validate that MISA_MXL is set properly. */ |
986 | switch (env->misa_mxl_max) { | |
987 | #ifdef TARGET_RISCV64 | |
988 | case MXL_RV64: | |
332dab68 | 989 | case MXL_RV128: |
6c3a9247 | 990 | cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; |
332dab68 | 991 | break; |
e91a7227 RH |
992 | #endif |
993 | case MXL_RV32: | |
1191be09 | 994 | cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; |
e91a7227 RH |
995 | break; |
996 | default: | |
997 | g_assert_not_reached(); | |
998 | } | |
999 | assert(env->misa_mxl_max == env->misa_mxl); | |
1000 | ||
5ab10952 DHB |
1001 | riscv_cpu_validate_set_extensions(cpu, &local_err); |
1002 | if (local_err != NULL) { | |
1003 | error_propagate(errp, local_err); | |
1004 | return; | |
b55d7d34 AF |
1005 | } |
1006 | ||
14664483 AP |
1007 | #ifndef CONFIG_USER_ONLY |
1008 | if (cpu->cfg.pmu_num) { | |
1009 | if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { | |
1010 | cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, | |
1011 | riscv_pmu_timer_cb, cpu); | |
1012 | } | |
1013 | } | |
1014 | #endif | |
1015 | ||
5371f5cd JW |
1016 | riscv_cpu_register_gdb_regs_for_features(cs); |
1017 | ||
dc5bd18f MC |
1018 | qemu_init_vcpu(cs); |
1019 | cpu_reset(cs); | |
1020 | ||
1021 | mcc->parent_realize(dev, errp); | |
1022 | } | |
1023 | ||
0f0b70ee AF |
1024 | #ifndef CONFIG_USER_ONLY |
1025 | static void riscv_cpu_set_irq(void *opaque, int irq, int level) | |
1026 | { | |
1027 | RISCVCPU *cpu = RISCV_CPU(opaque); | |
cd032fe7 | 1028 | CPURISCVState *env = &cpu->env; |
0f0b70ee | 1029 | |
cd032fe7 AP |
1030 | if (irq < IRQ_LOCAL_MAX) { |
1031 | switch (irq) { | |
1032 | case IRQ_U_SOFT: | |
1033 | case IRQ_S_SOFT: | |
1034 | case IRQ_VS_SOFT: | |
1035 | case IRQ_M_SOFT: | |
1036 | case IRQ_U_TIMER: | |
1037 | case IRQ_S_TIMER: | |
1038 | case IRQ_VS_TIMER: | |
1039 | case IRQ_M_TIMER: | |
1040 | case IRQ_U_EXT: | |
cd032fe7 AP |
1041 | case IRQ_VS_EXT: |
1042 | case IRQ_M_EXT: | |
8b5c807b | 1043 | if (kvm_enabled()) { |
cd032fe7 | 1044 | kvm_riscv_set_irq(cpu, irq, level); |
8b5c807b | 1045 | } else { |
cd032fe7 | 1046 | riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); |
8b5c807b | 1047 | } |
cd032fe7 | 1048 | break; |
33fe584f AF |
1049 | case IRQ_S_EXT: |
1050 | if (kvm_enabled()) { | |
1051 | kvm_riscv_set_irq(cpu, irq, level); | |
1052 | } else { | |
1053 | env->external_seip = level; | |
1054 | riscv_cpu_update_mip(cpu, 1 << irq, | |
1055 | BOOL_TO_MASK(level | env->software_seip)); | |
1056 | } | |
1057 | break; | |
cd032fe7 AP |
1058 | default: |
1059 | g_assert_not_reached(); | |
2b650fbb | 1060 | } |
cd032fe7 AP |
1061 | } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { |
1062 | /* Require H-extension for handling guest local interrupts */ | |
1063 | if (!riscv_has_ext(env, RVH)) { | |
1064 | g_assert_not_reached(); | |
1065 | } | |
1066 | ||
1067 | /* Compute bit position in HGEIP CSR */ | |
1068 | irq = irq - IRQ_LOCAL_MAX + 1; | |
1069 | if (env->geilen < irq) { | |
1070 | g_assert_not_reached(); | |
1071 | } | |
1072 | ||
1073 | /* Update HGEIP CSR */ | |
1074 | env->hgeip &= ~((target_ulong)1 << irq); | |
1075 | if (level) { | |
1076 | env->hgeip |= (target_ulong)1 << irq; | |
1077 | } | |
1078 | ||
1079 | /* Update mip.SGEIP bit */ | |
1080 | riscv_cpu_update_mip(cpu, MIP_SGEIP, | |
1081 | BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); | |
1082 | } else { | |
0f0b70ee AF |
1083 | g_assert_not_reached(); |
1084 | } | |
1085 | } | |
1086 | #endif /* CONFIG_USER_ONLY */ | |
1087 | ||
dc5bd18f MC |
1088 | static void riscv_cpu_init(Object *obj) |
1089 | { | |
dc5bd18f MC |
1090 | RISCVCPU *cpu = RISCV_CPU(obj); |
1091 | ||
26b2bc58 AF |
1092 | cpu->cfg.ext_ifencei = true; |
1093 | cpu->cfg.ext_icsr = true; | |
1094 | cpu->cfg.mmu = true; | |
1095 | cpu->cfg.pmp = true; | |
1096 | ||
7506ed90 | 1097 | cpu_set_cpustate_pointers(cpu); |
0f0b70ee AF |
1098 | |
1099 | #ifndef CONFIG_USER_ONLY | |
cd032fe7 AP |
1100 | qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, |
1101 | IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); | |
0f0b70ee | 1102 | #endif /* CONFIG_USER_ONLY */ |
dc5bd18f MC |
1103 | } |
1104 | ||
26b2bc58 | 1105 | static Property riscv_cpu_extensions[] = { |
9d3d60b7 | 1106 | /* Defaults for standard extensions */ |
b55d7d34 AF |
1107 | DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), |
1108 | DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), | |
1d398ab9 | 1109 | DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), |
b55d7d34 AF |
1110 | DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), |
1111 | DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), | |
1112 | DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), | |
1113 | DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), | |
1114 | DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), | |
1115 | DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), | |
1116 | DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), | |
9ec6622d | 1117 | DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), |
07cb270a | 1118 | DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), |
18d6d89e | 1119 | DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), |
14664483 | 1120 | DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), |
9d3d60b7 AF |
1121 | DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), |
1122 | DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), | |
4696f0ab | 1123 | DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), |
260b594d | 1124 | DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), |
13fb8c7b | 1125 | DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), |
e5237730 | 1126 | DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), |
2fc1b44d | 1127 | DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), |
bfefe406 | 1128 | DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), |
9d3d60b7 AF |
1129 | DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), |
1130 | DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), | |
43888c2f | 1131 | DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true), |
9d3d60b7 AF |
1132 | |
1133 | DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), | |
9ec6622d FC |
1134 | DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), |
1135 | DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), | |
1136 | DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), | |
9d3d60b7 | 1137 | |
c5d77ddd | 1138 | DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), |
2bacb224 | 1139 | DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), |
bbce8ba8 | 1140 | DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), |
2bacb224 | 1141 | |
0643c12e VG |
1142 | DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), |
1143 | DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), | |
1144 | DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), | |
cf7ed971 WL |
1145 | DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false), |
1146 | DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false), | |
1147 | DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false), | |
0643c12e | 1148 | DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), |
cf7ed971 WL |
1149 | DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false), |
1150 | DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false), | |
1151 | DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false), | |
1152 | DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false), | |
1153 | DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false), | |
1154 | DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false), | |
1155 | DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false), | |
1156 | DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false), | |
1157 | DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), | |
1158 | DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), | |
dfdb46a3 | 1159 | |
6b1accef WL |
1160 | DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), |
1161 | DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), | |
1162 | DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), | |
1163 | DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), | |
1164 | ||
6d00ffad WL |
1165 | DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), |
1166 | ||
0d429bd2 | 1167 | /* Vendor-specific custom extensions */ |
c9410a68 | 1168 | DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), |
426c0491 | 1169 | DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), |
fa134585 | 1170 | DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), |
49a7f3aa | 1171 | DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), |
32909338 | 1172 | DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), |
d4d90115 | 1173 | DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false), |
578086ba | 1174 | DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false), |
b8a5832b | 1175 | DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), |
45f9df86 | 1176 | DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false), |
af99aa72 | 1177 | DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false), |
134c3ffa | 1178 | DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), |
0d429bd2 PT |
1179 | DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), |
1180 | ||
dfdb46a3 | 1181 | /* These are experimental so mark with 'x-' */ |
0ee9a4e5 | 1182 | DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), |
a44da25a | 1183 | /* ePMP 0.9.3 */ |
5da9514e | 1184 | DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), |
dc9acc9c AP |
1185 | DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), |
1186 | DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), | |
5da9514e | 1187 | |
26b2bc58 AF |
1188 | DEFINE_PROP_END_OF_LIST(), |
1189 | }; | |
1190 | ||
c66ffcd5 DHB |
1191 | /* |
1192 | * Register CPU props based on env.misa_ext. If a non-zero | |
1193 | * value was set, register only the required cpu->cfg.ext_* | |
1194 | * properties and leave. env.misa_ext = 0 means that we want | |
1195 | * all the default properties to be registered. | |
1196 | */ | |
26b2bc58 AF |
1197 | static void register_cpu_props(DeviceState *dev) |
1198 | { | |
c66ffcd5 DHB |
1199 | RISCVCPU *cpu = RISCV_CPU(OBJECT(dev)); |
1200 | uint32_t misa_ext = cpu->env.misa_ext; | |
26b2bc58 AF |
1201 | Property *prop; |
1202 | ||
c66ffcd5 DHB |
1203 | /* |
1204 | * If misa_ext is not zero, set cfg properties now to | |
1205 | * allow them to be read during riscv_cpu_realize() | |
1206 | * later on. | |
1207 | */ | |
1208 | if (cpu->env.misa_ext != 0) { | |
1209 | cpu->cfg.ext_i = misa_ext & RVI; | |
1210 | cpu->cfg.ext_e = misa_ext & RVE; | |
1211 | cpu->cfg.ext_m = misa_ext & RVM; | |
1212 | cpu->cfg.ext_a = misa_ext & RVA; | |
1213 | cpu->cfg.ext_f = misa_ext & RVF; | |
1214 | cpu->cfg.ext_d = misa_ext & RVD; | |
1215 | cpu->cfg.ext_v = misa_ext & RVV; | |
1216 | cpu->cfg.ext_c = misa_ext & RVC; | |
1217 | cpu->cfg.ext_s = misa_ext & RVS; | |
1218 | cpu->cfg.ext_u = misa_ext & RVU; | |
1219 | cpu->cfg.ext_h = misa_ext & RVH; | |
1220 | cpu->cfg.ext_j = misa_ext & RVJ; | |
1221 | ||
1222 | /* | |
1223 | * We don't want to set the default riscv_cpu_extensions | |
1224 | * in this case. | |
1225 | */ | |
1226 | return; | |
1227 | } | |
1228 | ||
26b2bc58 AF |
1229 | for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { |
1230 | qdev_property_add_static(dev, prop); | |
1231 | } | |
1232 | } | |
1233 | ||
1234 | static Property riscv_cpu_properties[] = { | |
1235 | DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), | |
1236 | ||
1237 | DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), | |
1238 | DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), | |
1239 | DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), | |
1240 | ||
277b210d AF |
1241 | #ifndef CONFIG_USER_ONLY |
1242 | DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), | |
1243 | #endif | |
a4a9a443 TO |
1244 | |
1245 | DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), | |
b8312675 | 1246 | |
1247 | DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), | |
1ad3f9bd | 1248 | DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), |
c4e95030 AF |
1249 | DEFINE_PROP_END_OF_LIST(), |
1250 | }; | |
1251 | ||
edf64786 SP |
1252 | static gchar *riscv_gdb_arch_name(CPUState *cs) |
1253 | { | |
1254 | RISCVCPU *cpu = RISCV_CPU(cs); | |
1255 | CPURISCVState *env = &cpu->env; | |
1256 | ||
db23e5d9 RH |
1257 | switch (riscv_cpu_mxl(env)) { |
1258 | case MXL_RV32: | |
edf64786 | 1259 | return g_strdup("riscv:rv32"); |
db23e5d9 | 1260 | case MXL_RV64: |
332dab68 | 1261 | case MXL_RV128: |
edf64786 | 1262 | return g_strdup("riscv:rv64"); |
db23e5d9 RH |
1263 | default: |
1264 | g_assert_not_reached(); | |
edf64786 SP |
1265 | } |
1266 | } | |
1267 | ||
b93777e1 BM |
1268 | static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) |
1269 | { | |
1270 | RISCVCPU *cpu = RISCV_CPU(cs); | |
1271 | ||
1272 | if (strcmp(xmlname, "riscv-csr.xml") == 0) { | |
1273 | return cpu->dyn_csr_xml; | |
719d3561 HW |
1274 | } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { |
1275 | return cpu->dyn_vreg_xml; | |
b93777e1 BM |
1276 | } |
1277 | ||
1278 | return NULL; | |
1279 | } | |
1280 | ||
8b80bd28 PMD |
1281 | #ifndef CONFIG_USER_ONLY |
1282 | #include "hw/core/sysemu-cpu-ops.h" | |
1283 | ||
1284 | static const struct SysemuCPUOps riscv_sysemu_ops = { | |
08928c6d | 1285 | .get_phys_page_debug = riscv_cpu_get_phys_page_debug, |
715e3c1a PMD |
1286 | .write_elf64_note = riscv_cpu_write_elf64_note, |
1287 | .write_elf32_note = riscv_cpu_write_elf32_note, | |
feece4d0 | 1288 | .legacy_vmsd = &vmstate_riscv_cpu, |
8b80bd28 PMD |
1289 | }; |
1290 | #endif | |
1291 | ||
78271684 CF |
1292 | #include "hw/core/tcg-cpu-ops.h" |
1293 | ||
11906557 | 1294 | static const struct TCGCPUOps riscv_tcg_ops = { |
78271684 CF |
1295 | .initialize = riscv_translate_init, |
1296 | .synchronize_from_tb = riscv_cpu_synchronize_from_tb, | |
ad1e84f5 | 1297 | .restore_state_to_opc = riscv_restore_state_to_opc, |
78271684 CF |
1298 | |
1299 | #ifndef CONFIG_USER_ONLY | |
263e2ab2 | 1300 | .tlb_fill = riscv_cpu_tlb_fill, |
17b3c353 | 1301 | .cpu_exec_interrupt = riscv_cpu_exec_interrupt, |
78271684 CF |
1302 | .do_interrupt = riscv_cpu_do_interrupt, |
1303 | .do_transaction_failed = riscv_cpu_do_transaction_failed, | |
1304 | .do_unaligned_access = riscv_cpu_do_unaligned_access, | |
b5f6379d BM |
1305 | .debug_excp_handler = riscv_cpu_debug_excp_handler, |
1306 | .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, | |
1307 | .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, | |
78271684 CF |
1308 | #endif /* !CONFIG_USER_ONLY */ |
1309 | }; | |
1310 | ||
dc5bd18f MC |
1311 | static void riscv_cpu_class_init(ObjectClass *c, void *data) |
1312 | { | |
1313 | RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); | |
1314 | CPUClass *cc = CPU_CLASS(c); | |
1315 | DeviceClass *dc = DEVICE_CLASS(c); | |
4fa485a7 | 1316 | ResettableClass *rc = RESETTABLE_CLASS(c); |
dc5bd18f | 1317 | |
41fbbba7 MZ |
1318 | device_class_set_parent_realize(dc, riscv_cpu_realize, |
1319 | &mcc->parent_realize); | |
dc5bd18f | 1320 | |
4fa485a7 PM |
1321 | resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL, |
1322 | &mcc->parent_phases); | |
dc5bd18f MC |
1323 | |
1324 | cc->class_by_name = riscv_cpu_class_by_name; | |
1325 | cc->has_work = riscv_cpu_has_work; | |
dc5bd18f MC |
1326 | cc->dump_state = riscv_cpu_dump_state; |
1327 | cc->set_pc = riscv_cpu_set_pc; | |
e4fdf9df | 1328 | cc->get_pc = riscv_cpu_get_pc; |
dc5bd18f MC |
1329 | cc->gdb_read_register = riscv_cpu_gdb_read_register; |
1330 | cc->gdb_write_register = riscv_cpu_gdb_write_register; | |
5371f5cd | 1331 | cc->gdb_num_core_regs = 33; |
dc5bd18f MC |
1332 | cc->gdb_stop_before_watchpoint = true; |
1333 | cc->disas_set_info = riscv_cpu_disas_set_info; | |
8a4ca3c1 | 1334 | #ifndef CONFIG_USER_ONLY |
8b80bd28 | 1335 | cc->sysemu_ops = &riscv_sysemu_ops; |
dc5bd18f | 1336 | #endif |
edf64786 | 1337 | cc->gdb_arch_name = riscv_gdb_arch_name; |
b93777e1 | 1338 | cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; |
78271684 | 1339 | cc->tcg_ops = &riscv_tcg_ops; |
6a3d2e7c | 1340 | |
4f67d30b | 1341 | device_class_set_props(dc, riscv_cpu_properties); |
dc5bd18f MC |
1342 | } |
1343 | ||
a775398b AP |
1344 | static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) |
1345 | { | |
1346 | char *old = *isa_str; | |
1347 | char *new = *isa_str; | |
1348 | int i; | |
1349 | ||
a775398b | 1350 | for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { |
9a1f054d AP |
1351 | if (isa_edata_arr[i].multi_letter && |
1352 | isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { | |
a775398b AP |
1353 | new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); |
1354 | g_free(old); | |
1355 | old = new; | |
1356 | } | |
1357 | } | |
1358 | ||
1359 | *isa_str = new; | |
1360 | } | |
1361 | ||
dc5bd18f MC |
1362 | char *riscv_isa_string(RISCVCPU *cpu) |
1363 | { | |
1364 | int i; | |
0e2c3770 | 1365 | const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); |
d1fd31f8 MC |
1366 | char *isa_str = g_new(char, maxlen); |
1367 | char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); | |
0e2c3770 TO |
1368 | for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { |
1369 | if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { | |
1370 | *p++ = qemu_tolower(riscv_single_letter_exts[i]); | |
dc5bd18f MC |
1371 | } |
1372 | } | |
d1fd31f8 | 1373 | *p = '\0'; |
a4a9a443 TO |
1374 | if (!cpu->cfg.short_isa_string) { |
1375 | riscv_isa_string_ext(cpu, &isa_str, maxlen); | |
1376 | } | |
d1fd31f8 | 1377 | return isa_str; |
dc5bd18f MC |
1378 | } |
1379 | ||
eab15862 | 1380 | static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) |
dc5bd18f | 1381 | { |
eab15862 MC |
1382 | ObjectClass *class_a = (ObjectClass *)a; |
1383 | ObjectClass *class_b = (ObjectClass *)b; | |
1384 | const char *name_a, *name_b; | |
dc5bd18f | 1385 | |
eab15862 MC |
1386 | name_a = object_class_get_name(class_a); |
1387 | name_b = object_class_get_name(class_b); | |
1388 | return strcmp(name_a, name_b); | |
dc5bd18f MC |
1389 | } |
1390 | ||
eab15862 | 1391 | static void riscv_cpu_list_entry(gpointer data, gpointer user_data) |
dc5bd18f | 1392 | { |
eab15862 MC |
1393 | const char *typename = object_class_get_name(OBJECT_CLASS(data)); |
1394 | int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); | |
dc5bd18f | 1395 | |
0442428a | 1396 | qemu_printf("%.*s\n", len, typename); |
eab15862 | 1397 | } |
dc5bd18f | 1398 | |
0442428a | 1399 | void riscv_cpu_list(void) |
eab15862 | 1400 | { |
eab15862 MC |
1401 | GSList *list; |
1402 | ||
1403 | list = object_class_get_list(TYPE_RISCV_CPU, false); | |
1404 | list = g_slist_sort(list, riscv_cpu_list_compare); | |
0442428a | 1405 | g_slist_foreach(list, riscv_cpu_list_entry, NULL); |
eab15862 | 1406 | g_slist_free(list); |
dc5bd18f MC |
1407 | } |
1408 | ||
eab15862 MC |
1409 | #define DEFINE_CPU(type_name, initfn) \ |
1410 | { \ | |
1411 | .name = type_name, \ | |
1412 | .parent = TYPE_RISCV_CPU, \ | |
1413 | .instance_init = initfn \ | |
1414 | } | |
1415 | ||
1416 | static const TypeInfo riscv_cpu_type_infos[] = { | |
1417 | { | |
1418 | .name = TYPE_RISCV_CPU, | |
1419 | .parent = TYPE_CPU, | |
1420 | .instance_size = sizeof(RISCVCPU), | |
5de5b99b | 1421 | .instance_align = __alignof__(RISCVCPU), |
eab15862 MC |
1422 | .instance_init = riscv_cpu_init, |
1423 | .abstract = true, | |
1424 | .class_size = sizeof(RISCVCPUClass), | |
1425 | .class_init = riscv_cpu_class_init, | |
1426 | }, | |
1427 | DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), | |
10f1ca27 YJ |
1428 | #if defined(CONFIG_KVM) |
1429 | DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), | |
1430 | #endif | |
eab15862 | 1431 | #if defined(TARGET_RISCV32) |
094b072c | 1432 | DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), |
e8905c6c | 1433 | DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), |
114baaca | 1434 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), |
2fdd2c09 | 1435 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), |
114baaca | 1436 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), |
eab15862 | 1437 | #elif defined(TARGET_RISCV64) |
094b072c | 1438 | DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), |
114baaca AF |
1439 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), |
1440 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), | |
6ddc7069 | 1441 | DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), |
95bd8daa | 1442 | DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), |
332dab68 | 1443 | DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), |
eab15862 MC |
1444 | #endif |
1445 | }; | |
1446 | ||
1447 | DEFINE_TYPES(riscv_cpu_type_infos) |