]>
Commit | Line | Data |
---|---|---|
dc5bd18f MC |
1 | /* |
2 | * QEMU RISC-V CPU | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
0442428a | 21 | #include "qemu/qemu-print.h" |
856dfd8a | 22 | #include "qemu/ctype.h" |
dc5bd18f MC |
23 | #include "qemu/log.h" |
24 | #include "cpu.h" | |
f7697f0e | 25 | #include "internals.h" |
dc5bd18f MC |
26 | #include "exec/exec-all.h" |
27 | #include "qapi/error.h" | |
b55d7d34 | 28 | #include "qemu/error-report.h" |
c4e95030 | 29 | #include "hw/qdev-properties.h" |
dc5bd18f | 30 | #include "migration/vmstate.h" |
135b03cb | 31 | #include "fpu/softfloat-helpers.h" |
ad40be27 YJ |
32 | #include "sysemu/kvm.h" |
33 | #include "kvm_riscv.h" | |
dc5bd18f MC |
34 | |
35 | /* RISC-V CPU definitions */ | |
36 | ||
79f86934 | 37 | static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG"; |
dc5bd18f MC |
38 | |
39 | const char * const riscv_int_regnames[] = { | |
a9f37afa AP |
40 | "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", |
41 | "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", | |
42 | "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", | |
43 | "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", | |
44 | "x28/t3", "x29/t4", "x30/t5", "x31/t6" | |
dc5bd18f MC |
45 | }; |
46 | ||
2b547084 FP |
47 | const char * const riscv_int_regnamesh[] = { |
48 | "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", | |
49 | "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", | |
50 | "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", | |
51 | "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", | |
52 | "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", | |
53 | "x30h/t5h", "x31h/t6h" | |
54 | }; | |
55 | ||
dc5bd18f | 56 | const char * const riscv_fpr_regnames[] = { |
a9f37afa AP |
57 | "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", |
58 | "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", | |
59 | "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", | |
60 | "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", | |
61 | "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", | |
62 | "f30/ft10", "f31/ft11" | |
dc5bd18f MC |
63 | }; |
64 | ||
9a575d33 | 65 | static const char * const riscv_excp_names[] = { |
dc5bd18f MC |
66 | "misaligned_fetch", |
67 | "fault_fetch", | |
68 | "illegal_instruction", | |
69 | "breakpoint", | |
70 | "misaligned_load", | |
71 | "fault_load", | |
72 | "misaligned_store", | |
73 | "fault_store", | |
74 | "user_ecall", | |
75 | "supervisor_ecall", | |
76 | "hypervisor_ecall", | |
77 | "machine_ecall", | |
78 | "exec_page_fault", | |
79 | "load_page_fault", | |
80 | "reserved", | |
fd990e86 | 81 | "store_page_fault", |
ab67a1d0 AF |
82 | "reserved", |
83 | "reserved", | |
84 | "reserved", | |
85 | "reserved", | |
86 | "guest_exec_page_fault", | |
87 | "guest_load_page_fault", | |
88 | "reserved", | |
fd990e86 | 89 | "guest_store_page_fault", |
dc5bd18f MC |
90 | }; |
91 | ||
9a575d33 | 92 | static const char * const riscv_intr_names[] = { |
dc5bd18f MC |
93 | "u_software", |
94 | "s_software", | |
205377f8 | 95 | "vs_software", |
dc5bd18f MC |
96 | "m_software", |
97 | "u_timer", | |
98 | "s_timer", | |
205377f8 | 99 | "vs_timer", |
dc5bd18f MC |
100 | "m_timer", |
101 | "u_external", | |
6cfcf775 | 102 | "s_external", |
205377f8 | 103 | "vs_external", |
dc5bd18f | 104 | "m_external", |
426f0348 MC |
105 | "reserved", |
106 | "reserved", | |
107 | "reserved", | |
108 | "reserved" | |
dc5bd18f MC |
109 | }; |
110 | ||
c51a3f5d YJ |
111 | const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) |
112 | { | |
113 | if (async) { | |
114 | return (cause < ARRAY_SIZE(riscv_intr_names)) ? | |
115 | riscv_intr_names[cause] : "(unknown)"; | |
116 | } else { | |
117 | return (cause < ARRAY_SIZE(riscv_excp_names)) ? | |
118 | riscv_excp_names[cause] : "(unknown)"; | |
119 | } | |
120 | } | |
121 | ||
e91a7227 | 122 | static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) |
dc5bd18f | 123 | { |
e91a7227 RH |
124 | env->misa_mxl_max = env->misa_mxl = mxl; |
125 | env->misa_ext_mask = env->misa_ext = ext; | |
dc5bd18f MC |
126 | } |
127 | ||
c9a73910 | 128 | static void set_priv_version(CPURISCVState *env, int priv_ver) |
dc5bd18f | 129 | { |
dc5bd18f MC |
130 | env->priv_ver = priv_ver; |
131 | } | |
132 | ||
32931383 LZ |
133 | static void set_vext_version(CPURISCVState *env, int vext_ver) |
134 | { | |
135 | env->vext_ver = vext_ver; | |
136 | } | |
137 | ||
dc5bd18f MC |
138 | static void set_feature(CPURISCVState *env, int feature) |
139 | { | |
140 | env->features |= (1ULL << feature); | |
141 | } | |
142 | ||
01e723bf | 143 | static void set_resetvec(CPURISCVState *env, target_ulong resetvec) |
dc5bd18f MC |
144 | { |
145 | #ifndef CONFIG_USER_ONLY | |
146 | env->resetvec = resetvec; | |
147 | #endif | |
148 | } | |
149 | ||
150 | static void riscv_any_cpu_init(Object *obj) | |
151 | { | |
152 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
3820602f | 153 | #if defined(TARGET_RISCV32) |
e91a7227 | 154 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); |
3820602f | 155 | #elif defined(TARGET_RISCV64) |
e91a7227 | 156 | set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); |
3820602f | 157 | #endif |
c9a73910 | 158 | set_priv_version(env, PRIV_VERSION_1_11_0); |
dc5bd18f MC |
159 | } |
160 | ||
094b072c AF |
161 | #if defined(TARGET_RISCV64) |
162 | static void rv64_base_cpu_init(Object *obj) | |
8903bf6e AF |
163 | { |
164 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
b55d7d34 | 165 | /* We set this in the realise function */ |
e91a7227 | 166 | set_misa(env, MXL_RV64, 0); |
8903bf6e AF |
167 | } |
168 | ||
114baaca | 169 | static void rv64_sifive_u_cpu_init(Object *obj) |
dc5bd18f MC |
170 | { |
171 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
e91a7227 | 172 | set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); |
c9a73910 | 173 | set_priv_version(env, PRIV_VERSION_1_10_0); |
dc5bd18f MC |
174 | } |
175 | ||
114baaca | 176 | static void rv64_sifive_e_cpu_init(Object *obj) |
36b80ad9 AF |
177 | { |
178 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
e91a7227 | 179 | set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); |
36b80ad9 | 180 | set_priv_version(env, PRIV_VERSION_1_10_0); |
36b80ad9 AF |
181 | qdev_prop_set_bit(DEVICE(obj), "mmu", false); |
182 | } | |
332dab68 FP |
183 | |
184 | static void rv128_base_cpu_init(Object *obj) | |
185 | { | |
186 | if (qemu_tcg_mttcg_enabled()) { | |
187 | /* Missing 128-bit aligned atomics */ | |
188 | error_report("128-bit RISC-V currently does not work with Multi " | |
189 | "Threaded TCG. Please use: -accel tcg,thread=single"); | |
190 | exit(EXIT_FAILURE); | |
191 | } | |
192 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
193 | /* We set this in the realise function */ | |
194 | set_misa(env, MXL_RV128, 0); | |
195 | } | |
114baaca | 196 | #else |
094b072c AF |
197 | static void rv32_base_cpu_init(Object *obj) |
198 | { | |
199 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
200 | /* We set this in the realise function */ | |
e91a7227 | 201 | set_misa(env, MXL_RV32, 0); |
094b072c AF |
202 | } |
203 | ||
114baaca AF |
204 | static void rv32_sifive_u_cpu_init(Object *obj) |
205 | { | |
206 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
e91a7227 | 207 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); |
114baaca AF |
208 | set_priv_version(env, PRIV_VERSION_1_10_0); |
209 | } | |
36b80ad9 | 210 | |
114baaca AF |
211 | static void rv32_sifive_e_cpu_init(Object *obj) |
212 | { | |
213 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
e91a7227 | 214 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); |
114baaca AF |
215 | set_priv_version(env, PRIV_VERSION_1_10_0); |
216 | qdev_prop_set_bit(DEVICE(obj), "mmu", false); | |
217 | } | |
d8e72bd1 | 218 | |
e8905c6c | 219 | static void rv32_ibex_cpu_init(Object *obj) |
dc5bd18f MC |
220 | { |
221 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
e91a7227 | 222 | set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); |
c9a73910 | 223 | set_priv_version(env, PRIV_VERSION_1_10_0); |
8be6971b | 224 | qdev_prop_set_bit(DEVICE(obj), "mmu", false); |
ed6eebaa | 225 | qdev_prop_set_bit(DEVICE(obj), "x-epmp", true); |
dc5bd18f MC |
226 | } |
227 | ||
2fdd2c09 | 228 | static void rv32_imafcu_nommu_cpu_init(Object *obj) |
d784733b CW |
229 | { |
230 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
e91a7227 | 231 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); |
d784733b CW |
232 | set_priv_version(env, PRIV_VERSION_1_10_0); |
233 | set_resetvec(env, DEFAULT_RSTVEC); | |
8be6971b | 234 | qdev_prop_set_bit(DEVICE(obj), "mmu", false); |
d784733b | 235 | } |
eab15862 | 236 | #endif |
dc5bd18f MC |
237 | |
238 | static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) | |
239 | { | |
240 | ObjectClass *oc; | |
241 | char *typename; | |
242 | char **cpuname; | |
243 | ||
244 | cpuname = g_strsplit(cpu_model, ",", 1); | |
245 | typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); | |
246 | oc = object_class_by_name(typename); | |
247 | g_strfreev(cpuname); | |
248 | g_free(typename); | |
249 | if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || | |
250 | object_class_is_abstract(oc)) { | |
251 | return NULL; | |
252 | } | |
253 | return oc; | |
254 | } | |
255 | ||
90c84c56 | 256 | static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) |
dc5bd18f MC |
257 | { |
258 | RISCVCPU *cpu = RISCV_CPU(cs); | |
259 | CPURISCVState *env = &cpu->env; | |
260 | int i; | |
261 | ||
df30e652 AF |
262 | #if !defined(CONFIG_USER_ONLY) |
263 | if (riscv_has_ext(env, RVH)) { | |
264 | qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); | |
265 | } | |
266 | #endif | |
90c84c56 | 267 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); |
dc5bd18f | 268 | #ifndef CONFIG_USER_ONLY |
665b90d8 RH |
269 | { |
270 | static const int dump_csrs[] = { | |
271 | CSR_MHARTID, | |
272 | CSR_MSTATUS, | |
273 | CSR_MSTATUSH, | |
274 | CSR_HSTATUS, | |
275 | CSR_VSSTATUS, | |
276 | CSR_MIP, | |
277 | CSR_MIE, | |
278 | CSR_MIDELEG, | |
279 | CSR_HIDELEG, | |
280 | CSR_MEDELEG, | |
281 | CSR_HEDELEG, | |
282 | CSR_MTVEC, | |
283 | CSR_STVEC, | |
284 | CSR_VSTVEC, | |
285 | CSR_MEPC, | |
286 | CSR_SEPC, | |
287 | CSR_VSEPC, | |
288 | CSR_MCAUSE, | |
289 | CSR_SCAUSE, | |
290 | CSR_VSCAUSE, | |
291 | CSR_MTVAL, | |
292 | CSR_STVAL, | |
293 | CSR_HTVAL, | |
294 | CSR_MTVAL2, | |
295 | CSR_MSCRATCH, | |
296 | CSR_SSCRATCH, | |
297 | CSR_SATP, | |
bd5594ca AB |
298 | CSR_MMTE, |
299 | CSR_UPMBASE, | |
300 | CSR_UPMMASK, | |
301 | CSR_SPMBASE, | |
302 | CSR_SPMMASK, | |
303 | CSR_MPMBASE, | |
304 | CSR_MPMMASK, | |
665b90d8 RH |
305 | }; |
306 | ||
307 | for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { | |
308 | int csrno = dump_csrs[i]; | |
309 | target_ulong val = 0; | |
310 | RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); | |
311 | ||
312 | /* | |
313 | * Rely on the smode, hmode, etc, predicates within csr.c | |
314 | * to do the filtering of the registers that are present. | |
315 | */ | |
316 | if (res == RISCV_EXCP_NONE) { | |
317 | qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", | |
318 | csr_ops[csrno].name, val); | |
319 | } | |
320 | } | |
df30e652 | 321 | } |
dc5bd18f MC |
322 | #endif |
323 | ||
324 | for (i = 0; i < 32; i++) { | |
e573a7f3 | 325 | qemu_fprintf(f, " %-8s " TARGET_FMT_lx, |
90c84c56 | 326 | riscv_int_regnames[i], env->gpr[i]); |
dc5bd18f | 327 | if ((i & 3) == 3) { |
90c84c56 | 328 | qemu_fprintf(f, "\n"); |
dc5bd18f MC |
329 | } |
330 | } | |
86ea1880 RH |
331 | if (flags & CPU_DUMP_FPU) { |
332 | for (i = 0; i < 32; i++) { | |
e573a7f3 | 333 | qemu_fprintf(f, " %-8s %016" PRIx64, |
90c84c56 | 334 | riscv_fpr_regnames[i], env->fpr[i]); |
86ea1880 | 335 | if ((i & 3) == 3) { |
90c84c56 | 336 | qemu_fprintf(f, "\n"); |
86ea1880 | 337 | } |
dc5bd18f MC |
338 | } |
339 | } | |
340 | } | |
341 | ||
342 | static void riscv_cpu_set_pc(CPUState *cs, vaddr value) | |
343 | { | |
344 | RISCVCPU *cpu = RISCV_CPU(cs); | |
345 | CPURISCVState *env = &cpu->env; | |
346 | env->pc = value; | |
347 | } | |
348 | ||
04a37d4c RH |
349 | static void riscv_cpu_synchronize_from_tb(CPUState *cs, |
350 | const TranslationBlock *tb) | |
dc5bd18f MC |
351 | { |
352 | RISCVCPU *cpu = RISCV_CPU(cs); | |
353 | CPURISCVState *env = &cpu->env; | |
354 | env->pc = tb->pc; | |
355 | } | |
356 | ||
357 | static bool riscv_cpu_has_work(CPUState *cs) | |
358 | { | |
359 | #ifndef CONFIG_USER_ONLY | |
360 | RISCVCPU *cpu = RISCV_CPU(cs); | |
361 | CPURISCVState *env = &cpu->env; | |
362 | /* | |
363 | * Definition of the WFI instruction requires it to ignore the privilege | |
364 | * mode and delegation registers, but respect individual enables | |
365 | */ | |
7ec5d303 | 366 | return (env->mip & env->mie) != 0; |
dc5bd18f MC |
367 | #else |
368 | return true; | |
369 | #endif | |
370 | } | |
371 | ||
372 | void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, | |
373 | target_ulong *data) | |
374 | { | |
375 | env->pc = data[0]; | |
376 | } | |
377 | ||
781c67ca | 378 | static void riscv_cpu_reset(DeviceState *dev) |
dc5bd18f | 379 | { |
781c67ca | 380 | CPUState *cs = CPU(dev); |
dc5bd18f MC |
381 | RISCVCPU *cpu = RISCV_CPU(cs); |
382 | RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); | |
383 | CPURISCVState *env = &cpu->env; | |
384 | ||
781c67ca | 385 | mcc->parent_reset(dev); |
dc5bd18f | 386 | #ifndef CONFIG_USER_ONLY |
e91a7227 | 387 | env->misa_mxl = env->misa_mxl_max; |
dc5bd18f MC |
388 | env->priv = PRV_M; |
389 | env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); | |
92371bd9 RH |
390 | if (env->misa_mxl > MXL_RV32) { |
391 | /* | |
392 | * The reset status of SXL/UXL is undefined, but mstatus is WARL | |
393 | * and we must ensure that the value after init is valid for read. | |
394 | */ | |
395 | env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); | |
396 | env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); | |
397 | } | |
dc5bd18f MC |
398 | env->mcause = 0; |
399 | env->pc = env->resetvec; | |
ec352d0c | 400 | env->two_stage_lookup = false; |
4bbe8033 AB |
401 | /* mmte is supposed to have pm.current hardwired to 1 */ |
402 | env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); | |
dc5bd18f | 403 | #endif |
330d2ae3 | 404 | cs->exception_index = RISCV_EXCP_NONE; |
c13b169f | 405 | env->load_res = -1; |
dc5bd18f | 406 | set_default_nan_mode(1, &env->fp_status); |
ad40be27 YJ |
407 | |
408 | #ifndef CONFIG_USER_ONLY | |
409 | if (kvm_enabled()) { | |
410 | kvm_riscv_reset_vcpu(cpu); | |
411 | } | |
412 | #endif | |
dc5bd18f MC |
413 | } |
414 | ||
415 | static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) | |
416 | { | |
5c5a47f1 | 417 | RISCVCPU *cpu = RISCV_CPU(s); |
db23e5d9 RH |
418 | |
419 | switch (riscv_cpu_mxl(&cpu->env)) { | |
420 | case MXL_RV32: | |
5c5a47f1 | 421 | info->print_insn = print_insn_riscv32; |
db23e5d9 RH |
422 | break; |
423 | case MXL_RV64: | |
5c5a47f1 | 424 | info->print_insn = print_insn_riscv64; |
db23e5d9 | 425 | break; |
332dab68 FP |
426 | case MXL_RV128: |
427 | info->print_insn = print_insn_riscv128; | |
428 | break; | |
db23e5d9 RH |
429 | default: |
430 | g_assert_not_reached(); | |
5c5a47f1 | 431 | } |
dc5bd18f MC |
432 | } |
433 | ||
434 | static void riscv_cpu_realize(DeviceState *dev, Error **errp) | |
435 | { | |
436 | CPUState *cs = CPU(dev); | |
c4e95030 AF |
437 | RISCVCPU *cpu = RISCV_CPU(dev); |
438 | CPURISCVState *env = &cpu->env; | |
dc5bd18f | 439 | RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); |
a8b37120 | 440 | int priv_version = 0; |
dc5bd18f MC |
441 | Error *local_err = NULL; |
442 | ||
443 | cpu_exec_realizefn(cs, &local_err); | |
444 | if (local_err != NULL) { | |
445 | error_propagate(errp, local_err); | |
446 | return; | |
447 | } | |
448 | ||
c4e95030 | 449 | if (cpu->cfg.priv_spec) { |
e3147506 AF |
450 | if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { |
451 | priv_version = PRIV_VERSION_1_11_0; | |
452 | } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { | |
c4e95030 | 453 | priv_version = PRIV_VERSION_1_10_0; |
c4e95030 AF |
454 | } else { |
455 | error_setg(errp, | |
456 | "Unsupported privilege spec version '%s'", | |
457 | cpu->cfg.priv_spec); | |
458 | return; | |
459 | } | |
460 | } | |
461 | ||
a8b37120 LZ |
462 | if (priv_version) { |
463 | set_priv_version(env, priv_version); | |
464 | } else if (!env->priv_ver) { | |
465 | set_priv_version(env, PRIV_VERSION_1_11_0); | |
466 | } | |
c4e95030 AF |
467 | |
468 | if (cpu->cfg.mmu) { | |
469 | set_feature(env, RISCV_FEATURE_MMU); | |
470 | } | |
471 | ||
472 | if (cpu->cfg.pmp) { | |
473 | set_feature(env, RISCV_FEATURE_PMP); | |
5da9514e HW |
474 | |
475 | /* | |
476 | * Enhanced PMP should only be available | |
477 | * on harts with PMP support | |
478 | */ | |
479 | if (cpu->cfg.epmp) { | |
480 | set_feature(env, RISCV_FEATURE_EPMP); | |
481 | } | |
c4e95030 AF |
482 | } |
483 | ||
73f6ed97 BM |
484 | set_resetvec(env, cpu->cfg.resetvec); |
485 | ||
e91a7227 RH |
486 | /* Validate that MISA_MXL is set properly. */ |
487 | switch (env->misa_mxl_max) { | |
488 | #ifdef TARGET_RISCV64 | |
489 | case MXL_RV64: | |
490 | break; | |
332dab68 FP |
491 | case MXL_RV128: |
492 | break; | |
e91a7227 RH |
493 | #endif |
494 | case MXL_RV32: | |
495 | break; | |
496 | default: | |
497 | g_assert_not_reached(); | |
498 | } | |
499 | assert(env->misa_mxl_max == env->misa_mxl); | |
500 | ||
501 | /* If only MISA_EXT is unset for misa, then set it from properties */ | |
502 | if (env->misa_ext == 0) { | |
503 | uint32_t ext = 0; | |
504 | ||
b55d7d34 AF |
505 | /* Do some ISA extension error checking */ |
506 | if (cpu->cfg.ext_i && cpu->cfg.ext_e) { | |
507 | error_setg(errp, | |
508 | "I and E extensions are incompatible"); | |
509 | return; | |
510 | } | |
511 | ||
bdddd446 AF |
512 | if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { |
513 | error_setg(errp, | |
514 | "Either I or E extension must be set"); | |
515 | return; | |
516 | } | |
517 | ||
b55d7d34 AF |
518 | if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & |
519 | cpu->cfg.ext_a & cpu->cfg.ext_f & | |
520 | cpu->cfg.ext_d)) { | |
521 | warn_report("Setting G will also set IMAFD"); | |
522 | cpu->cfg.ext_i = true; | |
523 | cpu->cfg.ext_m = true; | |
524 | cpu->cfg.ext_a = true; | |
525 | cpu->cfg.ext_f = true; | |
526 | cpu->cfg.ext_d = true; | |
527 | } | |
528 | ||
529 | /* Set the ISA extensions, checks should have happened above */ | |
530 | if (cpu->cfg.ext_i) { | |
e91a7227 | 531 | ext |= RVI; |
b55d7d34 AF |
532 | } |
533 | if (cpu->cfg.ext_e) { | |
e91a7227 | 534 | ext |= RVE; |
b55d7d34 AF |
535 | } |
536 | if (cpu->cfg.ext_m) { | |
e91a7227 | 537 | ext |= RVM; |
b55d7d34 AF |
538 | } |
539 | if (cpu->cfg.ext_a) { | |
e91a7227 | 540 | ext |= RVA; |
b55d7d34 AF |
541 | } |
542 | if (cpu->cfg.ext_f) { | |
e91a7227 | 543 | ext |= RVF; |
b55d7d34 AF |
544 | } |
545 | if (cpu->cfg.ext_d) { | |
e91a7227 | 546 | ext |= RVD; |
b55d7d34 AF |
547 | } |
548 | if (cpu->cfg.ext_c) { | |
e91a7227 | 549 | ext |= RVC; |
b55d7d34 AF |
550 | } |
551 | if (cpu->cfg.ext_s) { | |
e91a7227 | 552 | ext |= RVS; |
b55d7d34 AF |
553 | } |
554 | if (cpu->cfg.ext_u) { | |
e91a7227 | 555 | ext |= RVU; |
b55d7d34 | 556 | } |
c9eefe05 | 557 | if (cpu->cfg.ext_h) { |
e91a7227 | 558 | ext |= RVH; |
c9eefe05 | 559 | } |
6bf91617 | 560 | if (cpu->cfg.ext_v) { |
9ec6622d | 561 | int vext_version = VEXT_VERSION_1_00_0; |
e91a7227 | 562 | ext |= RVV; |
6bf91617 LZ |
563 | if (!is_power_of_2(cpu->cfg.vlen)) { |
564 | error_setg(errp, | |
565 | "Vector extension VLEN must be power of 2"); | |
566 | return; | |
567 | } | |
568 | if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { | |
569 | error_setg(errp, | |
570 | "Vector extension implementation only supports VLEN " | |
571 | "in the range [128, %d]", RV_VLEN_MAX); | |
572 | return; | |
573 | } | |
574 | if (!is_power_of_2(cpu->cfg.elen)) { | |
575 | error_setg(errp, | |
576 | "Vector extension ELEN must be power of 2"); | |
577 | return; | |
578 | } | |
579 | if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) { | |
580 | error_setg(errp, | |
581 | "Vector extension implementation only supports ELEN " | |
582 | "in the range [8, 64]"); | |
583 | return; | |
584 | } | |
585 | if (cpu->cfg.vext_spec) { | |
9ec6622d FC |
586 | if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { |
587 | vext_version = VEXT_VERSION_1_00_0; | |
6bf91617 LZ |
588 | } else { |
589 | error_setg(errp, | |
590 | "Unsupported vector spec version '%s'", | |
591 | cpu->cfg.vext_spec); | |
592 | return; | |
593 | } | |
594 | } else { | |
cba42d61 | 595 | qemu_log("vector version is not specified, " |
9ec6622d | 596 | "use the default value v1.0\n"); |
6bf91617 LZ |
597 | } |
598 | set_vext_version(env, vext_version); | |
599 | } | |
0ee9a4e5 AB |
600 | if (cpu->cfg.ext_j) { |
601 | ext |= RVJ; | |
602 | } | |
b55d7d34 | 603 | |
e91a7227 | 604 | set_misa(env, env->misa_mxl, ext); |
b55d7d34 AF |
605 | } |
606 | ||
5371f5cd JW |
607 | riscv_cpu_register_gdb_regs_for_features(cs); |
608 | ||
dc5bd18f MC |
609 | qemu_init_vcpu(cs); |
610 | cpu_reset(cs); | |
611 | ||
612 | mcc->parent_realize(dev, errp); | |
613 | } | |
614 | ||
0f0b70ee AF |
615 | #ifndef CONFIG_USER_ONLY |
616 | static void riscv_cpu_set_irq(void *opaque, int irq, int level) | |
617 | { | |
618 | RISCVCPU *cpu = RISCV_CPU(opaque); | |
619 | ||
620 | switch (irq) { | |
621 | case IRQ_U_SOFT: | |
622 | case IRQ_S_SOFT: | |
623 | case IRQ_VS_SOFT: | |
624 | case IRQ_M_SOFT: | |
625 | case IRQ_U_TIMER: | |
626 | case IRQ_S_TIMER: | |
627 | case IRQ_VS_TIMER: | |
628 | case IRQ_M_TIMER: | |
629 | case IRQ_U_EXT: | |
630 | case IRQ_S_EXT: | |
631 | case IRQ_VS_EXT: | |
632 | case IRQ_M_EXT: | |
2b650fbb YJ |
633 | if (kvm_enabled()) { |
634 | kvm_riscv_set_irq(cpu, irq, level); | |
635 | } else { | |
636 | riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); | |
637 | } | |
0f0b70ee AF |
638 | break; |
639 | default: | |
640 | g_assert_not_reached(); | |
641 | } | |
642 | } | |
643 | #endif /* CONFIG_USER_ONLY */ | |
644 | ||
dc5bd18f MC |
645 | static void riscv_cpu_init(Object *obj) |
646 | { | |
dc5bd18f MC |
647 | RISCVCPU *cpu = RISCV_CPU(obj); |
648 | ||
7506ed90 | 649 | cpu_set_cpustate_pointers(cpu); |
0f0b70ee AF |
650 | |
651 | #ifndef CONFIG_USER_ONLY | |
652 | qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 12); | |
653 | #endif /* CONFIG_USER_ONLY */ | |
dc5bd18f MC |
654 | } |
655 | ||
c4e95030 | 656 | static Property riscv_cpu_properties[] = { |
9d3d60b7 | 657 | /* Defaults for standard extensions */ |
b55d7d34 AF |
658 | DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), |
659 | DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), | |
660 | DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true), | |
661 | DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), | |
662 | DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), | |
663 | DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), | |
664 | DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), | |
665 | DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), | |
666 | DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), | |
667 | DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), | |
9ec6622d | 668 | DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), |
07cb270a | 669 | DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), |
9d3d60b7 AF |
670 | DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), |
671 | DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), | |
672 | DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), | |
13fb8c7b | 673 | DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), |
e5237730 | 674 | DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), |
9d3d60b7 AF |
675 | DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), |
676 | DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), | |
677 | ||
678 | DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), | |
9ec6622d FC |
679 | DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), |
680 | DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), | |
681 | DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), | |
9d3d60b7 | 682 | |
0643c12e VG |
683 | DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), |
684 | DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), | |
685 | DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), | |
686 | DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), | |
dfdb46a3 PT |
687 | |
688 | /* These are experimental so mark with 'x-' */ | |
0ee9a4e5 | 689 | DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), |
a44da25a | 690 | /* ePMP 0.9.3 */ |
5da9514e HW |
691 | DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), |
692 | ||
9b4c9b2b | 693 | DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), |
c4e95030 AF |
694 | DEFINE_PROP_END_OF_LIST(), |
695 | }; | |
696 | ||
edf64786 SP |
697 | static gchar *riscv_gdb_arch_name(CPUState *cs) |
698 | { | |
699 | RISCVCPU *cpu = RISCV_CPU(cs); | |
700 | CPURISCVState *env = &cpu->env; | |
701 | ||
db23e5d9 RH |
702 | switch (riscv_cpu_mxl(env)) { |
703 | case MXL_RV32: | |
edf64786 | 704 | return g_strdup("riscv:rv32"); |
db23e5d9 | 705 | case MXL_RV64: |
332dab68 | 706 | case MXL_RV128: |
edf64786 | 707 | return g_strdup("riscv:rv64"); |
db23e5d9 RH |
708 | default: |
709 | g_assert_not_reached(); | |
edf64786 SP |
710 | } |
711 | } | |
712 | ||
b93777e1 BM |
713 | static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) |
714 | { | |
715 | RISCVCPU *cpu = RISCV_CPU(cs); | |
716 | ||
717 | if (strcmp(xmlname, "riscv-csr.xml") == 0) { | |
718 | return cpu->dyn_csr_xml; | |
719d3561 HW |
719 | } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { |
720 | return cpu->dyn_vreg_xml; | |
b93777e1 BM |
721 | } |
722 | ||
723 | return NULL; | |
724 | } | |
725 | ||
8b80bd28 PMD |
726 | #ifndef CONFIG_USER_ONLY |
727 | #include "hw/core/sysemu-cpu-ops.h" | |
728 | ||
729 | static const struct SysemuCPUOps riscv_sysemu_ops = { | |
08928c6d | 730 | .get_phys_page_debug = riscv_cpu_get_phys_page_debug, |
715e3c1a PMD |
731 | .write_elf64_note = riscv_cpu_write_elf64_note, |
732 | .write_elf32_note = riscv_cpu_write_elf32_note, | |
feece4d0 | 733 | .legacy_vmsd = &vmstate_riscv_cpu, |
8b80bd28 PMD |
734 | }; |
735 | #endif | |
736 | ||
78271684 CF |
737 | #include "hw/core/tcg-cpu-ops.h" |
738 | ||
11906557 | 739 | static const struct TCGCPUOps riscv_tcg_ops = { |
78271684 CF |
740 | .initialize = riscv_translate_init, |
741 | .synchronize_from_tb = riscv_cpu_synchronize_from_tb, | |
78271684 CF |
742 | |
743 | #ifndef CONFIG_USER_ONLY | |
263e2ab2 | 744 | .tlb_fill = riscv_cpu_tlb_fill, |
17b3c353 | 745 | .cpu_exec_interrupt = riscv_cpu_exec_interrupt, |
78271684 CF |
746 | .do_interrupt = riscv_cpu_do_interrupt, |
747 | .do_transaction_failed = riscv_cpu_do_transaction_failed, | |
748 | .do_unaligned_access = riscv_cpu_do_unaligned_access, | |
749 | #endif /* !CONFIG_USER_ONLY */ | |
750 | }; | |
751 | ||
dc5bd18f MC |
752 | static void riscv_cpu_class_init(ObjectClass *c, void *data) |
753 | { | |
754 | RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); | |
755 | CPUClass *cc = CPU_CLASS(c); | |
756 | DeviceClass *dc = DEVICE_CLASS(c); | |
757 | ||
41fbbba7 MZ |
758 | device_class_set_parent_realize(dc, riscv_cpu_realize, |
759 | &mcc->parent_realize); | |
dc5bd18f | 760 | |
781c67ca | 761 | device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset); |
dc5bd18f MC |
762 | |
763 | cc->class_by_name = riscv_cpu_class_by_name; | |
764 | cc->has_work = riscv_cpu_has_work; | |
dc5bd18f MC |
765 | cc->dump_state = riscv_cpu_dump_state; |
766 | cc->set_pc = riscv_cpu_set_pc; | |
dc5bd18f MC |
767 | cc->gdb_read_register = riscv_cpu_gdb_read_register; |
768 | cc->gdb_write_register = riscv_cpu_gdb_write_register; | |
5371f5cd JW |
769 | cc->gdb_num_core_regs = 33; |
770 | #if defined(TARGET_RISCV32) | |
771 | cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; | |
772 | #elif defined(TARGET_RISCV64) | |
773 | cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; | |
774 | #endif | |
dc5bd18f MC |
775 | cc->gdb_stop_before_watchpoint = true; |
776 | cc->disas_set_info = riscv_cpu_disas_set_info; | |
8a4ca3c1 | 777 | #ifndef CONFIG_USER_ONLY |
8b80bd28 | 778 | cc->sysemu_ops = &riscv_sysemu_ops; |
dc5bd18f | 779 | #endif |
edf64786 | 780 | cc->gdb_arch_name = riscv_gdb_arch_name; |
b93777e1 | 781 | cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; |
78271684 | 782 | cc->tcg_ops = &riscv_tcg_ops; |
6a3d2e7c | 783 | |
4f67d30b | 784 | device_class_set_props(dc, riscv_cpu_properties); |
dc5bd18f MC |
785 | } |
786 | ||
dc5bd18f MC |
787 | char *riscv_isa_string(RISCVCPU *cpu) |
788 | { | |
789 | int i; | |
d1fd31f8 MC |
790 | const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1; |
791 | char *isa_str = g_new(char, maxlen); | |
792 | char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); | |
dc5bd18f | 793 | for (i = 0; i < sizeof(riscv_exts); i++) { |
e91a7227 | 794 | if (cpu->env.misa_ext & RV(riscv_exts[i])) { |
d1fd31f8 | 795 | *p++ = qemu_tolower(riscv_exts[i]); |
dc5bd18f MC |
796 | } |
797 | } | |
d1fd31f8 MC |
798 | *p = '\0'; |
799 | return isa_str; | |
dc5bd18f MC |
800 | } |
801 | ||
eab15862 | 802 | static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) |
dc5bd18f | 803 | { |
eab15862 MC |
804 | ObjectClass *class_a = (ObjectClass *)a; |
805 | ObjectClass *class_b = (ObjectClass *)b; | |
806 | const char *name_a, *name_b; | |
dc5bd18f | 807 | |
eab15862 MC |
808 | name_a = object_class_get_name(class_a); |
809 | name_b = object_class_get_name(class_b); | |
810 | return strcmp(name_a, name_b); | |
dc5bd18f MC |
811 | } |
812 | ||
eab15862 | 813 | static void riscv_cpu_list_entry(gpointer data, gpointer user_data) |
dc5bd18f | 814 | { |
eab15862 MC |
815 | const char *typename = object_class_get_name(OBJECT_CLASS(data)); |
816 | int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); | |
dc5bd18f | 817 | |
0442428a | 818 | qemu_printf("%.*s\n", len, typename); |
eab15862 | 819 | } |
dc5bd18f | 820 | |
0442428a | 821 | void riscv_cpu_list(void) |
eab15862 | 822 | { |
eab15862 MC |
823 | GSList *list; |
824 | ||
825 | list = object_class_get_list(TYPE_RISCV_CPU, false); | |
826 | list = g_slist_sort(list, riscv_cpu_list_compare); | |
0442428a | 827 | g_slist_foreach(list, riscv_cpu_list_entry, NULL); |
eab15862 | 828 | g_slist_free(list); |
dc5bd18f MC |
829 | } |
830 | ||
eab15862 MC |
831 | #define DEFINE_CPU(type_name, initfn) \ |
832 | { \ | |
833 | .name = type_name, \ | |
834 | .parent = TYPE_RISCV_CPU, \ | |
835 | .instance_init = initfn \ | |
836 | } | |
837 | ||
838 | static const TypeInfo riscv_cpu_type_infos[] = { | |
839 | { | |
840 | .name = TYPE_RISCV_CPU, | |
841 | .parent = TYPE_CPU, | |
842 | .instance_size = sizeof(RISCVCPU), | |
5de5b99b | 843 | .instance_align = __alignof__(RISCVCPU), |
eab15862 MC |
844 | .instance_init = riscv_cpu_init, |
845 | .abstract = true, | |
846 | .class_size = sizeof(RISCVCPUClass), | |
847 | .class_init = riscv_cpu_class_init, | |
848 | }, | |
849 | DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), | |
850 | #if defined(TARGET_RISCV32) | |
094b072c | 851 | DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), |
e8905c6c | 852 | DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), |
114baaca | 853 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), |
2fdd2c09 | 854 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), |
114baaca | 855 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), |
eab15862 | 856 | #elif defined(TARGET_RISCV64) |
094b072c | 857 | DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), |
114baaca AF |
858 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), |
859 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), | |
6ddc7069 | 860 | DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), |
332dab68 | 861 | DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), |
eab15862 MC |
862 | #endif |
863 | }; | |
864 | ||
865 | DEFINE_TYPES(riscv_cpu_type_infos) |