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dc5bd18f MC |
1 | /* |
2 | * QEMU RISC-V CPU | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
0442428a | 21 | #include "qemu/qemu-print.h" |
856dfd8a | 22 | #include "qemu/ctype.h" |
dc5bd18f MC |
23 | #include "qemu/log.h" |
24 | #include "cpu.h" | |
14664483 | 25 | #include "pmu.h" |
f7697f0e | 26 | #include "internals.h" |
43888c2f | 27 | #include "time_helper.h" |
dc5bd18f MC |
28 | #include "exec/exec-all.h" |
29 | #include "qapi/error.h" | |
b55d7d34 | 30 | #include "qemu/error-report.h" |
c4e95030 | 31 | #include "hw/qdev-properties.h" |
dc5bd18f | 32 | #include "migration/vmstate.h" |
135b03cb | 33 | #include "fpu/softfloat-helpers.h" |
ad40be27 YJ |
34 | #include "sysemu/kvm.h" |
35 | #include "kvm_riscv.h" | |
dc5bd18f MC |
36 | |
37 | /* RISC-V CPU definitions */ | |
38 | ||
9951ba94 FC |
39 | #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ |
40 | (QEMU_VERSION_MINOR << 8) | \ | |
41 | (QEMU_VERSION_MICRO)) | |
075eeda9 | 42 | #define RISCV_CPU_MIMPID RISCV_CPU_MARCHID |
9951ba94 | 43 | |
0e2c3770 | 44 | static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; |
dc5bd18f | 45 | |
a775398b AP |
46 | struct isa_ext_data { |
47 | const char *name; | |
9a1f054d AP |
48 | bool multi_letter; |
49 | int min_version; | |
50 | int ext_enable_offset; | |
a775398b AP |
51 | }; |
52 | ||
9a1f054d AP |
53 | #define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \ |
54 | {#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} | |
55 | ||
56 | /** | |
57 | * Here are the ordering rules of extension naming defined by RISC-V | |
58 | * specification : | |
59 | * 1. All extensions should be separated from other multi-letter extensions | |
60 | * by an underscore. | |
61 | * 2. The first letter following the 'Z' conventionally indicates the most | |
62 | * closely related alphabetical extension category, IMAFDQLCBKJTPVH. | |
63 | * If multiple 'Z' extensions are named, they should be ordered first | |
64 | * by category, then alphabetically within a category. | |
65 | * 3. Standard supervisor-level extensions (starts with 'S') should be | |
66 | * listed after standard unprivileged extensions. If multiple | |
67 | * supervisor-level extensions are listed, they should be ordered | |
68 | * alphabetically. | |
69 | * 4. Non-standard extensions (starts with 'X') must be listed after all | |
70 | * standard extensions. They must be separated from other multi-letter | |
71 | * extensions by an underscore. | |
72 | */ | |
73 | static const struct isa_ext_data isa_edata_arr[] = { | |
74 | ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h), | |
75 | ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_12_0, ext_v), | |
76 | ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr), | |
77 | ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei), | |
4696f0ab | 78 | ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause), |
260b594d | 79 | ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs), |
9a1f054d AP |
80 | ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_12_0, ext_zfh), |
81 | ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin), | |
82 | ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx), | |
83 | ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx), | |
84 | ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba), | |
85 | ISA_EXT_DATA_ENTRY(zbb, true, PRIV_VERSION_1_12_0, ext_zbb), | |
86 | ISA_EXT_DATA_ENTRY(zbc, true, PRIV_VERSION_1_12_0, ext_zbc), | |
87 | ISA_EXT_DATA_ENTRY(zbkb, true, PRIV_VERSION_1_12_0, ext_zbkb), | |
88 | ISA_EXT_DATA_ENTRY(zbkc, true, PRIV_VERSION_1_12_0, ext_zbkc), | |
89 | ISA_EXT_DATA_ENTRY(zbkx, true, PRIV_VERSION_1_12_0, ext_zbkx), | |
90 | ISA_EXT_DATA_ENTRY(zbs, true, PRIV_VERSION_1_12_0, ext_zbs), | |
91 | ISA_EXT_DATA_ENTRY(zk, true, PRIV_VERSION_1_12_0, ext_zk), | |
92 | ISA_EXT_DATA_ENTRY(zkn, true, PRIV_VERSION_1_12_0, ext_zkn), | |
93 | ISA_EXT_DATA_ENTRY(zknd, true, PRIV_VERSION_1_12_0, ext_zknd), | |
94 | ISA_EXT_DATA_ENTRY(zkne, true, PRIV_VERSION_1_12_0, ext_zkne), | |
95 | ISA_EXT_DATA_ENTRY(zknh, true, PRIV_VERSION_1_12_0, ext_zknh), | |
96 | ISA_EXT_DATA_ENTRY(zkr, true, PRIV_VERSION_1_12_0, ext_zkr), | |
97 | ISA_EXT_DATA_ENTRY(zks, true, PRIV_VERSION_1_12_0, ext_zks), | |
98 | ISA_EXT_DATA_ENTRY(zksed, true, PRIV_VERSION_1_12_0, ext_zksed), | |
99 | ISA_EXT_DATA_ENTRY(zksh, true, PRIV_VERSION_1_12_0, ext_zksh), | |
100 | ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt), | |
101 | ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f), | |
102 | ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f), | |
103 | ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), | |
104 | ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), | |
dc9acc9c AP |
105 | ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia), |
106 | ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia), | |
14664483 | 107 | ISA_EXT_DATA_ENTRY(sscofpmf, true, PRIV_VERSION_1_12_0, ext_sscofpmf), |
43888c2f | 108 | ISA_EXT_DATA_ENTRY(sstc, true, PRIV_VERSION_1_12_0, ext_sstc), |
9a1f054d AP |
109 | ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), |
110 | ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), | |
111 | ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), | |
e0dea2f5 | 112 | ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), |
9a1f054d AP |
113 | }; |
114 | ||
115 | static bool isa_ext_is_enabled(RISCVCPU *cpu, | |
116 | const struct isa_ext_data *edata) | |
117 | { | |
118 | bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; | |
119 | ||
120 | return *ext_enabled; | |
121 | } | |
122 | ||
123 | static void isa_ext_update_enabled(RISCVCPU *cpu, | |
124 | const struct isa_ext_data *edata, bool en) | |
125 | { | |
126 | bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; | |
127 | ||
128 | *ext_enabled = en; | |
129 | } | |
130 | ||
dc5bd18f | 131 | const char * const riscv_int_regnames[] = { |
a9f37afa AP |
132 | "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", |
133 | "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", | |
134 | "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", | |
135 | "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", | |
136 | "x28/t3", "x29/t4", "x30/t5", "x31/t6" | |
dc5bd18f MC |
137 | }; |
138 | ||
2b547084 FP |
139 | const char * const riscv_int_regnamesh[] = { |
140 | "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", | |
141 | "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", | |
142 | "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", | |
143 | "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", | |
144 | "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", | |
145 | "x30h/t5h", "x31h/t6h" | |
146 | }; | |
147 | ||
dc5bd18f | 148 | const char * const riscv_fpr_regnames[] = { |
a9f37afa AP |
149 | "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", |
150 | "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", | |
151 | "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", | |
152 | "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", | |
153 | "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", | |
154 | "f30/ft10", "f31/ft11" | |
dc5bd18f MC |
155 | }; |
156 | ||
9a575d33 | 157 | static const char * const riscv_excp_names[] = { |
dc5bd18f MC |
158 | "misaligned_fetch", |
159 | "fault_fetch", | |
160 | "illegal_instruction", | |
161 | "breakpoint", | |
162 | "misaligned_load", | |
163 | "fault_load", | |
164 | "misaligned_store", | |
165 | "fault_store", | |
166 | "user_ecall", | |
167 | "supervisor_ecall", | |
168 | "hypervisor_ecall", | |
169 | "machine_ecall", | |
170 | "exec_page_fault", | |
171 | "load_page_fault", | |
172 | "reserved", | |
fd990e86 | 173 | "store_page_fault", |
ab67a1d0 AF |
174 | "reserved", |
175 | "reserved", | |
176 | "reserved", | |
177 | "reserved", | |
178 | "guest_exec_page_fault", | |
179 | "guest_load_page_fault", | |
180 | "reserved", | |
fd990e86 | 181 | "guest_store_page_fault", |
dc5bd18f MC |
182 | }; |
183 | ||
9a575d33 | 184 | static const char * const riscv_intr_names[] = { |
dc5bd18f MC |
185 | "u_software", |
186 | "s_software", | |
205377f8 | 187 | "vs_software", |
dc5bd18f MC |
188 | "m_software", |
189 | "u_timer", | |
190 | "s_timer", | |
205377f8 | 191 | "vs_timer", |
dc5bd18f MC |
192 | "m_timer", |
193 | "u_external", | |
6cfcf775 | 194 | "s_external", |
205377f8 | 195 | "vs_external", |
dc5bd18f | 196 | "m_external", |
426f0348 MC |
197 | "reserved", |
198 | "reserved", | |
199 | "reserved", | |
200 | "reserved" | |
dc5bd18f MC |
201 | }; |
202 | ||
26b2bc58 AF |
203 | static void register_cpu_props(DeviceState *dev); |
204 | ||
c51a3f5d YJ |
205 | const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) |
206 | { | |
207 | if (async) { | |
208 | return (cause < ARRAY_SIZE(riscv_intr_names)) ? | |
209 | riscv_intr_names[cause] : "(unknown)"; | |
210 | } else { | |
211 | return (cause < ARRAY_SIZE(riscv_excp_names)) ? | |
212 | riscv_excp_names[cause] : "(unknown)"; | |
213 | } | |
214 | } | |
215 | ||
e91a7227 | 216 | static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) |
dc5bd18f | 217 | { |
e91a7227 RH |
218 | env->misa_mxl_max = env->misa_mxl = mxl; |
219 | env->misa_ext_mask = env->misa_ext = ext; | |
dc5bd18f MC |
220 | } |
221 | ||
c9a73910 | 222 | static void set_priv_version(CPURISCVState *env, int priv_ver) |
dc5bd18f | 223 | { |
dc5bd18f MC |
224 | env->priv_ver = priv_ver; |
225 | } | |
226 | ||
32931383 LZ |
227 | static void set_vext_version(CPURISCVState *env, int vext_ver) |
228 | { | |
229 | env->vext_ver = vext_ver; | |
230 | } | |
231 | ||
dc5bd18f MC |
232 | static void riscv_any_cpu_init(Object *obj) |
233 | { | |
234 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
3820602f | 235 | #if defined(TARGET_RISCV32) |
e91a7227 | 236 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); |
3820602f | 237 | #elif defined(TARGET_RISCV64) |
e91a7227 | 238 | set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); |
3820602f | 239 | #endif |
7100fe6c | 240 | set_priv_version(env, PRIV_VERSION_1_12_0); |
26b2bc58 | 241 | register_cpu_props(DEVICE(obj)); |
dc5bd18f MC |
242 | } |
243 | ||
094b072c AF |
244 | #if defined(TARGET_RISCV64) |
245 | static void rv64_base_cpu_init(Object *obj) | |
8903bf6e AF |
246 | { |
247 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
b55d7d34 | 248 | /* We set this in the realise function */ |
e91a7227 | 249 | set_misa(env, MXL_RV64, 0); |
26b2bc58 | 250 | register_cpu_props(DEVICE(obj)); |
18800095 AP |
251 | /* Set latest version of privileged specification */ |
252 | set_priv_version(env, PRIV_VERSION_1_12_0); | |
8903bf6e AF |
253 | } |
254 | ||
114baaca | 255 | static void rv64_sifive_u_cpu_init(Object *obj) |
dc5bd18f MC |
256 | { |
257 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
e91a7227 | 258 | set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); |
c66ffcd5 | 259 | register_cpu_props(DEVICE(obj)); |
c9a73910 | 260 | set_priv_version(env, PRIV_VERSION_1_10_0); |
dc5bd18f MC |
261 | } |
262 | ||
114baaca | 263 | static void rv64_sifive_e_cpu_init(Object *obj) |
36b80ad9 AF |
264 | { |
265 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
26b2bc58 AF |
266 | RISCVCPU *cpu = RISCV_CPU(obj); |
267 | ||
e91a7227 | 268 | set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); |
c66ffcd5 | 269 | register_cpu_props(DEVICE(obj)); |
36b80ad9 | 270 | set_priv_version(env, PRIV_VERSION_1_10_0); |
26b2bc58 | 271 | cpu->cfg.mmu = false; |
36b80ad9 | 272 | } |
332dab68 FP |
273 | |
274 | static void rv128_base_cpu_init(Object *obj) | |
275 | { | |
276 | if (qemu_tcg_mttcg_enabled()) { | |
277 | /* Missing 128-bit aligned atomics */ | |
278 | error_report("128-bit RISC-V currently does not work with Multi " | |
279 | "Threaded TCG. Please use: -accel tcg,thread=single"); | |
280 | exit(EXIT_FAILURE); | |
281 | } | |
282 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
283 | /* We set this in the realise function */ | |
284 | set_misa(env, MXL_RV128, 0); | |
26b2bc58 | 285 | register_cpu_props(DEVICE(obj)); |
18800095 AP |
286 | /* Set latest version of privileged specification */ |
287 | set_priv_version(env, PRIV_VERSION_1_12_0); | |
332dab68 | 288 | } |
114baaca | 289 | #else |
094b072c AF |
290 | static void rv32_base_cpu_init(Object *obj) |
291 | { | |
292 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
293 | /* We set this in the realise function */ | |
e91a7227 | 294 | set_misa(env, MXL_RV32, 0); |
26b2bc58 | 295 | register_cpu_props(DEVICE(obj)); |
18800095 AP |
296 | /* Set latest version of privileged specification */ |
297 | set_priv_version(env, PRIV_VERSION_1_12_0); | |
094b072c AF |
298 | } |
299 | ||
114baaca AF |
300 | static void rv32_sifive_u_cpu_init(Object *obj) |
301 | { | |
302 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
e91a7227 | 303 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); |
c66ffcd5 | 304 | register_cpu_props(DEVICE(obj)); |
114baaca AF |
305 | set_priv_version(env, PRIV_VERSION_1_10_0); |
306 | } | |
36b80ad9 | 307 | |
114baaca AF |
308 | static void rv32_sifive_e_cpu_init(Object *obj) |
309 | { | |
310 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
26b2bc58 AF |
311 | RISCVCPU *cpu = RISCV_CPU(obj); |
312 | ||
e91a7227 | 313 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); |
c66ffcd5 | 314 | register_cpu_props(DEVICE(obj)); |
114baaca | 315 | set_priv_version(env, PRIV_VERSION_1_10_0); |
26b2bc58 | 316 | cpu->cfg.mmu = false; |
114baaca | 317 | } |
d8e72bd1 | 318 | |
e8905c6c | 319 | static void rv32_ibex_cpu_init(Object *obj) |
dc5bd18f MC |
320 | { |
321 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
26b2bc58 AF |
322 | RISCVCPU *cpu = RISCV_CPU(obj); |
323 | ||
e91a7227 | 324 | set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); |
c66ffcd5 | 325 | register_cpu_props(DEVICE(obj)); |
be2265c7 | 326 | set_priv_version(env, PRIV_VERSION_1_11_0); |
26b2bc58 AF |
327 | cpu->cfg.mmu = false; |
328 | cpu->cfg.epmp = true; | |
dc5bd18f MC |
329 | } |
330 | ||
2fdd2c09 | 331 | static void rv32_imafcu_nommu_cpu_init(Object *obj) |
d784733b CW |
332 | { |
333 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
26b2bc58 AF |
334 | RISCVCPU *cpu = RISCV_CPU(obj); |
335 | ||
e91a7227 | 336 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); |
c66ffcd5 | 337 | register_cpu_props(DEVICE(obj)); |
d784733b | 338 | set_priv_version(env, PRIV_VERSION_1_10_0); |
26b2bc58 | 339 | cpu->cfg.mmu = false; |
d784733b | 340 | } |
eab15862 | 341 | #endif |
dc5bd18f | 342 | |
10f1ca27 YJ |
343 | #if defined(CONFIG_KVM) |
344 | static void riscv_host_cpu_init(Object *obj) | |
345 | { | |
346 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
347 | #if defined(TARGET_RISCV32) | |
348 | set_misa(env, MXL_RV32, 0); | |
349 | #elif defined(TARGET_RISCV64) | |
350 | set_misa(env, MXL_RV64, 0); | |
351 | #endif | |
26b2bc58 | 352 | register_cpu_props(DEVICE(obj)); |
10f1ca27 YJ |
353 | } |
354 | #endif | |
355 | ||
dc5bd18f MC |
356 | static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) |
357 | { | |
358 | ObjectClass *oc; | |
359 | char *typename; | |
360 | char **cpuname; | |
361 | ||
362 | cpuname = g_strsplit(cpu_model, ",", 1); | |
363 | typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); | |
364 | oc = object_class_by_name(typename); | |
365 | g_strfreev(cpuname); | |
366 | g_free(typename); | |
367 | if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || | |
368 | object_class_is_abstract(oc)) { | |
369 | return NULL; | |
370 | } | |
371 | return oc; | |
372 | } | |
373 | ||
90c84c56 | 374 | static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) |
dc5bd18f MC |
375 | { |
376 | RISCVCPU *cpu = RISCV_CPU(cs); | |
377 | CPURISCVState *env = &cpu->env; | |
378 | int i; | |
379 | ||
df30e652 AF |
380 | #if !defined(CONFIG_USER_ONLY) |
381 | if (riscv_has_ext(env, RVH)) { | |
382 | qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); | |
383 | } | |
384 | #endif | |
90c84c56 | 385 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); |
dc5bd18f | 386 | #ifndef CONFIG_USER_ONLY |
665b90d8 RH |
387 | { |
388 | static const int dump_csrs[] = { | |
389 | CSR_MHARTID, | |
390 | CSR_MSTATUS, | |
391 | CSR_MSTATUSH, | |
bc7dca13 BM |
392 | /* |
393 | * CSR_SSTATUS is intentionally omitted here as its value | |
394 | * can be figured out by looking at CSR_MSTATUS | |
395 | */ | |
665b90d8 RH |
396 | CSR_HSTATUS, |
397 | CSR_VSSTATUS, | |
398 | CSR_MIP, | |
399 | CSR_MIE, | |
400 | CSR_MIDELEG, | |
401 | CSR_HIDELEG, | |
402 | CSR_MEDELEG, | |
403 | CSR_HEDELEG, | |
404 | CSR_MTVEC, | |
405 | CSR_STVEC, | |
406 | CSR_VSTVEC, | |
407 | CSR_MEPC, | |
408 | CSR_SEPC, | |
409 | CSR_VSEPC, | |
410 | CSR_MCAUSE, | |
411 | CSR_SCAUSE, | |
412 | CSR_VSCAUSE, | |
413 | CSR_MTVAL, | |
414 | CSR_STVAL, | |
415 | CSR_HTVAL, | |
416 | CSR_MTVAL2, | |
417 | CSR_MSCRATCH, | |
418 | CSR_SSCRATCH, | |
419 | CSR_SATP, | |
bd5594ca AB |
420 | CSR_MMTE, |
421 | CSR_UPMBASE, | |
422 | CSR_UPMMASK, | |
423 | CSR_SPMBASE, | |
424 | CSR_SPMMASK, | |
425 | CSR_MPMBASE, | |
426 | CSR_MPMMASK, | |
665b90d8 RH |
427 | }; |
428 | ||
429 | for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { | |
430 | int csrno = dump_csrs[i]; | |
431 | target_ulong val = 0; | |
432 | RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); | |
433 | ||
434 | /* | |
435 | * Rely on the smode, hmode, etc, predicates within csr.c | |
436 | * to do the filtering of the registers that are present. | |
437 | */ | |
438 | if (res == RISCV_EXCP_NONE) { | |
439 | qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", | |
440 | csr_ops[csrno].name, val); | |
441 | } | |
442 | } | |
df30e652 | 443 | } |
dc5bd18f MC |
444 | #endif |
445 | ||
446 | for (i = 0; i < 32; i++) { | |
e573a7f3 | 447 | qemu_fprintf(f, " %-8s " TARGET_FMT_lx, |
90c84c56 | 448 | riscv_int_regnames[i], env->gpr[i]); |
dc5bd18f | 449 | if ((i & 3) == 3) { |
90c84c56 | 450 | qemu_fprintf(f, "\n"); |
dc5bd18f MC |
451 | } |
452 | } | |
86ea1880 RH |
453 | if (flags & CPU_DUMP_FPU) { |
454 | for (i = 0; i < 32; i++) { | |
e573a7f3 | 455 | qemu_fprintf(f, " %-8s %016" PRIx64, |
90c84c56 | 456 | riscv_fpr_regnames[i], env->fpr[i]); |
86ea1880 | 457 | if ((i & 3) == 3) { |
90c84c56 | 458 | qemu_fprintf(f, "\n"); |
86ea1880 | 459 | } |
dc5bd18f MC |
460 | } |
461 | } | |
462 | } | |
463 | ||
464 | static void riscv_cpu_set_pc(CPUState *cs, vaddr value) | |
465 | { | |
466 | RISCVCPU *cpu = RISCV_CPU(cs); | |
467 | CPURISCVState *env = &cpu->env; | |
bf9e776e LZ |
468 | |
469 | if (env->xl == MXL_RV32) { | |
470 | env->pc = (int32_t)value; | |
471 | } else { | |
472 | env->pc = value; | |
473 | } | |
dc5bd18f MC |
474 | } |
475 | ||
e4fdf9df RH |
476 | static vaddr riscv_cpu_get_pc(CPUState *cs) |
477 | { | |
478 | RISCVCPU *cpu = RISCV_CPU(cs); | |
479 | CPURISCVState *env = &cpu->env; | |
480 | ||
481 | /* Match cpu_get_tb_cpu_state. */ | |
482 | if (env->xl == MXL_RV32) { | |
483 | return env->pc & UINT32_MAX; | |
484 | } | |
485 | return env->pc; | |
486 | } | |
487 | ||
04a37d4c RH |
488 | static void riscv_cpu_synchronize_from_tb(CPUState *cs, |
489 | const TranslationBlock *tb) | |
dc5bd18f MC |
490 | { |
491 | RISCVCPU *cpu = RISCV_CPU(cs); | |
492 | CPURISCVState *env = &cpu->env; | |
bf9e776e LZ |
493 | RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); |
494 | ||
495 | if (xl == MXL_RV32) { | |
fbf59aad | 496 | env->pc = (int32_t)tb_pc(tb); |
bf9e776e | 497 | } else { |
fbf59aad | 498 | env->pc = tb_pc(tb); |
bf9e776e | 499 | } |
dc5bd18f MC |
500 | } |
501 | ||
502 | static bool riscv_cpu_has_work(CPUState *cs) | |
503 | { | |
504 | #ifndef CONFIG_USER_ONLY | |
505 | RISCVCPU *cpu = RISCV_CPU(cs); | |
506 | CPURISCVState *env = &cpu->env; | |
507 | /* | |
508 | * Definition of the WFI instruction requires it to ignore the privilege | |
509 | * mode and delegation registers, but respect individual enables | |
510 | */ | |
8f42415f | 511 | return riscv_cpu_all_pending(env) != 0; |
dc5bd18f MC |
512 | #else |
513 | return true; | |
514 | #endif | |
515 | } | |
516 | ||
ad1e84f5 RH |
517 | static void riscv_restore_state_to_opc(CPUState *cs, |
518 | const TranslationBlock *tb, | |
519 | const uint64_t *data) | |
dc5bd18f | 520 | { |
ad1e84f5 RH |
521 | RISCVCPU *cpu = RISCV_CPU(cs); |
522 | CPURISCVState *env = &cpu->env; | |
bf9e776e | 523 | RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); |
ad1e84f5 | 524 | |
bf9e776e LZ |
525 | if (xl == MXL_RV32) { |
526 | env->pc = (int32_t)data[0]; | |
527 | } else { | |
528 | env->pc = data[0]; | |
529 | } | |
62cf0245 | 530 | env->bins = data[1]; |
dc5bd18f MC |
531 | } |
532 | ||
4fa485a7 | 533 | static void riscv_cpu_reset_hold(Object *obj) |
dc5bd18f | 534 | { |
43dc93af AP |
535 | #ifndef CONFIG_USER_ONLY |
536 | uint8_t iprio; | |
537 | int i, irq, rdzero; | |
538 | #endif | |
4fa485a7 | 539 | CPUState *cs = CPU(obj); |
dc5bd18f MC |
540 | RISCVCPU *cpu = RISCV_CPU(cs); |
541 | RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); | |
542 | CPURISCVState *env = &cpu->env; | |
543 | ||
4fa485a7 PM |
544 | if (mcc->parent_phases.hold) { |
545 | mcc->parent_phases.hold(obj); | |
546 | } | |
dc5bd18f | 547 | #ifndef CONFIG_USER_ONLY |
e91a7227 | 548 | env->misa_mxl = env->misa_mxl_max; |
dc5bd18f MC |
549 | env->priv = PRV_M; |
550 | env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); | |
92371bd9 RH |
551 | if (env->misa_mxl > MXL_RV32) { |
552 | /* | |
553 | * The reset status of SXL/UXL is undefined, but mstatus is WARL | |
554 | * and we must ensure that the value after init is valid for read. | |
555 | */ | |
556 | env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); | |
557 | env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); | |
5a2ae235 LZ |
558 | if (riscv_has_ext(env, RVH)) { |
559 | env->vsstatus = set_field(env->vsstatus, | |
560 | MSTATUS64_SXL, env->misa_mxl); | |
561 | env->vsstatus = set_field(env->vsstatus, | |
562 | MSTATUS64_UXL, env->misa_mxl); | |
563 | env->mstatus_hs = set_field(env->mstatus_hs, | |
564 | MSTATUS64_SXL, env->misa_mxl); | |
565 | env->mstatus_hs = set_field(env->mstatus_hs, | |
566 | MSTATUS64_UXL, env->misa_mxl); | |
567 | } | |
92371bd9 | 568 | } |
dc5bd18f | 569 | env->mcause = 0; |
881df35d | 570 | env->miclaim = MIP_SGEIP; |
dc5bd18f | 571 | env->pc = env->resetvec; |
62cf0245 | 572 | env->bins = 0; |
ec352d0c | 573 | env->two_stage_lookup = false; |
43dc93af AP |
574 | |
575 | /* Initialized default priorities of local interrupts. */ | |
576 | for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { | |
577 | iprio = riscv_cpu_default_priority(i); | |
578 | env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio; | |
579 | env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio; | |
580 | env->hviprio[i] = 0; | |
581 | } | |
582 | i = 0; | |
583 | while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) { | |
584 | if (!rdzero) { | |
585 | env->hviprio[irq] = env->miprio[irq]; | |
586 | } | |
587 | i++; | |
588 | } | |
4bbe8033 AB |
589 | /* mmte is supposed to have pm.current hardwired to 1 */ |
590 | env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); | |
dc5bd18f | 591 | #endif |
440544e1 | 592 | env->xl = riscv_cpu_mxl(env); |
40bfa5f6 | 593 | riscv_cpu_update_mask(env); |
330d2ae3 | 594 | cs->exception_index = RISCV_EXCP_NONE; |
c13b169f | 595 | env->load_res = -1; |
dc5bd18f | 596 | set_default_nan_mode(1, &env->fp_status); |
ad40be27 YJ |
597 | |
598 | #ifndef CONFIG_USER_ONLY | |
b6092544 BM |
599 | if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { |
600 | riscv_trigger_init(env); | |
601 | } | |
602 | ||
ad40be27 YJ |
603 | if (kvm_enabled()) { |
604 | kvm_riscv_reset_vcpu(cpu); | |
605 | } | |
606 | #endif | |
dc5bd18f MC |
607 | } |
608 | ||
609 | static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) | |
610 | { | |
5c5a47f1 | 611 | RISCVCPU *cpu = RISCV_CPU(s); |
db23e5d9 RH |
612 | |
613 | switch (riscv_cpu_mxl(&cpu->env)) { | |
614 | case MXL_RV32: | |
5c5a47f1 | 615 | info->print_insn = print_insn_riscv32; |
db23e5d9 RH |
616 | break; |
617 | case MXL_RV64: | |
5c5a47f1 | 618 | info->print_insn = print_insn_riscv64; |
db23e5d9 | 619 | break; |
332dab68 FP |
620 | case MXL_RV128: |
621 | info->print_insn = print_insn_riscv128; | |
622 | break; | |
db23e5d9 RH |
623 | default: |
624 | g_assert_not_reached(); | |
5c5a47f1 | 625 | } |
dc5bd18f MC |
626 | } |
627 | ||
5ab10952 DHB |
628 | /* |
629 | * Check consistency between chosen extensions while setting | |
630 | * cpu->cfg accordingly, doing a set_misa() in the end. | |
631 | */ | |
632 | static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) | |
633 | { | |
634 | CPURISCVState *env = &cpu->env; | |
635 | uint32_t ext = 0; | |
636 | ||
637 | /* Do some ISA extension error checking */ | |
638 | if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && | |
639 | cpu->cfg.ext_a && cpu->cfg.ext_f && | |
640 | cpu->cfg.ext_d && | |
641 | cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { | |
642 | warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); | |
643 | cpu->cfg.ext_i = true; | |
644 | cpu->cfg.ext_m = true; | |
645 | cpu->cfg.ext_a = true; | |
646 | cpu->cfg.ext_f = true; | |
647 | cpu->cfg.ext_d = true; | |
648 | cpu->cfg.ext_icsr = true; | |
649 | cpu->cfg.ext_ifencei = true; | |
650 | } | |
651 | ||
652 | if (cpu->cfg.ext_i && cpu->cfg.ext_e) { | |
653 | error_setg(errp, | |
654 | "I and E extensions are incompatible"); | |
655 | return; | |
656 | } | |
657 | ||
658 | if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { | |
659 | error_setg(errp, | |
660 | "Either I or E extension must be set"); | |
661 | return; | |
662 | } | |
663 | ||
664 | if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { | |
665 | error_setg(errp, | |
666 | "Setting S extension without U extension is illegal"); | |
667 | return; | |
668 | } | |
669 | ||
670 | if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { | |
671 | error_setg(errp, | |
672 | "H depends on an I base integer ISA with 32 x registers"); | |
673 | return; | |
674 | } | |
675 | ||
676 | if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { | |
677 | error_setg(errp, "H extension implicitly requires S-mode"); | |
678 | return; | |
679 | } | |
680 | ||
681 | if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { | |
682 | error_setg(errp, "F extension requires Zicsr"); | |
683 | return; | |
684 | } | |
685 | ||
686 | if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { | |
687 | error_setg(errp, "Zawrs extension requires A extension"); | |
688 | return; | |
689 | } | |
690 | ||
691 | if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) { | |
692 | error_setg(errp, "Zfh/Zfhmin extensions require F extension"); | |
693 | return; | |
694 | } | |
695 | ||
696 | if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { | |
697 | error_setg(errp, "D extension requires F extension"); | |
698 | return; | |
699 | } | |
700 | ||
701 | if (cpu->cfg.ext_v && !cpu->cfg.ext_d) { | |
702 | error_setg(errp, "V extension requires D extension"); | |
703 | return; | |
704 | } | |
705 | ||
706 | if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) { | |
707 | error_setg(errp, "Zve32f/Zve64f extensions require F extension"); | |
708 | return; | |
709 | } | |
710 | ||
711 | /* Set the ISA extensions, checks should have happened above */ | |
712 | if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || | |
713 | cpu->cfg.ext_zhinxmin) { | |
714 | cpu->cfg.ext_zfinx = true; | |
715 | } | |
716 | ||
717 | if (cpu->cfg.ext_zfinx) { | |
718 | if (!cpu->cfg.ext_icsr) { | |
719 | error_setg(errp, "Zfinx extension requires Zicsr"); | |
720 | return; | |
721 | } | |
722 | if (cpu->cfg.ext_f) { | |
723 | error_setg(errp, | |
724 | "Zfinx cannot be supported together with F extension"); | |
725 | return; | |
726 | } | |
727 | } | |
728 | ||
729 | if (cpu->cfg.ext_zk) { | |
730 | cpu->cfg.ext_zkn = true; | |
731 | cpu->cfg.ext_zkr = true; | |
732 | cpu->cfg.ext_zkt = true; | |
733 | } | |
734 | ||
735 | if (cpu->cfg.ext_zkn) { | |
736 | cpu->cfg.ext_zbkb = true; | |
737 | cpu->cfg.ext_zbkc = true; | |
738 | cpu->cfg.ext_zbkx = true; | |
739 | cpu->cfg.ext_zkne = true; | |
740 | cpu->cfg.ext_zknd = true; | |
741 | cpu->cfg.ext_zknh = true; | |
742 | } | |
743 | ||
744 | if (cpu->cfg.ext_zks) { | |
745 | cpu->cfg.ext_zbkb = true; | |
746 | cpu->cfg.ext_zbkc = true; | |
747 | cpu->cfg.ext_zbkx = true; | |
748 | cpu->cfg.ext_zksed = true; | |
749 | cpu->cfg.ext_zksh = true; | |
750 | } | |
751 | ||
752 | if (cpu->cfg.ext_i) { | |
753 | ext |= RVI; | |
754 | } | |
755 | if (cpu->cfg.ext_e) { | |
756 | ext |= RVE; | |
757 | } | |
758 | if (cpu->cfg.ext_m) { | |
759 | ext |= RVM; | |
760 | } | |
761 | if (cpu->cfg.ext_a) { | |
762 | ext |= RVA; | |
763 | } | |
764 | if (cpu->cfg.ext_f) { | |
765 | ext |= RVF; | |
766 | } | |
767 | if (cpu->cfg.ext_d) { | |
768 | ext |= RVD; | |
769 | } | |
770 | if (cpu->cfg.ext_c) { | |
771 | ext |= RVC; | |
772 | } | |
773 | if (cpu->cfg.ext_s) { | |
774 | ext |= RVS; | |
775 | } | |
776 | if (cpu->cfg.ext_u) { | |
777 | ext |= RVU; | |
778 | } | |
779 | if (cpu->cfg.ext_h) { | |
780 | ext |= RVH; | |
781 | } | |
782 | if (cpu->cfg.ext_v) { | |
783 | int vext_version = VEXT_VERSION_1_00_0; | |
784 | ext |= RVV; | |
785 | if (!is_power_of_2(cpu->cfg.vlen)) { | |
786 | error_setg(errp, | |
787 | "Vector extension VLEN must be power of 2"); | |
788 | return; | |
789 | } | |
790 | if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { | |
791 | error_setg(errp, | |
792 | "Vector extension implementation only supports VLEN " | |
793 | "in the range [128, %d]", RV_VLEN_MAX); | |
794 | return; | |
795 | } | |
796 | if (!is_power_of_2(cpu->cfg.elen)) { | |
797 | error_setg(errp, | |
798 | "Vector extension ELEN must be power of 2"); | |
799 | return; | |
800 | } | |
801 | if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { | |
802 | error_setg(errp, | |
803 | "Vector extension implementation only supports ELEN " | |
804 | "in the range [8, 64]"); | |
805 | return; | |
806 | } | |
807 | if (cpu->cfg.vext_spec) { | |
808 | if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { | |
809 | vext_version = VEXT_VERSION_1_00_0; | |
810 | } else { | |
811 | error_setg(errp, | |
812 | "Unsupported vector spec version '%s'", | |
813 | cpu->cfg.vext_spec); | |
814 | return; | |
815 | } | |
816 | } else { | |
817 | qemu_log("vector version is not specified, " | |
818 | "use the default value v1.0\n"); | |
819 | } | |
820 | set_vext_version(env, vext_version); | |
821 | } | |
822 | if (cpu->cfg.ext_j) { | |
823 | ext |= RVJ; | |
824 | } | |
825 | ||
826 | set_misa(env, env->misa_mxl, ext); | |
827 | } | |
828 | ||
dc5bd18f MC |
829 | static void riscv_cpu_realize(DeviceState *dev, Error **errp) |
830 | { | |
831 | CPUState *cs = CPU(dev); | |
c4e95030 AF |
832 | RISCVCPU *cpu = RISCV_CPU(dev); |
833 | CPURISCVState *env = &cpu->env; | |
dc5bd18f | 834 | RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); |
1191be09 | 835 | CPUClass *cc = CPU_CLASS(mcc); |
9a1f054d | 836 | int i, priv_version = -1; |
dc5bd18f MC |
837 | Error *local_err = NULL; |
838 | ||
839 | cpu_exec_realizefn(cs, &local_err); | |
840 | if (local_err != NULL) { | |
841 | error_propagate(errp, local_err); | |
842 | return; | |
843 | } | |
844 | ||
c4e95030 | 845 | if (cpu->cfg.priv_spec) { |
7100fe6c AP |
846 | if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { |
847 | priv_version = PRIV_VERSION_1_12_0; | |
848 | } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { | |
e3147506 AF |
849 | priv_version = PRIV_VERSION_1_11_0; |
850 | } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { | |
c4e95030 | 851 | priv_version = PRIV_VERSION_1_10_0; |
c4e95030 AF |
852 | } else { |
853 | error_setg(errp, | |
854 | "Unsupported privilege spec version '%s'", | |
855 | cpu->cfg.priv_spec); | |
856 | return; | |
857 | } | |
858 | } | |
859 | ||
18800095 | 860 | if (priv_version >= PRIV_VERSION_1_10_0) { |
a8b37120 | 861 | set_priv_version(env, priv_version); |
a8b37120 | 862 | } |
c4e95030 | 863 | |
9a1f054d AP |
864 | /* Force disable extensions if priv spec version does not match */ |
865 | for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { | |
866 | if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && | |
867 | (env->priv_ver < isa_edata_arr[i].min_version)) { | |
868 | isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); | |
869 | #ifndef CONFIG_USER_ONLY | |
870 | warn_report("disabling %s extension for hart 0x%lx because " | |
871 | "privilege spec version does not match", | |
872 | isa_edata_arr[i].name, (unsigned long)env->mhartid); | |
873 | #else | |
874 | warn_report("disabling %s extension because " | |
875 | "privilege spec version does not match", | |
876 | isa_edata_arr[i].name); | |
877 | #endif | |
878 | } | |
879 | } | |
880 | ||
c4e95030 | 881 | if (cpu->cfg.mmu) { |
f87adf23 | 882 | riscv_set_feature(env, RISCV_FEATURE_MMU); |
c4e95030 AF |
883 | } |
884 | ||
885 | if (cpu->cfg.pmp) { | |
f87adf23 | 886 | riscv_set_feature(env, RISCV_FEATURE_PMP); |
5da9514e HW |
887 | |
888 | /* | |
889 | * Enhanced PMP should only be available | |
890 | * on harts with PMP support | |
891 | */ | |
892 | if (cpu->cfg.epmp) { | |
f87adf23 | 893 | riscv_set_feature(env, RISCV_FEATURE_EPMP); |
5da9514e | 894 | } |
c4e95030 AF |
895 | } |
896 | ||
1acdb3b0 BM |
897 | if (cpu->cfg.debug) { |
898 | riscv_set_feature(env, RISCV_FEATURE_DEBUG); | |
899 | } | |
900 | ||
73f6ed97 | 901 | |
43888c2f AP |
902 | #ifndef CONFIG_USER_ONLY |
903 | if (cpu->cfg.ext_sstc) { | |
904 | riscv_timer_init(cpu); | |
905 | } | |
906 | #endif /* CONFIG_USER_ONLY */ | |
907 | ||
e91a7227 RH |
908 | /* Validate that MISA_MXL is set properly. */ |
909 | switch (env->misa_mxl_max) { | |
910 | #ifdef TARGET_RISCV64 | |
911 | case MXL_RV64: | |
332dab68 | 912 | case MXL_RV128: |
6c3a9247 | 913 | cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; |
332dab68 | 914 | break; |
e91a7227 RH |
915 | #endif |
916 | case MXL_RV32: | |
1191be09 | 917 | cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; |
e91a7227 RH |
918 | break; |
919 | default: | |
920 | g_assert_not_reached(); | |
921 | } | |
922 | assert(env->misa_mxl_max == env->misa_mxl); | |
923 | ||
5ab10952 DHB |
924 | riscv_cpu_validate_set_extensions(cpu, &local_err); |
925 | if (local_err != NULL) { | |
926 | error_propagate(errp, local_err); | |
927 | return; | |
b55d7d34 AF |
928 | } |
929 | ||
14664483 AP |
930 | #ifndef CONFIG_USER_ONLY |
931 | if (cpu->cfg.pmu_num) { | |
932 | if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { | |
933 | cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, | |
934 | riscv_pmu_timer_cb, cpu); | |
935 | } | |
936 | } | |
937 | #endif | |
938 | ||
5371f5cd JW |
939 | riscv_cpu_register_gdb_regs_for_features(cs); |
940 | ||
dc5bd18f MC |
941 | qemu_init_vcpu(cs); |
942 | cpu_reset(cs); | |
943 | ||
944 | mcc->parent_realize(dev, errp); | |
945 | } | |
946 | ||
0f0b70ee AF |
947 | #ifndef CONFIG_USER_ONLY |
948 | static void riscv_cpu_set_irq(void *opaque, int irq, int level) | |
949 | { | |
950 | RISCVCPU *cpu = RISCV_CPU(opaque); | |
cd032fe7 | 951 | CPURISCVState *env = &cpu->env; |
0f0b70ee | 952 | |
cd032fe7 AP |
953 | if (irq < IRQ_LOCAL_MAX) { |
954 | switch (irq) { | |
955 | case IRQ_U_SOFT: | |
956 | case IRQ_S_SOFT: | |
957 | case IRQ_VS_SOFT: | |
958 | case IRQ_M_SOFT: | |
959 | case IRQ_U_TIMER: | |
960 | case IRQ_S_TIMER: | |
961 | case IRQ_VS_TIMER: | |
962 | case IRQ_M_TIMER: | |
963 | case IRQ_U_EXT: | |
cd032fe7 AP |
964 | case IRQ_VS_EXT: |
965 | case IRQ_M_EXT: | |
8b5c807b | 966 | if (kvm_enabled()) { |
cd032fe7 | 967 | kvm_riscv_set_irq(cpu, irq, level); |
8b5c807b | 968 | } else { |
cd032fe7 | 969 | riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); |
8b5c807b | 970 | } |
cd032fe7 | 971 | break; |
33fe584f AF |
972 | case IRQ_S_EXT: |
973 | if (kvm_enabled()) { | |
974 | kvm_riscv_set_irq(cpu, irq, level); | |
975 | } else { | |
976 | env->external_seip = level; | |
977 | riscv_cpu_update_mip(cpu, 1 << irq, | |
978 | BOOL_TO_MASK(level | env->software_seip)); | |
979 | } | |
980 | break; | |
cd032fe7 AP |
981 | default: |
982 | g_assert_not_reached(); | |
2b650fbb | 983 | } |
cd032fe7 AP |
984 | } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { |
985 | /* Require H-extension for handling guest local interrupts */ | |
986 | if (!riscv_has_ext(env, RVH)) { | |
987 | g_assert_not_reached(); | |
988 | } | |
989 | ||
990 | /* Compute bit position in HGEIP CSR */ | |
991 | irq = irq - IRQ_LOCAL_MAX + 1; | |
992 | if (env->geilen < irq) { | |
993 | g_assert_not_reached(); | |
994 | } | |
995 | ||
996 | /* Update HGEIP CSR */ | |
997 | env->hgeip &= ~((target_ulong)1 << irq); | |
998 | if (level) { | |
999 | env->hgeip |= (target_ulong)1 << irq; | |
1000 | } | |
1001 | ||
1002 | /* Update mip.SGEIP bit */ | |
1003 | riscv_cpu_update_mip(cpu, MIP_SGEIP, | |
1004 | BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); | |
1005 | } else { | |
0f0b70ee AF |
1006 | g_assert_not_reached(); |
1007 | } | |
1008 | } | |
1009 | #endif /* CONFIG_USER_ONLY */ | |
1010 | ||
dc5bd18f MC |
1011 | static void riscv_cpu_init(Object *obj) |
1012 | { | |
dc5bd18f MC |
1013 | RISCVCPU *cpu = RISCV_CPU(obj); |
1014 | ||
26b2bc58 AF |
1015 | cpu->cfg.ext_ifencei = true; |
1016 | cpu->cfg.ext_icsr = true; | |
1017 | cpu->cfg.mmu = true; | |
1018 | cpu->cfg.pmp = true; | |
1019 | ||
7506ed90 | 1020 | cpu_set_cpustate_pointers(cpu); |
0f0b70ee AF |
1021 | |
1022 | #ifndef CONFIG_USER_ONLY | |
cd032fe7 AP |
1023 | qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, |
1024 | IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); | |
0f0b70ee | 1025 | #endif /* CONFIG_USER_ONLY */ |
dc5bd18f MC |
1026 | } |
1027 | ||
26b2bc58 | 1028 | static Property riscv_cpu_extensions[] = { |
9d3d60b7 | 1029 | /* Defaults for standard extensions */ |
b55d7d34 AF |
1030 | DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), |
1031 | DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), | |
1d398ab9 | 1032 | DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), |
b55d7d34 AF |
1033 | DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), |
1034 | DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), | |
1035 | DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), | |
1036 | DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), | |
1037 | DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), | |
1038 | DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), | |
1039 | DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), | |
9ec6622d | 1040 | DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), |
07cb270a | 1041 | DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), |
18d6d89e | 1042 | DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), |
14664483 | 1043 | DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), |
9d3d60b7 AF |
1044 | DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), |
1045 | DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), | |
4696f0ab | 1046 | DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), |
260b594d | 1047 | DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), |
13fb8c7b | 1048 | DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), |
e5237730 | 1049 | DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), |
2fc1b44d | 1050 | DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), |
bfefe406 | 1051 | DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), |
9d3d60b7 AF |
1052 | DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), |
1053 | DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), | |
43888c2f | 1054 | DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true), |
9d3d60b7 AF |
1055 | |
1056 | DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), | |
9ec6622d FC |
1057 | DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), |
1058 | DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), | |
1059 | DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), | |
9d3d60b7 | 1060 | |
c5d77ddd | 1061 | DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), |
2bacb224 | 1062 | DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), |
bbce8ba8 | 1063 | DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), |
2bacb224 | 1064 | |
0643c12e VG |
1065 | DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), |
1066 | DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), | |
1067 | DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), | |
cf7ed971 WL |
1068 | DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false), |
1069 | DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false), | |
1070 | DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false), | |
0643c12e | 1071 | DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), |
cf7ed971 WL |
1072 | DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false), |
1073 | DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false), | |
1074 | DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false), | |
1075 | DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false), | |
1076 | DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false), | |
1077 | DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false), | |
1078 | DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false), | |
1079 | DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false), | |
1080 | DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), | |
1081 | DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), | |
dfdb46a3 | 1082 | |
6b1accef WL |
1083 | DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), |
1084 | DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), | |
1085 | DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), | |
1086 | DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), | |
1087 | ||
6d00ffad WL |
1088 | DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), |
1089 | ||
0d429bd2 PT |
1090 | /* Vendor-specific custom extensions */ |
1091 | DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), | |
1092 | ||
dfdb46a3 | 1093 | /* These are experimental so mark with 'x-' */ |
0ee9a4e5 | 1094 | DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), |
a44da25a | 1095 | /* ePMP 0.9.3 */ |
5da9514e | 1096 | DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), |
dc9acc9c AP |
1097 | DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), |
1098 | DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), | |
5da9514e | 1099 | |
26b2bc58 AF |
1100 | DEFINE_PROP_END_OF_LIST(), |
1101 | }; | |
1102 | ||
c66ffcd5 DHB |
1103 | /* |
1104 | * Register CPU props based on env.misa_ext. If a non-zero | |
1105 | * value was set, register only the required cpu->cfg.ext_* | |
1106 | * properties and leave. env.misa_ext = 0 means that we want | |
1107 | * all the default properties to be registered. | |
1108 | */ | |
26b2bc58 AF |
1109 | static void register_cpu_props(DeviceState *dev) |
1110 | { | |
c66ffcd5 DHB |
1111 | RISCVCPU *cpu = RISCV_CPU(OBJECT(dev)); |
1112 | uint32_t misa_ext = cpu->env.misa_ext; | |
26b2bc58 AF |
1113 | Property *prop; |
1114 | ||
c66ffcd5 DHB |
1115 | /* |
1116 | * If misa_ext is not zero, set cfg properties now to | |
1117 | * allow them to be read during riscv_cpu_realize() | |
1118 | * later on. | |
1119 | */ | |
1120 | if (cpu->env.misa_ext != 0) { | |
1121 | cpu->cfg.ext_i = misa_ext & RVI; | |
1122 | cpu->cfg.ext_e = misa_ext & RVE; | |
1123 | cpu->cfg.ext_m = misa_ext & RVM; | |
1124 | cpu->cfg.ext_a = misa_ext & RVA; | |
1125 | cpu->cfg.ext_f = misa_ext & RVF; | |
1126 | cpu->cfg.ext_d = misa_ext & RVD; | |
1127 | cpu->cfg.ext_v = misa_ext & RVV; | |
1128 | cpu->cfg.ext_c = misa_ext & RVC; | |
1129 | cpu->cfg.ext_s = misa_ext & RVS; | |
1130 | cpu->cfg.ext_u = misa_ext & RVU; | |
1131 | cpu->cfg.ext_h = misa_ext & RVH; | |
1132 | cpu->cfg.ext_j = misa_ext & RVJ; | |
1133 | ||
1134 | /* | |
1135 | * We don't want to set the default riscv_cpu_extensions | |
1136 | * in this case. | |
1137 | */ | |
1138 | return; | |
1139 | } | |
1140 | ||
26b2bc58 AF |
1141 | for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { |
1142 | qdev_property_add_static(dev, prop); | |
1143 | } | |
1144 | } | |
1145 | ||
1146 | static Property riscv_cpu_properties[] = { | |
1147 | DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), | |
1148 | ||
1149 | DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), | |
1150 | DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), | |
1151 | DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), | |
1152 | ||
277b210d AF |
1153 | #ifndef CONFIG_USER_ONLY |
1154 | DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), | |
1155 | #endif | |
a4a9a443 TO |
1156 | |
1157 | DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), | |
b8312675 | 1158 | |
1159 | DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), | |
1ad3f9bd | 1160 | DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), |
c4e95030 AF |
1161 | DEFINE_PROP_END_OF_LIST(), |
1162 | }; | |
1163 | ||
edf64786 SP |
1164 | static gchar *riscv_gdb_arch_name(CPUState *cs) |
1165 | { | |
1166 | RISCVCPU *cpu = RISCV_CPU(cs); | |
1167 | CPURISCVState *env = &cpu->env; | |
1168 | ||
db23e5d9 RH |
1169 | switch (riscv_cpu_mxl(env)) { |
1170 | case MXL_RV32: | |
edf64786 | 1171 | return g_strdup("riscv:rv32"); |
db23e5d9 | 1172 | case MXL_RV64: |
332dab68 | 1173 | case MXL_RV128: |
edf64786 | 1174 | return g_strdup("riscv:rv64"); |
db23e5d9 RH |
1175 | default: |
1176 | g_assert_not_reached(); | |
edf64786 SP |
1177 | } |
1178 | } | |
1179 | ||
b93777e1 BM |
1180 | static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) |
1181 | { | |
1182 | RISCVCPU *cpu = RISCV_CPU(cs); | |
1183 | ||
1184 | if (strcmp(xmlname, "riscv-csr.xml") == 0) { | |
1185 | return cpu->dyn_csr_xml; | |
719d3561 HW |
1186 | } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { |
1187 | return cpu->dyn_vreg_xml; | |
b93777e1 BM |
1188 | } |
1189 | ||
1190 | return NULL; | |
1191 | } | |
1192 | ||
8b80bd28 PMD |
1193 | #ifndef CONFIG_USER_ONLY |
1194 | #include "hw/core/sysemu-cpu-ops.h" | |
1195 | ||
1196 | static const struct SysemuCPUOps riscv_sysemu_ops = { | |
08928c6d | 1197 | .get_phys_page_debug = riscv_cpu_get_phys_page_debug, |
715e3c1a PMD |
1198 | .write_elf64_note = riscv_cpu_write_elf64_note, |
1199 | .write_elf32_note = riscv_cpu_write_elf32_note, | |
feece4d0 | 1200 | .legacy_vmsd = &vmstate_riscv_cpu, |
8b80bd28 PMD |
1201 | }; |
1202 | #endif | |
1203 | ||
78271684 CF |
1204 | #include "hw/core/tcg-cpu-ops.h" |
1205 | ||
11906557 | 1206 | static const struct TCGCPUOps riscv_tcg_ops = { |
78271684 CF |
1207 | .initialize = riscv_translate_init, |
1208 | .synchronize_from_tb = riscv_cpu_synchronize_from_tb, | |
ad1e84f5 | 1209 | .restore_state_to_opc = riscv_restore_state_to_opc, |
78271684 CF |
1210 | |
1211 | #ifndef CONFIG_USER_ONLY | |
263e2ab2 | 1212 | .tlb_fill = riscv_cpu_tlb_fill, |
17b3c353 | 1213 | .cpu_exec_interrupt = riscv_cpu_exec_interrupt, |
78271684 CF |
1214 | .do_interrupt = riscv_cpu_do_interrupt, |
1215 | .do_transaction_failed = riscv_cpu_do_transaction_failed, | |
1216 | .do_unaligned_access = riscv_cpu_do_unaligned_access, | |
b5f6379d BM |
1217 | .debug_excp_handler = riscv_cpu_debug_excp_handler, |
1218 | .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, | |
1219 | .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, | |
78271684 CF |
1220 | #endif /* !CONFIG_USER_ONLY */ |
1221 | }; | |
1222 | ||
dc5bd18f MC |
1223 | static void riscv_cpu_class_init(ObjectClass *c, void *data) |
1224 | { | |
1225 | RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); | |
1226 | CPUClass *cc = CPU_CLASS(c); | |
1227 | DeviceClass *dc = DEVICE_CLASS(c); | |
4fa485a7 | 1228 | ResettableClass *rc = RESETTABLE_CLASS(c); |
dc5bd18f | 1229 | |
41fbbba7 MZ |
1230 | device_class_set_parent_realize(dc, riscv_cpu_realize, |
1231 | &mcc->parent_realize); | |
dc5bd18f | 1232 | |
4fa485a7 PM |
1233 | resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL, |
1234 | &mcc->parent_phases); | |
dc5bd18f MC |
1235 | |
1236 | cc->class_by_name = riscv_cpu_class_by_name; | |
1237 | cc->has_work = riscv_cpu_has_work; | |
dc5bd18f MC |
1238 | cc->dump_state = riscv_cpu_dump_state; |
1239 | cc->set_pc = riscv_cpu_set_pc; | |
e4fdf9df | 1240 | cc->get_pc = riscv_cpu_get_pc; |
dc5bd18f MC |
1241 | cc->gdb_read_register = riscv_cpu_gdb_read_register; |
1242 | cc->gdb_write_register = riscv_cpu_gdb_write_register; | |
5371f5cd | 1243 | cc->gdb_num_core_regs = 33; |
dc5bd18f MC |
1244 | cc->gdb_stop_before_watchpoint = true; |
1245 | cc->disas_set_info = riscv_cpu_disas_set_info; | |
8a4ca3c1 | 1246 | #ifndef CONFIG_USER_ONLY |
8b80bd28 | 1247 | cc->sysemu_ops = &riscv_sysemu_ops; |
dc5bd18f | 1248 | #endif |
edf64786 | 1249 | cc->gdb_arch_name = riscv_gdb_arch_name; |
b93777e1 | 1250 | cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; |
78271684 | 1251 | cc->tcg_ops = &riscv_tcg_ops; |
6a3d2e7c | 1252 | |
4f67d30b | 1253 | device_class_set_props(dc, riscv_cpu_properties); |
dc5bd18f MC |
1254 | } |
1255 | ||
a775398b AP |
1256 | static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) |
1257 | { | |
1258 | char *old = *isa_str; | |
1259 | char *new = *isa_str; | |
1260 | int i; | |
1261 | ||
a775398b | 1262 | for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { |
9a1f054d AP |
1263 | if (isa_edata_arr[i].multi_letter && |
1264 | isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { | |
a775398b AP |
1265 | new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); |
1266 | g_free(old); | |
1267 | old = new; | |
1268 | } | |
1269 | } | |
1270 | ||
1271 | *isa_str = new; | |
1272 | } | |
1273 | ||
dc5bd18f MC |
1274 | char *riscv_isa_string(RISCVCPU *cpu) |
1275 | { | |
1276 | int i; | |
0e2c3770 | 1277 | const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); |
d1fd31f8 MC |
1278 | char *isa_str = g_new(char, maxlen); |
1279 | char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); | |
0e2c3770 TO |
1280 | for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { |
1281 | if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { | |
1282 | *p++ = qemu_tolower(riscv_single_letter_exts[i]); | |
dc5bd18f MC |
1283 | } |
1284 | } | |
d1fd31f8 | 1285 | *p = '\0'; |
a4a9a443 TO |
1286 | if (!cpu->cfg.short_isa_string) { |
1287 | riscv_isa_string_ext(cpu, &isa_str, maxlen); | |
1288 | } | |
d1fd31f8 | 1289 | return isa_str; |
dc5bd18f MC |
1290 | } |
1291 | ||
eab15862 | 1292 | static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) |
dc5bd18f | 1293 | { |
eab15862 MC |
1294 | ObjectClass *class_a = (ObjectClass *)a; |
1295 | ObjectClass *class_b = (ObjectClass *)b; | |
1296 | const char *name_a, *name_b; | |
dc5bd18f | 1297 | |
eab15862 MC |
1298 | name_a = object_class_get_name(class_a); |
1299 | name_b = object_class_get_name(class_b); | |
1300 | return strcmp(name_a, name_b); | |
dc5bd18f MC |
1301 | } |
1302 | ||
eab15862 | 1303 | static void riscv_cpu_list_entry(gpointer data, gpointer user_data) |
dc5bd18f | 1304 | { |
eab15862 MC |
1305 | const char *typename = object_class_get_name(OBJECT_CLASS(data)); |
1306 | int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); | |
dc5bd18f | 1307 | |
0442428a | 1308 | qemu_printf("%.*s\n", len, typename); |
eab15862 | 1309 | } |
dc5bd18f | 1310 | |
0442428a | 1311 | void riscv_cpu_list(void) |
eab15862 | 1312 | { |
eab15862 MC |
1313 | GSList *list; |
1314 | ||
1315 | list = object_class_get_list(TYPE_RISCV_CPU, false); | |
1316 | list = g_slist_sort(list, riscv_cpu_list_compare); | |
0442428a | 1317 | g_slist_foreach(list, riscv_cpu_list_entry, NULL); |
eab15862 | 1318 | g_slist_free(list); |
dc5bd18f MC |
1319 | } |
1320 | ||
eab15862 MC |
1321 | #define DEFINE_CPU(type_name, initfn) \ |
1322 | { \ | |
1323 | .name = type_name, \ | |
1324 | .parent = TYPE_RISCV_CPU, \ | |
1325 | .instance_init = initfn \ | |
1326 | } | |
1327 | ||
1328 | static const TypeInfo riscv_cpu_type_infos[] = { | |
1329 | { | |
1330 | .name = TYPE_RISCV_CPU, | |
1331 | .parent = TYPE_CPU, | |
1332 | .instance_size = sizeof(RISCVCPU), | |
5de5b99b | 1333 | .instance_align = __alignof__(RISCVCPU), |
eab15862 MC |
1334 | .instance_init = riscv_cpu_init, |
1335 | .abstract = true, | |
1336 | .class_size = sizeof(RISCVCPUClass), | |
1337 | .class_init = riscv_cpu_class_init, | |
1338 | }, | |
1339 | DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), | |
10f1ca27 YJ |
1340 | #if defined(CONFIG_KVM) |
1341 | DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), | |
1342 | #endif | |
eab15862 | 1343 | #if defined(TARGET_RISCV32) |
094b072c | 1344 | DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), |
e8905c6c | 1345 | DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), |
114baaca | 1346 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), |
2fdd2c09 | 1347 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), |
114baaca | 1348 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), |
eab15862 | 1349 | #elif defined(TARGET_RISCV64) |
094b072c | 1350 | DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), |
114baaca AF |
1351 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), |
1352 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), | |
6ddc7069 | 1353 | DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), |
332dab68 | 1354 | DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), |
eab15862 MC |
1355 | #endif |
1356 | }; | |
1357 | ||
1358 | DEFINE_TYPES(riscv_cpu_type_infos) |