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target/riscv: remove kvm-stub.c
[mirror_qemu.git] / target / riscv / cpu.c
CommitLineData
dc5bd18f
MC		 1/*
2 * QEMU RISC-V CPU
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "qemu/osdep.h"
0442428a 21#include "qemu/qemu-print.h"
856dfd8a 22#include "qemu/ctype.h"
dc5bd18f
MC		 23#include "qemu/log.h"
24#include "cpu.h"
95bd8daa 25#include "cpu_vendorid.h"
f7697f0e 26#include "internals.h"
dc5bd18f
MC		 27#include "exec/exec-all.h"
28#include "qapi/error.h"
6f23aaeb 29#include "qapi/visitor.h"
b55d7d34 30#include "qemu/error-report.h"
c4e95030 31#include "hw/qdev-properties.h"
dc5bd18f 32#include "migration/vmstate.h"
135b03cb 33#include "fpu/softfloat-helpers.h"
ad40be27 34#include "sysemu/kvm.h"
eddabb6b 35#include "sysemu/tcg.h"
ad40be27 36#include "kvm_riscv.h"
0489d5bd 37#include "tcg/tcg.h"
dc5bd18f
MC		 38
39/* RISC-V CPU definitions */
0e2c3770 40static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
dc5bd18f 41
a775398b
AP		 42struct isa_ext_data {
43 const char *name;
9a1f054d
AP		 44 int min_version;
45 int ext_enable_offset;
a775398b
AP		 46};
47
ccc84a75 48#define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \
238fd586 49 {#_name, _min_ver, CPU_CFG_OFFSET(_prop)}
9a1f054d 50
b227f6a8
IK		 51/*
52 * From vector_helper.c
53 * Note that vector data is stored in host-endian 64-bit chunks,
54 * so addressing bytes needs a host-endian fixup.
55 */
56#if HOST_BIG_ENDIAN
57#define BYTE(x) ((x) ^ 7)
58#else
59#define BYTE(x) (x)
60#endif
61
3b57254d 62/*
9a1f054d
AP		 63 * Here are the ordering rules of extension naming defined by RISC-V
64 * specification :
65 * 1. All extensions should be separated from other multi-letter extensions
66 * by an underscore.
67 * 2. The first letter following the 'Z' conventionally indicates the most
68 * closely related alphabetical extension category, IMAFDQLCBKJTPVH.
69 * If multiple 'Z' extensions are named, they should be ordered first
70 * by category, then alphabetically within a category.
71 * 3. Standard supervisor-level extensions (starts with 'S') should be
72 * listed after standard unprivileged extensions. If multiple
73 * supervisor-level extensions are listed, they should be ordered
74 * alphabetically.
75 * 4. Non-standard extensions (starts with 'X') must be listed after all
76 * standard extensions. They must be separated from other multi-letter
77 * extensions by an underscore.
6508272a
DHB		 78 *
79 * Single letter extensions are checked in riscv_cpu_validate_misa_priv()
80 * instead.
9a1f054d
AP		 81 */
82static const struct isa_ext_data isa_edata_arr[] = {
ccc84a75
DHB		 83 ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom),
84 ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz),
85 ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond),
86 ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr),
87 ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei),
0228aca2 88 ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl),
ccc84a75 89 ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause),
50f94649 90 ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul),
ccc84a75 91 ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs),
a47842d1 92 ISA_EXT_DATA_ENTRY(zfa, PRIV_VERSION_1_12_0, ext_zfa),
889caa44 93 ISA_EXT_DATA_ENTRY(zfbfmin, PRIV_VERSION_1_12_0, ext_zfbfmin),
ccc84a75
DHB		 94 ISA_EXT_DATA_ENTRY(zfh, PRIV_VERSION_1_11_0, ext_zfh),
95 ISA_EXT_DATA_ENTRY(zfhmin, PRIV_VERSION_1_11_0, ext_zfhmin),
96 ISA_EXT_DATA_ENTRY(zfinx, PRIV_VERSION_1_12_0, ext_zfinx),
97 ISA_EXT_DATA_ENTRY(zdinx, PRIV_VERSION_1_12_0, ext_zdinx),
98 ISA_EXT_DATA_ENTRY(zca, PRIV_VERSION_1_12_0, ext_zca),
99 ISA_EXT_DATA_ENTRY(zcb, PRIV_VERSION_1_12_0, ext_zcb),
100 ISA_EXT_DATA_ENTRY(zcf, PRIV_VERSION_1_12_0, ext_zcf),
101 ISA_EXT_DATA_ENTRY(zcd, PRIV_VERSION_1_12_0, ext_zcd),
102 ISA_EXT_DATA_ENTRY(zce, PRIV_VERSION_1_12_0, ext_zce),
103 ISA_EXT_DATA_ENTRY(zcmp, PRIV_VERSION_1_12_0, ext_zcmp),
104 ISA_EXT_DATA_ENTRY(zcmt, PRIV_VERSION_1_12_0, ext_zcmt),
105 ISA_EXT_DATA_ENTRY(zba, PRIV_VERSION_1_12_0, ext_zba),
106 ISA_EXT_DATA_ENTRY(zbb, PRIV_VERSION_1_12_0, ext_zbb),
107 ISA_EXT_DATA_ENTRY(zbc, PRIV_VERSION_1_12_0, ext_zbc),
108 ISA_EXT_DATA_ENTRY(zbkb, PRIV_VERSION_1_12_0, ext_zbkb),
109 ISA_EXT_DATA_ENTRY(zbkc, PRIV_VERSION_1_12_0, ext_zbkc),
110 ISA_EXT_DATA_ENTRY(zbkx, PRIV_VERSION_1_12_0, ext_zbkx),
111 ISA_EXT_DATA_ENTRY(zbs, PRIV_VERSION_1_12_0, ext_zbs),
112 ISA_EXT_DATA_ENTRY(zk, PRIV_VERSION_1_12_0, ext_zk),
113 ISA_EXT_DATA_ENTRY(zkn, PRIV_VERSION_1_12_0, ext_zkn),
114 ISA_EXT_DATA_ENTRY(zknd, PRIV_VERSION_1_12_0, ext_zknd),
115 ISA_EXT_DATA_ENTRY(zkne, PRIV_VERSION_1_12_0, ext_zkne),
116 ISA_EXT_DATA_ENTRY(zknh, PRIV_VERSION_1_12_0, ext_zknh),
117 ISA_EXT_DATA_ENTRY(zkr, PRIV_VERSION_1_12_0, ext_zkr),
118 ISA_EXT_DATA_ENTRY(zks, PRIV_VERSION_1_12_0, ext_zks),
119 ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed),
120 ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh),
121 ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt),
06028472 122 ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
e13c7d3b 123 ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
ccc84a75
DHB		 124 ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
125 ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
126 ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
889caa44
WL		 127 ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
128 ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
ccc84a75
DHB		 129 ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
130 ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin),
767eb035 131 ISA_EXT_DATA_ENTRY(zvkg, PRIV_VERSION_1_12_0, ext_zvkg),
e972bf22 132 ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned),
fcf19433
KO		 133 ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha),
134 ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb),
8b045ff4 135 ISA_EXT_DATA_ENTRY(zvksed, PRIV_VERSION_1_12_0, ext_zvksed),
2350881c 136 ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh),
ccc84a75
DHB		 137 ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
138 ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
139 ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
03d7bbfd 140 ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, epmp),
3594e3e5 141 ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
ccc84a75
DHB		 142 ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
143 ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf),
144 ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
145 ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu),
146 ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
147 ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
148 ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
149 ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
150 ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb),
151 ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs),
152 ISA_EXT_DATA_ENTRY(xtheadcmo, PRIV_VERSION_1_11_0, ext_xtheadcmo),
153 ISA_EXT_DATA_ENTRY(xtheadcondmov, PRIV_VERSION_1_11_0, ext_xtheadcondmov),
154 ISA_EXT_DATA_ENTRY(xtheadfmemidx, PRIV_VERSION_1_11_0, ext_xtheadfmemidx),
155 ISA_EXT_DATA_ENTRY(xtheadfmv, PRIV_VERSION_1_11_0, ext_xtheadfmv),
156 ISA_EXT_DATA_ENTRY(xtheadmac, PRIV_VERSION_1_11_0, ext_xtheadmac),
157 ISA_EXT_DATA_ENTRY(xtheadmemidx, PRIV_VERSION_1_11_0, ext_xtheadmemidx),
158 ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempair),
159 ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync),
160 ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
9a1f054d
AP		 161};
162
549cbf78
DHB		 163/* Hash that stores user set extensions */
164static GHashTable *multi_ext_user_opts;
165
36c1118d 166bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
9a1f054d 167{
5f2c80f1 168 bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
9a1f054d
AP		 169
170 return *ext_enabled;
171}
172
36c1118d 173void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en)
9a1f054d 174{
5f2c80f1 175 bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
9a1f054d
AP		 176
177 *ext_enabled = en;
178}
179
36c1118d 180int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
997e7195
DHB		 181{
182 int i;
183
184 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
185 if (isa_edata_arr[i].ext_enable_offset != ext_offset) {
186 continue;
187 }
188
189 return isa_edata_arr[i].min_version;
190 }
191
192 g_assert_not_reached();
193}
194
36c1118d 195bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
0a9eb9b4
DHB		 196{
197 return g_hash_table_contains(multi_ext_user_opts,
198 GUINT_TO_POINTER(ext_offset));
199}
200
dc5bd18f 201const char * const riscv_int_regnames[] = {
c45eff30
WL		 202 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
203 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
204 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4",
205 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
206 "x28/t3", "x29/t4", "x30/t5", "x31/t6"
dc5bd18f
MC		 207};
208
2b547084 209const char * const riscv_int_regnamesh[] = {
c45eff30
WL		 210 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h",
211 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h",
212 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h",
213 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h",
214 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h",
215 "x30h/t5h", "x31h/t6h"
2b547084
FP		 216};
217
dc5bd18f 218const char * const riscv_fpr_regnames[] = {
c45eff30
WL		 219 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5",
220 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1",
221 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7",
222 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7",
223 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
224 "f30/ft10", "f31/ft11"
dc5bd18f
MC		 225};
226
b227f6a8
IK		 227const char * const riscv_rvv_regnames[] = {
228 "v0", "v1", "v2", "v3", "v4", "v5", "v6",
229 "v7", "v8", "v9", "v10", "v11", "v12", "v13",
230 "v14", "v15", "v16", "v17", "v18", "v19", "v20",
231 "v21", "v22", "v23", "v24", "v25", "v26", "v27",
232 "v28", "v29", "v30", "v31"
233};
234
9a575d33 235static const char * const riscv_excp_names[] = {
dc5bd18f
MC		 236 "misaligned_fetch",
237 "fault_fetch",
238 "illegal_instruction",
239 "breakpoint",
240 "misaligned_load",
241 "fault_load",
242 "misaligned_store",
243 "fault_store",
244 "user_ecall",
245 "supervisor_ecall",
246 "hypervisor_ecall",
247 "machine_ecall",
248 "exec_page_fault",
249 "load_page_fault",
250 "reserved",
fd990e86 251 "store_page_fault",
ab67a1d0
AF		 252 "reserved",
253 "reserved",
254 "reserved",
255 "reserved",
256 "guest_exec_page_fault",
257 "guest_load_page_fault",
258 "reserved",
fd990e86 259 "guest_store_page_fault",
dc5bd18f
MC		 260};
261
9a575d33 262static const char * const riscv_intr_names[] = {
dc5bd18f
MC		 263 "u_software",
264 "s_software",
205377f8 265 "vs_software",
dc5bd18f
MC		 266 "m_software",
267 "u_timer",
268 "s_timer",
205377f8 269 "vs_timer",
dc5bd18f
MC		 270 "m_timer",
271 "u_external",
6cfcf775 272 "s_external",
205377f8 273 "vs_external",
dc5bd18f 274 "m_external",
426f0348
MC		 275 "reserved",
276 "reserved",
277 "reserved",
278 "reserved"
dc5bd18f
MC		 279};
280
dd8f244f 281static void riscv_cpu_add_user_properties(Object *obj);
b97e5a6b 282static void riscv_init_max_cpu_extensions(Object *obj);
26b2bc58 283
c51a3f5d
YJ		 284const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
285{
286 if (async) {
287 return (cause < ARRAY_SIZE(riscv_intr_names)) ?
288 riscv_intr_names[cause] : "(unknown)";
289 } else {
290 return (cause < ARRAY_SIZE(riscv_excp_names)) ?
291 riscv_excp_names[cause] : "(unknown)";
292 }
293}
294
e91a7227 295static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
dc5bd18f 296{
e91a7227
RH		 297 env->misa_mxl_max = env->misa_mxl = mxl;
298 env->misa_ext_mask = env->misa_ext = ext;
dc5bd18f
MC		 299}
300
6f23aaeb
AG		 301#ifndef CONFIG_USER_ONLY
302static uint8_t satp_mode_from_str(const char *satp_mode_str)
303{
304 if (!strncmp(satp_mode_str, "mbare", 5)) {
305 return VM_1_10_MBARE;
306 }
307
308 if (!strncmp(satp_mode_str, "sv32", 4)) {
309 return VM_1_10_SV32;
310 }
311
312 if (!strncmp(satp_mode_str, "sv39", 4)) {
313 return VM_1_10_SV39;
314 }
315
316 if (!strncmp(satp_mode_str, "sv48", 4)) {
317 return VM_1_10_SV48;
318 }
319
320 if (!strncmp(satp_mode_str, "sv57", 4)) {
321 return VM_1_10_SV57;
322 }
323
324 if (!strncmp(satp_mode_str, "sv64", 4)) {
325 return VM_1_10_SV64;
326 }
327
328 g_assert_not_reached();
329}
330
331uint8_t satp_mode_max_from_map(uint32_t map)
332{
3a2fc235
DHB		 333 /*
334 * 'map = 0' will make us return (31 - 32), which C will
335 * happily overflow to UINT_MAX. There's no good result to
336 * return if 'map = 0' (e.g. returning 0 will be ambiguous
337 * with the result for 'map = 1').
338 *
339 * Assert out if map = 0. Callers will have to deal with
340 * it outside of this function.
341 */
342 g_assert(map > 0);
343
6f23aaeb
AG		 344 /* map here has at least one bit set, so no problem with clz */
345 return 31 - __builtin_clz(map);
346}
347
348const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit)
349{
350 if (is_32_bit) {
351 switch (satp_mode) {
352 case VM_1_10_SV32:
353 return "sv32";
354 case VM_1_10_MBARE:
355 return "none";
356 }
357 } else {
358 switch (satp_mode) {
359 case VM_1_10_SV64:
360 return "sv64";
361 case VM_1_10_SV57:
362 return "sv57";
363 case VM_1_10_SV48:
364 return "sv48";
365 case VM_1_10_SV39:
366 return "sv39";
367 case VM_1_10_MBARE:
368 return "none";
369 }
370 }
371
372 g_assert_not_reached();
373}
374
6df3747a
AG		 375static void set_satp_mode_max_supported(RISCVCPU *cpu,
376 uint8_t satp_mode)
6f23aaeb
AG		 377{
378 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32;
6df3747a 379 const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64;
6f23aaeb 380
6df3747a
AG		 381 for (int i = 0; i <= satp_mode; ++i) {
382 if (valid_vm[i]) {
383 cpu->cfg.satp_mode.supported |= (1 << i);
384 }
6f23aaeb
AG		 385 }
386}
6df3747a
AG		 387
388/* Set the satp mode to the max supported */
389static void set_satp_mode_default_map(RISCVCPU *cpu)
390{
391 cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported;
392}
6f23aaeb
AG		 393#endif
394
dc5bd18f
MC		 395static void riscv_any_cpu_init(Object *obj)
396{
7f0bdfb5
DHB		 397 RISCVCPU *cpu = RISCV_CPU(obj);
398 CPURISCVState *env = &cpu->env;
3820602f 399#if defined(TARGET_RISCV32)
e91a7227 400 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
3820602f 401#elif defined(TARGET_RISCV64)
e91a7227 402 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
3820602f 403#endif
6df3747a
AG		 404
405#ifndef CONFIG_USER_ONLY
406 set_satp_mode_max_supported(RISCV_CPU(obj),
c45eff30
WL		 407 riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ?
408 VM_1_10_SV32 : VM_1_10_SV57);
6df3747a
AG		 409#endif
410
b9a2b98e 411 env->priv_ver = PRIV_VERSION_LATEST;
7f0bdfb5
DHB		 412
413 /* inherited from parent obj via riscv_cpu_init() */
414 cpu->cfg.ext_ifencei = true;
415 cpu->cfg.ext_icsr = true;
416 cpu->cfg.mmu = true;
417 cpu->cfg.pmp = true;
dc5bd18f
MC		 418}
419
b97e5a6b
DHB		 420static void riscv_max_cpu_init(Object *obj)
421{
422 RISCVCPU *cpu = RISCV_CPU(obj);
423 CPURISCVState *env = &cpu->env;
424 RISCVMXL mlx = MXL_RV64;
425
426#ifdef TARGET_RISCV32
427 mlx = MXL_RV32;
428#endif
429 set_misa(env, mlx, 0);
b97e5a6b
DHB		 430 env->priv_ver = PRIV_VERSION_LATEST;
431#ifndef CONFIG_USER_ONLY
432 set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ?
433 VM_1_10_SV32 : VM_1_10_SV57);
434#endif
435}
436
094b072c
AF		 437#if defined(TARGET_RISCV64)
438static void rv64_base_cpu_init(Object *obj)
8903bf6e
AF		 439{
440 CPURISCVState *env = &RISCV_CPU(obj)->env;
b55d7d34 441 /* We set this in the realise function */
e91a7227 442 set_misa(env, MXL_RV64, 0);
18800095 443 /* Set latest version of privileged specification */
b9a2b98e 444 env->priv_ver = PRIV_VERSION_LATEST;
6df3747a
AG		 445#ifndef CONFIG_USER_ONLY
446 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
447#endif
8903bf6e
AF		 448}
449
114baaca 450static void rv64_sifive_u_cpu_init(Object *obj)
dc5bd18f 451{
7f0bdfb5
DHB		 452 RISCVCPU *cpu = RISCV_CPU(obj);
453 CPURISCVState *env = &cpu->env;
e91a7227 454 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
8c6eeb50 455 env->priv_ver = PRIV_VERSION_1_10_0;
6df3747a
AG		 456#ifndef CONFIG_USER_ONLY
457 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39);
458#endif
7f0bdfb5
DHB		 459
460 /* inherited from parent obj via riscv_cpu_init() */
461 cpu->cfg.ext_ifencei = true;
462 cpu->cfg.ext_icsr = true;
463 cpu->cfg.mmu = true;
464 cpu->cfg.pmp = true;
dc5bd18f
MC		 465}
466
114baaca 467static void rv64_sifive_e_cpu_init(Object *obj)
36b80ad9
AF		 468{
469 CPURISCVState *env = &RISCV_CPU(obj)->env;
26b2bc58
AF		 470 RISCVCPU *cpu = RISCV_CPU(obj);
471
e91a7227 472 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
8c6eeb50 473 env->priv_ver = PRIV_VERSION_1_10_0;
6df3747a
AG		 474#ifndef CONFIG_USER_ONLY
475 set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
476#endif
7f0bdfb5
DHB		 477
478 /* inherited from parent obj via riscv_cpu_init() */
479 cpu->cfg.ext_ifencei = true;
480 cpu->cfg.ext_icsr = true;
481 cpu->cfg.pmp = true;
36b80ad9 482}
332dab68 483
95bd8daa
CM		 484static void rv64_thead_c906_cpu_init(Object *obj)
485{
486 CPURISCVState *env = &RISCV_CPU(obj)->env;
487 RISCVCPU *cpu = RISCV_CPU(obj);
488
4f13abcb 489 set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU);
8c6eeb50 490 env->priv_ver = PRIV_VERSION_1_11_0;
95bd8daa 491
a47842d1 492 cpu->cfg.ext_zfa = true;
95bd8daa
CM		 493 cpu->cfg.ext_zfh = true;
494 cpu->cfg.mmu = true;
495 cpu->cfg.ext_xtheadba = true;
496 cpu->cfg.ext_xtheadbb = true;
497 cpu->cfg.ext_xtheadbs = true;
498 cpu->cfg.ext_xtheadcmo = true;
499 cpu->cfg.ext_xtheadcondmov = true;
500 cpu->cfg.ext_xtheadfmemidx = true;
501 cpu->cfg.ext_xtheadmac = true;
502 cpu->cfg.ext_xtheadmemidx = true;
503 cpu->cfg.ext_xtheadmempair = true;
504 cpu->cfg.ext_xtheadsync = true;
505
506 cpu->cfg.mvendorid = THEAD_VENDOR_ID;
6df3747a
AG		 507#ifndef CONFIG_USER_ONLY
508 set_satp_mode_max_supported(cpu, VM_1_10_SV39);
509#endif
7f0bdfb5
DHB		 510
511 /* inherited from parent obj via riscv_cpu_init() */
512 cpu->cfg.pmp = true;
95bd8daa
CM		 513}
514
e1d084a8
RP		 515static void rv64_veyron_v1_cpu_init(Object *obj)
516{
517 CPURISCVState *env = &RISCV_CPU(obj)->env;
518 RISCVCPU *cpu = RISCV_CPU(obj);
519
520 set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH);
521 env->priv_ver = PRIV_VERSION_1_12_0;
522
523 /* Enable ISA extensions */
524 cpu->cfg.mmu = true;
029f5fee
DHB		 525 cpu->cfg.ext_ifencei = true;
526 cpu->cfg.ext_icsr = true;
527 cpu->cfg.pmp = true;
e1d084a8
RP		 528 cpu->cfg.ext_icbom = true;
529 cpu->cfg.cbom_blocksize = 64;
530 cpu->cfg.cboz_blocksize = 64;
531 cpu->cfg.ext_icboz = true;
532 cpu->cfg.ext_smaia = true;
533 cpu->cfg.ext_ssaia = true;
534 cpu->cfg.ext_sscofpmf = true;
535 cpu->cfg.ext_sstc = true;
536 cpu->cfg.ext_svinval = true;
537 cpu->cfg.ext_svnapot = true;
538 cpu->cfg.ext_svpbmt = true;
539 cpu->cfg.ext_smstateen = true;
540 cpu->cfg.ext_zba = true;
541 cpu->cfg.ext_zbb = true;
542 cpu->cfg.ext_zbc = true;
543 cpu->cfg.ext_zbs = true;
544 cpu->cfg.ext_XVentanaCondOps = true;
545
546 cpu->cfg.mvendorid = VEYRON_V1_MVENDORID;
547 cpu->cfg.marchid = VEYRON_V1_MARCHID;
548 cpu->cfg.mimpid = VEYRON_V1_MIMPID;
549
550#ifndef CONFIG_USER_ONLY
551 set_satp_mode_max_supported(cpu, VM_1_10_SV48);
552#endif
553}
554
332dab68
FP		 555static void rv128_base_cpu_init(Object *obj)
556{
557 if (qemu_tcg_mttcg_enabled()) {
558 /* Missing 128-bit aligned atomics */
559 error_report("128-bit RISC-V currently does not work with Multi "
560 "Threaded TCG. Please use: -accel tcg,thread=single");
561 exit(EXIT_FAILURE);
562 }
563 CPURISCVState *env = &RISCV_CPU(obj)->env;
564 /* We set this in the realise function */
565 set_misa(env, MXL_RV128, 0);
18800095 566 /* Set latest version of privileged specification */
b9a2b98e 567 env->priv_ver = PRIV_VERSION_LATEST;
6df3747a
AG		 568#ifndef CONFIG_USER_ONLY
569 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
570#endif
332dab68 571}
114baaca 572#else
094b072c
AF		 573static void rv32_base_cpu_init(Object *obj)
574{
575 CPURISCVState *env = &RISCV_CPU(obj)->env;
576 /* We set this in the realise function */
e91a7227 577 set_misa(env, MXL_RV32, 0);
18800095 578 /* Set latest version of privileged specification */
b9a2b98e 579 env->priv_ver = PRIV_VERSION_LATEST;
6df3747a
AG		 580#ifndef CONFIG_USER_ONLY
581 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
582#endif
094b072c
AF		 583}
584
114baaca
AF		 585static void rv32_sifive_u_cpu_init(Object *obj)
586{
7f0bdfb5
DHB		 587 RISCVCPU *cpu = RISCV_CPU(obj);
588 CPURISCVState *env = &cpu->env;
e91a7227 589 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
8c6eeb50 590 env->priv_ver = PRIV_VERSION_1_10_0;
6df3747a
AG		 591#ifndef CONFIG_USER_ONLY
592 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
593#endif
7f0bdfb5
DHB		 594
595 /* inherited from parent obj via riscv_cpu_init() */
596 cpu->cfg.ext_ifencei = true;
597 cpu->cfg.ext_icsr = true;
598 cpu->cfg.mmu = true;
599 cpu->cfg.pmp = true;
114baaca 600}
36b80ad9 601
114baaca
AF		 602static void rv32_sifive_e_cpu_init(Object *obj)
603{
604 CPURISCVState *env = &RISCV_CPU(obj)->env;
26b2bc58
AF		 605 RISCVCPU *cpu = RISCV_CPU(obj);
606
e91a7227 607 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
8c6eeb50 608 env->priv_ver = PRIV_VERSION_1_10_0;
6df3747a
AG		 609#ifndef CONFIG_USER_ONLY
610 set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
611#endif
7f0bdfb5
DHB		 612
613 /* inherited from parent obj via riscv_cpu_init() */
614 cpu->cfg.ext_ifencei = true;
615 cpu->cfg.ext_icsr = true;
616 cpu->cfg.pmp = true;
114baaca 617}
d8e72bd1 618
e8905c6c 619static void rv32_ibex_cpu_init(Object *obj)
dc5bd18f
MC		 620{
621 CPURISCVState *env = &RISCV_CPU(obj)->env;
26b2bc58
AF		 622 RISCVCPU *cpu = RISCV_CPU(obj);
623
e91a7227 624 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
8c6eeb50 625 env->priv_ver = PRIV_VERSION_1_11_0;
6df3747a
AG		 626#ifndef CONFIG_USER_ONLY
627 set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
628#endif
26b2bc58 629 cpu->cfg.epmp = true;
7f0bdfb5
DHB		 630
631 /* inherited from parent obj via riscv_cpu_init() */
632 cpu->cfg.ext_ifencei = true;
633 cpu->cfg.ext_icsr = true;
634 cpu->cfg.pmp = true;
dc5bd18f
MC		 635}
636
2fdd2c09 637static void rv32_imafcu_nommu_cpu_init(Object *obj)
d784733b
CW		 638{
639 CPURISCVState *env = &RISCV_CPU(obj)->env;
26b2bc58
AF		 640 RISCVCPU *cpu = RISCV_CPU(obj);
641
e91a7227 642 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
8c6eeb50 643 env->priv_ver = PRIV_VERSION_1_10_0;
6df3747a
AG		 644#ifndef CONFIG_USER_ONLY
645 set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
646#endif
7f0bdfb5
DHB		 647
648 /* inherited from parent obj via riscv_cpu_init() */
649 cpu->cfg.ext_ifencei = true;
650 cpu->cfg.ext_icsr = true;
651 cpu->cfg.pmp = true;
d784733b 652}
eab15862 653#endif
dc5bd18f
MC		 654
655static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
656{
657 ObjectClass *oc;
658 char *typename;
659 char **cpuname;
660
661 cpuname = g_strsplit(cpu_model, ",", 1);
662 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]);
663 oc = object_class_by_name(typename);
664 g_strfreev(cpuname);
665 g_free(typename);
666 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) ||
667 object_class_is_abstract(oc)) {
668 return NULL;
669 }
670 return oc;
671}
672
90c84c56 673static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
dc5bd18f
MC		 674{
675 RISCVCPU *cpu = RISCV_CPU(cs);
676 CPURISCVState *env = &cpu->env;
b227f6a8
IK		 677 int i, j;
678 uint8_t *p;
dc5bd18f 679
df30e652
AF		 680#if !defined(CONFIG_USER_ONLY)
681 if (riscv_has_ext(env, RVH)) {
38256529 682 qemu_fprintf(f, " %s %d\n", "V = ", env->virt_enabled);
df30e652
AF		 683 }
684#endif
90c84c56 685 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc);
dc5bd18f 686#ifndef CONFIG_USER_ONLY
665b90d8
RH		 687 {
688 static const int dump_csrs[] = {
689 CSR_MHARTID,
690 CSR_MSTATUS,
691 CSR_MSTATUSH,
bc7dca13
BM		 692 /*
693 * CSR_SSTATUS is intentionally omitted here as its value
694 * can be figured out by looking at CSR_MSTATUS
695 */
665b90d8
RH		 696 CSR_HSTATUS,
697 CSR_VSSTATUS,
698 CSR_MIP,
699 CSR_MIE,
700 CSR_MIDELEG,
701 CSR_HIDELEG,
702 CSR_MEDELEG,
703 CSR_HEDELEG,
704 CSR_MTVEC,
705 CSR_STVEC,
706 CSR_VSTVEC,
707 CSR_MEPC,
708 CSR_SEPC,
709 CSR_VSEPC,
710 CSR_MCAUSE,
711 CSR_SCAUSE,
712 CSR_VSCAUSE,
713 CSR_MTVAL,
714 CSR_STVAL,
715 CSR_HTVAL,
716 CSR_MTVAL2,
717 CSR_MSCRATCH,
718 CSR_SSCRATCH,
719 CSR_SATP,
bd5594ca
AB		 720 CSR_MMTE,
721 CSR_UPMBASE,
722 CSR_UPMMASK,
723 CSR_SPMBASE,
724 CSR_SPMMASK,
725 CSR_MPMBASE,
726 CSR_MPMMASK,
665b90d8
RH		 727 };
728
29332994 729 for (i = 0; i < ARRAY_SIZE(dump_csrs); ++i) {
665b90d8
RH		 730 int csrno = dump_csrs[i];
731 target_ulong val = 0;
732 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
733
734 /*
735 * Rely on the smode, hmode, etc, predicates within csr.c
736 * to do the filtering of the registers that are present.
737 */
738 if (res == RISCV_EXCP_NONE) {
739 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
740 csr_ops[csrno].name, val);
741 }
742 }
df30e652 743 }
dc5bd18f
MC		 744#endif
745
746 for (i = 0; i < 32; i++) {
e573a7f3 747 qemu_fprintf(f, " %-8s " TARGET_FMT_lx,
90c84c56 748 riscv_int_regnames[i], env->gpr[i]);
dc5bd18f 749 if ((i & 3) == 3) {
90c84c56 750 qemu_fprintf(f, "\n");
dc5bd18f
MC		 751 }
752 }
86ea1880
RH		 753 if (flags & CPU_DUMP_FPU) {
754 for (i = 0; i < 32; i++) {
e573a7f3 755 qemu_fprintf(f, " %-8s %016" PRIx64,
90c84c56 756 riscv_fpr_regnames[i], env->fpr[i]);
86ea1880 757 if ((i & 3) == 3) {
90c84c56 758 qemu_fprintf(f, "\n");
86ea1880 759 }
dc5bd18f
MC		 760 }
761 }
b227f6a8
IK		 762 if (riscv_has_ext(env, RVV) && (flags & CPU_DUMP_VPU)) {
763 static const int dump_rvv_csrs[] = {
764 CSR_VSTART,
765 CSR_VXSAT,
766 CSR_VXRM,
767 CSR_VCSR,
768 CSR_VL,
769 CSR_VTYPE,
770 CSR_VLENB,
771 };
29332994 772 for (i = 0; i < ARRAY_SIZE(dump_rvv_csrs); ++i) {
b227f6a8
IK		 773 int csrno = dump_rvv_csrs[i];
774 target_ulong val = 0;
775 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
776
777 /*
778 * Rely on the smode, hmode, etc, predicates within csr.c
779 * to do the filtering of the registers that are present.
780 */
781 if (res == RISCV_EXCP_NONE) {
782 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
783 csr_ops[csrno].name, val);
784 }
785 }
786 uint16_t vlenb = cpu->cfg.vlen >> 3;
787
788 for (i = 0; i < 32; i++) {
789 qemu_fprintf(f, " %-8s ", riscv_rvv_regnames[i]);
790 p = (uint8_t *)env->vreg;
791 for (j = vlenb - 1 ; j >= 0; j--) {
792 qemu_fprintf(f, "%02x", *(p + i * vlenb + BYTE(j)));
793 }
794 qemu_fprintf(f, "\n");
795 }
796 }
dc5bd18f
MC		 797}
798
799static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
800{
801 RISCVCPU *cpu = RISCV_CPU(cs);
802 CPURISCVState *env = &cpu->env;
bf9e776e
LZ		 803
804 if (env->xl == MXL_RV32) {
805 env->pc = (int32_t)value;
806 } else {
807 env->pc = value;
808 }
dc5bd18f
MC		 809}
810
e4fdf9df
RH		 811static vaddr riscv_cpu_get_pc(CPUState *cs)
812{
813 RISCVCPU *cpu = RISCV_CPU(cs);
814 CPURISCVState *env = &cpu->env;
815
816 /* Match cpu_get_tb_cpu_state. */
817 if (env->xl == MXL_RV32) {
818 return env->pc & UINT32_MAX;
819 }
820 return env->pc;
821}
822
dc5bd18f
MC		 823static bool riscv_cpu_has_work(CPUState *cs)
824{
825#ifndef CONFIG_USER_ONLY
826 RISCVCPU *cpu = RISCV_CPU(cs);
827 CPURISCVState *env = &cpu->env;
828 /*
829 * Definition of the WFI instruction requires it to ignore the privilege
830 * mode and delegation registers, but respect individual enables
831 */
8f42415f 832 return riscv_cpu_all_pending(env) != 0;
dc5bd18f
MC		 833#else
834 return true;
835#endif
836}
837
4fa485a7 838static void riscv_cpu_reset_hold(Object *obj)
dc5bd18f 839{
43dc93af
AP		 840#ifndef CONFIG_USER_ONLY
841 uint8_t iprio;
842 int i, irq, rdzero;
843#endif
4fa485a7 844 CPUState *cs = CPU(obj);
dc5bd18f
MC		 845 RISCVCPU *cpu = RISCV_CPU(cs);
846 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
847 CPURISCVState *env = &cpu->env;
848
4fa485a7
PM		 849 if (mcc->parent_phases.hold) {
850 mcc->parent_phases.hold(obj);
851 }
dc5bd18f 852#ifndef CONFIG_USER_ONLY
e91a7227 853 env->misa_mxl = env->misa_mxl_max;
dc5bd18f
MC		 854 env->priv = PRV_M;
855 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
92371bd9
RH		 856 if (env->misa_mxl > MXL_RV32) {
857 /*
858 * The reset status of SXL/UXL is undefined, but mstatus is WARL
859 * and we must ensure that the value after init is valid for read.
860 */
861 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl);
862 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl);
5a2ae235
LZ		 863 if (riscv_has_ext(env, RVH)) {
864 env->vsstatus = set_field(env->vsstatus,
865 MSTATUS64_SXL, env->misa_mxl);
866 env->vsstatus = set_field(env->vsstatus,
867 MSTATUS64_UXL, env->misa_mxl);
868 env->mstatus_hs = set_field(env->mstatus_hs,
869 MSTATUS64_SXL, env->misa_mxl);
870 env->mstatus_hs = set_field(env->mstatus_hs,
871 MSTATUS64_UXL, env->misa_mxl);
872 }
92371bd9 873 }
dc5bd18f 874 env->mcause = 0;
881df35d 875 env->miclaim = MIP_SGEIP;
dc5bd18f 876 env->pc = env->resetvec;
62cf0245 877 env->bins = 0;
ec352d0c 878 env->two_stage_lookup = false;
43dc93af 879
0af3f115 880 env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) |
ed67d637 881 (cpu->cfg.ext_svadu ? MENVCFG_ADUE : 0);
0af3f115 882 env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) |
ed67d637 883 (cpu->cfg.ext_svadu ? HENVCFG_ADUE : 0);
7a6613da 884
43dc93af
AP		 885 /* Initialized default priorities of local interrupts. */
886 for (i = 0; i < ARRAY_SIZE(env->miprio); i++) {
887 iprio = riscv_cpu_default_priority(i);
888 env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio;
889 env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio;
890 env->hviprio[i] = 0;
891 }
892 i = 0;
893 while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) {
894 if (!rdzero) {
895 env->hviprio[irq] = env->miprio[irq];
896 }
897 i++;
898 }
4bbe8033 899 /* mmte is supposed to have pm.current hardwired to 1 */
42967f40 900 env->mmte |= (EXT_STATUS_INITIAL | MMTE_M_PM_CURRENT);
dc5bd18f 901#endif
440544e1 902 env->xl = riscv_cpu_mxl(env);
40bfa5f6 903 riscv_cpu_update_mask(env);
330d2ae3 904 cs->exception_index = RISCV_EXCP_NONE;
c13b169f 905 env->load_res = -1;
dc5bd18f 906 set_default_nan_mode(1, &env->fp_status);
ad40be27
YJ		 907
908#ifndef CONFIG_USER_ONLY
cdfb2905 909 if (cpu->cfg.debug) {
a7c272df 910 riscv_trigger_reset_hold(env);
b6092544
BM		 911 }
912
ad40be27
YJ		 913 if (kvm_enabled()) {
914 kvm_riscv_reset_vcpu(cpu);
915 }
916#endif
dc5bd18f
MC		 917}
918
919static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
920{
5c5a47f1 921 RISCVCPU *cpu = RISCV_CPU(s);
94692c3a 922 CPURISCVState *env = &cpu->env;
454c2201 923 info->target_info = &cpu->cfg;
db23e5d9 924
94692c3a 925 switch (env->xl) {
db23e5d9 926 case MXL_RV32:
5c5a47f1 927 info->print_insn = print_insn_riscv32;
db23e5d9
RH		 928 break;
929 case MXL_RV64:
5c5a47f1 930 info->print_insn = print_insn_riscv64;
db23e5d9 931 break;
332dab68
FP		 932 case MXL_RV128:
933 info->print_insn = print_insn_riscv128;
934 break;
db23e5d9
RH		 935 default:
936 g_assert_not_reached();
5c5a47f1 937 }
dc5bd18f
MC		 938}
939
36c1118d 940void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
bd305595
DHB		 941{
942 CPURISCVState *env = &cpu->env;
943 int i;
944
945 /* Force disable extensions if priv spec version does not match */
946 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
5f2c80f1 947 if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset) &&
bd305595 948 (env->priv_ver < isa_edata_arr[i].min_version)) {
5f2c80f1
DHB		 949 isa_ext_update_enabled(cpu, isa_edata_arr[i].ext_enable_offset,
950 false);
bd305595
DHB		 951#ifndef CONFIG_USER_ONLY
952 warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
953 " because privilege spec version does not match",
954 isa_edata_arr[i].name, env->mhartid);
955#else
956 warn_report("disabling %s extension because "
957 "privilege spec version does not match",
958 isa_edata_arr[i].name);
959#endif
960 }
961 }
962}
963
6f23aaeb
AG		 964#ifndef CONFIG_USER_ONLY
965static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp)
966{
967 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32;
3a2fc235
DHB		 968 uint8_t satp_mode_map_max, satp_mode_supported_max;
969
970 /* The CPU wants the OS to decide which satp mode to use */
971 if (cpu->cfg.satp_mode.supported == 0) {
972 return;
973 }
974
975 satp_mode_supported_max =
976 satp_mode_max_from_map(cpu->cfg.satp_mode.supported);
6f23aaeb
AG		 977
978 if (cpu->cfg.satp_mode.map == 0) {
979 if (cpu->cfg.satp_mode.init == 0) {
980 /* If unset by the user, we fallback to the default satp mode. */
981 set_satp_mode_default_map(cpu);
982 } else {
983 /*
984 * Find the lowest level that was disabled and then enable the
985 * first valid level below which can be found in
986 * valid_vm_1_10_32/64.
987 */
988 for (int i = 1; i < 16; ++i) {
6df3747a
AG		 989 if ((cpu->cfg.satp_mode.init & (1 << i)) &&
990 (cpu->cfg.satp_mode.supported & (1 << i))) {
6f23aaeb 991 for (int j = i - 1; j >= 0; --j) {
6df3747a 992 if (cpu->cfg.satp_mode.supported & (1 << j)) {
6f23aaeb
AG		 993 cpu->cfg.satp_mode.map |= (1 << j);
994 break;
995 }
996 }
997 break;
998 }
999 }
1000 }
1001 }
1002
6df3747a
AG		 1003 satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map);
1004
1005 /* Make sure the user asked for a supported configuration (HW and qemu) */
1006 if (satp_mode_map_max > satp_mode_supported_max) {
1007 error_setg(errp, "satp_mode %s is higher than hw max capability %s",
1008 satp_mode_str(satp_mode_map_max, rv32),
1009 satp_mode_str(satp_mode_supported_max, rv32));
1010 return;
6f23aaeb
AG		 1011 }
1012
1013 /*
1014 * Make sure the user did not ask for an invalid configuration as per
1015 * the specification.
1016 */
6f23aaeb 1017 if (!rv32) {
6df3747a 1018 for (int i = satp_mode_map_max - 1; i >= 0; --i) {
6f23aaeb
AG		 1019 if (!(cpu->cfg.satp_mode.map & (1 << i)) &&
1020 (cpu->cfg.satp_mode.init & (1 << i)) &&
6df3747a 1021 (cpu->cfg.satp_mode.supported & (1 << i))) {
6f23aaeb
AG		 1022 error_setg(errp, "cannot disable %s satp mode if %s "
1023 "is enabled", satp_mode_str(i, false),
6df3747a 1024 satp_mode_str(satp_mode_map_max, false));
6f23aaeb
AG		 1025 return;
1026 }
1027 }
1028 }
1029
1030 /* Finally expand the map so that all valid modes are set */
6df3747a
AG		 1031 for (int i = satp_mode_map_max - 1; i >= 0; --i) {
1032 if (cpu->cfg.satp_mode.supported & (1 << i)) {
6f23aaeb
AG		 1033 cpu->cfg.satp_mode.map |= (1 << i);
1034 }
1035 }
1036}
1037#endif
1038
1039static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
1040{
1041#ifndef CONFIG_USER_ONLY
1042 Error *local_err = NULL;
1043
1044 riscv_cpu_satp_mode_finalize(cpu, &local_err);
1045 if (local_err != NULL) {
1046 error_propagate(errp, local_err);
1047 return;
1048 }
1049#endif
1050}
1051
eddabb6b
DHB		 1052static void riscv_cpu_realize(DeviceState *dev, Error **errp)
1053{
1054 CPUState *cs = CPU(dev);
1055 RISCVCPU *cpu = RISCV_CPU(dev);
1056 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
1057 Error *local_err = NULL;
1058
f57d5f80
DHB		 1059 if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_CPU_ANY) != NULL) {
1060 warn_report("The 'any' CPU is deprecated and will be "
1061 "removed in the future.");
1062 }
1063
eddabb6b
DHB		 1064 cpu_exec_realizefn(cs, &local_err);
1065 if (local_err != NULL) {
1066 error_propagate(errp, local_err);
1067 return;
1068 }
1069
6f23aaeb
AG		 1070 riscv_cpu_finalize_features(cpu, &local_err);
1071 if (local_err != NULL) {
1072 error_propagate(errp, local_err);
1073 return;
1074 }
1075
5371f5cd
JW		 1076 riscv_cpu_register_gdb_regs_for_features(cs);
1077
a7c272df
AO		 1078#ifndef CONFIG_USER_ONLY
1079 if (cpu->cfg.debug) {
1080 riscv_trigger_realize(&cpu->env);
1081 }
1082#endif
1083
dc5bd18f
MC		 1084 qemu_init_vcpu(cs);
1085 cpu_reset(cs);
1086
1087 mcc->parent_realize(dev, errp);
1088}
1089
0f0b70ee 1090#ifndef CONFIG_USER_ONLY
6f23aaeb
AG		 1091static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name,
1092 void *opaque, Error **errp)
1093{
1094 RISCVSATPMap *satp_map = opaque;
1095 uint8_t satp = satp_mode_from_str(name);
1096 bool value;
1097
1098 value = satp_map->map & (1 << satp);
1099
1100 visit_type_bool(v, name, &value, errp);
1101}
1102
1103static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name,
1104 void *opaque, Error **errp)
1105{
1106 RISCVSATPMap *satp_map = opaque;
1107 uint8_t satp = satp_mode_from_str(name);
1108 bool value;
1109
1110 if (!visit_type_bool(v, name, &value, errp)) {
1111 return;
1112 }
1113
1114 satp_map->map = deposit32(satp_map->map, satp, 1, value);
1115 satp_map->init |= 1 << satp;
1116}
1117
7d0c302c 1118void riscv_add_satp_mode_properties(Object *obj)
6f23aaeb
AG		 1119{
1120 RISCVCPU *cpu = RISCV_CPU(obj);
1121
1122 if (cpu->env.misa_mxl == MXL_RV32) {
1123 object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp,
1124 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
1125 } else {
1126 object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp,
1127 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
1128 object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp,
1129 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
1130 object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp,
1131 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
1132 object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp,
1133 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
1134 }
1135}
1136
0f0b70ee
AF		 1137static void riscv_cpu_set_irq(void *opaque, int irq, int level)
1138{
1139 RISCVCPU *cpu = RISCV_CPU(opaque);
cd032fe7 1140 CPURISCVState *env = &cpu->env;
0f0b70ee 1141
cd032fe7
AP		 1142 if (irq < IRQ_LOCAL_MAX) {
1143 switch (irq) {
1144 case IRQ_U_SOFT:
1145 case IRQ_S_SOFT:
1146 case IRQ_VS_SOFT:
1147 case IRQ_M_SOFT:
1148 case IRQ_U_TIMER:
1149 case IRQ_S_TIMER:
1150 case IRQ_VS_TIMER:
1151 case IRQ_M_TIMER:
1152 case IRQ_U_EXT:
cd032fe7
AP		 1153 case IRQ_VS_EXT:
1154 case IRQ_M_EXT:
8b5c807b 1155 if (kvm_enabled()) {
cd032fe7 1156 kvm_riscv_set_irq(cpu, irq, level);
8b5c807b 1157 } else {
bbb9fc25 1158 riscv_cpu_update_mip(env, 1 << irq, BOOL_TO_MASK(level));
8b5c807b 1159 }
cd032fe7 1160 break;
33fe584f
AF		 1161 case IRQ_S_EXT:
1162 if (kvm_enabled()) {
1163 kvm_riscv_set_irq(cpu, irq, level);
1164 } else {
1165 env->external_seip = level;
bbb9fc25 1166 riscv_cpu_update_mip(env, 1 << irq,
33fe584f
AF		 1167 BOOL_TO_MASK(level | env->software_seip));
1168 }
1169 break;
cd032fe7
AP		 1170 default:
1171 g_assert_not_reached();
2b650fbb 1172 }
cd032fe7
AP		 1173 } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) {
1174 /* Require H-extension for handling guest local interrupts */
1175 if (!riscv_has_ext(env, RVH)) {
1176 g_assert_not_reached();
1177 }
1178
1179 /* Compute bit position in HGEIP CSR */
1180 irq = irq - IRQ_LOCAL_MAX + 1;
1181 if (env->geilen < irq) {
1182 g_assert_not_reached();
1183 }
1184
1185 /* Update HGEIP CSR */
1186 env->hgeip &= ~((target_ulong)1 << irq);
1187 if (level) {
1188 env->hgeip |= (target_ulong)1 << irq;
1189 }
1190
1191 /* Update mip.SGEIP bit */
bbb9fc25 1192 riscv_cpu_update_mip(env, MIP_SGEIP,
cd032fe7
AP		 1193 BOOL_TO_MASK(!!(env->hgeie & env->hgeip)));
1194 } else {
0f0b70ee
AF		 1195 g_assert_not_reached();
1196 }
1197}
1198#endif /* CONFIG_USER_ONLY */
1199
977bbb04
DHB		 1200static bool riscv_cpu_is_dynamic(Object *cpu_obj)
1201{
1202 return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
1203}
1204
1205static bool riscv_cpu_has_max_extensions(Object *cpu_obj)
1206{
1207 return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL;
1208}
1209
1210static bool riscv_cpu_has_user_properties(Object *cpu_obj)
1211{
1212 if (kvm_enabled() &&
1213 object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_HOST) != NULL) {
1214 return true;
1215 }
1216
1217 return riscv_cpu_is_dynamic(cpu_obj);
1218}
1219
1220static void riscv_cpu_post_init(Object *obj)
1221{
1222 if (riscv_cpu_has_user_properties(obj)) {
1223 riscv_cpu_add_user_properties(obj);
1224 }
1225
1226 if (riscv_cpu_has_max_extensions(obj)) {
1227 riscv_init_max_cpu_extensions(obj);
1228 }
1229}
1230
dc5bd18f
MC		 1231static void riscv_cpu_init(Object *obj)
1232{
0f0b70ee 1233#ifndef CONFIG_USER_ONLY
8fa08d7e 1234 qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq,
cd032fe7 1235 IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
0f0b70ee 1236#endif /* CONFIG_USER_ONLY */
549cbf78
DHB		 1237
1238 multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
dc5bd18f
MC		 1239}
1240
b3df64c8
DHB		 1241typedef struct RISCVCPUMisaExtConfig {
1242 const char *name;
1243 const char *description;
1244 target_ulong misa_bit;
1245 bool enabled;
1246} RISCVCPUMisaExtConfig;
1247
1248static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
1249 void *opaque, Error **errp)
1250{
1251 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
1252 target_ulong misa_bit = misa_ext_cfg->misa_bit;
1253 RISCVCPU *cpu = RISCV_CPU(obj);
1254 CPURISCVState *env = &cpu->env;
1255 bool value;
1256
1257 if (!visit_type_bool(v, name, &value, errp)) {
1258 return;
1259 }
1260
1261 if (value) {
1262 env->misa_ext |= misa_bit;
1263 env->misa_ext_mask |= misa_bit;
1264 } else {
1265 env->misa_ext &= ~misa_bit;
1266 env->misa_ext_mask &= ~misa_bit;
1267 }
1268}
1269
1270static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
1271 void *opaque, Error **errp)
1272{
1273 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
1274 target_ulong misa_bit = misa_ext_cfg->misa_bit;
1275 RISCVCPU *cpu = RISCV_CPU(obj);
1276 CPURISCVState *env = &cpu->env;
1277 bool value;
1278
1279 value = env->misa_ext & misa_bit;
1280
1281 visit_type_bool(v, name, &value, errp);
1282}
1283
ed7e6182
DHB		 1284typedef struct misa_ext_info {
1285 const char *name;
1286 const char *description;
1287} MISAExtInfo;
1288
1289#define MISA_INFO_IDX(_bit) \
1290 __builtin_ctz(_bit)
1291
1292#define MISA_EXT_INFO(_bit, _propname, _descr) \
1293 [MISA_INFO_IDX(_bit)] = {.name = _propname, .description = _descr}
1294
1295static const MISAExtInfo misa_ext_info_arr[] = {
1296 MISA_EXT_INFO(RVA, "a", "Atomic instructions"),
1297 MISA_EXT_INFO(RVC, "c", "Compressed instructions"),
1298 MISA_EXT_INFO(RVD, "d", "Double-precision float point"),
1299 MISA_EXT_INFO(RVF, "f", "Single-precision float point"),
1300 MISA_EXT_INFO(RVI, "i", "Base integer instruction set"),
1301 MISA_EXT_INFO(RVE, "e", "Base integer instruction set (embedded)"),
1302 MISA_EXT_INFO(RVM, "m", "Integer multiplication and division"),
1303 MISA_EXT_INFO(RVS, "s", "Supervisor-level instructions"),
1304 MISA_EXT_INFO(RVU, "u", "User-level instructions"),
1305 MISA_EXT_INFO(RVH, "h", "Hypervisor"),
1306 MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
1307 MISA_EXT_INFO(RVV, "v", "Vector operations"),
1308 MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
1309};
1310
1311static int riscv_validate_misa_info_idx(uint32_t bit)
1312{
1313 int idx;
1314
1315 /*
1316 * Our lowest valid input (RVA) is 1 and
1317 * __builtin_ctz() is UB with zero.
1318 */
1319 g_assert(bit != 0);
1320 idx = MISA_INFO_IDX(bit);
1321
1322 g_assert(idx < ARRAY_SIZE(misa_ext_info_arr));
1323 return idx;
1324}
1325
1326const char *riscv_get_misa_ext_name(uint32_t bit)
1327{
1328 int idx = riscv_validate_misa_info_idx(bit);
1329 const char *val = misa_ext_info_arr[idx].name;
1330
1331 g_assert(val != NULL);
1332 return val;
1333}
1334
1335const char *riscv_get_misa_ext_description(uint32_t bit)
1336{
1337 int idx = riscv_validate_misa_info_idx(bit);
1338 const char *val = misa_ext_info_arr[idx].description;
1339
1340 g_assert(val != NULL);
1341 return val;
1342}
1343
1344#define MISA_CFG(_bit, _enabled) \
1345 {.misa_bit = _bit, .enabled = _enabled}
1346
1347static RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
1348 MISA_CFG(RVA, true),
1349 MISA_CFG(RVC, true),
1350 MISA_CFG(RVD, true),
1351 MISA_CFG(RVF, true),
1352 MISA_CFG(RVI, true),
1353 MISA_CFG(RVE, false),
1354 MISA_CFG(RVM, true),
1355 MISA_CFG(RVS, true),
1356 MISA_CFG(RVU, true),
1357 MISA_CFG(RVH, true),
1358 MISA_CFG(RVJ, false),
1359 MISA_CFG(RVV, false),
1360 MISA_CFG(RVG, false),
4c759943 1361};
b3df64c8 1362
0a9eb9b4
DHB		 1363/*
1364 * We do not support user choice tracking for MISA
1365 * extensions yet because, so far, we do not silently
1366 * change MISA bits during realize() (RVG enables MISA
1367 * bits but the user is warned about it).
1368 */
32fa1776 1369void riscv_cpu_add_misa_properties(Object *cpu_obj)
b3df64c8
DHB		 1370{
1371 int i;
1372
1373 for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
ed7e6182
DHB		 1374 RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
1375 int bit = misa_cfg->misa_bit;
1376
1377 misa_cfg->name = riscv_get_misa_ext_name(bit);
1378 misa_cfg->description = riscv_get_misa_ext_description(bit);
b3df64c8 1379
92becce5
DHB		 1380 /* Check if KVM already created the property */
1381 if (object_property_find(cpu_obj, misa_cfg->name)) {
1382 continue;
1383 }
1384
b3df64c8
DHB		 1385 object_property_add(cpu_obj, misa_cfg->name, "bool",
1386 cpu_get_misa_ext_cfg,
1387 cpu_set_misa_ext_cfg,
1388 NULL, (void *)misa_cfg);
1389 object_property_set_description(cpu_obj, misa_cfg->name,
1390 misa_cfg->description);
1391 object_property_set_bool(cpu_obj, misa_cfg->name,
1392 misa_cfg->enabled, NULL);
1393 }
1394}
1395
549cbf78
DHB		 1396#define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \
1397 {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
1398 .enabled = _defval}
1399
32fa1776 1400const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
9d3d60b7 1401 /* Defaults for standard extensions */
549cbf78
DHB		 1402 MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
1403 MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true),
1404 MULTI_EXT_CFG_BOOL("Zicsr", ext_icsr, true),
1405 MULTI_EXT_CFG_BOOL("Zihintntl", ext_zihintntl, true),
1406 MULTI_EXT_CFG_BOOL("Zihintpause", ext_zihintpause, true),
1407 MULTI_EXT_CFG_BOOL("Zawrs", ext_zawrs, true),
1408 MULTI_EXT_CFG_BOOL("Zfa", ext_zfa, true),
1409 MULTI_EXT_CFG_BOOL("Zfh", ext_zfh, false),
1410 MULTI_EXT_CFG_BOOL("Zfhmin", ext_zfhmin, false),
1411 MULTI_EXT_CFG_BOOL("Zve32f", ext_zve32f, false),
1412 MULTI_EXT_CFG_BOOL("Zve64f", ext_zve64f, false),
1413 MULTI_EXT_CFG_BOOL("Zve64d", ext_zve64d, false),
1414 MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true),
1415
1416 MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false),
1417 MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true),
1418 MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false),
1419 MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false),
1420 MULTI_EXT_CFG_BOOL("svpbmt", ext_svpbmt, false),
1421
1422 MULTI_EXT_CFG_BOOL("zba", ext_zba, true),
1423 MULTI_EXT_CFG_BOOL("zbb", ext_zbb, true),
1424 MULTI_EXT_CFG_BOOL("zbc", ext_zbc, true),
1425 MULTI_EXT_CFG_BOOL("zbkb", ext_zbkb, false),
1426 MULTI_EXT_CFG_BOOL("zbkc", ext_zbkc, false),
1427 MULTI_EXT_CFG_BOOL("zbkx", ext_zbkx, false),
1428 MULTI_EXT_CFG_BOOL("zbs", ext_zbs, true),
1429 MULTI_EXT_CFG_BOOL("zk", ext_zk, false),
1430 MULTI_EXT_CFG_BOOL("zkn", ext_zkn, false),
1431 MULTI_EXT_CFG_BOOL("zknd", ext_zknd, false),
1432 MULTI_EXT_CFG_BOOL("zkne", ext_zkne, false),
1433 MULTI_EXT_CFG_BOOL("zknh", ext_zknh, false),
1434 MULTI_EXT_CFG_BOOL("zkr", ext_zkr, false),
1435 MULTI_EXT_CFG_BOOL("zks", ext_zks, false),
1436 MULTI_EXT_CFG_BOOL("zksed", ext_zksed, false),
1437 MULTI_EXT_CFG_BOOL("zksh", ext_zksh, false),
1438 MULTI_EXT_CFG_BOOL("zkt", ext_zkt, false),
1439
1440 MULTI_EXT_CFG_BOOL("zdinx", ext_zdinx, false),
1441 MULTI_EXT_CFG_BOOL("zfinx", ext_zfinx, false),
1442 MULTI_EXT_CFG_BOOL("zhinx", ext_zhinx, false),
1443 MULTI_EXT_CFG_BOOL("zhinxmin", ext_zhinxmin, false),
1444
1445 MULTI_EXT_CFG_BOOL("zicbom", ext_icbom, true),
1446 MULTI_EXT_CFG_BOOL("zicboz", ext_icboz, true),
1447
1448 MULTI_EXT_CFG_BOOL("zmmul", ext_zmmul, false),
1449
1450 MULTI_EXT_CFG_BOOL("zca", ext_zca, false),
1451 MULTI_EXT_CFG_BOOL("zcb", ext_zcb, false),
1452 MULTI_EXT_CFG_BOOL("zcd", ext_zcd, false),
1453 MULTI_EXT_CFG_BOOL("zce", ext_zce, false),
1454 MULTI_EXT_CFG_BOOL("zcf", ext_zcf, false),
1455 MULTI_EXT_CFG_BOOL("zcmp", ext_zcmp, false),
1456 MULTI_EXT_CFG_BOOL("zcmt", ext_zcmt, false),
1457 MULTI_EXT_CFG_BOOL("zicond", ext_zicond, false),
6672e29d 1458
82822b5d
DHB		 1459 DEFINE_PROP_END_OF_LIST(),
1460};
1461
32fa1776 1462const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
549cbf78
DHB		 1463 MULTI_EXT_CFG_BOOL("xtheadba", ext_xtheadba, false),
1464 MULTI_EXT_CFG_BOOL("xtheadbb", ext_xtheadbb, false),
1465 MULTI_EXT_CFG_BOOL("xtheadbs", ext_xtheadbs, false),
1466 MULTI_EXT_CFG_BOOL("xtheadcmo", ext_xtheadcmo, false),
1467 MULTI_EXT_CFG_BOOL("xtheadcondmov", ext_xtheadcondmov, false),
1468 MULTI_EXT_CFG_BOOL("xtheadfmemidx", ext_xtheadfmemidx, false),
1469 MULTI_EXT_CFG_BOOL("xtheadfmv", ext_xtheadfmv, false),
1470 MULTI_EXT_CFG_BOOL("xtheadmac", ext_xtheadmac, false),
1471 MULTI_EXT_CFG_BOOL("xtheadmemidx", ext_xtheadmemidx, false),
1472 MULTI_EXT_CFG_BOOL("xtheadmempair", ext_xtheadmempair, false),
1473 MULTI_EXT_CFG_BOOL("xtheadsync", ext_xtheadsync, false),
1474 MULTI_EXT_CFG_BOOL("xventanacondops", ext_XVentanaCondOps, false),
0d429bd2 1475
b955fd1a
DHB		 1476 DEFINE_PROP_END_OF_LIST(),
1477};
d364c0ab 1478
b955fd1a 1479/* These are experimental so mark with 'x-' */
32fa1776 1480const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
a44da25a 1481 /* ePMP 0.9.3 */
549cbf78
DHB		 1482 MULTI_EXT_CFG_BOOL("x-epmp", epmp, false),
1483 MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false),
1484 MULTI_EXT_CFG_BOOL("x-ssaia", ext_ssaia, false),
5da9514e 1485
549cbf78
DHB		 1486 MULTI_EXT_CFG_BOOL("x-zvfh", ext_zvfh, false),
1487 MULTI_EXT_CFG_BOOL("x-zvfhmin", ext_zvfhmin, false),
058d9d30 1488
549cbf78
DHB		 1489 MULTI_EXT_CFG_BOOL("x-zfbfmin", ext_zfbfmin, false),
1490 MULTI_EXT_CFG_BOOL("x-zvfbfmin", ext_zvfbfmin, false),
1491 MULTI_EXT_CFG_BOOL("x-zvfbfwma", ext_zvfbfwma, false),
889caa44 1492
e13c7d3b 1493 /* Vector cryptography extensions */
549cbf78
DHB		 1494 MULTI_EXT_CFG_BOOL("x-zvbb", ext_zvbb, false),
1495 MULTI_EXT_CFG_BOOL("x-zvbc", ext_zvbc, false),
1496 MULTI_EXT_CFG_BOOL("x-zvkg", ext_zvkg, false),
1497 MULTI_EXT_CFG_BOOL("x-zvkned", ext_zvkned, false),
1498 MULTI_EXT_CFG_BOOL("x-zvknha", ext_zvknha, false),
1499 MULTI_EXT_CFG_BOOL("x-zvknhb", ext_zvknhb, false),
1500 MULTI_EXT_CFG_BOOL("x-zvksed", ext_zvksed, false),
1501 MULTI_EXT_CFG_BOOL("x-zvksh", ext_zvksh, false),
e13c7d3b 1502
26b2bc58
AF		 1503 DEFINE_PROP_END_OF_LIST(),
1504};
1505
32fa1776 1506Property riscv_cpu_options[] = {
8ea3fcef
DHB		 1507 DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
1508
1509 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
1510 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
1511
1512 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
1513 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
1514
1515 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
1516 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
1517
1518 DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64),
1519 DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64),
d09d085a
DHB		 1520
1521 DEFINE_PROP_END_OF_LIST(),
8ea3fcef 1522};
56f0e992 1523
549cbf78
DHB		 1524static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
1525 void *opaque, Error **errp)
1526{
1527 const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
1528 bool value;
1529
1530 if (!visit_type_bool(v, name, &value, errp)) {
1531 return;
1532 }
1533
1534 isa_ext_update_enabled(RISCV_CPU(obj), multi_ext_cfg->offset, value);
1535
1536 g_hash_table_insert(multi_ext_user_opts,
1537 GUINT_TO_POINTER(multi_ext_cfg->offset),
1538 (gpointer)value);
1539}
1540
1541static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
1542 void *opaque, Error **errp)
1543{
1544 const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
1545 bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset);
1546
1547 visit_type_bool(v, name, &value, errp);
1548}
1549
1550static void cpu_add_multi_ext_prop(Object *cpu_obj,
ec34cd73 1551 const RISCVCPUMultiExtConfig *multi_cfg)
549cbf78
DHB		 1552{
1553 object_property_add(cpu_obj, multi_cfg->name, "bool",
1554 cpu_get_multi_ext_cfg,
1555 cpu_set_multi_ext_cfg,
1556 NULL, (void *)multi_cfg);
1557
1558 /*
1559 * Set def val directly instead of using
1560 * object_property_set_bool() to save the set()
1561 * callback hash for user inputs.
1562 */
1563 isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset,
1564 multi_cfg->enabled);
1565}
1566
1567static void riscv_cpu_add_multiext_prop_array(Object *obj,
ec34cd73 1568 const RISCVCPUMultiExtConfig *array)
370d7c8e 1569{
ec34cd73
DHB		 1570 const RISCVCPUMultiExtConfig *prop;
1571
370d7c8e
DHB		 1572 g_assert(array);
1573
ec34cd73 1574 for (prop = array; prop && prop->name; prop++) {
549cbf78 1575 cpu_add_multi_ext_prop(obj, prop);
370d7c8e
DHB		 1576 }
1577}
1578
c66ffcd5 1579/*
dd8f244f
DHB		 1580 * Add CPU properties with user-facing flags.
1581 *
1582 * This will overwrite existing env->misa_ext values with the
1583 * defaults set via riscv_cpu_add_misa_properties().
c66ffcd5 1584 */
dd8f244f 1585static void riscv_cpu_add_user_properties(Object *obj)
26b2bc58 1586{
492265ae
DHB		 1587#ifndef CONFIG_USER_ONLY
1588 if (kvm_enabled()) {
68aba1f2
DHB		 1589 kvm_riscv_cpu_add_kvm_properties(obj);
1590 return;
492265ae 1591 }
7d0c302c 1592 riscv_add_satp_mode_properties(obj);
492265ae
DHB		 1593#endif
1594
b3df64c8
DHB		 1595 riscv_cpu_add_misa_properties(obj);
1596
549cbf78
DHB		 1597 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions);
1598 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts);
1599 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts);
1600
1601 for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
1602 qdev_property_add_static(DEVICE(obj), prop);
1603 }
26b2bc58
AF		 1604}
1605
b97e5a6b
DHB		 1606/*
1607 * The 'max' type CPU will have all possible ratified
1608 * non-vendor extensions enabled.
1609 */
1610static void riscv_init_max_cpu_extensions(Object *obj)
1611{
1612 RISCVCPU *cpu = RISCV_CPU(obj);
1613 CPURISCVState *env = &cpu->env;
ec34cd73 1614 const RISCVCPUMultiExtConfig *prop;
b97e5a6b
DHB		 1615
1616 /* Enable RVG, RVJ and RVV that are disabled by default */
1617 set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
1618
1619 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
25aa6f72 1620 isa_ext_update_enabled(cpu, prop->offset, true);
b97e5a6b
DHB		 1621 }
1622
1623 /* set vector version */
1624 env->vext_ver = VEXT_VERSION_1_00_0;
1625
1626 /* Zfinx is not compatible with F. Disable it */
25aa6f72
DHB		 1627 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false);
1628 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false);
1629 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false);
1630 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false);
b97e5a6b 1631
25aa6f72
DHB		 1632 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false);
1633 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false);
1634 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false);
b97e5a6b
DHB		 1635
1636 if (env->misa_mxl != MXL_RV32) {
25aa6f72 1637 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false);
b97e5a6b
DHB		 1638 }
1639}
1640
26b2bc58
AF		 1641static Property riscv_cpu_properties[] = {
1642 DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
1643
277b210d
AF		 1644#ifndef CONFIG_USER_ONLY
1645 DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC),
1646#endif
a4a9a443
TO		 1647
1648 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false),
b8312675 1649
1650 DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false),
1ad3f9bd 1651 DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false),
54bd9b6e
DHB		 1652
1653 /*
1654 * write_misa() is marked as experimental for now so mark
1655 * it with -x and default to 'false'.
1656 */
1657 DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false),
c4e95030
AF		 1658 DEFINE_PROP_END_OF_LIST(),
1659};
1660
a6506838 1661static const gchar *riscv_gdb_arch_name(CPUState *cs)
edf64786
SP		 1662{
1663 RISCVCPU *cpu = RISCV_CPU(cs);
1664 CPURISCVState *env = &cpu->env;
1665
db23e5d9
RH		 1666 switch (riscv_cpu_mxl(env)) {
1667 case MXL_RV32:
a6506838 1668 return "riscv:rv32";
db23e5d9 1669 case MXL_RV64:
332dab68 1670 case MXL_RV128:
a6506838 1671 return "riscv:rv64";
db23e5d9
RH		 1672 default:
1673 g_assert_not_reached();
edf64786
SP		 1674 }
1675}
1676
b93777e1
BM		 1677static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
1678{
1679 RISCVCPU *cpu = RISCV_CPU(cs);
1680
1681 if (strcmp(xmlname, "riscv-csr.xml") == 0) {
1682 return cpu->dyn_csr_xml;
719d3561
HW		 1683 } else if (strcmp(xmlname, "riscv-vector.xml") == 0) {
1684 return cpu->dyn_vreg_xml;
b93777e1
BM		 1685 }
1686
1687 return NULL;
1688}
1689
8b80bd28 1690#ifndef CONFIG_USER_ONLY
f1bd6f8e
MC		 1691static int64_t riscv_get_arch_id(CPUState *cs)
1692{
1693 RISCVCPU *cpu = RISCV_CPU(cs);
1694
1695 return cpu->env.mhartid;
1696}
1697
8b80bd28
PMD		 1698#include "hw/core/sysemu-cpu-ops.h"
1699
1700static const struct SysemuCPUOps riscv_sysemu_ops = {
08928c6d 1701 .get_phys_page_debug = riscv_cpu_get_phys_page_debug,
715e3c1a
PMD		 1702 .write_elf64_note = riscv_cpu_write_elf64_note,
1703 .write_elf32_note = riscv_cpu_write_elf32_note,
feece4d0 1704 .legacy_vmsd = &vmstate_riscv_cpu,
8b80bd28
PMD		 1705};
1706#endif
1707
1e341500
DHB		 1708static void cpu_set_mvendorid(Object *obj, Visitor *v, const char *name,
1709 void *opaque, Error **errp)
1710{
1711 bool dynamic_cpu = riscv_cpu_is_dynamic(obj);
1712 RISCVCPU *cpu = RISCV_CPU(obj);
1713 uint32_t prev_val = cpu->cfg.mvendorid;
1714 uint32_t value;
1715
1716 if (!visit_type_uint32(v, name, &value, errp)) {
1717 return;
1718 }
1719
1720 if (!dynamic_cpu && prev_val != value) {
1721 error_setg(errp, "Unable to change %s mvendorid (0x%x)",
1722 object_get_typename(obj), prev_val);
1723 return;
1724 }
1725
1726 cpu->cfg.mvendorid = value;
1727}
1728
1729static void cpu_get_mvendorid(Object *obj, Visitor *v, const char *name,
1730 void *opaque, Error **errp)
1731{
1732 bool value = RISCV_CPU(obj)->cfg.mvendorid;
1733
1734 visit_type_bool(v, name, &value, errp);
1735}
1736
a1863ad3
DHB		 1737static void cpu_set_mimpid(Object *obj, Visitor *v, const char *name,
1738 void *opaque, Error **errp)
1739{
1740 bool dynamic_cpu = riscv_cpu_is_dynamic(obj);
1741 RISCVCPU *cpu = RISCV_CPU(obj);
1742 uint64_t prev_val = cpu->cfg.mimpid;
1743 uint64_t value;
1744
1745 if (!visit_type_uint64(v, name, &value, errp)) {
1746 return;
1747 }
1748
1749 if (!dynamic_cpu && prev_val != value) {
1750 error_setg(errp, "Unable to change %s mimpid (0x%" PRIu64 ")",
1751 object_get_typename(obj), prev_val);
1752 return;
1753 }
1754
1755 cpu->cfg.mimpid = value;
1756}
1757
1758static void cpu_get_mimpid(Object *obj, Visitor *v, const char *name,
1759 void *opaque, Error **errp)
1760{
1761 bool value = RISCV_CPU(obj)->cfg.mimpid;
1762
1763 visit_type_bool(v, name, &value, errp);
1764}
1765
d6a427e2
DHB		 1766static void cpu_set_marchid(Object *obj, Visitor *v, const char *name,
1767 void *opaque, Error **errp)
1768{
1769 bool dynamic_cpu = riscv_cpu_is_dynamic(obj);
1770 RISCVCPU *cpu = RISCV_CPU(obj);
1771 uint64_t prev_val = cpu->cfg.marchid;
1772 uint64_t value, invalid_val;
1773 uint32_t mxlen = 0;
1774
1775 if (!visit_type_uint64(v, name, &value, errp)) {
1776 return;
1777 }
1778
1779 if (!dynamic_cpu && prev_val != value) {
1780 error_setg(errp, "Unable to change %s marchid (0x%" PRIu64 ")",
1781 object_get_typename(obj), prev_val);
1782 return;
1783 }
1784
1785 switch (riscv_cpu_mxl(&cpu->env)) {
1786 case MXL_RV32:
1787 mxlen = 32;
1788 break;
1789 case MXL_RV64:
1790 case MXL_RV128:
1791 mxlen = 64;
1792 break;
1793 default:
1794 g_assert_not_reached();
1795 }
1796
1797 invalid_val = 1LL << (mxlen - 1);
1798
1799 if (value == invalid_val) {
1800 error_setg(errp, "Unable to set marchid with MSB (%u) bit set "
1801 "and the remaining bits zero", mxlen);
1802 return;
1803 }
1804
1805 cpu->cfg.marchid = value;
1806}
1807
1808static void cpu_get_marchid(Object *obj, Visitor *v, const char *name,
1809 void *opaque, Error **errp)
1810{
1811 bool value = RISCV_CPU(obj)->cfg.marchid;
1812
1813 visit_type_bool(v, name, &value, errp);
1814}
1815
dc5bd18f
MC		 1816static void riscv_cpu_class_init(ObjectClass *c, void *data)
1817{
1818 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
1819 CPUClass *cc = CPU_CLASS(c);
1820 DeviceClass *dc = DEVICE_CLASS(c);
4fa485a7 1821 ResettableClass *rc = RESETTABLE_CLASS(c);
dc5bd18f 1822
41fbbba7
MZ		 1823 device_class_set_parent_realize(dc, riscv_cpu_realize,
1824 &mcc->parent_realize);
dc5bd18f 1825
4fa485a7
PM		 1826 resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL,
1827 &mcc->parent_phases);
dc5bd18f
MC		 1828
1829 cc->class_by_name = riscv_cpu_class_by_name;
1830 cc->has_work = riscv_cpu_has_work;
dc5bd18f
MC		 1831 cc->dump_state = riscv_cpu_dump_state;
1832 cc->set_pc = riscv_cpu_set_pc;
e4fdf9df 1833 cc->get_pc = riscv_cpu_get_pc;
dc5bd18f
MC		 1834 cc->gdb_read_register = riscv_cpu_gdb_read_register;
1835 cc->gdb_write_register = riscv_cpu_gdb_write_register;
5371f5cd 1836 cc->gdb_num_core_regs = 33;
dc5bd18f
MC		 1837 cc->gdb_stop_before_watchpoint = true;
1838 cc->disas_set_info = riscv_cpu_disas_set_info;
8a4ca3c1 1839#ifndef CONFIG_USER_ONLY
8b80bd28 1840 cc->sysemu_ops = &riscv_sysemu_ops;
f1bd6f8e 1841 cc->get_arch_id = riscv_get_arch_id;
dc5bd18f 1842#endif
edf64786 1843 cc->gdb_arch_name = riscv_gdb_arch_name;
b93777e1 1844 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
6a3d2e7c 1845
1e341500
DHB		 1846 object_class_property_add(c, "mvendorid", "uint32", cpu_get_mvendorid,
1847 cpu_set_mvendorid, NULL, NULL);
a1863ad3
DHB		 1848
1849 object_class_property_add(c, "mimpid", "uint64", cpu_get_mimpid,
1850 cpu_set_mimpid, NULL, NULL);
d6a427e2
DHB		 1851
1852 object_class_property_add(c, "marchid", "uint64", cpu_get_marchid,
1853 cpu_set_marchid, NULL, NULL);
1e341500 1854
4f67d30b 1855 device_class_set_props(dc, riscv_cpu_properties);
dc5bd18f
MC		 1856}
1857
246f8796
WL		 1858static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,
1859 int max_str_len)
a775398b
AP		 1860{
1861 char *old = *isa_str;
1862 char *new = *isa_str;
1863 int i;
1864
a775398b 1865 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
5f2c80f1 1866 if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset)) {
a775398b
AP		 1867 new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
1868 g_free(old);
1869 old = new;
1870 }
1871 }
1872
1873 *isa_str = new;
1874}
1875
dc5bd18f
MC		 1876char *riscv_isa_string(RISCVCPU *cpu)
1877{
1878 int i;
0e2c3770 1879 const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts);
d1fd31f8
MC		 1880 char *isa_str = g_new(char, maxlen);
1881 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
0e2c3770
TO		 1882 for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) {
1883 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) {
1884 *p++ = qemu_tolower(riscv_single_letter_exts[i]);
dc5bd18f
MC		 1885 }
1886 }
d1fd31f8 1887 *p = '\0';
a4a9a443
TO		 1888 if (!cpu->cfg.short_isa_string) {
1889 riscv_isa_string_ext(cpu, &isa_str, maxlen);
1890 }
d1fd31f8 1891 return isa_str;
dc5bd18f
MC		 1892}
1893
eab15862 1894static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b)
dc5bd18f 1895{
eab15862
MC		 1896 ObjectClass *class_a = (ObjectClass *)a;
1897 ObjectClass *class_b = (ObjectClass *)b;
1898 const char *name_a, *name_b;
dc5bd18f 1899
eab15862
MC		 1900 name_a = object_class_get_name(class_a);
1901 name_b = object_class_get_name(class_b);
1902 return strcmp(name_a, name_b);
dc5bd18f
MC		 1903}
1904
eab15862 1905static void riscv_cpu_list_entry(gpointer data, gpointer user_data)
dc5bd18f 1906{
eab15862
MC		 1907 const char *typename = object_class_get_name(OBJECT_CLASS(data));
1908 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX);
dc5bd18f 1909
0442428a 1910 qemu_printf("%.*s\n", len, typename);
eab15862 1911}
dc5bd18f 1912
0442428a 1913void riscv_cpu_list(void)
eab15862 1914{
eab15862
MC		 1915 GSList *list;
1916
1917 list = object_class_get_list(TYPE_RISCV_CPU, false);
1918 list = g_slist_sort(list, riscv_cpu_list_compare);
0442428a 1919 g_slist_foreach(list, riscv_cpu_list_entry, NULL);
eab15862 1920 g_slist_free(list);
dc5bd18f
MC		 1921}
1922
eab15862
MC		 1923#define DEFINE_CPU(type_name, initfn) \
1924 { \
1925 .name = type_name, \
1926 .parent = TYPE_RISCV_CPU, \
1927 .instance_init = initfn \
1928 }
1929
9e1a30d3
DHB		 1930#define DEFINE_DYNAMIC_CPU(type_name, initfn) \
1931 { \
1932 .name = type_name, \
1933 .parent = TYPE_RISCV_DYNAMIC_CPU, \
1934 .instance_init = initfn \
1935 }
1936
eab15862
MC		 1937static const TypeInfo riscv_cpu_type_infos[] = {
1938 {
1939 .name = TYPE_RISCV_CPU,
1940 .parent = TYPE_CPU,
1941 .instance_size = sizeof(RISCVCPU),
f669c992 1942 .instance_align = __alignof(RISCVCPU),
eab15862 1943 .instance_init = riscv_cpu_init,
977bbb04 1944 .instance_post_init = riscv_cpu_post_init,
eab15862
MC		 1945 .abstract = true,
1946 .class_size = sizeof(RISCVCPUClass),
1947 .class_init = riscv_cpu_class_init,
1948 },
9e1a30d3
DHB		 1949 {
1950 .name = TYPE_RISCV_DYNAMIC_CPU,
1951 .parent = TYPE_RISCV_CPU,
1952 .abstract = true,
1953 },
1954 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
b97e5a6b 1955 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, riscv_max_cpu_init),
eab15862 1956#if defined(TARGET_RISCV32)
9e1a30d3 1957 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init),
e8905c6c 1958 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),
114baaca 1959 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init),
2fdd2c09 1960 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init),
114baaca 1961 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init),
eab15862 1962#elif defined(TARGET_RISCV64)
9e1a30d3 1963 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init),
114baaca
AF		 1964 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
1965 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
6ddc7069 1966 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init),
95bd8daa 1967 DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init),
e1d084a8 1968 DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init),
9e1a30d3 1969 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init),
eab15862
MC		 1970#endif
1971};
1972
1973DEFINE_TYPES(riscv_cpu_type_infos)
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