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target/riscv/tcg: add 'zic64b' support
[mirror_qemu.git] / target / riscv / cpu.c
CommitLineData
dc5bd18f
MC		 1/*
2 * QEMU RISC-V CPU
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "qemu/osdep.h"
0442428a 21#include "qemu/qemu-print.h"
856dfd8a 22#include "qemu/ctype.h"
dc5bd18f
MC		 23#include "qemu/log.h"
24#include "cpu.h"
95bd8daa 25#include "cpu_vendorid.h"
f7697f0e 26#include "internals.h"
dc5bd18f
MC		 27#include "exec/exec-all.h"
28#include "qapi/error.h"
6f23aaeb 29#include "qapi/visitor.h"
b55d7d34 30#include "qemu/error-report.h"
c4e95030 31#include "hw/qdev-properties.h"
dc5bd18f 32#include "migration/vmstate.h"
135b03cb 33#include "fpu/softfloat-helpers.h"
ad40be27 34#include "sysemu/kvm.h"
eddabb6b 35#include "sysemu/tcg.h"
fb80f333 36#include "kvm/kvm_riscv.h"
a13a6082 37#include "tcg/tcg-cpu.h"
0489d5bd 38#include "tcg/tcg.h"
dc5bd18f
MC		 39
40/* RISC-V CPU definitions */
0e2c3770 41static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
efa365b7
DHB		 42const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,
43 RVC, RVS, RVU, RVH, RVJ, RVG, 0};
dc5bd18f 44
b227f6a8
IK		 45/*
46 * From vector_helper.c
47 * Note that vector data is stored in host-endian 64-bit chunks,
48 * so addressing bytes needs a host-endian fixup.
49 */
50#if HOST_BIG_ENDIAN
51#define BYTE(x) ((x) ^ 7)
52#else
53#define BYTE(x) (x)
54#endif
55
7935e2c4
DHB		 56#define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \
57 {#_name, _min_ver, CPU_CFG_OFFSET(_prop)}
58
3b57254d 59/*
9a1f054d
AP		 60 * Here are the ordering rules of extension naming defined by RISC-V
61 * specification :
62 * 1. All extensions should be separated from other multi-letter extensions
63 * by an underscore.
64 * 2. The first letter following the 'Z' conventionally indicates the most
65 * closely related alphabetical extension category, IMAFDQLCBKJTPVH.
66 * If multiple 'Z' extensions are named, they should be ordered first
67 * by category, then alphabetically within a category.
68 * 3. Standard supervisor-level extensions (starts with 'S') should be
69 * listed after standard unprivileged extensions. If multiple
70 * supervisor-level extensions are listed, they should be ordered
71 * alphabetically.
72 * 4. Non-standard extensions (starts with 'X') must be listed after all
73 * standard extensions. They must be separated from other multi-letter
74 * extensions by an underscore.
6508272a
DHB		 75 *
76 * Single letter extensions are checked in riscv_cpu_validate_misa_priv()
77 * instead.
9a1f054d 78 */
7935e2c4 79const RISCVIsaExtData isa_edata_arr[] = {
a326a2b0 80 ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_zicbom),
cc2bf69a 81 ISA_EXT_DATA_ENTRY(zicbop, PRIV_VERSION_1_12_0, ext_zicbop),
e57039dd 82 ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_zicboz),
ccc84a75 83 ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond),
c0040993 84 ISA_EXT_DATA_ENTRY(zicntr, PRIV_VERSION_1_12_0, ext_zicntr),
960b389b 85 ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_zicsr),
12b12a14 86 ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_zifencei),
0228aca2 87 ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl),
ccc84a75 88 ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause),
08241216 89 ISA_EXT_DATA_ENTRY(zihpm, PRIV_VERSION_1_12_0, ext_zihpm),
50f94649 90 ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul),
b52d49e9 91 ISA_EXT_DATA_ENTRY(zacas, PRIV_VERSION_1_12_0, ext_zacas),
ccc84a75 92 ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs),
a47842d1 93 ISA_EXT_DATA_ENTRY(zfa, PRIV_VERSION_1_12_0, ext_zfa),
889caa44 94 ISA_EXT_DATA_ENTRY(zfbfmin, PRIV_VERSION_1_12_0, ext_zfbfmin),
ccc84a75
DHB		 95 ISA_EXT_DATA_ENTRY(zfh, PRIV_VERSION_1_11_0, ext_zfh),
96 ISA_EXT_DATA_ENTRY(zfhmin, PRIV_VERSION_1_11_0, ext_zfhmin),
97 ISA_EXT_DATA_ENTRY(zfinx, PRIV_VERSION_1_12_0, ext_zfinx),
98 ISA_EXT_DATA_ENTRY(zdinx, PRIV_VERSION_1_12_0, ext_zdinx),
99 ISA_EXT_DATA_ENTRY(zca, PRIV_VERSION_1_12_0, ext_zca),
100 ISA_EXT_DATA_ENTRY(zcb, PRIV_VERSION_1_12_0, ext_zcb),
101 ISA_EXT_DATA_ENTRY(zcf, PRIV_VERSION_1_12_0, ext_zcf),
102 ISA_EXT_DATA_ENTRY(zcd, PRIV_VERSION_1_12_0, ext_zcd),
103 ISA_EXT_DATA_ENTRY(zce, PRIV_VERSION_1_12_0, ext_zce),
104 ISA_EXT_DATA_ENTRY(zcmp, PRIV_VERSION_1_12_0, ext_zcmp),
105 ISA_EXT_DATA_ENTRY(zcmt, PRIV_VERSION_1_12_0, ext_zcmt),
106 ISA_EXT_DATA_ENTRY(zba, PRIV_VERSION_1_12_0, ext_zba),
107 ISA_EXT_DATA_ENTRY(zbb, PRIV_VERSION_1_12_0, ext_zbb),
108 ISA_EXT_DATA_ENTRY(zbc, PRIV_VERSION_1_12_0, ext_zbc),
109 ISA_EXT_DATA_ENTRY(zbkb, PRIV_VERSION_1_12_0, ext_zbkb),
110 ISA_EXT_DATA_ENTRY(zbkc, PRIV_VERSION_1_12_0, ext_zbkc),
111 ISA_EXT_DATA_ENTRY(zbkx, PRIV_VERSION_1_12_0, ext_zbkx),
112 ISA_EXT_DATA_ENTRY(zbs, PRIV_VERSION_1_12_0, ext_zbs),
113 ISA_EXT_DATA_ENTRY(zk, PRIV_VERSION_1_12_0, ext_zk),
114 ISA_EXT_DATA_ENTRY(zkn, PRIV_VERSION_1_12_0, ext_zkn),
115 ISA_EXT_DATA_ENTRY(zknd, PRIV_VERSION_1_12_0, ext_zknd),
116 ISA_EXT_DATA_ENTRY(zkne, PRIV_VERSION_1_12_0, ext_zkne),
117 ISA_EXT_DATA_ENTRY(zknh, PRIV_VERSION_1_12_0, ext_zknh),
118 ISA_EXT_DATA_ENTRY(zkr, PRIV_VERSION_1_12_0, ext_zkr),
119 ISA_EXT_DATA_ENTRY(zks, PRIV_VERSION_1_12_0, ext_zks),
120 ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed),
121 ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh),
122 ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt),
06028472 123 ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
e13c7d3b 124 ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
ccc84a75
DHB		 125 ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
126 ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
127 ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
889caa44
WL		 128 ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
129 ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
ccc84a75
DHB		 130 ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
131 ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin),
f209cb0a 132 ISA_EXT_DATA_ENTRY(zvkb, PRIV_VERSION_1_12_0, ext_zvkb),
767eb035 133 ISA_EXT_DATA_ENTRY(zvkg, PRIV_VERSION_1_12_0, ext_zvkg),
23aaefb9
MC		 134 ISA_EXT_DATA_ENTRY(zvkn, PRIV_VERSION_1_12_0, ext_zvkn),
135 ISA_EXT_DATA_ENTRY(zvknc, PRIV_VERSION_1_12_0, ext_zvknc),
e972bf22 136 ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned),
23aaefb9 137 ISA_EXT_DATA_ENTRY(zvkng, PRIV_VERSION_1_12_0, ext_zvkng),
fcf19433
KO		 138 ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha),
139 ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb),
b43419f2
MC		 140 ISA_EXT_DATA_ENTRY(zvks, PRIV_VERSION_1_12_0, ext_zvks),
141 ISA_EXT_DATA_ENTRY(zvksc, PRIV_VERSION_1_12_0, ext_zvksc),
8b045ff4 142 ISA_EXT_DATA_ENTRY(zvksed, PRIV_VERSION_1_12_0, ext_zvksed),
b43419f2 143 ISA_EXT_DATA_ENTRY(zvksg, PRIV_VERSION_1_12_0, ext_zvksg),
2350881c 144 ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh),
1c32b630 145 ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt),
ccc84a75
DHB		 146 ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
147 ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
148 ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
095fe72a 149 ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
3594e3e5 150 ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
ccc84a75
DHB		 151 ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
152 ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf),
153 ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
154 ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu),
155 ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
156 ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
157 ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
158 ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
159 ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb),
160 ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs),
161 ISA_EXT_DATA_ENTRY(xtheadcmo, PRIV_VERSION_1_11_0, ext_xtheadcmo),
162 ISA_EXT_DATA_ENTRY(xtheadcondmov, PRIV_VERSION_1_11_0, ext_xtheadcondmov),
163 ISA_EXT_DATA_ENTRY(xtheadfmemidx, PRIV_VERSION_1_11_0, ext_xtheadfmemidx),
164 ISA_EXT_DATA_ENTRY(xtheadfmv, PRIV_VERSION_1_11_0, ext_xtheadfmv),
165 ISA_EXT_DATA_ENTRY(xtheadmac, PRIV_VERSION_1_11_0, ext_xtheadmac),
166 ISA_EXT_DATA_ENTRY(xtheadmemidx, PRIV_VERSION_1_11_0, ext_xtheadmemidx),
167 ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempair),
168 ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync),
169 ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
7935e2c4
DHB		 170
171 DEFINE_PROP_END_OF_LIST(),
9a1f054d
AP		 172};
173
36c1118d 174bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
9a1f054d 175{
5f2c80f1 176 bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
9a1f054d
AP		 177
178 return *ext_enabled;
179}
180
36c1118d 181void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en)
9a1f054d 182{
5f2c80f1 183 bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
9a1f054d
AP		 184
185 *ext_enabled = en;
186}
187
dc5bd18f 188const char * const riscv_int_regnames[] = {
c45eff30
WL		 189 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
190 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
191 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4",
192 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
193 "x28/t3", "x29/t4", "x30/t5", "x31/t6"
dc5bd18f
MC		 194};
195
2b547084 196const char * const riscv_int_regnamesh[] = {
c45eff30
WL		 197 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h",
198 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h",
199 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h",
200 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h",
201 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h",
202 "x30h/t5h", "x31h/t6h"
2b547084
FP		 203};
204
dc5bd18f 205const char * const riscv_fpr_regnames[] = {
c45eff30
WL		 206 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5",
207 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1",
208 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7",
209 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7",
210 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
211 "f30/ft10", "f31/ft11"
dc5bd18f
MC		 212};
213
b227f6a8
IK		 214const char * const riscv_rvv_regnames[] = {
215 "v0", "v1", "v2", "v3", "v4", "v5", "v6",
216 "v7", "v8", "v9", "v10", "v11", "v12", "v13",
217 "v14", "v15", "v16", "v17", "v18", "v19", "v20",
218 "v21", "v22", "v23", "v24", "v25", "v26", "v27",
219 "v28", "v29", "v30", "v31"
220};
221
9a575d33 222static const char * const riscv_excp_names[] = {
dc5bd18f
MC		 223 "misaligned_fetch",
224 "fault_fetch",
225 "illegal_instruction",
226 "breakpoint",
227 "misaligned_load",
228 "fault_load",
229 "misaligned_store",
230 "fault_store",
231 "user_ecall",
232 "supervisor_ecall",
233 "hypervisor_ecall",
234 "machine_ecall",
235 "exec_page_fault",
236 "load_page_fault",
237 "reserved",
fd990e86 238 "store_page_fault",
ab67a1d0
AF		 239 "reserved",
240 "reserved",
241 "reserved",
242 "reserved",
243 "guest_exec_page_fault",
244 "guest_load_page_fault",
245 "reserved",
fd990e86 246 "guest_store_page_fault",
dc5bd18f
MC		 247};
248
9a575d33 249static const char * const riscv_intr_names[] = {
dc5bd18f
MC		 250 "u_software",
251 "s_software",
205377f8 252 "vs_software",
dc5bd18f
MC		 253 "m_software",
254 "u_timer",
255 "s_timer",
205377f8 256 "vs_timer",
dc5bd18f
MC		 257 "m_timer",
258 "u_external",
6cfcf775 259 "s_external",
205377f8 260 "vs_external",
dc5bd18f 261 "m_external",
426f0348
MC		 262 "reserved",
263 "reserved",
264 "reserved",
265 "reserved"
dc5bd18f
MC		 266};
267
c51a3f5d
YJ		 268const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
269{
270 if (async) {
271 return (cause < ARRAY_SIZE(riscv_intr_names)) ?
272 riscv_intr_names[cause] : "(unknown)";
273 } else {
274 return (cause < ARRAY_SIZE(riscv_excp_names)) ?
275 riscv_excp_names[cause] : "(unknown)";
276 }
277}
278
f51d03b0 279void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
dc5bd18f 280{
e91a7227
RH		 281 env->misa_mxl_max = env->misa_mxl = mxl;
282 env->misa_ext_mask = env->misa_ext = ext;
dc5bd18f
MC		 283}
284
6f23aaeb
AG		 285#ifndef CONFIG_USER_ONLY
286static uint8_t satp_mode_from_str(const char *satp_mode_str)
287{
288 if (!strncmp(satp_mode_str, "mbare", 5)) {
289 return VM_1_10_MBARE;
290 }
291
292 if (!strncmp(satp_mode_str, "sv32", 4)) {
293 return VM_1_10_SV32;
294 }
295
296 if (!strncmp(satp_mode_str, "sv39", 4)) {
297 return VM_1_10_SV39;
298 }
299
300 if (!strncmp(satp_mode_str, "sv48", 4)) {
301 return VM_1_10_SV48;
302 }
303
304 if (!strncmp(satp_mode_str, "sv57", 4)) {
305 return VM_1_10_SV57;
306 }
307
308 if (!strncmp(satp_mode_str, "sv64", 4)) {
309 return VM_1_10_SV64;
310 }
311
312 g_assert_not_reached();
313}
314
315uint8_t satp_mode_max_from_map(uint32_t map)
316{
3a2fc235
DHB		 317 /*
318 * 'map = 0' will make us return (31 - 32), which C will
319 * happily overflow to UINT_MAX. There's no good result to
320 * return if 'map = 0' (e.g. returning 0 will be ambiguous
321 * with the result for 'map = 1').
322 *
323 * Assert out if map = 0. Callers will have to deal with
324 * it outside of this function.
325 */
326 g_assert(map > 0);
327
6f23aaeb
AG		 328 /* map here has at least one bit set, so no problem with clz */
329 return 31 - __builtin_clz(map);
330}
331
332const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit)
333{
334 if (is_32_bit) {
335 switch (satp_mode) {
336 case VM_1_10_SV32:
337 return "sv32";
338 case VM_1_10_MBARE:
339 return "none";
340 }
341 } else {
342 switch (satp_mode) {
343 case VM_1_10_SV64:
344 return "sv64";
345 case VM_1_10_SV57:
346 return "sv57";
347 case VM_1_10_SV48:
348 return "sv48";
349 case VM_1_10_SV39:
350 return "sv39";
351 case VM_1_10_MBARE:
352 return "none";
353 }
354 }
355
356 g_assert_not_reached();
357}
358
6df3747a
AG		 359static void set_satp_mode_max_supported(RISCVCPU *cpu,
360 uint8_t satp_mode)
6f23aaeb
AG		 361{
362 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32;
6df3747a 363 const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64;
6f23aaeb 364
6df3747a
AG		 365 for (int i = 0; i <= satp_mode; ++i) {
366 if (valid_vm[i]) {
367 cpu->cfg.satp_mode.supported |= (1 << i);
368 }
6f23aaeb
AG		 369 }
370}
6df3747a
AG		 371
372/* Set the satp mode to the max supported */
373static void set_satp_mode_default_map(RISCVCPU *cpu)
374{
d379c748
DHB		 375 /*
376 * Bare CPUs do not default to the max available.
377 * Users must set a valid satp_mode in the command
378 * line.
379 */
380 if (object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_BARE_CPU) != NULL) {
381 warn_report("No satp mode set. Defaulting to 'bare'");
382 cpu->cfg.satp_mode.map = (1 << VM_1_10_MBARE);
383 return;
384 }
385
6df3747a
AG		 386 cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported;
387}
6f23aaeb
AG		 388#endif
389
dc5bd18f
MC		 390static void riscv_any_cpu_init(Object *obj)
391{
7f0bdfb5
DHB		 392 RISCVCPU *cpu = RISCV_CPU(obj);
393 CPURISCVState *env = &cpu->env;
3820602f 394#if defined(TARGET_RISCV32)
f51d03b0 395 riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
3820602f 396#elif defined(TARGET_RISCV64)
f51d03b0 397 riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
3820602f 398#endif
6df3747a
AG		 399
400#ifndef CONFIG_USER_ONLY
401 set_satp_mode_max_supported(RISCV_CPU(obj),
c45eff30
WL		 402 riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ?
403 VM_1_10_SV32 : VM_1_10_SV57);
6df3747a
AG		 404#endif
405
b9a2b98e 406 env->priv_ver = PRIV_VERSION_LATEST;
7f0bdfb5
DHB		 407
408 /* inherited from parent obj via riscv_cpu_init() */
12b12a14 409 cpu->cfg.ext_zifencei = true;
960b389b 410 cpu->cfg.ext_zicsr = true;
7f0bdfb5
DHB		 411 cpu->cfg.mmu = true;
412 cpu->cfg.pmp = true;
dc5bd18f
MC		 413}
414
b97e5a6b
DHB		 415static void riscv_max_cpu_init(Object *obj)
416{
417 RISCVCPU *cpu = RISCV_CPU(obj);
418 CPURISCVState *env = &cpu->env;
419 RISCVMXL mlx = MXL_RV64;
420
421#ifdef TARGET_RISCV32
422 mlx = MXL_RV32;
423#endif
f51d03b0 424 riscv_cpu_set_misa(env, mlx, 0);
b97e5a6b
DHB		 425 env->priv_ver = PRIV_VERSION_LATEST;
426#ifndef CONFIG_USER_ONLY
427 set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ?
428 VM_1_10_SV32 : VM_1_10_SV57);
429#endif
430}
431
094b072c
AF		 432#if defined(TARGET_RISCV64)
433static void rv64_base_cpu_init(Object *obj)
8903bf6e
AF		 434{
435 CPURISCVState *env = &RISCV_CPU(obj)->env;
b55d7d34 436 /* We set this in the realise function */
f51d03b0 437 riscv_cpu_set_misa(env, MXL_RV64, 0);
18800095 438 /* Set latest version of privileged specification */
b9a2b98e 439 env->priv_ver = PRIV_VERSION_LATEST;
6df3747a
AG		 440#ifndef CONFIG_USER_ONLY
441 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
442#endif
8903bf6e
AF		 443}
444
114baaca 445static void rv64_sifive_u_cpu_init(Object *obj)
dc5bd18f 446{
7f0bdfb5
DHB		 447 RISCVCPU *cpu = RISCV_CPU(obj);
448 CPURISCVState *env = &cpu->env;
f51d03b0
DHB		 449 riscv_cpu_set_misa(env, MXL_RV64,
450 RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
8c6eeb50 451 env->priv_ver = PRIV_VERSION_1_10_0;
6df3747a
AG		 452#ifndef CONFIG_USER_ONLY
453 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39);
454#endif
7f0bdfb5
DHB		 455
456 /* inherited from parent obj via riscv_cpu_init() */
12b12a14 457 cpu->cfg.ext_zifencei = true;
960b389b 458 cpu->cfg.ext_zicsr = true;
7f0bdfb5
DHB		 459 cpu->cfg.mmu = true;
460 cpu->cfg.pmp = true;
dc5bd18f
MC		 461}
462
114baaca 463static void rv64_sifive_e_cpu_init(Object *obj)
36b80ad9
AF		 464{
465 CPURISCVState *env = &RISCV_CPU(obj)->env;
26b2bc58
AF		 466 RISCVCPU *cpu = RISCV_CPU(obj);
467
f51d03b0 468 riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
8c6eeb50 469 env->priv_ver = PRIV_VERSION_1_10_0;
6df3747a
AG		 470#ifndef CONFIG_USER_ONLY
471 set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
472#endif
7f0bdfb5
DHB		 473
474 /* inherited from parent obj via riscv_cpu_init() */
12b12a14 475 cpu->cfg.ext_zifencei = true;
960b389b 476 cpu->cfg.ext_zicsr = true;
7f0bdfb5 477 cpu->cfg.pmp = true;
36b80ad9 478}
332dab68 479
95bd8daa
CM		 480static void rv64_thead_c906_cpu_init(Object *obj)
481{
482 CPURISCVState *env = &RISCV_CPU(obj)->env;
483 RISCVCPU *cpu = RISCV_CPU(obj);
484
f51d03b0 485 riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU);
8c6eeb50 486 env->priv_ver = PRIV_VERSION_1_11_0;
95bd8daa 487
a47842d1 488 cpu->cfg.ext_zfa = true;
95bd8daa
CM		 489 cpu->cfg.ext_zfh = true;
490 cpu->cfg.mmu = true;
491 cpu->cfg.ext_xtheadba = true;
492 cpu->cfg.ext_xtheadbb = true;
493 cpu->cfg.ext_xtheadbs = true;
494 cpu->cfg.ext_xtheadcmo = true;
495 cpu->cfg.ext_xtheadcondmov = true;
496 cpu->cfg.ext_xtheadfmemidx = true;
497 cpu->cfg.ext_xtheadmac = true;
498 cpu->cfg.ext_xtheadmemidx = true;
499 cpu->cfg.ext_xtheadmempair = true;
500 cpu->cfg.ext_xtheadsync = true;
501
502 cpu->cfg.mvendorid = THEAD_VENDOR_ID;
6df3747a
AG		 503#ifndef CONFIG_USER_ONLY
504 set_satp_mode_max_supported(cpu, VM_1_10_SV39);
505#endif
7f0bdfb5
DHB		 506
507 /* inherited from parent obj via riscv_cpu_init() */
508 cpu->cfg.pmp = true;
95bd8daa
CM		 509}
510
e1d084a8
RP		 511static void rv64_veyron_v1_cpu_init(Object *obj)
512{
513 CPURISCVState *env = &RISCV_CPU(obj)->env;
514 RISCVCPU *cpu = RISCV_CPU(obj);
515
f51d03b0 516 riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH);
e1d084a8
RP		 517 env->priv_ver = PRIV_VERSION_1_12_0;
518
519 /* Enable ISA extensions */
520 cpu->cfg.mmu = true;
12b12a14 521 cpu->cfg.ext_zifencei = true;
960b389b 522 cpu->cfg.ext_zicsr = true;
029f5fee 523 cpu->cfg.pmp = true;
a326a2b0 524 cpu->cfg.ext_zicbom = true;
e1d084a8
RP		 525 cpu->cfg.cbom_blocksize = 64;
526 cpu->cfg.cboz_blocksize = 64;
e57039dd 527 cpu->cfg.ext_zicboz = true;
e1d084a8
RP		 528 cpu->cfg.ext_smaia = true;
529 cpu->cfg.ext_ssaia = true;
530 cpu->cfg.ext_sscofpmf = true;
531 cpu->cfg.ext_sstc = true;
532 cpu->cfg.ext_svinval = true;
533 cpu->cfg.ext_svnapot = true;
534 cpu->cfg.ext_svpbmt = true;
535 cpu->cfg.ext_smstateen = true;
536 cpu->cfg.ext_zba = true;
537 cpu->cfg.ext_zbb = true;
538 cpu->cfg.ext_zbc = true;
539 cpu->cfg.ext_zbs = true;
540 cpu->cfg.ext_XVentanaCondOps = true;
541
542 cpu->cfg.mvendorid = VEYRON_V1_MVENDORID;
543 cpu->cfg.marchid = VEYRON_V1_MARCHID;
544 cpu->cfg.mimpid = VEYRON_V1_MIMPID;
545
546#ifndef CONFIG_USER_ONLY
547 set_satp_mode_max_supported(cpu, VM_1_10_SV48);
548#endif
549}
550
332dab68
FP		 551static void rv128_base_cpu_init(Object *obj)
552{
553 if (qemu_tcg_mttcg_enabled()) {
554 /* Missing 128-bit aligned atomics */
555 error_report("128-bit RISC-V currently does not work with Multi "
556 "Threaded TCG. Please use: -accel tcg,thread=single");
557 exit(EXIT_FAILURE);
558 }
559 CPURISCVState *env = &RISCV_CPU(obj)->env;
560 /* We set this in the realise function */
f51d03b0 561 riscv_cpu_set_misa(env, MXL_RV128, 0);
18800095 562 /* Set latest version of privileged specification */
b9a2b98e 563 env->priv_ver = PRIV_VERSION_LATEST;
6df3747a
AG		 564#ifndef CONFIG_USER_ONLY
565 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
566#endif
332dab68 567}
d379c748
DHB		 568
569static void rv64i_bare_cpu_init(Object *obj)
570{
571 CPURISCVState *env = &RISCV_CPU(obj)->env;
572 riscv_cpu_set_misa(env, MXL_RV64, RVI);
573
574 /* Remove the defaults from the parent class */
575 RISCV_CPU(obj)->cfg.ext_zicntr = false;
576 RISCV_CPU(obj)->cfg.ext_zihpm = false;
577
578 /* Set to QEMU's first supported priv version */
579 env->priv_ver = PRIV_VERSION_1_10_0;
580
581 /*
582 * Support all available satp_mode settings. The default
583 * value will be set to MBARE if the user doesn't set
584 * satp_mode manually (see set_satp_mode_default()).
585 */
586#ifndef CONFIG_USER_ONLY
587 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV64);
588#endif
589}
114baaca 590#else
094b072c
AF		 591static void rv32_base_cpu_init(Object *obj)
592{
593 CPURISCVState *env = &RISCV_CPU(obj)->env;
594 /* We set this in the realise function */
f51d03b0 595 riscv_cpu_set_misa(env, MXL_RV32, 0);
18800095 596 /* Set latest version of privileged specification */
b9a2b98e 597 env->priv_ver = PRIV_VERSION_LATEST;
6df3747a
AG		 598#ifndef CONFIG_USER_ONLY
599 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
600#endif
094b072c
AF		 601}
602
114baaca
AF		 603static void rv32_sifive_u_cpu_init(Object *obj)
604{
7f0bdfb5
DHB		 605 RISCVCPU *cpu = RISCV_CPU(obj);
606 CPURISCVState *env = &cpu->env;
f51d03b0
DHB		 607 riscv_cpu_set_misa(env, MXL_RV32,
608 RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
8c6eeb50 609 env->priv_ver = PRIV_VERSION_1_10_0;
6df3747a
AG		 610#ifndef CONFIG_USER_ONLY
611 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
612#endif
7f0bdfb5
DHB		 613
614 /* inherited from parent obj via riscv_cpu_init() */
12b12a14 615 cpu->cfg.ext_zifencei = true;
960b389b 616 cpu->cfg.ext_zicsr = true;
7f0bdfb5
DHB		 617 cpu->cfg.mmu = true;
618 cpu->cfg.pmp = true;
114baaca 619}
36b80ad9 620
114baaca
AF		 621static void rv32_sifive_e_cpu_init(Object *obj)
622{
623 CPURISCVState *env = &RISCV_CPU(obj)->env;
26b2bc58
AF		 624 RISCVCPU *cpu = RISCV_CPU(obj);
625
f51d03b0 626 riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
8c6eeb50 627 env->priv_ver = PRIV_VERSION_1_10_0;
6df3747a
AG		 628#ifndef CONFIG_USER_ONLY
629 set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
630#endif
7f0bdfb5
DHB		 631
632 /* inherited from parent obj via riscv_cpu_init() */
12b12a14 633 cpu->cfg.ext_zifencei = true;
960b389b 634 cpu->cfg.ext_zicsr = true;
7f0bdfb5 635 cpu->cfg.pmp = true;
114baaca 636}
d8e72bd1 637
e8905c6c 638static void rv32_ibex_cpu_init(Object *obj)
dc5bd18f
MC		 639{
640 CPURISCVState *env = &RISCV_CPU(obj)->env;
26b2bc58
AF		 641 RISCVCPU *cpu = RISCV_CPU(obj);
642
f51d03b0 643 riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
c541b07d 644 env->priv_ver = PRIV_VERSION_1_12_0;
6df3747a
AG		 645#ifndef CONFIG_USER_ONLY
646 set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
647#endif
7f0bdfb5 648 /* inherited from parent obj via riscv_cpu_init() */
12b12a14 649 cpu->cfg.ext_zifencei = true;
960b389b 650 cpu->cfg.ext_zicsr = true;
7f0bdfb5 651 cpu->cfg.pmp = true;
095fe72a 652 cpu->cfg.ext_smepmp = true;
dc5bd18f
MC		 653}
654
2fdd2c09 655static void rv32_imafcu_nommu_cpu_init(Object *obj)
d784733b
CW		 656{
657 CPURISCVState *env = &RISCV_CPU(obj)->env;
26b2bc58
AF		 658 RISCVCPU *cpu = RISCV_CPU(obj);
659
f51d03b0 660 riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
8c6eeb50 661 env->priv_ver = PRIV_VERSION_1_10_0;
6df3747a
AG		 662#ifndef CONFIG_USER_ONLY
663 set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
664#endif
7f0bdfb5
DHB		 665
666 /* inherited from parent obj via riscv_cpu_init() */
12b12a14 667 cpu->cfg.ext_zifencei = true;
960b389b 668 cpu->cfg.ext_zicsr = true;
7f0bdfb5 669 cpu->cfg.pmp = true;
d784733b 670}
eab15862 671#endif
dc5bd18f
MC		 672
673static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
674{
675 ObjectClass *oc;
676 char *typename;
677 char **cpuname;
678
679 cpuname = g_strsplit(cpu_model, ",", 1);
680 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]);
681 oc = object_class_by_name(typename);
682 g_strfreev(cpuname);
683 g_free(typename);
d5be19f5 684
dc5bd18f
MC		 685 return oc;
686}
687
b933720b
DHB		 688char *riscv_cpu_get_name(RISCVCPU *cpu)
689{
690 RISCVCPUClass *rcc = RISCV_CPU_GET_CLASS(cpu);
691 const char *typename = object_class_get_name(OBJECT_CLASS(rcc));
692
693 g_assert(g_str_has_suffix(typename, RISCV_CPU_TYPE_SUFFIX));
694
4b26aa9f 695 return cpu_model_from_type(typename);
b933720b
DHB		 696}
697
90c84c56 698static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
dc5bd18f
MC		 699{
700 RISCVCPU *cpu = RISCV_CPU(cs);
701 CPURISCVState *env = &cpu->env;
b227f6a8
IK		 702 int i, j;
703 uint8_t *p;
dc5bd18f 704
df30e652
AF		 705#if !defined(CONFIG_USER_ONLY)
706 if (riscv_has_ext(env, RVH)) {
38256529 707 qemu_fprintf(f, " %s %d\n", "V = ", env->virt_enabled);
df30e652
AF		 708 }
709#endif
90c84c56 710 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc);
dc5bd18f 711#ifndef CONFIG_USER_ONLY
665b90d8
RH		 712 {
713 static const int dump_csrs[] = {
714 CSR_MHARTID,
715 CSR_MSTATUS,
716 CSR_MSTATUSH,
bc7dca13
BM		 717 /*
718 * CSR_SSTATUS is intentionally omitted here as its value
719 * can be figured out by looking at CSR_MSTATUS
720 */
665b90d8
RH		 721 CSR_HSTATUS,
722 CSR_VSSTATUS,
723 CSR_MIP,
724 CSR_MIE,
725 CSR_MIDELEG,
726 CSR_HIDELEG,
727 CSR_MEDELEG,
728 CSR_HEDELEG,
729 CSR_MTVEC,
730 CSR_STVEC,
731 CSR_VSTVEC,
732 CSR_MEPC,
733 CSR_SEPC,
734 CSR_VSEPC,
735 CSR_MCAUSE,
736 CSR_SCAUSE,
737 CSR_VSCAUSE,
738 CSR_MTVAL,
739 CSR_STVAL,
740 CSR_HTVAL,
741 CSR_MTVAL2,
742 CSR_MSCRATCH,
743 CSR_SSCRATCH,
744 CSR_SATP,
bd5594ca
AB		 745 CSR_MMTE,
746 CSR_UPMBASE,
747 CSR_UPMMASK,
748 CSR_SPMBASE,
749 CSR_SPMMASK,
750 CSR_MPMBASE,
751 CSR_MPMMASK,
665b90d8
RH		 752 };
753
29332994 754 for (i = 0; i < ARRAY_SIZE(dump_csrs); ++i) {
665b90d8
RH		 755 int csrno = dump_csrs[i];
756 target_ulong val = 0;
757 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
758
759 /*
760 * Rely on the smode, hmode, etc, predicates within csr.c
761 * to do the filtering of the registers that are present.
762 */
763 if (res == RISCV_EXCP_NONE) {
764 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
765 csr_ops[csrno].name, val);
766 }
767 }
df30e652 768 }
dc5bd18f
MC		 769#endif
770
771 for (i = 0; i < 32; i++) {
e573a7f3 772 qemu_fprintf(f, " %-8s " TARGET_FMT_lx,
90c84c56 773 riscv_int_regnames[i], env->gpr[i]);
dc5bd18f 774 if ((i & 3) == 3) {
90c84c56 775 qemu_fprintf(f, "\n");
dc5bd18f
MC		 776 }
777 }
86ea1880
RH		 778 if (flags & CPU_DUMP_FPU) {
779 for (i = 0; i < 32; i++) {
e573a7f3 780 qemu_fprintf(f, " %-8s %016" PRIx64,
90c84c56 781 riscv_fpr_regnames[i], env->fpr[i]);
86ea1880 782 if ((i & 3) == 3) {
90c84c56 783 qemu_fprintf(f, "\n");
86ea1880 784 }
dc5bd18f
MC		 785 }
786 }
b227f6a8
IK		 787 if (riscv_has_ext(env, RVV) && (flags & CPU_DUMP_VPU)) {
788 static const int dump_rvv_csrs[] = {
789 CSR_VSTART,
790 CSR_VXSAT,
791 CSR_VXRM,
792 CSR_VCSR,
793 CSR_VL,
794 CSR_VTYPE,
795 CSR_VLENB,
796 };
29332994 797 for (i = 0; i < ARRAY_SIZE(dump_rvv_csrs); ++i) {
b227f6a8
IK		 798 int csrno = dump_rvv_csrs[i];
799 target_ulong val = 0;
800 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
801
802 /*
803 * Rely on the smode, hmode, etc, predicates within csr.c
804 * to do the filtering of the registers that are present.
805 */
806 if (res == RISCV_EXCP_NONE) {
807 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
808 csr_ops[csrno].name, val);
809 }
810 }
811 uint16_t vlenb = cpu->cfg.vlen >> 3;
812
813 for (i = 0; i < 32; i++) {
814 qemu_fprintf(f, " %-8s ", riscv_rvv_regnames[i]);
815 p = (uint8_t *)env->vreg;
816 for (j = vlenb - 1 ; j >= 0; j--) {
817 qemu_fprintf(f, "%02x", *(p + i * vlenb + BYTE(j)));
818 }
819 qemu_fprintf(f, "\n");
820 }
821 }
dc5bd18f
MC		 822}
823
824static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
825{
826 RISCVCPU *cpu = RISCV_CPU(cs);
827 CPURISCVState *env = &cpu->env;
bf9e776e
LZ		 828
829 if (env->xl == MXL_RV32) {
830 env->pc = (int32_t)value;
831 } else {
832 env->pc = value;
833 }
dc5bd18f
MC		 834}
835
e4fdf9df
RH		 836static vaddr riscv_cpu_get_pc(CPUState *cs)
837{
838 RISCVCPU *cpu = RISCV_CPU(cs);
839 CPURISCVState *env = &cpu->env;
840
841 /* Match cpu_get_tb_cpu_state. */
842 if (env->xl == MXL_RV32) {
843 return env->pc & UINT32_MAX;
844 }
845 return env->pc;
846}
847
dc5bd18f
MC		 848static bool riscv_cpu_has_work(CPUState *cs)
849{
850#ifndef CONFIG_USER_ONLY
851 RISCVCPU *cpu = RISCV_CPU(cs);
852 CPURISCVState *env = &cpu->env;
853 /*
854 * Definition of the WFI instruction requires it to ignore the privilege
855 * mode and delegation registers, but respect individual enables
856 */
1697837e 857 return riscv_cpu_all_pending(env) != 0 ||
40336d5b
RK		 858 riscv_cpu_sirq_pending(env) != RISCV_EXCP_NONE ||
859 riscv_cpu_vsirq_pending(env) != RISCV_EXCP_NONE;
dc5bd18f
MC		 860#else
861 return true;
862#endif
863}
864
4fa485a7 865static void riscv_cpu_reset_hold(Object *obj)
dc5bd18f 866{
43dc93af
AP		 867#ifndef CONFIG_USER_ONLY
868 uint8_t iprio;
869 int i, irq, rdzero;
870#endif
4fa485a7 871 CPUState *cs = CPU(obj);
dc5bd18f
MC		 872 RISCVCPU *cpu = RISCV_CPU(cs);
873 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
874 CPURISCVState *env = &cpu->env;
875
4fa485a7
PM		 876 if (mcc->parent_phases.hold) {
877 mcc->parent_phases.hold(obj);
878 }
dc5bd18f 879#ifndef CONFIG_USER_ONLY
e91a7227 880 env->misa_mxl = env->misa_mxl_max;
dc5bd18f
MC		 881 env->priv = PRV_M;
882 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
92371bd9
RH		 883 if (env->misa_mxl > MXL_RV32) {
884 /*
885 * The reset status of SXL/UXL is undefined, but mstatus is WARL
886 * and we must ensure that the value after init is valid for read.
887 */
888 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl);
889 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl);
5a2ae235
LZ		 890 if (riscv_has_ext(env, RVH)) {
891 env->vsstatus = set_field(env->vsstatus,
892 MSTATUS64_SXL, env->misa_mxl);
893 env->vsstatus = set_field(env->vsstatus,
894 MSTATUS64_UXL, env->misa_mxl);
895 env->mstatus_hs = set_field(env->mstatus_hs,
896 MSTATUS64_SXL, env->misa_mxl);
897 env->mstatus_hs = set_field(env->mstatus_hs,
898 MSTATUS64_UXL, env->misa_mxl);
899 }
92371bd9 900 }
dc5bd18f 901 env->mcause = 0;
881df35d 902 env->miclaim = MIP_SGEIP;
dc5bd18f 903 env->pc = env->resetvec;
62cf0245 904 env->bins = 0;
ec352d0c 905 env->two_stage_lookup = false;
43dc93af 906
0af3f115 907 env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) |
ed67d637 908 (cpu->cfg.ext_svadu ? MENVCFG_ADUE : 0);
0af3f115 909 env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) |
ed67d637 910 (cpu->cfg.ext_svadu ? HENVCFG_ADUE : 0);
7a6613da 911
43dc93af
AP		 912 /* Initialized default priorities of local interrupts. */
913 for (i = 0; i < ARRAY_SIZE(env->miprio); i++) {
914 iprio = riscv_cpu_default_priority(i);
915 env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio;
916 env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio;
917 env->hviprio[i] = 0;
918 }
919 i = 0;
920 while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) {
921 if (!rdzero) {
922 env->hviprio[irq] = env->miprio[irq];
923 }
924 i++;
925 }
4bbe8033 926 /* mmte is supposed to have pm.current hardwired to 1 */
42967f40 927 env->mmte |= (EXT_STATUS_INITIAL | MMTE_M_PM_CURRENT);
4bf501dc
MC		 928
929 /*
930 * Clear mseccfg and unlock all the PMP entries upon reset.
931 * This is allowed as per the priv and smepmp specifications
932 * and is needed to clear stale entries across reboots.
933 */
934 if (riscv_cpu_cfg(env)->ext_smepmp) {
935 env->mseccfg = 0;
936 }
937
938 pmp_unlock_entries(env);
dc5bd18f 939#endif
440544e1 940 env->xl = riscv_cpu_mxl(env);
40bfa5f6 941 riscv_cpu_update_mask(env);
330d2ae3 942 cs->exception_index = RISCV_EXCP_NONE;
c13b169f 943 env->load_res = -1;
dc5bd18f 944 set_default_nan_mode(1, &env->fp_status);
ad40be27
YJ		 945
946#ifndef CONFIG_USER_ONLY
cdfb2905 947 if (cpu->cfg.debug) {
a7c272df 948 riscv_trigger_reset_hold(env);
b6092544
BM		 949 }
950
ad40be27
YJ		 951 if (kvm_enabled()) {
952 kvm_riscv_reset_vcpu(cpu);
953 }
954#endif
dc5bd18f
MC		 955}
956
957static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
958{
5c5a47f1 959 RISCVCPU *cpu = RISCV_CPU(s);
94692c3a 960 CPURISCVState *env = &cpu->env;
454c2201 961 info->target_info = &cpu->cfg;
db23e5d9 962
94692c3a 963 switch (env->xl) {
db23e5d9 964 case MXL_RV32:
5c5a47f1 965 info->print_insn = print_insn_riscv32;
db23e5d9
RH		 966 break;
967 case MXL_RV64:
5c5a47f1 968 info->print_insn = print_insn_riscv64;
db23e5d9 969 break;
332dab68
FP		 970 case MXL_RV128:
971 info->print_insn = print_insn_riscv128;
972 break;
db23e5d9
RH		 973 default:
974 g_assert_not_reached();
5c5a47f1 975 }
dc5bd18f
MC		 976}
977
6f23aaeb
AG		 978#ifndef CONFIG_USER_ONLY
979static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp)
980{
981 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32;
3a2fc235
DHB		 982 uint8_t satp_mode_map_max, satp_mode_supported_max;
983
984 /* The CPU wants the OS to decide which satp mode to use */
985 if (cpu->cfg.satp_mode.supported == 0) {
986 return;
987 }
988
989 satp_mode_supported_max =
990 satp_mode_max_from_map(cpu->cfg.satp_mode.supported);
6f23aaeb
AG		 991
992 if (cpu->cfg.satp_mode.map == 0) {
993 if (cpu->cfg.satp_mode.init == 0) {
994 /* If unset by the user, we fallback to the default satp mode. */
995 set_satp_mode_default_map(cpu);
996 } else {
997 /*
998 * Find the lowest level that was disabled and then enable the
999 * first valid level below which can be found in
1000 * valid_vm_1_10_32/64.
1001 */
1002 for (int i = 1; i < 16; ++i) {
6df3747a
AG		 1003 if ((cpu->cfg.satp_mode.init & (1 << i)) &&
1004 (cpu->cfg.satp_mode.supported & (1 << i))) {
6f23aaeb 1005 for (int j = i - 1; j >= 0; --j) {
6df3747a 1006 if (cpu->cfg.satp_mode.supported & (1 << j)) {
6f23aaeb
AG		 1007 cpu->cfg.satp_mode.map |= (1 << j);
1008 break;
1009 }
1010 }
1011 break;
1012 }
1013 }
1014 }
1015 }
1016
6df3747a
AG		 1017 satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map);
1018
1019 /* Make sure the user asked for a supported configuration (HW and qemu) */
1020 if (satp_mode_map_max > satp_mode_supported_max) {
1021 error_setg(errp, "satp_mode %s is higher than hw max capability %s",
1022 satp_mode_str(satp_mode_map_max, rv32),
1023 satp_mode_str(satp_mode_supported_max, rv32));
1024 return;
6f23aaeb
AG		 1025 }
1026
1027 /*
1028 * Make sure the user did not ask for an invalid configuration as per
1029 * the specification.
1030 */
6f23aaeb 1031 if (!rv32) {
6df3747a 1032 for (int i = satp_mode_map_max - 1; i >= 0; --i) {
6f23aaeb
AG		 1033 if (!(cpu->cfg.satp_mode.map & (1 << i)) &&
1034 (cpu->cfg.satp_mode.init & (1 << i)) &&
6df3747a 1035 (cpu->cfg.satp_mode.supported & (1 << i))) {
6f23aaeb
AG		 1036 error_setg(errp, "cannot disable %s satp mode if %s "
1037 "is enabled", satp_mode_str(i, false),
6df3747a 1038 satp_mode_str(satp_mode_map_max, false));
6f23aaeb
AG		 1039 return;
1040 }
1041 }
1042 }
1043
1044 /* Finally expand the map so that all valid modes are set */
6df3747a
AG		 1045 for (int i = satp_mode_map_max - 1; i >= 0; --i) {
1046 if (cpu->cfg.satp_mode.supported & (1 << i)) {
6f23aaeb
AG		 1047 cpu->cfg.satp_mode.map |= (1 << i);
1048 }
1049 }
1050}
1051#endif
1052
a13a6082 1053void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
6f23aaeb 1054{
6f23aaeb
AG		 1055 Error *local_err = NULL;
1056
a13a6082
DHB		 1057 /*
1058 * KVM accel does not have a specialized finalize()
1059 * callback because its extensions are validated
1060 * in the get()/set() callbacks of each property.
1061 */
1062 if (tcg_enabled()) {
1063 riscv_tcg_cpu_finalize_features(cpu, &local_err);
1064 if (local_err != NULL) {
1065 error_propagate(errp, local_err);
1066 return;
1067 }
1068 }
1069
1070#ifndef CONFIG_USER_ONLY
6f23aaeb
AG		 1071 riscv_cpu_satp_mode_finalize(cpu, &local_err);
1072 if (local_err != NULL) {
1073 error_propagate(errp, local_err);
1074 return;
1075 }
1076#endif
1077}
1078
eddabb6b
DHB		 1079static void riscv_cpu_realize(DeviceState *dev, Error **errp)
1080{
1081 CPUState *cs = CPU(dev);
1082 RISCVCPU *cpu = RISCV_CPU(dev);
1083 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
1084 Error *local_err = NULL;
1085
f57d5f80
DHB		 1086 if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_CPU_ANY) != NULL) {
1087 warn_report("The 'any' CPU is deprecated and will be "
1088 "removed in the future.");
1089 }
1090
eddabb6b
DHB		 1091 cpu_exec_realizefn(cs, &local_err);
1092 if (local_err != NULL) {
1093 error_propagate(errp, local_err);
1094 return;
1095 }
1096
6f23aaeb
AG		 1097 riscv_cpu_finalize_features(cpu, &local_err);
1098 if (local_err != NULL) {
1099 error_propagate(errp, local_err);
1100 return;
1101 }
1102
5371f5cd
JW		 1103 riscv_cpu_register_gdb_regs_for_features(cs);
1104
a7c272df
AO		 1105#ifndef CONFIG_USER_ONLY
1106 if (cpu->cfg.debug) {
1107 riscv_trigger_realize(&cpu->env);
1108 }
1109#endif
1110
dc5bd18f
MC		 1111 qemu_init_vcpu(cs);
1112 cpu_reset(cs);
1113
1114 mcc->parent_realize(dev, errp);
1115}
1116
ef58fad0
DHB		 1117bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu)
1118{
1119 if (tcg_enabled()) {
1120 return riscv_cpu_tcg_compatible(cpu);
1121 }
1122
1123 return true;
1124}
1125
0f0b70ee 1126#ifndef CONFIG_USER_ONLY
6f23aaeb
AG		 1127static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name,
1128 void *opaque, Error **errp)
1129{
1130 RISCVSATPMap *satp_map = opaque;
1131 uint8_t satp = satp_mode_from_str(name);
1132 bool value;
1133
1134 value = satp_map->map & (1 << satp);
1135
1136 visit_type_bool(v, name, &value, errp);
1137}
1138
1139static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name,
1140 void *opaque, Error **errp)
1141{
1142 RISCVSATPMap *satp_map = opaque;
1143 uint8_t satp = satp_mode_from_str(name);
1144 bool value;
1145
1146 if (!visit_type_bool(v, name, &value, errp)) {
1147 return;
1148 }
1149
1150 satp_map->map = deposit32(satp_map->map, satp, 1, value);
1151 satp_map->init |= 1 << satp;
1152}
1153
7d0c302c 1154void riscv_add_satp_mode_properties(Object *obj)
6f23aaeb
AG		 1155{
1156 RISCVCPU *cpu = RISCV_CPU(obj);
1157
1158 if (cpu->env.misa_mxl == MXL_RV32) {
1159 object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp,
1160 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
1161 } else {
1162 object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp,
1163 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
1164 object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp,
1165 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
1166 object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp,
1167 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
1168 object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp,
1169 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
1170 }
1171}
1172
0f0b70ee
AF		 1173static void riscv_cpu_set_irq(void *opaque, int irq, int level)
1174{
1175 RISCVCPU *cpu = RISCV_CPU(opaque);
cd032fe7 1176 CPURISCVState *env = &cpu->env;
0f0b70ee 1177
cd032fe7
AP		 1178 if (irq < IRQ_LOCAL_MAX) {
1179 switch (irq) {
1180 case IRQ_U_SOFT:
1181 case IRQ_S_SOFT:
1182 case IRQ_VS_SOFT:
1183 case IRQ_M_SOFT:
1184 case IRQ_U_TIMER:
1185 case IRQ_S_TIMER:
1186 case IRQ_VS_TIMER:
1187 case IRQ_M_TIMER:
1188 case IRQ_U_EXT:
cd032fe7
AP		 1189 case IRQ_VS_EXT:
1190 case IRQ_M_EXT:
8b5c807b 1191 if (kvm_enabled()) {
cd032fe7 1192 kvm_riscv_set_irq(cpu, irq, level);
8b5c807b 1193 } else {
bbb9fc25 1194 riscv_cpu_update_mip(env, 1 << irq, BOOL_TO_MASK(level));
8b5c807b 1195 }
cd032fe7 1196 break;
33fe584f
AF		 1197 case IRQ_S_EXT:
1198 if (kvm_enabled()) {
1199 kvm_riscv_set_irq(cpu, irq, level);
1200 } else {
1201 env->external_seip = level;
bbb9fc25 1202 riscv_cpu_update_mip(env, 1 << irq,
33fe584f
AF		 1203 BOOL_TO_MASK(level | env->software_seip));
1204 }
1205 break;
cd032fe7
AP		 1206 default:
1207 g_assert_not_reached();
2b650fbb 1208 }
cd032fe7
AP		 1209 } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) {
1210 /* Require H-extension for handling guest local interrupts */
1211 if (!riscv_has_ext(env, RVH)) {
1212 g_assert_not_reached();
1213 }
1214
1215 /* Compute bit position in HGEIP CSR */
1216 irq = irq - IRQ_LOCAL_MAX + 1;
1217 if (env->geilen < irq) {
1218 g_assert_not_reached();
1219 }
1220
1221 /* Update HGEIP CSR */
1222 env->hgeip &= ~((target_ulong)1 << irq);
1223 if (level) {
1224 env->hgeip |= (target_ulong)1 << irq;
1225 }
1226
1227 /* Update mip.SGEIP bit */
bbb9fc25 1228 riscv_cpu_update_mip(env, MIP_SGEIP,
cd032fe7
AP		 1229 BOOL_TO_MASK(!!(env->hgeie & env->hgeip)));
1230 } else {
0f0b70ee
AF		 1231 g_assert_not_reached();
1232 }
1233}
1234#endif /* CONFIG_USER_ONLY */
1235
977bbb04
DHB		 1236static bool riscv_cpu_is_dynamic(Object *cpu_obj)
1237{
1238 return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
1239}
1240
977bbb04
DHB		 1241static void riscv_cpu_post_init(Object *obj)
1242{
d86c25b2 1243 accel_cpu_instance_init(CPU(obj));
977bbb04
DHB		 1244}
1245
dc5bd18f
MC		 1246static void riscv_cpu_init(Object *obj)
1247{
0f0b70ee 1248#ifndef CONFIG_USER_ONLY
8fa08d7e 1249 qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq,
cd032fe7 1250 IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
0f0b70ee 1251#endif /* CONFIG_USER_ONLY */
c0040993
DHB		 1252
1253 /*
1254 * The timer and performance counters extensions were supported
1255 * in QEMU before they were added as discrete extensions in the
1256 * ISA. To keep compatibility we'll always default them to 'true'
1257 * for all CPUs. Each accelerator will decide what to do when
1258 * users disable them.
1259 */
1260 RISCV_CPU(obj)->cfg.ext_zicntr = true;
08241216 1261 RISCV_CPU(obj)->cfg.ext_zihpm = true;
dc5bd18f
MC		 1262}
1263
ed7e6182
DHB		 1264typedef struct misa_ext_info {
1265 const char *name;
1266 const char *description;
1267} MISAExtInfo;
1268
1269#define MISA_INFO_IDX(_bit) \
1270 __builtin_ctz(_bit)
1271
1272#define MISA_EXT_INFO(_bit, _propname, _descr) \
1273 [MISA_INFO_IDX(_bit)] = {.name = _propname, .description = _descr}
1274
1275static const MISAExtInfo misa_ext_info_arr[] = {
1276 MISA_EXT_INFO(RVA, "a", "Atomic instructions"),
1277 MISA_EXT_INFO(RVC, "c", "Compressed instructions"),
1278 MISA_EXT_INFO(RVD, "d", "Double-precision float point"),
1279 MISA_EXT_INFO(RVF, "f", "Single-precision float point"),
1280 MISA_EXT_INFO(RVI, "i", "Base integer instruction set"),
1281 MISA_EXT_INFO(RVE, "e", "Base integer instruction set (embedded)"),
1282 MISA_EXT_INFO(RVM, "m", "Integer multiplication and division"),
1283 MISA_EXT_INFO(RVS, "s", "Supervisor-level instructions"),
1284 MISA_EXT_INFO(RVU, "u", "User-level instructions"),
1285 MISA_EXT_INFO(RVH, "h", "Hypervisor"),
1286 MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
1287 MISA_EXT_INFO(RVV, "v", "Vector operations"),
1288 MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
1289};
1290
1291static int riscv_validate_misa_info_idx(uint32_t bit)
1292{
1293 int idx;
1294
1295 /*
1296 * Our lowest valid input (RVA) is 1 and
1297 * __builtin_ctz() is UB with zero.
1298 */
1299 g_assert(bit != 0);
1300 idx = MISA_INFO_IDX(bit);
1301
1302 g_assert(idx < ARRAY_SIZE(misa_ext_info_arr));
1303 return idx;
1304}
1305
1306const char *riscv_get_misa_ext_name(uint32_t bit)
1307{
1308 int idx = riscv_validate_misa_info_idx(bit);
1309 const char *val = misa_ext_info_arr[idx].name;
1310
1311 g_assert(val != NULL);
1312 return val;
1313}
1314
1315const char *riscv_get_misa_ext_description(uint32_t bit)
1316{
1317 int idx = riscv_validate_misa_info_idx(bit);
1318 const char *val = misa_ext_info_arr[idx].description;
1319
1320 g_assert(val != NULL);
1321 return val;
1322}
1323
549cbf78
DHB		 1324#define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \
1325 {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
1326 .enabled = _defval}
1327
32fa1776 1328const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
9d3d60b7 1329 /* Defaults for standard extensions */
549cbf78 1330 MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
12b12a14 1331 MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true),
960b389b 1332 MULTI_EXT_CFG_BOOL("zicsr", ext_zicsr, true),
8043effd
DHB		 1333 MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true),
1334 MULTI_EXT_CFG_BOOL("zihintpause", ext_zihintpause, true),
b52d49e9 1335 MULTI_EXT_CFG_BOOL("zacas", ext_zacas, false),
8043effd
DHB		 1336 MULTI_EXT_CFG_BOOL("zawrs", ext_zawrs, true),
1337 MULTI_EXT_CFG_BOOL("zfa", ext_zfa, true),
1338 MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false),
1339 MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false),
1340 MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false),
1341 MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
1342 MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
549cbf78
DHB		 1343 MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true),
1344
095fe72a 1345 MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false),
549cbf78
DHB		 1346 MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false),
1347 MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true),
1348 MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false),
1349 MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false),
1350 MULTI_EXT_CFG_BOOL("svpbmt", ext_svpbmt, false),
1351
c0040993 1352 MULTI_EXT_CFG_BOOL("zicntr", ext_zicntr, true),
08241216 1353 MULTI_EXT_CFG_BOOL("zihpm", ext_zihpm, true),
c0040993 1354
549cbf78
DHB		 1355 MULTI_EXT_CFG_BOOL("zba", ext_zba, true),
1356 MULTI_EXT_CFG_BOOL("zbb", ext_zbb, true),
1357 MULTI_EXT_CFG_BOOL("zbc", ext_zbc, true),
1358 MULTI_EXT_CFG_BOOL("zbkb", ext_zbkb, false),
1359 MULTI_EXT_CFG_BOOL("zbkc", ext_zbkc, false),
1360 MULTI_EXT_CFG_BOOL("zbkx", ext_zbkx, false),
1361 MULTI_EXT_CFG_BOOL("zbs", ext_zbs, true),
1362 MULTI_EXT_CFG_BOOL("zk", ext_zk, false),
1363 MULTI_EXT_CFG_BOOL("zkn", ext_zkn, false),
1364 MULTI_EXT_CFG_BOOL("zknd", ext_zknd, false),
1365 MULTI_EXT_CFG_BOOL("zkne", ext_zkne, false),
1366 MULTI_EXT_CFG_BOOL("zknh", ext_zknh, false),
1367 MULTI_EXT_CFG_BOOL("zkr", ext_zkr, false),
1368 MULTI_EXT_CFG_BOOL("zks", ext_zks, false),
1369 MULTI_EXT_CFG_BOOL("zksed", ext_zksed, false),
1370 MULTI_EXT_CFG_BOOL("zksh", ext_zksh, false),
1371 MULTI_EXT_CFG_BOOL("zkt", ext_zkt, false),
1372
1373 MULTI_EXT_CFG_BOOL("zdinx", ext_zdinx, false),
1374 MULTI_EXT_CFG_BOOL("zfinx", ext_zfinx, false),
1375 MULTI_EXT_CFG_BOOL("zhinx", ext_zhinx, false),
1376 MULTI_EXT_CFG_BOOL("zhinxmin", ext_zhinxmin, false),
1377
a326a2b0 1378 MULTI_EXT_CFG_BOOL("zicbom", ext_zicbom, true),
cc2bf69a 1379 MULTI_EXT_CFG_BOOL("zicbop", ext_zicbop, true),
e57039dd 1380 MULTI_EXT_CFG_BOOL("zicboz", ext_zicboz, true),
549cbf78
DHB		 1381
1382 MULTI_EXT_CFG_BOOL("zmmul", ext_zmmul, false),
1383
1384 MULTI_EXT_CFG_BOOL("zca", ext_zca, false),
1385 MULTI_EXT_CFG_BOOL("zcb", ext_zcb, false),
1386 MULTI_EXT_CFG_BOOL("zcd", ext_zcd, false),
1387 MULTI_EXT_CFG_BOOL("zce", ext_zce, false),
1388 MULTI_EXT_CFG_BOOL("zcf", ext_zcf, false),
1389 MULTI_EXT_CFG_BOOL("zcmp", ext_zcmp, false),
1390 MULTI_EXT_CFG_BOOL("zcmt", ext_zcmt, false),
1391 MULTI_EXT_CFG_BOOL("zicond", ext_zicond, false),
6672e29d 1392
ea61ef70
MC		 1393 /* Vector cryptography extensions */
1394 MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false),
1395 MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false),
1396 MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false),
1397 MULTI_EXT_CFG_BOOL("zvkg", ext_zvkg, false),
1398 MULTI_EXT_CFG_BOOL("zvkned", ext_zvkned, false),
1399 MULTI_EXT_CFG_BOOL("zvknha", ext_zvknha, false),
1400 MULTI_EXT_CFG_BOOL("zvknhb", ext_zvknhb, false),
1401 MULTI_EXT_CFG_BOOL("zvksed", ext_zvksed, false),
1402 MULTI_EXT_CFG_BOOL("zvksh", ext_zvksh, false),
1403 MULTI_EXT_CFG_BOOL("zvkt", ext_zvkt, false),
1404 MULTI_EXT_CFG_BOOL("zvkn", ext_zvkn, false),
1405 MULTI_EXT_CFG_BOOL("zvknc", ext_zvknc, false),
1406 MULTI_EXT_CFG_BOOL("zvkng", ext_zvkng, false),
1407 MULTI_EXT_CFG_BOOL("zvks", ext_zvks, false),
1408 MULTI_EXT_CFG_BOOL("zvksc", ext_zvksc, false),
1409 MULTI_EXT_CFG_BOOL("zvksg", ext_zvksg, false),
1410
82822b5d
DHB		 1411 DEFINE_PROP_END_OF_LIST(),
1412};
1413
32fa1776 1414const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
549cbf78
DHB		 1415 MULTI_EXT_CFG_BOOL("xtheadba", ext_xtheadba, false),
1416 MULTI_EXT_CFG_BOOL("xtheadbb", ext_xtheadbb, false),
1417 MULTI_EXT_CFG_BOOL("xtheadbs", ext_xtheadbs, false),
1418 MULTI_EXT_CFG_BOOL("xtheadcmo", ext_xtheadcmo, false),
1419 MULTI_EXT_CFG_BOOL("xtheadcondmov", ext_xtheadcondmov, false),
1420 MULTI_EXT_CFG_BOOL("xtheadfmemidx", ext_xtheadfmemidx, false),
1421 MULTI_EXT_CFG_BOOL("xtheadfmv", ext_xtheadfmv, false),
1422 MULTI_EXT_CFG_BOOL("xtheadmac", ext_xtheadmac, false),
1423 MULTI_EXT_CFG_BOOL("xtheadmemidx", ext_xtheadmemidx, false),
1424 MULTI_EXT_CFG_BOOL("xtheadmempair", ext_xtheadmempair, false),
1425 MULTI_EXT_CFG_BOOL("xtheadsync", ext_xtheadsync, false),
1426 MULTI_EXT_CFG_BOOL("xventanacondops", ext_XVentanaCondOps, false),
0d429bd2 1427
b955fd1a
DHB		 1428 DEFINE_PROP_END_OF_LIST(),
1429};
d364c0ab 1430
b955fd1a 1431/* These are experimental so mark with 'x-' */
32fa1776 1432const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
549cbf78
DHB		 1433 MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false),
1434 MULTI_EXT_CFG_BOOL("x-ssaia", ext_ssaia, false),
5da9514e 1435
549cbf78
DHB		 1436 MULTI_EXT_CFG_BOOL("x-zvfh", ext_zvfh, false),
1437 MULTI_EXT_CFG_BOOL("x-zvfhmin", ext_zvfhmin, false),
058d9d30 1438
549cbf78
DHB		 1439 MULTI_EXT_CFG_BOOL("x-zfbfmin", ext_zfbfmin, false),
1440 MULTI_EXT_CFG_BOOL("x-zvfbfmin", ext_zvfbfmin, false),
1441 MULTI_EXT_CFG_BOOL("x-zvfbfwma", ext_zvfbfwma, false),
889caa44 1442
26b2bc58
AF		 1443 DEFINE_PROP_END_OF_LIST(),
1444};
1445
5fe2800b
DHB		 1446const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = {
1447 MULTI_EXT_CFG_BOOL("zic64b", zic64b, true),
1448
1449 DEFINE_PROP_END_OF_LIST(),
1450};
1451
8043effd
DHB		 1452/* Deprecated entries marked for future removal */
1453const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[] = {
12b12a14 1454 MULTI_EXT_CFG_BOOL("Zifencei", ext_zifencei, true),
960b389b 1455 MULTI_EXT_CFG_BOOL("Zicsr", ext_zicsr, true),
8043effd
DHB		 1456 MULTI_EXT_CFG_BOOL("Zihintntl", ext_zihintntl, true),
1457 MULTI_EXT_CFG_BOOL("Zihintpause", ext_zihintpause, true),
1458 MULTI_EXT_CFG_BOOL("Zawrs", ext_zawrs, true),
1459 MULTI_EXT_CFG_BOOL("Zfa", ext_zfa, true),
1460 MULTI_EXT_CFG_BOOL("Zfh", ext_zfh, false),
1461 MULTI_EXT_CFG_BOOL("Zfhmin", ext_zfhmin, false),
1462 MULTI_EXT_CFG_BOOL("Zve32f", ext_zve32f, false),
1463 MULTI_EXT_CFG_BOOL("Zve64f", ext_zve64f, false),
1464 MULTI_EXT_CFG_BOOL("Zve64d", ext_zve64d, false),
1465
1466 DEFINE_PROP_END_OF_LIST(),
1467};
1468
69b3849b
RB		 1469static void prop_pmu_num_set(Object *obj, Visitor *v, const char *name,
1470 void *opaque, Error **errp)
1471{
1472 RISCVCPU *cpu = RISCV_CPU(obj);
1473 uint8_t pmu_num;
1474
1475 visit_type_uint8(v, name, &pmu_num, errp);
1476
1477 if (pmu_num > (RV_MAX_MHPMCOUNTERS - 3)) {
1478 error_setg(errp, "Number of counters exceeds maximum available");
1479 return;
1480 }
1481
1482 if (pmu_num == 0) {
1483 cpu->cfg.pmu_mask = 0;
1484 } else {
1485 cpu->cfg.pmu_mask = MAKE_64BIT_MASK(3, pmu_num);
1486 }
1487
1488 warn_report("\"pmu-num\" property is deprecated; use \"pmu-mask\"");
1489}
1490
1491static void prop_pmu_num_get(Object *obj, Visitor *v, const char *name,
1492 void *opaque, Error **errp)
1493{
1494 RISCVCPU *cpu = RISCV_CPU(obj);
1495 uint8_t pmu_num = ctpop32(cpu->cfg.pmu_mask);
1496
1497 visit_type_uint8(v, name, &pmu_num, errp);
1498}
1499
1500const PropertyInfo prop_pmu_num = {
1501 .name = "pmu-num",
1502 .get = prop_pmu_num_get,
1503 .set = prop_pmu_num_set,
1504};
1505
32fa1776 1506Property riscv_cpu_options[] = {
69b3849b
RB		 1507 DEFINE_PROP_UINT32("pmu-mask", RISCVCPU, cfg.pmu_mask, MAKE_64BIT_MASK(3, 16)),
1508 {.name = "pmu-num", .info = &prop_pmu_num}, /* Deprecated */
8ea3fcef
DHB		 1509
1510 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
1511 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
1512
1513 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
1514 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
1515
1516 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
1517 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
1518
1519 DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64),
cc2bf69a 1520 DEFINE_PROP_UINT16("cbop_blocksize", RISCVCPU, cfg.cbop_blocksize, 64),
8ea3fcef 1521 DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64),
d09d085a
DHB		 1522
1523 DEFINE_PROP_END_OF_LIST(),
8ea3fcef 1524};
56f0e992 1525
26b2bc58
AF		 1526static Property riscv_cpu_properties[] = {
1527 DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
1528
277b210d
AF		 1529#ifndef CONFIG_USER_ONLY
1530 DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC),
1531#endif
a4a9a443
TO		 1532
1533 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false),
b8312675 1534
1535 DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false),
1ad3f9bd 1536 DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false),
54bd9b6e
DHB		 1537
1538 /*
1539 * write_misa() is marked as experimental for now so mark
1540 * it with -x and default to 'false'.
1541 */
1542 DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false),
c4e95030
AF		 1543 DEFINE_PROP_END_OF_LIST(),
1544};
1545
a6506838 1546static const gchar *riscv_gdb_arch_name(CPUState *cs)
edf64786
SP		 1547{
1548 RISCVCPU *cpu = RISCV_CPU(cs);
1549 CPURISCVState *env = &cpu->env;
1550
db23e5d9
RH		 1551 switch (riscv_cpu_mxl(env)) {
1552 case MXL_RV32:
a6506838 1553 return "riscv:rv32";
db23e5d9 1554 case MXL_RV64:
332dab68 1555 case MXL_RV128:
a6506838 1556 return "riscv:rv64";
db23e5d9
RH		 1557 default:
1558 g_assert_not_reached();
edf64786
SP		 1559 }
1560}
1561
b93777e1
BM		 1562static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
1563{
1564 RISCVCPU *cpu = RISCV_CPU(cs);
1565
1566 if (strcmp(xmlname, "riscv-csr.xml") == 0) {
1567 return cpu->dyn_csr_xml;
719d3561
HW		 1568 } else if (strcmp(xmlname, "riscv-vector.xml") == 0) {
1569 return cpu->dyn_vreg_xml;
b93777e1
BM		 1570 }
1571
1572 return NULL;
1573}
1574
8b80bd28 1575#ifndef CONFIG_USER_ONLY
f1bd6f8e
MC		 1576static int64_t riscv_get_arch_id(CPUState *cs)
1577{
1578 RISCVCPU *cpu = RISCV_CPU(cs);
1579
1580 return cpu->env.mhartid;
1581}
1582
8b80bd28
PMD		 1583#include "hw/core/sysemu-cpu-ops.h"
1584
1585static const struct SysemuCPUOps riscv_sysemu_ops = {
08928c6d 1586 .get_phys_page_debug = riscv_cpu_get_phys_page_debug,
715e3c1a
PMD		 1587 .write_elf64_note = riscv_cpu_write_elf64_note,
1588 .write_elf32_note = riscv_cpu_write_elf32_note,
feece4d0 1589 .legacy_vmsd = &vmstate_riscv_cpu,
8b80bd28
PMD		 1590};
1591#endif
1592
1e341500
DHB		 1593static void cpu_set_mvendorid(Object *obj, Visitor *v, const char *name,
1594 void *opaque, Error **errp)
1595{
1596 bool dynamic_cpu = riscv_cpu_is_dynamic(obj);
1597 RISCVCPU *cpu = RISCV_CPU(obj);
1598 uint32_t prev_val = cpu->cfg.mvendorid;
1599 uint32_t value;
1600
1601 if (!visit_type_uint32(v, name, &value, errp)) {
1602 return;
1603 }
1604
1605 if (!dynamic_cpu && prev_val != value) {
1606 error_setg(errp, "Unable to change %s mvendorid (0x%x)",
1607 object_get_typename(obj), prev_val);
1608 return;
1609 }
1610
1611 cpu->cfg.mvendorid = value;
1612}
1613
1614static void cpu_get_mvendorid(Object *obj, Visitor *v, const char *name,
1615 void *opaque, Error **errp)
1616{
8d326cb8 1617 uint32_t value = RISCV_CPU(obj)->cfg.mvendorid;
1e341500 1618
8d326cb8 1619 visit_type_uint32(v, name, &value, errp);
1e341500
DHB		 1620}
1621
a1863ad3
DHB		 1622static void cpu_set_mimpid(Object *obj, Visitor *v, const char *name,
1623 void *opaque, Error **errp)
1624{
1625 bool dynamic_cpu = riscv_cpu_is_dynamic(obj);
1626 RISCVCPU *cpu = RISCV_CPU(obj);
1627 uint64_t prev_val = cpu->cfg.mimpid;
1628 uint64_t value;
1629
1630 if (!visit_type_uint64(v, name, &value, errp)) {
1631 return;
1632 }
1633
1634 if (!dynamic_cpu && prev_val != value) {
1635 error_setg(errp, "Unable to change %s mimpid (0x%" PRIu64 ")",
1636 object_get_typename(obj), prev_val);
1637 return;
1638 }
1639
1640 cpu->cfg.mimpid = value;
1641}
1642
1643static void cpu_get_mimpid(Object *obj, Visitor *v, const char *name,
1644 void *opaque, Error **errp)
1645{
8d326cb8 1646 uint64_t value = RISCV_CPU(obj)->cfg.mimpid;
a1863ad3 1647
8d326cb8 1648 visit_type_uint64(v, name, &value, errp);
a1863ad3
DHB		 1649}
1650
d6a427e2
DHB		 1651static void cpu_set_marchid(Object *obj, Visitor *v, const char *name,
1652 void *opaque, Error **errp)
1653{
1654 bool dynamic_cpu = riscv_cpu_is_dynamic(obj);
1655 RISCVCPU *cpu = RISCV_CPU(obj);
1656 uint64_t prev_val = cpu->cfg.marchid;
1657 uint64_t value, invalid_val;
1658 uint32_t mxlen = 0;
1659
1660 if (!visit_type_uint64(v, name, &value, errp)) {
1661 return;
1662 }
1663
1664 if (!dynamic_cpu && prev_val != value) {
1665 error_setg(errp, "Unable to change %s marchid (0x%" PRIu64 ")",
1666 object_get_typename(obj), prev_val);
1667 return;
1668 }
1669
1670 switch (riscv_cpu_mxl(&cpu->env)) {
1671 case MXL_RV32:
1672 mxlen = 32;
1673 break;
1674 case MXL_RV64:
1675 case MXL_RV128:
1676 mxlen = 64;
1677 break;
1678 default:
1679 g_assert_not_reached();
1680 }
1681
1682 invalid_val = 1LL << (mxlen - 1);
1683
1684 if (value == invalid_val) {
1685 error_setg(errp, "Unable to set marchid with MSB (%u) bit set "
1686 "and the remaining bits zero", mxlen);
1687 return;
1688 }
1689
1690 cpu->cfg.marchid = value;
1691}
1692
1693static void cpu_get_marchid(Object *obj, Visitor *v, const char *name,
1694 void *opaque, Error **errp)
1695{
8d326cb8 1696 uint64_t value = RISCV_CPU(obj)->cfg.marchid;
d6a427e2 1697
8d326cb8 1698 visit_type_uint64(v, name, &value, errp);
d6a427e2
DHB		 1699}
1700
dc5bd18f
MC		 1701static void riscv_cpu_class_init(ObjectClass *c, void *data)
1702{
1703 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
1704 CPUClass *cc = CPU_CLASS(c);
1705 DeviceClass *dc = DEVICE_CLASS(c);
4fa485a7 1706 ResettableClass *rc = RESETTABLE_CLASS(c);
dc5bd18f 1707
41fbbba7
MZ		 1708 device_class_set_parent_realize(dc, riscv_cpu_realize,
1709 &mcc->parent_realize);
dc5bd18f 1710
4fa485a7
PM		 1711 resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL,
1712 &mcc->parent_phases);
dc5bd18f
MC		 1713
1714 cc->class_by_name = riscv_cpu_class_by_name;
1715 cc->has_work = riscv_cpu_has_work;
dc5bd18f
MC		 1716 cc->dump_state = riscv_cpu_dump_state;
1717 cc->set_pc = riscv_cpu_set_pc;
e4fdf9df 1718 cc->get_pc = riscv_cpu_get_pc;
dc5bd18f
MC		 1719 cc->gdb_read_register = riscv_cpu_gdb_read_register;
1720 cc->gdb_write_register = riscv_cpu_gdb_write_register;
5371f5cd 1721 cc->gdb_num_core_regs = 33;
dc5bd18f
MC		 1722 cc->gdb_stop_before_watchpoint = true;
1723 cc->disas_set_info = riscv_cpu_disas_set_info;
8a4ca3c1 1724#ifndef CONFIG_USER_ONLY
8b80bd28 1725 cc->sysemu_ops = &riscv_sysemu_ops;
f1bd6f8e 1726 cc->get_arch_id = riscv_get_arch_id;
dc5bd18f 1727#endif
edf64786 1728 cc->gdb_arch_name = riscv_gdb_arch_name;
b93777e1 1729 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
6a3d2e7c 1730
1e341500
DHB		 1731 object_class_property_add(c, "mvendorid", "uint32", cpu_get_mvendorid,
1732 cpu_set_mvendorid, NULL, NULL);
a1863ad3
DHB		 1733
1734 object_class_property_add(c, "mimpid", "uint64", cpu_get_mimpid,
1735 cpu_set_mimpid, NULL, NULL);
d6a427e2
DHB		 1736
1737 object_class_property_add(c, "marchid", "uint64", cpu_get_marchid,
1738 cpu_set_marchid, NULL, NULL);
1e341500 1739
4f67d30b 1740 device_class_set_props(dc, riscv_cpu_properties);
dc5bd18f
MC		 1741}
1742
246f8796
WL		 1743static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,
1744 int max_str_len)
a775398b 1745{
7935e2c4 1746 const RISCVIsaExtData *edata;
a775398b
AP		 1747 char *old = *isa_str;
1748 char *new = *isa_str;
a775398b 1749
7935e2c4
DHB		 1750 for (edata = isa_edata_arr; edata && edata->name; edata++) {
1751 if (isa_ext_is_enabled(cpu, edata->ext_enable_offset)) {
1752 new = g_strconcat(old, "_", edata->name, NULL);
a775398b
AP		 1753 g_free(old);
1754 old = new;
1755 }
1756 }
1757
1758 *isa_str = new;
1759}
1760
dc5bd18f
MC		 1761char *riscv_isa_string(RISCVCPU *cpu)
1762{
1763 int i;
0e2c3770 1764 const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts);
d1fd31f8
MC		 1765 char *isa_str = g_new(char, maxlen);
1766 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
0e2c3770
TO		 1767 for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) {
1768 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) {
1769 *p++ = qemu_tolower(riscv_single_letter_exts[i]);
dc5bd18f
MC		 1770 }
1771 }
d1fd31f8 1772 *p = '\0';
a4a9a443
TO		 1773 if (!cpu->cfg.short_isa_string) {
1774 riscv_isa_string_ext(cpu, &isa_str, maxlen);
1775 }
d1fd31f8 1776 return isa_str;
dc5bd18f
MC		 1777}
1778
eab15862
MC		 1779#define DEFINE_CPU(type_name, initfn) \
1780 { \
1781 .name = type_name, \
1782 .parent = TYPE_RISCV_CPU, \
1783 .instance_init = initfn \
1784 }
1785
9e1a30d3
DHB		 1786#define DEFINE_DYNAMIC_CPU(type_name, initfn) \
1787 { \
1788 .name = type_name, \
1789 .parent = TYPE_RISCV_DYNAMIC_CPU, \
1790 .instance_init = initfn \
1791 }
1792
ee557ad5
DHB		 1793#define DEFINE_VENDOR_CPU(type_name, initfn) \
1794 { \
1795 .name = type_name, \
1796 .parent = TYPE_RISCV_VENDOR_CPU, \
1797 .instance_init = initfn \
1798 }
1799
d379c748
DHB		 1800#define DEFINE_BARE_CPU(type_name, initfn) \
1801 { \
1802 .name = type_name, \
1803 .parent = TYPE_RISCV_BARE_CPU, \
1804 .instance_init = initfn \
1805 }
1806
eab15862
MC		 1807static const TypeInfo riscv_cpu_type_infos[] = {
1808 {
1809 .name = TYPE_RISCV_CPU,
1810 .parent = TYPE_CPU,
1811 .instance_size = sizeof(RISCVCPU),
f669c992 1812 .instance_align = __alignof(RISCVCPU),
eab15862 1813 .instance_init = riscv_cpu_init,
977bbb04 1814 .instance_post_init = riscv_cpu_post_init,
eab15862
MC		 1815 .abstract = true,
1816 .class_size = sizeof(RISCVCPUClass),
1817 .class_init = riscv_cpu_class_init,
1818 },
9e1a30d3
DHB		 1819 {
1820 .name = TYPE_RISCV_DYNAMIC_CPU,
1821 .parent = TYPE_RISCV_CPU,
1822 .abstract = true,
1823 },
ee557ad5
DHB		 1824 {
1825 .name = TYPE_RISCV_VENDOR_CPU,
1826 .parent = TYPE_RISCV_CPU,
1827 .abstract = true,
1828 },
d379c748
DHB		 1829 {
1830 .name = TYPE_RISCV_BARE_CPU,
1831 .parent = TYPE_RISCV_CPU,
1832 .abstract = true,
1833 },
9e1a30d3 1834 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
b97e5a6b 1835 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, riscv_max_cpu_init),
eab15862 1836#if defined(TARGET_RISCV32)
9e1a30d3 1837 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init),
ee557ad5
DHB		 1838 DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),
1839 DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init),
1840 DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init),
1841 DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init),
eab15862 1842#elif defined(TARGET_RISCV64)
9e1a30d3 1843 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init),
ee557ad5
DHB		 1844 DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
1845 DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
1846 DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init),
1847 DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init),
1848 DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init),
9e1a30d3 1849 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init),
d379c748 1850 DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, rv64i_bare_cpu_init),
eab15862
MC		 1851#endif
1852};
1853
1854DEFINE_TYPES(riscv_cpu_type_infos)
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