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dc5bd18f MC |
1 | /* |
2 | * QEMU RISC-V CPU | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
0442428a | 21 | #include "qemu/qemu-print.h" |
856dfd8a | 22 | #include "qemu/ctype.h" |
dc5bd18f MC |
23 | #include "qemu/log.h" |
24 | #include "cpu.h" | |
95bd8daa | 25 | #include "cpu_vendorid.h" |
14664483 | 26 | #include "pmu.h" |
f7697f0e | 27 | #include "internals.h" |
43888c2f | 28 | #include "time_helper.h" |
dc5bd18f MC |
29 | #include "exec/exec-all.h" |
30 | #include "qapi/error.h" | |
6f23aaeb | 31 | #include "qapi/visitor.h" |
b55d7d34 | 32 | #include "qemu/error-report.h" |
c4e95030 | 33 | #include "hw/qdev-properties.h" |
dc5bd18f | 34 | #include "migration/vmstate.h" |
135b03cb | 35 | #include "fpu/softfloat-helpers.h" |
ad40be27 YJ |
36 | #include "sysemu/kvm.h" |
37 | #include "kvm_riscv.h" | |
0489d5bd | 38 | #include "tcg/tcg.h" |
dc5bd18f MC |
39 | |
40 | /* RISC-V CPU definitions */ | |
41 | ||
9951ba94 FC |
42 | #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ |
43 | (QEMU_VERSION_MINOR << 8) | \ | |
44 | (QEMU_VERSION_MICRO)) | |
075eeda9 | 45 | #define RISCV_CPU_MIMPID RISCV_CPU_MARCHID |
9951ba94 | 46 | |
0e2c3770 | 47 | static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; |
dc5bd18f | 48 | |
a775398b AP |
49 | struct isa_ext_data { |
50 | const char *name; | |
9a1f054d AP |
51 | bool multi_letter; |
52 | int min_version; | |
53 | int ext_enable_offset; | |
a775398b AP |
54 | }; |
55 | ||
9a1f054d AP |
56 | #define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \ |
57 | {#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} | |
58 | ||
59 | /** | |
60 | * Here are the ordering rules of extension naming defined by RISC-V | |
61 | * specification : | |
62 | * 1. All extensions should be separated from other multi-letter extensions | |
63 | * by an underscore. | |
64 | * 2. The first letter following the 'Z' conventionally indicates the most | |
65 | * closely related alphabetical extension category, IMAFDQLCBKJTPVH. | |
66 | * If multiple 'Z' extensions are named, they should be ordered first | |
67 | * by category, then alphabetically within a category. | |
68 | * 3. Standard supervisor-level extensions (starts with 'S') should be | |
69 | * listed after standard unprivileged extensions. If multiple | |
70 | * supervisor-level extensions are listed, they should be ordered | |
71 | * alphabetically. | |
72 | * 4. Non-standard extensions (starts with 'X') must be listed after all | |
73 | * standard extensions. They must be separated from other multi-letter | |
74 | * extensions by an underscore. | |
75 | */ | |
76 | static const struct isa_ext_data isa_edata_arr[] = { | |
77 | ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h), | |
0e660142 | 78 | ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_10_0, ext_v), |
e05da09b | 79 | ISA_EXT_DATA_ENTRY(zicbom, true, PRIV_VERSION_1_12_0, ext_icbom), |
a939c500 | 80 | ISA_EXT_DATA_ENTRY(zicboz, true, PRIV_VERSION_1_12_0, ext_icboz), |
b8e1f32c | 81 | ISA_EXT_DATA_ENTRY(zicond, true, PRIV_VERSION_1_12_0, ext_zicond), |
9a1f054d AP |
82 | ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr), |
83 | ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei), | |
4696f0ab | 84 | ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause), |
260b594d | 85 | ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs), |
7ad2878c | 86 | ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_11_0, ext_zfh), |
9a1f054d AP |
87 | ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin), |
88 | ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx), | |
89 | ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx), | |
90 | ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba), | |
91 | ISA_EXT_DATA_ENTRY(zbb, true, PRIV_VERSION_1_12_0, ext_zbb), | |
92 | ISA_EXT_DATA_ENTRY(zbc, true, PRIV_VERSION_1_12_0, ext_zbc), | |
93 | ISA_EXT_DATA_ENTRY(zbkb, true, PRIV_VERSION_1_12_0, ext_zbkb), | |
94 | ISA_EXT_DATA_ENTRY(zbkc, true, PRIV_VERSION_1_12_0, ext_zbkc), | |
95 | ISA_EXT_DATA_ENTRY(zbkx, true, PRIV_VERSION_1_12_0, ext_zbkx), | |
96 | ISA_EXT_DATA_ENTRY(zbs, true, PRIV_VERSION_1_12_0, ext_zbs), | |
97 | ISA_EXT_DATA_ENTRY(zk, true, PRIV_VERSION_1_12_0, ext_zk), | |
98 | ISA_EXT_DATA_ENTRY(zkn, true, PRIV_VERSION_1_12_0, ext_zkn), | |
99 | ISA_EXT_DATA_ENTRY(zknd, true, PRIV_VERSION_1_12_0, ext_zknd), | |
100 | ISA_EXT_DATA_ENTRY(zkne, true, PRIV_VERSION_1_12_0, ext_zkne), | |
101 | ISA_EXT_DATA_ENTRY(zknh, true, PRIV_VERSION_1_12_0, ext_zknh), | |
102 | ISA_EXT_DATA_ENTRY(zkr, true, PRIV_VERSION_1_12_0, ext_zkr), | |
103 | ISA_EXT_DATA_ENTRY(zks, true, PRIV_VERSION_1_12_0, ext_zks), | |
104 | ISA_EXT_DATA_ENTRY(zksed, true, PRIV_VERSION_1_12_0, ext_zksed), | |
105 | ISA_EXT_DATA_ENTRY(zksh, true, PRIV_VERSION_1_12_0, ext_zksh), | |
106 | ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt), | |
107 | ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f), | |
108 | ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f), | |
058d9d30 WL |
109 | ISA_EXT_DATA_ENTRY(zve64d, true, PRIV_VERSION_1_12_0, ext_zve64d), |
110 | ISA_EXT_DATA_ENTRY(zvfh, true, PRIV_VERSION_1_12_0, ext_zvfh), | |
111 | ISA_EXT_DATA_ENTRY(zvfhmin, true, PRIV_VERSION_1_12_0, ext_zvfhmin), | |
9a1f054d AP |
112 | ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), |
113 | ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), | |
dc9acc9c AP |
114 | ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia), |
115 | ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia), | |
14664483 | 116 | ISA_EXT_DATA_ENTRY(sscofpmf, true, PRIV_VERSION_1_12_0, ext_sscofpmf), |
43888c2f | 117 | ISA_EXT_DATA_ENTRY(sstc, true, PRIV_VERSION_1_12_0, ext_sstc), |
62108f05 | 118 | ISA_EXT_DATA_ENTRY(svadu, true, PRIV_VERSION_1_12_0, ext_svadu), |
9a1f054d AP |
119 | ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), |
120 | ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), | |
121 | ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), | |
c9410a68 | 122 | ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba), |
426c0491 | 123 | ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb), |
fa134585 | 124 | ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs), |
49a7f3aa | 125 | ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), |
32909338 | 126 | ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov), |
d4d90115 | 127 | ISA_EXT_DATA_ENTRY(xtheadfmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadfmemidx), |
578086ba | 128 | ISA_EXT_DATA_ENTRY(xtheadfmv, true, PRIV_VERSION_1_11_0, ext_xtheadfmv), |
b8a5832b | 129 | ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac), |
45f9df86 | 130 | ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadmemidx), |
af99aa72 | 131 | ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xtheadmempair), |
134c3ffa | 132 | ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync), |
e0dea2f5 | 133 | ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), |
9a1f054d AP |
134 | }; |
135 | ||
136 | static bool isa_ext_is_enabled(RISCVCPU *cpu, | |
137 | const struct isa_ext_data *edata) | |
138 | { | |
139 | bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; | |
140 | ||
141 | return *ext_enabled; | |
142 | } | |
143 | ||
144 | static void isa_ext_update_enabled(RISCVCPU *cpu, | |
145 | const struct isa_ext_data *edata, bool en) | |
146 | { | |
147 | bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; | |
148 | ||
149 | *ext_enabled = en; | |
150 | } | |
151 | ||
dc5bd18f | 152 | const char * const riscv_int_regnames[] = { |
a9f37afa AP |
153 | "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", |
154 | "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", | |
155 | "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", | |
156 | "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", | |
157 | "x28/t3", "x29/t4", "x30/t5", "x31/t6" | |
dc5bd18f MC |
158 | }; |
159 | ||
2b547084 FP |
160 | const char * const riscv_int_regnamesh[] = { |
161 | "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", | |
162 | "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", | |
163 | "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", | |
164 | "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", | |
165 | "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", | |
166 | "x30h/t5h", "x31h/t6h" | |
167 | }; | |
168 | ||
dc5bd18f | 169 | const char * const riscv_fpr_regnames[] = { |
a9f37afa AP |
170 | "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", |
171 | "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", | |
172 | "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", | |
173 | "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", | |
174 | "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", | |
175 | "f30/ft10", "f31/ft11" | |
dc5bd18f MC |
176 | }; |
177 | ||
9a575d33 | 178 | static const char * const riscv_excp_names[] = { |
dc5bd18f MC |
179 | "misaligned_fetch", |
180 | "fault_fetch", | |
181 | "illegal_instruction", | |
182 | "breakpoint", | |
183 | "misaligned_load", | |
184 | "fault_load", | |
185 | "misaligned_store", | |
186 | "fault_store", | |
187 | "user_ecall", | |
188 | "supervisor_ecall", | |
189 | "hypervisor_ecall", | |
190 | "machine_ecall", | |
191 | "exec_page_fault", | |
192 | "load_page_fault", | |
193 | "reserved", | |
fd990e86 | 194 | "store_page_fault", |
ab67a1d0 AF |
195 | "reserved", |
196 | "reserved", | |
197 | "reserved", | |
198 | "reserved", | |
199 | "guest_exec_page_fault", | |
200 | "guest_load_page_fault", | |
201 | "reserved", | |
fd990e86 | 202 | "guest_store_page_fault", |
dc5bd18f MC |
203 | }; |
204 | ||
9a575d33 | 205 | static const char * const riscv_intr_names[] = { |
dc5bd18f MC |
206 | "u_software", |
207 | "s_software", | |
205377f8 | 208 | "vs_software", |
dc5bd18f MC |
209 | "m_software", |
210 | "u_timer", | |
211 | "s_timer", | |
205377f8 | 212 | "vs_timer", |
dc5bd18f MC |
213 | "m_timer", |
214 | "u_external", | |
6cfcf775 | 215 | "s_external", |
205377f8 | 216 | "vs_external", |
dc5bd18f | 217 | "m_external", |
426f0348 MC |
218 | "reserved", |
219 | "reserved", | |
220 | "reserved", | |
221 | "reserved" | |
dc5bd18f MC |
222 | }; |
223 | ||
c01756a7 | 224 | static void register_cpu_props(Object *obj); |
26b2bc58 | 225 | |
c51a3f5d YJ |
226 | const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) |
227 | { | |
228 | if (async) { | |
229 | return (cause < ARRAY_SIZE(riscv_intr_names)) ? | |
230 | riscv_intr_names[cause] : "(unknown)"; | |
231 | } else { | |
232 | return (cause < ARRAY_SIZE(riscv_excp_names)) ? | |
233 | riscv_excp_names[cause] : "(unknown)"; | |
234 | } | |
235 | } | |
236 | ||
e91a7227 | 237 | static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) |
dc5bd18f | 238 | { |
e91a7227 RH |
239 | env->misa_mxl_max = env->misa_mxl = mxl; |
240 | env->misa_ext_mask = env->misa_ext = ext; | |
dc5bd18f MC |
241 | } |
242 | ||
c9a73910 | 243 | static void set_priv_version(CPURISCVState *env, int priv_ver) |
dc5bd18f | 244 | { |
dc5bd18f MC |
245 | env->priv_ver = priv_ver; |
246 | } | |
247 | ||
32931383 LZ |
248 | static void set_vext_version(CPURISCVState *env, int vext_ver) |
249 | { | |
250 | env->vext_ver = vext_ver; | |
251 | } | |
252 | ||
6f23aaeb AG |
253 | #ifndef CONFIG_USER_ONLY |
254 | static uint8_t satp_mode_from_str(const char *satp_mode_str) | |
255 | { | |
256 | if (!strncmp(satp_mode_str, "mbare", 5)) { | |
257 | return VM_1_10_MBARE; | |
258 | } | |
259 | ||
260 | if (!strncmp(satp_mode_str, "sv32", 4)) { | |
261 | return VM_1_10_SV32; | |
262 | } | |
263 | ||
264 | if (!strncmp(satp_mode_str, "sv39", 4)) { | |
265 | return VM_1_10_SV39; | |
266 | } | |
267 | ||
268 | if (!strncmp(satp_mode_str, "sv48", 4)) { | |
269 | return VM_1_10_SV48; | |
270 | } | |
271 | ||
272 | if (!strncmp(satp_mode_str, "sv57", 4)) { | |
273 | return VM_1_10_SV57; | |
274 | } | |
275 | ||
276 | if (!strncmp(satp_mode_str, "sv64", 4)) { | |
277 | return VM_1_10_SV64; | |
278 | } | |
279 | ||
280 | g_assert_not_reached(); | |
281 | } | |
282 | ||
283 | uint8_t satp_mode_max_from_map(uint32_t map) | |
284 | { | |
285 | /* map here has at least one bit set, so no problem with clz */ | |
286 | return 31 - __builtin_clz(map); | |
287 | } | |
288 | ||
289 | const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) | |
290 | { | |
291 | if (is_32_bit) { | |
292 | switch (satp_mode) { | |
293 | case VM_1_10_SV32: | |
294 | return "sv32"; | |
295 | case VM_1_10_MBARE: | |
296 | return "none"; | |
297 | } | |
298 | } else { | |
299 | switch (satp_mode) { | |
300 | case VM_1_10_SV64: | |
301 | return "sv64"; | |
302 | case VM_1_10_SV57: | |
303 | return "sv57"; | |
304 | case VM_1_10_SV48: | |
305 | return "sv48"; | |
306 | case VM_1_10_SV39: | |
307 | return "sv39"; | |
308 | case VM_1_10_MBARE: | |
309 | return "none"; | |
310 | } | |
311 | } | |
312 | ||
313 | g_assert_not_reached(); | |
314 | } | |
315 | ||
316 | /* Sets the satp mode to the max supported */ | |
317 | static void set_satp_mode_default_map(RISCVCPU *cpu) | |
318 | { | |
319 | bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; | |
320 | ||
321 | if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { | |
322 | cpu->cfg.satp_mode.map |= (1 << (rv32 ? VM_1_10_SV32 : VM_1_10_SV57)); | |
323 | } else { | |
324 | cpu->cfg.satp_mode.map |= (1 << VM_1_10_MBARE); | |
325 | } | |
326 | } | |
327 | #endif | |
328 | ||
dc5bd18f MC |
329 | static void riscv_any_cpu_init(Object *obj) |
330 | { | |
331 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
3820602f | 332 | #if defined(TARGET_RISCV32) |
e91a7227 | 333 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); |
3820602f | 334 | #elif defined(TARGET_RISCV64) |
e91a7227 | 335 | set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); |
3820602f | 336 | #endif |
7100fe6c | 337 | set_priv_version(env, PRIV_VERSION_1_12_0); |
c01756a7 | 338 | register_cpu_props(obj); |
dc5bd18f MC |
339 | } |
340 | ||
094b072c AF |
341 | #if defined(TARGET_RISCV64) |
342 | static void rv64_base_cpu_init(Object *obj) | |
8903bf6e AF |
343 | { |
344 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
b55d7d34 | 345 | /* We set this in the realise function */ |
e91a7227 | 346 | set_misa(env, MXL_RV64, 0); |
c01756a7 | 347 | register_cpu_props(obj); |
18800095 AP |
348 | /* Set latest version of privileged specification */ |
349 | set_priv_version(env, PRIV_VERSION_1_12_0); | |
8903bf6e AF |
350 | } |
351 | ||
114baaca | 352 | static void rv64_sifive_u_cpu_init(Object *obj) |
dc5bd18f MC |
353 | { |
354 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
e91a7227 | 355 | set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); |
c01756a7 | 356 | register_cpu_props(obj); |
c9a73910 | 357 | set_priv_version(env, PRIV_VERSION_1_10_0); |
dc5bd18f MC |
358 | } |
359 | ||
114baaca | 360 | static void rv64_sifive_e_cpu_init(Object *obj) |
36b80ad9 AF |
361 | { |
362 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
26b2bc58 AF |
363 | RISCVCPU *cpu = RISCV_CPU(obj); |
364 | ||
e91a7227 | 365 | set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); |
c01756a7 | 366 | register_cpu_props(obj); |
36b80ad9 | 367 | set_priv_version(env, PRIV_VERSION_1_10_0); |
26b2bc58 | 368 | cpu->cfg.mmu = false; |
36b80ad9 | 369 | } |
332dab68 | 370 | |
95bd8daa CM |
371 | static void rv64_thead_c906_cpu_init(Object *obj) |
372 | { | |
373 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
374 | RISCVCPU *cpu = RISCV_CPU(obj); | |
375 | ||
376 | set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); | |
377 | set_priv_version(env, PRIV_VERSION_1_11_0); | |
378 | ||
379 | cpu->cfg.ext_g = true; | |
380 | cpu->cfg.ext_c = true; | |
381 | cpu->cfg.ext_u = true; | |
382 | cpu->cfg.ext_s = true; | |
383 | cpu->cfg.ext_icsr = true; | |
384 | cpu->cfg.ext_zfh = true; | |
385 | cpu->cfg.mmu = true; | |
386 | cpu->cfg.ext_xtheadba = true; | |
387 | cpu->cfg.ext_xtheadbb = true; | |
388 | cpu->cfg.ext_xtheadbs = true; | |
389 | cpu->cfg.ext_xtheadcmo = true; | |
390 | cpu->cfg.ext_xtheadcondmov = true; | |
391 | cpu->cfg.ext_xtheadfmemidx = true; | |
392 | cpu->cfg.ext_xtheadmac = true; | |
393 | cpu->cfg.ext_xtheadmemidx = true; | |
394 | cpu->cfg.ext_xtheadmempair = true; | |
395 | cpu->cfg.ext_xtheadsync = true; | |
396 | ||
397 | cpu->cfg.mvendorid = THEAD_VENDOR_ID; | |
398 | } | |
399 | ||
332dab68 FP |
400 | static void rv128_base_cpu_init(Object *obj) |
401 | { | |
402 | if (qemu_tcg_mttcg_enabled()) { | |
403 | /* Missing 128-bit aligned atomics */ | |
404 | error_report("128-bit RISC-V currently does not work with Multi " | |
405 | "Threaded TCG. Please use: -accel tcg,thread=single"); | |
406 | exit(EXIT_FAILURE); | |
407 | } | |
408 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
409 | /* We set this in the realise function */ | |
410 | set_misa(env, MXL_RV128, 0); | |
c01756a7 | 411 | register_cpu_props(obj); |
18800095 AP |
412 | /* Set latest version of privileged specification */ |
413 | set_priv_version(env, PRIV_VERSION_1_12_0); | |
332dab68 | 414 | } |
114baaca | 415 | #else |
094b072c AF |
416 | static void rv32_base_cpu_init(Object *obj) |
417 | { | |
418 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
419 | /* We set this in the realise function */ | |
e91a7227 | 420 | set_misa(env, MXL_RV32, 0); |
c01756a7 | 421 | register_cpu_props(obj); |
18800095 AP |
422 | /* Set latest version of privileged specification */ |
423 | set_priv_version(env, PRIV_VERSION_1_12_0); | |
094b072c AF |
424 | } |
425 | ||
114baaca AF |
426 | static void rv32_sifive_u_cpu_init(Object *obj) |
427 | { | |
428 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
e91a7227 | 429 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); |
c01756a7 | 430 | register_cpu_props(obj); |
114baaca AF |
431 | set_priv_version(env, PRIV_VERSION_1_10_0); |
432 | } | |
36b80ad9 | 433 | |
114baaca AF |
434 | static void rv32_sifive_e_cpu_init(Object *obj) |
435 | { | |
436 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
26b2bc58 AF |
437 | RISCVCPU *cpu = RISCV_CPU(obj); |
438 | ||
e91a7227 | 439 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); |
c01756a7 | 440 | register_cpu_props(obj); |
114baaca | 441 | set_priv_version(env, PRIV_VERSION_1_10_0); |
26b2bc58 | 442 | cpu->cfg.mmu = false; |
114baaca | 443 | } |
d8e72bd1 | 444 | |
e8905c6c | 445 | static void rv32_ibex_cpu_init(Object *obj) |
dc5bd18f MC |
446 | { |
447 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
26b2bc58 AF |
448 | RISCVCPU *cpu = RISCV_CPU(obj); |
449 | ||
e91a7227 | 450 | set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); |
c01756a7 | 451 | register_cpu_props(obj); |
be2265c7 | 452 | set_priv_version(env, PRIV_VERSION_1_11_0); |
26b2bc58 AF |
453 | cpu->cfg.mmu = false; |
454 | cpu->cfg.epmp = true; | |
dc5bd18f MC |
455 | } |
456 | ||
2fdd2c09 | 457 | static void rv32_imafcu_nommu_cpu_init(Object *obj) |
d784733b CW |
458 | { |
459 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
26b2bc58 AF |
460 | RISCVCPU *cpu = RISCV_CPU(obj); |
461 | ||
e91a7227 | 462 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); |
c01756a7 | 463 | register_cpu_props(obj); |
d784733b | 464 | set_priv_version(env, PRIV_VERSION_1_10_0); |
26b2bc58 | 465 | cpu->cfg.mmu = false; |
d784733b | 466 | } |
eab15862 | 467 | #endif |
dc5bd18f | 468 | |
10f1ca27 YJ |
469 | #if defined(CONFIG_KVM) |
470 | static void riscv_host_cpu_init(Object *obj) | |
471 | { | |
472 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
473 | #if defined(TARGET_RISCV32) | |
474 | set_misa(env, MXL_RV32, 0); | |
475 | #elif defined(TARGET_RISCV64) | |
476 | set_misa(env, MXL_RV64, 0); | |
477 | #endif | |
c01756a7 | 478 | register_cpu_props(obj); |
10f1ca27 YJ |
479 | } |
480 | #endif | |
481 | ||
dc5bd18f MC |
482 | static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) |
483 | { | |
484 | ObjectClass *oc; | |
485 | char *typename; | |
486 | char **cpuname; | |
487 | ||
488 | cpuname = g_strsplit(cpu_model, ",", 1); | |
489 | typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); | |
490 | oc = object_class_by_name(typename); | |
491 | g_strfreev(cpuname); | |
492 | g_free(typename); | |
493 | if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || | |
494 | object_class_is_abstract(oc)) { | |
495 | return NULL; | |
496 | } | |
497 | return oc; | |
498 | } | |
499 | ||
90c84c56 | 500 | static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) |
dc5bd18f MC |
501 | { |
502 | RISCVCPU *cpu = RISCV_CPU(cs); | |
503 | CPURISCVState *env = &cpu->env; | |
504 | int i; | |
505 | ||
df30e652 AF |
506 | #if !defined(CONFIG_USER_ONLY) |
507 | if (riscv_has_ext(env, RVH)) { | |
508 | qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); | |
509 | } | |
510 | #endif | |
90c84c56 | 511 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); |
dc5bd18f | 512 | #ifndef CONFIG_USER_ONLY |
665b90d8 RH |
513 | { |
514 | static const int dump_csrs[] = { | |
515 | CSR_MHARTID, | |
516 | CSR_MSTATUS, | |
517 | CSR_MSTATUSH, | |
bc7dca13 BM |
518 | /* |
519 | * CSR_SSTATUS is intentionally omitted here as its value | |
520 | * can be figured out by looking at CSR_MSTATUS | |
521 | */ | |
665b90d8 RH |
522 | CSR_HSTATUS, |
523 | CSR_VSSTATUS, | |
524 | CSR_MIP, | |
525 | CSR_MIE, | |
526 | CSR_MIDELEG, | |
527 | CSR_HIDELEG, | |
528 | CSR_MEDELEG, | |
529 | CSR_HEDELEG, | |
530 | CSR_MTVEC, | |
531 | CSR_STVEC, | |
532 | CSR_VSTVEC, | |
533 | CSR_MEPC, | |
534 | CSR_SEPC, | |
535 | CSR_VSEPC, | |
536 | CSR_MCAUSE, | |
537 | CSR_SCAUSE, | |
538 | CSR_VSCAUSE, | |
539 | CSR_MTVAL, | |
540 | CSR_STVAL, | |
541 | CSR_HTVAL, | |
542 | CSR_MTVAL2, | |
543 | CSR_MSCRATCH, | |
544 | CSR_SSCRATCH, | |
545 | CSR_SATP, | |
bd5594ca AB |
546 | CSR_MMTE, |
547 | CSR_UPMBASE, | |
548 | CSR_UPMMASK, | |
549 | CSR_SPMBASE, | |
550 | CSR_SPMMASK, | |
551 | CSR_MPMBASE, | |
552 | CSR_MPMMASK, | |
665b90d8 RH |
553 | }; |
554 | ||
555 | for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { | |
556 | int csrno = dump_csrs[i]; | |
557 | target_ulong val = 0; | |
558 | RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); | |
559 | ||
560 | /* | |
561 | * Rely on the smode, hmode, etc, predicates within csr.c | |
562 | * to do the filtering of the registers that are present. | |
563 | */ | |
564 | if (res == RISCV_EXCP_NONE) { | |
565 | qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", | |
566 | csr_ops[csrno].name, val); | |
567 | } | |
568 | } | |
df30e652 | 569 | } |
dc5bd18f MC |
570 | #endif |
571 | ||
572 | for (i = 0; i < 32; i++) { | |
e573a7f3 | 573 | qemu_fprintf(f, " %-8s " TARGET_FMT_lx, |
90c84c56 | 574 | riscv_int_regnames[i], env->gpr[i]); |
dc5bd18f | 575 | if ((i & 3) == 3) { |
90c84c56 | 576 | qemu_fprintf(f, "\n"); |
dc5bd18f MC |
577 | } |
578 | } | |
86ea1880 RH |
579 | if (flags & CPU_DUMP_FPU) { |
580 | for (i = 0; i < 32; i++) { | |
e573a7f3 | 581 | qemu_fprintf(f, " %-8s %016" PRIx64, |
90c84c56 | 582 | riscv_fpr_regnames[i], env->fpr[i]); |
86ea1880 | 583 | if ((i & 3) == 3) { |
90c84c56 | 584 | qemu_fprintf(f, "\n"); |
86ea1880 | 585 | } |
dc5bd18f MC |
586 | } |
587 | } | |
588 | } | |
589 | ||
590 | static void riscv_cpu_set_pc(CPUState *cs, vaddr value) | |
591 | { | |
592 | RISCVCPU *cpu = RISCV_CPU(cs); | |
593 | CPURISCVState *env = &cpu->env; | |
bf9e776e LZ |
594 | |
595 | if (env->xl == MXL_RV32) { | |
596 | env->pc = (int32_t)value; | |
597 | } else { | |
598 | env->pc = value; | |
599 | } | |
dc5bd18f MC |
600 | } |
601 | ||
e4fdf9df RH |
602 | static vaddr riscv_cpu_get_pc(CPUState *cs) |
603 | { | |
604 | RISCVCPU *cpu = RISCV_CPU(cs); | |
605 | CPURISCVState *env = &cpu->env; | |
606 | ||
607 | /* Match cpu_get_tb_cpu_state. */ | |
608 | if (env->xl == MXL_RV32) { | |
609 | return env->pc & UINT32_MAX; | |
610 | } | |
611 | return env->pc; | |
612 | } | |
613 | ||
04a37d4c RH |
614 | static void riscv_cpu_synchronize_from_tb(CPUState *cs, |
615 | const TranslationBlock *tb) | |
dc5bd18f MC |
616 | { |
617 | RISCVCPU *cpu = RISCV_CPU(cs); | |
618 | CPURISCVState *env = &cpu->env; | |
bf9e776e LZ |
619 | RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); |
620 | ||
0489d5bd AJ |
621 | tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); |
622 | ||
bf9e776e | 623 | if (xl == MXL_RV32) { |
0489d5bd | 624 | env->pc = (int32_t) tb->pc; |
bf9e776e | 625 | } else { |
0489d5bd | 626 | env->pc = tb->pc; |
bf9e776e | 627 | } |
dc5bd18f MC |
628 | } |
629 | ||
630 | static bool riscv_cpu_has_work(CPUState *cs) | |
631 | { | |
632 | #ifndef CONFIG_USER_ONLY | |
633 | RISCVCPU *cpu = RISCV_CPU(cs); | |
634 | CPURISCVState *env = &cpu->env; | |
635 | /* | |
636 | * Definition of the WFI instruction requires it to ignore the privilege | |
637 | * mode and delegation registers, but respect individual enables | |
638 | */ | |
8f42415f | 639 | return riscv_cpu_all_pending(env) != 0; |
dc5bd18f MC |
640 | #else |
641 | return true; | |
642 | #endif | |
643 | } | |
644 | ||
ad1e84f5 RH |
645 | static void riscv_restore_state_to_opc(CPUState *cs, |
646 | const TranslationBlock *tb, | |
647 | const uint64_t *data) | |
dc5bd18f | 648 | { |
ad1e84f5 RH |
649 | RISCVCPU *cpu = RISCV_CPU(cs); |
650 | CPURISCVState *env = &cpu->env; | |
bf9e776e | 651 | RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); |
ad1e84f5 | 652 | |
bf9e776e LZ |
653 | if (xl == MXL_RV32) { |
654 | env->pc = (int32_t)data[0]; | |
655 | } else { | |
656 | env->pc = data[0]; | |
657 | } | |
62cf0245 | 658 | env->bins = data[1]; |
dc5bd18f MC |
659 | } |
660 | ||
4fa485a7 | 661 | static void riscv_cpu_reset_hold(Object *obj) |
dc5bd18f | 662 | { |
43dc93af AP |
663 | #ifndef CONFIG_USER_ONLY |
664 | uint8_t iprio; | |
665 | int i, irq, rdzero; | |
666 | #endif | |
4fa485a7 | 667 | CPUState *cs = CPU(obj); |
dc5bd18f MC |
668 | RISCVCPU *cpu = RISCV_CPU(cs); |
669 | RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); | |
670 | CPURISCVState *env = &cpu->env; | |
671 | ||
4fa485a7 PM |
672 | if (mcc->parent_phases.hold) { |
673 | mcc->parent_phases.hold(obj); | |
674 | } | |
dc5bd18f | 675 | #ifndef CONFIG_USER_ONLY |
e91a7227 | 676 | env->misa_mxl = env->misa_mxl_max; |
dc5bd18f MC |
677 | env->priv = PRV_M; |
678 | env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); | |
92371bd9 RH |
679 | if (env->misa_mxl > MXL_RV32) { |
680 | /* | |
681 | * The reset status of SXL/UXL is undefined, but mstatus is WARL | |
682 | * and we must ensure that the value after init is valid for read. | |
683 | */ | |
684 | env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); | |
685 | env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); | |
5a2ae235 LZ |
686 | if (riscv_has_ext(env, RVH)) { |
687 | env->vsstatus = set_field(env->vsstatus, | |
688 | MSTATUS64_SXL, env->misa_mxl); | |
689 | env->vsstatus = set_field(env->vsstatus, | |
690 | MSTATUS64_UXL, env->misa_mxl); | |
691 | env->mstatus_hs = set_field(env->mstatus_hs, | |
692 | MSTATUS64_SXL, env->misa_mxl); | |
693 | env->mstatus_hs = set_field(env->mstatus_hs, | |
694 | MSTATUS64_UXL, env->misa_mxl); | |
695 | } | |
92371bd9 | 696 | } |
dc5bd18f | 697 | env->mcause = 0; |
881df35d | 698 | env->miclaim = MIP_SGEIP; |
dc5bd18f | 699 | env->pc = env->resetvec; |
62cf0245 | 700 | env->bins = 0; |
ec352d0c | 701 | env->two_stage_lookup = false; |
43dc93af | 702 | |
0af3f115 WL |
703 | env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) | |
704 | (cpu->cfg.ext_svadu ? MENVCFG_HADE : 0); | |
705 | env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) | | |
706 | (cpu->cfg.ext_svadu ? HENVCFG_HADE : 0); | |
7a6613da | 707 | |
43dc93af AP |
708 | /* Initialized default priorities of local interrupts. */ |
709 | for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { | |
710 | iprio = riscv_cpu_default_priority(i); | |
711 | env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio; | |
712 | env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio; | |
713 | env->hviprio[i] = 0; | |
714 | } | |
715 | i = 0; | |
716 | while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) { | |
717 | if (!rdzero) { | |
718 | env->hviprio[irq] = env->miprio[irq]; | |
719 | } | |
720 | i++; | |
721 | } | |
4bbe8033 AB |
722 | /* mmte is supposed to have pm.current hardwired to 1 */ |
723 | env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); | |
dc5bd18f | 724 | #endif |
440544e1 | 725 | env->xl = riscv_cpu_mxl(env); |
40bfa5f6 | 726 | riscv_cpu_update_mask(env); |
330d2ae3 | 727 | cs->exception_index = RISCV_EXCP_NONE; |
c13b169f | 728 | env->load_res = -1; |
dc5bd18f | 729 | set_default_nan_mode(1, &env->fp_status); |
ad40be27 YJ |
730 | |
731 | #ifndef CONFIG_USER_ONLY | |
cdfb2905 | 732 | if (cpu->cfg.debug) { |
b6092544 BM |
733 | riscv_trigger_init(env); |
734 | } | |
735 | ||
ad40be27 YJ |
736 | if (kvm_enabled()) { |
737 | kvm_riscv_reset_vcpu(cpu); | |
738 | } | |
739 | #endif | |
dc5bd18f MC |
740 | } |
741 | ||
742 | static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) | |
743 | { | |
5c5a47f1 | 744 | RISCVCPU *cpu = RISCV_CPU(s); |
db23e5d9 RH |
745 | |
746 | switch (riscv_cpu_mxl(&cpu->env)) { | |
747 | case MXL_RV32: | |
5c5a47f1 | 748 | info->print_insn = print_insn_riscv32; |
db23e5d9 RH |
749 | break; |
750 | case MXL_RV64: | |
5c5a47f1 | 751 | info->print_insn = print_insn_riscv64; |
db23e5d9 | 752 | break; |
332dab68 FP |
753 | case MXL_RV128: |
754 | info->print_insn = print_insn_riscv128; | |
755 | break; | |
db23e5d9 RH |
756 | default: |
757 | g_assert_not_reached(); | |
5c5a47f1 | 758 | } |
dc5bd18f MC |
759 | } |
760 | ||
5ab10952 DHB |
761 | /* |
762 | * Check consistency between chosen extensions while setting | |
763 | * cpu->cfg accordingly, doing a set_misa() in the end. | |
764 | */ | |
765 | static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) | |
766 | { | |
767 | CPURISCVState *env = &cpu->env; | |
768 | uint32_t ext = 0; | |
769 | ||
770 | /* Do some ISA extension error checking */ | |
771 | if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && | |
772 | cpu->cfg.ext_a && cpu->cfg.ext_f && | |
773 | cpu->cfg.ext_d && | |
774 | cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { | |
775 | warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); | |
776 | cpu->cfg.ext_i = true; | |
777 | cpu->cfg.ext_m = true; | |
778 | cpu->cfg.ext_a = true; | |
779 | cpu->cfg.ext_f = true; | |
780 | cpu->cfg.ext_d = true; | |
781 | cpu->cfg.ext_icsr = true; | |
782 | cpu->cfg.ext_ifencei = true; | |
783 | } | |
784 | ||
785 | if (cpu->cfg.ext_i && cpu->cfg.ext_e) { | |
786 | error_setg(errp, | |
787 | "I and E extensions are incompatible"); | |
788 | return; | |
789 | } | |
790 | ||
791 | if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { | |
792 | error_setg(errp, | |
793 | "Either I or E extension must be set"); | |
794 | return; | |
795 | } | |
796 | ||
797 | if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { | |
798 | error_setg(errp, | |
799 | "Setting S extension without U extension is illegal"); | |
800 | return; | |
801 | } | |
802 | ||
803 | if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { | |
804 | error_setg(errp, | |
805 | "H depends on an I base integer ISA with 32 x registers"); | |
806 | return; | |
807 | } | |
808 | ||
809 | if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { | |
810 | error_setg(errp, "H extension implicitly requires S-mode"); | |
811 | return; | |
812 | } | |
813 | ||
814 | if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { | |
815 | error_setg(errp, "F extension requires Zicsr"); | |
816 | return; | |
817 | } | |
818 | ||
819 | if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { | |
820 | error_setg(errp, "Zawrs extension requires A extension"); | |
821 | return; | |
822 | } | |
823 | ||
1d2cb5a8 WL |
824 | if (cpu->cfg.ext_zfh) { |
825 | cpu->cfg.ext_zfhmin = true; | |
826 | } | |
827 | ||
828 | if (cpu->cfg.ext_zfhmin && !cpu->cfg.ext_f) { | |
5ab10952 DHB |
829 | error_setg(errp, "Zfh/Zfhmin extensions require F extension"); |
830 | return; | |
831 | } | |
832 | ||
833 | if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { | |
834 | error_setg(errp, "D extension requires F extension"); | |
835 | return; | |
836 | } | |
837 | ||
e7f0a803 WL |
838 | /* The V vector extension depends on the Zve64d extension */ |
839 | if (cpu->cfg.ext_v) { | |
840 | cpu->cfg.ext_zve64d = true; | |
841 | } | |
842 | ||
843 | /* The Zve64d extension depends on the Zve64f extension */ | |
844 | if (cpu->cfg.ext_zve64d) { | |
845 | cpu->cfg.ext_zve64f = true; | |
846 | } | |
847 | ||
848 | /* The Zve64f extension depends on the Zve32f extension */ | |
849 | if (cpu->cfg.ext_zve64f) { | |
850 | cpu->cfg.ext_zve32f = true; | |
851 | } | |
852 | ||
853 | if (cpu->cfg.ext_zve64d && !cpu->cfg.ext_d) { | |
854 | error_setg(errp, "Zve64d/V extensions require D extension"); | |
5ab10952 DHB |
855 | return; |
856 | } | |
857 | ||
e7f0a803 | 858 | if (cpu->cfg.ext_zve32f && !cpu->cfg.ext_f) { |
5ab10952 DHB |
859 | error_setg(errp, "Zve32f/Zve64f extensions require F extension"); |
860 | return; | |
861 | } | |
862 | ||
2e60f9ec WL |
863 | if (cpu->cfg.ext_zvfh) { |
864 | cpu->cfg.ext_zvfhmin = true; | |
865 | } | |
866 | ||
867 | if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { | |
868 | error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension"); | |
869 | return; | |
870 | } | |
871 | ||
872 | if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { | |
873 | error_setg(errp, "Zvfh extensions requires Zfhmin extension"); | |
874 | return; | |
875 | } | |
876 | ||
5ab10952 | 877 | /* Set the ISA extensions, checks should have happened above */ |
a0d805f0 WL |
878 | if (cpu->cfg.ext_zhinx) { |
879 | cpu->cfg.ext_zhinxmin = true; | |
880 | } | |
881 | ||
882 | if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) { | |
5ab10952 DHB |
883 | cpu->cfg.ext_zfinx = true; |
884 | } | |
885 | ||
886 | if (cpu->cfg.ext_zfinx) { | |
887 | if (!cpu->cfg.ext_icsr) { | |
888 | error_setg(errp, "Zfinx extension requires Zicsr"); | |
889 | return; | |
890 | } | |
891 | if (cpu->cfg.ext_f) { | |
892 | error_setg(errp, | |
51f33081 | 893 | "Zfinx cannot be supported together with F extension"); |
5ab10952 DHB |
894 | return; |
895 | } | |
896 | } | |
897 | ||
898 | if (cpu->cfg.ext_zk) { | |
899 | cpu->cfg.ext_zkn = true; | |
900 | cpu->cfg.ext_zkr = true; | |
901 | cpu->cfg.ext_zkt = true; | |
902 | } | |
903 | ||
904 | if (cpu->cfg.ext_zkn) { | |
905 | cpu->cfg.ext_zbkb = true; | |
906 | cpu->cfg.ext_zbkc = true; | |
907 | cpu->cfg.ext_zbkx = true; | |
908 | cpu->cfg.ext_zkne = true; | |
909 | cpu->cfg.ext_zknd = true; | |
910 | cpu->cfg.ext_zknh = true; | |
911 | } | |
912 | ||
913 | if (cpu->cfg.ext_zks) { | |
914 | cpu->cfg.ext_zbkb = true; | |
915 | cpu->cfg.ext_zbkc = true; | |
916 | cpu->cfg.ext_zbkx = true; | |
917 | cpu->cfg.ext_zksed = true; | |
918 | cpu->cfg.ext_zksh = true; | |
919 | } | |
920 | ||
921 | if (cpu->cfg.ext_i) { | |
922 | ext |= RVI; | |
923 | } | |
924 | if (cpu->cfg.ext_e) { | |
925 | ext |= RVE; | |
926 | } | |
927 | if (cpu->cfg.ext_m) { | |
928 | ext |= RVM; | |
929 | } | |
930 | if (cpu->cfg.ext_a) { | |
931 | ext |= RVA; | |
932 | } | |
933 | if (cpu->cfg.ext_f) { | |
934 | ext |= RVF; | |
935 | } | |
936 | if (cpu->cfg.ext_d) { | |
937 | ext |= RVD; | |
938 | } | |
939 | if (cpu->cfg.ext_c) { | |
940 | ext |= RVC; | |
941 | } | |
942 | if (cpu->cfg.ext_s) { | |
943 | ext |= RVS; | |
944 | } | |
945 | if (cpu->cfg.ext_u) { | |
946 | ext |= RVU; | |
947 | } | |
948 | if (cpu->cfg.ext_h) { | |
949 | ext |= RVH; | |
950 | } | |
951 | if (cpu->cfg.ext_v) { | |
952 | int vext_version = VEXT_VERSION_1_00_0; | |
953 | ext |= RVV; | |
954 | if (!is_power_of_2(cpu->cfg.vlen)) { | |
955 | error_setg(errp, | |
51f33081 | 956 | "Vector extension VLEN must be power of 2"); |
5ab10952 DHB |
957 | return; |
958 | } | |
959 | if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { | |
960 | error_setg(errp, | |
51f33081 WL |
961 | "Vector extension implementation only supports VLEN " |
962 | "in the range [128, %d]", RV_VLEN_MAX); | |
5ab10952 DHB |
963 | return; |
964 | } | |
965 | if (!is_power_of_2(cpu->cfg.elen)) { | |
966 | error_setg(errp, | |
51f33081 | 967 | "Vector extension ELEN must be power of 2"); |
5ab10952 DHB |
968 | return; |
969 | } | |
51f33081 | 970 | if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { |
5ab10952 | 971 | error_setg(errp, |
51f33081 WL |
972 | "Vector extension implementation only supports ELEN " |
973 | "in the range [8, 64]"); | |
5ab10952 DHB |
974 | return; |
975 | } | |
51f33081 WL |
976 | if (cpu->cfg.vext_spec) { |
977 | if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { | |
978 | vext_version = VEXT_VERSION_1_00_0; | |
979 | } else { | |
980 | error_setg(errp, | |
981 | "Unsupported vector spec version '%s'", | |
982 | cpu->cfg.vext_spec); | |
983 | return; | |
984 | } | |
985 | } else { | |
986 | qemu_log("vector version is not specified, " | |
987 | "use the default value v1.0\n"); | |
988 | } | |
989 | set_vext_version(env, vext_version); | |
5ab10952 DHB |
990 | } |
991 | if (cpu->cfg.ext_j) { | |
992 | ext |= RVJ; | |
993 | } | |
994 | ||
995 | set_misa(env, env->misa_mxl, ext); | |
996 | } | |
997 | ||
6f23aaeb AG |
998 | #ifndef CONFIG_USER_ONLY |
999 | static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) | |
1000 | { | |
1001 | bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; | |
1002 | const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; | |
1003 | uint8_t satp_mode_max; | |
1004 | ||
1005 | if (cpu->cfg.satp_mode.map == 0) { | |
1006 | if (cpu->cfg.satp_mode.init == 0) { | |
1007 | /* If unset by the user, we fallback to the default satp mode. */ | |
1008 | set_satp_mode_default_map(cpu); | |
1009 | } else { | |
1010 | /* | |
1011 | * Find the lowest level that was disabled and then enable the | |
1012 | * first valid level below which can be found in | |
1013 | * valid_vm_1_10_32/64. | |
1014 | */ | |
1015 | for (int i = 1; i < 16; ++i) { | |
1016 | if ((cpu->cfg.satp_mode.init & (1 << i)) && valid_vm[i]) { | |
1017 | for (int j = i - 1; j >= 0; --j) { | |
1018 | if (valid_vm[j]) { | |
1019 | cpu->cfg.satp_mode.map |= (1 << j); | |
1020 | break; | |
1021 | } | |
1022 | } | |
1023 | break; | |
1024 | } | |
1025 | } | |
1026 | } | |
1027 | } | |
1028 | ||
1029 | /* Make sure the configuration asked is supported by qemu */ | |
1030 | for (int i = 0; i < 16; ++i) { | |
1031 | if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { | |
1032 | error_setg(errp, "satp_mode %s is not valid", | |
1033 | satp_mode_str(i, rv32)); | |
1034 | return; | |
1035 | } | |
1036 | } | |
1037 | ||
1038 | /* | |
1039 | * Make sure the user did not ask for an invalid configuration as per | |
1040 | * the specification. | |
1041 | */ | |
1042 | satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); | |
1043 | ||
1044 | if (!rv32) { | |
1045 | for (int i = satp_mode_max - 1; i >= 0; --i) { | |
1046 | if (!(cpu->cfg.satp_mode.map & (1 << i)) && | |
1047 | (cpu->cfg.satp_mode.init & (1 << i)) && | |
1048 | valid_vm[i]) { | |
1049 | error_setg(errp, "cannot disable %s satp mode if %s " | |
1050 | "is enabled", satp_mode_str(i, false), | |
1051 | satp_mode_str(satp_mode_max, false)); | |
1052 | return; | |
1053 | } | |
1054 | } | |
1055 | } | |
1056 | ||
1057 | /* Finally expand the map so that all valid modes are set */ | |
1058 | for (int i = satp_mode_max - 1; i >= 0; --i) { | |
1059 | if (valid_vm[i]) { | |
1060 | cpu->cfg.satp_mode.map |= (1 << i); | |
1061 | } | |
1062 | } | |
1063 | } | |
1064 | #endif | |
1065 | ||
1066 | static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) | |
1067 | { | |
1068 | #ifndef CONFIG_USER_ONLY | |
1069 | Error *local_err = NULL; | |
1070 | ||
1071 | riscv_cpu_satp_mode_finalize(cpu, &local_err); | |
1072 | if (local_err != NULL) { | |
1073 | error_propagate(errp, local_err); | |
1074 | return; | |
1075 | } | |
1076 | #endif | |
1077 | } | |
1078 | ||
dc5bd18f MC |
1079 | static void riscv_cpu_realize(DeviceState *dev, Error **errp) |
1080 | { | |
1081 | CPUState *cs = CPU(dev); | |
c4e95030 AF |
1082 | RISCVCPU *cpu = RISCV_CPU(dev); |
1083 | CPURISCVState *env = &cpu->env; | |
dc5bd18f | 1084 | RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); |
1191be09 | 1085 | CPUClass *cc = CPU_CLASS(mcc); |
9a1f054d | 1086 | int i, priv_version = -1; |
dc5bd18f MC |
1087 | Error *local_err = NULL; |
1088 | ||
1089 | cpu_exec_realizefn(cs, &local_err); | |
1090 | if (local_err != NULL) { | |
1091 | error_propagate(errp, local_err); | |
1092 | return; | |
1093 | } | |
1094 | ||
c4e95030 | 1095 | if (cpu->cfg.priv_spec) { |
7100fe6c AP |
1096 | if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { |
1097 | priv_version = PRIV_VERSION_1_12_0; | |
1098 | } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { | |
e3147506 AF |
1099 | priv_version = PRIV_VERSION_1_11_0; |
1100 | } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { | |
c4e95030 | 1101 | priv_version = PRIV_VERSION_1_10_0; |
c4e95030 AF |
1102 | } else { |
1103 | error_setg(errp, | |
1104 | "Unsupported privilege spec version '%s'", | |
1105 | cpu->cfg.priv_spec); | |
1106 | return; | |
1107 | } | |
1108 | } | |
1109 | ||
18800095 | 1110 | if (priv_version >= PRIV_VERSION_1_10_0) { |
a8b37120 | 1111 | set_priv_version(env, priv_version); |
a8b37120 | 1112 | } |
c4e95030 | 1113 | |
9a1f054d AP |
1114 | /* Force disable extensions if priv spec version does not match */ |
1115 | for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { | |
1116 | if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && | |
1117 | (env->priv_ver < isa_edata_arr[i].min_version)) { | |
1118 | isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); | |
1119 | #ifndef CONFIG_USER_ONLY | |
877a3a37 BM |
1120 | warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx |
1121 | " because privilege spec version does not match", | |
1122 | isa_edata_arr[i].name, env->mhartid); | |
9a1f054d AP |
1123 | #else |
1124 | warn_report("disabling %s extension because " | |
1125 | "privilege spec version does not match", | |
1126 | isa_edata_arr[i].name); | |
1127 | #endif | |
1128 | } | |
1129 | } | |
1130 | ||
6a3ffda2 | 1131 | if (cpu->cfg.epmp && !cpu->cfg.pmp) { |
5da9514e HW |
1132 | /* |
1133 | * Enhanced PMP should only be available | |
1134 | * on harts with PMP support | |
1135 | */ | |
6a3ffda2 DHB |
1136 | error_setg(errp, "Invalid configuration: EPMP requires PMP support"); |
1137 | return; | |
1acdb3b0 BM |
1138 | } |
1139 | ||
73f6ed97 | 1140 | |
43888c2f AP |
1141 | #ifndef CONFIG_USER_ONLY |
1142 | if (cpu->cfg.ext_sstc) { | |
1143 | riscv_timer_init(cpu); | |
1144 | } | |
1145 | #endif /* CONFIG_USER_ONLY */ | |
1146 | ||
e91a7227 RH |
1147 | /* Validate that MISA_MXL is set properly. */ |
1148 | switch (env->misa_mxl_max) { | |
1149 | #ifdef TARGET_RISCV64 | |
1150 | case MXL_RV64: | |
332dab68 | 1151 | case MXL_RV128: |
6c3a9247 | 1152 | cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; |
332dab68 | 1153 | break; |
e91a7227 RH |
1154 | #endif |
1155 | case MXL_RV32: | |
1191be09 | 1156 | cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; |
e91a7227 RH |
1157 | break; |
1158 | default: | |
1159 | g_assert_not_reached(); | |
1160 | } | |
1161 | assert(env->misa_mxl_max == env->misa_mxl); | |
1162 | ||
5ab10952 DHB |
1163 | riscv_cpu_validate_set_extensions(cpu, &local_err); |
1164 | if (local_err != NULL) { | |
1165 | error_propagate(errp, local_err); | |
1166 | return; | |
b55d7d34 AF |
1167 | } |
1168 | ||
14664483 AP |
1169 | #ifndef CONFIG_USER_ONLY |
1170 | if (cpu->cfg.pmu_num) { | |
1171 | if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { | |
1172 | cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, | |
1173 | riscv_pmu_timer_cb, cpu); | |
1174 | } | |
1175 | } | |
1176 | #endif | |
1177 | ||
6f23aaeb AG |
1178 | riscv_cpu_finalize_features(cpu, &local_err); |
1179 | if (local_err != NULL) { | |
1180 | error_propagate(errp, local_err); | |
1181 | return; | |
1182 | } | |
1183 | ||
5371f5cd JW |
1184 | riscv_cpu_register_gdb_regs_for_features(cs); |
1185 | ||
dc5bd18f MC |
1186 | qemu_init_vcpu(cs); |
1187 | cpu_reset(cs); | |
1188 | ||
1189 | mcc->parent_realize(dev, errp); | |
1190 | } | |
1191 | ||
0f0b70ee | 1192 | #ifndef CONFIG_USER_ONLY |
6f23aaeb AG |
1193 | static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, |
1194 | void *opaque, Error **errp) | |
1195 | { | |
1196 | RISCVSATPMap *satp_map = opaque; | |
1197 | uint8_t satp = satp_mode_from_str(name); | |
1198 | bool value; | |
1199 | ||
1200 | value = satp_map->map & (1 << satp); | |
1201 | ||
1202 | visit_type_bool(v, name, &value, errp); | |
1203 | } | |
1204 | ||
1205 | static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, | |
1206 | void *opaque, Error **errp) | |
1207 | { | |
1208 | RISCVSATPMap *satp_map = opaque; | |
1209 | uint8_t satp = satp_mode_from_str(name); | |
1210 | bool value; | |
1211 | ||
1212 | if (!visit_type_bool(v, name, &value, errp)) { | |
1213 | return; | |
1214 | } | |
1215 | ||
1216 | satp_map->map = deposit32(satp_map->map, satp, 1, value); | |
1217 | satp_map->init |= 1 << satp; | |
1218 | } | |
1219 | ||
1220 | static void riscv_add_satp_mode_properties(Object *obj) | |
1221 | { | |
1222 | RISCVCPU *cpu = RISCV_CPU(obj); | |
1223 | ||
1224 | if (cpu->env.misa_mxl == MXL_RV32) { | |
1225 | object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, | |
1226 | cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); | |
1227 | } else { | |
1228 | object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, | |
1229 | cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); | |
1230 | object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, | |
1231 | cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); | |
1232 | object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, | |
1233 | cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); | |
1234 | object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, | |
1235 | cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); | |
1236 | } | |
1237 | } | |
1238 | ||
0f0b70ee AF |
1239 | static void riscv_cpu_set_irq(void *opaque, int irq, int level) |
1240 | { | |
1241 | RISCVCPU *cpu = RISCV_CPU(opaque); | |
cd032fe7 | 1242 | CPURISCVState *env = &cpu->env; |
0f0b70ee | 1243 | |
cd032fe7 AP |
1244 | if (irq < IRQ_LOCAL_MAX) { |
1245 | switch (irq) { | |
1246 | case IRQ_U_SOFT: | |
1247 | case IRQ_S_SOFT: | |
1248 | case IRQ_VS_SOFT: | |
1249 | case IRQ_M_SOFT: | |
1250 | case IRQ_U_TIMER: | |
1251 | case IRQ_S_TIMER: | |
1252 | case IRQ_VS_TIMER: | |
1253 | case IRQ_M_TIMER: | |
1254 | case IRQ_U_EXT: | |
cd032fe7 AP |
1255 | case IRQ_VS_EXT: |
1256 | case IRQ_M_EXT: | |
8b5c807b | 1257 | if (kvm_enabled()) { |
cd032fe7 | 1258 | kvm_riscv_set_irq(cpu, irq, level); |
8b5c807b | 1259 | } else { |
cd032fe7 | 1260 | riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); |
8b5c807b | 1261 | } |
cd032fe7 | 1262 | break; |
33fe584f AF |
1263 | case IRQ_S_EXT: |
1264 | if (kvm_enabled()) { | |
1265 | kvm_riscv_set_irq(cpu, irq, level); | |
1266 | } else { | |
1267 | env->external_seip = level; | |
1268 | riscv_cpu_update_mip(cpu, 1 << irq, | |
1269 | BOOL_TO_MASK(level | env->software_seip)); | |
1270 | } | |
1271 | break; | |
cd032fe7 AP |
1272 | default: |
1273 | g_assert_not_reached(); | |
2b650fbb | 1274 | } |
cd032fe7 AP |
1275 | } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { |
1276 | /* Require H-extension for handling guest local interrupts */ | |
1277 | if (!riscv_has_ext(env, RVH)) { | |
1278 | g_assert_not_reached(); | |
1279 | } | |
1280 | ||
1281 | /* Compute bit position in HGEIP CSR */ | |
1282 | irq = irq - IRQ_LOCAL_MAX + 1; | |
1283 | if (env->geilen < irq) { | |
1284 | g_assert_not_reached(); | |
1285 | } | |
1286 | ||
1287 | /* Update HGEIP CSR */ | |
1288 | env->hgeip &= ~((target_ulong)1 << irq); | |
1289 | if (level) { | |
1290 | env->hgeip |= (target_ulong)1 << irq; | |
1291 | } | |
1292 | ||
1293 | /* Update mip.SGEIP bit */ | |
1294 | riscv_cpu_update_mip(cpu, MIP_SGEIP, | |
1295 | BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); | |
1296 | } else { | |
0f0b70ee AF |
1297 | g_assert_not_reached(); |
1298 | } | |
1299 | } | |
1300 | #endif /* CONFIG_USER_ONLY */ | |
1301 | ||
dc5bd18f MC |
1302 | static void riscv_cpu_init(Object *obj) |
1303 | { | |
dc5bd18f MC |
1304 | RISCVCPU *cpu = RISCV_CPU(obj); |
1305 | ||
26b2bc58 AF |
1306 | cpu->cfg.ext_ifencei = true; |
1307 | cpu->cfg.ext_icsr = true; | |
1308 | cpu->cfg.mmu = true; | |
1309 | cpu->cfg.pmp = true; | |
1310 | ||
7506ed90 | 1311 | cpu_set_cpustate_pointers(cpu); |
0f0b70ee AF |
1312 | |
1313 | #ifndef CONFIG_USER_ONLY | |
cd032fe7 AP |
1314 | qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, |
1315 | IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); | |
0f0b70ee | 1316 | #endif /* CONFIG_USER_ONLY */ |
dc5bd18f MC |
1317 | } |
1318 | ||
26b2bc58 | 1319 | static Property riscv_cpu_extensions[] = { |
9d3d60b7 | 1320 | /* Defaults for standard extensions */ |
b55d7d34 AF |
1321 | DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), |
1322 | DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), | |
1d398ab9 | 1323 | DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), |
b55d7d34 AF |
1324 | DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), |
1325 | DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), | |
1326 | DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), | |
1327 | DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), | |
1328 | DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), | |
1329 | DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), | |
1330 | DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), | |
9ec6622d | 1331 | DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), |
07cb270a | 1332 | DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), |
18d6d89e | 1333 | DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), |
14664483 | 1334 | DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), |
9d3d60b7 AF |
1335 | DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), |
1336 | DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), | |
4696f0ab | 1337 | DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), |
260b594d | 1338 | DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), |
13fb8c7b | 1339 | DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), |
e5237730 | 1340 | DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), |
2fc1b44d | 1341 | DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), |
bfefe406 | 1342 | DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), |
058d9d30 | 1343 | DEFINE_PROP_BOOL("Zve64d", RISCVCPU, cfg.ext_zve64d, false), |
9d3d60b7 AF |
1344 | DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), |
1345 | DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), | |
43888c2f | 1346 | DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true), |
9d3d60b7 AF |
1347 | |
1348 | DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), | |
9ec6622d FC |
1349 | DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), |
1350 | DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), | |
1351 | DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), | |
9d3d60b7 | 1352 | |
62108f05 WL |
1353 | DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true), |
1354 | ||
c5d77ddd | 1355 | DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), |
2bacb224 | 1356 | DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), |
bbce8ba8 | 1357 | DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), |
2bacb224 | 1358 | |
0643c12e VG |
1359 | DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), |
1360 | DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), | |
1361 | DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), | |
cf7ed971 WL |
1362 | DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false), |
1363 | DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false), | |
1364 | DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false), | |
0643c12e | 1365 | DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), |
cf7ed971 WL |
1366 | DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false), |
1367 | DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false), | |
1368 | DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false), | |
1369 | DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false), | |
1370 | DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false), | |
1371 | DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false), | |
1372 | DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false), | |
1373 | DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false), | |
1374 | DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), | |
1375 | DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), | |
dfdb46a3 | 1376 | |
6b1accef WL |
1377 | DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), |
1378 | DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), | |
1379 | DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), | |
1380 | DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), | |
1381 | ||
e05da09b CM |
1382 | DEFINE_PROP_BOOL("zicbom", RISCVCPU, cfg.ext_icbom, true), |
1383 | DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64), | |
a939c500 CM |
1384 | DEFINE_PROP_BOOL("zicboz", RISCVCPU, cfg.ext_icboz, true), |
1385 | DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), | |
1386 | ||
6d00ffad WL |
1387 | DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), |
1388 | ||
0d429bd2 | 1389 | /* Vendor-specific custom extensions */ |
c9410a68 | 1390 | DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), |
426c0491 | 1391 | DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), |
fa134585 | 1392 | DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), |
49a7f3aa | 1393 | DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), |
32909338 | 1394 | DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), |
d4d90115 | 1395 | DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false), |
578086ba | 1396 | DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false), |
b8a5832b | 1397 | DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), |
45f9df86 | 1398 | DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false), |
af99aa72 | 1399 | DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false), |
134c3ffa | 1400 | DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), |
0d429bd2 PT |
1401 | DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), |
1402 | ||
dfdb46a3 | 1403 | /* These are experimental so mark with 'x-' */ |
b8e1f32c | 1404 | DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), |
0ee9a4e5 | 1405 | DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), |
a44da25a | 1406 | /* ePMP 0.9.3 */ |
5da9514e | 1407 | DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), |
dc9acc9c AP |
1408 | DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), |
1409 | DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), | |
5da9514e | 1410 | |
058d9d30 WL |
1411 | DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false), |
1412 | DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false), | |
1413 | ||
26b2bc58 AF |
1414 | DEFINE_PROP_END_OF_LIST(), |
1415 | }; | |
1416 | ||
c66ffcd5 DHB |
1417 | /* |
1418 | * Register CPU props based on env.misa_ext. If a non-zero | |
1419 | * value was set, register only the required cpu->cfg.ext_* | |
1420 | * properties and leave. env.misa_ext = 0 means that we want | |
1421 | * all the default properties to be registered. | |
1422 | */ | |
c01756a7 | 1423 | static void register_cpu_props(Object *obj) |
26b2bc58 | 1424 | { |
c01756a7 | 1425 | RISCVCPU *cpu = RISCV_CPU(obj); |
c66ffcd5 | 1426 | uint32_t misa_ext = cpu->env.misa_ext; |
26b2bc58 | 1427 | Property *prop; |
c01756a7 | 1428 | DeviceState *dev = DEVICE(obj); |
26b2bc58 | 1429 | |
c66ffcd5 DHB |
1430 | /* |
1431 | * If misa_ext is not zero, set cfg properties now to | |
1432 | * allow them to be read during riscv_cpu_realize() | |
1433 | * later on. | |
1434 | */ | |
1435 | if (cpu->env.misa_ext != 0) { | |
1436 | cpu->cfg.ext_i = misa_ext & RVI; | |
1437 | cpu->cfg.ext_e = misa_ext & RVE; | |
1438 | cpu->cfg.ext_m = misa_ext & RVM; | |
1439 | cpu->cfg.ext_a = misa_ext & RVA; | |
1440 | cpu->cfg.ext_f = misa_ext & RVF; | |
1441 | cpu->cfg.ext_d = misa_ext & RVD; | |
1442 | cpu->cfg.ext_v = misa_ext & RVV; | |
1443 | cpu->cfg.ext_c = misa_ext & RVC; | |
1444 | cpu->cfg.ext_s = misa_ext & RVS; | |
1445 | cpu->cfg.ext_u = misa_ext & RVU; | |
1446 | cpu->cfg.ext_h = misa_ext & RVH; | |
1447 | cpu->cfg.ext_j = misa_ext & RVJ; | |
1448 | ||
1449 | /* | |
1450 | * We don't want to set the default riscv_cpu_extensions | |
1451 | * in this case. | |
1452 | */ | |
1453 | return; | |
1454 | } | |
1455 | ||
26b2bc58 AF |
1456 | for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { |
1457 | qdev_property_add_static(dev, prop); | |
1458 | } | |
6f23aaeb AG |
1459 | |
1460 | #ifndef CONFIG_USER_ONLY | |
1461 | riscv_add_satp_mode_properties(obj); | |
1462 | #endif | |
26b2bc58 AF |
1463 | } |
1464 | ||
1465 | static Property riscv_cpu_properties[] = { | |
1466 | DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), | |
1467 | ||
1468 | DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), | |
1469 | DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), | |
1470 | DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), | |
1471 | ||
277b210d AF |
1472 | #ifndef CONFIG_USER_ONLY |
1473 | DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), | |
1474 | #endif | |
a4a9a443 TO |
1475 | |
1476 | DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), | |
b8312675 | 1477 | |
1478 | DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), | |
1ad3f9bd | 1479 | DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), |
54bd9b6e DHB |
1480 | |
1481 | /* | |
1482 | * write_misa() is marked as experimental for now so mark | |
1483 | * it with -x and default to 'false'. | |
1484 | */ | |
1485 | DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false), | |
c4e95030 AF |
1486 | DEFINE_PROP_END_OF_LIST(), |
1487 | }; | |
1488 | ||
edf64786 SP |
1489 | static gchar *riscv_gdb_arch_name(CPUState *cs) |
1490 | { | |
1491 | RISCVCPU *cpu = RISCV_CPU(cs); | |
1492 | CPURISCVState *env = &cpu->env; | |
1493 | ||
db23e5d9 RH |
1494 | switch (riscv_cpu_mxl(env)) { |
1495 | case MXL_RV32: | |
edf64786 | 1496 | return g_strdup("riscv:rv32"); |
db23e5d9 | 1497 | case MXL_RV64: |
332dab68 | 1498 | case MXL_RV128: |
edf64786 | 1499 | return g_strdup("riscv:rv64"); |
db23e5d9 RH |
1500 | default: |
1501 | g_assert_not_reached(); | |
edf64786 SP |
1502 | } |
1503 | } | |
1504 | ||
b93777e1 BM |
1505 | static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) |
1506 | { | |
1507 | RISCVCPU *cpu = RISCV_CPU(cs); | |
1508 | ||
1509 | if (strcmp(xmlname, "riscv-csr.xml") == 0) { | |
1510 | return cpu->dyn_csr_xml; | |
719d3561 HW |
1511 | } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { |
1512 | return cpu->dyn_vreg_xml; | |
b93777e1 BM |
1513 | } |
1514 | ||
1515 | return NULL; | |
1516 | } | |
1517 | ||
8b80bd28 | 1518 | #ifndef CONFIG_USER_ONLY |
f1bd6f8e MC |
1519 | static int64_t riscv_get_arch_id(CPUState *cs) |
1520 | { | |
1521 | RISCVCPU *cpu = RISCV_CPU(cs); | |
1522 | ||
1523 | return cpu->env.mhartid; | |
1524 | } | |
1525 | ||
8b80bd28 PMD |
1526 | #include "hw/core/sysemu-cpu-ops.h" |
1527 | ||
1528 | static const struct SysemuCPUOps riscv_sysemu_ops = { | |
08928c6d | 1529 | .get_phys_page_debug = riscv_cpu_get_phys_page_debug, |
715e3c1a PMD |
1530 | .write_elf64_note = riscv_cpu_write_elf64_note, |
1531 | .write_elf32_note = riscv_cpu_write_elf32_note, | |
feece4d0 | 1532 | .legacy_vmsd = &vmstate_riscv_cpu, |
8b80bd28 PMD |
1533 | }; |
1534 | #endif | |
1535 | ||
78271684 CF |
1536 | #include "hw/core/tcg-cpu-ops.h" |
1537 | ||
11906557 | 1538 | static const struct TCGCPUOps riscv_tcg_ops = { |
78271684 CF |
1539 | .initialize = riscv_translate_init, |
1540 | .synchronize_from_tb = riscv_cpu_synchronize_from_tb, | |
ad1e84f5 | 1541 | .restore_state_to_opc = riscv_restore_state_to_opc, |
78271684 CF |
1542 | |
1543 | #ifndef CONFIG_USER_ONLY | |
263e2ab2 | 1544 | .tlb_fill = riscv_cpu_tlb_fill, |
17b3c353 | 1545 | .cpu_exec_interrupt = riscv_cpu_exec_interrupt, |
78271684 CF |
1546 | .do_interrupt = riscv_cpu_do_interrupt, |
1547 | .do_transaction_failed = riscv_cpu_do_transaction_failed, | |
1548 | .do_unaligned_access = riscv_cpu_do_unaligned_access, | |
b5f6379d BM |
1549 | .debug_excp_handler = riscv_cpu_debug_excp_handler, |
1550 | .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, | |
1551 | .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, | |
78271684 CF |
1552 | #endif /* !CONFIG_USER_ONLY */ |
1553 | }; | |
1554 | ||
dc5bd18f MC |
1555 | static void riscv_cpu_class_init(ObjectClass *c, void *data) |
1556 | { | |
1557 | RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); | |
1558 | CPUClass *cc = CPU_CLASS(c); | |
1559 | DeviceClass *dc = DEVICE_CLASS(c); | |
4fa485a7 | 1560 | ResettableClass *rc = RESETTABLE_CLASS(c); |
dc5bd18f | 1561 | |
41fbbba7 MZ |
1562 | device_class_set_parent_realize(dc, riscv_cpu_realize, |
1563 | &mcc->parent_realize); | |
dc5bd18f | 1564 | |
4fa485a7 PM |
1565 | resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL, |
1566 | &mcc->parent_phases); | |
dc5bd18f MC |
1567 | |
1568 | cc->class_by_name = riscv_cpu_class_by_name; | |
1569 | cc->has_work = riscv_cpu_has_work; | |
dc5bd18f MC |
1570 | cc->dump_state = riscv_cpu_dump_state; |
1571 | cc->set_pc = riscv_cpu_set_pc; | |
e4fdf9df | 1572 | cc->get_pc = riscv_cpu_get_pc; |
dc5bd18f MC |
1573 | cc->gdb_read_register = riscv_cpu_gdb_read_register; |
1574 | cc->gdb_write_register = riscv_cpu_gdb_write_register; | |
5371f5cd | 1575 | cc->gdb_num_core_regs = 33; |
dc5bd18f MC |
1576 | cc->gdb_stop_before_watchpoint = true; |
1577 | cc->disas_set_info = riscv_cpu_disas_set_info; | |
8a4ca3c1 | 1578 | #ifndef CONFIG_USER_ONLY |
8b80bd28 | 1579 | cc->sysemu_ops = &riscv_sysemu_ops; |
f1bd6f8e | 1580 | cc->get_arch_id = riscv_get_arch_id; |
dc5bd18f | 1581 | #endif |
edf64786 | 1582 | cc->gdb_arch_name = riscv_gdb_arch_name; |
b93777e1 | 1583 | cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; |
78271684 | 1584 | cc->tcg_ops = &riscv_tcg_ops; |
6a3d2e7c | 1585 | |
4f67d30b | 1586 | device_class_set_props(dc, riscv_cpu_properties); |
dc5bd18f MC |
1587 | } |
1588 | ||
a775398b AP |
1589 | static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) |
1590 | { | |
1591 | char *old = *isa_str; | |
1592 | char *new = *isa_str; | |
1593 | int i; | |
1594 | ||
a775398b | 1595 | for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { |
9a1f054d AP |
1596 | if (isa_edata_arr[i].multi_letter && |
1597 | isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { | |
a775398b AP |
1598 | new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); |
1599 | g_free(old); | |
1600 | old = new; | |
1601 | } | |
1602 | } | |
1603 | ||
1604 | *isa_str = new; | |
1605 | } | |
1606 | ||
dc5bd18f MC |
1607 | char *riscv_isa_string(RISCVCPU *cpu) |
1608 | { | |
1609 | int i; | |
0e2c3770 | 1610 | const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); |
d1fd31f8 MC |
1611 | char *isa_str = g_new(char, maxlen); |
1612 | char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); | |
0e2c3770 TO |
1613 | for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { |
1614 | if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { | |
1615 | *p++ = qemu_tolower(riscv_single_letter_exts[i]); | |
dc5bd18f MC |
1616 | } |
1617 | } | |
d1fd31f8 | 1618 | *p = '\0'; |
a4a9a443 TO |
1619 | if (!cpu->cfg.short_isa_string) { |
1620 | riscv_isa_string_ext(cpu, &isa_str, maxlen); | |
1621 | } | |
d1fd31f8 | 1622 | return isa_str; |
dc5bd18f MC |
1623 | } |
1624 | ||
eab15862 | 1625 | static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) |
dc5bd18f | 1626 | { |
eab15862 MC |
1627 | ObjectClass *class_a = (ObjectClass *)a; |
1628 | ObjectClass *class_b = (ObjectClass *)b; | |
1629 | const char *name_a, *name_b; | |
dc5bd18f | 1630 | |
eab15862 MC |
1631 | name_a = object_class_get_name(class_a); |
1632 | name_b = object_class_get_name(class_b); | |
1633 | return strcmp(name_a, name_b); | |
dc5bd18f MC |
1634 | } |
1635 | ||
eab15862 | 1636 | static void riscv_cpu_list_entry(gpointer data, gpointer user_data) |
dc5bd18f | 1637 | { |
eab15862 MC |
1638 | const char *typename = object_class_get_name(OBJECT_CLASS(data)); |
1639 | int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); | |
dc5bd18f | 1640 | |
0442428a | 1641 | qemu_printf("%.*s\n", len, typename); |
eab15862 | 1642 | } |
dc5bd18f | 1643 | |
0442428a | 1644 | void riscv_cpu_list(void) |
eab15862 | 1645 | { |
eab15862 MC |
1646 | GSList *list; |
1647 | ||
1648 | list = object_class_get_list(TYPE_RISCV_CPU, false); | |
1649 | list = g_slist_sort(list, riscv_cpu_list_compare); | |
0442428a | 1650 | g_slist_foreach(list, riscv_cpu_list_entry, NULL); |
eab15862 | 1651 | g_slist_free(list); |
dc5bd18f MC |
1652 | } |
1653 | ||
eab15862 MC |
1654 | #define DEFINE_CPU(type_name, initfn) \ |
1655 | { \ | |
1656 | .name = type_name, \ | |
1657 | .parent = TYPE_RISCV_CPU, \ | |
1658 | .instance_init = initfn \ | |
1659 | } | |
1660 | ||
1661 | static const TypeInfo riscv_cpu_type_infos[] = { | |
1662 | { | |
1663 | .name = TYPE_RISCV_CPU, | |
1664 | .parent = TYPE_CPU, | |
1665 | .instance_size = sizeof(RISCVCPU), | |
5de5b99b | 1666 | .instance_align = __alignof__(RISCVCPU), |
eab15862 MC |
1667 | .instance_init = riscv_cpu_init, |
1668 | .abstract = true, | |
1669 | .class_size = sizeof(RISCVCPUClass), | |
1670 | .class_init = riscv_cpu_class_init, | |
1671 | }, | |
1672 | DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), | |
10f1ca27 YJ |
1673 | #if defined(CONFIG_KVM) |
1674 | DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), | |
1675 | #endif | |
eab15862 | 1676 | #if defined(TARGET_RISCV32) |
094b072c | 1677 | DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), |
e8905c6c | 1678 | DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), |
114baaca | 1679 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), |
2fdd2c09 | 1680 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), |
114baaca | 1681 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), |
eab15862 | 1682 | #elif defined(TARGET_RISCV64) |
094b072c | 1683 | DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), |
114baaca AF |
1684 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), |
1685 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), | |
6ddc7069 | 1686 | DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), |
95bd8daa | 1687 | DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), |
332dab68 | 1688 | DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), |
eab15862 MC |
1689 | #endif |
1690 | }; | |
1691 | ||
1692 | DEFINE_TYPES(riscv_cpu_type_infos) |