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dc5bd18f MC |
1 | /* |
2 | * QEMU RISC-V CPU | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
0442428a | 21 | #include "qemu/qemu-print.h" |
856dfd8a | 22 | #include "qemu/ctype.h" |
dc5bd18f MC |
23 | #include "qemu/log.h" |
24 | #include "cpu.h" | |
f7697f0e | 25 | #include "internals.h" |
dc5bd18f MC |
26 | #include "exec/exec-all.h" |
27 | #include "qapi/error.h" | |
b55d7d34 | 28 | #include "qemu/error-report.h" |
c4e95030 | 29 | #include "hw/qdev-properties.h" |
dc5bd18f | 30 | #include "migration/vmstate.h" |
135b03cb | 31 | #include "fpu/softfloat-helpers.h" |
dc5bd18f MC |
32 | |
33 | /* RISC-V CPU definitions */ | |
34 | ||
79f86934 | 35 | static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG"; |
dc5bd18f MC |
36 | |
37 | const char * const riscv_int_regnames[] = { | |
a9f37afa AP |
38 | "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", |
39 | "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", | |
40 | "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", | |
41 | "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", | |
42 | "x28/t3", "x29/t4", "x30/t5", "x31/t6" | |
dc5bd18f MC |
43 | }; |
44 | ||
45 | const char * const riscv_fpr_regnames[] = { | |
a9f37afa AP |
46 | "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", |
47 | "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", | |
48 | "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", | |
49 | "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", | |
50 | "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", | |
51 | "f30/ft10", "f31/ft11" | |
dc5bd18f MC |
52 | }; |
53 | ||
9a575d33 | 54 | static const char * const riscv_excp_names[] = { |
dc5bd18f MC |
55 | "misaligned_fetch", |
56 | "fault_fetch", | |
57 | "illegal_instruction", | |
58 | "breakpoint", | |
59 | "misaligned_load", | |
60 | "fault_load", | |
61 | "misaligned_store", | |
62 | "fault_store", | |
63 | "user_ecall", | |
64 | "supervisor_ecall", | |
65 | "hypervisor_ecall", | |
66 | "machine_ecall", | |
67 | "exec_page_fault", | |
68 | "load_page_fault", | |
69 | "reserved", | |
fd990e86 | 70 | "store_page_fault", |
ab67a1d0 AF |
71 | "reserved", |
72 | "reserved", | |
73 | "reserved", | |
74 | "reserved", | |
75 | "guest_exec_page_fault", | |
76 | "guest_load_page_fault", | |
77 | "reserved", | |
fd990e86 | 78 | "guest_store_page_fault", |
dc5bd18f MC |
79 | }; |
80 | ||
9a575d33 | 81 | static const char * const riscv_intr_names[] = { |
dc5bd18f MC |
82 | "u_software", |
83 | "s_software", | |
205377f8 | 84 | "vs_software", |
dc5bd18f MC |
85 | "m_software", |
86 | "u_timer", | |
87 | "s_timer", | |
205377f8 | 88 | "vs_timer", |
dc5bd18f MC |
89 | "m_timer", |
90 | "u_external", | |
6cfcf775 | 91 | "s_external", |
205377f8 | 92 | "vs_external", |
dc5bd18f | 93 | "m_external", |
426f0348 MC |
94 | "reserved", |
95 | "reserved", | |
96 | "reserved", | |
97 | "reserved" | |
dc5bd18f MC |
98 | }; |
99 | ||
c51a3f5d YJ |
100 | const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) |
101 | { | |
102 | if (async) { | |
103 | return (cause < ARRAY_SIZE(riscv_intr_names)) ? | |
104 | riscv_intr_names[cause] : "(unknown)"; | |
105 | } else { | |
106 | return (cause < ARRAY_SIZE(riscv_excp_names)) ? | |
107 | riscv_excp_names[cause] : "(unknown)"; | |
108 | } | |
109 | } | |
110 | ||
e91a7227 | 111 | static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) |
dc5bd18f | 112 | { |
e91a7227 RH |
113 | env->misa_mxl_max = env->misa_mxl = mxl; |
114 | env->misa_ext_mask = env->misa_ext = ext; | |
dc5bd18f MC |
115 | } |
116 | ||
c9a73910 | 117 | static void set_priv_version(CPURISCVState *env, int priv_ver) |
dc5bd18f | 118 | { |
dc5bd18f MC |
119 | env->priv_ver = priv_ver; |
120 | } | |
121 | ||
32931383 LZ |
122 | static void set_vext_version(CPURISCVState *env, int vext_ver) |
123 | { | |
124 | env->vext_ver = vext_ver; | |
125 | } | |
126 | ||
dc5bd18f MC |
127 | static void set_feature(CPURISCVState *env, int feature) |
128 | { | |
129 | env->features |= (1ULL << feature); | |
130 | } | |
131 | ||
01e723bf | 132 | static void set_resetvec(CPURISCVState *env, target_ulong resetvec) |
dc5bd18f MC |
133 | { |
134 | #ifndef CONFIG_USER_ONLY | |
135 | env->resetvec = resetvec; | |
136 | #endif | |
137 | } | |
138 | ||
139 | static void riscv_any_cpu_init(Object *obj) | |
140 | { | |
141 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
3820602f | 142 | #if defined(TARGET_RISCV32) |
e91a7227 | 143 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); |
3820602f | 144 | #elif defined(TARGET_RISCV64) |
e91a7227 | 145 | set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); |
3820602f | 146 | #endif |
c9a73910 | 147 | set_priv_version(env, PRIV_VERSION_1_11_0); |
dc5bd18f MC |
148 | } |
149 | ||
094b072c AF |
150 | #if defined(TARGET_RISCV64) |
151 | static void rv64_base_cpu_init(Object *obj) | |
8903bf6e AF |
152 | { |
153 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
b55d7d34 | 154 | /* We set this in the realise function */ |
e91a7227 | 155 | set_misa(env, MXL_RV64, 0); |
8903bf6e AF |
156 | } |
157 | ||
114baaca | 158 | static void rv64_sifive_u_cpu_init(Object *obj) |
dc5bd18f MC |
159 | { |
160 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
e91a7227 | 161 | set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); |
c9a73910 | 162 | set_priv_version(env, PRIV_VERSION_1_10_0); |
dc5bd18f MC |
163 | } |
164 | ||
114baaca | 165 | static void rv64_sifive_e_cpu_init(Object *obj) |
36b80ad9 AF |
166 | { |
167 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
e91a7227 | 168 | set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); |
36b80ad9 | 169 | set_priv_version(env, PRIV_VERSION_1_10_0); |
36b80ad9 AF |
170 | qdev_prop_set_bit(DEVICE(obj), "mmu", false); |
171 | } | |
114baaca | 172 | #else |
094b072c AF |
173 | static void rv32_base_cpu_init(Object *obj) |
174 | { | |
175 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
176 | /* We set this in the realise function */ | |
e91a7227 | 177 | set_misa(env, MXL_RV32, 0); |
094b072c AF |
178 | } |
179 | ||
114baaca AF |
180 | static void rv32_sifive_u_cpu_init(Object *obj) |
181 | { | |
182 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
e91a7227 | 183 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); |
114baaca AF |
184 | set_priv_version(env, PRIV_VERSION_1_10_0); |
185 | } | |
36b80ad9 | 186 | |
114baaca AF |
187 | static void rv32_sifive_e_cpu_init(Object *obj) |
188 | { | |
189 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
e91a7227 | 190 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); |
114baaca AF |
191 | set_priv_version(env, PRIV_VERSION_1_10_0); |
192 | qdev_prop_set_bit(DEVICE(obj), "mmu", false); | |
193 | } | |
d8e72bd1 | 194 | |
e8905c6c | 195 | static void rv32_ibex_cpu_init(Object *obj) |
dc5bd18f MC |
196 | { |
197 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
e91a7227 | 198 | set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); |
c9a73910 | 199 | set_priv_version(env, PRIV_VERSION_1_10_0); |
8be6971b | 200 | qdev_prop_set_bit(DEVICE(obj), "mmu", false); |
ed6eebaa | 201 | qdev_prop_set_bit(DEVICE(obj), "x-epmp", true); |
dc5bd18f MC |
202 | } |
203 | ||
2fdd2c09 | 204 | static void rv32_imafcu_nommu_cpu_init(Object *obj) |
d784733b CW |
205 | { |
206 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
e91a7227 | 207 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); |
d784733b CW |
208 | set_priv_version(env, PRIV_VERSION_1_10_0); |
209 | set_resetvec(env, DEFAULT_RSTVEC); | |
8be6971b | 210 | qdev_prop_set_bit(DEVICE(obj), "mmu", false); |
d784733b | 211 | } |
eab15862 | 212 | #endif |
dc5bd18f MC |
213 | |
214 | static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) | |
215 | { | |
216 | ObjectClass *oc; | |
217 | char *typename; | |
218 | char **cpuname; | |
219 | ||
220 | cpuname = g_strsplit(cpu_model, ",", 1); | |
221 | typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); | |
222 | oc = object_class_by_name(typename); | |
223 | g_strfreev(cpuname); | |
224 | g_free(typename); | |
225 | if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || | |
226 | object_class_is_abstract(oc)) { | |
227 | return NULL; | |
228 | } | |
229 | return oc; | |
230 | } | |
231 | ||
90c84c56 | 232 | static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) |
dc5bd18f MC |
233 | { |
234 | RISCVCPU *cpu = RISCV_CPU(cs); | |
235 | CPURISCVState *env = &cpu->env; | |
236 | int i; | |
237 | ||
df30e652 AF |
238 | #if !defined(CONFIG_USER_ONLY) |
239 | if (riscv_has_ext(env, RVH)) { | |
240 | qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); | |
241 | } | |
242 | #endif | |
90c84c56 | 243 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); |
dc5bd18f | 244 | #ifndef CONFIG_USER_ONLY |
90c84c56 | 245 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); |
284d697c | 246 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus); |
db23e5d9 | 247 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
5c5a47f1 AF |
248 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", |
249 | (target_ulong)(env->mstatus >> 32)); | |
250 | } | |
df30e652 AF |
251 | if (riscv_has_ext(env, RVH)) { |
252 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus); | |
e573a7f3 | 253 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus", |
284d697c | 254 | (target_ulong)env->vsstatus); |
df30e652 | 255 | } |
02861613 | 256 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip); |
90c84c56 MA |
257 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie); |
258 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg); | |
df30e652 AF |
259 | if (riscv_has_ext(env, RVH)) { |
260 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg); | |
261 | } | |
90c84c56 | 262 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg); |
df30e652 AF |
263 | if (riscv_has_ext(env, RVH)) { |
264 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg); | |
265 | } | |
90c84c56 | 266 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec ", env->mtvec); |
df30e652 AF |
267 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec ", env->stvec); |
268 | if (riscv_has_ext(env, RVH)) { | |
269 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec ", env->vstvec); | |
270 | } | |
90c84c56 | 271 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc ", env->mepc); |
df30e652 AF |
272 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc ", env->sepc); |
273 | if (riscv_has_ext(env, RVH)) { | |
274 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc ", env->vsepc); | |
275 | } | |
90c84c56 | 276 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause ", env->mcause); |
df30e652 AF |
277 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause ", env->scause); |
278 | if (riscv_has_ext(env, RVH)) { | |
279 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause); | |
280 | } | |
a722701d CD |
281 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval); |
282 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->stval); | |
df30e652 | 283 | if (riscv_has_ext(env, RVH)) { |
e573a7f3 TG |
284 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval); |
285 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2); | |
df30e652 | 286 | } |
a722701d CD |
287 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch", env->mscratch); |
288 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch", env->sscratch); | |
289 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "satp ", env->satp); | |
dc5bd18f MC |
290 | #endif |
291 | ||
292 | for (i = 0; i < 32; i++) { | |
e573a7f3 | 293 | qemu_fprintf(f, " %-8s " TARGET_FMT_lx, |
90c84c56 | 294 | riscv_int_regnames[i], env->gpr[i]); |
dc5bd18f | 295 | if ((i & 3) == 3) { |
90c84c56 | 296 | qemu_fprintf(f, "\n"); |
dc5bd18f MC |
297 | } |
298 | } | |
86ea1880 RH |
299 | if (flags & CPU_DUMP_FPU) { |
300 | for (i = 0; i < 32; i++) { | |
e573a7f3 | 301 | qemu_fprintf(f, " %-8s %016" PRIx64, |
90c84c56 | 302 | riscv_fpr_regnames[i], env->fpr[i]); |
86ea1880 | 303 | if ((i & 3) == 3) { |
90c84c56 | 304 | qemu_fprintf(f, "\n"); |
86ea1880 | 305 | } |
dc5bd18f MC |
306 | } |
307 | } | |
308 | } | |
309 | ||
310 | static void riscv_cpu_set_pc(CPUState *cs, vaddr value) | |
311 | { | |
312 | RISCVCPU *cpu = RISCV_CPU(cs); | |
313 | CPURISCVState *env = &cpu->env; | |
314 | env->pc = value; | |
315 | } | |
316 | ||
04a37d4c RH |
317 | static void riscv_cpu_synchronize_from_tb(CPUState *cs, |
318 | const TranslationBlock *tb) | |
dc5bd18f MC |
319 | { |
320 | RISCVCPU *cpu = RISCV_CPU(cs); | |
321 | CPURISCVState *env = &cpu->env; | |
322 | env->pc = tb->pc; | |
323 | } | |
324 | ||
325 | static bool riscv_cpu_has_work(CPUState *cs) | |
326 | { | |
327 | #ifndef CONFIG_USER_ONLY | |
328 | RISCVCPU *cpu = RISCV_CPU(cs); | |
329 | CPURISCVState *env = &cpu->env; | |
330 | /* | |
331 | * Definition of the WFI instruction requires it to ignore the privilege | |
332 | * mode and delegation registers, but respect individual enables | |
333 | */ | |
7ec5d303 | 334 | return (env->mip & env->mie) != 0; |
dc5bd18f MC |
335 | #else |
336 | return true; | |
337 | #endif | |
338 | } | |
339 | ||
340 | void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, | |
341 | target_ulong *data) | |
342 | { | |
343 | env->pc = data[0]; | |
344 | } | |
345 | ||
781c67ca | 346 | static void riscv_cpu_reset(DeviceState *dev) |
dc5bd18f | 347 | { |
781c67ca | 348 | CPUState *cs = CPU(dev); |
dc5bd18f MC |
349 | RISCVCPU *cpu = RISCV_CPU(cs); |
350 | RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); | |
351 | CPURISCVState *env = &cpu->env; | |
352 | ||
781c67ca | 353 | mcc->parent_reset(dev); |
dc5bd18f | 354 | #ifndef CONFIG_USER_ONLY |
e91a7227 | 355 | env->misa_mxl = env->misa_mxl_max; |
dc5bd18f MC |
356 | env->priv = PRV_M; |
357 | env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); | |
92371bd9 RH |
358 | if (env->misa_mxl > MXL_RV32) { |
359 | /* | |
360 | * The reset status of SXL/UXL is undefined, but mstatus is WARL | |
361 | * and we must ensure that the value after init is valid for read. | |
362 | */ | |
363 | env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); | |
364 | env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); | |
365 | } | |
dc5bd18f MC |
366 | env->mcause = 0; |
367 | env->pc = env->resetvec; | |
ec352d0c | 368 | env->two_stage_lookup = false; |
dc5bd18f | 369 | #endif |
330d2ae3 | 370 | cs->exception_index = RISCV_EXCP_NONE; |
c13b169f | 371 | env->load_res = -1; |
dc5bd18f MC |
372 | set_default_nan_mode(1, &env->fp_status); |
373 | } | |
374 | ||
375 | static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) | |
376 | { | |
5c5a47f1 | 377 | RISCVCPU *cpu = RISCV_CPU(s); |
db23e5d9 RH |
378 | |
379 | switch (riscv_cpu_mxl(&cpu->env)) { | |
380 | case MXL_RV32: | |
5c5a47f1 | 381 | info->print_insn = print_insn_riscv32; |
db23e5d9 RH |
382 | break; |
383 | case MXL_RV64: | |
5c5a47f1 | 384 | info->print_insn = print_insn_riscv64; |
db23e5d9 RH |
385 | break; |
386 | default: | |
387 | g_assert_not_reached(); | |
5c5a47f1 | 388 | } |
dc5bd18f MC |
389 | } |
390 | ||
391 | static void riscv_cpu_realize(DeviceState *dev, Error **errp) | |
392 | { | |
393 | CPUState *cs = CPU(dev); | |
c4e95030 AF |
394 | RISCVCPU *cpu = RISCV_CPU(dev); |
395 | CPURISCVState *env = &cpu->env; | |
dc5bd18f | 396 | RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); |
a8b37120 | 397 | int priv_version = 0; |
dc5bd18f MC |
398 | Error *local_err = NULL; |
399 | ||
400 | cpu_exec_realizefn(cs, &local_err); | |
401 | if (local_err != NULL) { | |
402 | error_propagate(errp, local_err); | |
403 | return; | |
404 | } | |
405 | ||
c4e95030 | 406 | if (cpu->cfg.priv_spec) { |
e3147506 AF |
407 | if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { |
408 | priv_version = PRIV_VERSION_1_11_0; | |
409 | } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { | |
c4e95030 | 410 | priv_version = PRIV_VERSION_1_10_0; |
c4e95030 AF |
411 | } else { |
412 | error_setg(errp, | |
413 | "Unsupported privilege spec version '%s'", | |
414 | cpu->cfg.priv_spec); | |
415 | return; | |
416 | } | |
417 | } | |
418 | ||
a8b37120 LZ |
419 | if (priv_version) { |
420 | set_priv_version(env, priv_version); | |
421 | } else if (!env->priv_ver) { | |
422 | set_priv_version(env, PRIV_VERSION_1_11_0); | |
423 | } | |
c4e95030 AF |
424 | |
425 | if (cpu->cfg.mmu) { | |
426 | set_feature(env, RISCV_FEATURE_MMU); | |
427 | } | |
428 | ||
429 | if (cpu->cfg.pmp) { | |
430 | set_feature(env, RISCV_FEATURE_PMP); | |
5da9514e HW |
431 | |
432 | /* | |
433 | * Enhanced PMP should only be available | |
434 | * on harts with PMP support | |
435 | */ | |
436 | if (cpu->cfg.epmp) { | |
437 | set_feature(env, RISCV_FEATURE_EPMP); | |
438 | } | |
c4e95030 AF |
439 | } |
440 | ||
73f6ed97 BM |
441 | set_resetvec(env, cpu->cfg.resetvec); |
442 | ||
e91a7227 RH |
443 | /* Validate that MISA_MXL is set properly. */ |
444 | switch (env->misa_mxl_max) { | |
445 | #ifdef TARGET_RISCV64 | |
446 | case MXL_RV64: | |
447 | break; | |
448 | #endif | |
449 | case MXL_RV32: | |
450 | break; | |
451 | default: | |
452 | g_assert_not_reached(); | |
453 | } | |
454 | assert(env->misa_mxl_max == env->misa_mxl); | |
455 | ||
456 | /* If only MISA_EXT is unset for misa, then set it from properties */ | |
457 | if (env->misa_ext == 0) { | |
458 | uint32_t ext = 0; | |
459 | ||
b55d7d34 AF |
460 | /* Do some ISA extension error checking */ |
461 | if (cpu->cfg.ext_i && cpu->cfg.ext_e) { | |
462 | error_setg(errp, | |
463 | "I and E extensions are incompatible"); | |
464 | return; | |
465 | } | |
466 | ||
bdddd446 AF |
467 | if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { |
468 | error_setg(errp, | |
469 | "Either I or E extension must be set"); | |
470 | return; | |
471 | } | |
472 | ||
b55d7d34 AF |
473 | if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & |
474 | cpu->cfg.ext_a & cpu->cfg.ext_f & | |
475 | cpu->cfg.ext_d)) { | |
476 | warn_report("Setting G will also set IMAFD"); | |
477 | cpu->cfg.ext_i = true; | |
478 | cpu->cfg.ext_m = true; | |
479 | cpu->cfg.ext_a = true; | |
480 | cpu->cfg.ext_f = true; | |
481 | cpu->cfg.ext_d = true; | |
482 | } | |
483 | ||
484 | /* Set the ISA extensions, checks should have happened above */ | |
485 | if (cpu->cfg.ext_i) { | |
e91a7227 | 486 | ext |= RVI; |
b55d7d34 AF |
487 | } |
488 | if (cpu->cfg.ext_e) { | |
e91a7227 | 489 | ext |= RVE; |
b55d7d34 AF |
490 | } |
491 | if (cpu->cfg.ext_m) { | |
e91a7227 | 492 | ext |= RVM; |
b55d7d34 AF |
493 | } |
494 | if (cpu->cfg.ext_a) { | |
e91a7227 | 495 | ext |= RVA; |
b55d7d34 AF |
496 | } |
497 | if (cpu->cfg.ext_f) { | |
e91a7227 | 498 | ext |= RVF; |
b55d7d34 AF |
499 | } |
500 | if (cpu->cfg.ext_d) { | |
e91a7227 | 501 | ext |= RVD; |
b55d7d34 AF |
502 | } |
503 | if (cpu->cfg.ext_c) { | |
e91a7227 | 504 | ext |= RVC; |
b55d7d34 AF |
505 | } |
506 | if (cpu->cfg.ext_s) { | |
e91a7227 | 507 | ext |= RVS; |
b55d7d34 AF |
508 | } |
509 | if (cpu->cfg.ext_u) { | |
e91a7227 | 510 | ext |= RVU; |
b55d7d34 | 511 | } |
c9eefe05 | 512 | if (cpu->cfg.ext_h) { |
e91a7227 | 513 | ext |= RVH; |
c9eefe05 | 514 | } |
6bf91617 | 515 | if (cpu->cfg.ext_v) { |
a8b37120 | 516 | int vext_version = VEXT_VERSION_0_07_1; |
e91a7227 | 517 | ext |= RVV; |
6bf91617 LZ |
518 | if (!is_power_of_2(cpu->cfg.vlen)) { |
519 | error_setg(errp, | |
520 | "Vector extension VLEN must be power of 2"); | |
521 | return; | |
522 | } | |
523 | if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { | |
524 | error_setg(errp, | |
525 | "Vector extension implementation only supports VLEN " | |
526 | "in the range [128, %d]", RV_VLEN_MAX); | |
527 | return; | |
528 | } | |
529 | if (!is_power_of_2(cpu->cfg.elen)) { | |
530 | error_setg(errp, | |
531 | "Vector extension ELEN must be power of 2"); | |
532 | return; | |
533 | } | |
534 | if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) { | |
535 | error_setg(errp, | |
536 | "Vector extension implementation only supports ELEN " | |
537 | "in the range [8, 64]"); | |
538 | return; | |
539 | } | |
540 | if (cpu->cfg.vext_spec) { | |
541 | if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) { | |
542 | vext_version = VEXT_VERSION_0_07_1; | |
543 | } else { | |
544 | error_setg(errp, | |
545 | "Unsupported vector spec version '%s'", | |
546 | cpu->cfg.vext_spec); | |
547 | return; | |
548 | } | |
549 | } else { | |
cba42d61 | 550 | qemu_log("vector version is not specified, " |
6bf91617 LZ |
551 | "use the default value v0.7.1\n"); |
552 | } | |
553 | set_vext_version(env, vext_version); | |
554 | } | |
b55d7d34 | 555 | |
e91a7227 | 556 | set_misa(env, env->misa_mxl, ext); |
b55d7d34 AF |
557 | } |
558 | ||
5371f5cd JW |
559 | riscv_cpu_register_gdb_regs_for_features(cs); |
560 | ||
dc5bd18f MC |
561 | qemu_init_vcpu(cs); |
562 | cpu_reset(cs); | |
563 | ||
564 | mcc->parent_realize(dev, errp); | |
565 | } | |
566 | ||
0f0b70ee AF |
567 | #ifndef CONFIG_USER_ONLY |
568 | static void riscv_cpu_set_irq(void *opaque, int irq, int level) | |
569 | { | |
570 | RISCVCPU *cpu = RISCV_CPU(opaque); | |
571 | ||
572 | switch (irq) { | |
573 | case IRQ_U_SOFT: | |
574 | case IRQ_S_SOFT: | |
575 | case IRQ_VS_SOFT: | |
576 | case IRQ_M_SOFT: | |
577 | case IRQ_U_TIMER: | |
578 | case IRQ_S_TIMER: | |
579 | case IRQ_VS_TIMER: | |
580 | case IRQ_M_TIMER: | |
581 | case IRQ_U_EXT: | |
582 | case IRQ_S_EXT: | |
583 | case IRQ_VS_EXT: | |
584 | case IRQ_M_EXT: | |
585 | riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); | |
586 | break; | |
587 | default: | |
588 | g_assert_not_reached(); | |
589 | } | |
590 | } | |
591 | #endif /* CONFIG_USER_ONLY */ | |
592 | ||
dc5bd18f MC |
593 | static void riscv_cpu_init(Object *obj) |
594 | { | |
dc5bd18f MC |
595 | RISCVCPU *cpu = RISCV_CPU(obj); |
596 | ||
7506ed90 | 597 | cpu_set_cpustate_pointers(cpu); |
0f0b70ee AF |
598 | |
599 | #ifndef CONFIG_USER_ONLY | |
600 | qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 12); | |
601 | #endif /* CONFIG_USER_ONLY */ | |
dc5bd18f MC |
602 | } |
603 | ||
c4e95030 | 604 | static Property riscv_cpu_properties[] = { |
9d3d60b7 | 605 | /* Defaults for standard extensions */ |
b55d7d34 AF |
606 | DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), |
607 | DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), | |
608 | DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true), | |
609 | DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), | |
610 | DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), | |
611 | DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), | |
612 | DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), | |
613 | DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), | |
614 | DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), | |
615 | DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), | |
9d3d60b7 AF |
616 | DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), |
617 | DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), | |
618 | DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), | |
619 | DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), | |
620 | DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), | |
621 | ||
622 | DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), | |
623 | ||
624 | /* These are experimental so mark with 'x-' */ | |
878dd0e9 PT |
625 | DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false), |
626 | DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false), | |
627 | DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false), | |
628 | DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false), | |
c9eefe05 | 629 | DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), |
6bf91617 | 630 | DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), |
6bf91617 LZ |
631 | DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), |
632 | DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), | |
633 | DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), | |
a44da25a | 634 | /* ePMP 0.9.3 */ |
5da9514e HW |
635 | DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), |
636 | ||
9b4c9b2b | 637 | DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), |
c4e95030 AF |
638 | DEFINE_PROP_END_OF_LIST(), |
639 | }; | |
640 | ||
edf64786 SP |
641 | static gchar *riscv_gdb_arch_name(CPUState *cs) |
642 | { | |
643 | RISCVCPU *cpu = RISCV_CPU(cs); | |
644 | CPURISCVState *env = &cpu->env; | |
645 | ||
db23e5d9 RH |
646 | switch (riscv_cpu_mxl(env)) { |
647 | case MXL_RV32: | |
edf64786 | 648 | return g_strdup("riscv:rv32"); |
db23e5d9 | 649 | case MXL_RV64: |
edf64786 | 650 | return g_strdup("riscv:rv64"); |
db23e5d9 RH |
651 | default: |
652 | g_assert_not_reached(); | |
edf64786 SP |
653 | } |
654 | } | |
655 | ||
b93777e1 BM |
656 | static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) |
657 | { | |
658 | RISCVCPU *cpu = RISCV_CPU(cs); | |
659 | ||
660 | if (strcmp(xmlname, "riscv-csr.xml") == 0) { | |
661 | return cpu->dyn_csr_xml; | |
662 | } | |
663 | ||
664 | return NULL; | |
665 | } | |
666 | ||
8b80bd28 PMD |
667 | #ifndef CONFIG_USER_ONLY |
668 | #include "hw/core/sysemu-cpu-ops.h" | |
669 | ||
670 | static const struct SysemuCPUOps riscv_sysemu_ops = { | |
08928c6d | 671 | .get_phys_page_debug = riscv_cpu_get_phys_page_debug, |
715e3c1a PMD |
672 | .write_elf64_note = riscv_cpu_write_elf64_note, |
673 | .write_elf32_note = riscv_cpu_write_elf32_note, | |
feece4d0 | 674 | .legacy_vmsd = &vmstate_riscv_cpu, |
8b80bd28 PMD |
675 | }; |
676 | #endif | |
677 | ||
78271684 CF |
678 | #include "hw/core/tcg-cpu-ops.h" |
679 | ||
11906557 | 680 | static const struct TCGCPUOps riscv_tcg_ops = { |
78271684 CF |
681 | .initialize = riscv_translate_init, |
682 | .synchronize_from_tb = riscv_cpu_synchronize_from_tb, | |
78271684 CF |
683 | .tlb_fill = riscv_cpu_tlb_fill, |
684 | ||
685 | #ifndef CONFIG_USER_ONLY | |
17b3c353 | 686 | .cpu_exec_interrupt = riscv_cpu_exec_interrupt, |
78271684 CF |
687 | .do_interrupt = riscv_cpu_do_interrupt, |
688 | .do_transaction_failed = riscv_cpu_do_transaction_failed, | |
689 | .do_unaligned_access = riscv_cpu_do_unaligned_access, | |
690 | #endif /* !CONFIG_USER_ONLY */ | |
691 | }; | |
692 | ||
dc5bd18f MC |
693 | static void riscv_cpu_class_init(ObjectClass *c, void *data) |
694 | { | |
695 | RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); | |
696 | CPUClass *cc = CPU_CLASS(c); | |
697 | DeviceClass *dc = DEVICE_CLASS(c); | |
698 | ||
41fbbba7 MZ |
699 | device_class_set_parent_realize(dc, riscv_cpu_realize, |
700 | &mcc->parent_realize); | |
dc5bd18f | 701 | |
781c67ca | 702 | device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset); |
dc5bd18f MC |
703 | |
704 | cc->class_by_name = riscv_cpu_class_by_name; | |
705 | cc->has_work = riscv_cpu_has_work; | |
dc5bd18f MC |
706 | cc->dump_state = riscv_cpu_dump_state; |
707 | cc->set_pc = riscv_cpu_set_pc; | |
dc5bd18f MC |
708 | cc->gdb_read_register = riscv_cpu_gdb_read_register; |
709 | cc->gdb_write_register = riscv_cpu_gdb_write_register; | |
5371f5cd JW |
710 | cc->gdb_num_core_regs = 33; |
711 | #if defined(TARGET_RISCV32) | |
712 | cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; | |
713 | #elif defined(TARGET_RISCV64) | |
714 | cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; | |
715 | #endif | |
dc5bd18f MC |
716 | cc->gdb_stop_before_watchpoint = true; |
717 | cc->disas_set_info = riscv_cpu_disas_set_info; | |
8a4ca3c1 | 718 | #ifndef CONFIG_USER_ONLY |
8b80bd28 | 719 | cc->sysemu_ops = &riscv_sysemu_ops; |
dc5bd18f | 720 | #endif |
edf64786 | 721 | cc->gdb_arch_name = riscv_gdb_arch_name; |
b93777e1 | 722 | cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; |
78271684 | 723 | cc->tcg_ops = &riscv_tcg_ops; |
6a3d2e7c | 724 | |
4f67d30b | 725 | device_class_set_props(dc, riscv_cpu_properties); |
dc5bd18f MC |
726 | } |
727 | ||
dc5bd18f MC |
728 | char *riscv_isa_string(RISCVCPU *cpu) |
729 | { | |
730 | int i; | |
d1fd31f8 MC |
731 | const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1; |
732 | char *isa_str = g_new(char, maxlen); | |
733 | char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); | |
dc5bd18f | 734 | for (i = 0; i < sizeof(riscv_exts); i++) { |
e91a7227 | 735 | if (cpu->env.misa_ext & RV(riscv_exts[i])) { |
d1fd31f8 | 736 | *p++ = qemu_tolower(riscv_exts[i]); |
dc5bd18f MC |
737 | } |
738 | } | |
d1fd31f8 MC |
739 | *p = '\0'; |
740 | return isa_str; | |
dc5bd18f MC |
741 | } |
742 | ||
eab15862 | 743 | static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) |
dc5bd18f | 744 | { |
eab15862 MC |
745 | ObjectClass *class_a = (ObjectClass *)a; |
746 | ObjectClass *class_b = (ObjectClass *)b; | |
747 | const char *name_a, *name_b; | |
dc5bd18f | 748 | |
eab15862 MC |
749 | name_a = object_class_get_name(class_a); |
750 | name_b = object_class_get_name(class_b); | |
751 | return strcmp(name_a, name_b); | |
dc5bd18f MC |
752 | } |
753 | ||
eab15862 | 754 | static void riscv_cpu_list_entry(gpointer data, gpointer user_data) |
dc5bd18f | 755 | { |
eab15862 MC |
756 | const char *typename = object_class_get_name(OBJECT_CLASS(data)); |
757 | int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); | |
dc5bd18f | 758 | |
0442428a | 759 | qemu_printf("%.*s\n", len, typename); |
eab15862 | 760 | } |
dc5bd18f | 761 | |
0442428a | 762 | void riscv_cpu_list(void) |
eab15862 | 763 | { |
eab15862 MC |
764 | GSList *list; |
765 | ||
766 | list = object_class_get_list(TYPE_RISCV_CPU, false); | |
767 | list = g_slist_sort(list, riscv_cpu_list_compare); | |
0442428a | 768 | g_slist_foreach(list, riscv_cpu_list_entry, NULL); |
eab15862 | 769 | g_slist_free(list); |
dc5bd18f MC |
770 | } |
771 | ||
eab15862 MC |
772 | #define DEFINE_CPU(type_name, initfn) \ |
773 | { \ | |
774 | .name = type_name, \ | |
775 | .parent = TYPE_RISCV_CPU, \ | |
776 | .instance_init = initfn \ | |
777 | } | |
778 | ||
779 | static const TypeInfo riscv_cpu_type_infos[] = { | |
780 | { | |
781 | .name = TYPE_RISCV_CPU, | |
782 | .parent = TYPE_CPU, | |
783 | .instance_size = sizeof(RISCVCPU), | |
5de5b99b | 784 | .instance_align = __alignof__(RISCVCPU), |
eab15862 MC |
785 | .instance_init = riscv_cpu_init, |
786 | .abstract = true, | |
787 | .class_size = sizeof(RISCVCPUClass), | |
788 | .class_init = riscv_cpu_class_init, | |
789 | }, | |
790 | DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), | |
791 | #if defined(TARGET_RISCV32) | |
094b072c | 792 | DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), |
e8905c6c | 793 | DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), |
114baaca | 794 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), |
2fdd2c09 | 795 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), |
114baaca | 796 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), |
eab15862 | 797 | #elif defined(TARGET_RISCV64) |
094b072c | 798 | DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), |
114baaca AF |
799 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), |
800 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), | |
6ddc7069 | 801 | DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), |
eab15862 MC |
802 | #endif |
803 | }; | |
804 | ||
805 | DEFINE_TYPES(riscv_cpu_type_infos) |