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dc5bd18f MC |
1 | /* |
2 | * QEMU RISC-V CPU | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
0442428a | 21 | #include "qemu/qemu-print.h" |
856dfd8a | 22 | #include "qemu/ctype.h" |
dc5bd18f MC |
23 | #include "qemu/log.h" |
24 | #include "cpu.h" | |
95bd8daa | 25 | #include "cpu_vendorid.h" |
14664483 | 26 | #include "pmu.h" |
f7697f0e | 27 | #include "internals.h" |
43888c2f | 28 | #include "time_helper.h" |
dc5bd18f MC |
29 | #include "exec/exec-all.h" |
30 | #include "qapi/error.h" | |
b55d7d34 | 31 | #include "qemu/error-report.h" |
c4e95030 | 32 | #include "hw/qdev-properties.h" |
dc5bd18f | 33 | #include "migration/vmstate.h" |
135b03cb | 34 | #include "fpu/softfloat-helpers.h" |
ad40be27 YJ |
35 | #include "sysemu/kvm.h" |
36 | #include "kvm_riscv.h" | |
0489d5bd | 37 | #include "tcg/tcg.h" |
dc5bd18f MC |
38 | |
39 | /* RISC-V CPU definitions */ | |
40 | ||
9951ba94 FC |
41 | #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ |
42 | (QEMU_VERSION_MINOR << 8) | \ | |
43 | (QEMU_VERSION_MICRO)) | |
075eeda9 | 44 | #define RISCV_CPU_MIMPID RISCV_CPU_MARCHID |
9951ba94 | 45 | |
0e2c3770 | 46 | static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; |
dc5bd18f | 47 | |
a775398b AP |
48 | struct isa_ext_data { |
49 | const char *name; | |
9a1f054d AP |
50 | bool multi_letter; |
51 | int min_version; | |
52 | int ext_enable_offset; | |
a775398b AP |
53 | }; |
54 | ||
9a1f054d AP |
55 | #define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \ |
56 | {#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} | |
57 | ||
58 | /** | |
59 | * Here are the ordering rules of extension naming defined by RISC-V | |
60 | * specification : | |
61 | * 1. All extensions should be separated from other multi-letter extensions | |
62 | * by an underscore. | |
63 | * 2. The first letter following the 'Z' conventionally indicates the most | |
64 | * closely related alphabetical extension category, IMAFDQLCBKJTPVH. | |
65 | * If multiple 'Z' extensions are named, they should be ordered first | |
66 | * by category, then alphabetically within a category. | |
67 | * 3. Standard supervisor-level extensions (starts with 'S') should be | |
68 | * listed after standard unprivileged extensions. If multiple | |
69 | * supervisor-level extensions are listed, they should be ordered | |
70 | * alphabetically. | |
71 | * 4. Non-standard extensions (starts with 'X') must be listed after all | |
72 | * standard extensions. They must be separated from other multi-letter | |
73 | * extensions by an underscore. | |
74 | */ | |
75 | static const struct isa_ext_data isa_edata_arr[] = { | |
76 | ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h), | |
0e660142 | 77 | ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_10_0, ext_v), |
a939c500 | 78 | ISA_EXT_DATA_ENTRY(zicboz, true, PRIV_VERSION_1_12_0, ext_icboz), |
b8e1f32c | 79 | ISA_EXT_DATA_ENTRY(zicond, true, PRIV_VERSION_1_12_0, ext_zicond), |
9a1f054d AP |
80 | ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr), |
81 | ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei), | |
4696f0ab | 82 | ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause), |
260b594d | 83 | ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs), |
7ad2878c | 84 | ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_11_0, ext_zfh), |
9a1f054d AP |
85 | ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin), |
86 | ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx), | |
87 | ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx), | |
88 | ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba), | |
89 | ISA_EXT_DATA_ENTRY(zbb, true, PRIV_VERSION_1_12_0, ext_zbb), | |
90 | ISA_EXT_DATA_ENTRY(zbc, true, PRIV_VERSION_1_12_0, ext_zbc), | |
91 | ISA_EXT_DATA_ENTRY(zbkb, true, PRIV_VERSION_1_12_0, ext_zbkb), | |
92 | ISA_EXT_DATA_ENTRY(zbkc, true, PRIV_VERSION_1_12_0, ext_zbkc), | |
93 | ISA_EXT_DATA_ENTRY(zbkx, true, PRIV_VERSION_1_12_0, ext_zbkx), | |
94 | ISA_EXT_DATA_ENTRY(zbs, true, PRIV_VERSION_1_12_0, ext_zbs), | |
95 | ISA_EXT_DATA_ENTRY(zk, true, PRIV_VERSION_1_12_0, ext_zk), | |
96 | ISA_EXT_DATA_ENTRY(zkn, true, PRIV_VERSION_1_12_0, ext_zkn), | |
97 | ISA_EXT_DATA_ENTRY(zknd, true, PRIV_VERSION_1_12_0, ext_zknd), | |
98 | ISA_EXT_DATA_ENTRY(zkne, true, PRIV_VERSION_1_12_0, ext_zkne), | |
99 | ISA_EXT_DATA_ENTRY(zknh, true, PRIV_VERSION_1_12_0, ext_zknh), | |
100 | ISA_EXT_DATA_ENTRY(zkr, true, PRIV_VERSION_1_12_0, ext_zkr), | |
101 | ISA_EXT_DATA_ENTRY(zks, true, PRIV_VERSION_1_12_0, ext_zks), | |
102 | ISA_EXT_DATA_ENTRY(zksed, true, PRIV_VERSION_1_12_0, ext_zksed), | |
103 | ISA_EXT_DATA_ENTRY(zksh, true, PRIV_VERSION_1_12_0, ext_zksh), | |
104 | ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt), | |
105 | ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f), | |
106 | ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f), | |
058d9d30 WL |
107 | ISA_EXT_DATA_ENTRY(zve64d, true, PRIV_VERSION_1_12_0, ext_zve64d), |
108 | ISA_EXT_DATA_ENTRY(zvfh, true, PRIV_VERSION_1_12_0, ext_zvfh), | |
109 | ISA_EXT_DATA_ENTRY(zvfhmin, true, PRIV_VERSION_1_12_0, ext_zvfhmin), | |
9a1f054d AP |
110 | ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), |
111 | ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), | |
dc9acc9c AP |
112 | ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia), |
113 | ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia), | |
14664483 | 114 | ISA_EXT_DATA_ENTRY(sscofpmf, true, PRIV_VERSION_1_12_0, ext_sscofpmf), |
43888c2f | 115 | ISA_EXT_DATA_ENTRY(sstc, true, PRIV_VERSION_1_12_0, ext_sstc), |
62108f05 | 116 | ISA_EXT_DATA_ENTRY(svadu, true, PRIV_VERSION_1_12_0, ext_svadu), |
9a1f054d AP |
117 | ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), |
118 | ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), | |
119 | ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), | |
c9410a68 | 120 | ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba), |
426c0491 | 121 | ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb), |
fa134585 | 122 | ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs), |
49a7f3aa | 123 | ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), |
32909338 | 124 | ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov), |
d4d90115 | 125 | ISA_EXT_DATA_ENTRY(xtheadfmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadfmemidx), |
578086ba | 126 | ISA_EXT_DATA_ENTRY(xtheadfmv, true, PRIV_VERSION_1_11_0, ext_xtheadfmv), |
b8a5832b | 127 | ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac), |
45f9df86 | 128 | ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadmemidx), |
af99aa72 | 129 | ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xtheadmempair), |
134c3ffa | 130 | ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync), |
e0dea2f5 | 131 | ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), |
9a1f054d AP |
132 | }; |
133 | ||
134 | static bool isa_ext_is_enabled(RISCVCPU *cpu, | |
135 | const struct isa_ext_data *edata) | |
136 | { | |
137 | bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; | |
138 | ||
139 | return *ext_enabled; | |
140 | } | |
141 | ||
142 | static void isa_ext_update_enabled(RISCVCPU *cpu, | |
143 | const struct isa_ext_data *edata, bool en) | |
144 | { | |
145 | bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; | |
146 | ||
147 | *ext_enabled = en; | |
148 | } | |
149 | ||
dc5bd18f | 150 | const char * const riscv_int_regnames[] = { |
a9f37afa AP |
151 | "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", |
152 | "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", | |
153 | "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", | |
154 | "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", | |
155 | "x28/t3", "x29/t4", "x30/t5", "x31/t6" | |
dc5bd18f MC |
156 | }; |
157 | ||
2b547084 FP |
158 | const char * const riscv_int_regnamesh[] = { |
159 | "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", | |
160 | "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", | |
161 | "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", | |
162 | "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", | |
163 | "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", | |
164 | "x30h/t5h", "x31h/t6h" | |
165 | }; | |
166 | ||
dc5bd18f | 167 | const char * const riscv_fpr_regnames[] = { |
a9f37afa AP |
168 | "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", |
169 | "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", | |
170 | "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", | |
171 | "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", | |
172 | "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", | |
173 | "f30/ft10", "f31/ft11" | |
dc5bd18f MC |
174 | }; |
175 | ||
9a575d33 | 176 | static const char * const riscv_excp_names[] = { |
dc5bd18f MC |
177 | "misaligned_fetch", |
178 | "fault_fetch", | |
179 | "illegal_instruction", | |
180 | "breakpoint", | |
181 | "misaligned_load", | |
182 | "fault_load", | |
183 | "misaligned_store", | |
184 | "fault_store", | |
185 | "user_ecall", | |
186 | "supervisor_ecall", | |
187 | "hypervisor_ecall", | |
188 | "machine_ecall", | |
189 | "exec_page_fault", | |
190 | "load_page_fault", | |
191 | "reserved", | |
fd990e86 | 192 | "store_page_fault", |
ab67a1d0 AF |
193 | "reserved", |
194 | "reserved", | |
195 | "reserved", | |
196 | "reserved", | |
197 | "guest_exec_page_fault", | |
198 | "guest_load_page_fault", | |
199 | "reserved", | |
fd990e86 | 200 | "guest_store_page_fault", |
dc5bd18f MC |
201 | }; |
202 | ||
9a575d33 | 203 | static const char * const riscv_intr_names[] = { |
dc5bd18f MC |
204 | "u_software", |
205 | "s_software", | |
205377f8 | 206 | "vs_software", |
dc5bd18f MC |
207 | "m_software", |
208 | "u_timer", | |
209 | "s_timer", | |
205377f8 | 210 | "vs_timer", |
dc5bd18f MC |
211 | "m_timer", |
212 | "u_external", | |
6cfcf775 | 213 | "s_external", |
205377f8 | 214 | "vs_external", |
dc5bd18f | 215 | "m_external", |
426f0348 MC |
216 | "reserved", |
217 | "reserved", | |
218 | "reserved", | |
219 | "reserved" | |
dc5bd18f MC |
220 | }; |
221 | ||
26b2bc58 AF |
222 | static void register_cpu_props(DeviceState *dev); |
223 | ||
c51a3f5d YJ |
224 | const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) |
225 | { | |
226 | if (async) { | |
227 | return (cause < ARRAY_SIZE(riscv_intr_names)) ? | |
228 | riscv_intr_names[cause] : "(unknown)"; | |
229 | } else { | |
230 | return (cause < ARRAY_SIZE(riscv_excp_names)) ? | |
231 | riscv_excp_names[cause] : "(unknown)"; | |
232 | } | |
233 | } | |
234 | ||
e91a7227 | 235 | static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) |
dc5bd18f | 236 | { |
e91a7227 RH |
237 | env->misa_mxl_max = env->misa_mxl = mxl; |
238 | env->misa_ext_mask = env->misa_ext = ext; | |
dc5bd18f MC |
239 | } |
240 | ||
c9a73910 | 241 | static void set_priv_version(CPURISCVState *env, int priv_ver) |
dc5bd18f | 242 | { |
dc5bd18f MC |
243 | env->priv_ver = priv_ver; |
244 | } | |
245 | ||
32931383 LZ |
246 | static void set_vext_version(CPURISCVState *env, int vext_ver) |
247 | { | |
248 | env->vext_ver = vext_ver; | |
249 | } | |
250 | ||
dc5bd18f MC |
251 | static void riscv_any_cpu_init(Object *obj) |
252 | { | |
253 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
3820602f | 254 | #if defined(TARGET_RISCV32) |
e91a7227 | 255 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); |
3820602f | 256 | #elif defined(TARGET_RISCV64) |
e91a7227 | 257 | set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); |
3820602f | 258 | #endif |
7100fe6c | 259 | set_priv_version(env, PRIV_VERSION_1_12_0); |
26b2bc58 | 260 | register_cpu_props(DEVICE(obj)); |
dc5bd18f MC |
261 | } |
262 | ||
094b072c AF |
263 | #if defined(TARGET_RISCV64) |
264 | static void rv64_base_cpu_init(Object *obj) | |
8903bf6e AF |
265 | { |
266 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
b55d7d34 | 267 | /* We set this in the realise function */ |
e91a7227 | 268 | set_misa(env, MXL_RV64, 0); |
26b2bc58 | 269 | register_cpu_props(DEVICE(obj)); |
18800095 AP |
270 | /* Set latest version of privileged specification */ |
271 | set_priv_version(env, PRIV_VERSION_1_12_0); | |
8903bf6e AF |
272 | } |
273 | ||
114baaca | 274 | static void rv64_sifive_u_cpu_init(Object *obj) |
dc5bd18f MC |
275 | { |
276 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
e91a7227 | 277 | set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); |
c66ffcd5 | 278 | register_cpu_props(DEVICE(obj)); |
c9a73910 | 279 | set_priv_version(env, PRIV_VERSION_1_10_0); |
dc5bd18f MC |
280 | } |
281 | ||
114baaca | 282 | static void rv64_sifive_e_cpu_init(Object *obj) |
36b80ad9 AF |
283 | { |
284 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
26b2bc58 AF |
285 | RISCVCPU *cpu = RISCV_CPU(obj); |
286 | ||
e91a7227 | 287 | set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); |
c66ffcd5 | 288 | register_cpu_props(DEVICE(obj)); |
36b80ad9 | 289 | set_priv_version(env, PRIV_VERSION_1_10_0); |
26b2bc58 | 290 | cpu->cfg.mmu = false; |
36b80ad9 | 291 | } |
332dab68 | 292 | |
95bd8daa CM |
293 | static void rv64_thead_c906_cpu_init(Object *obj) |
294 | { | |
295 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
296 | RISCVCPU *cpu = RISCV_CPU(obj); | |
297 | ||
298 | set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); | |
299 | set_priv_version(env, PRIV_VERSION_1_11_0); | |
300 | ||
301 | cpu->cfg.ext_g = true; | |
302 | cpu->cfg.ext_c = true; | |
303 | cpu->cfg.ext_u = true; | |
304 | cpu->cfg.ext_s = true; | |
305 | cpu->cfg.ext_icsr = true; | |
306 | cpu->cfg.ext_zfh = true; | |
307 | cpu->cfg.mmu = true; | |
308 | cpu->cfg.ext_xtheadba = true; | |
309 | cpu->cfg.ext_xtheadbb = true; | |
310 | cpu->cfg.ext_xtheadbs = true; | |
311 | cpu->cfg.ext_xtheadcmo = true; | |
312 | cpu->cfg.ext_xtheadcondmov = true; | |
313 | cpu->cfg.ext_xtheadfmemidx = true; | |
314 | cpu->cfg.ext_xtheadmac = true; | |
315 | cpu->cfg.ext_xtheadmemidx = true; | |
316 | cpu->cfg.ext_xtheadmempair = true; | |
317 | cpu->cfg.ext_xtheadsync = true; | |
318 | ||
319 | cpu->cfg.mvendorid = THEAD_VENDOR_ID; | |
320 | } | |
321 | ||
332dab68 FP |
322 | static void rv128_base_cpu_init(Object *obj) |
323 | { | |
324 | if (qemu_tcg_mttcg_enabled()) { | |
325 | /* Missing 128-bit aligned atomics */ | |
326 | error_report("128-bit RISC-V currently does not work with Multi " | |
327 | "Threaded TCG. Please use: -accel tcg,thread=single"); | |
328 | exit(EXIT_FAILURE); | |
329 | } | |
330 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
331 | /* We set this in the realise function */ | |
332 | set_misa(env, MXL_RV128, 0); | |
26b2bc58 | 333 | register_cpu_props(DEVICE(obj)); |
18800095 AP |
334 | /* Set latest version of privileged specification */ |
335 | set_priv_version(env, PRIV_VERSION_1_12_0); | |
332dab68 | 336 | } |
114baaca | 337 | #else |
094b072c AF |
338 | static void rv32_base_cpu_init(Object *obj) |
339 | { | |
340 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
341 | /* We set this in the realise function */ | |
e91a7227 | 342 | set_misa(env, MXL_RV32, 0); |
26b2bc58 | 343 | register_cpu_props(DEVICE(obj)); |
18800095 AP |
344 | /* Set latest version of privileged specification */ |
345 | set_priv_version(env, PRIV_VERSION_1_12_0); | |
094b072c AF |
346 | } |
347 | ||
114baaca AF |
348 | static void rv32_sifive_u_cpu_init(Object *obj) |
349 | { | |
350 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
e91a7227 | 351 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); |
c66ffcd5 | 352 | register_cpu_props(DEVICE(obj)); |
114baaca AF |
353 | set_priv_version(env, PRIV_VERSION_1_10_0); |
354 | } | |
36b80ad9 | 355 | |
114baaca AF |
356 | static void rv32_sifive_e_cpu_init(Object *obj) |
357 | { | |
358 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
26b2bc58 AF |
359 | RISCVCPU *cpu = RISCV_CPU(obj); |
360 | ||
e91a7227 | 361 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); |
c66ffcd5 | 362 | register_cpu_props(DEVICE(obj)); |
114baaca | 363 | set_priv_version(env, PRIV_VERSION_1_10_0); |
26b2bc58 | 364 | cpu->cfg.mmu = false; |
114baaca | 365 | } |
d8e72bd1 | 366 | |
e8905c6c | 367 | static void rv32_ibex_cpu_init(Object *obj) |
dc5bd18f MC |
368 | { |
369 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
26b2bc58 AF |
370 | RISCVCPU *cpu = RISCV_CPU(obj); |
371 | ||
e91a7227 | 372 | set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); |
c66ffcd5 | 373 | register_cpu_props(DEVICE(obj)); |
be2265c7 | 374 | set_priv_version(env, PRIV_VERSION_1_11_0); |
26b2bc58 AF |
375 | cpu->cfg.mmu = false; |
376 | cpu->cfg.epmp = true; | |
dc5bd18f MC |
377 | } |
378 | ||
2fdd2c09 | 379 | static void rv32_imafcu_nommu_cpu_init(Object *obj) |
d784733b CW |
380 | { |
381 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
26b2bc58 AF |
382 | RISCVCPU *cpu = RISCV_CPU(obj); |
383 | ||
e91a7227 | 384 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); |
c66ffcd5 | 385 | register_cpu_props(DEVICE(obj)); |
d784733b | 386 | set_priv_version(env, PRIV_VERSION_1_10_0); |
26b2bc58 | 387 | cpu->cfg.mmu = false; |
d784733b | 388 | } |
eab15862 | 389 | #endif |
dc5bd18f | 390 | |
10f1ca27 YJ |
391 | #if defined(CONFIG_KVM) |
392 | static void riscv_host_cpu_init(Object *obj) | |
393 | { | |
394 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
395 | #if defined(TARGET_RISCV32) | |
396 | set_misa(env, MXL_RV32, 0); | |
397 | #elif defined(TARGET_RISCV64) | |
398 | set_misa(env, MXL_RV64, 0); | |
399 | #endif | |
26b2bc58 | 400 | register_cpu_props(DEVICE(obj)); |
10f1ca27 YJ |
401 | } |
402 | #endif | |
403 | ||
dc5bd18f MC |
404 | static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) |
405 | { | |
406 | ObjectClass *oc; | |
407 | char *typename; | |
408 | char **cpuname; | |
409 | ||
410 | cpuname = g_strsplit(cpu_model, ",", 1); | |
411 | typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); | |
412 | oc = object_class_by_name(typename); | |
413 | g_strfreev(cpuname); | |
414 | g_free(typename); | |
415 | if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || | |
416 | object_class_is_abstract(oc)) { | |
417 | return NULL; | |
418 | } | |
419 | return oc; | |
420 | } | |
421 | ||
90c84c56 | 422 | static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) |
dc5bd18f MC |
423 | { |
424 | RISCVCPU *cpu = RISCV_CPU(cs); | |
425 | CPURISCVState *env = &cpu->env; | |
426 | int i; | |
427 | ||
df30e652 AF |
428 | #if !defined(CONFIG_USER_ONLY) |
429 | if (riscv_has_ext(env, RVH)) { | |
430 | qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); | |
431 | } | |
432 | #endif | |
90c84c56 | 433 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); |
dc5bd18f | 434 | #ifndef CONFIG_USER_ONLY |
665b90d8 RH |
435 | { |
436 | static const int dump_csrs[] = { | |
437 | CSR_MHARTID, | |
438 | CSR_MSTATUS, | |
439 | CSR_MSTATUSH, | |
bc7dca13 BM |
440 | /* |
441 | * CSR_SSTATUS is intentionally omitted here as its value | |
442 | * can be figured out by looking at CSR_MSTATUS | |
443 | */ | |
665b90d8 RH |
444 | CSR_HSTATUS, |
445 | CSR_VSSTATUS, | |
446 | CSR_MIP, | |
447 | CSR_MIE, | |
448 | CSR_MIDELEG, | |
449 | CSR_HIDELEG, | |
450 | CSR_MEDELEG, | |
451 | CSR_HEDELEG, | |
452 | CSR_MTVEC, | |
453 | CSR_STVEC, | |
454 | CSR_VSTVEC, | |
455 | CSR_MEPC, | |
456 | CSR_SEPC, | |
457 | CSR_VSEPC, | |
458 | CSR_MCAUSE, | |
459 | CSR_SCAUSE, | |
460 | CSR_VSCAUSE, | |
461 | CSR_MTVAL, | |
462 | CSR_STVAL, | |
463 | CSR_HTVAL, | |
464 | CSR_MTVAL2, | |
465 | CSR_MSCRATCH, | |
466 | CSR_SSCRATCH, | |
467 | CSR_SATP, | |
bd5594ca AB |
468 | CSR_MMTE, |
469 | CSR_UPMBASE, | |
470 | CSR_UPMMASK, | |
471 | CSR_SPMBASE, | |
472 | CSR_SPMMASK, | |
473 | CSR_MPMBASE, | |
474 | CSR_MPMMASK, | |
665b90d8 RH |
475 | }; |
476 | ||
477 | for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { | |
478 | int csrno = dump_csrs[i]; | |
479 | target_ulong val = 0; | |
480 | RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); | |
481 | ||
482 | /* | |
483 | * Rely on the smode, hmode, etc, predicates within csr.c | |
484 | * to do the filtering of the registers that are present. | |
485 | */ | |
486 | if (res == RISCV_EXCP_NONE) { | |
487 | qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", | |
488 | csr_ops[csrno].name, val); | |
489 | } | |
490 | } | |
df30e652 | 491 | } |
dc5bd18f MC |
492 | #endif |
493 | ||
494 | for (i = 0; i < 32; i++) { | |
e573a7f3 | 495 | qemu_fprintf(f, " %-8s " TARGET_FMT_lx, |
90c84c56 | 496 | riscv_int_regnames[i], env->gpr[i]); |
dc5bd18f | 497 | if ((i & 3) == 3) { |
90c84c56 | 498 | qemu_fprintf(f, "\n"); |
dc5bd18f MC |
499 | } |
500 | } | |
86ea1880 RH |
501 | if (flags & CPU_DUMP_FPU) { |
502 | for (i = 0; i < 32; i++) { | |
e573a7f3 | 503 | qemu_fprintf(f, " %-8s %016" PRIx64, |
90c84c56 | 504 | riscv_fpr_regnames[i], env->fpr[i]); |
86ea1880 | 505 | if ((i & 3) == 3) { |
90c84c56 | 506 | qemu_fprintf(f, "\n"); |
86ea1880 | 507 | } |
dc5bd18f MC |
508 | } |
509 | } | |
510 | } | |
511 | ||
512 | static void riscv_cpu_set_pc(CPUState *cs, vaddr value) | |
513 | { | |
514 | RISCVCPU *cpu = RISCV_CPU(cs); | |
515 | CPURISCVState *env = &cpu->env; | |
bf9e776e LZ |
516 | |
517 | if (env->xl == MXL_RV32) { | |
518 | env->pc = (int32_t)value; | |
519 | } else { | |
520 | env->pc = value; | |
521 | } | |
dc5bd18f MC |
522 | } |
523 | ||
e4fdf9df RH |
524 | static vaddr riscv_cpu_get_pc(CPUState *cs) |
525 | { | |
526 | RISCVCPU *cpu = RISCV_CPU(cs); | |
527 | CPURISCVState *env = &cpu->env; | |
528 | ||
529 | /* Match cpu_get_tb_cpu_state. */ | |
530 | if (env->xl == MXL_RV32) { | |
531 | return env->pc & UINT32_MAX; | |
532 | } | |
533 | return env->pc; | |
534 | } | |
535 | ||
04a37d4c RH |
536 | static void riscv_cpu_synchronize_from_tb(CPUState *cs, |
537 | const TranslationBlock *tb) | |
dc5bd18f MC |
538 | { |
539 | RISCVCPU *cpu = RISCV_CPU(cs); | |
540 | CPURISCVState *env = &cpu->env; | |
bf9e776e LZ |
541 | RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); |
542 | ||
0489d5bd AJ |
543 | tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); |
544 | ||
bf9e776e | 545 | if (xl == MXL_RV32) { |
0489d5bd | 546 | env->pc = (int32_t) tb->pc; |
bf9e776e | 547 | } else { |
0489d5bd | 548 | env->pc = tb->pc; |
bf9e776e | 549 | } |
dc5bd18f MC |
550 | } |
551 | ||
552 | static bool riscv_cpu_has_work(CPUState *cs) | |
553 | { | |
554 | #ifndef CONFIG_USER_ONLY | |
555 | RISCVCPU *cpu = RISCV_CPU(cs); | |
556 | CPURISCVState *env = &cpu->env; | |
557 | /* | |
558 | * Definition of the WFI instruction requires it to ignore the privilege | |
559 | * mode and delegation registers, but respect individual enables | |
560 | */ | |
8f42415f | 561 | return riscv_cpu_all_pending(env) != 0; |
dc5bd18f MC |
562 | #else |
563 | return true; | |
564 | #endif | |
565 | } | |
566 | ||
ad1e84f5 RH |
567 | static void riscv_restore_state_to_opc(CPUState *cs, |
568 | const TranslationBlock *tb, | |
569 | const uint64_t *data) | |
dc5bd18f | 570 | { |
ad1e84f5 RH |
571 | RISCVCPU *cpu = RISCV_CPU(cs); |
572 | CPURISCVState *env = &cpu->env; | |
bf9e776e | 573 | RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); |
ad1e84f5 | 574 | |
bf9e776e LZ |
575 | if (xl == MXL_RV32) { |
576 | env->pc = (int32_t)data[0]; | |
577 | } else { | |
578 | env->pc = data[0]; | |
579 | } | |
62cf0245 | 580 | env->bins = data[1]; |
dc5bd18f MC |
581 | } |
582 | ||
4fa485a7 | 583 | static void riscv_cpu_reset_hold(Object *obj) |
dc5bd18f | 584 | { |
43dc93af AP |
585 | #ifndef CONFIG_USER_ONLY |
586 | uint8_t iprio; | |
587 | int i, irq, rdzero; | |
588 | #endif | |
4fa485a7 | 589 | CPUState *cs = CPU(obj); |
dc5bd18f MC |
590 | RISCVCPU *cpu = RISCV_CPU(cs); |
591 | RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); | |
592 | CPURISCVState *env = &cpu->env; | |
593 | ||
4fa485a7 PM |
594 | if (mcc->parent_phases.hold) { |
595 | mcc->parent_phases.hold(obj); | |
596 | } | |
dc5bd18f | 597 | #ifndef CONFIG_USER_ONLY |
e91a7227 | 598 | env->misa_mxl = env->misa_mxl_max; |
dc5bd18f MC |
599 | env->priv = PRV_M; |
600 | env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); | |
92371bd9 RH |
601 | if (env->misa_mxl > MXL_RV32) { |
602 | /* | |
603 | * The reset status of SXL/UXL is undefined, but mstatus is WARL | |
604 | * and we must ensure that the value after init is valid for read. | |
605 | */ | |
606 | env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); | |
607 | env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); | |
5a2ae235 LZ |
608 | if (riscv_has_ext(env, RVH)) { |
609 | env->vsstatus = set_field(env->vsstatus, | |
610 | MSTATUS64_SXL, env->misa_mxl); | |
611 | env->vsstatus = set_field(env->vsstatus, | |
612 | MSTATUS64_UXL, env->misa_mxl); | |
613 | env->mstatus_hs = set_field(env->mstatus_hs, | |
614 | MSTATUS64_SXL, env->misa_mxl); | |
615 | env->mstatus_hs = set_field(env->mstatus_hs, | |
616 | MSTATUS64_UXL, env->misa_mxl); | |
617 | } | |
92371bd9 | 618 | } |
dc5bd18f | 619 | env->mcause = 0; |
881df35d | 620 | env->miclaim = MIP_SGEIP; |
dc5bd18f | 621 | env->pc = env->resetvec; |
62cf0245 | 622 | env->bins = 0; |
ec352d0c | 623 | env->two_stage_lookup = false; |
43dc93af | 624 | |
0af3f115 WL |
625 | env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) | |
626 | (cpu->cfg.ext_svadu ? MENVCFG_HADE : 0); | |
627 | env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) | | |
628 | (cpu->cfg.ext_svadu ? HENVCFG_HADE : 0); | |
7a6613da | 629 | |
43dc93af AP |
630 | /* Initialized default priorities of local interrupts. */ |
631 | for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { | |
632 | iprio = riscv_cpu_default_priority(i); | |
633 | env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio; | |
634 | env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio; | |
635 | env->hviprio[i] = 0; | |
636 | } | |
637 | i = 0; | |
638 | while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) { | |
639 | if (!rdzero) { | |
640 | env->hviprio[irq] = env->miprio[irq]; | |
641 | } | |
642 | i++; | |
643 | } | |
4bbe8033 AB |
644 | /* mmte is supposed to have pm.current hardwired to 1 */ |
645 | env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); | |
dc5bd18f | 646 | #endif |
440544e1 | 647 | env->xl = riscv_cpu_mxl(env); |
40bfa5f6 | 648 | riscv_cpu_update_mask(env); |
330d2ae3 | 649 | cs->exception_index = RISCV_EXCP_NONE; |
c13b169f | 650 | env->load_res = -1; |
dc5bd18f | 651 | set_default_nan_mode(1, &env->fp_status); |
ad40be27 YJ |
652 | |
653 | #ifndef CONFIG_USER_ONLY | |
cdfb2905 | 654 | if (cpu->cfg.debug) { |
b6092544 BM |
655 | riscv_trigger_init(env); |
656 | } | |
657 | ||
ad40be27 YJ |
658 | if (kvm_enabled()) { |
659 | kvm_riscv_reset_vcpu(cpu); | |
660 | } | |
661 | #endif | |
dc5bd18f MC |
662 | } |
663 | ||
664 | static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) | |
665 | { | |
5c5a47f1 | 666 | RISCVCPU *cpu = RISCV_CPU(s); |
db23e5d9 RH |
667 | |
668 | switch (riscv_cpu_mxl(&cpu->env)) { | |
669 | case MXL_RV32: | |
5c5a47f1 | 670 | info->print_insn = print_insn_riscv32; |
db23e5d9 RH |
671 | break; |
672 | case MXL_RV64: | |
5c5a47f1 | 673 | info->print_insn = print_insn_riscv64; |
db23e5d9 | 674 | break; |
332dab68 FP |
675 | case MXL_RV128: |
676 | info->print_insn = print_insn_riscv128; | |
677 | break; | |
db23e5d9 RH |
678 | default: |
679 | g_assert_not_reached(); | |
5c5a47f1 | 680 | } |
dc5bd18f MC |
681 | } |
682 | ||
5ab10952 DHB |
683 | /* |
684 | * Check consistency between chosen extensions while setting | |
685 | * cpu->cfg accordingly, doing a set_misa() in the end. | |
686 | */ | |
687 | static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) | |
688 | { | |
689 | CPURISCVState *env = &cpu->env; | |
690 | uint32_t ext = 0; | |
691 | ||
692 | /* Do some ISA extension error checking */ | |
693 | if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && | |
694 | cpu->cfg.ext_a && cpu->cfg.ext_f && | |
695 | cpu->cfg.ext_d && | |
696 | cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { | |
697 | warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); | |
698 | cpu->cfg.ext_i = true; | |
699 | cpu->cfg.ext_m = true; | |
700 | cpu->cfg.ext_a = true; | |
701 | cpu->cfg.ext_f = true; | |
702 | cpu->cfg.ext_d = true; | |
703 | cpu->cfg.ext_icsr = true; | |
704 | cpu->cfg.ext_ifencei = true; | |
705 | } | |
706 | ||
707 | if (cpu->cfg.ext_i && cpu->cfg.ext_e) { | |
708 | error_setg(errp, | |
709 | "I and E extensions are incompatible"); | |
710 | return; | |
711 | } | |
712 | ||
713 | if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { | |
714 | error_setg(errp, | |
715 | "Either I or E extension must be set"); | |
716 | return; | |
717 | } | |
718 | ||
719 | if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { | |
720 | error_setg(errp, | |
721 | "Setting S extension without U extension is illegal"); | |
722 | return; | |
723 | } | |
724 | ||
725 | if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { | |
726 | error_setg(errp, | |
727 | "H depends on an I base integer ISA with 32 x registers"); | |
728 | return; | |
729 | } | |
730 | ||
731 | if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { | |
732 | error_setg(errp, "H extension implicitly requires S-mode"); | |
733 | return; | |
734 | } | |
735 | ||
736 | if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { | |
737 | error_setg(errp, "F extension requires Zicsr"); | |
738 | return; | |
739 | } | |
740 | ||
741 | if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { | |
742 | error_setg(errp, "Zawrs extension requires A extension"); | |
743 | return; | |
744 | } | |
745 | ||
1d2cb5a8 WL |
746 | if (cpu->cfg.ext_zfh) { |
747 | cpu->cfg.ext_zfhmin = true; | |
748 | } | |
749 | ||
750 | if (cpu->cfg.ext_zfhmin && !cpu->cfg.ext_f) { | |
5ab10952 DHB |
751 | error_setg(errp, "Zfh/Zfhmin extensions require F extension"); |
752 | return; | |
753 | } | |
754 | ||
755 | if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { | |
756 | error_setg(errp, "D extension requires F extension"); | |
757 | return; | |
758 | } | |
759 | ||
e7f0a803 WL |
760 | /* The V vector extension depends on the Zve64d extension */ |
761 | if (cpu->cfg.ext_v) { | |
762 | cpu->cfg.ext_zve64d = true; | |
763 | } | |
764 | ||
765 | /* The Zve64d extension depends on the Zve64f extension */ | |
766 | if (cpu->cfg.ext_zve64d) { | |
767 | cpu->cfg.ext_zve64f = true; | |
768 | } | |
769 | ||
770 | /* The Zve64f extension depends on the Zve32f extension */ | |
771 | if (cpu->cfg.ext_zve64f) { | |
772 | cpu->cfg.ext_zve32f = true; | |
773 | } | |
774 | ||
775 | if (cpu->cfg.ext_zve64d && !cpu->cfg.ext_d) { | |
776 | error_setg(errp, "Zve64d/V extensions require D extension"); | |
5ab10952 DHB |
777 | return; |
778 | } | |
779 | ||
e7f0a803 | 780 | if (cpu->cfg.ext_zve32f && !cpu->cfg.ext_f) { |
5ab10952 DHB |
781 | error_setg(errp, "Zve32f/Zve64f extensions require F extension"); |
782 | return; | |
783 | } | |
784 | ||
2e60f9ec WL |
785 | if (cpu->cfg.ext_zvfh) { |
786 | cpu->cfg.ext_zvfhmin = true; | |
787 | } | |
788 | ||
789 | if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { | |
790 | error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension"); | |
791 | return; | |
792 | } | |
793 | ||
794 | if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { | |
795 | error_setg(errp, "Zvfh extensions requires Zfhmin extension"); | |
796 | return; | |
797 | } | |
798 | ||
5ab10952 | 799 | /* Set the ISA extensions, checks should have happened above */ |
a0d805f0 WL |
800 | if (cpu->cfg.ext_zhinx) { |
801 | cpu->cfg.ext_zhinxmin = true; | |
802 | } | |
803 | ||
804 | if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) { | |
5ab10952 DHB |
805 | cpu->cfg.ext_zfinx = true; |
806 | } | |
807 | ||
808 | if (cpu->cfg.ext_zfinx) { | |
809 | if (!cpu->cfg.ext_icsr) { | |
810 | error_setg(errp, "Zfinx extension requires Zicsr"); | |
811 | return; | |
812 | } | |
813 | if (cpu->cfg.ext_f) { | |
814 | error_setg(errp, | |
51f33081 | 815 | "Zfinx cannot be supported together with F extension"); |
5ab10952 DHB |
816 | return; |
817 | } | |
818 | } | |
819 | ||
820 | if (cpu->cfg.ext_zk) { | |
821 | cpu->cfg.ext_zkn = true; | |
822 | cpu->cfg.ext_zkr = true; | |
823 | cpu->cfg.ext_zkt = true; | |
824 | } | |
825 | ||
826 | if (cpu->cfg.ext_zkn) { | |
827 | cpu->cfg.ext_zbkb = true; | |
828 | cpu->cfg.ext_zbkc = true; | |
829 | cpu->cfg.ext_zbkx = true; | |
830 | cpu->cfg.ext_zkne = true; | |
831 | cpu->cfg.ext_zknd = true; | |
832 | cpu->cfg.ext_zknh = true; | |
833 | } | |
834 | ||
835 | if (cpu->cfg.ext_zks) { | |
836 | cpu->cfg.ext_zbkb = true; | |
837 | cpu->cfg.ext_zbkc = true; | |
838 | cpu->cfg.ext_zbkx = true; | |
839 | cpu->cfg.ext_zksed = true; | |
840 | cpu->cfg.ext_zksh = true; | |
841 | } | |
842 | ||
843 | if (cpu->cfg.ext_i) { | |
844 | ext |= RVI; | |
845 | } | |
846 | if (cpu->cfg.ext_e) { | |
847 | ext |= RVE; | |
848 | } | |
849 | if (cpu->cfg.ext_m) { | |
850 | ext |= RVM; | |
851 | } | |
852 | if (cpu->cfg.ext_a) { | |
853 | ext |= RVA; | |
854 | } | |
855 | if (cpu->cfg.ext_f) { | |
856 | ext |= RVF; | |
857 | } | |
858 | if (cpu->cfg.ext_d) { | |
859 | ext |= RVD; | |
860 | } | |
861 | if (cpu->cfg.ext_c) { | |
862 | ext |= RVC; | |
863 | } | |
864 | if (cpu->cfg.ext_s) { | |
865 | ext |= RVS; | |
866 | } | |
867 | if (cpu->cfg.ext_u) { | |
868 | ext |= RVU; | |
869 | } | |
870 | if (cpu->cfg.ext_h) { | |
871 | ext |= RVH; | |
872 | } | |
873 | if (cpu->cfg.ext_v) { | |
874 | int vext_version = VEXT_VERSION_1_00_0; | |
875 | ext |= RVV; | |
876 | if (!is_power_of_2(cpu->cfg.vlen)) { | |
877 | error_setg(errp, | |
51f33081 | 878 | "Vector extension VLEN must be power of 2"); |
5ab10952 DHB |
879 | return; |
880 | } | |
881 | if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { | |
882 | error_setg(errp, | |
51f33081 WL |
883 | "Vector extension implementation only supports VLEN " |
884 | "in the range [128, %d]", RV_VLEN_MAX); | |
5ab10952 DHB |
885 | return; |
886 | } | |
887 | if (!is_power_of_2(cpu->cfg.elen)) { | |
888 | error_setg(errp, | |
51f33081 | 889 | "Vector extension ELEN must be power of 2"); |
5ab10952 DHB |
890 | return; |
891 | } | |
51f33081 | 892 | if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { |
5ab10952 | 893 | error_setg(errp, |
51f33081 WL |
894 | "Vector extension implementation only supports ELEN " |
895 | "in the range [8, 64]"); | |
5ab10952 DHB |
896 | return; |
897 | } | |
51f33081 WL |
898 | if (cpu->cfg.vext_spec) { |
899 | if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { | |
900 | vext_version = VEXT_VERSION_1_00_0; | |
901 | } else { | |
902 | error_setg(errp, | |
903 | "Unsupported vector spec version '%s'", | |
904 | cpu->cfg.vext_spec); | |
905 | return; | |
906 | } | |
907 | } else { | |
908 | qemu_log("vector version is not specified, " | |
909 | "use the default value v1.0\n"); | |
910 | } | |
911 | set_vext_version(env, vext_version); | |
5ab10952 DHB |
912 | } |
913 | if (cpu->cfg.ext_j) { | |
914 | ext |= RVJ; | |
915 | } | |
916 | ||
917 | set_misa(env, env->misa_mxl, ext); | |
918 | } | |
919 | ||
dc5bd18f MC |
920 | static void riscv_cpu_realize(DeviceState *dev, Error **errp) |
921 | { | |
922 | CPUState *cs = CPU(dev); | |
c4e95030 AF |
923 | RISCVCPU *cpu = RISCV_CPU(dev); |
924 | CPURISCVState *env = &cpu->env; | |
dc5bd18f | 925 | RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); |
1191be09 | 926 | CPUClass *cc = CPU_CLASS(mcc); |
9a1f054d | 927 | int i, priv_version = -1; |
dc5bd18f MC |
928 | Error *local_err = NULL; |
929 | ||
930 | cpu_exec_realizefn(cs, &local_err); | |
931 | if (local_err != NULL) { | |
932 | error_propagate(errp, local_err); | |
933 | return; | |
934 | } | |
935 | ||
c4e95030 | 936 | if (cpu->cfg.priv_spec) { |
7100fe6c AP |
937 | if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { |
938 | priv_version = PRIV_VERSION_1_12_0; | |
939 | } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { | |
e3147506 AF |
940 | priv_version = PRIV_VERSION_1_11_0; |
941 | } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { | |
c4e95030 | 942 | priv_version = PRIV_VERSION_1_10_0; |
c4e95030 AF |
943 | } else { |
944 | error_setg(errp, | |
945 | "Unsupported privilege spec version '%s'", | |
946 | cpu->cfg.priv_spec); | |
947 | return; | |
948 | } | |
949 | } | |
950 | ||
18800095 | 951 | if (priv_version >= PRIV_VERSION_1_10_0) { |
a8b37120 | 952 | set_priv_version(env, priv_version); |
a8b37120 | 953 | } |
c4e95030 | 954 | |
9a1f054d AP |
955 | /* Force disable extensions if priv spec version does not match */ |
956 | for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { | |
957 | if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && | |
958 | (env->priv_ver < isa_edata_arr[i].min_version)) { | |
959 | isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); | |
960 | #ifndef CONFIG_USER_ONLY | |
877a3a37 BM |
961 | warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx |
962 | " because privilege spec version does not match", | |
963 | isa_edata_arr[i].name, env->mhartid); | |
9a1f054d AP |
964 | #else |
965 | warn_report("disabling %s extension because " | |
966 | "privilege spec version does not match", | |
967 | isa_edata_arr[i].name); | |
968 | #endif | |
969 | } | |
970 | } | |
971 | ||
6a3ffda2 | 972 | if (cpu->cfg.epmp && !cpu->cfg.pmp) { |
5da9514e HW |
973 | /* |
974 | * Enhanced PMP should only be available | |
975 | * on harts with PMP support | |
976 | */ | |
6a3ffda2 DHB |
977 | error_setg(errp, "Invalid configuration: EPMP requires PMP support"); |
978 | return; | |
1acdb3b0 BM |
979 | } |
980 | ||
73f6ed97 | 981 | |
43888c2f AP |
982 | #ifndef CONFIG_USER_ONLY |
983 | if (cpu->cfg.ext_sstc) { | |
984 | riscv_timer_init(cpu); | |
985 | } | |
986 | #endif /* CONFIG_USER_ONLY */ | |
987 | ||
e91a7227 RH |
988 | /* Validate that MISA_MXL is set properly. */ |
989 | switch (env->misa_mxl_max) { | |
990 | #ifdef TARGET_RISCV64 | |
991 | case MXL_RV64: | |
332dab68 | 992 | case MXL_RV128: |
6c3a9247 | 993 | cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; |
332dab68 | 994 | break; |
e91a7227 RH |
995 | #endif |
996 | case MXL_RV32: | |
1191be09 | 997 | cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; |
e91a7227 RH |
998 | break; |
999 | default: | |
1000 | g_assert_not_reached(); | |
1001 | } | |
1002 | assert(env->misa_mxl_max == env->misa_mxl); | |
1003 | ||
5ab10952 DHB |
1004 | riscv_cpu_validate_set_extensions(cpu, &local_err); |
1005 | if (local_err != NULL) { | |
1006 | error_propagate(errp, local_err); | |
1007 | return; | |
b55d7d34 AF |
1008 | } |
1009 | ||
14664483 AP |
1010 | #ifndef CONFIG_USER_ONLY |
1011 | if (cpu->cfg.pmu_num) { | |
1012 | if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { | |
1013 | cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, | |
1014 | riscv_pmu_timer_cb, cpu); | |
1015 | } | |
1016 | } | |
1017 | #endif | |
1018 | ||
5371f5cd JW |
1019 | riscv_cpu_register_gdb_regs_for_features(cs); |
1020 | ||
dc5bd18f MC |
1021 | qemu_init_vcpu(cs); |
1022 | cpu_reset(cs); | |
1023 | ||
1024 | mcc->parent_realize(dev, errp); | |
1025 | } | |
1026 | ||
0f0b70ee AF |
1027 | #ifndef CONFIG_USER_ONLY |
1028 | static void riscv_cpu_set_irq(void *opaque, int irq, int level) | |
1029 | { | |
1030 | RISCVCPU *cpu = RISCV_CPU(opaque); | |
cd032fe7 | 1031 | CPURISCVState *env = &cpu->env; |
0f0b70ee | 1032 | |
cd032fe7 AP |
1033 | if (irq < IRQ_LOCAL_MAX) { |
1034 | switch (irq) { | |
1035 | case IRQ_U_SOFT: | |
1036 | case IRQ_S_SOFT: | |
1037 | case IRQ_VS_SOFT: | |
1038 | case IRQ_M_SOFT: | |
1039 | case IRQ_U_TIMER: | |
1040 | case IRQ_S_TIMER: | |
1041 | case IRQ_VS_TIMER: | |
1042 | case IRQ_M_TIMER: | |
1043 | case IRQ_U_EXT: | |
cd032fe7 AP |
1044 | case IRQ_VS_EXT: |
1045 | case IRQ_M_EXT: | |
8b5c807b | 1046 | if (kvm_enabled()) { |
cd032fe7 | 1047 | kvm_riscv_set_irq(cpu, irq, level); |
8b5c807b | 1048 | } else { |
cd032fe7 | 1049 | riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); |
8b5c807b | 1050 | } |
cd032fe7 | 1051 | break; |
33fe584f AF |
1052 | case IRQ_S_EXT: |
1053 | if (kvm_enabled()) { | |
1054 | kvm_riscv_set_irq(cpu, irq, level); | |
1055 | } else { | |
1056 | env->external_seip = level; | |
1057 | riscv_cpu_update_mip(cpu, 1 << irq, | |
1058 | BOOL_TO_MASK(level | env->software_seip)); | |
1059 | } | |
1060 | break; | |
cd032fe7 AP |
1061 | default: |
1062 | g_assert_not_reached(); | |
2b650fbb | 1063 | } |
cd032fe7 AP |
1064 | } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { |
1065 | /* Require H-extension for handling guest local interrupts */ | |
1066 | if (!riscv_has_ext(env, RVH)) { | |
1067 | g_assert_not_reached(); | |
1068 | } | |
1069 | ||
1070 | /* Compute bit position in HGEIP CSR */ | |
1071 | irq = irq - IRQ_LOCAL_MAX + 1; | |
1072 | if (env->geilen < irq) { | |
1073 | g_assert_not_reached(); | |
1074 | } | |
1075 | ||
1076 | /* Update HGEIP CSR */ | |
1077 | env->hgeip &= ~((target_ulong)1 << irq); | |
1078 | if (level) { | |
1079 | env->hgeip |= (target_ulong)1 << irq; | |
1080 | } | |
1081 | ||
1082 | /* Update mip.SGEIP bit */ | |
1083 | riscv_cpu_update_mip(cpu, MIP_SGEIP, | |
1084 | BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); | |
1085 | } else { | |
0f0b70ee AF |
1086 | g_assert_not_reached(); |
1087 | } | |
1088 | } | |
1089 | #endif /* CONFIG_USER_ONLY */ | |
1090 | ||
dc5bd18f MC |
1091 | static void riscv_cpu_init(Object *obj) |
1092 | { | |
dc5bd18f MC |
1093 | RISCVCPU *cpu = RISCV_CPU(obj); |
1094 | ||
26b2bc58 AF |
1095 | cpu->cfg.ext_ifencei = true; |
1096 | cpu->cfg.ext_icsr = true; | |
1097 | cpu->cfg.mmu = true; | |
1098 | cpu->cfg.pmp = true; | |
1099 | ||
7506ed90 | 1100 | cpu_set_cpustate_pointers(cpu); |
0f0b70ee AF |
1101 | |
1102 | #ifndef CONFIG_USER_ONLY | |
cd032fe7 AP |
1103 | qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, |
1104 | IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); | |
0f0b70ee | 1105 | #endif /* CONFIG_USER_ONLY */ |
dc5bd18f MC |
1106 | } |
1107 | ||
26b2bc58 | 1108 | static Property riscv_cpu_extensions[] = { |
9d3d60b7 | 1109 | /* Defaults for standard extensions */ |
b55d7d34 AF |
1110 | DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), |
1111 | DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), | |
1d398ab9 | 1112 | DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), |
b55d7d34 AF |
1113 | DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), |
1114 | DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), | |
1115 | DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), | |
1116 | DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), | |
1117 | DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), | |
1118 | DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), | |
1119 | DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), | |
9ec6622d | 1120 | DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), |
07cb270a | 1121 | DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), |
18d6d89e | 1122 | DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), |
14664483 | 1123 | DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), |
9d3d60b7 AF |
1124 | DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), |
1125 | DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), | |
4696f0ab | 1126 | DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), |
260b594d | 1127 | DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), |
13fb8c7b | 1128 | DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), |
e5237730 | 1129 | DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), |
2fc1b44d | 1130 | DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), |
bfefe406 | 1131 | DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), |
058d9d30 | 1132 | DEFINE_PROP_BOOL("Zve64d", RISCVCPU, cfg.ext_zve64d, false), |
9d3d60b7 AF |
1133 | DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), |
1134 | DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), | |
43888c2f | 1135 | DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true), |
9d3d60b7 AF |
1136 | |
1137 | DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), | |
9ec6622d FC |
1138 | DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), |
1139 | DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), | |
1140 | DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), | |
9d3d60b7 | 1141 | |
62108f05 WL |
1142 | DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true), |
1143 | ||
c5d77ddd | 1144 | DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), |
2bacb224 | 1145 | DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), |
bbce8ba8 | 1146 | DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), |
2bacb224 | 1147 | |
0643c12e VG |
1148 | DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), |
1149 | DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), | |
1150 | DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), | |
cf7ed971 WL |
1151 | DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false), |
1152 | DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false), | |
1153 | DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false), | |
0643c12e | 1154 | DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), |
cf7ed971 WL |
1155 | DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false), |
1156 | DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false), | |
1157 | DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false), | |
1158 | DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false), | |
1159 | DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false), | |
1160 | DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false), | |
1161 | DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false), | |
1162 | DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false), | |
1163 | DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), | |
1164 | DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), | |
dfdb46a3 | 1165 | |
6b1accef WL |
1166 | DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), |
1167 | DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), | |
1168 | DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), | |
1169 | DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), | |
1170 | ||
a939c500 CM |
1171 | DEFINE_PROP_BOOL("zicboz", RISCVCPU, cfg.ext_icboz, true), |
1172 | DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), | |
1173 | ||
6d00ffad WL |
1174 | DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), |
1175 | ||
0d429bd2 | 1176 | /* Vendor-specific custom extensions */ |
c9410a68 | 1177 | DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), |
426c0491 | 1178 | DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), |
fa134585 | 1179 | DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), |
49a7f3aa | 1180 | DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), |
32909338 | 1181 | DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), |
d4d90115 | 1182 | DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false), |
578086ba | 1183 | DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false), |
b8a5832b | 1184 | DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), |
45f9df86 | 1185 | DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false), |
af99aa72 | 1186 | DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false), |
134c3ffa | 1187 | DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), |
0d429bd2 PT |
1188 | DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), |
1189 | ||
dfdb46a3 | 1190 | /* These are experimental so mark with 'x-' */ |
b8e1f32c | 1191 | DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), |
0ee9a4e5 | 1192 | DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), |
a44da25a | 1193 | /* ePMP 0.9.3 */ |
5da9514e | 1194 | DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), |
dc9acc9c AP |
1195 | DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), |
1196 | DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), | |
5da9514e | 1197 | |
058d9d30 WL |
1198 | DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false), |
1199 | DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false), | |
1200 | ||
26b2bc58 AF |
1201 | DEFINE_PROP_END_OF_LIST(), |
1202 | }; | |
1203 | ||
c66ffcd5 DHB |
1204 | /* |
1205 | * Register CPU props based on env.misa_ext. If a non-zero | |
1206 | * value was set, register only the required cpu->cfg.ext_* | |
1207 | * properties and leave. env.misa_ext = 0 means that we want | |
1208 | * all the default properties to be registered. | |
1209 | */ | |
26b2bc58 AF |
1210 | static void register_cpu_props(DeviceState *dev) |
1211 | { | |
c66ffcd5 DHB |
1212 | RISCVCPU *cpu = RISCV_CPU(OBJECT(dev)); |
1213 | uint32_t misa_ext = cpu->env.misa_ext; | |
26b2bc58 AF |
1214 | Property *prop; |
1215 | ||
c66ffcd5 DHB |
1216 | /* |
1217 | * If misa_ext is not zero, set cfg properties now to | |
1218 | * allow them to be read during riscv_cpu_realize() | |
1219 | * later on. | |
1220 | */ | |
1221 | if (cpu->env.misa_ext != 0) { | |
1222 | cpu->cfg.ext_i = misa_ext & RVI; | |
1223 | cpu->cfg.ext_e = misa_ext & RVE; | |
1224 | cpu->cfg.ext_m = misa_ext & RVM; | |
1225 | cpu->cfg.ext_a = misa_ext & RVA; | |
1226 | cpu->cfg.ext_f = misa_ext & RVF; | |
1227 | cpu->cfg.ext_d = misa_ext & RVD; | |
1228 | cpu->cfg.ext_v = misa_ext & RVV; | |
1229 | cpu->cfg.ext_c = misa_ext & RVC; | |
1230 | cpu->cfg.ext_s = misa_ext & RVS; | |
1231 | cpu->cfg.ext_u = misa_ext & RVU; | |
1232 | cpu->cfg.ext_h = misa_ext & RVH; | |
1233 | cpu->cfg.ext_j = misa_ext & RVJ; | |
1234 | ||
1235 | /* | |
1236 | * We don't want to set the default riscv_cpu_extensions | |
1237 | * in this case. | |
1238 | */ | |
1239 | return; | |
1240 | } | |
1241 | ||
26b2bc58 AF |
1242 | for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { |
1243 | qdev_property_add_static(dev, prop); | |
1244 | } | |
1245 | } | |
1246 | ||
1247 | static Property riscv_cpu_properties[] = { | |
1248 | DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), | |
1249 | ||
1250 | DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), | |
1251 | DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), | |
1252 | DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), | |
1253 | ||
277b210d AF |
1254 | #ifndef CONFIG_USER_ONLY |
1255 | DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), | |
1256 | #endif | |
a4a9a443 TO |
1257 | |
1258 | DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), | |
b8312675 | 1259 | |
1260 | DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), | |
1ad3f9bd | 1261 | DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), |
54bd9b6e DHB |
1262 | |
1263 | /* | |
1264 | * write_misa() is marked as experimental for now so mark | |
1265 | * it with -x and default to 'false'. | |
1266 | */ | |
1267 | DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false), | |
c4e95030 AF |
1268 | DEFINE_PROP_END_OF_LIST(), |
1269 | }; | |
1270 | ||
edf64786 SP |
1271 | static gchar *riscv_gdb_arch_name(CPUState *cs) |
1272 | { | |
1273 | RISCVCPU *cpu = RISCV_CPU(cs); | |
1274 | CPURISCVState *env = &cpu->env; | |
1275 | ||
db23e5d9 RH |
1276 | switch (riscv_cpu_mxl(env)) { |
1277 | case MXL_RV32: | |
edf64786 | 1278 | return g_strdup("riscv:rv32"); |
db23e5d9 | 1279 | case MXL_RV64: |
332dab68 | 1280 | case MXL_RV128: |
edf64786 | 1281 | return g_strdup("riscv:rv64"); |
db23e5d9 RH |
1282 | default: |
1283 | g_assert_not_reached(); | |
edf64786 SP |
1284 | } |
1285 | } | |
1286 | ||
b93777e1 BM |
1287 | static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) |
1288 | { | |
1289 | RISCVCPU *cpu = RISCV_CPU(cs); | |
1290 | ||
1291 | if (strcmp(xmlname, "riscv-csr.xml") == 0) { | |
1292 | return cpu->dyn_csr_xml; | |
719d3561 HW |
1293 | } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { |
1294 | return cpu->dyn_vreg_xml; | |
b93777e1 BM |
1295 | } |
1296 | ||
1297 | return NULL; | |
1298 | } | |
1299 | ||
8b80bd28 PMD |
1300 | #ifndef CONFIG_USER_ONLY |
1301 | #include "hw/core/sysemu-cpu-ops.h" | |
1302 | ||
1303 | static const struct SysemuCPUOps riscv_sysemu_ops = { | |
08928c6d | 1304 | .get_phys_page_debug = riscv_cpu_get_phys_page_debug, |
715e3c1a PMD |
1305 | .write_elf64_note = riscv_cpu_write_elf64_note, |
1306 | .write_elf32_note = riscv_cpu_write_elf32_note, | |
feece4d0 | 1307 | .legacy_vmsd = &vmstate_riscv_cpu, |
8b80bd28 PMD |
1308 | }; |
1309 | #endif | |
1310 | ||
78271684 CF |
1311 | #include "hw/core/tcg-cpu-ops.h" |
1312 | ||
11906557 | 1313 | static const struct TCGCPUOps riscv_tcg_ops = { |
78271684 CF |
1314 | .initialize = riscv_translate_init, |
1315 | .synchronize_from_tb = riscv_cpu_synchronize_from_tb, | |
ad1e84f5 | 1316 | .restore_state_to_opc = riscv_restore_state_to_opc, |
78271684 CF |
1317 | |
1318 | #ifndef CONFIG_USER_ONLY | |
263e2ab2 | 1319 | .tlb_fill = riscv_cpu_tlb_fill, |
17b3c353 | 1320 | .cpu_exec_interrupt = riscv_cpu_exec_interrupt, |
78271684 CF |
1321 | .do_interrupt = riscv_cpu_do_interrupt, |
1322 | .do_transaction_failed = riscv_cpu_do_transaction_failed, | |
1323 | .do_unaligned_access = riscv_cpu_do_unaligned_access, | |
b5f6379d BM |
1324 | .debug_excp_handler = riscv_cpu_debug_excp_handler, |
1325 | .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, | |
1326 | .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, | |
78271684 CF |
1327 | #endif /* !CONFIG_USER_ONLY */ |
1328 | }; | |
1329 | ||
dc5bd18f MC |
1330 | static void riscv_cpu_class_init(ObjectClass *c, void *data) |
1331 | { | |
1332 | RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); | |
1333 | CPUClass *cc = CPU_CLASS(c); | |
1334 | DeviceClass *dc = DEVICE_CLASS(c); | |
4fa485a7 | 1335 | ResettableClass *rc = RESETTABLE_CLASS(c); |
dc5bd18f | 1336 | |
41fbbba7 MZ |
1337 | device_class_set_parent_realize(dc, riscv_cpu_realize, |
1338 | &mcc->parent_realize); | |
dc5bd18f | 1339 | |
4fa485a7 PM |
1340 | resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL, |
1341 | &mcc->parent_phases); | |
dc5bd18f MC |
1342 | |
1343 | cc->class_by_name = riscv_cpu_class_by_name; | |
1344 | cc->has_work = riscv_cpu_has_work; | |
dc5bd18f MC |
1345 | cc->dump_state = riscv_cpu_dump_state; |
1346 | cc->set_pc = riscv_cpu_set_pc; | |
e4fdf9df | 1347 | cc->get_pc = riscv_cpu_get_pc; |
dc5bd18f MC |
1348 | cc->gdb_read_register = riscv_cpu_gdb_read_register; |
1349 | cc->gdb_write_register = riscv_cpu_gdb_write_register; | |
5371f5cd | 1350 | cc->gdb_num_core_regs = 33; |
dc5bd18f MC |
1351 | cc->gdb_stop_before_watchpoint = true; |
1352 | cc->disas_set_info = riscv_cpu_disas_set_info; | |
8a4ca3c1 | 1353 | #ifndef CONFIG_USER_ONLY |
8b80bd28 | 1354 | cc->sysemu_ops = &riscv_sysemu_ops; |
dc5bd18f | 1355 | #endif |
edf64786 | 1356 | cc->gdb_arch_name = riscv_gdb_arch_name; |
b93777e1 | 1357 | cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; |
78271684 | 1358 | cc->tcg_ops = &riscv_tcg_ops; |
6a3d2e7c | 1359 | |
4f67d30b | 1360 | device_class_set_props(dc, riscv_cpu_properties); |
dc5bd18f MC |
1361 | } |
1362 | ||
a775398b AP |
1363 | static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) |
1364 | { | |
1365 | char *old = *isa_str; | |
1366 | char *new = *isa_str; | |
1367 | int i; | |
1368 | ||
a775398b | 1369 | for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { |
9a1f054d AP |
1370 | if (isa_edata_arr[i].multi_letter && |
1371 | isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { | |
a775398b AP |
1372 | new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); |
1373 | g_free(old); | |
1374 | old = new; | |
1375 | } | |
1376 | } | |
1377 | ||
1378 | *isa_str = new; | |
1379 | } | |
1380 | ||
dc5bd18f MC |
1381 | char *riscv_isa_string(RISCVCPU *cpu) |
1382 | { | |
1383 | int i; | |
0e2c3770 | 1384 | const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); |
d1fd31f8 MC |
1385 | char *isa_str = g_new(char, maxlen); |
1386 | char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); | |
0e2c3770 TO |
1387 | for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { |
1388 | if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { | |
1389 | *p++ = qemu_tolower(riscv_single_letter_exts[i]); | |
dc5bd18f MC |
1390 | } |
1391 | } | |
d1fd31f8 | 1392 | *p = '\0'; |
a4a9a443 TO |
1393 | if (!cpu->cfg.short_isa_string) { |
1394 | riscv_isa_string_ext(cpu, &isa_str, maxlen); | |
1395 | } | |
d1fd31f8 | 1396 | return isa_str; |
dc5bd18f MC |
1397 | } |
1398 | ||
eab15862 | 1399 | static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) |
dc5bd18f | 1400 | { |
eab15862 MC |
1401 | ObjectClass *class_a = (ObjectClass *)a; |
1402 | ObjectClass *class_b = (ObjectClass *)b; | |
1403 | const char *name_a, *name_b; | |
dc5bd18f | 1404 | |
eab15862 MC |
1405 | name_a = object_class_get_name(class_a); |
1406 | name_b = object_class_get_name(class_b); | |
1407 | return strcmp(name_a, name_b); | |
dc5bd18f MC |
1408 | } |
1409 | ||
eab15862 | 1410 | static void riscv_cpu_list_entry(gpointer data, gpointer user_data) |
dc5bd18f | 1411 | { |
eab15862 MC |
1412 | const char *typename = object_class_get_name(OBJECT_CLASS(data)); |
1413 | int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); | |
dc5bd18f | 1414 | |
0442428a | 1415 | qemu_printf("%.*s\n", len, typename); |
eab15862 | 1416 | } |
dc5bd18f | 1417 | |
0442428a | 1418 | void riscv_cpu_list(void) |
eab15862 | 1419 | { |
eab15862 MC |
1420 | GSList *list; |
1421 | ||
1422 | list = object_class_get_list(TYPE_RISCV_CPU, false); | |
1423 | list = g_slist_sort(list, riscv_cpu_list_compare); | |
0442428a | 1424 | g_slist_foreach(list, riscv_cpu_list_entry, NULL); |
eab15862 | 1425 | g_slist_free(list); |
dc5bd18f MC |
1426 | } |
1427 | ||
eab15862 MC |
1428 | #define DEFINE_CPU(type_name, initfn) \ |
1429 | { \ | |
1430 | .name = type_name, \ | |
1431 | .parent = TYPE_RISCV_CPU, \ | |
1432 | .instance_init = initfn \ | |
1433 | } | |
1434 | ||
1435 | static const TypeInfo riscv_cpu_type_infos[] = { | |
1436 | { | |
1437 | .name = TYPE_RISCV_CPU, | |
1438 | .parent = TYPE_CPU, | |
1439 | .instance_size = sizeof(RISCVCPU), | |
5de5b99b | 1440 | .instance_align = __alignof__(RISCVCPU), |
eab15862 MC |
1441 | .instance_init = riscv_cpu_init, |
1442 | .abstract = true, | |
1443 | .class_size = sizeof(RISCVCPUClass), | |
1444 | .class_init = riscv_cpu_class_init, | |
1445 | }, | |
1446 | DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), | |
10f1ca27 YJ |
1447 | #if defined(CONFIG_KVM) |
1448 | DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), | |
1449 | #endif | |
eab15862 | 1450 | #if defined(TARGET_RISCV32) |
094b072c | 1451 | DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), |
e8905c6c | 1452 | DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), |
114baaca | 1453 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), |
2fdd2c09 | 1454 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), |
114baaca | 1455 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), |
eab15862 | 1456 | #elif defined(TARGET_RISCV64) |
094b072c | 1457 | DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), |
114baaca AF |
1458 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), |
1459 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), | |
6ddc7069 | 1460 | DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), |
95bd8daa | 1461 | DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), |
332dab68 | 1462 | DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), |
eab15862 MC |
1463 | #endif |
1464 | }; | |
1465 | ||
1466 | DEFINE_TYPES(riscv_cpu_type_infos) |