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dc5bd18f MC |
1 | /* |
2 | * QEMU RISC-V CPU | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
0442428a | 21 | #include "qemu/qemu-print.h" |
856dfd8a | 22 | #include "qemu/ctype.h" |
dc5bd18f MC |
23 | #include "qemu/log.h" |
24 | #include "cpu.h" | |
f7697f0e | 25 | #include "internals.h" |
dc5bd18f MC |
26 | #include "exec/exec-all.h" |
27 | #include "qapi/error.h" | |
b55d7d34 | 28 | #include "qemu/error-report.h" |
c4e95030 | 29 | #include "hw/qdev-properties.h" |
dc5bd18f | 30 | #include "migration/vmstate.h" |
135b03cb | 31 | #include "fpu/softfloat-helpers.h" |
dc5bd18f MC |
32 | |
33 | /* RISC-V CPU definitions */ | |
34 | ||
79f86934 | 35 | static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG"; |
dc5bd18f MC |
36 | |
37 | const char * const riscv_int_regnames[] = { | |
a9f37afa AP |
38 | "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", |
39 | "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", | |
40 | "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", | |
41 | "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", | |
42 | "x28/t3", "x29/t4", "x30/t5", "x31/t6" | |
dc5bd18f MC |
43 | }; |
44 | ||
45 | const char * const riscv_fpr_regnames[] = { | |
a9f37afa AP |
46 | "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", |
47 | "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", | |
48 | "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", | |
49 | "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", | |
50 | "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", | |
51 | "f30/ft10", "f31/ft11" | |
dc5bd18f MC |
52 | }; |
53 | ||
54 | const char * const riscv_excp_names[] = { | |
55 | "misaligned_fetch", | |
56 | "fault_fetch", | |
57 | "illegal_instruction", | |
58 | "breakpoint", | |
59 | "misaligned_load", | |
60 | "fault_load", | |
61 | "misaligned_store", | |
62 | "fault_store", | |
63 | "user_ecall", | |
64 | "supervisor_ecall", | |
65 | "hypervisor_ecall", | |
66 | "machine_ecall", | |
67 | "exec_page_fault", | |
68 | "load_page_fault", | |
69 | "reserved", | |
fd990e86 | 70 | "store_page_fault", |
ab67a1d0 AF |
71 | "reserved", |
72 | "reserved", | |
73 | "reserved", | |
74 | "reserved", | |
75 | "guest_exec_page_fault", | |
76 | "guest_load_page_fault", | |
77 | "reserved", | |
fd990e86 | 78 | "guest_store_page_fault", |
dc5bd18f MC |
79 | }; |
80 | ||
81 | const char * const riscv_intr_names[] = { | |
82 | "u_software", | |
83 | "s_software", | |
205377f8 | 84 | "vs_software", |
dc5bd18f MC |
85 | "m_software", |
86 | "u_timer", | |
87 | "s_timer", | |
205377f8 | 88 | "vs_timer", |
dc5bd18f MC |
89 | "m_timer", |
90 | "u_external", | |
6cfcf775 | 91 | "s_external", |
205377f8 | 92 | "vs_external", |
dc5bd18f | 93 | "m_external", |
426f0348 MC |
94 | "reserved", |
95 | "reserved", | |
96 | "reserved", | |
97 | "reserved" | |
dc5bd18f MC |
98 | }; |
99 | ||
c51a3f5d YJ |
100 | const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) |
101 | { | |
102 | if (async) { | |
103 | return (cause < ARRAY_SIZE(riscv_intr_names)) ? | |
104 | riscv_intr_names[cause] : "(unknown)"; | |
105 | } else { | |
106 | return (cause < ARRAY_SIZE(riscv_excp_names)) ? | |
107 | riscv_excp_names[cause] : "(unknown)"; | |
108 | } | |
109 | } | |
110 | ||
51ae0cab AF |
111 | bool riscv_cpu_is_32bit(CPURISCVState *env) |
112 | { | |
113 | if (env->misa & RV64) { | |
114 | return false; | |
115 | } | |
116 | ||
117 | return true; | |
118 | } | |
119 | ||
dc5bd18f MC |
120 | static void set_misa(CPURISCVState *env, target_ulong misa) |
121 | { | |
f18637cd | 122 | env->misa_mask = env->misa = misa; |
dc5bd18f MC |
123 | } |
124 | ||
c9a73910 | 125 | static void set_priv_version(CPURISCVState *env, int priv_ver) |
dc5bd18f | 126 | { |
dc5bd18f MC |
127 | env->priv_ver = priv_ver; |
128 | } | |
129 | ||
32931383 LZ |
130 | static void set_vext_version(CPURISCVState *env, int vext_ver) |
131 | { | |
132 | env->vext_ver = vext_ver; | |
133 | } | |
134 | ||
dc5bd18f MC |
135 | static void set_feature(CPURISCVState *env, int feature) |
136 | { | |
137 | env->features |= (1ULL << feature); | |
138 | } | |
139 | ||
01e723bf | 140 | static void set_resetvec(CPURISCVState *env, target_ulong resetvec) |
dc5bd18f MC |
141 | { |
142 | #ifndef CONFIG_USER_ONLY | |
143 | env->resetvec = resetvec; | |
144 | #endif | |
145 | } | |
146 | ||
147 | static void riscv_any_cpu_init(Object *obj) | |
148 | { | |
149 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
3820602f AF |
150 | #if defined(TARGET_RISCV32) |
151 | set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVU); | |
152 | #elif defined(TARGET_RISCV64) | |
153 | set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVU); | |
154 | #endif | |
c9a73910 | 155 | set_priv_version(env, PRIV_VERSION_1_11_0); |
dc5bd18f MC |
156 | } |
157 | ||
094b072c AF |
158 | #if defined(TARGET_RISCV64) |
159 | static void rv64_base_cpu_init(Object *obj) | |
8903bf6e AF |
160 | { |
161 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
b55d7d34 | 162 | /* We set this in the realise function */ |
094b072c | 163 | set_misa(env, RV64); |
8903bf6e AF |
164 | } |
165 | ||
114baaca | 166 | static void rv64_sifive_u_cpu_init(Object *obj) |
dc5bd18f MC |
167 | { |
168 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
114baaca | 169 | set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); |
c9a73910 | 170 | set_priv_version(env, PRIV_VERSION_1_10_0); |
dc5bd18f MC |
171 | } |
172 | ||
114baaca | 173 | static void rv64_sifive_e_cpu_init(Object *obj) |
36b80ad9 AF |
174 | { |
175 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
114baaca | 176 | set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU); |
36b80ad9 | 177 | set_priv_version(env, PRIV_VERSION_1_10_0); |
36b80ad9 AF |
178 | qdev_prop_set_bit(DEVICE(obj), "mmu", false); |
179 | } | |
114baaca | 180 | #else |
094b072c AF |
181 | static void rv32_base_cpu_init(Object *obj) |
182 | { | |
183 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
184 | /* We set this in the realise function */ | |
185 | set_misa(env, RV32); | |
186 | } | |
187 | ||
114baaca AF |
188 | static void rv32_sifive_u_cpu_init(Object *obj) |
189 | { | |
190 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
191 | set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); | |
192 | set_priv_version(env, PRIV_VERSION_1_10_0); | |
193 | } | |
36b80ad9 | 194 | |
114baaca AF |
195 | static void rv32_sifive_e_cpu_init(Object *obj) |
196 | { | |
197 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
198 | set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU); | |
199 | set_priv_version(env, PRIV_VERSION_1_10_0); | |
200 | qdev_prop_set_bit(DEVICE(obj), "mmu", false); | |
201 | } | |
d8e72bd1 | 202 | |
e8905c6c | 203 | static void rv32_ibex_cpu_init(Object *obj) |
dc5bd18f MC |
204 | { |
205 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
d8e72bd1 | 206 | set_misa(env, RV32 | RVI | RVM | RVC | RVU); |
c9a73910 | 207 | set_priv_version(env, PRIV_VERSION_1_10_0); |
8be6971b | 208 | qdev_prop_set_bit(DEVICE(obj), "mmu", false); |
ed6eebaa | 209 | qdev_prop_set_bit(DEVICE(obj), "x-epmp", true); |
dc5bd18f MC |
210 | } |
211 | ||
2fdd2c09 | 212 | static void rv32_imafcu_nommu_cpu_init(Object *obj) |
d784733b CW |
213 | { |
214 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
215 | set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU); | |
216 | set_priv_version(env, PRIV_VERSION_1_10_0); | |
217 | set_resetvec(env, DEFAULT_RSTVEC); | |
8be6971b | 218 | qdev_prop_set_bit(DEVICE(obj), "mmu", false); |
d784733b | 219 | } |
eab15862 | 220 | #endif |
dc5bd18f MC |
221 | |
222 | static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) | |
223 | { | |
224 | ObjectClass *oc; | |
225 | char *typename; | |
226 | char **cpuname; | |
227 | ||
228 | cpuname = g_strsplit(cpu_model, ",", 1); | |
229 | typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); | |
230 | oc = object_class_by_name(typename); | |
231 | g_strfreev(cpuname); | |
232 | g_free(typename); | |
233 | if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || | |
234 | object_class_is_abstract(oc)) { | |
235 | return NULL; | |
236 | } | |
237 | return oc; | |
238 | } | |
239 | ||
90c84c56 | 240 | static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) |
dc5bd18f MC |
241 | { |
242 | RISCVCPU *cpu = RISCV_CPU(cs); | |
243 | CPURISCVState *env = &cpu->env; | |
244 | int i; | |
245 | ||
df30e652 AF |
246 | #if !defined(CONFIG_USER_ONLY) |
247 | if (riscv_has_ext(env, RVH)) { | |
248 | qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); | |
249 | } | |
250 | #endif | |
90c84c56 | 251 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); |
dc5bd18f | 252 | #ifndef CONFIG_USER_ONLY |
90c84c56 | 253 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); |
284d697c | 254 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus); |
5c5a47f1 AF |
255 | if (riscv_cpu_is_32bit(env)) { |
256 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", | |
257 | (target_ulong)(env->mstatus >> 32)); | |
258 | } | |
df30e652 AF |
259 | if (riscv_has_ext(env, RVH)) { |
260 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus); | |
284d697c YJ |
261 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", |
262 | (target_ulong)env->vsstatus); | |
df30e652 | 263 | } |
02861613 | 264 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip); |
90c84c56 MA |
265 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie); |
266 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg); | |
df30e652 AF |
267 | if (riscv_has_ext(env, RVH)) { |
268 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg); | |
269 | } | |
90c84c56 | 270 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg); |
df30e652 AF |
271 | if (riscv_has_ext(env, RVH)) { |
272 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg); | |
273 | } | |
90c84c56 | 274 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec ", env->mtvec); |
df30e652 AF |
275 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec ", env->stvec); |
276 | if (riscv_has_ext(env, RVH)) { | |
277 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec ", env->vstvec); | |
278 | } | |
90c84c56 | 279 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc ", env->mepc); |
df30e652 AF |
280 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc ", env->sepc); |
281 | if (riscv_has_ext(env, RVH)) { | |
282 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc ", env->vsepc); | |
283 | } | |
90c84c56 | 284 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause ", env->mcause); |
df30e652 AF |
285 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause ", env->scause); |
286 | if (riscv_has_ext(env, RVH)) { | |
287 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause); | |
288 | } | |
289 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval); | |
ac12b601 | 290 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->stval); |
df30e652 AF |
291 | if (riscv_has_ext(env, RVH)) { |
292 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval); | |
293 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2); | |
294 | } | |
dc5bd18f MC |
295 | #endif |
296 | ||
297 | for (i = 0; i < 32; i++) { | |
90c84c56 MA |
298 | qemu_fprintf(f, " %s " TARGET_FMT_lx, |
299 | riscv_int_regnames[i], env->gpr[i]); | |
dc5bd18f | 300 | if ((i & 3) == 3) { |
90c84c56 | 301 | qemu_fprintf(f, "\n"); |
dc5bd18f MC |
302 | } |
303 | } | |
86ea1880 RH |
304 | if (flags & CPU_DUMP_FPU) { |
305 | for (i = 0; i < 32; i++) { | |
90c84c56 MA |
306 | qemu_fprintf(f, " %s %016" PRIx64, |
307 | riscv_fpr_regnames[i], env->fpr[i]); | |
86ea1880 | 308 | if ((i & 3) == 3) { |
90c84c56 | 309 | qemu_fprintf(f, "\n"); |
86ea1880 | 310 | } |
dc5bd18f MC |
311 | } |
312 | } | |
313 | } | |
314 | ||
315 | static void riscv_cpu_set_pc(CPUState *cs, vaddr value) | |
316 | { | |
317 | RISCVCPU *cpu = RISCV_CPU(cs); | |
318 | CPURISCVState *env = &cpu->env; | |
319 | env->pc = value; | |
320 | } | |
321 | ||
04a37d4c RH |
322 | static void riscv_cpu_synchronize_from_tb(CPUState *cs, |
323 | const TranslationBlock *tb) | |
dc5bd18f MC |
324 | { |
325 | RISCVCPU *cpu = RISCV_CPU(cs); | |
326 | CPURISCVState *env = &cpu->env; | |
327 | env->pc = tb->pc; | |
328 | } | |
329 | ||
330 | static bool riscv_cpu_has_work(CPUState *cs) | |
331 | { | |
332 | #ifndef CONFIG_USER_ONLY | |
333 | RISCVCPU *cpu = RISCV_CPU(cs); | |
334 | CPURISCVState *env = &cpu->env; | |
335 | /* | |
336 | * Definition of the WFI instruction requires it to ignore the privilege | |
337 | * mode and delegation registers, but respect individual enables | |
338 | */ | |
7ec5d303 | 339 | return (env->mip & env->mie) != 0; |
dc5bd18f MC |
340 | #else |
341 | return true; | |
342 | #endif | |
343 | } | |
344 | ||
345 | void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, | |
346 | target_ulong *data) | |
347 | { | |
348 | env->pc = data[0]; | |
349 | } | |
350 | ||
781c67ca | 351 | static void riscv_cpu_reset(DeviceState *dev) |
dc5bd18f | 352 | { |
781c67ca | 353 | CPUState *cs = CPU(dev); |
dc5bd18f MC |
354 | RISCVCPU *cpu = RISCV_CPU(cs); |
355 | RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); | |
356 | CPURISCVState *env = &cpu->env; | |
357 | ||
781c67ca | 358 | mcc->parent_reset(dev); |
dc5bd18f MC |
359 | #ifndef CONFIG_USER_ONLY |
360 | env->priv = PRV_M; | |
361 | env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); | |
362 | env->mcause = 0; | |
363 | env->pc = env->resetvec; | |
ec352d0c | 364 | env->two_stage_lookup = false; |
dc5bd18f | 365 | #endif |
330d2ae3 | 366 | cs->exception_index = RISCV_EXCP_NONE; |
c13b169f | 367 | env->load_res = -1; |
dc5bd18f MC |
368 | set_default_nan_mode(1, &env->fp_status); |
369 | } | |
370 | ||
371 | static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) | |
372 | { | |
5c5a47f1 AF |
373 | RISCVCPU *cpu = RISCV_CPU(s); |
374 | if (riscv_cpu_is_32bit(&cpu->env)) { | |
375 | info->print_insn = print_insn_riscv32; | |
376 | } else { | |
377 | info->print_insn = print_insn_riscv64; | |
378 | } | |
dc5bd18f MC |
379 | } |
380 | ||
381 | static void riscv_cpu_realize(DeviceState *dev, Error **errp) | |
382 | { | |
383 | CPUState *cs = CPU(dev); | |
c4e95030 AF |
384 | RISCVCPU *cpu = RISCV_CPU(dev); |
385 | CPURISCVState *env = &cpu->env; | |
dc5bd18f | 386 | RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); |
e3147506 | 387 | int priv_version = PRIV_VERSION_1_11_0; |
32931383 | 388 | int vext_version = VEXT_VERSION_0_07_1; |
094b072c | 389 | target_ulong target_misa = env->misa; |
dc5bd18f MC |
390 | Error *local_err = NULL; |
391 | ||
392 | cpu_exec_realizefn(cs, &local_err); | |
393 | if (local_err != NULL) { | |
394 | error_propagate(errp, local_err); | |
395 | return; | |
396 | } | |
397 | ||
c4e95030 | 398 | if (cpu->cfg.priv_spec) { |
e3147506 AF |
399 | if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { |
400 | priv_version = PRIV_VERSION_1_11_0; | |
401 | } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { | |
c4e95030 | 402 | priv_version = PRIV_VERSION_1_10_0; |
c4e95030 AF |
403 | } else { |
404 | error_setg(errp, | |
405 | "Unsupported privilege spec version '%s'", | |
406 | cpu->cfg.priv_spec); | |
407 | return; | |
408 | } | |
409 | } | |
410 | ||
c9a73910 | 411 | set_priv_version(env, priv_version); |
32931383 | 412 | set_vext_version(env, vext_version); |
c4e95030 AF |
413 | |
414 | if (cpu->cfg.mmu) { | |
415 | set_feature(env, RISCV_FEATURE_MMU); | |
416 | } | |
417 | ||
418 | if (cpu->cfg.pmp) { | |
419 | set_feature(env, RISCV_FEATURE_PMP); | |
5da9514e HW |
420 | |
421 | /* | |
422 | * Enhanced PMP should only be available | |
423 | * on harts with PMP support | |
424 | */ | |
425 | if (cpu->cfg.epmp) { | |
426 | set_feature(env, RISCV_FEATURE_EPMP); | |
427 | } | |
c4e95030 AF |
428 | } |
429 | ||
73f6ed97 BM |
430 | set_resetvec(env, cpu->cfg.resetvec); |
431 | ||
094b072c AF |
432 | /* If only XLEN is set for misa, then set misa from properties */ |
433 | if (env->misa == RV32 || env->misa == RV64) { | |
b55d7d34 AF |
434 | /* Do some ISA extension error checking */ |
435 | if (cpu->cfg.ext_i && cpu->cfg.ext_e) { | |
436 | error_setg(errp, | |
437 | "I and E extensions are incompatible"); | |
438 | return; | |
439 | } | |
440 | ||
bdddd446 AF |
441 | if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { |
442 | error_setg(errp, | |
443 | "Either I or E extension must be set"); | |
444 | return; | |
445 | } | |
446 | ||
b55d7d34 AF |
447 | if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & |
448 | cpu->cfg.ext_a & cpu->cfg.ext_f & | |
449 | cpu->cfg.ext_d)) { | |
450 | warn_report("Setting G will also set IMAFD"); | |
451 | cpu->cfg.ext_i = true; | |
452 | cpu->cfg.ext_m = true; | |
453 | cpu->cfg.ext_a = true; | |
454 | cpu->cfg.ext_f = true; | |
455 | cpu->cfg.ext_d = true; | |
456 | } | |
457 | ||
458 | /* Set the ISA extensions, checks should have happened above */ | |
459 | if (cpu->cfg.ext_i) { | |
460 | target_misa |= RVI; | |
461 | } | |
462 | if (cpu->cfg.ext_e) { | |
463 | target_misa |= RVE; | |
464 | } | |
465 | if (cpu->cfg.ext_m) { | |
466 | target_misa |= RVM; | |
467 | } | |
468 | if (cpu->cfg.ext_a) { | |
469 | target_misa |= RVA; | |
470 | } | |
471 | if (cpu->cfg.ext_f) { | |
472 | target_misa |= RVF; | |
473 | } | |
474 | if (cpu->cfg.ext_d) { | |
475 | target_misa |= RVD; | |
476 | } | |
477 | if (cpu->cfg.ext_c) { | |
478 | target_misa |= RVC; | |
479 | } | |
480 | if (cpu->cfg.ext_s) { | |
481 | target_misa |= RVS; | |
482 | } | |
483 | if (cpu->cfg.ext_u) { | |
484 | target_misa |= RVU; | |
485 | } | |
c9eefe05 AF |
486 | if (cpu->cfg.ext_h) { |
487 | target_misa |= RVH; | |
488 | } | |
6bf91617 LZ |
489 | if (cpu->cfg.ext_v) { |
490 | target_misa |= RVV; | |
491 | if (!is_power_of_2(cpu->cfg.vlen)) { | |
492 | error_setg(errp, | |
493 | "Vector extension VLEN must be power of 2"); | |
494 | return; | |
495 | } | |
496 | if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { | |
497 | error_setg(errp, | |
498 | "Vector extension implementation only supports VLEN " | |
499 | "in the range [128, %d]", RV_VLEN_MAX); | |
500 | return; | |
501 | } | |
502 | if (!is_power_of_2(cpu->cfg.elen)) { | |
503 | error_setg(errp, | |
504 | "Vector extension ELEN must be power of 2"); | |
505 | return; | |
506 | } | |
507 | if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) { | |
508 | error_setg(errp, | |
509 | "Vector extension implementation only supports ELEN " | |
510 | "in the range [8, 64]"); | |
511 | return; | |
512 | } | |
513 | if (cpu->cfg.vext_spec) { | |
514 | if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) { | |
515 | vext_version = VEXT_VERSION_0_07_1; | |
516 | } else { | |
517 | error_setg(errp, | |
518 | "Unsupported vector spec version '%s'", | |
519 | cpu->cfg.vext_spec); | |
520 | return; | |
521 | } | |
522 | } else { | |
cba42d61 | 523 | qemu_log("vector version is not specified, " |
6bf91617 LZ |
524 | "use the default value v0.7.1\n"); |
525 | } | |
526 | set_vext_version(env, vext_version); | |
527 | } | |
b55d7d34 | 528 | |
094b072c | 529 | set_misa(env, target_misa); |
b55d7d34 AF |
530 | } |
531 | ||
5371f5cd JW |
532 | riscv_cpu_register_gdb_regs_for_features(cs); |
533 | ||
dc5bd18f MC |
534 | qemu_init_vcpu(cs); |
535 | cpu_reset(cs); | |
536 | ||
537 | mcc->parent_realize(dev, errp); | |
538 | } | |
539 | ||
540 | static void riscv_cpu_init(Object *obj) | |
541 | { | |
dc5bd18f MC |
542 | RISCVCPU *cpu = RISCV_CPU(obj); |
543 | ||
7506ed90 | 544 | cpu_set_cpustate_pointers(cpu); |
dc5bd18f MC |
545 | } |
546 | ||
c4e95030 | 547 | static Property riscv_cpu_properties[] = { |
b55d7d34 AF |
548 | DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), |
549 | DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), | |
550 | DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true), | |
551 | DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), | |
552 | DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), | |
553 | DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), | |
554 | DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), | |
555 | DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), | |
556 | DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), | |
557 | DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), | |
c9eefe05 AF |
558 | /* This is experimental so mark with 'x-' */ |
559 | DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), | |
6bf91617 | 560 | DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), |
0a13a5b8 | 561 | DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), |
50fba816 | 562 | DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), |
591bddea | 563 | DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), |
c4e95030 | 564 | DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), |
6bf91617 LZ |
565 | DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), |
566 | DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), | |
567 | DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), | |
c4e95030 AF |
568 | DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), |
569 | DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), | |
5da9514e HW |
570 | DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), |
571 | ||
9b4c9b2b | 572 | DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), |
c4e95030 AF |
573 | DEFINE_PROP_END_OF_LIST(), |
574 | }; | |
575 | ||
edf64786 SP |
576 | static gchar *riscv_gdb_arch_name(CPUState *cs) |
577 | { | |
578 | RISCVCPU *cpu = RISCV_CPU(cs); | |
579 | CPURISCVState *env = &cpu->env; | |
580 | ||
581 | if (riscv_cpu_is_32bit(env)) { | |
582 | return g_strdup("riscv:rv32"); | |
583 | } else { | |
584 | return g_strdup("riscv:rv64"); | |
585 | } | |
586 | } | |
587 | ||
b93777e1 BM |
588 | static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) |
589 | { | |
590 | RISCVCPU *cpu = RISCV_CPU(cs); | |
591 | ||
592 | if (strcmp(xmlname, "riscv-csr.xml") == 0) { | |
593 | return cpu->dyn_csr_xml; | |
594 | } | |
595 | ||
596 | return NULL; | |
597 | } | |
598 | ||
78271684 CF |
599 | #include "hw/core/tcg-cpu-ops.h" |
600 | ||
601 | static struct TCGCPUOps riscv_tcg_ops = { | |
602 | .initialize = riscv_translate_init, | |
603 | .synchronize_from_tb = riscv_cpu_synchronize_from_tb, | |
604 | .cpu_exec_interrupt = riscv_cpu_exec_interrupt, | |
605 | .tlb_fill = riscv_cpu_tlb_fill, | |
606 | ||
607 | #ifndef CONFIG_USER_ONLY | |
608 | .do_interrupt = riscv_cpu_do_interrupt, | |
609 | .do_transaction_failed = riscv_cpu_do_transaction_failed, | |
610 | .do_unaligned_access = riscv_cpu_do_unaligned_access, | |
611 | #endif /* !CONFIG_USER_ONLY */ | |
612 | }; | |
613 | ||
dc5bd18f MC |
614 | static void riscv_cpu_class_init(ObjectClass *c, void *data) |
615 | { | |
616 | RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); | |
617 | CPUClass *cc = CPU_CLASS(c); | |
618 | DeviceClass *dc = DEVICE_CLASS(c); | |
619 | ||
41fbbba7 MZ |
620 | device_class_set_parent_realize(dc, riscv_cpu_realize, |
621 | &mcc->parent_realize); | |
dc5bd18f | 622 | |
781c67ca | 623 | device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset); |
dc5bd18f MC |
624 | |
625 | cc->class_by_name = riscv_cpu_class_by_name; | |
626 | cc->has_work = riscv_cpu_has_work; | |
dc5bd18f MC |
627 | cc->dump_state = riscv_cpu_dump_state; |
628 | cc->set_pc = riscv_cpu_set_pc; | |
dc5bd18f MC |
629 | cc->gdb_read_register = riscv_cpu_gdb_read_register; |
630 | cc->gdb_write_register = riscv_cpu_gdb_write_register; | |
5371f5cd JW |
631 | cc->gdb_num_core_regs = 33; |
632 | #if defined(TARGET_RISCV32) | |
633 | cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; | |
634 | #elif defined(TARGET_RISCV64) | |
635 | cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; | |
636 | #endif | |
dc5bd18f MC |
637 | cc->gdb_stop_before_watchpoint = true; |
638 | cc->disas_set_info = riscv_cpu_disas_set_info; | |
8a4ca3c1 | 639 | #ifndef CONFIG_USER_ONLY |
dc5bd18f | 640 | cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug; |
744c72a8 | 641 | cc->legacy_vmsd = &vmstate_riscv_cpu; |
43a96588 YJ |
642 | cc->write_elf64_note = riscv_cpu_write_elf64_note; |
643 | cc->write_elf32_note = riscv_cpu_write_elf32_note; | |
dc5bd18f | 644 | #endif |
edf64786 | 645 | cc->gdb_arch_name = riscv_gdb_arch_name; |
b93777e1 | 646 | cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; |
78271684 | 647 | cc->tcg_ops = &riscv_tcg_ops; |
6a3d2e7c | 648 | |
4f67d30b | 649 | device_class_set_props(dc, riscv_cpu_properties); |
dc5bd18f MC |
650 | } |
651 | ||
dc5bd18f MC |
652 | char *riscv_isa_string(RISCVCPU *cpu) |
653 | { | |
654 | int i; | |
d1fd31f8 MC |
655 | const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1; |
656 | char *isa_str = g_new(char, maxlen); | |
657 | char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); | |
dc5bd18f MC |
658 | for (i = 0; i < sizeof(riscv_exts); i++) { |
659 | if (cpu->env.misa & RV(riscv_exts[i])) { | |
d1fd31f8 | 660 | *p++ = qemu_tolower(riscv_exts[i]); |
dc5bd18f MC |
661 | } |
662 | } | |
d1fd31f8 MC |
663 | *p = '\0'; |
664 | return isa_str; | |
dc5bd18f MC |
665 | } |
666 | ||
eab15862 | 667 | static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) |
dc5bd18f | 668 | { |
eab15862 MC |
669 | ObjectClass *class_a = (ObjectClass *)a; |
670 | ObjectClass *class_b = (ObjectClass *)b; | |
671 | const char *name_a, *name_b; | |
dc5bd18f | 672 | |
eab15862 MC |
673 | name_a = object_class_get_name(class_a); |
674 | name_b = object_class_get_name(class_b); | |
675 | return strcmp(name_a, name_b); | |
dc5bd18f MC |
676 | } |
677 | ||
eab15862 | 678 | static void riscv_cpu_list_entry(gpointer data, gpointer user_data) |
dc5bd18f | 679 | { |
eab15862 MC |
680 | const char *typename = object_class_get_name(OBJECT_CLASS(data)); |
681 | int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); | |
dc5bd18f | 682 | |
0442428a | 683 | qemu_printf("%.*s\n", len, typename); |
eab15862 | 684 | } |
dc5bd18f | 685 | |
0442428a | 686 | void riscv_cpu_list(void) |
eab15862 | 687 | { |
eab15862 MC |
688 | GSList *list; |
689 | ||
690 | list = object_class_get_list(TYPE_RISCV_CPU, false); | |
691 | list = g_slist_sort(list, riscv_cpu_list_compare); | |
0442428a | 692 | g_slist_foreach(list, riscv_cpu_list_entry, NULL); |
eab15862 | 693 | g_slist_free(list); |
dc5bd18f MC |
694 | } |
695 | ||
eab15862 MC |
696 | #define DEFINE_CPU(type_name, initfn) \ |
697 | { \ | |
698 | .name = type_name, \ | |
699 | .parent = TYPE_RISCV_CPU, \ | |
700 | .instance_init = initfn \ | |
701 | } | |
702 | ||
703 | static const TypeInfo riscv_cpu_type_infos[] = { | |
704 | { | |
705 | .name = TYPE_RISCV_CPU, | |
706 | .parent = TYPE_CPU, | |
707 | .instance_size = sizeof(RISCVCPU), | |
5de5b99b | 708 | .instance_align = __alignof__(RISCVCPU), |
eab15862 MC |
709 | .instance_init = riscv_cpu_init, |
710 | .abstract = true, | |
711 | .class_size = sizeof(RISCVCPUClass), | |
712 | .class_init = riscv_cpu_class_init, | |
713 | }, | |
714 | DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), | |
715 | #if defined(TARGET_RISCV32) | |
094b072c | 716 | DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), |
e8905c6c | 717 | DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), |
114baaca | 718 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), |
2fdd2c09 | 719 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), |
114baaca | 720 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), |
eab15862 | 721 | #elif defined(TARGET_RISCV64) |
094b072c | 722 | DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), |
114baaca AF |
723 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), |
724 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), | |
6ddc7069 | 725 | DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), |
eab15862 MC |
726 | #endif |
727 | }; | |
728 | ||
729 | DEFINE_TYPES(riscv_cpu_type_infos) |