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dc5bd18f MC |
1 | /* |
2 | * QEMU RISC-V CPU | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
0442428a | 21 | #include "qemu/qemu-print.h" |
856dfd8a | 22 | #include "qemu/ctype.h" |
dc5bd18f MC |
23 | #include "qemu/log.h" |
24 | #include "cpu.h" | |
f7697f0e | 25 | #include "internals.h" |
dc5bd18f MC |
26 | #include "exec/exec-all.h" |
27 | #include "qapi/error.h" | |
b55d7d34 | 28 | #include "qemu/error-report.h" |
c4e95030 | 29 | #include "hw/qdev-properties.h" |
dc5bd18f | 30 | #include "migration/vmstate.h" |
135b03cb | 31 | #include "fpu/softfloat-helpers.h" |
ad40be27 YJ |
32 | #include "sysemu/kvm.h" |
33 | #include "kvm_riscv.h" | |
dc5bd18f MC |
34 | |
35 | /* RISC-V CPU definitions */ | |
36 | ||
79f86934 | 37 | static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG"; |
dc5bd18f MC |
38 | |
39 | const char * const riscv_int_regnames[] = { | |
a9f37afa AP |
40 | "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", |
41 | "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", | |
42 | "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", | |
43 | "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", | |
44 | "x28/t3", "x29/t4", "x30/t5", "x31/t6" | |
dc5bd18f MC |
45 | }; |
46 | ||
2b547084 FP |
47 | const char * const riscv_int_regnamesh[] = { |
48 | "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", | |
49 | "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", | |
50 | "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", | |
51 | "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", | |
52 | "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", | |
53 | "x30h/t5h", "x31h/t6h" | |
54 | }; | |
55 | ||
dc5bd18f | 56 | const char * const riscv_fpr_regnames[] = { |
a9f37afa AP |
57 | "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", |
58 | "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", | |
59 | "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", | |
60 | "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", | |
61 | "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", | |
62 | "f30/ft10", "f31/ft11" | |
dc5bd18f MC |
63 | }; |
64 | ||
9a575d33 | 65 | static const char * const riscv_excp_names[] = { |
dc5bd18f MC |
66 | "misaligned_fetch", |
67 | "fault_fetch", | |
68 | "illegal_instruction", | |
69 | "breakpoint", | |
70 | "misaligned_load", | |
71 | "fault_load", | |
72 | "misaligned_store", | |
73 | "fault_store", | |
74 | "user_ecall", | |
75 | "supervisor_ecall", | |
76 | "hypervisor_ecall", | |
77 | "machine_ecall", | |
78 | "exec_page_fault", | |
79 | "load_page_fault", | |
80 | "reserved", | |
fd990e86 | 81 | "store_page_fault", |
ab67a1d0 AF |
82 | "reserved", |
83 | "reserved", | |
84 | "reserved", | |
85 | "reserved", | |
86 | "guest_exec_page_fault", | |
87 | "guest_load_page_fault", | |
88 | "reserved", | |
fd990e86 | 89 | "guest_store_page_fault", |
dc5bd18f MC |
90 | }; |
91 | ||
9a575d33 | 92 | static const char * const riscv_intr_names[] = { |
dc5bd18f MC |
93 | "u_software", |
94 | "s_software", | |
205377f8 | 95 | "vs_software", |
dc5bd18f MC |
96 | "m_software", |
97 | "u_timer", | |
98 | "s_timer", | |
205377f8 | 99 | "vs_timer", |
dc5bd18f MC |
100 | "m_timer", |
101 | "u_external", | |
6cfcf775 | 102 | "s_external", |
205377f8 | 103 | "vs_external", |
dc5bd18f | 104 | "m_external", |
426f0348 MC |
105 | "reserved", |
106 | "reserved", | |
107 | "reserved", | |
108 | "reserved" | |
dc5bd18f MC |
109 | }; |
110 | ||
c51a3f5d YJ |
111 | const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) |
112 | { | |
113 | if (async) { | |
114 | return (cause < ARRAY_SIZE(riscv_intr_names)) ? | |
115 | riscv_intr_names[cause] : "(unknown)"; | |
116 | } else { | |
117 | return (cause < ARRAY_SIZE(riscv_excp_names)) ? | |
118 | riscv_excp_names[cause] : "(unknown)"; | |
119 | } | |
120 | } | |
121 | ||
e91a7227 | 122 | static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) |
dc5bd18f | 123 | { |
e91a7227 RH |
124 | env->misa_mxl_max = env->misa_mxl = mxl; |
125 | env->misa_ext_mask = env->misa_ext = ext; | |
dc5bd18f MC |
126 | } |
127 | ||
c9a73910 | 128 | static void set_priv_version(CPURISCVState *env, int priv_ver) |
dc5bd18f | 129 | { |
dc5bd18f MC |
130 | env->priv_ver = priv_ver; |
131 | } | |
132 | ||
32931383 LZ |
133 | static void set_vext_version(CPURISCVState *env, int vext_ver) |
134 | { | |
135 | env->vext_ver = vext_ver; | |
136 | } | |
137 | ||
01e723bf | 138 | static void set_resetvec(CPURISCVState *env, target_ulong resetvec) |
dc5bd18f MC |
139 | { |
140 | #ifndef CONFIG_USER_ONLY | |
141 | env->resetvec = resetvec; | |
142 | #endif | |
143 | } | |
144 | ||
145 | static void riscv_any_cpu_init(Object *obj) | |
146 | { | |
147 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
3820602f | 148 | #if defined(TARGET_RISCV32) |
e91a7227 | 149 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); |
3820602f | 150 | #elif defined(TARGET_RISCV64) |
e91a7227 | 151 | set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); |
3820602f | 152 | #endif |
c9a73910 | 153 | set_priv_version(env, PRIV_VERSION_1_11_0); |
dc5bd18f MC |
154 | } |
155 | ||
094b072c AF |
156 | #if defined(TARGET_RISCV64) |
157 | static void rv64_base_cpu_init(Object *obj) | |
8903bf6e AF |
158 | { |
159 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
b55d7d34 | 160 | /* We set this in the realise function */ |
e91a7227 | 161 | set_misa(env, MXL_RV64, 0); |
8903bf6e AF |
162 | } |
163 | ||
114baaca | 164 | static void rv64_sifive_u_cpu_init(Object *obj) |
dc5bd18f MC |
165 | { |
166 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
e91a7227 | 167 | set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); |
c9a73910 | 168 | set_priv_version(env, PRIV_VERSION_1_10_0); |
dc5bd18f MC |
169 | } |
170 | ||
114baaca | 171 | static void rv64_sifive_e_cpu_init(Object *obj) |
36b80ad9 AF |
172 | { |
173 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
e91a7227 | 174 | set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); |
36b80ad9 | 175 | set_priv_version(env, PRIV_VERSION_1_10_0); |
36b80ad9 AF |
176 | qdev_prop_set_bit(DEVICE(obj), "mmu", false); |
177 | } | |
332dab68 FP |
178 | |
179 | static void rv128_base_cpu_init(Object *obj) | |
180 | { | |
181 | if (qemu_tcg_mttcg_enabled()) { | |
182 | /* Missing 128-bit aligned atomics */ | |
183 | error_report("128-bit RISC-V currently does not work with Multi " | |
184 | "Threaded TCG. Please use: -accel tcg,thread=single"); | |
185 | exit(EXIT_FAILURE); | |
186 | } | |
187 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
188 | /* We set this in the realise function */ | |
189 | set_misa(env, MXL_RV128, 0); | |
190 | } | |
114baaca | 191 | #else |
094b072c AF |
192 | static void rv32_base_cpu_init(Object *obj) |
193 | { | |
194 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
195 | /* We set this in the realise function */ | |
e91a7227 | 196 | set_misa(env, MXL_RV32, 0); |
094b072c AF |
197 | } |
198 | ||
114baaca AF |
199 | static void rv32_sifive_u_cpu_init(Object *obj) |
200 | { | |
201 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
e91a7227 | 202 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); |
114baaca AF |
203 | set_priv_version(env, PRIV_VERSION_1_10_0); |
204 | } | |
36b80ad9 | 205 | |
114baaca AF |
206 | static void rv32_sifive_e_cpu_init(Object *obj) |
207 | { | |
208 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
e91a7227 | 209 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); |
114baaca AF |
210 | set_priv_version(env, PRIV_VERSION_1_10_0); |
211 | qdev_prop_set_bit(DEVICE(obj), "mmu", false); | |
212 | } | |
d8e72bd1 | 213 | |
e8905c6c | 214 | static void rv32_ibex_cpu_init(Object *obj) |
dc5bd18f MC |
215 | { |
216 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
e91a7227 | 217 | set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); |
c9a73910 | 218 | set_priv_version(env, PRIV_VERSION_1_10_0); |
8be6971b | 219 | qdev_prop_set_bit(DEVICE(obj), "mmu", false); |
ed6eebaa | 220 | qdev_prop_set_bit(DEVICE(obj), "x-epmp", true); |
dc5bd18f MC |
221 | } |
222 | ||
2fdd2c09 | 223 | static void rv32_imafcu_nommu_cpu_init(Object *obj) |
d784733b CW |
224 | { |
225 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
e91a7227 | 226 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); |
d784733b CW |
227 | set_priv_version(env, PRIV_VERSION_1_10_0); |
228 | set_resetvec(env, DEFAULT_RSTVEC); | |
8be6971b | 229 | qdev_prop_set_bit(DEVICE(obj), "mmu", false); |
d784733b | 230 | } |
eab15862 | 231 | #endif |
dc5bd18f | 232 | |
10f1ca27 YJ |
233 | #if defined(CONFIG_KVM) |
234 | static void riscv_host_cpu_init(Object *obj) | |
235 | { | |
236 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
237 | #if defined(TARGET_RISCV32) | |
238 | set_misa(env, MXL_RV32, 0); | |
239 | #elif defined(TARGET_RISCV64) | |
240 | set_misa(env, MXL_RV64, 0); | |
241 | #endif | |
242 | } | |
243 | #endif | |
244 | ||
dc5bd18f MC |
245 | static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) |
246 | { | |
247 | ObjectClass *oc; | |
248 | char *typename; | |
249 | char **cpuname; | |
250 | ||
251 | cpuname = g_strsplit(cpu_model, ",", 1); | |
252 | typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); | |
253 | oc = object_class_by_name(typename); | |
254 | g_strfreev(cpuname); | |
255 | g_free(typename); | |
256 | if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || | |
257 | object_class_is_abstract(oc)) { | |
258 | return NULL; | |
259 | } | |
260 | return oc; | |
261 | } | |
262 | ||
90c84c56 | 263 | static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) |
dc5bd18f MC |
264 | { |
265 | RISCVCPU *cpu = RISCV_CPU(cs); | |
266 | CPURISCVState *env = &cpu->env; | |
267 | int i; | |
268 | ||
df30e652 AF |
269 | #if !defined(CONFIG_USER_ONLY) |
270 | if (riscv_has_ext(env, RVH)) { | |
271 | qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); | |
272 | } | |
273 | #endif | |
90c84c56 | 274 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); |
dc5bd18f | 275 | #ifndef CONFIG_USER_ONLY |
665b90d8 RH |
276 | { |
277 | static const int dump_csrs[] = { | |
278 | CSR_MHARTID, | |
279 | CSR_MSTATUS, | |
280 | CSR_MSTATUSH, | |
281 | CSR_HSTATUS, | |
282 | CSR_VSSTATUS, | |
283 | CSR_MIP, | |
284 | CSR_MIE, | |
285 | CSR_MIDELEG, | |
286 | CSR_HIDELEG, | |
287 | CSR_MEDELEG, | |
288 | CSR_HEDELEG, | |
289 | CSR_MTVEC, | |
290 | CSR_STVEC, | |
291 | CSR_VSTVEC, | |
292 | CSR_MEPC, | |
293 | CSR_SEPC, | |
294 | CSR_VSEPC, | |
295 | CSR_MCAUSE, | |
296 | CSR_SCAUSE, | |
297 | CSR_VSCAUSE, | |
298 | CSR_MTVAL, | |
299 | CSR_STVAL, | |
300 | CSR_HTVAL, | |
301 | CSR_MTVAL2, | |
302 | CSR_MSCRATCH, | |
303 | CSR_SSCRATCH, | |
304 | CSR_SATP, | |
bd5594ca AB |
305 | CSR_MMTE, |
306 | CSR_UPMBASE, | |
307 | CSR_UPMMASK, | |
308 | CSR_SPMBASE, | |
309 | CSR_SPMMASK, | |
310 | CSR_MPMBASE, | |
311 | CSR_MPMMASK, | |
665b90d8 RH |
312 | }; |
313 | ||
314 | for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { | |
315 | int csrno = dump_csrs[i]; | |
316 | target_ulong val = 0; | |
317 | RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); | |
318 | ||
319 | /* | |
320 | * Rely on the smode, hmode, etc, predicates within csr.c | |
321 | * to do the filtering of the registers that are present. | |
322 | */ | |
323 | if (res == RISCV_EXCP_NONE) { | |
324 | qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", | |
325 | csr_ops[csrno].name, val); | |
326 | } | |
327 | } | |
df30e652 | 328 | } |
dc5bd18f MC |
329 | #endif |
330 | ||
331 | for (i = 0; i < 32; i++) { | |
e573a7f3 | 332 | qemu_fprintf(f, " %-8s " TARGET_FMT_lx, |
90c84c56 | 333 | riscv_int_regnames[i], env->gpr[i]); |
dc5bd18f | 334 | if ((i & 3) == 3) { |
90c84c56 | 335 | qemu_fprintf(f, "\n"); |
dc5bd18f MC |
336 | } |
337 | } | |
86ea1880 RH |
338 | if (flags & CPU_DUMP_FPU) { |
339 | for (i = 0; i < 32; i++) { | |
e573a7f3 | 340 | qemu_fprintf(f, " %-8s %016" PRIx64, |
90c84c56 | 341 | riscv_fpr_regnames[i], env->fpr[i]); |
86ea1880 | 342 | if ((i & 3) == 3) { |
90c84c56 | 343 | qemu_fprintf(f, "\n"); |
86ea1880 | 344 | } |
dc5bd18f MC |
345 | } |
346 | } | |
347 | } | |
348 | ||
349 | static void riscv_cpu_set_pc(CPUState *cs, vaddr value) | |
350 | { | |
351 | RISCVCPU *cpu = RISCV_CPU(cs); | |
352 | CPURISCVState *env = &cpu->env; | |
bf9e776e LZ |
353 | |
354 | if (env->xl == MXL_RV32) { | |
355 | env->pc = (int32_t)value; | |
356 | } else { | |
357 | env->pc = value; | |
358 | } | |
dc5bd18f MC |
359 | } |
360 | ||
04a37d4c RH |
361 | static void riscv_cpu_synchronize_from_tb(CPUState *cs, |
362 | const TranslationBlock *tb) | |
dc5bd18f MC |
363 | { |
364 | RISCVCPU *cpu = RISCV_CPU(cs); | |
365 | CPURISCVState *env = &cpu->env; | |
bf9e776e LZ |
366 | RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); |
367 | ||
368 | if (xl == MXL_RV32) { | |
369 | env->pc = (int32_t)tb->pc; | |
370 | } else { | |
371 | env->pc = tb->pc; | |
372 | } | |
dc5bd18f MC |
373 | } |
374 | ||
375 | static bool riscv_cpu_has_work(CPUState *cs) | |
376 | { | |
377 | #ifndef CONFIG_USER_ONLY | |
378 | RISCVCPU *cpu = RISCV_CPU(cs); | |
379 | CPURISCVState *env = &cpu->env; | |
380 | /* | |
381 | * Definition of the WFI instruction requires it to ignore the privilege | |
382 | * mode and delegation registers, but respect individual enables | |
383 | */ | |
7ec5d303 | 384 | return (env->mip & env->mie) != 0; |
dc5bd18f MC |
385 | #else |
386 | return true; | |
387 | #endif | |
388 | } | |
389 | ||
390 | void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, | |
391 | target_ulong *data) | |
392 | { | |
bf9e776e LZ |
393 | RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); |
394 | if (xl == MXL_RV32) { | |
395 | env->pc = (int32_t)data[0]; | |
396 | } else { | |
397 | env->pc = data[0]; | |
398 | } | |
dc5bd18f MC |
399 | } |
400 | ||
781c67ca | 401 | static void riscv_cpu_reset(DeviceState *dev) |
dc5bd18f | 402 | { |
43dc93af AP |
403 | #ifndef CONFIG_USER_ONLY |
404 | uint8_t iprio; | |
405 | int i, irq, rdzero; | |
406 | #endif | |
781c67ca | 407 | CPUState *cs = CPU(dev); |
dc5bd18f MC |
408 | RISCVCPU *cpu = RISCV_CPU(cs); |
409 | RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); | |
410 | CPURISCVState *env = &cpu->env; | |
411 | ||
781c67ca | 412 | mcc->parent_reset(dev); |
dc5bd18f | 413 | #ifndef CONFIG_USER_ONLY |
e91a7227 | 414 | env->misa_mxl = env->misa_mxl_max; |
dc5bd18f MC |
415 | env->priv = PRV_M; |
416 | env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); | |
92371bd9 RH |
417 | if (env->misa_mxl > MXL_RV32) { |
418 | /* | |
419 | * The reset status of SXL/UXL is undefined, but mstatus is WARL | |
420 | * and we must ensure that the value after init is valid for read. | |
421 | */ | |
422 | env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); | |
423 | env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); | |
5a2ae235 LZ |
424 | if (riscv_has_ext(env, RVH)) { |
425 | env->vsstatus = set_field(env->vsstatus, | |
426 | MSTATUS64_SXL, env->misa_mxl); | |
427 | env->vsstatus = set_field(env->vsstatus, | |
428 | MSTATUS64_UXL, env->misa_mxl); | |
429 | env->mstatus_hs = set_field(env->mstatus_hs, | |
430 | MSTATUS64_SXL, env->misa_mxl); | |
431 | env->mstatus_hs = set_field(env->mstatus_hs, | |
432 | MSTATUS64_UXL, env->misa_mxl); | |
433 | } | |
92371bd9 | 434 | } |
dc5bd18f | 435 | env->mcause = 0; |
881df35d | 436 | env->miclaim = MIP_SGEIP; |
dc5bd18f | 437 | env->pc = env->resetvec; |
ec352d0c | 438 | env->two_stage_lookup = false; |
43dc93af AP |
439 | |
440 | /* Initialized default priorities of local interrupts. */ | |
441 | for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { | |
442 | iprio = riscv_cpu_default_priority(i); | |
443 | env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio; | |
444 | env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio; | |
445 | env->hviprio[i] = 0; | |
446 | } | |
447 | i = 0; | |
448 | while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) { | |
449 | if (!rdzero) { | |
450 | env->hviprio[irq] = env->miprio[irq]; | |
451 | } | |
452 | i++; | |
453 | } | |
4bbe8033 AB |
454 | /* mmte is supposed to have pm.current hardwired to 1 */ |
455 | env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); | |
dc5bd18f | 456 | #endif |
440544e1 | 457 | env->xl = riscv_cpu_mxl(env); |
40bfa5f6 | 458 | riscv_cpu_update_mask(env); |
330d2ae3 | 459 | cs->exception_index = RISCV_EXCP_NONE; |
c13b169f | 460 | env->load_res = -1; |
dc5bd18f | 461 | set_default_nan_mode(1, &env->fp_status); |
ad40be27 YJ |
462 | |
463 | #ifndef CONFIG_USER_ONLY | |
464 | if (kvm_enabled()) { | |
465 | kvm_riscv_reset_vcpu(cpu); | |
466 | } | |
467 | #endif | |
dc5bd18f MC |
468 | } |
469 | ||
470 | static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) | |
471 | { | |
5c5a47f1 | 472 | RISCVCPU *cpu = RISCV_CPU(s); |
db23e5d9 RH |
473 | |
474 | switch (riscv_cpu_mxl(&cpu->env)) { | |
475 | case MXL_RV32: | |
5c5a47f1 | 476 | info->print_insn = print_insn_riscv32; |
db23e5d9 RH |
477 | break; |
478 | case MXL_RV64: | |
5c5a47f1 | 479 | info->print_insn = print_insn_riscv64; |
db23e5d9 | 480 | break; |
332dab68 FP |
481 | case MXL_RV128: |
482 | info->print_insn = print_insn_riscv128; | |
483 | break; | |
db23e5d9 RH |
484 | default: |
485 | g_assert_not_reached(); | |
5c5a47f1 | 486 | } |
dc5bd18f MC |
487 | } |
488 | ||
489 | static void riscv_cpu_realize(DeviceState *dev, Error **errp) | |
490 | { | |
491 | CPUState *cs = CPU(dev); | |
c4e95030 AF |
492 | RISCVCPU *cpu = RISCV_CPU(dev); |
493 | CPURISCVState *env = &cpu->env; | |
dc5bd18f | 494 | RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); |
1191be09 | 495 | CPUClass *cc = CPU_CLASS(mcc); |
a8b37120 | 496 | int priv_version = 0; |
dc5bd18f MC |
497 | Error *local_err = NULL; |
498 | ||
499 | cpu_exec_realizefn(cs, &local_err); | |
500 | if (local_err != NULL) { | |
501 | error_propagate(errp, local_err); | |
502 | return; | |
503 | } | |
504 | ||
c4e95030 | 505 | if (cpu->cfg.priv_spec) { |
e3147506 AF |
506 | if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { |
507 | priv_version = PRIV_VERSION_1_11_0; | |
508 | } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { | |
c4e95030 | 509 | priv_version = PRIV_VERSION_1_10_0; |
c4e95030 AF |
510 | } else { |
511 | error_setg(errp, | |
512 | "Unsupported privilege spec version '%s'", | |
513 | cpu->cfg.priv_spec); | |
514 | return; | |
515 | } | |
516 | } | |
517 | ||
a8b37120 LZ |
518 | if (priv_version) { |
519 | set_priv_version(env, priv_version); | |
520 | } else if (!env->priv_ver) { | |
521 | set_priv_version(env, PRIV_VERSION_1_11_0); | |
522 | } | |
c4e95030 AF |
523 | |
524 | if (cpu->cfg.mmu) { | |
f87adf23 | 525 | riscv_set_feature(env, RISCV_FEATURE_MMU); |
c4e95030 AF |
526 | } |
527 | ||
528 | if (cpu->cfg.pmp) { | |
f87adf23 | 529 | riscv_set_feature(env, RISCV_FEATURE_PMP); |
5da9514e HW |
530 | |
531 | /* | |
532 | * Enhanced PMP should only be available | |
533 | * on harts with PMP support | |
534 | */ | |
535 | if (cpu->cfg.epmp) { | |
f87adf23 | 536 | riscv_set_feature(env, RISCV_FEATURE_EPMP); |
5da9514e | 537 | } |
c4e95030 AF |
538 | } |
539 | ||
73f6ed97 BM |
540 | set_resetvec(env, cpu->cfg.resetvec); |
541 | ||
e91a7227 RH |
542 | /* Validate that MISA_MXL is set properly. */ |
543 | switch (env->misa_mxl_max) { | |
544 | #ifdef TARGET_RISCV64 | |
545 | case MXL_RV64: | |
332dab68 | 546 | case MXL_RV128: |
6c3a9247 | 547 | cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; |
332dab68 | 548 | break; |
e91a7227 RH |
549 | #endif |
550 | case MXL_RV32: | |
1191be09 | 551 | cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; |
e91a7227 RH |
552 | break; |
553 | default: | |
554 | g_assert_not_reached(); | |
555 | } | |
556 | assert(env->misa_mxl_max == env->misa_mxl); | |
557 | ||
558 | /* If only MISA_EXT is unset for misa, then set it from properties */ | |
559 | if (env->misa_ext == 0) { | |
560 | uint32_t ext = 0; | |
561 | ||
b55d7d34 AF |
562 | /* Do some ISA extension error checking */ |
563 | if (cpu->cfg.ext_i && cpu->cfg.ext_e) { | |
564 | error_setg(errp, | |
565 | "I and E extensions are incompatible"); | |
566 | return; | |
567 | } | |
568 | ||
bdddd446 AF |
569 | if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { |
570 | error_setg(errp, | |
571 | "Either I or E extension must be set"); | |
572 | return; | |
573 | } | |
574 | ||
b55d7d34 AF |
575 | if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & |
576 | cpu->cfg.ext_a & cpu->cfg.ext_f & | |
577 | cpu->cfg.ext_d)) { | |
578 | warn_report("Setting G will also set IMAFD"); | |
579 | cpu->cfg.ext_i = true; | |
580 | cpu->cfg.ext_m = true; | |
581 | cpu->cfg.ext_a = true; | |
582 | cpu->cfg.ext_f = true; | |
583 | cpu->cfg.ext_d = true; | |
584 | } | |
585 | ||
586 | /* Set the ISA extensions, checks should have happened above */ | |
587 | if (cpu->cfg.ext_i) { | |
e91a7227 | 588 | ext |= RVI; |
b55d7d34 AF |
589 | } |
590 | if (cpu->cfg.ext_e) { | |
e91a7227 | 591 | ext |= RVE; |
b55d7d34 AF |
592 | } |
593 | if (cpu->cfg.ext_m) { | |
e91a7227 | 594 | ext |= RVM; |
b55d7d34 AF |
595 | } |
596 | if (cpu->cfg.ext_a) { | |
e91a7227 | 597 | ext |= RVA; |
b55d7d34 AF |
598 | } |
599 | if (cpu->cfg.ext_f) { | |
e91a7227 | 600 | ext |= RVF; |
b55d7d34 AF |
601 | } |
602 | if (cpu->cfg.ext_d) { | |
e91a7227 | 603 | ext |= RVD; |
b55d7d34 AF |
604 | } |
605 | if (cpu->cfg.ext_c) { | |
e91a7227 | 606 | ext |= RVC; |
b55d7d34 AF |
607 | } |
608 | if (cpu->cfg.ext_s) { | |
e91a7227 | 609 | ext |= RVS; |
b55d7d34 AF |
610 | } |
611 | if (cpu->cfg.ext_u) { | |
e91a7227 | 612 | ext |= RVU; |
b55d7d34 | 613 | } |
c9eefe05 | 614 | if (cpu->cfg.ext_h) { |
e91a7227 | 615 | ext |= RVH; |
c9eefe05 | 616 | } |
6bf91617 | 617 | if (cpu->cfg.ext_v) { |
9ec6622d | 618 | int vext_version = VEXT_VERSION_1_00_0; |
e91a7227 | 619 | ext |= RVV; |
6bf91617 LZ |
620 | if (!is_power_of_2(cpu->cfg.vlen)) { |
621 | error_setg(errp, | |
622 | "Vector extension VLEN must be power of 2"); | |
623 | return; | |
624 | } | |
625 | if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { | |
626 | error_setg(errp, | |
627 | "Vector extension implementation only supports VLEN " | |
628 | "in the range [128, %d]", RV_VLEN_MAX); | |
629 | return; | |
630 | } | |
631 | if (!is_power_of_2(cpu->cfg.elen)) { | |
632 | error_setg(errp, | |
633 | "Vector extension ELEN must be power of 2"); | |
634 | return; | |
635 | } | |
636 | if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) { | |
637 | error_setg(errp, | |
638 | "Vector extension implementation only supports ELEN " | |
639 | "in the range [8, 64]"); | |
640 | return; | |
641 | } | |
642 | if (cpu->cfg.vext_spec) { | |
9ec6622d FC |
643 | if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { |
644 | vext_version = VEXT_VERSION_1_00_0; | |
6bf91617 LZ |
645 | } else { |
646 | error_setg(errp, | |
647 | "Unsupported vector spec version '%s'", | |
648 | cpu->cfg.vext_spec); | |
649 | return; | |
650 | } | |
651 | } else { | |
cba42d61 | 652 | qemu_log("vector version is not specified, " |
9ec6622d | 653 | "use the default value v1.0\n"); |
6bf91617 LZ |
654 | } |
655 | set_vext_version(env, vext_version); | |
656 | } | |
32e579b8 FC |
657 | if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) { |
658 | error_setg(errp, "Zve32f/Zve64f extension depends upon RVF."); | |
b4a99d40 FC |
659 | return; |
660 | } | |
0ee9a4e5 AB |
661 | if (cpu->cfg.ext_j) { |
662 | ext |= RVJ; | |
663 | } | |
b55d7d34 | 664 | |
e91a7227 | 665 | set_misa(env, env->misa_mxl, ext); |
b55d7d34 AF |
666 | } |
667 | ||
5371f5cd JW |
668 | riscv_cpu_register_gdb_regs_for_features(cs); |
669 | ||
dc5bd18f MC |
670 | qemu_init_vcpu(cs); |
671 | cpu_reset(cs); | |
672 | ||
673 | mcc->parent_realize(dev, errp); | |
674 | } | |
675 | ||
0f0b70ee AF |
676 | #ifndef CONFIG_USER_ONLY |
677 | static void riscv_cpu_set_irq(void *opaque, int irq, int level) | |
678 | { | |
679 | RISCVCPU *cpu = RISCV_CPU(opaque); | |
cd032fe7 | 680 | CPURISCVState *env = &cpu->env; |
0f0b70ee | 681 | |
cd032fe7 AP |
682 | if (irq < IRQ_LOCAL_MAX) { |
683 | switch (irq) { | |
684 | case IRQ_U_SOFT: | |
685 | case IRQ_S_SOFT: | |
686 | case IRQ_VS_SOFT: | |
687 | case IRQ_M_SOFT: | |
688 | case IRQ_U_TIMER: | |
689 | case IRQ_S_TIMER: | |
690 | case IRQ_VS_TIMER: | |
691 | case IRQ_M_TIMER: | |
692 | case IRQ_U_EXT: | |
693 | case IRQ_S_EXT: | |
694 | case IRQ_VS_EXT: | |
695 | case IRQ_M_EXT: | |
696 | if (kvm_enabled()) { | |
697 | kvm_riscv_set_irq(cpu, irq, level); | |
698 | } else { | |
699 | riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); | |
700 | } | |
701 | break; | |
702 | default: | |
703 | g_assert_not_reached(); | |
2b650fbb | 704 | } |
cd032fe7 AP |
705 | } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { |
706 | /* Require H-extension for handling guest local interrupts */ | |
707 | if (!riscv_has_ext(env, RVH)) { | |
708 | g_assert_not_reached(); | |
709 | } | |
710 | ||
711 | /* Compute bit position in HGEIP CSR */ | |
712 | irq = irq - IRQ_LOCAL_MAX + 1; | |
713 | if (env->geilen < irq) { | |
714 | g_assert_not_reached(); | |
715 | } | |
716 | ||
717 | /* Update HGEIP CSR */ | |
718 | env->hgeip &= ~((target_ulong)1 << irq); | |
719 | if (level) { | |
720 | env->hgeip |= (target_ulong)1 << irq; | |
721 | } | |
722 | ||
723 | /* Update mip.SGEIP bit */ | |
724 | riscv_cpu_update_mip(cpu, MIP_SGEIP, | |
725 | BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); | |
726 | } else { | |
0f0b70ee AF |
727 | g_assert_not_reached(); |
728 | } | |
729 | } | |
730 | #endif /* CONFIG_USER_ONLY */ | |
731 | ||
dc5bd18f MC |
732 | static void riscv_cpu_init(Object *obj) |
733 | { | |
dc5bd18f MC |
734 | RISCVCPU *cpu = RISCV_CPU(obj); |
735 | ||
7506ed90 | 736 | cpu_set_cpustate_pointers(cpu); |
0f0b70ee AF |
737 | |
738 | #ifndef CONFIG_USER_ONLY | |
cd032fe7 AP |
739 | qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, |
740 | IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); | |
0f0b70ee | 741 | #endif /* CONFIG_USER_ONLY */ |
dc5bd18f MC |
742 | } |
743 | ||
c4e95030 | 744 | static Property riscv_cpu_properties[] = { |
9d3d60b7 | 745 | /* Defaults for standard extensions */ |
b55d7d34 AF |
746 | DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), |
747 | DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), | |
748 | DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true), | |
749 | DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), | |
750 | DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), | |
751 | DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), | |
752 | DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), | |
753 | DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), | |
754 | DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), | |
755 | DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), | |
9ec6622d | 756 | DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), |
07cb270a | 757 | DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), |
9d3d60b7 AF |
758 | DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), |
759 | DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), | |
760 | DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), | |
13fb8c7b | 761 | DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), |
e5237730 | 762 | DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), |
2fc1b44d | 763 | DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), |
bfefe406 | 764 | DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), |
9d3d60b7 AF |
765 | DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), |
766 | DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), | |
767 | ||
768 | DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), | |
9ec6622d FC |
769 | DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), |
770 | DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), | |
771 | DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), | |
9d3d60b7 | 772 | |
0643c12e VG |
773 | DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), |
774 | DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), | |
775 | DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), | |
776 | DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), | |
dfdb46a3 | 777 | |
0d429bd2 PT |
778 | /* Vendor-specific custom extensions */ |
779 | DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), | |
780 | ||
dfdb46a3 | 781 | /* These are experimental so mark with 'x-' */ |
0ee9a4e5 | 782 | DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), |
a44da25a | 783 | /* ePMP 0.9.3 */ |
5da9514e HW |
784 | DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), |
785 | ||
9b4c9b2b | 786 | DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), |
c4e95030 AF |
787 | DEFINE_PROP_END_OF_LIST(), |
788 | }; | |
789 | ||
edf64786 SP |
790 | static gchar *riscv_gdb_arch_name(CPUState *cs) |
791 | { | |
792 | RISCVCPU *cpu = RISCV_CPU(cs); | |
793 | CPURISCVState *env = &cpu->env; | |
794 | ||
db23e5d9 RH |
795 | switch (riscv_cpu_mxl(env)) { |
796 | case MXL_RV32: | |
edf64786 | 797 | return g_strdup("riscv:rv32"); |
db23e5d9 | 798 | case MXL_RV64: |
332dab68 | 799 | case MXL_RV128: |
edf64786 | 800 | return g_strdup("riscv:rv64"); |
db23e5d9 RH |
801 | default: |
802 | g_assert_not_reached(); | |
edf64786 SP |
803 | } |
804 | } | |
805 | ||
b93777e1 BM |
806 | static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) |
807 | { | |
808 | RISCVCPU *cpu = RISCV_CPU(cs); | |
809 | ||
810 | if (strcmp(xmlname, "riscv-csr.xml") == 0) { | |
811 | return cpu->dyn_csr_xml; | |
719d3561 HW |
812 | } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { |
813 | return cpu->dyn_vreg_xml; | |
b93777e1 BM |
814 | } |
815 | ||
816 | return NULL; | |
817 | } | |
818 | ||
8b80bd28 PMD |
819 | #ifndef CONFIG_USER_ONLY |
820 | #include "hw/core/sysemu-cpu-ops.h" | |
821 | ||
822 | static const struct SysemuCPUOps riscv_sysemu_ops = { | |
08928c6d | 823 | .get_phys_page_debug = riscv_cpu_get_phys_page_debug, |
715e3c1a PMD |
824 | .write_elf64_note = riscv_cpu_write_elf64_note, |
825 | .write_elf32_note = riscv_cpu_write_elf32_note, | |
feece4d0 | 826 | .legacy_vmsd = &vmstate_riscv_cpu, |
8b80bd28 PMD |
827 | }; |
828 | #endif | |
829 | ||
78271684 CF |
830 | #include "hw/core/tcg-cpu-ops.h" |
831 | ||
11906557 | 832 | static const struct TCGCPUOps riscv_tcg_ops = { |
78271684 CF |
833 | .initialize = riscv_translate_init, |
834 | .synchronize_from_tb = riscv_cpu_synchronize_from_tb, | |
78271684 CF |
835 | |
836 | #ifndef CONFIG_USER_ONLY | |
263e2ab2 | 837 | .tlb_fill = riscv_cpu_tlb_fill, |
17b3c353 | 838 | .cpu_exec_interrupt = riscv_cpu_exec_interrupt, |
78271684 CF |
839 | .do_interrupt = riscv_cpu_do_interrupt, |
840 | .do_transaction_failed = riscv_cpu_do_transaction_failed, | |
841 | .do_unaligned_access = riscv_cpu_do_unaligned_access, | |
842 | #endif /* !CONFIG_USER_ONLY */ | |
843 | }; | |
844 | ||
dc5bd18f MC |
845 | static void riscv_cpu_class_init(ObjectClass *c, void *data) |
846 | { | |
847 | RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); | |
848 | CPUClass *cc = CPU_CLASS(c); | |
849 | DeviceClass *dc = DEVICE_CLASS(c); | |
850 | ||
41fbbba7 MZ |
851 | device_class_set_parent_realize(dc, riscv_cpu_realize, |
852 | &mcc->parent_realize); | |
dc5bd18f | 853 | |
781c67ca | 854 | device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset); |
dc5bd18f MC |
855 | |
856 | cc->class_by_name = riscv_cpu_class_by_name; | |
857 | cc->has_work = riscv_cpu_has_work; | |
dc5bd18f MC |
858 | cc->dump_state = riscv_cpu_dump_state; |
859 | cc->set_pc = riscv_cpu_set_pc; | |
dc5bd18f MC |
860 | cc->gdb_read_register = riscv_cpu_gdb_read_register; |
861 | cc->gdb_write_register = riscv_cpu_gdb_write_register; | |
5371f5cd | 862 | cc->gdb_num_core_regs = 33; |
dc5bd18f MC |
863 | cc->gdb_stop_before_watchpoint = true; |
864 | cc->disas_set_info = riscv_cpu_disas_set_info; | |
8a4ca3c1 | 865 | #ifndef CONFIG_USER_ONLY |
8b80bd28 | 866 | cc->sysemu_ops = &riscv_sysemu_ops; |
dc5bd18f | 867 | #endif |
edf64786 | 868 | cc->gdb_arch_name = riscv_gdb_arch_name; |
b93777e1 | 869 | cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; |
78271684 | 870 | cc->tcg_ops = &riscv_tcg_ops; |
6a3d2e7c | 871 | |
4f67d30b | 872 | device_class_set_props(dc, riscv_cpu_properties); |
dc5bd18f MC |
873 | } |
874 | ||
dc5bd18f MC |
875 | char *riscv_isa_string(RISCVCPU *cpu) |
876 | { | |
877 | int i; | |
d1fd31f8 MC |
878 | const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1; |
879 | char *isa_str = g_new(char, maxlen); | |
880 | char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); | |
dc5bd18f | 881 | for (i = 0; i < sizeof(riscv_exts); i++) { |
e91a7227 | 882 | if (cpu->env.misa_ext & RV(riscv_exts[i])) { |
d1fd31f8 | 883 | *p++ = qemu_tolower(riscv_exts[i]); |
dc5bd18f MC |
884 | } |
885 | } | |
d1fd31f8 MC |
886 | *p = '\0'; |
887 | return isa_str; | |
dc5bd18f MC |
888 | } |
889 | ||
eab15862 | 890 | static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) |
dc5bd18f | 891 | { |
eab15862 MC |
892 | ObjectClass *class_a = (ObjectClass *)a; |
893 | ObjectClass *class_b = (ObjectClass *)b; | |
894 | const char *name_a, *name_b; | |
dc5bd18f | 895 | |
eab15862 MC |
896 | name_a = object_class_get_name(class_a); |
897 | name_b = object_class_get_name(class_b); | |
898 | return strcmp(name_a, name_b); | |
dc5bd18f MC |
899 | } |
900 | ||
eab15862 | 901 | static void riscv_cpu_list_entry(gpointer data, gpointer user_data) |
dc5bd18f | 902 | { |
eab15862 MC |
903 | const char *typename = object_class_get_name(OBJECT_CLASS(data)); |
904 | int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); | |
dc5bd18f | 905 | |
0442428a | 906 | qemu_printf("%.*s\n", len, typename); |
eab15862 | 907 | } |
dc5bd18f | 908 | |
0442428a | 909 | void riscv_cpu_list(void) |
eab15862 | 910 | { |
eab15862 MC |
911 | GSList *list; |
912 | ||
913 | list = object_class_get_list(TYPE_RISCV_CPU, false); | |
914 | list = g_slist_sort(list, riscv_cpu_list_compare); | |
0442428a | 915 | g_slist_foreach(list, riscv_cpu_list_entry, NULL); |
eab15862 | 916 | g_slist_free(list); |
dc5bd18f MC |
917 | } |
918 | ||
eab15862 MC |
919 | #define DEFINE_CPU(type_name, initfn) \ |
920 | { \ | |
921 | .name = type_name, \ | |
922 | .parent = TYPE_RISCV_CPU, \ | |
923 | .instance_init = initfn \ | |
924 | } | |
925 | ||
926 | static const TypeInfo riscv_cpu_type_infos[] = { | |
927 | { | |
928 | .name = TYPE_RISCV_CPU, | |
929 | .parent = TYPE_CPU, | |
930 | .instance_size = sizeof(RISCVCPU), | |
5de5b99b | 931 | .instance_align = __alignof__(RISCVCPU), |
eab15862 MC |
932 | .instance_init = riscv_cpu_init, |
933 | .abstract = true, | |
934 | .class_size = sizeof(RISCVCPUClass), | |
935 | .class_init = riscv_cpu_class_init, | |
936 | }, | |
937 | DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), | |
10f1ca27 YJ |
938 | #if defined(CONFIG_KVM) |
939 | DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), | |
940 | #endif | |
eab15862 | 941 | #if defined(TARGET_RISCV32) |
094b072c | 942 | DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), |
e8905c6c | 943 | DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), |
114baaca | 944 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), |
2fdd2c09 | 945 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), |
114baaca | 946 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), |
eab15862 | 947 | #elif defined(TARGET_RISCV64) |
094b072c | 948 | DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), |
114baaca AF |
949 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), |
950 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), | |
6ddc7069 | 951 | DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), |
332dab68 | 952 | DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), |
eab15862 MC |
953 | #endif |
954 | }; | |
955 | ||
956 | DEFINE_TYPES(riscv_cpu_type_infos) |