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dc5bd18f MC |
1 | /* |
2 | * QEMU RISC-V CPU | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
0442428a | 21 | #include "qemu/qemu-print.h" |
856dfd8a | 22 | #include "qemu/ctype.h" |
dc5bd18f MC |
23 | #include "qemu/log.h" |
24 | #include "cpu.h" | |
f7697f0e | 25 | #include "internals.h" |
dc5bd18f MC |
26 | #include "exec/exec-all.h" |
27 | #include "qapi/error.h" | |
b55d7d34 | 28 | #include "qemu/error-report.h" |
c4e95030 | 29 | #include "hw/qdev-properties.h" |
dc5bd18f | 30 | #include "migration/vmstate.h" |
135b03cb | 31 | #include "fpu/softfloat-helpers.h" |
ad40be27 YJ |
32 | #include "sysemu/kvm.h" |
33 | #include "kvm_riscv.h" | |
dc5bd18f MC |
34 | |
35 | /* RISC-V CPU definitions */ | |
36 | ||
9951ba94 FC |
37 | #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ |
38 | (QEMU_VERSION_MINOR << 8) | \ | |
39 | (QEMU_VERSION_MICRO)) | |
075eeda9 | 40 | #define RISCV_CPU_MIMPID RISCV_CPU_MARCHID |
9951ba94 | 41 | |
0e2c3770 | 42 | static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; |
dc5bd18f | 43 | |
a775398b AP |
44 | struct isa_ext_data { |
45 | const char *name; | |
9a1f054d AP |
46 | bool multi_letter; |
47 | int min_version; | |
48 | int ext_enable_offset; | |
a775398b AP |
49 | }; |
50 | ||
9a1f054d AP |
51 | #define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \ |
52 | {#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} | |
53 | ||
54 | /** | |
55 | * Here are the ordering rules of extension naming defined by RISC-V | |
56 | * specification : | |
57 | * 1. All extensions should be separated from other multi-letter extensions | |
58 | * by an underscore. | |
59 | * 2. The first letter following the 'Z' conventionally indicates the most | |
60 | * closely related alphabetical extension category, IMAFDQLCBKJTPVH. | |
61 | * If multiple 'Z' extensions are named, they should be ordered first | |
62 | * by category, then alphabetically within a category. | |
63 | * 3. Standard supervisor-level extensions (starts with 'S') should be | |
64 | * listed after standard unprivileged extensions. If multiple | |
65 | * supervisor-level extensions are listed, they should be ordered | |
66 | * alphabetically. | |
67 | * 4. Non-standard extensions (starts with 'X') must be listed after all | |
68 | * standard extensions. They must be separated from other multi-letter | |
69 | * extensions by an underscore. | |
70 | */ | |
71 | static const struct isa_ext_data isa_edata_arr[] = { | |
72 | ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h), | |
73 | ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_12_0, ext_v), | |
74 | ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr), | |
75 | ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei), | |
4696f0ab | 76 | ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause), |
9a1f054d AP |
77 | ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_12_0, ext_zfh), |
78 | ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin), | |
79 | ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx), | |
80 | ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx), | |
81 | ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba), | |
82 | ISA_EXT_DATA_ENTRY(zbb, true, PRIV_VERSION_1_12_0, ext_zbb), | |
83 | ISA_EXT_DATA_ENTRY(zbc, true, PRIV_VERSION_1_12_0, ext_zbc), | |
84 | ISA_EXT_DATA_ENTRY(zbkb, true, PRIV_VERSION_1_12_0, ext_zbkb), | |
85 | ISA_EXT_DATA_ENTRY(zbkc, true, PRIV_VERSION_1_12_0, ext_zbkc), | |
86 | ISA_EXT_DATA_ENTRY(zbkx, true, PRIV_VERSION_1_12_0, ext_zbkx), | |
87 | ISA_EXT_DATA_ENTRY(zbs, true, PRIV_VERSION_1_12_0, ext_zbs), | |
88 | ISA_EXT_DATA_ENTRY(zk, true, PRIV_VERSION_1_12_0, ext_zk), | |
89 | ISA_EXT_DATA_ENTRY(zkn, true, PRIV_VERSION_1_12_0, ext_zkn), | |
90 | ISA_EXT_DATA_ENTRY(zknd, true, PRIV_VERSION_1_12_0, ext_zknd), | |
91 | ISA_EXT_DATA_ENTRY(zkne, true, PRIV_VERSION_1_12_0, ext_zkne), | |
92 | ISA_EXT_DATA_ENTRY(zknh, true, PRIV_VERSION_1_12_0, ext_zknh), | |
93 | ISA_EXT_DATA_ENTRY(zkr, true, PRIV_VERSION_1_12_0, ext_zkr), | |
94 | ISA_EXT_DATA_ENTRY(zks, true, PRIV_VERSION_1_12_0, ext_zks), | |
95 | ISA_EXT_DATA_ENTRY(zksed, true, PRIV_VERSION_1_12_0, ext_zksed), | |
96 | ISA_EXT_DATA_ENTRY(zksh, true, PRIV_VERSION_1_12_0, ext_zksh), | |
97 | ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt), | |
98 | ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f), | |
99 | ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f), | |
100 | ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), | |
101 | ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), | |
dc9acc9c AP |
102 | ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia), |
103 | ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia), | |
9a1f054d AP |
104 | ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), |
105 | ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), | |
106 | ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), | |
e0dea2f5 | 107 | ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), |
9a1f054d AP |
108 | }; |
109 | ||
110 | static bool isa_ext_is_enabled(RISCVCPU *cpu, | |
111 | const struct isa_ext_data *edata) | |
112 | { | |
113 | bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; | |
114 | ||
115 | return *ext_enabled; | |
116 | } | |
117 | ||
118 | static void isa_ext_update_enabled(RISCVCPU *cpu, | |
119 | const struct isa_ext_data *edata, bool en) | |
120 | { | |
121 | bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; | |
122 | ||
123 | *ext_enabled = en; | |
124 | } | |
125 | ||
dc5bd18f | 126 | const char * const riscv_int_regnames[] = { |
a9f37afa AP |
127 | "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", |
128 | "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", | |
129 | "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", | |
130 | "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", | |
131 | "x28/t3", "x29/t4", "x30/t5", "x31/t6" | |
dc5bd18f MC |
132 | }; |
133 | ||
2b547084 FP |
134 | const char * const riscv_int_regnamesh[] = { |
135 | "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", | |
136 | "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", | |
137 | "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", | |
138 | "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", | |
139 | "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", | |
140 | "x30h/t5h", "x31h/t6h" | |
141 | }; | |
142 | ||
dc5bd18f | 143 | const char * const riscv_fpr_regnames[] = { |
a9f37afa AP |
144 | "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", |
145 | "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", | |
146 | "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", | |
147 | "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", | |
148 | "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", | |
149 | "f30/ft10", "f31/ft11" | |
dc5bd18f MC |
150 | }; |
151 | ||
9a575d33 | 152 | static const char * const riscv_excp_names[] = { |
dc5bd18f MC |
153 | "misaligned_fetch", |
154 | "fault_fetch", | |
155 | "illegal_instruction", | |
156 | "breakpoint", | |
157 | "misaligned_load", | |
158 | "fault_load", | |
159 | "misaligned_store", | |
160 | "fault_store", | |
161 | "user_ecall", | |
162 | "supervisor_ecall", | |
163 | "hypervisor_ecall", | |
164 | "machine_ecall", | |
165 | "exec_page_fault", | |
166 | "load_page_fault", | |
167 | "reserved", | |
fd990e86 | 168 | "store_page_fault", |
ab67a1d0 AF |
169 | "reserved", |
170 | "reserved", | |
171 | "reserved", | |
172 | "reserved", | |
173 | "guest_exec_page_fault", | |
174 | "guest_load_page_fault", | |
175 | "reserved", | |
fd990e86 | 176 | "guest_store_page_fault", |
dc5bd18f MC |
177 | }; |
178 | ||
9a575d33 | 179 | static const char * const riscv_intr_names[] = { |
dc5bd18f MC |
180 | "u_software", |
181 | "s_software", | |
205377f8 | 182 | "vs_software", |
dc5bd18f MC |
183 | "m_software", |
184 | "u_timer", | |
185 | "s_timer", | |
205377f8 | 186 | "vs_timer", |
dc5bd18f MC |
187 | "m_timer", |
188 | "u_external", | |
6cfcf775 | 189 | "s_external", |
205377f8 | 190 | "vs_external", |
dc5bd18f | 191 | "m_external", |
426f0348 MC |
192 | "reserved", |
193 | "reserved", | |
194 | "reserved", | |
195 | "reserved" | |
dc5bd18f MC |
196 | }; |
197 | ||
26b2bc58 AF |
198 | static void register_cpu_props(DeviceState *dev); |
199 | ||
c51a3f5d YJ |
200 | const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) |
201 | { | |
202 | if (async) { | |
203 | return (cause < ARRAY_SIZE(riscv_intr_names)) ? | |
204 | riscv_intr_names[cause] : "(unknown)"; | |
205 | } else { | |
206 | return (cause < ARRAY_SIZE(riscv_excp_names)) ? | |
207 | riscv_excp_names[cause] : "(unknown)"; | |
208 | } | |
209 | } | |
210 | ||
e91a7227 | 211 | static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) |
dc5bd18f | 212 | { |
e91a7227 RH |
213 | env->misa_mxl_max = env->misa_mxl = mxl; |
214 | env->misa_ext_mask = env->misa_ext = ext; | |
dc5bd18f MC |
215 | } |
216 | ||
c9a73910 | 217 | static void set_priv_version(CPURISCVState *env, int priv_ver) |
dc5bd18f | 218 | { |
dc5bd18f MC |
219 | env->priv_ver = priv_ver; |
220 | } | |
221 | ||
32931383 LZ |
222 | static void set_vext_version(CPURISCVState *env, int vext_ver) |
223 | { | |
224 | env->vext_ver = vext_ver; | |
225 | } | |
226 | ||
01e723bf | 227 | static void set_resetvec(CPURISCVState *env, target_ulong resetvec) |
dc5bd18f MC |
228 | { |
229 | #ifndef CONFIG_USER_ONLY | |
230 | env->resetvec = resetvec; | |
231 | #endif | |
232 | } | |
233 | ||
234 | static void riscv_any_cpu_init(Object *obj) | |
235 | { | |
236 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
3820602f | 237 | #if defined(TARGET_RISCV32) |
e91a7227 | 238 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); |
3820602f | 239 | #elif defined(TARGET_RISCV64) |
e91a7227 | 240 | set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); |
3820602f | 241 | #endif |
7100fe6c | 242 | set_priv_version(env, PRIV_VERSION_1_12_0); |
26b2bc58 | 243 | register_cpu_props(DEVICE(obj)); |
dc5bd18f MC |
244 | } |
245 | ||
094b072c AF |
246 | #if defined(TARGET_RISCV64) |
247 | static void rv64_base_cpu_init(Object *obj) | |
8903bf6e AF |
248 | { |
249 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
b55d7d34 | 250 | /* We set this in the realise function */ |
e91a7227 | 251 | set_misa(env, MXL_RV64, 0); |
26b2bc58 | 252 | register_cpu_props(DEVICE(obj)); |
18800095 AP |
253 | /* Set latest version of privileged specification */ |
254 | set_priv_version(env, PRIV_VERSION_1_12_0); | |
8903bf6e AF |
255 | } |
256 | ||
114baaca | 257 | static void rv64_sifive_u_cpu_init(Object *obj) |
dc5bd18f MC |
258 | { |
259 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
e91a7227 | 260 | set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); |
c9a73910 | 261 | set_priv_version(env, PRIV_VERSION_1_10_0); |
dc5bd18f MC |
262 | } |
263 | ||
114baaca | 264 | static void rv64_sifive_e_cpu_init(Object *obj) |
36b80ad9 AF |
265 | { |
266 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
26b2bc58 AF |
267 | RISCVCPU *cpu = RISCV_CPU(obj); |
268 | ||
e91a7227 | 269 | set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); |
36b80ad9 | 270 | set_priv_version(env, PRIV_VERSION_1_10_0); |
26b2bc58 | 271 | cpu->cfg.mmu = false; |
36b80ad9 | 272 | } |
332dab68 FP |
273 | |
274 | static void rv128_base_cpu_init(Object *obj) | |
275 | { | |
276 | if (qemu_tcg_mttcg_enabled()) { | |
277 | /* Missing 128-bit aligned atomics */ | |
278 | error_report("128-bit RISC-V currently does not work with Multi " | |
279 | "Threaded TCG. Please use: -accel tcg,thread=single"); | |
280 | exit(EXIT_FAILURE); | |
281 | } | |
282 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
283 | /* We set this in the realise function */ | |
284 | set_misa(env, MXL_RV128, 0); | |
26b2bc58 | 285 | register_cpu_props(DEVICE(obj)); |
18800095 AP |
286 | /* Set latest version of privileged specification */ |
287 | set_priv_version(env, PRIV_VERSION_1_12_0); | |
332dab68 | 288 | } |
114baaca | 289 | #else |
094b072c AF |
290 | static void rv32_base_cpu_init(Object *obj) |
291 | { | |
292 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
293 | /* We set this in the realise function */ | |
e91a7227 | 294 | set_misa(env, MXL_RV32, 0); |
26b2bc58 | 295 | register_cpu_props(DEVICE(obj)); |
18800095 AP |
296 | /* Set latest version of privileged specification */ |
297 | set_priv_version(env, PRIV_VERSION_1_12_0); | |
094b072c AF |
298 | } |
299 | ||
114baaca AF |
300 | static void rv32_sifive_u_cpu_init(Object *obj) |
301 | { | |
302 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
e91a7227 | 303 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); |
114baaca AF |
304 | set_priv_version(env, PRIV_VERSION_1_10_0); |
305 | } | |
36b80ad9 | 306 | |
114baaca AF |
307 | static void rv32_sifive_e_cpu_init(Object *obj) |
308 | { | |
309 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
26b2bc58 AF |
310 | RISCVCPU *cpu = RISCV_CPU(obj); |
311 | ||
e91a7227 | 312 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); |
114baaca | 313 | set_priv_version(env, PRIV_VERSION_1_10_0); |
26b2bc58 | 314 | cpu->cfg.mmu = false; |
114baaca | 315 | } |
d8e72bd1 | 316 | |
e8905c6c | 317 | static void rv32_ibex_cpu_init(Object *obj) |
dc5bd18f MC |
318 | { |
319 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
26b2bc58 AF |
320 | RISCVCPU *cpu = RISCV_CPU(obj); |
321 | ||
e91a7227 | 322 | set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); |
be2265c7 | 323 | set_priv_version(env, PRIV_VERSION_1_11_0); |
26b2bc58 AF |
324 | cpu->cfg.mmu = false; |
325 | cpu->cfg.epmp = true; | |
dc5bd18f MC |
326 | } |
327 | ||
2fdd2c09 | 328 | static void rv32_imafcu_nommu_cpu_init(Object *obj) |
d784733b CW |
329 | { |
330 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
26b2bc58 AF |
331 | RISCVCPU *cpu = RISCV_CPU(obj); |
332 | ||
e91a7227 | 333 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); |
d784733b CW |
334 | set_priv_version(env, PRIV_VERSION_1_10_0); |
335 | set_resetvec(env, DEFAULT_RSTVEC); | |
26b2bc58 | 336 | cpu->cfg.mmu = false; |
d784733b | 337 | } |
eab15862 | 338 | #endif |
dc5bd18f | 339 | |
10f1ca27 YJ |
340 | #if defined(CONFIG_KVM) |
341 | static void riscv_host_cpu_init(Object *obj) | |
342 | { | |
343 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
344 | #if defined(TARGET_RISCV32) | |
345 | set_misa(env, MXL_RV32, 0); | |
346 | #elif defined(TARGET_RISCV64) | |
347 | set_misa(env, MXL_RV64, 0); | |
348 | #endif | |
26b2bc58 | 349 | register_cpu_props(DEVICE(obj)); |
10f1ca27 YJ |
350 | } |
351 | #endif | |
352 | ||
dc5bd18f MC |
353 | static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) |
354 | { | |
355 | ObjectClass *oc; | |
356 | char *typename; | |
357 | char **cpuname; | |
358 | ||
359 | cpuname = g_strsplit(cpu_model, ",", 1); | |
360 | typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); | |
361 | oc = object_class_by_name(typename); | |
362 | g_strfreev(cpuname); | |
363 | g_free(typename); | |
364 | if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || | |
365 | object_class_is_abstract(oc)) { | |
366 | return NULL; | |
367 | } | |
368 | return oc; | |
369 | } | |
370 | ||
90c84c56 | 371 | static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) |
dc5bd18f MC |
372 | { |
373 | RISCVCPU *cpu = RISCV_CPU(cs); | |
374 | CPURISCVState *env = &cpu->env; | |
375 | int i; | |
376 | ||
df30e652 AF |
377 | #if !defined(CONFIG_USER_ONLY) |
378 | if (riscv_has_ext(env, RVH)) { | |
379 | qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); | |
380 | } | |
381 | #endif | |
90c84c56 | 382 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); |
dc5bd18f | 383 | #ifndef CONFIG_USER_ONLY |
665b90d8 RH |
384 | { |
385 | static const int dump_csrs[] = { | |
386 | CSR_MHARTID, | |
387 | CSR_MSTATUS, | |
388 | CSR_MSTATUSH, | |
389 | CSR_HSTATUS, | |
390 | CSR_VSSTATUS, | |
391 | CSR_MIP, | |
392 | CSR_MIE, | |
393 | CSR_MIDELEG, | |
394 | CSR_HIDELEG, | |
395 | CSR_MEDELEG, | |
396 | CSR_HEDELEG, | |
397 | CSR_MTVEC, | |
398 | CSR_STVEC, | |
399 | CSR_VSTVEC, | |
400 | CSR_MEPC, | |
401 | CSR_SEPC, | |
402 | CSR_VSEPC, | |
403 | CSR_MCAUSE, | |
404 | CSR_SCAUSE, | |
405 | CSR_VSCAUSE, | |
406 | CSR_MTVAL, | |
407 | CSR_STVAL, | |
408 | CSR_HTVAL, | |
409 | CSR_MTVAL2, | |
410 | CSR_MSCRATCH, | |
411 | CSR_SSCRATCH, | |
412 | CSR_SATP, | |
bd5594ca AB |
413 | CSR_MMTE, |
414 | CSR_UPMBASE, | |
415 | CSR_UPMMASK, | |
416 | CSR_SPMBASE, | |
417 | CSR_SPMMASK, | |
418 | CSR_MPMBASE, | |
419 | CSR_MPMMASK, | |
665b90d8 RH |
420 | }; |
421 | ||
422 | for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { | |
423 | int csrno = dump_csrs[i]; | |
424 | target_ulong val = 0; | |
425 | RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); | |
426 | ||
427 | /* | |
428 | * Rely on the smode, hmode, etc, predicates within csr.c | |
429 | * to do the filtering of the registers that are present. | |
430 | */ | |
431 | if (res == RISCV_EXCP_NONE) { | |
432 | qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", | |
433 | csr_ops[csrno].name, val); | |
434 | } | |
435 | } | |
df30e652 | 436 | } |
dc5bd18f MC |
437 | #endif |
438 | ||
439 | for (i = 0; i < 32; i++) { | |
e573a7f3 | 440 | qemu_fprintf(f, " %-8s " TARGET_FMT_lx, |
90c84c56 | 441 | riscv_int_regnames[i], env->gpr[i]); |
dc5bd18f | 442 | if ((i & 3) == 3) { |
90c84c56 | 443 | qemu_fprintf(f, "\n"); |
dc5bd18f MC |
444 | } |
445 | } | |
86ea1880 RH |
446 | if (flags & CPU_DUMP_FPU) { |
447 | for (i = 0; i < 32; i++) { | |
e573a7f3 | 448 | qemu_fprintf(f, " %-8s %016" PRIx64, |
90c84c56 | 449 | riscv_fpr_regnames[i], env->fpr[i]); |
86ea1880 | 450 | if ((i & 3) == 3) { |
90c84c56 | 451 | qemu_fprintf(f, "\n"); |
86ea1880 | 452 | } |
dc5bd18f MC |
453 | } |
454 | } | |
455 | } | |
456 | ||
457 | static void riscv_cpu_set_pc(CPUState *cs, vaddr value) | |
458 | { | |
459 | RISCVCPU *cpu = RISCV_CPU(cs); | |
460 | CPURISCVState *env = &cpu->env; | |
bf9e776e LZ |
461 | |
462 | if (env->xl == MXL_RV32) { | |
463 | env->pc = (int32_t)value; | |
464 | } else { | |
465 | env->pc = value; | |
466 | } | |
dc5bd18f MC |
467 | } |
468 | ||
04a37d4c RH |
469 | static void riscv_cpu_synchronize_from_tb(CPUState *cs, |
470 | const TranslationBlock *tb) | |
dc5bd18f MC |
471 | { |
472 | RISCVCPU *cpu = RISCV_CPU(cs); | |
473 | CPURISCVState *env = &cpu->env; | |
bf9e776e LZ |
474 | RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); |
475 | ||
476 | if (xl == MXL_RV32) { | |
477 | env->pc = (int32_t)tb->pc; | |
478 | } else { | |
479 | env->pc = tb->pc; | |
480 | } | |
dc5bd18f MC |
481 | } |
482 | ||
483 | static bool riscv_cpu_has_work(CPUState *cs) | |
484 | { | |
485 | #ifndef CONFIG_USER_ONLY | |
486 | RISCVCPU *cpu = RISCV_CPU(cs); | |
487 | CPURISCVState *env = &cpu->env; | |
488 | /* | |
489 | * Definition of the WFI instruction requires it to ignore the privilege | |
490 | * mode and delegation registers, but respect individual enables | |
491 | */ | |
8f42415f | 492 | return riscv_cpu_all_pending(env) != 0; |
dc5bd18f MC |
493 | #else |
494 | return true; | |
495 | #endif | |
496 | } | |
497 | ||
498 | void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, | |
499 | target_ulong *data) | |
500 | { | |
bf9e776e LZ |
501 | RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); |
502 | if (xl == MXL_RV32) { | |
503 | env->pc = (int32_t)data[0]; | |
504 | } else { | |
505 | env->pc = data[0]; | |
506 | } | |
62cf0245 | 507 | env->bins = data[1]; |
dc5bd18f MC |
508 | } |
509 | ||
781c67ca | 510 | static void riscv_cpu_reset(DeviceState *dev) |
dc5bd18f | 511 | { |
43dc93af AP |
512 | #ifndef CONFIG_USER_ONLY |
513 | uint8_t iprio; | |
514 | int i, irq, rdzero; | |
515 | #endif | |
781c67ca | 516 | CPUState *cs = CPU(dev); |
dc5bd18f MC |
517 | RISCVCPU *cpu = RISCV_CPU(cs); |
518 | RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); | |
519 | CPURISCVState *env = &cpu->env; | |
520 | ||
781c67ca | 521 | mcc->parent_reset(dev); |
dc5bd18f | 522 | #ifndef CONFIG_USER_ONLY |
e91a7227 | 523 | env->misa_mxl = env->misa_mxl_max; |
dc5bd18f MC |
524 | env->priv = PRV_M; |
525 | env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); | |
92371bd9 RH |
526 | if (env->misa_mxl > MXL_RV32) { |
527 | /* | |
528 | * The reset status of SXL/UXL is undefined, but mstatus is WARL | |
529 | * and we must ensure that the value after init is valid for read. | |
530 | */ | |
531 | env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); | |
532 | env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); | |
5a2ae235 LZ |
533 | if (riscv_has_ext(env, RVH)) { |
534 | env->vsstatus = set_field(env->vsstatus, | |
535 | MSTATUS64_SXL, env->misa_mxl); | |
536 | env->vsstatus = set_field(env->vsstatus, | |
537 | MSTATUS64_UXL, env->misa_mxl); | |
538 | env->mstatus_hs = set_field(env->mstatus_hs, | |
539 | MSTATUS64_SXL, env->misa_mxl); | |
540 | env->mstatus_hs = set_field(env->mstatus_hs, | |
541 | MSTATUS64_UXL, env->misa_mxl); | |
542 | } | |
92371bd9 | 543 | } |
dc5bd18f | 544 | env->mcause = 0; |
881df35d | 545 | env->miclaim = MIP_SGEIP; |
dc5bd18f | 546 | env->pc = env->resetvec; |
62cf0245 | 547 | env->bins = 0; |
ec352d0c | 548 | env->two_stage_lookup = false; |
43dc93af AP |
549 | |
550 | /* Initialized default priorities of local interrupts. */ | |
551 | for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { | |
552 | iprio = riscv_cpu_default_priority(i); | |
553 | env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio; | |
554 | env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio; | |
555 | env->hviprio[i] = 0; | |
556 | } | |
557 | i = 0; | |
558 | while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) { | |
559 | if (!rdzero) { | |
560 | env->hviprio[irq] = env->miprio[irq]; | |
561 | } | |
562 | i++; | |
563 | } | |
4bbe8033 AB |
564 | /* mmte is supposed to have pm.current hardwired to 1 */ |
565 | env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); | |
dc5bd18f | 566 | #endif |
440544e1 | 567 | env->xl = riscv_cpu_mxl(env); |
40bfa5f6 | 568 | riscv_cpu_update_mask(env); |
330d2ae3 | 569 | cs->exception_index = RISCV_EXCP_NONE; |
c13b169f | 570 | env->load_res = -1; |
dc5bd18f | 571 | set_default_nan_mode(1, &env->fp_status); |
ad40be27 YJ |
572 | |
573 | #ifndef CONFIG_USER_ONLY | |
b6092544 BM |
574 | if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { |
575 | riscv_trigger_init(env); | |
576 | } | |
577 | ||
ad40be27 YJ |
578 | if (kvm_enabled()) { |
579 | kvm_riscv_reset_vcpu(cpu); | |
580 | } | |
581 | #endif | |
dc5bd18f MC |
582 | } |
583 | ||
584 | static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) | |
585 | { | |
5c5a47f1 | 586 | RISCVCPU *cpu = RISCV_CPU(s); |
db23e5d9 RH |
587 | |
588 | switch (riscv_cpu_mxl(&cpu->env)) { | |
589 | case MXL_RV32: | |
5c5a47f1 | 590 | info->print_insn = print_insn_riscv32; |
db23e5d9 RH |
591 | break; |
592 | case MXL_RV64: | |
5c5a47f1 | 593 | info->print_insn = print_insn_riscv64; |
db23e5d9 | 594 | break; |
332dab68 FP |
595 | case MXL_RV128: |
596 | info->print_insn = print_insn_riscv128; | |
597 | break; | |
db23e5d9 RH |
598 | default: |
599 | g_assert_not_reached(); | |
5c5a47f1 | 600 | } |
dc5bd18f MC |
601 | } |
602 | ||
603 | static void riscv_cpu_realize(DeviceState *dev, Error **errp) | |
604 | { | |
605 | CPUState *cs = CPU(dev); | |
c4e95030 AF |
606 | RISCVCPU *cpu = RISCV_CPU(dev); |
607 | CPURISCVState *env = &cpu->env; | |
dc5bd18f | 608 | RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); |
1191be09 | 609 | CPUClass *cc = CPU_CLASS(mcc); |
9a1f054d | 610 | int i, priv_version = -1; |
dc5bd18f MC |
611 | Error *local_err = NULL; |
612 | ||
613 | cpu_exec_realizefn(cs, &local_err); | |
614 | if (local_err != NULL) { | |
615 | error_propagate(errp, local_err); | |
616 | return; | |
617 | } | |
618 | ||
c4e95030 | 619 | if (cpu->cfg.priv_spec) { |
7100fe6c AP |
620 | if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { |
621 | priv_version = PRIV_VERSION_1_12_0; | |
622 | } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { | |
e3147506 AF |
623 | priv_version = PRIV_VERSION_1_11_0; |
624 | } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { | |
c4e95030 | 625 | priv_version = PRIV_VERSION_1_10_0; |
c4e95030 AF |
626 | } else { |
627 | error_setg(errp, | |
628 | "Unsupported privilege spec version '%s'", | |
629 | cpu->cfg.priv_spec); | |
630 | return; | |
631 | } | |
632 | } | |
633 | ||
18800095 | 634 | if (priv_version >= PRIV_VERSION_1_10_0) { |
a8b37120 | 635 | set_priv_version(env, priv_version); |
a8b37120 | 636 | } |
c4e95030 | 637 | |
9a1f054d AP |
638 | /* Force disable extensions if priv spec version does not match */ |
639 | for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { | |
640 | if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && | |
641 | (env->priv_ver < isa_edata_arr[i].min_version)) { | |
642 | isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); | |
643 | #ifndef CONFIG_USER_ONLY | |
644 | warn_report("disabling %s extension for hart 0x%lx because " | |
645 | "privilege spec version does not match", | |
646 | isa_edata_arr[i].name, (unsigned long)env->mhartid); | |
647 | #else | |
648 | warn_report("disabling %s extension because " | |
649 | "privilege spec version does not match", | |
650 | isa_edata_arr[i].name); | |
651 | #endif | |
652 | } | |
653 | } | |
654 | ||
c4e95030 | 655 | if (cpu->cfg.mmu) { |
f87adf23 | 656 | riscv_set_feature(env, RISCV_FEATURE_MMU); |
c4e95030 AF |
657 | } |
658 | ||
659 | if (cpu->cfg.pmp) { | |
f87adf23 | 660 | riscv_set_feature(env, RISCV_FEATURE_PMP); |
5da9514e HW |
661 | |
662 | /* | |
663 | * Enhanced PMP should only be available | |
664 | * on harts with PMP support | |
665 | */ | |
666 | if (cpu->cfg.epmp) { | |
f87adf23 | 667 | riscv_set_feature(env, RISCV_FEATURE_EPMP); |
5da9514e | 668 | } |
c4e95030 AF |
669 | } |
670 | ||
1acdb3b0 BM |
671 | if (cpu->cfg.debug) { |
672 | riscv_set_feature(env, RISCV_FEATURE_DEBUG); | |
673 | } | |
674 | ||
73f6ed97 BM |
675 | set_resetvec(env, cpu->cfg.resetvec); |
676 | ||
e91a7227 RH |
677 | /* Validate that MISA_MXL is set properly. */ |
678 | switch (env->misa_mxl_max) { | |
679 | #ifdef TARGET_RISCV64 | |
680 | case MXL_RV64: | |
332dab68 | 681 | case MXL_RV128: |
6c3a9247 | 682 | cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; |
332dab68 | 683 | break; |
e91a7227 RH |
684 | #endif |
685 | case MXL_RV32: | |
1191be09 | 686 | cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; |
e91a7227 RH |
687 | break; |
688 | default: | |
689 | g_assert_not_reached(); | |
690 | } | |
691 | assert(env->misa_mxl_max == env->misa_mxl); | |
692 | ||
693 | /* If only MISA_EXT is unset for misa, then set it from properties */ | |
694 | if (env->misa_ext == 0) { | |
695 | uint32_t ext = 0; | |
696 | ||
b55d7d34 | 697 | /* Do some ISA extension error checking */ |
61cdf459 TO |
698 | if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && |
699 | cpu->cfg.ext_a && cpu->cfg.ext_f && | |
9f6b7da5 TO |
700 | cpu->cfg.ext_d && |
701 | cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { | |
702 | warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); | |
b55d7d34 AF |
703 | cpu->cfg.ext_i = true; |
704 | cpu->cfg.ext_m = true; | |
705 | cpu->cfg.ext_a = true; | |
706 | cpu->cfg.ext_f = true; | |
707 | cpu->cfg.ext_d = true; | |
9f6b7da5 TO |
708 | cpu->cfg.ext_icsr = true; |
709 | cpu->cfg.ext_ifencei = true; | |
b55d7d34 AF |
710 | } |
711 | ||
bb06941f WL |
712 | if (cpu->cfg.ext_i && cpu->cfg.ext_e) { |
713 | error_setg(errp, | |
714 | "I and E extensions are incompatible"); | |
715 | return; | |
716 | } | |
717 | ||
718 | if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { | |
719 | error_setg(errp, | |
720 | "Either I or E extension must be set"); | |
721 | return; | |
722 | } | |
723 | ||
0b572c81 WL |
724 | if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { |
725 | error_setg(errp, | |
726 | "Setting S extension without U extension is illegal"); | |
727 | return; | |
728 | } | |
729 | ||
756b0374 WL |
730 | if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { |
731 | error_setg(errp, | |
732 | "H depends on an I base integer ISA with 32 x registers"); | |
733 | return; | |
734 | } | |
735 | ||
62a09b9b WL |
736 | if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { |
737 | error_setg(errp, "H extension implicitly requires S-mode"); | |
738 | return; | |
739 | } | |
740 | ||
1086504c TO |
741 | if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { |
742 | error_setg(errp, "F extension requires Zicsr"); | |
743 | return; | |
744 | } | |
745 | ||
746 | if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) { | |
747 | error_setg(errp, "Zfh/Zfhmin extensions require F extension"); | |
748 | return; | |
749 | } | |
750 | ||
751 | if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { | |
752 | error_setg(errp, "D extension requires F extension"); | |
753 | return; | |
754 | } | |
755 | ||
756 | if (cpu->cfg.ext_v && !cpu->cfg.ext_d) { | |
757 | error_setg(errp, "V extension requires D extension"); | |
758 | return; | |
759 | } | |
760 | ||
bc573816 TO |
761 | if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) { |
762 | error_setg(errp, "Zve32f/Zve64f extensions require F extension"); | |
763 | return; | |
764 | } | |
765 | ||
766 | /* Set the ISA extensions, checks should have happened above */ | |
89ffdcec WL |
767 | if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || |
768 | cpu->cfg.ext_zhinxmin) { | |
769 | cpu->cfg.ext_zfinx = true; | |
770 | } | |
771 | ||
bc573816 TO |
772 | if (cpu->cfg.ext_zfinx) { |
773 | if (!cpu->cfg.ext_icsr) { | |
774 | error_setg(errp, "Zfinx extension requires Zicsr"); | |
775 | return; | |
776 | } | |
777 | if (cpu->cfg.ext_f) { | |
778 | error_setg(errp, | |
779 | "Zfinx cannot be supported together with F extension"); | |
780 | return; | |
781 | } | |
1086504c TO |
782 | } |
783 | ||
eef82872 WL |
784 | if (cpu->cfg.ext_zk) { |
785 | cpu->cfg.ext_zkn = true; | |
786 | cpu->cfg.ext_zkr = true; | |
787 | cpu->cfg.ext_zkt = true; | |
788 | } | |
789 | ||
790 | if (cpu->cfg.ext_zkn) { | |
791 | cpu->cfg.ext_zbkb = true; | |
792 | cpu->cfg.ext_zbkc = true; | |
793 | cpu->cfg.ext_zbkx = true; | |
794 | cpu->cfg.ext_zkne = true; | |
795 | cpu->cfg.ext_zknd = true; | |
796 | cpu->cfg.ext_zknh = true; | |
797 | } | |
798 | ||
799 | if (cpu->cfg.ext_zks) { | |
800 | cpu->cfg.ext_zbkb = true; | |
801 | cpu->cfg.ext_zbkc = true; | |
802 | cpu->cfg.ext_zbkx = true; | |
803 | cpu->cfg.ext_zksed = true; | |
804 | cpu->cfg.ext_zksh = true; | |
805 | } | |
806 | ||
b55d7d34 | 807 | if (cpu->cfg.ext_i) { |
e91a7227 | 808 | ext |= RVI; |
b55d7d34 AF |
809 | } |
810 | if (cpu->cfg.ext_e) { | |
e91a7227 | 811 | ext |= RVE; |
b55d7d34 AF |
812 | } |
813 | if (cpu->cfg.ext_m) { | |
e91a7227 | 814 | ext |= RVM; |
b55d7d34 AF |
815 | } |
816 | if (cpu->cfg.ext_a) { | |
e91a7227 | 817 | ext |= RVA; |
b55d7d34 AF |
818 | } |
819 | if (cpu->cfg.ext_f) { | |
e91a7227 | 820 | ext |= RVF; |
b55d7d34 AF |
821 | } |
822 | if (cpu->cfg.ext_d) { | |
e91a7227 | 823 | ext |= RVD; |
b55d7d34 AF |
824 | } |
825 | if (cpu->cfg.ext_c) { | |
e91a7227 | 826 | ext |= RVC; |
b55d7d34 AF |
827 | } |
828 | if (cpu->cfg.ext_s) { | |
e91a7227 | 829 | ext |= RVS; |
b55d7d34 AF |
830 | } |
831 | if (cpu->cfg.ext_u) { | |
e91a7227 | 832 | ext |= RVU; |
b55d7d34 | 833 | } |
c9eefe05 | 834 | if (cpu->cfg.ext_h) { |
e91a7227 | 835 | ext |= RVH; |
c9eefe05 | 836 | } |
6bf91617 | 837 | if (cpu->cfg.ext_v) { |
9ec6622d | 838 | int vext_version = VEXT_VERSION_1_00_0; |
e91a7227 | 839 | ext |= RVV; |
6bf91617 LZ |
840 | if (!is_power_of_2(cpu->cfg.vlen)) { |
841 | error_setg(errp, | |
842 | "Vector extension VLEN must be power of 2"); | |
843 | return; | |
844 | } | |
845 | if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { | |
846 | error_setg(errp, | |
847 | "Vector extension implementation only supports VLEN " | |
848 | "in the range [128, %d]", RV_VLEN_MAX); | |
849 | return; | |
850 | } | |
851 | if (!is_power_of_2(cpu->cfg.elen)) { | |
852 | error_setg(errp, | |
853 | "Vector extension ELEN must be power of 2"); | |
854 | return; | |
855 | } | |
856 | if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) { | |
857 | error_setg(errp, | |
858 | "Vector extension implementation only supports ELEN " | |
859 | "in the range [8, 64]"); | |
860 | return; | |
861 | } | |
862 | if (cpu->cfg.vext_spec) { | |
9ec6622d FC |
863 | if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { |
864 | vext_version = VEXT_VERSION_1_00_0; | |
6bf91617 LZ |
865 | } else { |
866 | error_setg(errp, | |
867 | "Unsupported vector spec version '%s'", | |
868 | cpu->cfg.vext_spec); | |
869 | return; | |
870 | } | |
871 | } else { | |
cba42d61 | 872 | qemu_log("vector version is not specified, " |
9ec6622d | 873 | "use the default value v1.0\n"); |
6bf91617 LZ |
874 | } |
875 | set_vext_version(env, vext_version); | |
876 | } | |
0ee9a4e5 AB |
877 | if (cpu->cfg.ext_j) { |
878 | ext |= RVJ; | |
879 | } | |
b55d7d34 | 880 | |
e91a7227 | 881 | set_misa(env, env->misa_mxl, ext); |
b55d7d34 AF |
882 | } |
883 | ||
5371f5cd JW |
884 | riscv_cpu_register_gdb_regs_for_features(cs); |
885 | ||
dc5bd18f MC |
886 | qemu_init_vcpu(cs); |
887 | cpu_reset(cs); | |
888 | ||
889 | mcc->parent_realize(dev, errp); | |
890 | } | |
891 | ||
0f0b70ee AF |
892 | #ifndef CONFIG_USER_ONLY |
893 | static void riscv_cpu_set_irq(void *opaque, int irq, int level) | |
894 | { | |
895 | RISCVCPU *cpu = RISCV_CPU(opaque); | |
cd032fe7 | 896 | CPURISCVState *env = &cpu->env; |
0f0b70ee | 897 | |
cd032fe7 AP |
898 | if (irq < IRQ_LOCAL_MAX) { |
899 | switch (irq) { | |
900 | case IRQ_U_SOFT: | |
901 | case IRQ_S_SOFT: | |
902 | case IRQ_VS_SOFT: | |
903 | case IRQ_M_SOFT: | |
904 | case IRQ_U_TIMER: | |
905 | case IRQ_S_TIMER: | |
906 | case IRQ_VS_TIMER: | |
907 | case IRQ_M_TIMER: | |
908 | case IRQ_U_EXT: | |
cd032fe7 AP |
909 | case IRQ_VS_EXT: |
910 | case IRQ_M_EXT: | |
8b5c807b | 911 | if (kvm_enabled()) { |
cd032fe7 | 912 | kvm_riscv_set_irq(cpu, irq, level); |
8b5c807b | 913 | } else { |
cd032fe7 | 914 | riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); |
8b5c807b | 915 | } |
cd032fe7 | 916 | break; |
33fe584f AF |
917 | case IRQ_S_EXT: |
918 | if (kvm_enabled()) { | |
919 | kvm_riscv_set_irq(cpu, irq, level); | |
920 | } else { | |
921 | env->external_seip = level; | |
922 | riscv_cpu_update_mip(cpu, 1 << irq, | |
923 | BOOL_TO_MASK(level | env->software_seip)); | |
924 | } | |
925 | break; | |
cd032fe7 AP |
926 | default: |
927 | g_assert_not_reached(); | |
2b650fbb | 928 | } |
cd032fe7 AP |
929 | } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { |
930 | /* Require H-extension for handling guest local interrupts */ | |
931 | if (!riscv_has_ext(env, RVH)) { | |
932 | g_assert_not_reached(); | |
933 | } | |
934 | ||
935 | /* Compute bit position in HGEIP CSR */ | |
936 | irq = irq - IRQ_LOCAL_MAX + 1; | |
937 | if (env->geilen < irq) { | |
938 | g_assert_not_reached(); | |
939 | } | |
940 | ||
941 | /* Update HGEIP CSR */ | |
942 | env->hgeip &= ~((target_ulong)1 << irq); | |
943 | if (level) { | |
944 | env->hgeip |= (target_ulong)1 << irq; | |
945 | } | |
946 | ||
947 | /* Update mip.SGEIP bit */ | |
948 | riscv_cpu_update_mip(cpu, MIP_SGEIP, | |
949 | BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); | |
950 | } else { | |
0f0b70ee AF |
951 | g_assert_not_reached(); |
952 | } | |
953 | } | |
954 | #endif /* CONFIG_USER_ONLY */ | |
955 | ||
dc5bd18f MC |
956 | static void riscv_cpu_init(Object *obj) |
957 | { | |
dc5bd18f MC |
958 | RISCVCPU *cpu = RISCV_CPU(obj); |
959 | ||
26b2bc58 AF |
960 | cpu->cfg.ext_ifencei = true; |
961 | cpu->cfg.ext_icsr = true; | |
962 | cpu->cfg.mmu = true; | |
963 | cpu->cfg.pmp = true; | |
964 | ||
7506ed90 | 965 | cpu_set_cpustate_pointers(cpu); |
0f0b70ee AF |
966 | |
967 | #ifndef CONFIG_USER_ONLY | |
cd032fe7 AP |
968 | qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, |
969 | IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); | |
0f0b70ee | 970 | #endif /* CONFIG_USER_ONLY */ |
dc5bd18f MC |
971 | } |
972 | ||
26b2bc58 | 973 | static Property riscv_cpu_extensions[] = { |
9d3d60b7 | 974 | /* Defaults for standard extensions */ |
b55d7d34 AF |
975 | DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), |
976 | DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), | |
1d398ab9 | 977 | DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), |
b55d7d34 AF |
978 | DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), |
979 | DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), | |
980 | DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), | |
981 | DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), | |
982 | DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), | |
983 | DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), | |
984 | DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), | |
9ec6622d | 985 | DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), |
07cb270a | 986 | DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), |
18d6d89e | 987 | DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), |
9d3d60b7 AF |
988 | DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), |
989 | DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), | |
4696f0ab | 990 | DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), |
13fb8c7b | 991 | DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), |
e5237730 | 992 | DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), |
2fc1b44d | 993 | DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), |
bfefe406 | 994 | DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), |
9d3d60b7 AF |
995 | DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), |
996 | DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), | |
997 | ||
998 | DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), | |
9ec6622d FC |
999 | DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), |
1000 | DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), | |
1001 | DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), | |
9d3d60b7 | 1002 | |
c5d77ddd | 1003 | DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), |
2bacb224 | 1004 | DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), |
bbce8ba8 | 1005 | DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), |
2bacb224 | 1006 | |
0643c12e VG |
1007 | DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), |
1008 | DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), | |
1009 | DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), | |
cf7ed971 WL |
1010 | DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false), |
1011 | DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false), | |
1012 | DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false), | |
0643c12e | 1013 | DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), |
cf7ed971 WL |
1014 | DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false), |
1015 | DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false), | |
1016 | DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false), | |
1017 | DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false), | |
1018 | DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false), | |
1019 | DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false), | |
1020 | DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false), | |
1021 | DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false), | |
1022 | DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), | |
1023 | DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), | |
dfdb46a3 | 1024 | |
6b1accef WL |
1025 | DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), |
1026 | DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), | |
1027 | DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), | |
1028 | DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), | |
1029 | ||
6d00ffad WL |
1030 | DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), |
1031 | ||
0d429bd2 PT |
1032 | /* Vendor-specific custom extensions */ |
1033 | DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), | |
1034 | ||
dfdb46a3 | 1035 | /* These are experimental so mark with 'x-' */ |
0ee9a4e5 | 1036 | DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), |
a44da25a | 1037 | /* ePMP 0.9.3 */ |
5da9514e | 1038 | DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), |
dc9acc9c AP |
1039 | DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), |
1040 | DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), | |
5da9514e | 1041 | |
26b2bc58 AF |
1042 | DEFINE_PROP_END_OF_LIST(), |
1043 | }; | |
1044 | ||
1045 | static void register_cpu_props(DeviceState *dev) | |
1046 | { | |
1047 | Property *prop; | |
1048 | ||
1049 | for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { | |
1050 | qdev_property_add_static(dev, prop); | |
1051 | } | |
1052 | } | |
1053 | ||
1054 | static Property riscv_cpu_properties[] = { | |
1055 | DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), | |
1056 | ||
1057 | DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), | |
1058 | DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), | |
1059 | DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), | |
1060 | ||
9b4c9b2b | 1061 | DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), |
a4a9a443 TO |
1062 | |
1063 | DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), | |
b8312675 | 1064 | |
1065 | DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), | |
1ad3f9bd | 1066 | DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), |
c4e95030 AF |
1067 | DEFINE_PROP_END_OF_LIST(), |
1068 | }; | |
1069 | ||
edf64786 SP |
1070 | static gchar *riscv_gdb_arch_name(CPUState *cs) |
1071 | { | |
1072 | RISCVCPU *cpu = RISCV_CPU(cs); | |
1073 | CPURISCVState *env = &cpu->env; | |
1074 | ||
db23e5d9 RH |
1075 | switch (riscv_cpu_mxl(env)) { |
1076 | case MXL_RV32: | |
edf64786 | 1077 | return g_strdup("riscv:rv32"); |
db23e5d9 | 1078 | case MXL_RV64: |
332dab68 | 1079 | case MXL_RV128: |
edf64786 | 1080 | return g_strdup("riscv:rv64"); |
db23e5d9 RH |
1081 | default: |
1082 | g_assert_not_reached(); | |
edf64786 SP |
1083 | } |
1084 | } | |
1085 | ||
b93777e1 BM |
1086 | static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) |
1087 | { | |
1088 | RISCVCPU *cpu = RISCV_CPU(cs); | |
1089 | ||
1090 | if (strcmp(xmlname, "riscv-csr.xml") == 0) { | |
1091 | return cpu->dyn_csr_xml; | |
719d3561 HW |
1092 | } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { |
1093 | return cpu->dyn_vreg_xml; | |
b93777e1 BM |
1094 | } |
1095 | ||
1096 | return NULL; | |
1097 | } | |
1098 | ||
8b80bd28 PMD |
1099 | #ifndef CONFIG_USER_ONLY |
1100 | #include "hw/core/sysemu-cpu-ops.h" | |
1101 | ||
1102 | static const struct SysemuCPUOps riscv_sysemu_ops = { | |
08928c6d | 1103 | .get_phys_page_debug = riscv_cpu_get_phys_page_debug, |
715e3c1a PMD |
1104 | .write_elf64_note = riscv_cpu_write_elf64_note, |
1105 | .write_elf32_note = riscv_cpu_write_elf32_note, | |
feece4d0 | 1106 | .legacy_vmsd = &vmstate_riscv_cpu, |
8b80bd28 PMD |
1107 | }; |
1108 | #endif | |
1109 | ||
78271684 CF |
1110 | #include "hw/core/tcg-cpu-ops.h" |
1111 | ||
11906557 | 1112 | static const struct TCGCPUOps riscv_tcg_ops = { |
78271684 CF |
1113 | .initialize = riscv_translate_init, |
1114 | .synchronize_from_tb = riscv_cpu_synchronize_from_tb, | |
78271684 CF |
1115 | |
1116 | #ifndef CONFIG_USER_ONLY | |
263e2ab2 | 1117 | .tlb_fill = riscv_cpu_tlb_fill, |
17b3c353 | 1118 | .cpu_exec_interrupt = riscv_cpu_exec_interrupt, |
78271684 CF |
1119 | .do_interrupt = riscv_cpu_do_interrupt, |
1120 | .do_transaction_failed = riscv_cpu_do_transaction_failed, | |
1121 | .do_unaligned_access = riscv_cpu_do_unaligned_access, | |
b5f6379d BM |
1122 | .debug_excp_handler = riscv_cpu_debug_excp_handler, |
1123 | .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, | |
1124 | .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, | |
78271684 CF |
1125 | #endif /* !CONFIG_USER_ONLY */ |
1126 | }; | |
1127 | ||
dc5bd18f MC |
1128 | static void riscv_cpu_class_init(ObjectClass *c, void *data) |
1129 | { | |
1130 | RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); | |
1131 | CPUClass *cc = CPU_CLASS(c); | |
1132 | DeviceClass *dc = DEVICE_CLASS(c); | |
1133 | ||
41fbbba7 MZ |
1134 | device_class_set_parent_realize(dc, riscv_cpu_realize, |
1135 | &mcc->parent_realize); | |
dc5bd18f | 1136 | |
781c67ca | 1137 | device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset); |
dc5bd18f MC |
1138 | |
1139 | cc->class_by_name = riscv_cpu_class_by_name; | |
1140 | cc->has_work = riscv_cpu_has_work; | |
dc5bd18f MC |
1141 | cc->dump_state = riscv_cpu_dump_state; |
1142 | cc->set_pc = riscv_cpu_set_pc; | |
dc5bd18f MC |
1143 | cc->gdb_read_register = riscv_cpu_gdb_read_register; |
1144 | cc->gdb_write_register = riscv_cpu_gdb_write_register; | |
5371f5cd | 1145 | cc->gdb_num_core_regs = 33; |
dc5bd18f MC |
1146 | cc->gdb_stop_before_watchpoint = true; |
1147 | cc->disas_set_info = riscv_cpu_disas_set_info; | |
8a4ca3c1 | 1148 | #ifndef CONFIG_USER_ONLY |
8b80bd28 | 1149 | cc->sysemu_ops = &riscv_sysemu_ops; |
dc5bd18f | 1150 | #endif |
edf64786 | 1151 | cc->gdb_arch_name = riscv_gdb_arch_name; |
b93777e1 | 1152 | cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; |
78271684 | 1153 | cc->tcg_ops = &riscv_tcg_ops; |
6a3d2e7c | 1154 | |
4f67d30b | 1155 | device_class_set_props(dc, riscv_cpu_properties); |
dc5bd18f MC |
1156 | } |
1157 | ||
a775398b AP |
1158 | static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) |
1159 | { | |
1160 | char *old = *isa_str; | |
1161 | char *new = *isa_str; | |
1162 | int i; | |
1163 | ||
a775398b | 1164 | for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { |
9a1f054d AP |
1165 | if (isa_edata_arr[i].multi_letter && |
1166 | isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { | |
a775398b AP |
1167 | new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); |
1168 | g_free(old); | |
1169 | old = new; | |
1170 | } | |
1171 | } | |
1172 | ||
1173 | *isa_str = new; | |
1174 | } | |
1175 | ||
dc5bd18f MC |
1176 | char *riscv_isa_string(RISCVCPU *cpu) |
1177 | { | |
1178 | int i; | |
0e2c3770 | 1179 | const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); |
d1fd31f8 MC |
1180 | char *isa_str = g_new(char, maxlen); |
1181 | char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); | |
0e2c3770 TO |
1182 | for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { |
1183 | if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { | |
1184 | *p++ = qemu_tolower(riscv_single_letter_exts[i]); | |
dc5bd18f MC |
1185 | } |
1186 | } | |
d1fd31f8 | 1187 | *p = '\0'; |
a4a9a443 TO |
1188 | if (!cpu->cfg.short_isa_string) { |
1189 | riscv_isa_string_ext(cpu, &isa_str, maxlen); | |
1190 | } | |
d1fd31f8 | 1191 | return isa_str; |
dc5bd18f MC |
1192 | } |
1193 | ||
eab15862 | 1194 | static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) |
dc5bd18f | 1195 | { |
eab15862 MC |
1196 | ObjectClass *class_a = (ObjectClass *)a; |
1197 | ObjectClass *class_b = (ObjectClass *)b; | |
1198 | const char *name_a, *name_b; | |
dc5bd18f | 1199 | |
eab15862 MC |
1200 | name_a = object_class_get_name(class_a); |
1201 | name_b = object_class_get_name(class_b); | |
1202 | return strcmp(name_a, name_b); | |
dc5bd18f MC |
1203 | } |
1204 | ||
eab15862 | 1205 | static void riscv_cpu_list_entry(gpointer data, gpointer user_data) |
dc5bd18f | 1206 | { |
eab15862 MC |
1207 | const char *typename = object_class_get_name(OBJECT_CLASS(data)); |
1208 | int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); | |
dc5bd18f | 1209 | |
0442428a | 1210 | qemu_printf("%.*s\n", len, typename); |
eab15862 | 1211 | } |
dc5bd18f | 1212 | |
0442428a | 1213 | void riscv_cpu_list(void) |
eab15862 | 1214 | { |
eab15862 MC |
1215 | GSList *list; |
1216 | ||
1217 | list = object_class_get_list(TYPE_RISCV_CPU, false); | |
1218 | list = g_slist_sort(list, riscv_cpu_list_compare); | |
0442428a | 1219 | g_slist_foreach(list, riscv_cpu_list_entry, NULL); |
eab15862 | 1220 | g_slist_free(list); |
dc5bd18f MC |
1221 | } |
1222 | ||
eab15862 MC |
1223 | #define DEFINE_CPU(type_name, initfn) \ |
1224 | { \ | |
1225 | .name = type_name, \ | |
1226 | .parent = TYPE_RISCV_CPU, \ | |
1227 | .instance_init = initfn \ | |
1228 | } | |
1229 | ||
1230 | static const TypeInfo riscv_cpu_type_infos[] = { | |
1231 | { | |
1232 | .name = TYPE_RISCV_CPU, | |
1233 | .parent = TYPE_CPU, | |
1234 | .instance_size = sizeof(RISCVCPU), | |
5de5b99b | 1235 | .instance_align = __alignof__(RISCVCPU), |
eab15862 MC |
1236 | .instance_init = riscv_cpu_init, |
1237 | .abstract = true, | |
1238 | .class_size = sizeof(RISCVCPUClass), | |
1239 | .class_init = riscv_cpu_class_init, | |
1240 | }, | |
1241 | DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), | |
10f1ca27 YJ |
1242 | #if defined(CONFIG_KVM) |
1243 | DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), | |
1244 | #endif | |
eab15862 | 1245 | #if defined(TARGET_RISCV32) |
094b072c | 1246 | DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), |
e8905c6c | 1247 | DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), |
114baaca | 1248 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), |
2fdd2c09 | 1249 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), |
114baaca | 1250 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), |
eab15862 | 1251 | #elif defined(TARGET_RISCV64) |
094b072c | 1252 | DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), |
114baaca AF |
1253 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), |
1254 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), | |
6ddc7069 | 1255 | DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), |
332dab68 | 1256 | DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), |
eab15862 MC |
1257 | #endif |
1258 | }; | |
1259 | ||
1260 | DEFINE_TYPES(riscv_cpu_type_infos) |