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dc5bd18f MC |
1 | /* |
2 | * QEMU RISC-V CPU | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
0442428a | 21 | #include "qemu/qemu-print.h" |
856dfd8a | 22 | #include "qemu/ctype.h" |
dc5bd18f MC |
23 | #include "qemu/log.h" |
24 | #include "cpu.h" | |
95bd8daa | 25 | #include "cpu_vendorid.h" |
14664483 | 26 | #include "pmu.h" |
f7697f0e | 27 | #include "internals.h" |
43888c2f | 28 | #include "time_helper.h" |
dc5bd18f MC |
29 | #include "exec/exec-all.h" |
30 | #include "qapi/error.h" | |
6f23aaeb | 31 | #include "qapi/visitor.h" |
b55d7d34 | 32 | #include "qemu/error-report.h" |
c4e95030 | 33 | #include "hw/qdev-properties.h" |
dc5bd18f | 34 | #include "migration/vmstate.h" |
135b03cb | 35 | #include "fpu/softfloat-helpers.h" |
ad40be27 YJ |
36 | #include "sysemu/kvm.h" |
37 | #include "kvm_riscv.h" | |
0489d5bd | 38 | #include "tcg/tcg.h" |
dc5bd18f MC |
39 | |
40 | /* RISC-V CPU definitions */ | |
41 | ||
9951ba94 FC |
42 | #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ |
43 | (QEMU_VERSION_MINOR << 8) | \ | |
44 | (QEMU_VERSION_MICRO)) | |
075eeda9 | 45 | #define RISCV_CPU_MIMPID RISCV_CPU_MARCHID |
9951ba94 | 46 | |
0e2c3770 | 47 | static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; |
dc5bd18f | 48 | |
a775398b AP |
49 | struct isa_ext_data { |
50 | const char *name; | |
9a1f054d AP |
51 | int min_version; |
52 | int ext_enable_offset; | |
a775398b AP |
53 | }; |
54 | ||
ccc84a75 DHB |
55 | #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ |
56 | {#_name, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} | |
9a1f054d | 57 | |
3b57254d | 58 | /* |
9a1f054d AP |
59 | * Here are the ordering rules of extension naming defined by RISC-V |
60 | * specification : | |
61 | * 1. All extensions should be separated from other multi-letter extensions | |
62 | * by an underscore. | |
63 | * 2. The first letter following the 'Z' conventionally indicates the most | |
64 | * closely related alphabetical extension category, IMAFDQLCBKJTPVH. | |
65 | * If multiple 'Z' extensions are named, they should be ordered first | |
66 | * by category, then alphabetically within a category. | |
67 | * 3. Standard supervisor-level extensions (starts with 'S') should be | |
68 | * listed after standard unprivileged extensions. If multiple | |
69 | * supervisor-level extensions are listed, they should be ordered | |
70 | * alphabetically. | |
71 | * 4. Non-standard extensions (starts with 'X') must be listed after all | |
72 | * standard extensions. They must be separated from other multi-letter | |
73 | * extensions by an underscore. | |
6508272a DHB |
74 | * |
75 | * Single letter extensions are checked in riscv_cpu_validate_misa_priv() | |
76 | * instead. | |
9a1f054d AP |
77 | */ |
78 | static const struct isa_ext_data isa_edata_arr[] = { | |
ccc84a75 DHB |
79 | ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom), |
80 | ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz), | |
81 | ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), | |
82 | ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr), | |
83 | ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei), | |
84 | ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), | |
85 | ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs), | |
86 | ISA_EXT_DATA_ENTRY(zfh, PRIV_VERSION_1_11_0, ext_zfh), | |
87 | ISA_EXT_DATA_ENTRY(zfhmin, PRIV_VERSION_1_11_0, ext_zfhmin), | |
88 | ISA_EXT_DATA_ENTRY(zfinx, PRIV_VERSION_1_12_0, ext_zfinx), | |
89 | ISA_EXT_DATA_ENTRY(zdinx, PRIV_VERSION_1_12_0, ext_zdinx), | |
90 | ISA_EXT_DATA_ENTRY(zca, PRIV_VERSION_1_12_0, ext_zca), | |
91 | ISA_EXT_DATA_ENTRY(zcb, PRIV_VERSION_1_12_0, ext_zcb), | |
92 | ISA_EXT_DATA_ENTRY(zcf, PRIV_VERSION_1_12_0, ext_zcf), | |
93 | ISA_EXT_DATA_ENTRY(zcd, PRIV_VERSION_1_12_0, ext_zcd), | |
94 | ISA_EXT_DATA_ENTRY(zce, PRIV_VERSION_1_12_0, ext_zce), | |
95 | ISA_EXT_DATA_ENTRY(zcmp, PRIV_VERSION_1_12_0, ext_zcmp), | |
96 | ISA_EXT_DATA_ENTRY(zcmt, PRIV_VERSION_1_12_0, ext_zcmt), | |
97 | ISA_EXT_DATA_ENTRY(zba, PRIV_VERSION_1_12_0, ext_zba), | |
98 | ISA_EXT_DATA_ENTRY(zbb, PRIV_VERSION_1_12_0, ext_zbb), | |
99 | ISA_EXT_DATA_ENTRY(zbc, PRIV_VERSION_1_12_0, ext_zbc), | |
100 | ISA_EXT_DATA_ENTRY(zbkb, PRIV_VERSION_1_12_0, ext_zbkb), | |
101 | ISA_EXT_DATA_ENTRY(zbkc, PRIV_VERSION_1_12_0, ext_zbkc), | |
102 | ISA_EXT_DATA_ENTRY(zbkx, PRIV_VERSION_1_12_0, ext_zbkx), | |
103 | ISA_EXT_DATA_ENTRY(zbs, PRIV_VERSION_1_12_0, ext_zbs), | |
104 | ISA_EXT_DATA_ENTRY(zk, PRIV_VERSION_1_12_0, ext_zk), | |
105 | ISA_EXT_DATA_ENTRY(zkn, PRIV_VERSION_1_12_0, ext_zkn), | |
106 | ISA_EXT_DATA_ENTRY(zknd, PRIV_VERSION_1_12_0, ext_zknd), | |
107 | ISA_EXT_DATA_ENTRY(zkne, PRIV_VERSION_1_12_0, ext_zkne), | |
108 | ISA_EXT_DATA_ENTRY(zknh, PRIV_VERSION_1_12_0, ext_zknh), | |
109 | ISA_EXT_DATA_ENTRY(zkr, PRIV_VERSION_1_12_0, ext_zkr), | |
110 | ISA_EXT_DATA_ENTRY(zks, PRIV_VERSION_1_12_0, ext_zks), | |
111 | ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed), | |
112 | ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh), | |
113 | ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt), | |
114 | ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f), | |
115 | ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f), | |
116 | ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d), | |
117 | ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh), | |
118 | ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), | |
119 | ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), | |
120 | ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), | |
121 | ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), | |
122 | ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), | |
123 | ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), | |
124 | ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), | |
125 | ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu), | |
126 | ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), | |
127 | ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), | |
128 | ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), | |
129 | ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), | |
130 | ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), | |
131 | ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), | |
132 | ISA_EXT_DATA_ENTRY(xtheadcmo, PRIV_VERSION_1_11_0, ext_xtheadcmo), | |
133 | ISA_EXT_DATA_ENTRY(xtheadcondmov, PRIV_VERSION_1_11_0, ext_xtheadcondmov), | |
134 | ISA_EXT_DATA_ENTRY(xtheadfmemidx, PRIV_VERSION_1_11_0, ext_xtheadfmemidx), | |
135 | ISA_EXT_DATA_ENTRY(xtheadfmv, PRIV_VERSION_1_11_0, ext_xtheadfmv), | |
136 | ISA_EXT_DATA_ENTRY(xtheadmac, PRIV_VERSION_1_11_0, ext_xtheadmac), | |
137 | ISA_EXT_DATA_ENTRY(xtheadmemidx, PRIV_VERSION_1_11_0, ext_xtheadmemidx), | |
138 | ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempair), | |
139 | ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync), | |
140 | ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), | |
9a1f054d AP |
141 | }; |
142 | ||
143 | static bool isa_ext_is_enabled(RISCVCPU *cpu, | |
144 | const struct isa_ext_data *edata) | |
145 | { | |
146 | bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; | |
147 | ||
148 | return *ext_enabled; | |
149 | } | |
150 | ||
151 | static void isa_ext_update_enabled(RISCVCPU *cpu, | |
152 | const struct isa_ext_data *edata, bool en) | |
153 | { | |
154 | bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; | |
155 | ||
156 | *ext_enabled = en; | |
157 | } | |
158 | ||
dc5bd18f | 159 | const char * const riscv_int_regnames[] = { |
c45eff30 WL |
160 | "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", |
161 | "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", | |
162 | "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", | |
163 | "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", | |
164 | "x28/t3", "x29/t4", "x30/t5", "x31/t6" | |
dc5bd18f MC |
165 | }; |
166 | ||
2b547084 | 167 | const char * const riscv_int_regnamesh[] = { |
c45eff30 WL |
168 | "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", |
169 | "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", | |
170 | "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", | |
171 | "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", | |
172 | "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", | |
173 | "x30h/t5h", "x31h/t6h" | |
2b547084 FP |
174 | }; |
175 | ||
dc5bd18f | 176 | const char * const riscv_fpr_regnames[] = { |
c45eff30 WL |
177 | "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", |
178 | "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", | |
179 | "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", | |
180 | "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", | |
181 | "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", | |
182 | "f30/ft10", "f31/ft11" | |
dc5bd18f MC |
183 | }; |
184 | ||
9a575d33 | 185 | static const char * const riscv_excp_names[] = { |
dc5bd18f MC |
186 | "misaligned_fetch", |
187 | "fault_fetch", | |
188 | "illegal_instruction", | |
189 | "breakpoint", | |
190 | "misaligned_load", | |
191 | "fault_load", | |
192 | "misaligned_store", | |
193 | "fault_store", | |
194 | "user_ecall", | |
195 | "supervisor_ecall", | |
196 | "hypervisor_ecall", | |
197 | "machine_ecall", | |
198 | "exec_page_fault", | |
199 | "load_page_fault", | |
200 | "reserved", | |
fd990e86 | 201 | "store_page_fault", |
ab67a1d0 AF |
202 | "reserved", |
203 | "reserved", | |
204 | "reserved", | |
205 | "reserved", | |
206 | "guest_exec_page_fault", | |
207 | "guest_load_page_fault", | |
208 | "reserved", | |
fd990e86 | 209 | "guest_store_page_fault", |
dc5bd18f MC |
210 | }; |
211 | ||
9a575d33 | 212 | static const char * const riscv_intr_names[] = { |
dc5bd18f MC |
213 | "u_software", |
214 | "s_software", | |
205377f8 | 215 | "vs_software", |
dc5bd18f MC |
216 | "m_software", |
217 | "u_timer", | |
218 | "s_timer", | |
205377f8 | 219 | "vs_timer", |
dc5bd18f MC |
220 | "m_timer", |
221 | "u_external", | |
6cfcf775 | 222 | "s_external", |
205377f8 | 223 | "vs_external", |
dc5bd18f | 224 | "m_external", |
426f0348 MC |
225 | "reserved", |
226 | "reserved", | |
227 | "reserved", | |
228 | "reserved" | |
dc5bd18f MC |
229 | }; |
230 | ||
dd8f244f | 231 | static void riscv_cpu_add_user_properties(Object *obj); |
26b2bc58 | 232 | |
c51a3f5d YJ |
233 | const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) |
234 | { | |
235 | if (async) { | |
236 | return (cause < ARRAY_SIZE(riscv_intr_names)) ? | |
237 | riscv_intr_names[cause] : "(unknown)"; | |
238 | } else { | |
239 | return (cause < ARRAY_SIZE(riscv_excp_names)) ? | |
240 | riscv_excp_names[cause] : "(unknown)"; | |
241 | } | |
242 | } | |
243 | ||
e91a7227 | 244 | static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) |
dc5bd18f | 245 | { |
e91a7227 RH |
246 | env->misa_mxl_max = env->misa_mxl = mxl; |
247 | env->misa_ext_mask = env->misa_ext = ext; | |
dc5bd18f MC |
248 | } |
249 | ||
6f23aaeb AG |
250 | #ifndef CONFIG_USER_ONLY |
251 | static uint8_t satp_mode_from_str(const char *satp_mode_str) | |
252 | { | |
253 | if (!strncmp(satp_mode_str, "mbare", 5)) { | |
254 | return VM_1_10_MBARE; | |
255 | } | |
256 | ||
257 | if (!strncmp(satp_mode_str, "sv32", 4)) { | |
258 | return VM_1_10_SV32; | |
259 | } | |
260 | ||
261 | if (!strncmp(satp_mode_str, "sv39", 4)) { | |
262 | return VM_1_10_SV39; | |
263 | } | |
264 | ||
265 | if (!strncmp(satp_mode_str, "sv48", 4)) { | |
266 | return VM_1_10_SV48; | |
267 | } | |
268 | ||
269 | if (!strncmp(satp_mode_str, "sv57", 4)) { | |
270 | return VM_1_10_SV57; | |
271 | } | |
272 | ||
273 | if (!strncmp(satp_mode_str, "sv64", 4)) { | |
274 | return VM_1_10_SV64; | |
275 | } | |
276 | ||
277 | g_assert_not_reached(); | |
278 | } | |
279 | ||
280 | uint8_t satp_mode_max_from_map(uint32_t map) | |
281 | { | |
282 | /* map here has at least one bit set, so no problem with clz */ | |
283 | return 31 - __builtin_clz(map); | |
284 | } | |
285 | ||
286 | const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) | |
287 | { | |
288 | if (is_32_bit) { | |
289 | switch (satp_mode) { | |
290 | case VM_1_10_SV32: | |
291 | return "sv32"; | |
292 | case VM_1_10_MBARE: | |
293 | return "none"; | |
294 | } | |
295 | } else { | |
296 | switch (satp_mode) { | |
297 | case VM_1_10_SV64: | |
298 | return "sv64"; | |
299 | case VM_1_10_SV57: | |
300 | return "sv57"; | |
301 | case VM_1_10_SV48: | |
302 | return "sv48"; | |
303 | case VM_1_10_SV39: | |
304 | return "sv39"; | |
305 | case VM_1_10_MBARE: | |
306 | return "none"; | |
307 | } | |
308 | } | |
309 | ||
310 | g_assert_not_reached(); | |
311 | } | |
312 | ||
6df3747a AG |
313 | static void set_satp_mode_max_supported(RISCVCPU *cpu, |
314 | uint8_t satp_mode) | |
6f23aaeb AG |
315 | { |
316 | bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; | |
6df3747a | 317 | const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; |
6f23aaeb | 318 | |
6df3747a AG |
319 | for (int i = 0; i <= satp_mode; ++i) { |
320 | if (valid_vm[i]) { | |
321 | cpu->cfg.satp_mode.supported |= (1 << i); | |
322 | } | |
6f23aaeb AG |
323 | } |
324 | } | |
6df3747a AG |
325 | |
326 | /* Set the satp mode to the max supported */ | |
327 | static void set_satp_mode_default_map(RISCVCPU *cpu) | |
328 | { | |
329 | cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported; | |
330 | } | |
6f23aaeb AG |
331 | #endif |
332 | ||
dc5bd18f MC |
333 | static void riscv_any_cpu_init(Object *obj) |
334 | { | |
7f0bdfb5 DHB |
335 | RISCVCPU *cpu = RISCV_CPU(obj); |
336 | CPURISCVState *env = &cpu->env; | |
3820602f | 337 | #if defined(TARGET_RISCV32) |
e91a7227 | 338 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); |
3820602f | 339 | #elif defined(TARGET_RISCV64) |
e91a7227 | 340 | set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); |
3820602f | 341 | #endif |
6df3747a AG |
342 | |
343 | #ifndef CONFIG_USER_ONLY | |
344 | set_satp_mode_max_supported(RISCV_CPU(obj), | |
c45eff30 WL |
345 | riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ? |
346 | VM_1_10_SV32 : VM_1_10_SV57); | |
6df3747a AG |
347 | #endif |
348 | ||
b9a2b98e | 349 | env->priv_ver = PRIV_VERSION_LATEST; |
7f0bdfb5 DHB |
350 | |
351 | /* inherited from parent obj via riscv_cpu_init() */ | |
352 | cpu->cfg.ext_ifencei = true; | |
353 | cpu->cfg.ext_icsr = true; | |
354 | cpu->cfg.mmu = true; | |
355 | cpu->cfg.pmp = true; | |
dc5bd18f MC |
356 | } |
357 | ||
094b072c AF |
358 | #if defined(TARGET_RISCV64) |
359 | static void rv64_base_cpu_init(Object *obj) | |
8903bf6e AF |
360 | { |
361 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
b55d7d34 | 362 | /* We set this in the realise function */ |
e91a7227 | 363 | set_misa(env, MXL_RV64, 0); |
dd8f244f | 364 | riscv_cpu_add_user_properties(obj); |
18800095 | 365 | /* Set latest version of privileged specification */ |
b9a2b98e | 366 | env->priv_ver = PRIV_VERSION_LATEST; |
6df3747a AG |
367 | #ifndef CONFIG_USER_ONLY |
368 | set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); | |
369 | #endif | |
8903bf6e AF |
370 | } |
371 | ||
114baaca | 372 | static void rv64_sifive_u_cpu_init(Object *obj) |
dc5bd18f | 373 | { |
7f0bdfb5 DHB |
374 | RISCVCPU *cpu = RISCV_CPU(obj); |
375 | CPURISCVState *env = &cpu->env; | |
e91a7227 | 376 | set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); |
8c6eeb50 | 377 | env->priv_ver = PRIV_VERSION_1_10_0; |
6df3747a AG |
378 | #ifndef CONFIG_USER_ONLY |
379 | set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); | |
380 | #endif | |
7f0bdfb5 DHB |
381 | |
382 | /* inherited from parent obj via riscv_cpu_init() */ | |
383 | cpu->cfg.ext_ifencei = true; | |
384 | cpu->cfg.ext_icsr = true; | |
385 | cpu->cfg.mmu = true; | |
386 | cpu->cfg.pmp = true; | |
dc5bd18f MC |
387 | } |
388 | ||
114baaca | 389 | static void rv64_sifive_e_cpu_init(Object *obj) |
36b80ad9 AF |
390 | { |
391 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
26b2bc58 AF |
392 | RISCVCPU *cpu = RISCV_CPU(obj); |
393 | ||
e91a7227 | 394 | set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); |
8c6eeb50 | 395 | env->priv_ver = PRIV_VERSION_1_10_0; |
6df3747a AG |
396 | #ifndef CONFIG_USER_ONLY |
397 | set_satp_mode_max_supported(cpu, VM_1_10_MBARE); | |
398 | #endif | |
7f0bdfb5 DHB |
399 | |
400 | /* inherited from parent obj via riscv_cpu_init() */ | |
401 | cpu->cfg.ext_ifencei = true; | |
402 | cpu->cfg.ext_icsr = true; | |
403 | cpu->cfg.pmp = true; | |
36b80ad9 | 404 | } |
332dab68 | 405 | |
95bd8daa CM |
406 | static void rv64_thead_c906_cpu_init(Object *obj) |
407 | { | |
408 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
409 | RISCVCPU *cpu = RISCV_CPU(obj); | |
410 | ||
4f13abcb | 411 | set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU); |
8c6eeb50 | 412 | env->priv_ver = PRIV_VERSION_1_11_0; |
95bd8daa | 413 | |
95bd8daa CM |
414 | cpu->cfg.ext_zfh = true; |
415 | cpu->cfg.mmu = true; | |
416 | cpu->cfg.ext_xtheadba = true; | |
417 | cpu->cfg.ext_xtheadbb = true; | |
418 | cpu->cfg.ext_xtheadbs = true; | |
419 | cpu->cfg.ext_xtheadcmo = true; | |
420 | cpu->cfg.ext_xtheadcondmov = true; | |
421 | cpu->cfg.ext_xtheadfmemidx = true; | |
422 | cpu->cfg.ext_xtheadmac = true; | |
423 | cpu->cfg.ext_xtheadmemidx = true; | |
424 | cpu->cfg.ext_xtheadmempair = true; | |
425 | cpu->cfg.ext_xtheadsync = true; | |
426 | ||
427 | cpu->cfg.mvendorid = THEAD_VENDOR_ID; | |
6df3747a AG |
428 | #ifndef CONFIG_USER_ONLY |
429 | set_satp_mode_max_supported(cpu, VM_1_10_SV39); | |
430 | #endif | |
7f0bdfb5 DHB |
431 | |
432 | /* inherited from parent obj via riscv_cpu_init() */ | |
433 | cpu->cfg.pmp = true; | |
95bd8daa CM |
434 | } |
435 | ||
e1d084a8 RP |
436 | static void rv64_veyron_v1_cpu_init(Object *obj) |
437 | { | |
438 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
439 | RISCVCPU *cpu = RISCV_CPU(obj); | |
440 | ||
441 | set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH); | |
442 | env->priv_ver = PRIV_VERSION_1_12_0; | |
443 | ||
444 | /* Enable ISA extensions */ | |
445 | cpu->cfg.mmu = true; | |
446 | cpu->cfg.ext_icbom = true; | |
447 | cpu->cfg.cbom_blocksize = 64; | |
448 | cpu->cfg.cboz_blocksize = 64; | |
449 | cpu->cfg.ext_icboz = true; | |
450 | cpu->cfg.ext_smaia = true; | |
451 | cpu->cfg.ext_ssaia = true; | |
452 | cpu->cfg.ext_sscofpmf = true; | |
453 | cpu->cfg.ext_sstc = true; | |
454 | cpu->cfg.ext_svinval = true; | |
455 | cpu->cfg.ext_svnapot = true; | |
456 | cpu->cfg.ext_svpbmt = true; | |
457 | cpu->cfg.ext_smstateen = true; | |
458 | cpu->cfg.ext_zba = true; | |
459 | cpu->cfg.ext_zbb = true; | |
460 | cpu->cfg.ext_zbc = true; | |
461 | cpu->cfg.ext_zbs = true; | |
462 | cpu->cfg.ext_XVentanaCondOps = true; | |
463 | ||
464 | cpu->cfg.mvendorid = VEYRON_V1_MVENDORID; | |
465 | cpu->cfg.marchid = VEYRON_V1_MARCHID; | |
466 | cpu->cfg.mimpid = VEYRON_V1_MIMPID; | |
467 | ||
468 | #ifndef CONFIG_USER_ONLY | |
469 | set_satp_mode_max_supported(cpu, VM_1_10_SV48); | |
470 | #endif | |
471 | } | |
472 | ||
332dab68 FP |
473 | static void rv128_base_cpu_init(Object *obj) |
474 | { | |
475 | if (qemu_tcg_mttcg_enabled()) { | |
476 | /* Missing 128-bit aligned atomics */ | |
477 | error_report("128-bit RISC-V currently does not work with Multi " | |
478 | "Threaded TCG. Please use: -accel tcg,thread=single"); | |
479 | exit(EXIT_FAILURE); | |
480 | } | |
481 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
482 | /* We set this in the realise function */ | |
483 | set_misa(env, MXL_RV128, 0); | |
dd8f244f | 484 | riscv_cpu_add_user_properties(obj); |
18800095 | 485 | /* Set latest version of privileged specification */ |
b9a2b98e | 486 | env->priv_ver = PRIV_VERSION_LATEST; |
6df3747a AG |
487 | #ifndef CONFIG_USER_ONLY |
488 | set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); | |
489 | #endif | |
332dab68 | 490 | } |
114baaca | 491 | #else |
094b072c AF |
492 | static void rv32_base_cpu_init(Object *obj) |
493 | { | |
494 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
495 | /* We set this in the realise function */ | |
e91a7227 | 496 | set_misa(env, MXL_RV32, 0); |
dd8f244f | 497 | riscv_cpu_add_user_properties(obj); |
18800095 | 498 | /* Set latest version of privileged specification */ |
b9a2b98e | 499 | env->priv_ver = PRIV_VERSION_LATEST; |
6df3747a AG |
500 | #ifndef CONFIG_USER_ONLY |
501 | set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); | |
502 | #endif | |
094b072c AF |
503 | } |
504 | ||
114baaca AF |
505 | static void rv32_sifive_u_cpu_init(Object *obj) |
506 | { | |
7f0bdfb5 DHB |
507 | RISCVCPU *cpu = RISCV_CPU(obj); |
508 | CPURISCVState *env = &cpu->env; | |
e91a7227 | 509 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); |
8c6eeb50 | 510 | env->priv_ver = PRIV_VERSION_1_10_0; |
6df3747a AG |
511 | #ifndef CONFIG_USER_ONLY |
512 | set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); | |
513 | #endif | |
7f0bdfb5 DHB |
514 | |
515 | /* inherited from parent obj via riscv_cpu_init() */ | |
516 | cpu->cfg.ext_ifencei = true; | |
517 | cpu->cfg.ext_icsr = true; | |
518 | cpu->cfg.mmu = true; | |
519 | cpu->cfg.pmp = true; | |
114baaca | 520 | } |
36b80ad9 | 521 | |
114baaca AF |
522 | static void rv32_sifive_e_cpu_init(Object *obj) |
523 | { | |
524 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
26b2bc58 AF |
525 | RISCVCPU *cpu = RISCV_CPU(obj); |
526 | ||
e91a7227 | 527 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); |
8c6eeb50 | 528 | env->priv_ver = PRIV_VERSION_1_10_0; |
6df3747a AG |
529 | #ifndef CONFIG_USER_ONLY |
530 | set_satp_mode_max_supported(cpu, VM_1_10_MBARE); | |
531 | #endif | |
7f0bdfb5 DHB |
532 | |
533 | /* inherited from parent obj via riscv_cpu_init() */ | |
534 | cpu->cfg.ext_ifencei = true; | |
535 | cpu->cfg.ext_icsr = true; | |
536 | cpu->cfg.pmp = true; | |
114baaca | 537 | } |
d8e72bd1 | 538 | |
e8905c6c | 539 | static void rv32_ibex_cpu_init(Object *obj) |
dc5bd18f MC |
540 | { |
541 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
26b2bc58 AF |
542 | RISCVCPU *cpu = RISCV_CPU(obj); |
543 | ||
e91a7227 | 544 | set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); |
8c6eeb50 | 545 | env->priv_ver = PRIV_VERSION_1_11_0; |
6df3747a AG |
546 | #ifndef CONFIG_USER_ONLY |
547 | set_satp_mode_max_supported(cpu, VM_1_10_MBARE); | |
548 | #endif | |
26b2bc58 | 549 | cpu->cfg.epmp = true; |
7f0bdfb5 DHB |
550 | |
551 | /* inherited from parent obj via riscv_cpu_init() */ | |
552 | cpu->cfg.ext_ifencei = true; | |
553 | cpu->cfg.ext_icsr = true; | |
554 | cpu->cfg.pmp = true; | |
dc5bd18f MC |
555 | } |
556 | ||
2fdd2c09 | 557 | static void rv32_imafcu_nommu_cpu_init(Object *obj) |
d784733b CW |
558 | { |
559 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
26b2bc58 AF |
560 | RISCVCPU *cpu = RISCV_CPU(obj); |
561 | ||
e91a7227 | 562 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); |
8c6eeb50 | 563 | env->priv_ver = PRIV_VERSION_1_10_0; |
6df3747a AG |
564 | #ifndef CONFIG_USER_ONLY |
565 | set_satp_mode_max_supported(cpu, VM_1_10_MBARE); | |
566 | #endif | |
7f0bdfb5 DHB |
567 | |
568 | /* inherited from parent obj via riscv_cpu_init() */ | |
569 | cpu->cfg.ext_ifencei = true; | |
570 | cpu->cfg.ext_icsr = true; | |
571 | cpu->cfg.pmp = true; | |
d784733b | 572 | } |
eab15862 | 573 | #endif |
dc5bd18f | 574 | |
10f1ca27 YJ |
575 | #if defined(CONFIG_KVM) |
576 | static void riscv_host_cpu_init(Object *obj) | |
577 | { | |
578 | CPURISCVState *env = &RISCV_CPU(obj)->env; | |
579 | #if defined(TARGET_RISCV32) | |
580 | set_misa(env, MXL_RV32, 0); | |
581 | #elif defined(TARGET_RISCV64) | |
582 | set_misa(env, MXL_RV64, 0); | |
583 | #endif | |
dd8f244f | 584 | riscv_cpu_add_user_properties(obj); |
10f1ca27 YJ |
585 | } |
586 | #endif | |
587 | ||
dc5bd18f MC |
588 | static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) |
589 | { | |
590 | ObjectClass *oc; | |
591 | char *typename; | |
592 | char **cpuname; | |
593 | ||
594 | cpuname = g_strsplit(cpu_model, ",", 1); | |
595 | typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); | |
596 | oc = object_class_by_name(typename); | |
597 | g_strfreev(cpuname); | |
598 | g_free(typename); | |
599 | if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || | |
600 | object_class_is_abstract(oc)) { | |
601 | return NULL; | |
602 | } | |
603 | return oc; | |
604 | } | |
605 | ||
90c84c56 | 606 | static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) |
dc5bd18f MC |
607 | { |
608 | RISCVCPU *cpu = RISCV_CPU(cs); | |
609 | CPURISCVState *env = &cpu->env; | |
610 | int i; | |
611 | ||
df30e652 AF |
612 | #if !defined(CONFIG_USER_ONLY) |
613 | if (riscv_has_ext(env, RVH)) { | |
38256529 | 614 | qemu_fprintf(f, " %s %d\n", "V = ", env->virt_enabled); |
df30e652 AF |
615 | } |
616 | #endif | |
90c84c56 | 617 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); |
dc5bd18f | 618 | #ifndef CONFIG_USER_ONLY |
665b90d8 RH |
619 | { |
620 | static const int dump_csrs[] = { | |
621 | CSR_MHARTID, | |
622 | CSR_MSTATUS, | |
623 | CSR_MSTATUSH, | |
bc7dca13 BM |
624 | /* |
625 | * CSR_SSTATUS is intentionally omitted here as its value | |
626 | * can be figured out by looking at CSR_MSTATUS | |
627 | */ | |
665b90d8 RH |
628 | CSR_HSTATUS, |
629 | CSR_VSSTATUS, | |
630 | CSR_MIP, | |
631 | CSR_MIE, | |
632 | CSR_MIDELEG, | |
633 | CSR_HIDELEG, | |
634 | CSR_MEDELEG, | |
635 | CSR_HEDELEG, | |
636 | CSR_MTVEC, | |
637 | CSR_STVEC, | |
638 | CSR_VSTVEC, | |
639 | CSR_MEPC, | |
640 | CSR_SEPC, | |
641 | CSR_VSEPC, | |
642 | CSR_MCAUSE, | |
643 | CSR_SCAUSE, | |
644 | CSR_VSCAUSE, | |
645 | CSR_MTVAL, | |
646 | CSR_STVAL, | |
647 | CSR_HTVAL, | |
648 | CSR_MTVAL2, | |
649 | CSR_MSCRATCH, | |
650 | CSR_SSCRATCH, | |
651 | CSR_SATP, | |
bd5594ca AB |
652 | CSR_MMTE, |
653 | CSR_UPMBASE, | |
654 | CSR_UPMMASK, | |
655 | CSR_SPMBASE, | |
656 | CSR_SPMMASK, | |
657 | CSR_MPMBASE, | |
658 | CSR_MPMMASK, | |
665b90d8 RH |
659 | }; |
660 | ||
661 | for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { | |
662 | int csrno = dump_csrs[i]; | |
663 | target_ulong val = 0; | |
664 | RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); | |
665 | ||
666 | /* | |
667 | * Rely on the smode, hmode, etc, predicates within csr.c | |
668 | * to do the filtering of the registers that are present. | |
669 | */ | |
670 | if (res == RISCV_EXCP_NONE) { | |
671 | qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", | |
672 | csr_ops[csrno].name, val); | |
673 | } | |
674 | } | |
df30e652 | 675 | } |
dc5bd18f MC |
676 | #endif |
677 | ||
678 | for (i = 0; i < 32; i++) { | |
e573a7f3 | 679 | qemu_fprintf(f, " %-8s " TARGET_FMT_lx, |
90c84c56 | 680 | riscv_int_regnames[i], env->gpr[i]); |
dc5bd18f | 681 | if ((i & 3) == 3) { |
90c84c56 | 682 | qemu_fprintf(f, "\n"); |
dc5bd18f MC |
683 | } |
684 | } | |
86ea1880 RH |
685 | if (flags & CPU_DUMP_FPU) { |
686 | for (i = 0; i < 32; i++) { | |
e573a7f3 | 687 | qemu_fprintf(f, " %-8s %016" PRIx64, |
90c84c56 | 688 | riscv_fpr_regnames[i], env->fpr[i]); |
86ea1880 | 689 | if ((i & 3) == 3) { |
90c84c56 | 690 | qemu_fprintf(f, "\n"); |
86ea1880 | 691 | } |
dc5bd18f MC |
692 | } |
693 | } | |
694 | } | |
695 | ||
696 | static void riscv_cpu_set_pc(CPUState *cs, vaddr value) | |
697 | { | |
698 | RISCVCPU *cpu = RISCV_CPU(cs); | |
699 | CPURISCVState *env = &cpu->env; | |
bf9e776e LZ |
700 | |
701 | if (env->xl == MXL_RV32) { | |
702 | env->pc = (int32_t)value; | |
703 | } else { | |
704 | env->pc = value; | |
705 | } | |
dc5bd18f MC |
706 | } |
707 | ||
e4fdf9df RH |
708 | static vaddr riscv_cpu_get_pc(CPUState *cs) |
709 | { | |
710 | RISCVCPU *cpu = RISCV_CPU(cs); | |
711 | CPURISCVState *env = &cpu->env; | |
712 | ||
713 | /* Match cpu_get_tb_cpu_state. */ | |
714 | if (env->xl == MXL_RV32) { | |
715 | return env->pc & UINT32_MAX; | |
716 | } | |
717 | return env->pc; | |
718 | } | |
719 | ||
04a37d4c RH |
720 | static void riscv_cpu_synchronize_from_tb(CPUState *cs, |
721 | const TranslationBlock *tb) | |
dc5bd18f MC |
722 | { |
723 | RISCVCPU *cpu = RISCV_CPU(cs); | |
724 | CPURISCVState *env = &cpu->env; | |
bf9e776e LZ |
725 | RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); |
726 | ||
0489d5bd AJ |
727 | tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); |
728 | ||
bf9e776e | 729 | if (xl == MXL_RV32) { |
0489d5bd | 730 | env->pc = (int32_t) tb->pc; |
bf9e776e | 731 | } else { |
0489d5bd | 732 | env->pc = tb->pc; |
bf9e776e | 733 | } |
dc5bd18f MC |
734 | } |
735 | ||
736 | static bool riscv_cpu_has_work(CPUState *cs) | |
737 | { | |
738 | #ifndef CONFIG_USER_ONLY | |
739 | RISCVCPU *cpu = RISCV_CPU(cs); | |
740 | CPURISCVState *env = &cpu->env; | |
741 | /* | |
742 | * Definition of the WFI instruction requires it to ignore the privilege | |
743 | * mode and delegation registers, but respect individual enables | |
744 | */ | |
8f42415f | 745 | return riscv_cpu_all_pending(env) != 0; |
dc5bd18f MC |
746 | #else |
747 | return true; | |
748 | #endif | |
749 | } | |
750 | ||
ad1e84f5 RH |
751 | static void riscv_restore_state_to_opc(CPUState *cs, |
752 | const TranslationBlock *tb, | |
753 | const uint64_t *data) | |
dc5bd18f | 754 | { |
ad1e84f5 RH |
755 | RISCVCPU *cpu = RISCV_CPU(cs); |
756 | CPURISCVState *env = &cpu->env; | |
bf9e776e | 757 | RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); |
ad1e84f5 | 758 | |
bf9e776e LZ |
759 | if (xl == MXL_RV32) { |
760 | env->pc = (int32_t)data[0]; | |
761 | } else { | |
762 | env->pc = data[0]; | |
763 | } | |
62cf0245 | 764 | env->bins = data[1]; |
dc5bd18f MC |
765 | } |
766 | ||
4fa485a7 | 767 | static void riscv_cpu_reset_hold(Object *obj) |
dc5bd18f | 768 | { |
43dc93af AP |
769 | #ifndef CONFIG_USER_ONLY |
770 | uint8_t iprio; | |
771 | int i, irq, rdzero; | |
772 | #endif | |
4fa485a7 | 773 | CPUState *cs = CPU(obj); |
dc5bd18f MC |
774 | RISCVCPU *cpu = RISCV_CPU(cs); |
775 | RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); | |
776 | CPURISCVState *env = &cpu->env; | |
777 | ||
4fa485a7 PM |
778 | if (mcc->parent_phases.hold) { |
779 | mcc->parent_phases.hold(obj); | |
780 | } | |
dc5bd18f | 781 | #ifndef CONFIG_USER_ONLY |
e91a7227 | 782 | env->misa_mxl = env->misa_mxl_max; |
dc5bd18f MC |
783 | env->priv = PRV_M; |
784 | env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); | |
92371bd9 RH |
785 | if (env->misa_mxl > MXL_RV32) { |
786 | /* | |
787 | * The reset status of SXL/UXL is undefined, but mstatus is WARL | |
788 | * and we must ensure that the value after init is valid for read. | |
789 | */ | |
790 | env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); | |
791 | env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); | |
5a2ae235 LZ |
792 | if (riscv_has_ext(env, RVH)) { |
793 | env->vsstatus = set_field(env->vsstatus, | |
794 | MSTATUS64_SXL, env->misa_mxl); | |
795 | env->vsstatus = set_field(env->vsstatus, | |
796 | MSTATUS64_UXL, env->misa_mxl); | |
797 | env->mstatus_hs = set_field(env->mstatus_hs, | |
798 | MSTATUS64_SXL, env->misa_mxl); | |
799 | env->mstatus_hs = set_field(env->mstatus_hs, | |
800 | MSTATUS64_UXL, env->misa_mxl); | |
801 | } | |
92371bd9 | 802 | } |
dc5bd18f | 803 | env->mcause = 0; |
881df35d | 804 | env->miclaim = MIP_SGEIP; |
dc5bd18f | 805 | env->pc = env->resetvec; |
62cf0245 | 806 | env->bins = 0; |
ec352d0c | 807 | env->two_stage_lookup = false; |
43dc93af | 808 | |
0af3f115 WL |
809 | env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) | |
810 | (cpu->cfg.ext_svadu ? MENVCFG_HADE : 0); | |
811 | env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) | | |
812 | (cpu->cfg.ext_svadu ? HENVCFG_HADE : 0); | |
7a6613da | 813 | |
43dc93af AP |
814 | /* Initialized default priorities of local interrupts. */ |
815 | for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { | |
816 | iprio = riscv_cpu_default_priority(i); | |
817 | env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio; | |
818 | env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio; | |
819 | env->hviprio[i] = 0; | |
820 | } | |
821 | i = 0; | |
822 | while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) { | |
823 | if (!rdzero) { | |
824 | env->hviprio[irq] = env->miprio[irq]; | |
825 | } | |
826 | i++; | |
827 | } | |
4bbe8033 | 828 | /* mmte is supposed to have pm.current hardwired to 1 */ |
42967f40 | 829 | env->mmte |= (EXT_STATUS_INITIAL | MMTE_M_PM_CURRENT); |
dc5bd18f | 830 | #endif |
440544e1 | 831 | env->xl = riscv_cpu_mxl(env); |
40bfa5f6 | 832 | riscv_cpu_update_mask(env); |
330d2ae3 | 833 | cs->exception_index = RISCV_EXCP_NONE; |
c13b169f | 834 | env->load_res = -1; |
dc5bd18f | 835 | set_default_nan_mode(1, &env->fp_status); |
ad40be27 YJ |
836 | |
837 | #ifndef CONFIG_USER_ONLY | |
cdfb2905 | 838 | if (cpu->cfg.debug) { |
b6092544 BM |
839 | riscv_trigger_init(env); |
840 | } | |
841 | ||
ad40be27 YJ |
842 | if (kvm_enabled()) { |
843 | kvm_riscv_reset_vcpu(cpu); | |
844 | } | |
845 | #endif | |
dc5bd18f MC |
846 | } |
847 | ||
848 | static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) | |
849 | { | |
5c5a47f1 | 850 | RISCVCPU *cpu = RISCV_CPU(s); |
db23e5d9 RH |
851 | |
852 | switch (riscv_cpu_mxl(&cpu->env)) { | |
853 | case MXL_RV32: | |
5c5a47f1 | 854 | info->print_insn = print_insn_riscv32; |
db23e5d9 RH |
855 | break; |
856 | case MXL_RV64: | |
5c5a47f1 | 857 | info->print_insn = print_insn_riscv64; |
db23e5d9 | 858 | break; |
332dab68 FP |
859 | case MXL_RV128: |
860 | info->print_insn = print_insn_riscv128; | |
861 | break; | |
db23e5d9 RH |
862 | default: |
863 | g_assert_not_reached(); | |
5c5a47f1 | 864 | } |
dc5bd18f MC |
865 | } |
866 | ||
d63be184 DHB |
867 | static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, |
868 | Error **errp) | |
869 | { | |
870 | int vext_version = VEXT_VERSION_1_00_0; | |
871 | ||
872 | if (!is_power_of_2(cfg->vlen)) { | |
873 | error_setg(errp, "Vector extension VLEN must be power of 2"); | |
874 | return; | |
875 | } | |
876 | if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) { | |
877 | error_setg(errp, | |
878 | "Vector extension implementation only supports VLEN " | |
879 | "in the range [128, %d]", RV_VLEN_MAX); | |
880 | return; | |
881 | } | |
882 | if (!is_power_of_2(cfg->elen)) { | |
883 | error_setg(errp, "Vector extension ELEN must be power of 2"); | |
884 | return; | |
885 | } | |
886 | if (cfg->elen > 64 || cfg->elen < 8) { | |
887 | error_setg(errp, | |
888 | "Vector extension implementation only supports ELEN " | |
889 | "in the range [8, 64]"); | |
890 | return; | |
891 | } | |
892 | if (cfg->vext_spec) { | |
893 | if (!g_strcmp0(cfg->vext_spec, "v1.0")) { | |
894 | vext_version = VEXT_VERSION_1_00_0; | |
895 | } else { | |
896 | error_setg(errp, "Unsupported vector spec version '%s'", | |
897 | cfg->vext_spec); | |
898 | return; | |
899 | } | |
900 | } else { | |
901 | qemu_log("vector version is not specified, " | |
902 | "use the default value v1.0\n"); | |
903 | } | |
2238c9d1 | 904 | env->vext_ver = vext_version; |
d63be184 DHB |
905 | } |
906 | ||
bd305595 DHB |
907 | static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp) |
908 | { | |
909 | CPURISCVState *env = &cpu->env; | |
910 | int priv_version = -1; | |
911 | ||
912 | if (cpu->cfg.priv_spec) { | |
913 | if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { | |
914 | priv_version = PRIV_VERSION_1_12_0; | |
915 | } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { | |
916 | priv_version = PRIV_VERSION_1_11_0; | |
917 | } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { | |
918 | priv_version = PRIV_VERSION_1_10_0; | |
919 | } else { | |
920 | error_setg(errp, | |
921 | "Unsupported privilege spec version '%s'", | |
922 | cpu->cfg.priv_spec); | |
923 | return; | |
924 | } | |
925 | ||
926 | env->priv_ver = priv_version; | |
927 | } | |
928 | } | |
929 | ||
930 | static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) | |
931 | { | |
932 | CPURISCVState *env = &cpu->env; | |
933 | int i; | |
934 | ||
935 | /* Force disable extensions if priv spec version does not match */ | |
936 | for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { | |
937 | if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && | |
938 | (env->priv_ver < isa_edata_arr[i].min_version)) { | |
939 | isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); | |
940 | #ifndef CONFIG_USER_ONLY | |
941 | warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx | |
942 | " because privilege spec version does not match", | |
943 | isa_edata_arr[i].name, env->mhartid); | |
944 | #else | |
945 | warn_report("disabling %s extension because " | |
946 | "privilege spec version does not match", | |
947 | isa_edata_arr[i].name); | |
948 | #endif | |
949 | } | |
950 | } | |
951 | } | |
952 | ||
f5664064 DHB |
953 | static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) |
954 | { | |
955 | RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); | |
956 | CPUClass *cc = CPU_CLASS(mcc); | |
957 | CPURISCVState *env = &cpu->env; | |
958 | ||
959 | /* Validate that MISA_MXL is set properly. */ | |
960 | switch (env->misa_mxl_max) { | |
961 | #ifdef TARGET_RISCV64 | |
962 | case MXL_RV64: | |
963 | case MXL_RV128: | |
964 | cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; | |
965 | break; | |
966 | #endif | |
967 | case MXL_RV32: | |
968 | cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; | |
969 | break; | |
970 | default: | |
971 | g_assert_not_reached(); | |
972 | } | |
973 | ||
974 | if (env->misa_mxl_max != env->misa_mxl) { | |
975 | error_setg(errp, "misa_mxl_max must be equal to misa_mxl"); | |
976 | return; | |
977 | } | |
978 | } | |
979 | ||
5ab10952 DHB |
980 | /* |
981 | * Check consistency between chosen extensions while setting | |
1ffa805c | 982 | * cpu->cfg accordingly. |
5ab10952 | 983 | */ |
faf3b5d8 | 984 | void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) |
5ab10952 DHB |
985 | { |
986 | CPURISCVState *env = &cpu->env; | |
d63be184 | 987 | Error *local_err = NULL; |
5ab10952 DHB |
988 | |
989 | /* Do some ISA extension error checking */ | |
4f13abcb DHB |
990 | if (riscv_has_ext(env, RVG) && |
991 | !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) && | |
992 | riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) && | |
993 | riscv_has_ext(env, RVD) && | |
994 | cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { | |
5ab10952 | 995 | warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); |
5ab10952 DHB |
996 | cpu->cfg.ext_icsr = true; |
997 | cpu->cfg.ext_ifencei = true; | |
1ffa805c DHB |
998 | |
999 | env->misa_ext |= RVI | RVM | RVA | RVF | RVD; | |
faf3b5d8 | 1000 | env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD; |
5ab10952 DHB |
1001 | } |
1002 | ||
427d8e7d | 1003 | if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { |
5ab10952 DHB |
1004 | error_setg(errp, |
1005 | "I and E extensions are incompatible"); | |
1006 | return; | |
1007 | } | |
1008 | ||
427d8e7d | 1009 | if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { |
5ab10952 DHB |
1010 | error_setg(errp, |
1011 | "Either I or E extension must be set"); | |
1012 | return; | |
1013 | } | |
1014 | ||
e17801e1 | 1015 | if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) { |
5ab10952 DHB |
1016 | error_setg(errp, |
1017 | "Setting S extension without U extension is illegal"); | |
1018 | return; | |
1019 | } | |
1020 | ||
b5c042e8 | 1021 | if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { |
5ab10952 DHB |
1022 | error_setg(errp, |
1023 | "H depends on an I base integer ISA with 32 x registers"); | |
1024 | return; | |
1025 | } | |
1026 | ||
b5c042e8 | 1027 | if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { |
5ab10952 DHB |
1028 | error_setg(errp, "H extension implicitly requires S-mode"); |
1029 | return; | |
1030 | } | |
1031 | ||
4b33598f | 1032 | if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) { |
5ab10952 DHB |
1033 | error_setg(errp, "F extension requires Zicsr"); |
1034 | return; | |
1035 | } | |
1036 | ||
4c759943 | 1037 | if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { |
5ab10952 DHB |
1038 | error_setg(errp, "Zawrs extension requires A extension"); |
1039 | return; | |
1040 | } | |
1041 | ||
1d2cb5a8 WL |
1042 | if (cpu->cfg.ext_zfh) { |
1043 | cpu->cfg.ext_zfhmin = true; | |
1044 | } | |
1045 | ||
4b33598f | 1046 | if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { |
5ab10952 DHB |
1047 | error_setg(errp, "Zfh/Zfhmin extensions require F extension"); |
1048 | return; | |
1049 | } | |
1050 | ||
4b33598f | 1051 | if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { |
5ab10952 DHB |
1052 | error_setg(errp, "D extension requires F extension"); |
1053 | return; | |
1054 | } | |
1055 | ||
3e7674fd | 1056 | if (riscv_has_ext(env, RVV)) { |
d63be184 DHB |
1057 | riscv_cpu_validate_v(env, &cpu->cfg, &local_err); |
1058 | if (local_err != NULL) { | |
1059 | error_propagate(errp, local_err); | |
1060 | return; | |
1061 | } | |
1062 | ||
1063 | /* The V vector extension depends on the Zve64d extension */ | |
e7f0a803 WL |
1064 | cpu->cfg.ext_zve64d = true; |
1065 | } | |
1066 | ||
1067 | /* The Zve64d extension depends on the Zve64f extension */ | |
1068 | if (cpu->cfg.ext_zve64d) { | |
1069 | cpu->cfg.ext_zve64f = true; | |
1070 | } | |
1071 | ||
1072 | /* The Zve64f extension depends on the Zve32f extension */ | |
1073 | if (cpu->cfg.ext_zve64f) { | |
1074 | cpu->cfg.ext_zve32f = true; | |
1075 | } | |
1076 | ||
ffffd954 | 1077 | if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) { |
e7f0a803 | 1078 | error_setg(errp, "Zve64d/V extensions require D extension"); |
5ab10952 DHB |
1079 | return; |
1080 | } | |
1081 | ||
4b33598f | 1082 | if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) { |
5ab10952 DHB |
1083 | error_setg(errp, "Zve32f/Zve64f extensions require F extension"); |
1084 | return; | |
1085 | } | |
1086 | ||
2e60f9ec WL |
1087 | if (cpu->cfg.ext_zvfh) { |
1088 | cpu->cfg.ext_zvfhmin = true; | |
1089 | } | |
1090 | ||
1091 | if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { | |
1092 | error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension"); | |
1093 | return; | |
1094 | } | |
1095 | ||
1096 | if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { | |
1097 | error_setg(errp, "Zvfh extensions requires Zfhmin extension"); | |
1098 | return; | |
1099 | } | |
1100 | ||
5ab10952 | 1101 | /* Set the ISA extensions, checks should have happened above */ |
a0d805f0 WL |
1102 | if (cpu->cfg.ext_zhinx) { |
1103 | cpu->cfg.ext_zhinxmin = true; | |
1104 | } | |
1105 | ||
9ba63f94 WL |
1106 | if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) { |
1107 | error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx"); | |
1108 | return; | |
5ab10952 DHB |
1109 | } |
1110 | ||
1111 | if (cpu->cfg.ext_zfinx) { | |
1112 | if (!cpu->cfg.ext_icsr) { | |
1113 | error_setg(errp, "Zfinx extension requires Zicsr"); | |
1114 | return; | |
1115 | } | |
4b33598f | 1116 | if (riscv_has_ext(env, RVF)) { |
5ab10952 | 1117 | error_setg(errp, |
51f33081 | 1118 | "Zfinx cannot be supported together with F extension"); |
5ab10952 DHB |
1119 | return; |
1120 | } | |
1121 | } | |
1122 | ||
00d312bd WL |
1123 | if (cpu->cfg.ext_zce) { |
1124 | cpu->cfg.ext_zca = true; | |
1125 | cpu->cfg.ext_zcb = true; | |
1126 | cpu->cfg.ext_zcmp = true; | |
1127 | cpu->cfg.ext_zcmt = true; | |
4b33598f | 1128 | if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) { |
00d312bd WL |
1129 | cpu->cfg.ext_zcf = true; |
1130 | } | |
1131 | } | |
1132 | ||
c00226e1 | 1133 | if (riscv_has_ext(env, RVC)) { |
2288a5ce | 1134 | cpu->cfg.ext_zca = true; |
4b33598f | 1135 | if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) { |
2288a5ce WL |
1136 | cpu->cfg.ext_zcf = true; |
1137 | } | |
ffffd954 | 1138 | if (riscv_has_ext(env, RVD)) { |
2288a5ce WL |
1139 | cpu->cfg.ext_zcd = true; |
1140 | } | |
1141 | } | |
1142 | ||
1143 | if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { | |
1144 | error_setg(errp, "Zcf extension is only relevant to RV32"); | |
1145 | return; | |
1146 | } | |
1147 | ||
4b33598f | 1148 | if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { |
2288a5ce WL |
1149 | error_setg(errp, "Zcf extension requires F extension"); |
1150 | return; | |
1151 | } | |
1152 | ||
ffffd954 | 1153 | if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { |
2288a5ce WL |
1154 | error_setg(errp, "Zcd extension requires D extension"); |
1155 | return; | |
1156 | } | |
1157 | ||
1158 | if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || | |
1159 | cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { | |
1160 | error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " | |
1161 | "extension"); | |
1162 | return; | |
1163 | } | |
1164 | ||
1165 | if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { | |
1166 | error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " | |
1167 | "Zcd extension"); | |
1168 | return; | |
1169 | } | |
1170 | ||
1171 | if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) { | |
1172 | error_setg(errp, "Zcmt extension requires Zicsr extension"); | |
1173 | return; | |
1174 | } | |
1175 | ||
5ab10952 DHB |
1176 | if (cpu->cfg.ext_zk) { |
1177 | cpu->cfg.ext_zkn = true; | |
1178 | cpu->cfg.ext_zkr = true; | |
1179 | cpu->cfg.ext_zkt = true; | |
1180 | } | |
1181 | ||
1182 | if (cpu->cfg.ext_zkn) { | |
1183 | cpu->cfg.ext_zbkb = true; | |
1184 | cpu->cfg.ext_zbkc = true; | |
1185 | cpu->cfg.ext_zbkx = true; | |
1186 | cpu->cfg.ext_zkne = true; | |
1187 | cpu->cfg.ext_zknd = true; | |
1188 | cpu->cfg.ext_zknh = true; | |
1189 | } | |
1190 | ||
1191 | if (cpu->cfg.ext_zks) { | |
1192 | cpu->cfg.ext_zbkb = true; | |
1193 | cpu->cfg.ext_zbkc = true; | |
1194 | cpu->cfg.ext_zbkx = true; | |
1195 | cpu->cfg.ext_zksed = true; | |
1196 | cpu->cfg.ext_zksh = true; | |
1197 | } | |
bd305595 DHB |
1198 | |
1199 | /* | |
1200 | * Disable isa extensions based on priv spec after we | |
1201 | * validated and set everything we need. | |
1202 | */ | |
1203 | riscv_cpu_disable_priv_spec_isa_exts(cpu); | |
5ab10952 DHB |
1204 | } |
1205 | ||
6f23aaeb AG |
1206 | #ifndef CONFIG_USER_ONLY |
1207 | static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) | |
1208 | { | |
1209 | bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; | |
6df3747a AG |
1210 | uint8_t satp_mode_map_max; |
1211 | uint8_t satp_mode_supported_max = | |
1212 | satp_mode_max_from_map(cpu->cfg.satp_mode.supported); | |
6f23aaeb AG |
1213 | |
1214 | if (cpu->cfg.satp_mode.map == 0) { | |
1215 | if (cpu->cfg.satp_mode.init == 0) { | |
1216 | /* If unset by the user, we fallback to the default satp mode. */ | |
1217 | set_satp_mode_default_map(cpu); | |
1218 | } else { | |
1219 | /* | |
1220 | * Find the lowest level that was disabled and then enable the | |
1221 | * first valid level below which can be found in | |
1222 | * valid_vm_1_10_32/64. | |
1223 | */ | |
1224 | for (int i = 1; i < 16; ++i) { | |
6df3747a AG |
1225 | if ((cpu->cfg.satp_mode.init & (1 << i)) && |
1226 | (cpu->cfg.satp_mode.supported & (1 << i))) { | |
6f23aaeb | 1227 | for (int j = i - 1; j >= 0; --j) { |
6df3747a | 1228 | if (cpu->cfg.satp_mode.supported & (1 << j)) { |
6f23aaeb AG |
1229 | cpu->cfg.satp_mode.map |= (1 << j); |
1230 | break; | |
1231 | } | |
1232 | } | |
1233 | break; | |
1234 | } | |
1235 | } | |
1236 | } | |
1237 | } | |
1238 | ||
6df3747a AG |
1239 | satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); |
1240 | ||
1241 | /* Make sure the user asked for a supported configuration (HW and qemu) */ | |
1242 | if (satp_mode_map_max > satp_mode_supported_max) { | |
1243 | error_setg(errp, "satp_mode %s is higher than hw max capability %s", | |
1244 | satp_mode_str(satp_mode_map_max, rv32), | |
1245 | satp_mode_str(satp_mode_supported_max, rv32)); | |
1246 | return; | |
6f23aaeb AG |
1247 | } |
1248 | ||
1249 | /* | |
1250 | * Make sure the user did not ask for an invalid configuration as per | |
1251 | * the specification. | |
1252 | */ | |
6f23aaeb | 1253 | if (!rv32) { |
6df3747a | 1254 | for (int i = satp_mode_map_max - 1; i >= 0; --i) { |
6f23aaeb AG |
1255 | if (!(cpu->cfg.satp_mode.map & (1 << i)) && |
1256 | (cpu->cfg.satp_mode.init & (1 << i)) && | |
6df3747a | 1257 | (cpu->cfg.satp_mode.supported & (1 << i))) { |
6f23aaeb AG |
1258 | error_setg(errp, "cannot disable %s satp mode if %s " |
1259 | "is enabled", satp_mode_str(i, false), | |
6df3747a | 1260 | satp_mode_str(satp_mode_map_max, false)); |
6f23aaeb AG |
1261 | return; |
1262 | } | |
1263 | } | |
1264 | } | |
1265 | ||
1266 | /* Finally expand the map so that all valid modes are set */ | |
6df3747a AG |
1267 | for (int i = satp_mode_map_max - 1; i >= 0; --i) { |
1268 | if (cpu->cfg.satp_mode.supported & (1 << i)) { | |
6f23aaeb AG |
1269 | cpu->cfg.satp_mode.map |= (1 << i); |
1270 | } | |
1271 | } | |
1272 | } | |
1273 | #endif | |
1274 | ||
1275 | static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) | |
1276 | { | |
1277 | #ifndef CONFIG_USER_ONLY | |
1278 | Error *local_err = NULL; | |
1279 | ||
1280 | riscv_cpu_satp_mode_finalize(cpu, &local_err); | |
1281 | if (local_err != NULL) { | |
1282 | error_propagate(errp, local_err); | |
1283 | return; | |
1284 | } | |
1285 | #endif | |
1286 | } | |
1287 | ||
6508272a DHB |
1288 | static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) |
1289 | { | |
1290 | if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { | |
1291 | error_setg(errp, "H extension requires priv spec 1.12.0"); | |
1292 | return; | |
1293 | } | |
1294 | } | |
1295 | ||
dc5bd18f MC |
1296 | static void riscv_cpu_realize(DeviceState *dev, Error **errp) |
1297 | { | |
1298 | CPUState *cs = CPU(dev); | |
c4e95030 AF |
1299 | RISCVCPU *cpu = RISCV_CPU(dev); |
1300 | CPURISCVState *env = &cpu->env; | |
dc5bd18f MC |
1301 | RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); |
1302 | Error *local_err = NULL; | |
1303 | ||
1304 | cpu_exec_realizefn(cs, &local_err); | |
1305 | if (local_err != NULL) { | |
1306 | error_propagate(errp, local_err); | |
1307 | return; | |
1308 | } | |
1309 | ||
f5664064 DHB |
1310 | riscv_cpu_validate_misa_mxl(cpu, &local_err); |
1311 | if (local_err != NULL) { | |
1312 | error_propagate(errp, local_err); | |
1313 | return; | |
1314 | } | |
1315 | ||
bd305595 DHB |
1316 | riscv_cpu_validate_priv_spec(cpu, &local_err); |
1317 | if (local_err != NULL) { | |
1318 | error_propagate(errp, local_err); | |
1319 | return; | |
a8b37120 | 1320 | } |
c4e95030 | 1321 | |
6508272a DHB |
1322 | riscv_cpu_validate_misa_priv(env, &local_err); |
1323 | if (local_err != NULL) { | |
1324 | error_propagate(errp, local_err); | |
1325 | return; | |
1326 | } | |
1327 | ||
6a3ffda2 | 1328 | if (cpu->cfg.epmp && !cpu->cfg.pmp) { |
5da9514e HW |
1329 | /* |
1330 | * Enhanced PMP should only be available | |
1331 | * on harts with PMP support | |
1332 | */ | |
6a3ffda2 DHB |
1333 | error_setg(errp, "Invalid configuration: EPMP requires PMP support"); |
1334 | return; | |
1acdb3b0 BM |
1335 | } |
1336 | ||
5ab10952 DHB |
1337 | riscv_cpu_validate_set_extensions(cpu, &local_err); |
1338 | if (local_err != NULL) { | |
1339 | error_propagate(errp, local_err); | |
1340 | return; | |
b55d7d34 AF |
1341 | } |
1342 | ||
14664483 | 1343 | #ifndef CONFIG_USER_ONLY |
e2fa85f4 DHB |
1344 | if (cpu->cfg.ext_sstc) { |
1345 | riscv_timer_init(cpu); | |
1346 | } | |
1347 | ||
14664483 AP |
1348 | if (cpu->cfg.pmu_num) { |
1349 | if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { | |
1350 | cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, | |
1351 | riscv_pmu_timer_cb, cpu); | |
1352 | } | |
1353 | } | |
1354 | #endif | |
1355 | ||
6f23aaeb AG |
1356 | riscv_cpu_finalize_features(cpu, &local_err); |
1357 | if (local_err != NULL) { | |
1358 | error_propagate(errp, local_err); | |
1359 | return; | |
1360 | } | |
1361 | ||
5371f5cd JW |
1362 | riscv_cpu_register_gdb_regs_for_features(cs); |
1363 | ||
dc5bd18f MC |
1364 | qemu_init_vcpu(cs); |
1365 | cpu_reset(cs); | |
1366 | ||
1367 | mcc->parent_realize(dev, errp); | |
1368 | } | |
1369 | ||
0f0b70ee | 1370 | #ifndef CONFIG_USER_ONLY |
6f23aaeb AG |
1371 | static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, |
1372 | void *opaque, Error **errp) | |
1373 | { | |
1374 | RISCVSATPMap *satp_map = opaque; | |
1375 | uint8_t satp = satp_mode_from_str(name); | |
1376 | bool value; | |
1377 | ||
1378 | value = satp_map->map & (1 << satp); | |
1379 | ||
1380 | visit_type_bool(v, name, &value, errp); | |
1381 | } | |
1382 | ||
1383 | static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, | |
1384 | void *opaque, Error **errp) | |
1385 | { | |
1386 | RISCVSATPMap *satp_map = opaque; | |
1387 | uint8_t satp = satp_mode_from_str(name); | |
1388 | bool value; | |
1389 | ||
1390 | if (!visit_type_bool(v, name, &value, errp)) { | |
1391 | return; | |
1392 | } | |
1393 | ||
1394 | satp_map->map = deposit32(satp_map->map, satp, 1, value); | |
1395 | satp_map->init |= 1 << satp; | |
1396 | } | |
1397 | ||
1398 | static void riscv_add_satp_mode_properties(Object *obj) | |
1399 | { | |
1400 | RISCVCPU *cpu = RISCV_CPU(obj); | |
1401 | ||
1402 | if (cpu->env.misa_mxl == MXL_RV32) { | |
1403 | object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, | |
1404 | cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); | |
1405 | } else { | |
1406 | object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, | |
1407 | cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); | |
1408 | object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, | |
1409 | cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); | |
1410 | object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, | |
1411 | cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); | |
1412 | object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, | |
1413 | cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); | |
1414 | } | |
1415 | } | |
1416 | ||
0f0b70ee AF |
1417 | static void riscv_cpu_set_irq(void *opaque, int irq, int level) |
1418 | { | |
1419 | RISCVCPU *cpu = RISCV_CPU(opaque); | |
cd032fe7 | 1420 | CPURISCVState *env = &cpu->env; |
0f0b70ee | 1421 | |
cd032fe7 AP |
1422 | if (irq < IRQ_LOCAL_MAX) { |
1423 | switch (irq) { | |
1424 | case IRQ_U_SOFT: | |
1425 | case IRQ_S_SOFT: | |
1426 | case IRQ_VS_SOFT: | |
1427 | case IRQ_M_SOFT: | |
1428 | case IRQ_U_TIMER: | |
1429 | case IRQ_S_TIMER: | |
1430 | case IRQ_VS_TIMER: | |
1431 | case IRQ_M_TIMER: | |
1432 | case IRQ_U_EXT: | |
cd032fe7 AP |
1433 | case IRQ_VS_EXT: |
1434 | case IRQ_M_EXT: | |
8b5c807b | 1435 | if (kvm_enabled()) { |
cd032fe7 | 1436 | kvm_riscv_set_irq(cpu, irq, level); |
8b5c807b | 1437 | } else { |
bbb9fc25 | 1438 | riscv_cpu_update_mip(env, 1 << irq, BOOL_TO_MASK(level)); |
8b5c807b | 1439 | } |
cd032fe7 | 1440 | break; |
33fe584f AF |
1441 | case IRQ_S_EXT: |
1442 | if (kvm_enabled()) { | |
1443 | kvm_riscv_set_irq(cpu, irq, level); | |
1444 | } else { | |
1445 | env->external_seip = level; | |
bbb9fc25 | 1446 | riscv_cpu_update_mip(env, 1 << irq, |
33fe584f AF |
1447 | BOOL_TO_MASK(level | env->software_seip)); |
1448 | } | |
1449 | break; | |
cd032fe7 AP |
1450 | default: |
1451 | g_assert_not_reached(); | |
2b650fbb | 1452 | } |
cd032fe7 AP |
1453 | } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { |
1454 | /* Require H-extension for handling guest local interrupts */ | |
1455 | if (!riscv_has_ext(env, RVH)) { | |
1456 | g_assert_not_reached(); | |
1457 | } | |
1458 | ||
1459 | /* Compute bit position in HGEIP CSR */ | |
1460 | irq = irq - IRQ_LOCAL_MAX + 1; | |
1461 | if (env->geilen < irq) { | |
1462 | g_assert_not_reached(); | |
1463 | } | |
1464 | ||
1465 | /* Update HGEIP CSR */ | |
1466 | env->hgeip &= ~((target_ulong)1 << irq); | |
1467 | if (level) { | |
1468 | env->hgeip |= (target_ulong)1 << irq; | |
1469 | } | |
1470 | ||
1471 | /* Update mip.SGEIP bit */ | |
bbb9fc25 | 1472 | riscv_cpu_update_mip(env, MIP_SGEIP, |
cd032fe7 AP |
1473 | BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); |
1474 | } else { | |
0f0b70ee AF |
1475 | g_assert_not_reached(); |
1476 | } | |
1477 | } | |
1478 | #endif /* CONFIG_USER_ONLY */ | |
1479 | ||
dc5bd18f MC |
1480 | static void riscv_cpu_init(Object *obj) |
1481 | { | |
dc5bd18f MC |
1482 | RISCVCPU *cpu = RISCV_CPU(obj); |
1483 | ||
7506ed90 | 1484 | cpu_set_cpustate_pointers(cpu); |
0f0b70ee AF |
1485 | |
1486 | #ifndef CONFIG_USER_ONLY | |
cd032fe7 AP |
1487 | qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, |
1488 | IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); | |
0f0b70ee | 1489 | #endif /* CONFIG_USER_ONLY */ |
dc5bd18f MC |
1490 | } |
1491 | ||
b3df64c8 DHB |
1492 | typedef struct RISCVCPUMisaExtConfig { |
1493 | const char *name; | |
1494 | const char *description; | |
1495 | target_ulong misa_bit; | |
1496 | bool enabled; | |
1497 | } RISCVCPUMisaExtConfig; | |
1498 | ||
1499 | static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, | |
1500 | void *opaque, Error **errp) | |
1501 | { | |
1502 | const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; | |
1503 | target_ulong misa_bit = misa_ext_cfg->misa_bit; | |
1504 | RISCVCPU *cpu = RISCV_CPU(obj); | |
1505 | CPURISCVState *env = &cpu->env; | |
1506 | bool value; | |
1507 | ||
1508 | if (!visit_type_bool(v, name, &value, errp)) { | |
1509 | return; | |
1510 | } | |
1511 | ||
1512 | if (value) { | |
1513 | env->misa_ext |= misa_bit; | |
1514 | env->misa_ext_mask |= misa_bit; | |
1515 | } else { | |
1516 | env->misa_ext &= ~misa_bit; | |
1517 | env->misa_ext_mask &= ~misa_bit; | |
1518 | } | |
1519 | } | |
1520 | ||
1521 | static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, | |
1522 | void *opaque, Error **errp) | |
1523 | { | |
1524 | const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; | |
1525 | target_ulong misa_bit = misa_ext_cfg->misa_bit; | |
1526 | RISCVCPU *cpu = RISCV_CPU(obj); | |
1527 | CPURISCVState *env = &cpu->env; | |
1528 | bool value; | |
1529 | ||
1530 | value = env->misa_ext & misa_bit; | |
1531 | ||
1532 | visit_type_bool(v, name, &value, errp); | |
1533 | } | |
1534 | ||
4c759943 DHB |
1535 | static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { |
1536 | {.name = "a", .description = "Atomic instructions", | |
1537 | .misa_bit = RVA, .enabled = true}, | |
c00226e1 DHB |
1538 | {.name = "c", .description = "Compressed instructions", |
1539 | .misa_bit = RVC, .enabled = true}, | |
ffffd954 DHB |
1540 | {.name = "d", .description = "Double-precision float point", |
1541 | .misa_bit = RVD, .enabled = true}, | |
4b33598f DHB |
1542 | {.name = "f", .description = "Single-precision float point", |
1543 | .misa_bit = RVF, .enabled = true}, | |
74828eab DHB |
1544 | {.name = "i", .description = "Base integer instruction set", |
1545 | .misa_bit = RVI, .enabled = true}, | |
427d8e7d DHB |
1546 | {.name = "e", .description = "Base integer instruction set (embedded)", |
1547 | .misa_bit = RVE, .enabled = false}, | |
1a36e23a DHB |
1548 | {.name = "m", .description = "Integer multiplication and division", |
1549 | .misa_bit = RVM, .enabled = true}, | |
f1ea2a52 DHB |
1550 | {.name = "s", .description = "Supervisor-level instructions", |
1551 | .misa_bit = RVS, .enabled = true}, | |
e17801e1 DHB |
1552 | {.name = "u", .description = "User-level instructions", |
1553 | .misa_bit = RVU, .enabled = true}, | |
b5c042e8 DHB |
1554 | {.name = "h", .description = "Hypervisor", |
1555 | .misa_bit = RVH, .enabled = true}, | |
64f4b541 DHB |
1556 | {.name = "x-j", .description = "Dynamic translated languages", |
1557 | .misa_bit = RVJ, .enabled = false}, | |
3e7674fd DHB |
1558 | {.name = "v", .description = "Vector operations", |
1559 | .misa_bit = RVV, .enabled = false}, | |
4f13abcb DHB |
1560 | {.name = "g", .description = "General purpose (IMAFD_Zicsr_Zifencei)", |
1561 | .misa_bit = RVG, .enabled = false}, | |
4c759943 | 1562 | }; |
b3df64c8 DHB |
1563 | |
1564 | static void riscv_cpu_add_misa_properties(Object *cpu_obj) | |
1565 | { | |
1566 | int i; | |
1567 | ||
1568 | for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { | |
1569 | const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; | |
1570 | ||
1571 | object_property_add(cpu_obj, misa_cfg->name, "bool", | |
1572 | cpu_get_misa_ext_cfg, | |
1573 | cpu_set_misa_ext_cfg, | |
1574 | NULL, (void *)misa_cfg); | |
1575 | object_property_set_description(cpu_obj, misa_cfg->name, | |
1576 | misa_cfg->description); | |
1577 | object_property_set_bool(cpu_obj, misa_cfg->name, | |
1578 | misa_cfg->enabled, NULL); | |
1579 | } | |
1580 | } | |
1581 | ||
26b2bc58 | 1582 | static Property riscv_cpu_extensions[] = { |
9d3d60b7 | 1583 | /* Defaults for standard extensions */ |
18d6d89e | 1584 | DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), |
14664483 | 1585 | DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), |
9d3d60b7 AF |
1586 | DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), |
1587 | DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), | |
4696f0ab | 1588 | DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), |
260b594d | 1589 | DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), |
13fb8c7b | 1590 | DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), |
e5237730 | 1591 | DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), |
2fc1b44d | 1592 | DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), |
bfefe406 | 1593 | DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), |
058d9d30 | 1594 | DEFINE_PROP_BOOL("Zve64d", RISCVCPU, cfg.ext_zve64d, false), |
9d3d60b7 AF |
1595 | DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), |
1596 | DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), | |
43888c2f | 1597 | DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true), |
9d3d60b7 AF |
1598 | |
1599 | DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), | |
9ec6622d FC |
1600 | DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), |
1601 | DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), | |
1602 | DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), | |
9d3d60b7 | 1603 | |
62108f05 WL |
1604 | DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true), |
1605 | ||
c5d77ddd | 1606 | DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), |
2bacb224 | 1607 | DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), |
bbce8ba8 | 1608 | DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), |
2bacb224 | 1609 | |
0643c12e VG |
1610 | DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), |
1611 | DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), | |
1612 | DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), | |
cf7ed971 WL |
1613 | DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false), |
1614 | DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false), | |
1615 | DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false), | |
0643c12e | 1616 | DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), |
cf7ed971 WL |
1617 | DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false), |
1618 | DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false), | |
1619 | DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false), | |
1620 | DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false), | |
1621 | DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false), | |
1622 | DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false), | |
1623 | DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false), | |
1624 | DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false), | |
1625 | DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), | |
1626 | DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), | |
dfdb46a3 | 1627 | |
6b1accef WL |
1628 | DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), |
1629 | DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), | |
1630 | DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), | |
1631 | DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), | |
1632 | ||
e05da09b CM |
1633 | DEFINE_PROP_BOOL("zicbom", RISCVCPU, cfg.ext_icbom, true), |
1634 | DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64), | |
a939c500 CM |
1635 | DEFINE_PROP_BOOL("zicboz", RISCVCPU, cfg.ext_icboz, true), |
1636 | DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), | |
1637 | ||
6d00ffad WL |
1638 | DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), |
1639 | ||
6672e29d WL |
1640 | DEFINE_PROP_BOOL("zca", RISCVCPU, cfg.ext_zca, false), |
1641 | DEFINE_PROP_BOOL("zcb", RISCVCPU, cfg.ext_zcb, false), | |
1642 | DEFINE_PROP_BOOL("zcd", RISCVCPU, cfg.ext_zcd, false), | |
1643 | DEFINE_PROP_BOOL("zce", RISCVCPU, cfg.ext_zce, false), | |
1644 | DEFINE_PROP_BOOL("zcf", RISCVCPU, cfg.ext_zcf, false), | |
1645 | DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false), | |
1646 | DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false), | |
1647 | ||
0d429bd2 | 1648 | /* Vendor-specific custom extensions */ |
c9410a68 | 1649 | DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), |
426c0491 | 1650 | DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), |
fa134585 | 1651 | DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), |
49a7f3aa | 1652 | DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), |
32909338 | 1653 | DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), |
d4d90115 | 1654 | DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false), |
578086ba | 1655 | DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false), |
b8a5832b | 1656 | DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), |
45f9df86 | 1657 | DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false), |
af99aa72 | 1658 | DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false), |
134c3ffa | 1659 | DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), |
0d429bd2 PT |
1660 | DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), |
1661 | ||
dfdb46a3 | 1662 | /* These are experimental so mark with 'x-' */ |
b8e1f32c | 1663 | DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), |
d364c0ab | 1664 | |
a44da25a | 1665 | /* ePMP 0.9.3 */ |
5da9514e | 1666 | DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), |
dc9acc9c AP |
1667 | DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), |
1668 | DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), | |
5da9514e | 1669 | |
058d9d30 WL |
1670 | DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false), |
1671 | DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false), | |
1672 | ||
26b2bc58 AF |
1673 | DEFINE_PROP_END_OF_LIST(), |
1674 | }; | |
1675 | ||
c66ffcd5 | 1676 | /* |
dd8f244f DHB |
1677 | * Add CPU properties with user-facing flags. |
1678 | * | |
1679 | * This will overwrite existing env->misa_ext values with the | |
1680 | * defaults set via riscv_cpu_add_misa_properties(). | |
c66ffcd5 | 1681 | */ |
dd8f244f | 1682 | static void riscv_cpu_add_user_properties(Object *obj) |
26b2bc58 AF |
1683 | { |
1684 | Property *prop; | |
c01756a7 | 1685 | DeviceState *dev = DEVICE(obj); |
26b2bc58 | 1686 | |
b3df64c8 DHB |
1687 | riscv_cpu_add_misa_properties(obj); |
1688 | ||
26b2bc58 AF |
1689 | for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { |
1690 | qdev_property_add_static(dev, prop); | |
1691 | } | |
6f23aaeb AG |
1692 | |
1693 | #ifndef CONFIG_USER_ONLY | |
1694 | riscv_add_satp_mode_properties(obj); | |
1695 | #endif | |
26b2bc58 AF |
1696 | } |
1697 | ||
1698 | static Property riscv_cpu_properties[] = { | |
1699 | DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), | |
1700 | ||
1701 | DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), | |
1702 | DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), | |
1703 | DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), | |
1704 | ||
277b210d AF |
1705 | #ifndef CONFIG_USER_ONLY |
1706 | DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), | |
1707 | #endif | |
a4a9a443 TO |
1708 | |
1709 | DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), | |
b8312675 | 1710 | |
1711 | DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), | |
1ad3f9bd | 1712 | DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), |
54bd9b6e DHB |
1713 | |
1714 | /* | |
1715 | * write_misa() is marked as experimental for now so mark | |
1716 | * it with -x and default to 'false'. | |
1717 | */ | |
1718 | DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false), | |
c4e95030 AF |
1719 | DEFINE_PROP_END_OF_LIST(), |
1720 | }; | |
1721 | ||
edf64786 SP |
1722 | static gchar *riscv_gdb_arch_name(CPUState *cs) |
1723 | { | |
1724 | RISCVCPU *cpu = RISCV_CPU(cs); | |
1725 | CPURISCVState *env = &cpu->env; | |
1726 | ||
db23e5d9 RH |
1727 | switch (riscv_cpu_mxl(env)) { |
1728 | case MXL_RV32: | |
edf64786 | 1729 | return g_strdup("riscv:rv32"); |
db23e5d9 | 1730 | case MXL_RV64: |
332dab68 | 1731 | case MXL_RV128: |
edf64786 | 1732 | return g_strdup("riscv:rv64"); |
db23e5d9 RH |
1733 | default: |
1734 | g_assert_not_reached(); | |
edf64786 SP |
1735 | } |
1736 | } | |
1737 | ||
b93777e1 BM |
1738 | static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) |
1739 | { | |
1740 | RISCVCPU *cpu = RISCV_CPU(cs); | |
1741 | ||
1742 | if (strcmp(xmlname, "riscv-csr.xml") == 0) { | |
1743 | return cpu->dyn_csr_xml; | |
719d3561 HW |
1744 | } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { |
1745 | return cpu->dyn_vreg_xml; | |
b93777e1 BM |
1746 | } |
1747 | ||
1748 | return NULL; | |
1749 | } | |
1750 | ||
8b80bd28 | 1751 | #ifndef CONFIG_USER_ONLY |
f1bd6f8e MC |
1752 | static int64_t riscv_get_arch_id(CPUState *cs) |
1753 | { | |
1754 | RISCVCPU *cpu = RISCV_CPU(cs); | |
1755 | ||
1756 | return cpu->env.mhartid; | |
1757 | } | |
1758 | ||
8b80bd28 PMD |
1759 | #include "hw/core/sysemu-cpu-ops.h" |
1760 | ||
1761 | static const struct SysemuCPUOps riscv_sysemu_ops = { | |
08928c6d | 1762 | .get_phys_page_debug = riscv_cpu_get_phys_page_debug, |
715e3c1a PMD |
1763 | .write_elf64_note = riscv_cpu_write_elf64_note, |
1764 | .write_elf32_note = riscv_cpu_write_elf32_note, | |
feece4d0 | 1765 | .legacy_vmsd = &vmstate_riscv_cpu, |
8b80bd28 PMD |
1766 | }; |
1767 | #endif | |
1768 | ||
78271684 CF |
1769 | #include "hw/core/tcg-cpu-ops.h" |
1770 | ||
11906557 | 1771 | static const struct TCGCPUOps riscv_tcg_ops = { |
78271684 CF |
1772 | .initialize = riscv_translate_init, |
1773 | .synchronize_from_tb = riscv_cpu_synchronize_from_tb, | |
ad1e84f5 | 1774 | .restore_state_to_opc = riscv_restore_state_to_opc, |
78271684 CF |
1775 | |
1776 | #ifndef CONFIG_USER_ONLY | |
263e2ab2 | 1777 | .tlb_fill = riscv_cpu_tlb_fill, |
17b3c353 | 1778 | .cpu_exec_interrupt = riscv_cpu_exec_interrupt, |
78271684 CF |
1779 | .do_interrupt = riscv_cpu_do_interrupt, |
1780 | .do_transaction_failed = riscv_cpu_do_transaction_failed, | |
1781 | .do_unaligned_access = riscv_cpu_do_unaligned_access, | |
b5f6379d BM |
1782 | .debug_excp_handler = riscv_cpu_debug_excp_handler, |
1783 | .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, | |
1784 | .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, | |
78271684 CF |
1785 | #endif /* !CONFIG_USER_ONLY */ |
1786 | }; | |
1787 | ||
dc5bd18f MC |
1788 | static void riscv_cpu_class_init(ObjectClass *c, void *data) |
1789 | { | |
1790 | RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); | |
1791 | CPUClass *cc = CPU_CLASS(c); | |
1792 | DeviceClass *dc = DEVICE_CLASS(c); | |
4fa485a7 | 1793 | ResettableClass *rc = RESETTABLE_CLASS(c); |
dc5bd18f | 1794 | |
41fbbba7 MZ |
1795 | device_class_set_parent_realize(dc, riscv_cpu_realize, |
1796 | &mcc->parent_realize); | |
dc5bd18f | 1797 | |
4fa485a7 PM |
1798 | resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL, |
1799 | &mcc->parent_phases); | |
dc5bd18f MC |
1800 | |
1801 | cc->class_by_name = riscv_cpu_class_by_name; | |
1802 | cc->has_work = riscv_cpu_has_work; | |
dc5bd18f MC |
1803 | cc->dump_state = riscv_cpu_dump_state; |
1804 | cc->set_pc = riscv_cpu_set_pc; | |
e4fdf9df | 1805 | cc->get_pc = riscv_cpu_get_pc; |
dc5bd18f MC |
1806 | cc->gdb_read_register = riscv_cpu_gdb_read_register; |
1807 | cc->gdb_write_register = riscv_cpu_gdb_write_register; | |
5371f5cd | 1808 | cc->gdb_num_core_regs = 33; |
dc5bd18f MC |
1809 | cc->gdb_stop_before_watchpoint = true; |
1810 | cc->disas_set_info = riscv_cpu_disas_set_info; | |
8a4ca3c1 | 1811 | #ifndef CONFIG_USER_ONLY |
8b80bd28 | 1812 | cc->sysemu_ops = &riscv_sysemu_ops; |
f1bd6f8e | 1813 | cc->get_arch_id = riscv_get_arch_id; |
dc5bd18f | 1814 | #endif |
edf64786 | 1815 | cc->gdb_arch_name = riscv_gdb_arch_name; |
b93777e1 | 1816 | cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; |
78271684 | 1817 | cc->tcg_ops = &riscv_tcg_ops; |
6a3d2e7c | 1818 | |
4f67d30b | 1819 | device_class_set_props(dc, riscv_cpu_properties); |
dc5bd18f MC |
1820 | } |
1821 | ||
246f8796 WL |
1822 | static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, |
1823 | int max_str_len) | |
a775398b AP |
1824 | { |
1825 | char *old = *isa_str; | |
1826 | char *new = *isa_str; | |
1827 | int i; | |
1828 | ||
a775398b | 1829 | for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { |
61a33ea9 WL |
1830 | if (cpu->env.priv_ver >= isa_edata_arr[i].min_version && |
1831 | isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { | |
a775398b AP |
1832 | new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); |
1833 | g_free(old); | |
1834 | old = new; | |
1835 | } | |
1836 | } | |
1837 | ||
1838 | *isa_str = new; | |
1839 | } | |
1840 | ||
dc5bd18f MC |
1841 | char *riscv_isa_string(RISCVCPU *cpu) |
1842 | { | |
1843 | int i; | |
0e2c3770 | 1844 | const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); |
d1fd31f8 MC |
1845 | char *isa_str = g_new(char, maxlen); |
1846 | char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); | |
0e2c3770 TO |
1847 | for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { |
1848 | if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { | |
1849 | *p++ = qemu_tolower(riscv_single_letter_exts[i]); | |
dc5bd18f MC |
1850 | } |
1851 | } | |
d1fd31f8 | 1852 | *p = '\0'; |
a4a9a443 TO |
1853 | if (!cpu->cfg.short_isa_string) { |
1854 | riscv_isa_string_ext(cpu, &isa_str, maxlen); | |
1855 | } | |
d1fd31f8 | 1856 | return isa_str; |
dc5bd18f MC |
1857 | } |
1858 | ||
eab15862 | 1859 | static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) |
dc5bd18f | 1860 | { |
eab15862 MC |
1861 | ObjectClass *class_a = (ObjectClass *)a; |
1862 | ObjectClass *class_b = (ObjectClass *)b; | |
1863 | const char *name_a, *name_b; | |
dc5bd18f | 1864 | |
eab15862 MC |
1865 | name_a = object_class_get_name(class_a); |
1866 | name_b = object_class_get_name(class_b); | |
1867 | return strcmp(name_a, name_b); | |
dc5bd18f MC |
1868 | } |
1869 | ||
eab15862 | 1870 | static void riscv_cpu_list_entry(gpointer data, gpointer user_data) |
dc5bd18f | 1871 | { |
eab15862 MC |
1872 | const char *typename = object_class_get_name(OBJECT_CLASS(data)); |
1873 | int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); | |
dc5bd18f | 1874 | |
0442428a | 1875 | qemu_printf("%.*s\n", len, typename); |
eab15862 | 1876 | } |
dc5bd18f | 1877 | |
0442428a | 1878 | void riscv_cpu_list(void) |
eab15862 | 1879 | { |
eab15862 MC |
1880 | GSList *list; |
1881 | ||
1882 | list = object_class_get_list(TYPE_RISCV_CPU, false); | |
1883 | list = g_slist_sort(list, riscv_cpu_list_compare); | |
0442428a | 1884 | g_slist_foreach(list, riscv_cpu_list_entry, NULL); |
eab15862 | 1885 | g_slist_free(list); |
dc5bd18f MC |
1886 | } |
1887 | ||
eab15862 MC |
1888 | #define DEFINE_CPU(type_name, initfn) \ |
1889 | { \ | |
1890 | .name = type_name, \ | |
1891 | .parent = TYPE_RISCV_CPU, \ | |
1892 | .instance_init = initfn \ | |
1893 | } | |
1894 | ||
9e1a30d3 DHB |
1895 | #define DEFINE_DYNAMIC_CPU(type_name, initfn) \ |
1896 | { \ | |
1897 | .name = type_name, \ | |
1898 | .parent = TYPE_RISCV_DYNAMIC_CPU, \ | |
1899 | .instance_init = initfn \ | |
1900 | } | |
1901 | ||
eab15862 MC |
1902 | static const TypeInfo riscv_cpu_type_infos[] = { |
1903 | { | |
1904 | .name = TYPE_RISCV_CPU, | |
1905 | .parent = TYPE_CPU, | |
1906 | .instance_size = sizeof(RISCVCPU), | |
5de5b99b | 1907 | .instance_align = __alignof__(RISCVCPU), |
eab15862 MC |
1908 | .instance_init = riscv_cpu_init, |
1909 | .abstract = true, | |
1910 | .class_size = sizeof(RISCVCPUClass), | |
1911 | .class_init = riscv_cpu_class_init, | |
1912 | }, | |
9e1a30d3 DHB |
1913 | { |
1914 | .name = TYPE_RISCV_DYNAMIC_CPU, | |
1915 | .parent = TYPE_RISCV_CPU, | |
1916 | .abstract = true, | |
1917 | }, | |
1918 | DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), | |
10f1ca27 YJ |
1919 | #if defined(CONFIG_KVM) |
1920 | DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), | |
1921 | #endif | |
eab15862 | 1922 | #if defined(TARGET_RISCV32) |
9e1a30d3 | 1923 | DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), |
e8905c6c | 1924 | DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), |
114baaca | 1925 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), |
2fdd2c09 | 1926 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), |
114baaca | 1927 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), |
eab15862 | 1928 | #elif defined(TARGET_RISCV64) |
9e1a30d3 | 1929 | DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), |
114baaca AF |
1930 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), |
1931 | DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), | |
6ddc7069 | 1932 | DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), |
95bd8daa | 1933 | DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), |
e1d084a8 | 1934 | DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init), |
9e1a30d3 | 1935 | DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), |
eab15862 MC |
1936 | #endif |
1937 | }; | |
1938 | ||
1939 | DEFINE_TYPES(riscv_cpu_type_infos) |