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dc5bd18f MC |
1 | /* |
2 | * QEMU RISC-V CPU | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #ifndef RISCV_CPU_H | |
21 | #define RISCV_CPU_H | |
22 | ||
2e5b09fd | 23 | #include "hw/core/cpu.h" |
2b7168fc | 24 | #include "hw/registerfields.h" |
32fa1776 | 25 | #include "hw/qdev-properties.h" |
dc5bd18f | 26 | #include "exec/cpu-defs.h" |
69242e7e | 27 | #include "qemu/cpu-float.h" |
db1015e9 | 28 | #include "qom/object.h" |
961738ff | 29 | #include "qemu/int128.h" |
e91a7227 | 30 | #include "cpu_bits.h" |
b902ff29 | 31 | #include "cpu_cfg.h" |
6f23aaeb | 32 | #include "qapi/qapi-types-common.h" |
85840bd2 | 33 | #include "cpu-qom.h" |
dc5bd18f | 34 | |
74433bf0 RH |
35 | #define TCG_GUEST_DEFAULT_MO 0 |
36 | ||
62cf0245 AP |
37 | /* |
38 | * RISC-V-specific extra insn start words: | |
39 | * 1: Original instruction opcode | |
40 | */ | |
41 | #define TARGET_INSN_START_EXTRA_WORDS 1 | |
42 | ||
dc5bd18f MC |
43 | #define RV(x) ((target_ulong)1 << (x - 'A')) |
44 | ||
ed7e6182 | 45 | /* |
efa365b7 | 46 | * Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[] |
ed7e6182 DHB |
47 | * when adding new MISA bits here. |
48 | */ | |
dc5bd18f | 49 | #define RVI RV('I') |
79f86934 | 50 | #define RVE RV('E') /* E and I are mutually exclusive */ |
dc5bd18f MC |
51 | #define RVM RV('M') |
52 | #define RVA RV('A') | |
53 | #define RVF RV('F') | |
54 | #define RVD RV('D') | |
ad9e5aa2 | 55 | #define RVV RV('V') |
dc5bd18f MC |
56 | #define RVC RV('C') |
57 | #define RVS RV('S') | |
58 | #define RVU RV('U') | |
af1fa003 | 59 | #define RVH RV('H') |
53dcea58 | 60 | #define RVJ RV('J') |
4f13abcb | 61 | #define RVG RV('G') |
dc5bd18f | 62 | |
efa365b7 | 63 | extern const uint32_t misa_bits[]; |
ed7e6182 DHB |
64 | const char *riscv_get_misa_ext_name(uint32_t bit); |
65 | const char *riscv_get_misa_ext_description(uint32_t bit); | |
dc5bd18f | 66 | |
238fd586 DHB |
67 | #define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop) |
68 | ||
a46d410c AP |
69 | /* Privileged specification version */ |
70 | enum { | |
71 | PRIV_VERSION_1_10_0 = 0, | |
72 | PRIV_VERSION_1_11_0, | |
3a4af26d | 73 | PRIV_VERSION_1_12_0, |
b9a2b98e DHB |
74 | |
75 | PRIV_VERSION_LATEST = PRIV_VERSION_1_12_0, | |
a46d410c | 76 | }; |
dc5bd18f | 77 | |
9ec6622d | 78 | #define VEXT_VERSION_1_00_0 0x00010000 |
32931383 | 79 | |
33a9a57d YJ |
80 | enum { |
81 | TRANSLATE_SUCCESS, | |
82 | TRANSLATE_FAIL, | |
83 | TRANSLATE_PMP_FAIL, | |
84 | TRANSLATE_G_STAGE_FAIL | |
85 | }; | |
86 | ||
42967f40 LZ |
87 | /* Extension context status */ |
88 | typedef enum { | |
89 | EXT_STATUS_DISABLED = 0, | |
90 | EXT_STATUS_INITIAL, | |
91 | EXT_STATUS_CLEAN, | |
92 | EXT_STATUS_DIRTY, | |
93 | } RISCVExtStatus; | |
94 | ||
dc5bd18f MC |
95 | #define MMU_USER_IDX 3 |
96 | ||
97 | #define MAX_RISCV_PMPS (16) | |
98 | ||
bbf3d1b4 | 99 | #if !defined(CONFIG_USER_ONLY) |
dc5bd18f | 100 | #include "pmp.h" |
95799e36 | 101 | #include "debug.h" |
bbf3d1b4 | 102 | #endif |
dc5bd18f | 103 | |
8a4b5257 | 104 | #define RV_VLEN_MAX 1024 |
3780e337 | 105 | #define RV_MAX_MHPMEVENTS 32 |
621f35bb | 106 | #define RV_MAX_MHPMCOUNTERS 32 |
ad9e5aa2 | 107 | |
33f1beaf FC |
108 | FIELD(VTYPE, VLMUL, 0, 3) |
109 | FIELD(VTYPE, VSEW, 3, 3) | |
3479a814 FC |
110 | FIELD(VTYPE, VTA, 6, 1) |
111 | FIELD(VTYPE, VMA, 7, 1) | |
33f1beaf FC |
112 | FIELD(VTYPE, VEDIV, 8, 2) |
113 | FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) | |
2b7168fc | 114 | |
3780e337 AP |
115 | typedef struct PMUCTRState { |
116 | /* Current value of a counter */ | |
117 | target_ulong mhpmcounter_val; | |
3b57254d | 118 | /* Current value of a counter in RV32 */ |
3780e337 AP |
119 | target_ulong mhpmcounterh_val; |
120 | /* Snapshot values of counter */ | |
121 | target_ulong mhpmcounter_prev; | |
122 | /* Snapshort value of a counter in RV32 */ | |
123 | target_ulong mhpmcounterh_prev; | |
124 | bool started; | |
14664483 AP |
125 | /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */ |
126 | target_ulong irq_overflow_left; | |
3780e337 AP |
127 | } PMUCTRState; |
128 | ||
1ea4a06a | 129 | struct CPUArchState { |
dc5bd18f | 130 | target_ulong gpr[32]; |
2b547084 | 131 | target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ |
ad9e5aa2 LZ |
132 | |
133 | /* vector coprocessor state. */ | |
134 | uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); | |
135 | target_ulong vxrm; | |
136 | target_ulong vxsat; | |
137 | target_ulong vl; | |
138 | target_ulong vstart; | |
139 | target_ulong vtype; | |
d96a271a | 140 | bool vill; |
ad9e5aa2 | 141 | |
dc5bd18f MC |
142 | target_ulong pc; |
143 | target_ulong load_res; | |
144 | target_ulong load_val; | |
145 | ||
04bc3027 PMD |
146 | /* Floating-Point state */ |
147 | uint64_t fpr[32]; /* assume both F and D extensions */ | |
dc5bd18f | 148 | target_ulong frm; |
04bc3027 | 149 | float_status fp_status; |
dc5bd18f MC |
150 | |
151 | target_ulong badaddr; | |
62cf0245 | 152 | target_ulong bins; |
48eaeb56 | 153 | |
36a18664 | 154 | target_ulong guest_phys_fault_addr; |
dc5bd18f | 155 | |
dc5bd18f | 156 | target_ulong priv_ver; |
d2c1a177 | 157 | target_ulong bext_ver; |
32931383 | 158 | target_ulong vext_ver; |
e91a7227 RH |
159 | |
160 | /* RISCVMXL, but uint32_t for vmstate migration */ | |
161 | uint32_t misa_mxl; /* current mxl */ | |
162 | uint32_t misa_mxl_max; /* max mxl for this cpu */ | |
163 | uint32_t misa_ext; /* current extensions */ | |
164 | uint32_t misa_ext_mask; /* max ext for this cpu */ | |
440544e1 | 165 | uint32_t xl; /* current xlen */ |
dc5bd18f | 166 | |
b3a5d1fb FP |
167 | /* 128-bit helpers upper part return value */ |
168 | target_ulong retxh; | |
169 | ||
ce3af0bb WL |
170 | target_ulong jvt; |
171 | ||
5836c3ec KC |
172 | #ifdef CONFIG_USER_ONLY |
173 | uint32_t elf_flags; | |
174 | #endif | |
175 | ||
dc5bd18f MC |
176 | #ifndef CONFIG_USER_ONLY |
177 | target_ulong priv; | |
ef6bb7b6 | 178 | /* This contains QEMU specific information about the virt state. */ |
b3c5077b | 179 | bool virt_enabled; |
cd032fe7 | 180 | target_ulong geilen; |
277b210d | 181 | uint64_t resetvec; |
dc5bd18f MC |
182 | |
183 | target_ulong mhartid; | |
284d697c YJ |
184 | /* |
185 | * For RV32 this is 32-bit mstatus and 32-bit mstatush. | |
186 | * For RV64 this is a 64-bit mstatus. | |
187 | */ | |
188 | uint64_t mstatus; | |
85ba724f | 189 | |
d028ac75 | 190 | uint64_t mip; |
33fe584f AF |
191 | /* |
192 | * MIP contains the software writable version of SEIP ORed with the | |
193 | * external interrupt value. The MIP register is always up-to-date. | |
194 | * To keep track of the current source, we also save booleans of the values | |
195 | * here. | |
196 | */ | |
197 | bool external_seip; | |
198 | bool software_seip; | |
66e594f2 | 199 | |
d028ac75 | 200 | uint64_t miclaim; |
85ba724f | 201 | |
d028ac75 AP |
202 | uint64_t mie; |
203 | uint64_t mideleg; | |
dc5bd18f | 204 | |
dc5bd18f | 205 | target_ulong satp; /* since: priv-1.10.0 */ |
ac12b601 | 206 | target_ulong stval; |
dc5bd18f MC |
207 | target_ulong medeleg; |
208 | ||
209 | target_ulong stvec; | |
210 | target_ulong sepc; | |
211 | target_ulong scause; | |
212 | ||
213 | target_ulong mtvec; | |
214 | target_ulong mepc; | |
215 | target_ulong mcause; | |
216 | target_ulong mtval; /* since: priv-1.10.0 */ | |
217 | ||
43dc93af AP |
218 | /* Machine and Supervisor interrupt priorities */ |
219 | uint8_t miprio[64]; | |
220 | uint8_t siprio[64]; | |
221 | ||
d1ceff40 AP |
222 | /* AIA CSRs */ |
223 | target_ulong miselect; | |
224 | target_ulong siselect; | |
225 | ||
bd023ce3 AF |
226 | /* Hypervisor CSRs */ |
227 | target_ulong hstatus; | |
228 | target_ulong hedeleg; | |
d028ac75 | 229 | uint64_t hideleg; |
bd023ce3 AF |
230 | target_ulong hcounteren; |
231 | target_ulong htval; | |
232 | target_ulong htinst; | |
233 | target_ulong hgatp; | |
cd032fe7 AP |
234 | target_ulong hgeie; |
235 | target_ulong hgeip; | |
c6957248 | 236 | uint64_t htimedelta; |
bd023ce3 | 237 | |
43dc93af | 238 | /* Hypervisor controlled virtual interrupt priorities */ |
2b602398 | 239 | target_ulong hvictl; |
43dc93af AP |
240 | uint8_t hviprio[64]; |
241 | ||
2c64ab66 FP |
242 | /* Upper 64-bits of 128-bit CSRs */ |
243 | uint64_t mscratchh; | |
244 | uint64_t sscratchh; | |
245 | ||
bd023ce3 | 246 | /* Virtual CSRs */ |
284d697c YJ |
247 | /* |
248 | * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. | |
249 | * For RV64 this is a 64-bit vsstatus. | |
250 | */ | |
251 | uint64_t vsstatus; | |
bd023ce3 AF |
252 | target_ulong vstvec; |
253 | target_ulong vsscratch; | |
254 | target_ulong vsepc; | |
255 | target_ulong vscause; | |
256 | target_ulong vstval; | |
257 | target_ulong vsatp; | |
258 | ||
d1ceff40 AP |
259 | /* AIA VS-mode CSRs */ |
260 | target_ulong vsiselect; | |
261 | ||
bd023ce3 AF |
262 | target_ulong mtval2; |
263 | target_ulong mtinst; | |
264 | ||
66e594f2 AF |
265 | /* HS Backup CSRs */ |
266 | target_ulong stvec_hs; | |
267 | target_ulong sscratch_hs; | |
268 | target_ulong sepc_hs; | |
269 | target_ulong scause_hs; | |
270 | target_ulong stval_hs; | |
271 | target_ulong satp_hs; | |
284d697c | 272 | uint64_t mstatus_hs; |
66e594f2 | 273 | |
3b57254d WL |
274 | /* |
275 | * Signals whether the current exception occurred with two-stage address | |
276 | * translation active. | |
277 | */ | |
ec352d0c | 278 | bool two_stage_lookup; |
8e2aa21b AP |
279 | /* |
280 | * Signals whether the current exception occurred while doing two-stage | |
281 | * address translation for the VS-stage page table walk. | |
282 | */ | |
283 | bool two_stage_indirect_lookup; | |
ec352d0c | 284 | |
8c59f5c1 MC |
285 | target_ulong scounteren; |
286 | target_ulong mcounteren; | |
dc5bd18f | 287 | |
b1675eeb AP |
288 | target_ulong mcountinhibit; |
289 | ||
3780e337 AP |
290 | /* PMU counter state */ |
291 | PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; | |
621f35bb | 292 | |
3b57254d | 293 | /* PMU event selector configured values. First three are unused */ |
621f35bb AP |
294 | target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; |
295 | ||
3b57254d | 296 | /* PMU event selector configured values for RV32 */ |
14664483 AP |
297 | target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; |
298 | ||
dc5bd18f MC |
299 | target_ulong sscratch; |
300 | target_ulong mscratch; | |
301 | ||
43888c2f AP |
302 | /* Sstc CSRs */ |
303 | uint64_t stimecmp; | |
304 | ||
3ec0fe18 AP |
305 | uint64_t vstimecmp; |
306 | ||
dc5bd18f MC |
307 | /* physical memory protection */ |
308 | pmp_table_t pmp_state; | |
2582a95c | 309 | target_ulong mseccfg; |
753e3fe2 | 310 | |
95799e36 BM |
311 | /* trigger module */ |
312 | target_ulong trigger_cur; | |
9495c488 FC |
313 | target_ulong tdata1[RV_MAX_TRIGGERS]; |
314 | target_ulong tdata2[RV_MAX_TRIGGERS]; | |
315 | target_ulong tdata3[RV_MAX_TRIGGERS]; | |
316 | struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; | |
317 | struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; | |
5a4ae64c LZ |
318 | QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; |
319 | int64_t last_icount; | |
577f0286 | 320 | bool itrigger_enabled; |
95799e36 | 321 | |
c6957248 | 322 | /* machine specific rdtime callback */ |
e2f01f3c FC |
323 | uint64_t (*rdtime_fn)(void *); |
324 | void *rdtime_fn_arg; | |
c6957248 | 325 | |
69077dd6 AP |
326 | /* machine specific AIA ireg read-modify-write callback */ |
327 | #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ | |
328 | ((((__xlen) & 0xff) << 24) | \ | |
329 | (((__vgein) & 0x3f) << 20) | \ | |
330 | (((__virt) & 0x1) << 18) | \ | |
331 | (((__priv) & 0x3) << 16) | \ | |
332 | (__isel & 0xffff)) | |
333 | #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) | |
334 | #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) | |
335 | #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) | |
336 | #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) | |
337 | #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) | |
338 | int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, | |
339 | target_ulong *val, target_ulong new_val, target_ulong write_mask); | |
340 | void *aia_ireg_rmw_fn_arg[4]; | |
341 | ||
753e3fe2 JW |
342 | /* True if in debugger mode. */ |
343 | bool debugger; | |
4bbe8033 AB |
344 | |
345 | /* | |
346 | * CSRs for PointerMasking extension | |
347 | */ | |
348 | target_ulong mmte; | |
349 | target_ulong mpmmask; | |
350 | target_ulong mpmbase; | |
351 | target_ulong spmmask; | |
352 | target_ulong spmbase; | |
353 | target_ulong upmmask; | |
354 | target_ulong upmbase; | |
29a9ec9b | 355 | |
42fe7499 | 356 | /* CSRs for execution environment configuration */ |
29a9ec9b | 357 | uint64_t menvcfg; |
3bee0e40 MC |
358 | uint64_t mstateen[SMSTATEEN_MAX_COUNT]; |
359 | uint64_t hstateen[SMSTATEEN_MAX_COUNT]; | |
360 | uint64_t sstateen[SMSTATEEN_MAX_COUNT]; | |
29a9ec9b AP |
361 | target_ulong senvcfg; |
362 | uint64_t henvcfg; | |
dc5bd18f | 363 | #endif |
40bfa5f6 LZ |
364 | target_ulong cur_pmmask; |
365 | target_ulong cur_pmbase; | |
dc5bd18f | 366 | |
dc5bd18f | 367 | /* Fields from here on are preserved across CPU reset. */ |
43888c2f | 368 | QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ |
3ec0fe18 AP |
369 | QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */ |
370 | bool vstime_irq; | |
ad40be27 YJ |
371 | |
372 | hwaddr kernel_addr; | |
373 | hwaddr fdt_addr; | |
27abe66f | 374 | |
9638cbde | 375 | #ifdef CONFIG_KVM |
27abe66f YJ |
376 | /* kvm timer */ |
377 | bool kvm_timer_dirty; | |
378 | uint64_t kvm_timer_time; | |
379 | uint64_t kvm_timer_compare; | |
380 | uint64_t kvm_timer_state; | |
381 | uint64_t kvm_timer_frequency; | |
9638cbde | 382 | #endif /* CONFIG_KVM */ |
dc5bd18f MC |
383 | }; |
384 | ||
3b57254d | 385 | /* |
dc5bd18f MC |
386 | * RISCVCPU: |
387 | * @env: #CPURISCVState | |
388 | * | |
389 | * A RISCV CPU. | |
390 | */ | |
b36e239e | 391 | struct ArchCPU { |
3b57254d | 392 | /* < private > */ |
dc5bd18f | 393 | CPUState parent_obj; |
3b57254d | 394 | /* < public > */ |
3b3d7df5 | 395 | |
dc5bd18f | 396 | CPURISCVState env; |
c4e95030 | 397 | |
b93777e1 | 398 | char *dyn_csr_xml; |
719d3561 | 399 | char *dyn_vreg_xml; |
b93777e1 | 400 | |
c4e95030 | 401 | /* Configuration Settings */ |
466292bd | 402 | RISCVCPUConfig cfg; |
14664483 AP |
403 | |
404 | QEMUTimer *pmu_timer; | |
405 | /* A bitmask of Available programmable counters */ | |
406 | uint32_t pmu_avail_ctrs; | |
407 | /* Mapping of events to counters */ | |
408 | GHashTable *pmu_event_ctr_map; | |
db1015e9 | 409 | }; |
dc5bd18f | 410 | |
dc5bd18f MC |
411 | static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) |
412 | { | |
e91a7227 | 413 | return (env->misa_ext & ext) != 0; |
dc5bd18f MC |
414 | } |
415 | ||
dc5bd18f | 416 | #include "cpu_user.h" |
dc5bd18f MC |
417 | |
418 | extern const char * const riscv_int_regnames[]; | |
2b547084 | 419 | extern const char * const riscv_int_regnamesh[]; |
dc5bd18f | 420 | extern const char * const riscv_fpr_regnames[]; |
dc5bd18f | 421 | |
c51a3f5d | 422 | const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); |
dc5bd18f | 423 | void riscv_cpu_do_interrupt(CPUState *cpu); |
43a96588 | 424 | int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, |
1af0006a | 425 | int cpuid, DumpState *s); |
43a96588 | 426 | int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, |
1af0006a | 427 | int cpuid, DumpState *s); |
a010bdbe | 428 | int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); |
dc5bd18f | 429 | int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); |
43dc93af AP |
430 | int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); |
431 | uint8_t riscv_cpu_default_priority(int irq); | |
8f42415f | 432 | uint64_t riscv_cpu_all_pending(CPURISCVState *env); |
43dc93af AP |
433 | int riscv_cpu_mirq_pending(CPURISCVState *env); |
434 | int riscv_cpu_sirq_pending(CPURISCVState *env); | |
435 | int riscv_cpu_vsirq_pending(CPURISCVState *env); | |
b345b480 | 436 | bool riscv_cpu_fp_enabled(CPURISCVState *env); |
cd032fe7 AP |
437 | target_ulong riscv_cpu_get_geilen(CPURISCVState *env); |
438 | void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); | |
61b4b69d | 439 | bool riscv_cpu_vector_enabled(CPURISCVState *env); |
ef6bb7b6 | 440 | void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); |
dc5bd18f | 441 | int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); |
8905770b | 442 | G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, |
246f8796 WL |
443 | MMUAccessType access_type, |
444 | int mmu_idx, uintptr_t retaddr); | |
8a4ca3c1 RH |
445 | bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
446 | MMUAccessType access_type, int mmu_idx, | |
447 | bool probe, uintptr_t retaddr); | |
dc5bd18f | 448 | char *riscv_isa_string(RISCVCPU *cpu); |
0442428a | 449 | void riscv_cpu_list(void); |
dc5bd18f | 450 | |
dc5bd18f MC |
451 | #define cpu_list riscv_cpu_list |
452 | #define cpu_mmu_index riscv_cpu_mmu_index | |
453 | ||
85ba724f | 454 | #ifndef CONFIG_USER_ONLY |
d90ebc47 PMD |
455 | void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, |
456 | vaddr addr, unsigned size, | |
457 | MMUAccessType access_type, | |
458 | int mmu_idx, MemTxAttrs attrs, | |
459 | MemTxResult response, uintptr_t retaddr); | |
6d2d454a | 460 | hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); |
17b3c353 | 461 | bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); |
66e594f2 | 462 | void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); |
d028ac75 | 463 | int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); |
bbb9fc25 WL |
464 | uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, |
465 | uint64_t value); | |
1ebad505 | 466 | void riscv_cpu_interrupt(CPURISCVState *env); |
85ba724f | 467 | #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ |
e2f01f3c FC |
468 | void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), |
469 | void *arg); | |
69077dd6 AP |
470 | void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, |
471 | int (*rmw_fn)(void *arg, | |
472 | target_ulong reg, | |
473 | target_ulong *val, | |
474 | target_ulong new_val, | |
475 | target_ulong write_mask), | |
476 | void *rmw_fn_arg); | |
ce3af0bb WL |
477 | |
478 | RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit); | |
85ba724f | 479 | #endif |
fb738839 | 480 | void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); |
dc5bd18f MC |
481 | |
482 | void riscv_translate_init(void); | |
8905770b MAL |
483 | G_NORETURN void riscv_raise_exception(CPURISCVState *env, |
484 | uint32_t exception, uintptr_t pc); | |
dc5bd18f | 485 | |
fb738839 MC |
486 | target_ulong riscv_cpu_get_fflags(CPURISCVState *env); |
487 | void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); | |
dc5bd18f | 488 | |
2b7168fc LZ |
489 | #include "exec/cpu-all.h" |
490 | ||
61d56494 | 491 | FIELD(TB_FLAGS, MEM_IDX, 0, 3) |
ebd47648 LZ |
492 | FIELD(TB_FLAGS, FS, 3, 2) |
493 | /* Vector flags */ | |
494 | FIELD(TB_FLAGS, VS, 5, 2) | |
495 | FIELD(TB_FLAGS, LMUL, 7, 3) | |
496 | FIELD(TB_FLAGS, SEW, 10, 3) | |
497 | FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1) | |
498 | FIELD(TB_FLAGS, VILL, 14, 1) | |
0f58cbbe | 499 | FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1) |
92371bd9 | 500 | /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ |
25f3ddff | 501 | FIELD(TB_FLAGS, XL, 16, 2) |
0774a7a1 | 502 | /* If PointerMasking should be applied */ |
25f3ddff RH |
503 | FIELD(TB_FLAGS, PM_MASK_ENABLED, 18, 1) |
504 | FIELD(TB_FLAGS, PM_BASE_ENABLED, 19, 1) | |
505 | FIELD(TB_FLAGS, VTA, 20, 1) | |
506 | FIELD(TB_FLAGS, VMA, 21, 1) | |
2c9d7471 | 507 | /* Native debug itrigger */ |
25f3ddff | 508 | FIELD(TB_FLAGS, ITRIGGER, 22, 1) |
f1966390 | 509 | /* Virtual mode enabled */ |
25f3ddff | 510 | FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1) |
0f58cbbe | 511 | FIELD(TB_FLAGS, PRIV, 24, 2) |
3a610f54 | 512 | FIELD(TB_FLAGS, AXL, 26, 2) |
2b7168fc | 513 | |
db23e5d9 RH |
514 | #ifdef TARGET_RISCV32 |
515 | #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) | |
516 | #else | |
517 | static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) | |
518 | { | |
519 | return env->misa_mxl; | |
520 | } | |
521 | #endif | |
2b602398 | 522 | #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) |
51ae0cab | 523 | |
d4ea7117 DHB |
524 | static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) |
525 | { | |
526 | return &env_archcpu(env)->cfg; | |
527 | } | |
528 | ||
3a610f54 WL |
529 | #if !defined(CONFIG_USER_ONLY) |
530 | static inline int cpu_address_mode(CPURISCVState *env) | |
531 | { | |
532 | int mode = env->priv; | |
533 | ||
534 | if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) { | |
535 | mode = get_field(env->mstatus, MSTATUS_MPP); | |
536 | } | |
537 | return mode; | |
538 | } | |
539 | ||
540 | static inline RISCVMXL cpu_get_xl(CPURISCVState *env, target_ulong mode) | |
440544e1 LZ |
541 | { |
542 | RISCVMXL xl = env->misa_mxl; | |
440544e1 LZ |
543 | /* |
544 | * When emulating a 32-bit-only cpu, use RV32. | |
545 | * When emulating a 64-bit cpu, and MXL has been reduced to RV32, | |
546 | * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened | |
547 | * back to RV64 for lower privs. | |
548 | */ | |
549 | if (xl != MXL_RV32) { | |
3a610f54 | 550 | switch (mode) { |
440544e1 LZ |
551 | case PRV_M: |
552 | break; | |
553 | case PRV_U: | |
554 | xl = get_field(env->mstatus, MSTATUS64_UXL); | |
555 | break; | |
44b8f74b | 556 | default: /* PRV_S */ |
440544e1 LZ |
557 | xl = get_field(env->mstatus, MSTATUS64_SXL); |
558 | break; | |
559 | } | |
560 | } | |
440544e1 LZ |
561 | return xl; |
562 | } | |
563 | #endif | |
564 | ||
3a610f54 WL |
565 | #if defined(TARGET_RISCV32) |
566 | #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) | |
567 | #else | |
568 | static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) | |
569 | { | |
570 | #if !defined(CONFIG_USER_ONLY) | |
571 | return cpu_get_xl(env, env->priv); | |
572 | #else | |
573 | return env->misa_mxl; | |
574 | #endif | |
575 | } | |
576 | #endif | |
577 | ||
578 | #if defined(TARGET_RISCV32) | |
579 | #define cpu_address_xl(env) ((void)(env), MXL_RV32) | |
580 | #else | |
581 | static inline RISCVMXL cpu_address_xl(CPURISCVState *env) | |
582 | { | |
583 | #ifdef CONFIG_USER_ONLY | |
584 | return env->xl; | |
585 | #else | |
586 | int mode = cpu_address_mode(env); | |
587 | ||
588 | return cpu_get_xl(env, mode); | |
589 | #endif | |
590 | } | |
591 | #endif | |
592 | ||
31961cfe LZ |
593 | static inline int riscv_cpu_xlen(CPURISCVState *env) |
594 | { | |
595 | return 16 << env->xl; | |
596 | } | |
597 | ||
05e6ca5e GR |
598 | #ifdef TARGET_RISCV32 |
599 | #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) | |
600 | #else | |
601 | static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) | |
602 | { | |
603 | #ifdef CONFIG_USER_ONLY | |
604 | return env->misa_mxl; | |
605 | #else | |
606 | return get_field(env->mstatus, MSTATUS64_SXL); | |
607 | #endif | |
608 | } | |
609 | #endif | |
610 | ||
2b7168fc | 611 | /* |
a689a82b FC |
612 | * Encode LMUL to lmul as follows: |
613 | * LMUL vlmul lmul | |
614 | * 1 000 0 | |
615 | * 2 001 1 | |
616 | * 4 010 2 | |
617 | * 8 011 3 | |
618 | * - 100 - | |
619 | * 1/8 101 -3 | |
620 | * 1/4 110 -2 | |
621 | * 1/2 111 -1 | |
622 | * | |
623 | * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) | |
624 | * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 | |
625 | * => VLMAX = vlen >> (1 + 3 - (-3)) | |
626 | * = 256 >> 7 | |
627 | * = 2 | |
2b7168fc LZ |
628 | */ |
629 | static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) | |
630 | { | |
a689a82b FC |
631 | uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); |
632 | int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); | |
2b7168fc LZ |
633 | return cpu->cfg.vlen >> (sew + 3 - lmul); |
634 | } | |
635 | ||
bb5de525 AJ |
636 | void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, |
637 | uint64_t *cs_base, uint32_t *pflags); | |
dc5bd18f | 638 | |
40bfa5f6 LZ |
639 | void riscv_cpu_update_mask(CPURISCVState *env); |
640 | ||
533c91e8 AF |
641 | RISCVException riscv_csrrw(CPURISCVState *env, int csrno, |
642 | target_ulong *ret_value, | |
643 | target_ulong new_value, target_ulong write_mask); | |
644 | RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, | |
645 | target_ulong *ret_value, | |
646 | target_ulong new_value, | |
647 | target_ulong write_mask); | |
c7b95171 | 648 | |
fb738839 MC |
649 | static inline void riscv_csr_write(CPURISCVState *env, int csrno, |
650 | target_ulong val) | |
c7b95171 MC |
651 | { |
652 | riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); | |
653 | } | |
654 | ||
fb738839 | 655 | static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) |
c7b95171 MC |
656 | { |
657 | target_ulong val = 0; | |
658 | riscv_csrrw(env, csrno, &val, 0, 0); | |
659 | return val; | |
660 | } | |
661 | ||
0e62f92e AF |
662 | typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, |
663 | int csrno); | |
605def6e AF |
664 | typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, |
665 | target_ulong *ret_value); | |
666 | typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, | |
667 | target_ulong new_value); | |
668 | typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, | |
669 | target_ulong *ret_value, | |
670 | target_ulong new_value, | |
671 | target_ulong write_mask); | |
c7b95171 | 672 | |
961738ff FP |
673 | RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, |
674 | Int128 *ret_value, | |
675 | Int128 new_value, Int128 write_mask); | |
676 | ||
457c360f FP |
677 | typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, |
678 | Int128 *ret_value); | |
679 | typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, | |
680 | Int128 new_value); | |
681 | ||
c7b95171 | 682 | typedef struct { |
8ceac5dc | 683 | const char *name; |
a88365c1 | 684 | riscv_csr_predicate_fn predicate; |
c7b95171 MC |
685 | riscv_csr_read_fn read; |
686 | riscv_csr_write_fn write; | |
687 | riscv_csr_op_fn op; | |
457c360f FP |
688 | riscv_csr_read128_fn read128; |
689 | riscv_csr_write128_fn write128; | |
a4b2fa43 AP |
690 | /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ |
691 | uint32_t min_priv_ver; | |
c7b95171 MC |
692 | } riscv_csr_operations; |
693 | ||
56118ee8 BM |
694 | /* CSR function table constants */ |
695 | enum { | |
696 | CSR_TABLE_SIZE = 0x1000 | |
697 | }; | |
698 | ||
3b57254d | 699 | /* |
14664483 AP |
700 | * The event id are encoded based on the encoding specified in the |
701 | * SBI specification v0.3 | |
702 | */ | |
703 | ||
704 | enum riscv_pmu_event_idx { | |
705 | RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01, | |
706 | RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02, | |
707 | RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019, | |
708 | RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B, | |
709 | RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021, | |
710 | }; | |
711 | ||
36c1118d DHB |
712 | /* used by tcg/tcg-cpu.c*/ |
713 | void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); | |
36c1118d | 714 | bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); |
f51d03b0 | 715 | void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext); |
36c1118d | 716 | |
32fa1776 DHB |
717 | typedef struct RISCVCPUMultiExtConfig { |
718 | const char *name; | |
719 | uint32_t offset; | |
720 | bool enabled; | |
721 | } RISCVCPUMultiExtConfig; | |
722 | ||
723 | extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[]; | |
724 | extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[]; | |
725 | extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; | |
8043effd | 726 | extern const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[]; |
32fa1776 DHB |
727 | extern Property riscv_cpu_options[]; |
728 | ||
7935e2c4 DHB |
729 | typedef struct isa_ext_data { |
730 | const char *name; | |
731 | int min_version; | |
732 | int ext_enable_offset; | |
733 | } RISCVIsaExtData; | |
734 | extern const RISCVIsaExtData isa_edata_arr[]; | |
b933720b | 735 | char *riscv_cpu_get_name(RISCVCPU *cpu); |
7935e2c4 | 736 | |
7d0c302c | 737 | void riscv_add_satp_mode_properties(Object *obj); |
32fa1776 | 738 | |
56118ee8 | 739 | /* CSR function table */ |
6f03770d | 740 | extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; |
56118ee8 | 741 | |
6f23aaeb AG |
742 | extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; |
743 | ||
c7b95171 MC |
744 | void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); |
745 | void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); | |
dc5bd18f | 746 | |
5371f5cd JW |
747 | void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); |
748 | ||
6f23aaeb AG |
749 | uint8_t satp_mode_max_from_map(uint32_t map); |
750 | const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); | |
751 | ||
dc5bd18f | 752 | #endif /* RISCV_CPU_H */ |