]>
Commit | Line | Data |
---|---|---|
dc5bd18f MC |
1 | /* |
2 | * QEMU RISC-V CPU | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #ifndef RISCV_CPU_H | |
21 | #define RISCV_CPU_H | |
22 | ||
2e5b09fd | 23 | #include "hw/core/cpu.h" |
2b7168fc | 24 | #include "hw/registerfields.h" |
dc5bd18f | 25 | #include "exec/cpu-defs.h" |
135b03cb | 26 | #include "fpu/softfloat-types.h" |
db1015e9 | 27 | #include "qom/object.h" |
dc5bd18f | 28 | |
74433bf0 RH |
29 | #define TCG_GUEST_DEFAULT_MO 0 |
30 | ||
dc5bd18f MC |
31 | #define TYPE_RISCV_CPU "riscv-cpu" |
32 | ||
33 | #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU | |
34 | #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) | |
0dacec87 | 35 | #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU |
dc5bd18f MC |
36 | |
37 | #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") | |
8903bf6e AF |
38 | #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") |
39 | #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") | |
36b80ad9 | 40 | #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") |
dc5bd18f | 41 | #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") |
d784733b | 42 | #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") |
dc5bd18f MC |
43 | #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") |
44 | #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") | |
45 | #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") | |
46 | ||
c0a635f3 AF |
47 | #if defined(TARGET_RISCV32) |
48 | # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 | |
49 | #elif defined(TARGET_RISCV64) | |
50 | # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 | |
51 | #endif | |
52 | ||
dc5bd18f MC |
53 | #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) |
54 | #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) | |
55 | ||
56 | #if defined(TARGET_RISCV32) | |
57 | #define RVXLEN RV32 | |
58 | #elif defined(TARGET_RISCV64) | |
59 | #define RVXLEN RV64 | |
60 | #endif | |
61 | ||
62 | #define RV(x) ((target_ulong)1 << (x - 'A')) | |
63 | ||
64 | #define RVI RV('I') | |
79f86934 | 65 | #define RVE RV('E') /* E and I are mutually exclusive */ |
dc5bd18f MC |
66 | #define RVM RV('M') |
67 | #define RVA RV('A') | |
68 | #define RVF RV('F') | |
69 | #define RVD RV('D') | |
ad9e5aa2 | 70 | #define RVV RV('V') |
dc5bd18f MC |
71 | #define RVC RV('C') |
72 | #define RVS RV('S') | |
73 | #define RVU RV('U') | |
af1fa003 | 74 | #define RVH RV('H') |
dc5bd18f MC |
75 | |
76 | /* S extension denotes that Supervisor mode exists, however it is possible | |
77 | to have a core that support S mode but does not have an MMU and there | |
78 | is currently no bit in misa to indicate whether an MMU exists or not | |
a88365c1 | 79 | so a cpu features bitfield is required, likewise for optional PMP support */ |
dc5bd18f | 80 | enum { |
a88365c1 | 81 | RISCV_FEATURE_MMU, |
f18637cd MC |
82 | RISCV_FEATURE_PMP, |
83 | RISCV_FEATURE_MISA | |
dc5bd18f MC |
84 | }; |
85 | ||
dc5bd18f | 86 | #define PRIV_VERSION_1_10_0 0x00011000 |
6729dbbd | 87 | #define PRIV_VERSION_1_11_0 0x00011100 |
dc5bd18f | 88 | |
32931383 LZ |
89 | #define VEXT_VERSION_0_07_1 0x00000701 |
90 | ||
33a9a57d YJ |
91 | enum { |
92 | TRANSLATE_SUCCESS, | |
93 | TRANSLATE_FAIL, | |
94 | TRANSLATE_PMP_FAIL, | |
95 | TRANSLATE_G_STAGE_FAIL | |
96 | }; | |
97 | ||
dc5bd18f MC |
98 | #define MMU_USER_IDX 3 |
99 | ||
100 | #define MAX_RISCV_PMPS (16) | |
101 | ||
102 | typedef struct CPURISCVState CPURISCVState; | |
103 | ||
104 | #include "pmp.h" | |
105 | ||
6bf91617 | 106 | #define RV_VLEN_MAX 256 |
ad9e5aa2 | 107 | |
2b7168fc LZ |
108 | FIELD(VTYPE, VLMUL, 0, 2) |
109 | FIELD(VTYPE, VSEW, 2, 3) | |
110 | FIELD(VTYPE, VEDIV, 5, 2) | |
111 | FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9) | |
fbcbafa2 | 112 | FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) |
2b7168fc | 113 | |
dc5bd18f MC |
114 | struct CPURISCVState { |
115 | target_ulong gpr[32]; | |
116 | uint64_t fpr[32]; /* assume both F and D extensions */ | |
ad9e5aa2 LZ |
117 | |
118 | /* vector coprocessor state. */ | |
119 | uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); | |
120 | target_ulong vxrm; | |
121 | target_ulong vxsat; | |
122 | target_ulong vl; | |
123 | target_ulong vstart; | |
124 | target_ulong vtype; | |
125 | ||
dc5bd18f MC |
126 | target_ulong pc; |
127 | target_ulong load_res; | |
128 | target_ulong load_val; | |
129 | ||
130 | target_ulong frm; | |
131 | ||
132 | target_ulong badaddr; | |
36a18664 | 133 | target_ulong guest_phys_fault_addr; |
dc5bd18f | 134 | |
dc5bd18f | 135 | target_ulong priv_ver; |
32931383 | 136 | target_ulong vext_ver; |
dc5bd18f | 137 | target_ulong misa; |
f18637cd | 138 | target_ulong misa_mask; |
dc5bd18f MC |
139 | |
140 | uint32_t features; | |
141 | ||
5836c3ec KC |
142 | #ifdef CONFIG_USER_ONLY |
143 | uint32_t elf_flags; | |
144 | #endif | |
145 | ||
dc5bd18f MC |
146 | #ifndef CONFIG_USER_ONLY |
147 | target_ulong priv; | |
ef6bb7b6 AF |
148 | /* This contains QEMU specific information about the virt state. */ |
149 | target_ulong virt; | |
dc5bd18f MC |
150 | target_ulong resetvec; |
151 | ||
152 | target_ulong mhartid; | |
284d697c YJ |
153 | /* |
154 | * For RV32 this is 32-bit mstatus and 32-bit mstatush. | |
155 | * For RV64 this is a 64-bit mstatus. | |
156 | */ | |
157 | uint64_t mstatus; | |
85ba724f | 158 | |
02861613 | 159 | target_ulong mip; |
66e594f2 | 160 | |
e3e7039c | 161 | uint32_t miclaim; |
85ba724f | 162 | |
dc5bd18f MC |
163 | target_ulong mie; |
164 | target_ulong mideleg; | |
165 | ||
166 | target_ulong sptbr; /* until: priv-1.9.1 */ | |
167 | target_ulong satp; /* since: priv-1.10.0 */ | |
168 | target_ulong sbadaddr; | |
169 | target_ulong mbadaddr; | |
170 | target_ulong medeleg; | |
171 | ||
172 | target_ulong stvec; | |
173 | target_ulong sepc; | |
174 | target_ulong scause; | |
175 | ||
176 | target_ulong mtvec; | |
177 | target_ulong mepc; | |
178 | target_ulong mcause; | |
179 | target_ulong mtval; /* since: priv-1.10.0 */ | |
180 | ||
bd023ce3 AF |
181 | /* Hypervisor CSRs */ |
182 | target_ulong hstatus; | |
183 | target_ulong hedeleg; | |
184 | target_ulong hideleg; | |
185 | target_ulong hcounteren; | |
186 | target_ulong htval; | |
187 | target_ulong htinst; | |
188 | target_ulong hgatp; | |
c6957248 | 189 | uint64_t htimedelta; |
bd023ce3 AF |
190 | |
191 | /* Virtual CSRs */ | |
284d697c YJ |
192 | /* |
193 | * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. | |
194 | * For RV64 this is a 64-bit vsstatus. | |
195 | */ | |
196 | uint64_t vsstatus; | |
bd023ce3 AF |
197 | target_ulong vstvec; |
198 | target_ulong vsscratch; | |
199 | target_ulong vsepc; | |
200 | target_ulong vscause; | |
201 | target_ulong vstval; | |
202 | target_ulong vsatp; | |
203 | ||
204 | target_ulong mtval2; | |
205 | target_ulong mtinst; | |
206 | ||
66e594f2 AF |
207 | /* HS Backup CSRs */ |
208 | target_ulong stvec_hs; | |
209 | target_ulong sscratch_hs; | |
210 | target_ulong sepc_hs; | |
211 | target_ulong scause_hs; | |
212 | target_ulong stval_hs; | |
213 | target_ulong satp_hs; | |
284d697c | 214 | uint64_t mstatus_hs; |
66e594f2 | 215 | |
8c59f5c1 MC |
216 | target_ulong scounteren; |
217 | target_ulong mcounteren; | |
dc5bd18f MC |
218 | |
219 | target_ulong sscratch; | |
220 | target_ulong mscratch; | |
221 | ||
222 | /* temporary htif regs */ | |
223 | uint64_t mfromhost; | |
224 | uint64_t mtohost; | |
225 | uint64_t timecmp; | |
226 | ||
227 | /* physical memory protection */ | |
228 | pmp_table_t pmp_state; | |
753e3fe2 | 229 | |
c6957248 | 230 | /* machine specific rdtime callback */ |
a47ef6e9 BM |
231 | uint64_t (*rdtime_fn)(uint32_t); |
232 | uint32_t rdtime_fn_arg; | |
c6957248 | 233 | |
753e3fe2 JW |
234 | /* True if in debugger mode. */ |
235 | bool debugger; | |
dc5bd18f MC |
236 | #endif |
237 | ||
238 | float_status fp_status; | |
239 | ||
dc5bd18f MC |
240 | /* Fields from here on are preserved across CPU reset. */ |
241 | QEMUTimer *timer; /* Internal timer */ | |
242 | }; | |
243 | ||
c821774a | 244 | OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass, |
30b5707c | 245 | RISCV_CPU) |
dc5bd18f MC |
246 | |
247 | /** | |
248 | * RISCVCPUClass: | |
249 | * @parent_realize: The parent class' realize handler. | |
250 | * @parent_reset: The parent class' reset handler. | |
251 | * | |
252 | * A RISCV CPU model. | |
253 | */ | |
db1015e9 | 254 | struct RISCVCPUClass { |
dc5bd18f MC |
255 | /*< private >*/ |
256 | CPUClass parent_class; | |
257 | /*< public >*/ | |
258 | DeviceRealize parent_realize; | |
781c67ca | 259 | DeviceReset parent_reset; |
db1015e9 | 260 | }; |
dc5bd18f MC |
261 | |
262 | /** | |
263 | * RISCVCPU: | |
264 | * @env: #CPURISCVState | |
265 | * | |
266 | * A RISCV CPU. | |
267 | */ | |
db1015e9 | 268 | struct RISCVCPU { |
dc5bd18f MC |
269 | /*< private >*/ |
270 | CPUState parent_obj; | |
271 | /*< public >*/ | |
5b146dc7 | 272 | CPUNegativeOffsetState neg; |
dc5bd18f | 273 | CPURISCVState env; |
c4e95030 AF |
274 | |
275 | /* Configuration Settings */ | |
276 | struct { | |
b55d7d34 AF |
277 | bool ext_i; |
278 | bool ext_e; | |
279 | bool ext_g; | |
280 | bool ext_m; | |
281 | bool ext_a; | |
282 | bool ext_f; | |
283 | bool ext_d; | |
284 | bool ext_c; | |
285 | bool ext_s; | |
286 | bool ext_u; | |
c9eefe05 | 287 | bool ext_h; |
6bf91617 | 288 | bool ext_v; |
0a13a5b8 | 289 | bool ext_counters; |
50fba816 | 290 | bool ext_ifencei; |
591bddea | 291 | bool ext_icsr; |
b55d7d34 | 292 | |
c4e95030 AF |
293 | char *priv_spec; |
294 | char *user_spec; | |
6bf91617 | 295 | char *vext_spec; |
32931383 LZ |
296 | uint16_t vlen; |
297 | uint16_t elen; | |
c4e95030 AF |
298 | bool mmu; |
299 | bool pmp; | |
9b4c9b2b | 300 | uint64_t resetvec; |
c4e95030 | 301 | } cfg; |
db1015e9 | 302 | }; |
dc5bd18f | 303 | |
dc5bd18f MC |
304 | static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) |
305 | { | |
306 | return (env->misa & ext) != 0; | |
307 | } | |
308 | ||
309 | static inline bool riscv_feature(CPURISCVState *env, int feature) | |
310 | { | |
311 | return env->features & (1ULL << feature); | |
312 | } | |
313 | ||
314 | #include "cpu_user.h" | |
315 | #include "cpu_bits.h" | |
316 | ||
317 | extern const char * const riscv_int_regnames[]; | |
318 | extern const char * const riscv_fpr_regnames[]; | |
319 | extern const char * const riscv_excp_names[]; | |
320 | extern const char * const riscv_intr_names[]; | |
321 | ||
c51a3f5d | 322 | const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); |
dc5bd18f | 323 | void riscv_cpu_do_interrupt(CPUState *cpu); |
a010bdbe | 324 | int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); |
dc5bd18f MC |
325 | int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); |
326 | bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); | |
b345b480 | 327 | bool riscv_cpu_fp_enabled(CPURISCVState *env); |
ef6bb7b6 AF |
328 | bool riscv_cpu_virt_enabled(CPURISCVState *env); |
329 | void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); | |
c7b1bbc8 AF |
330 | bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); |
331 | void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable); | |
1c1c060a | 332 | bool riscv_cpu_two_stage_lookup(int mmu_idx); |
dc5bd18f MC |
333 | int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); |
334 | hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); | |
335 | void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, | |
336 | MMUAccessType access_type, int mmu_idx, | |
337 | uintptr_t retaddr); | |
8a4ca3c1 RH |
338 | bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
339 | MMUAccessType access_type, int mmu_idx, | |
340 | bool probe, uintptr_t retaddr); | |
37207e12 PD |
341 | void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, |
342 | vaddr addr, unsigned size, | |
343 | MMUAccessType access_type, | |
344 | int mmu_idx, MemTxAttrs attrs, | |
345 | MemTxResult response, uintptr_t retaddr); | |
dc5bd18f | 346 | char *riscv_isa_string(RISCVCPU *cpu); |
0442428a | 347 | void riscv_cpu_list(void); |
dc5bd18f | 348 | |
fb738839 | 349 | #define cpu_signal_handler riscv_cpu_signal_handler |
dc5bd18f MC |
350 | #define cpu_list riscv_cpu_list |
351 | #define cpu_mmu_index riscv_cpu_mmu_index | |
352 | ||
85ba724f | 353 | #ifndef CONFIG_USER_ONLY |
66e594f2 | 354 | void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); |
e3e7039c | 355 | int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); |
85ba724f MC |
356 | uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); |
357 | #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ | |
a47ef6e9 BM |
358 | void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), |
359 | uint32_t arg); | |
85ba724f | 360 | #endif |
fb738839 | 361 | void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); |
dc5bd18f MC |
362 | |
363 | void riscv_translate_init(void); | |
fb738839 MC |
364 | int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc); |
365 | void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, | |
366 | uint32_t exception, uintptr_t pc); | |
dc5bd18f | 367 | |
fb738839 MC |
368 | target_ulong riscv_cpu_get_fflags(CPURISCVState *env); |
369 | void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); | |
dc5bd18f | 370 | |
c445593d AF |
371 | #define TB_FLAGS_MMU_MASK 7 |
372 | #define TB_FLAGS_PRIV_MMU_MASK 3 | |
373 | #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) | |
83a71719 | 374 | #define TB_FLAGS_MSTATUS_FS MSTATUS_FS |
dc5bd18f | 375 | |
2b7168fc LZ |
376 | typedef CPURISCVState CPUArchState; |
377 | typedef RISCVCPU ArchCPU; | |
378 | #include "exec/cpu-all.h" | |
379 | ||
380 | FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1) | |
381 | FIELD(TB_FLAGS, LMUL, 3, 2) | |
382 | FIELD(TB_FLAGS, SEW, 5, 3) | |
383 | FIELD(TB_FLAGS, VILL, 8, 1) | |
743077b3 AF |
384 | /* Is a Hypervisor instruction load/store allowed? */ |
385 | FIELD(TB_FLAGS, HLSX, 9, 1) | |
2b7168fc | 386 | |
51ae0cab AF |
387 | bool riscv_cpu_is_32bit(CPURISCVState *env); |
388 | ||
2b7168fc LZ |
389 | /* |
390 | * A simplification for VLMAX | |
391 | * = (1 << LMUL) * VLEN / (8 * (1 << SEW)) | |
392 | * = (VLEN << LMUL) / (8 << SEW) | |
393 | * = (VLEN << LMUL) >> (SEW + 3) | |
394 | * = VLEN >> (SEW + 3 - LMUL) | |
395 | */ | |
396 | static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) | |
397 | { | |
398 | uint8_t sew, lmul; | |
399 | ||
400 | sew = FIELD_EX64(vtype, VTYPE, VSEW); | |
401 | lmul = FIELD_EX64(vtype, VTYPE, VLMUL); | |
402 | return cpu->cfg.vlen >> (sew + 3 - lmul); | |
403 | } | |
404 | ||
dc5bd18f | 405 | static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, |
2b7168fc | 406 | target_ulong *cs_base, uint32_t *pflags) |
dc5bd18f | 407 | { |
2b7168fc LZ |
408 | uint32_t flags = 0; |
409 | ||
dc5bd18f MC |
410 | *pc = env->pc; |
411 | *cs_base = 0; | |
2b7168fc LZ |
412 | |
413 | if (riscv_has_ext(env, RVV)) { | |
414 | uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype); | |
415 | bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl); | |
416 | flags = FIELD_DP32(flags, TB_FLAGS, VILL, | |
417 | FIELD_EX64(env->vtype, VTYPE, VILL)); | |
418 | flags = FIELD_DP32(flags, TB_FLAGS, SEW, | |
419 | FIELD_EX64(env->vtype, VTYPE, VSEW)); | |
420 | flags = FIELD_DP32(flags, TB_FLAGS, LMUL, | |
421 | FIELD_EX64(env->vtype, VTYPE, VLMUL)); | |
422 | flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); | |
423 | } else { | |
424 | flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); | |
425 | } | |
426 | ||
dc5bd18f | 427 | #ifdef CONFIG_USER_ONLY |
2b7168fc | 428 | flags |= TB_FLAGS_MSTATUS_FS; |
dc5bd18f | 429 | #else |
2b7168fc | 430 | flags |= cpu_mmu_index(env, 0); |
e28eaed8 | 431 | if (riscv_cpu_fp_enabled(env)) { |
2b7168fc | 432 | flags |= env->mstatus & MSTATUS_FS; |
e28eaed8 | 433 | } |
743077b3 AF |
434 | |
435 | if (riscv_has_ext(env, RVH)) { | |
436 | if (env->priv == PRV_M || | |
437 | (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || | |
438 | (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && | |
439 | get_field(env->hstatus, HSTATUS_HU))) { | |
440 | flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); | |
441 | } | |
442 | } | |
dc5bd18f | 443 | #endif |
743077b3 | 444 | |
2b7168fc | 445 | *pflags = flags; |
dc5bd18f MC |
446 | } |
447 | ||
c7b95171 MC |
448 | int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, |
449 | target_ulong new_value, target_ulong write_mask); | |
753e3fe2 JW |
450 | int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value, |
451 | target_ulong new_value, target_ulong write_mask); | |
c7b95171 | 452 | |
fb738839 MC |
453 | static inline void riscv_csr_write(CPURISCVState *env, int csrno, |
454 | target_ulong val) | |
c7b95171 MC |
455 | { |
456 | riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); | |
457 | } | |
458 | ||
fb738839 | 459 | static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) |
c7b95171 MC |
460 | { |
461 | target_ulong val = 0; | |
462 | riscv_csrrw(env, csrno, &val, 0, 0); | |
463 | return val; | |
464 | } | |
465 | ||
466 | typedef int (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno); | |
467 | typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, | |
468 | target_ulong *ret_value); | |
469 | typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, | |
470 | target_ulong new_value); | |
471 | typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, | |
472 | target_ulong *ret_value, target_ulong new_value, target_ulong write_mask); | |
473 | ||
474 | typedef struct { | |
a88365c1 | 475 | riscv_csr_predicate_fn predicate; |
c7b95171 MC |
476 | riscv_csr_read_fn read; |
477 | riscv_csr_write_fn write; | |
478 | riscv_csr_op_fn op; | |
479 | } riscv_csr_operations; | |
480 | ||
481 | void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); | |
482 | void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); | |
dc5bd18f | 483 | |
5371f5cd JW |
484 | void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); |
485 | ||
dc5bd18f | 486 | #endif /* RISCV_CPU_H */ |