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dc5bd18f MC |
1 | /* |
2 | * QEMU RISC-V CPU | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #ifndef RISCV_CPU_H | |
21 | #define RISCV_CPU_H | |
22 | ||
2e5b09fd | 23 | #include "hw/core/cpu.h" |
2b7168fc | 24 | #include "hw/registerfields.h" |
dc5bd18f | 25 | #include "exec/cpu-defs.h" |
69242e7e | 26 | #include "qemu/cpu-float.h" |
db1015e9 | 27 | #include "qom/object.h" |
961738ff | 28 | #include "qemu/int128.h" |
e91a7227 | 29 | #include "cpu_bits.h" |
6f23aaeb | 30 | #include "qapi/qapi-types-common.h" |
dc5bd18f | 31 | |
74433bf0 RH |
32 | #define TCG_GUEST_DEFAULT_MO 0 |
33 | ||
62cf0245 AP |
34 | /* |
35 | * RISC-V-specific extra insn start words: | |
36 | * 1: Original instruction opcode | |
37 | */ | |
38 | #define TARGET_INSN_START_EXTRA_WORDS 1 | |
39 | ||
dc5bd18f MC |
40 | #define TYPE_RISCV_CPU "riscv-cpu" |
41 | ||
42 | #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU | |
43 | #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) | |
0dacec87 | 44 | #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU |
dc5bd18f MC |
45 | |
46 | #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") | |
8903bf6e AF |
47 | #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") |
48 | #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") | |
332dab68 | 49 | #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") |
36b80ad9 | 50 | #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") |
6ddc7069 | 51 | #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") |
dc5bd18f | 52 | #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") |
d784733b | 53 | #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") |
dc5bd18f MC |
54 | #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") |
55 | #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") | |
56 | #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") | |
95bd8daa | 57 | #define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") |
10f1ca27 | 58 | #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") |
dc5bd18f | 59 | |
c0a635f3 AF |
60 | #if defined(TARGET_RISCV32) |
61 | # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 | |
62 | #elif defined(TARGET_RISCV64) | |
63 | # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 | |
64 | #endif | |
65 | ||
dc5bd18f MC |
66 | #define RV(x) ((target_ulong)1 << (x - 'A')) |
67 | ||
c66ffcd5 DHB |
68 | /* |
69 | * Consider updating register_cpu_props() when adding | |
70 | * new MISA bits here. | |
71 | */ | |
dc5bd18f | 72 | #define RVI RV('I') |
79f86934 | 73 | #define RVE RV('E') /* E and I are mutually exclusive */ |
dc5bd18f MC |
74 | #define RVM RV('M') |
75 | #define RVA RV('A') | |
76 | #define RVF RV('F') | |
77 | #define RVD RV('D') | |
ad9e5aa2 | 78 | #define RVV RV('V') |
dc5bd18f MC |
79 | #define RVC RV('C') |
80 | #define RVS RV('S') | |
81 | #define RVU RV('U') | |
af1fa003 | 82 | #define RVH RV('H') |
53dcea58 | 83 | #define RVJ RV('J') |
dc5bd18f | 84 | |
dc5bd18f | 85 | |
a46d410c AP |
86 | /* Privileged specification version */ |
87 | enum { | |
88 | PRIV_VERSION_1_10_0 = 0, | |
89 | PRIV_VERSION_1_11_0, | |
3a4af26d | 90 | PRIV_VERSION_1_12_0, |
a46d410c | 91 | }; |
dc5bd18f | 92 | |
9ec6622d | 93 | #define VEXT_VERSION_1_00_0 0x00010000 |
32931383 | 94 | |
33a9a57d YJ |
95 | enum { |
96 | TRANSLATE_SUCCESS, | |
97 | TRANSLATE_FAIL, | |
98 | TRANSLATE_PMP_FAIL, | |
99 | TRANSLATE_G_STAGE_FAIL | |
100 | }; | |
101 | ||
dc5bd18f MC |
102 | #define MMU_USER_IDX 3 |
103 | ||
104 | #define MAX_RISCV_PMPS (16) | |
105 | ||
1ea4a06a | 106 | typedef struct CPUArchState CPURISCVState; |
dc5bd18f | 107 | |
bbf3d1b4 | 108 | #if !defined(CONFIG_USER_ONLY) |
dc5bd18f | 109 | #include "pmp.h" |
95799e36 | 110 | #include "debug.h" |
bbf3d1b4 | 111 | #endif |
dc5bd18f | 112 | |
8a4b5257 | 113 | #define RV_VLEN_MAX 1024 |
3780e337 | 114 | #define RV_MAX_MHPMEVENTS 32 |
621f35bb | 115 | #define RV_MAX_MHPMCOUNTERS 32 |
ad9e5aa2 | 116 | |
33f1beaf FC |
117 | FIELD(VTYPE, VLMUL, 0, 3) |
118 | FIELD(VTYPE, VSEW, 3, 3) | |
3479a814 FC |
119 | FIELD(VTYPE, VTA, 6, 1) |
120 | FIELD(VTYPE, VMA, 7, 1) | |
33f1beaf FC |
121 | FIELD(VTYPE, VEDIV, 8, 2) |
122 | FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) | |
2b7168fc | 123 | |
3780e337 AP |
124 | typedef struct PMUCTRState { |
125 | /* Current value of a counter */ | |
126 | target_ulong mhpmcounter_val; | |
3b57254d | 127 | /* Current value of a counter in RV32 */ |
3780e337 AP |
128 | target_ulong mhpmcounterh_val; |
129 | /* Snapshot values of counter */ | |
130 | target_ulong mhpmcounter_prev; | |
131 | /* Snapshort value of a counter in RV32 */ | |
132 | target_ulong mhpmcounterh_prev; | |
133 | bool started; | |
14664483 AP |
134 | /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */ |
135 | target_ulong irq_overflow_left; | |
3780e337 AP |
136 | } PMUCTRState; |
137 | ||
1ea4a06a | 138 | struct CPUArchState { |
dc5bd18f | 139 | target_ulong gpr[32]; |
2b547084 | 140 | target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ |
ad9e5aa2 LZ |
141 | |
142 | /* vector coprocessor state. */ | |
143 | uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); | |
144 | target_ulong vxrm; | |
145 | target_ulong vxsat; | |
146 | target_ulong vl; | |
147 | target_ulong vstart; | |
148 | target_ulong vtype; | |
d96a271a | 149 | bool vill; |
ad9e5aa2 | 150 | |
dc5bd18f MC |
151 | target_ulong pc; |
152 | target_ulong load_res; | |
153 | target_ulong load_val; | |
154 | ||
04bc3027 PMD |
155 | /* Floating-Point state */ |
156 | uint64_t fpr[32]; /* assume both F and D extensions */ | |
dc5bd18f | 157 | target_ulong frm; |
04bc3027 | 158 | float_status fp_status; |
dc5bd18f MC |
159 | |
160 | target_ulong badaddr; | |
62cf0245 | 161 | target_ulong bins; |
48eaeb56 | 162 | |
36a18664 | 163 | target_ulong guest_phys_fault_addr; |
dc5bd18f | 164 | |
dc5bd18f | 165 | target_ulong priv_ver; |
d2c1a177 | 166 | target_ulong bext_ver; |
32931383 | 167 | target_ulong vext_ver; |
e91a7227 RH |
168 | |
169 | /* RISCVMXL, but uint32_t for vmstate migration */ | |
170 | uint32_t misa_mxl; /* current mxl */ | |
171 | uint32_t misa_mxl_max; /* max mxl for this cpu */ | |
172 | uint32_t misa_ext; /* current extensions */ | |
173 | uint32_t misa_ext_mask; /* max ext for this cpu */ | |
440544e1 | 174 | uint32_t xl; /* current xlen */ |
dc5bd18f | 175 | |
b3a5d1fb FP |
176 | /* 128-bit helpers upper part return value */ |
177 | target_ulong retxh; | |
178 | ||
ce3af0bb WL |
179 | target_ulong jvt; |
180 | ||
5836c3ec KC |
181 | #ifdef CONFIG_USER_ONLY |
182 | uint32_t elf_flags; | |
183 | #endif | |
184 | ||
dc5bd18f MC |
185 | #ifndef CONFIG_USER_ONLY |
186 | target_ulong priv; | |
ef6bb7b6 | 187 | /* This contains QEMU specific information about the virt state. */ |
b3c5077b | 188 | bool virt_enabled; |
cd032fe7 | 189 | target_ulong geilen; |
277b210d | 190 | uint64_t resetvec; |
dc5bd18f MC |
191 | |
192 | target_ulong mhartid; | |
284d697c YJ |
193 | /* |
194 | * For RV32 this is 32-bit mstatus and 32-bit mstatush. | |
195 | * For RV64 this is a 64-bit mstatus. | |
196 | */ | |
197 | uint64_t mstatus; | |
85ba724f | 198 | |
d028ac75 | 199 | uint64_t mip; |
33fe584f AF |
200 | /* |
201 | * MIP contains the software writable version of SEIP ORed with the | |
202 | * external interrupt value. The MIP register is always up-to-date. | |
203 | * To keep track of the current source, we also save booleans of the values | |
204 | * here. | |
205 | */ | |
206 | bool external_seip; | |
207 | bool software_seip; | |
66e594f2 | 208 | |
d028ac75 | 209 | uint64_t miclaim; |
85ba724f | 210 | |
d028ac75 AP |
211 | uint64_t mie; |
212 | uint64_t mideleg; | |
dc5bd18f | 213 | |
dc5bd18f | 214 | target_ulong satp; /* since: priv-1.10.0 */ |
ac12b601 | 215 | target_ulong stval; |
dc5bd18f MC |
216 | target_ulong medeleg; |
217 | ||
218 | target_ulong stvec; | |
219 | target_ulong sepc; | |
220 | target_ulong scause; | |
221 | ||
222 | target_ulong mtvec; | |
223 | target_ulong mepc; | |
224 | target_ulong mcause; | |
225 | target_ulong mtval; /* since: priv-1.10.0 */ | |
226 | ||
43dc93af AP |
227 | /* Machine and Supervisor interrupt priorities */ |
228 | uint8_t miprio[64]; | |
229 | uint8_t siprio[64]; | |
230 | ||
d1ceff40 AP |
231 | /* AIA CSRs */ |
232 | target_ulong miselect; | |
233 | target_ulong siselect; | |
234 | ||
bd023ce3 AF |
235 | /* Hypervisor CSRs */ |
236 | target_ulong hstatus; | |
237 | target_ulong hedeleg; | |
d028ac75 | 238 | uint64_t hideleg; |
bd023ce3 AF |
239 | target_ulong hcounteren; |
240 | target_ulong htval; | |
241 | target_ulong htinst; | |
242 | target_ulong hgatp; | |
cd032fe7 AP |
243 | target_ulong hgeie; |
244 | target_ulong hgeip; | |
c6957248 | 245 | uint64_t htimedelta; |
bd023ce3 | 246 | |
43dc93af | 247 | /* Hypervisor controlled virtual interrupt priorities */ |
2b602398 | 248 | target_ulong hvictl; |
43dc93af AP |
249 | uint8_t hviprio[64]; |
250 | ||
2c64ab66 FP |
251 | /* Upper 64-bits of 128-bit CSRs */ |
252 | uint64_t mscratchh; | |
253 | uint64_t sscratchh; | |
254 | ||
bd023ce3 | 255 | /* Virtual CSRs */ |
284d697c YJ |
256 | /* |
257 | * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. | |
258 | * For RV64 this is a 64-bit vsstatus. | |
259 | */ | |
260 | uint64_t vsstatus; | |
bd023ce3 AF |
261 | target_ulong vstvec; |
262 | target_ulong vsscratch; | |
263 | target_ulong vsepc; | |
264 | target_ulong vscause; | |
265 | target_ulong vstval; | |
266 | target_ulong vsatp; | |
267 | ||
d1ceff40 AP |
268 | /* AIA VS-mode CSRs */ |
269 | target_ulong vsiselect; | |
270 | ||
bd023ce3 AF |
271 | target_ulong mtval2; |
272 | target_ulong mtinst; | |
273 | ||
66e594f2 AF |
274 | /* HS Backup CSRs */ |
275 | target_ulong stvec_hs; | |
276 | target_ulong sscratch_hs; | |
277 | target_ulong sepc_hs; | |
278 | target_ulong scause_hs; | |
279 | target_ulong stval_hs; | |
280 | target_ulong satp_hs; | |
284d697c | 281 | uint64_t mstatus_hs; |
66e594f2 | 282 | |
3b57254d WL |
283 | /* |
284 | * Signals whether the current exception occurred with two-stage address | |
285 | * translation active. | |
286 | */ | |
ec352d0c | 287 | bool two_stage_lookup; |
8e2aa21b AP |
288 | /* |
289 | * Signals whether the current exception occurred while doing two-stage | |
290 | * address translation for the VS-stage page table walk. | |
291 | */ | |
292 | bool two_stage_indirect_lookup; | |
ec352d0c | 293 | |
8c59f5c1 MC |
294 | target_ulong scounteren; |
295 | target_ulong mcounteren; | |
dc5bd18f | 296 | |
b1675eeb AP |
297 | target_ulong mcountinhibit; |
298 | ||
3780e337 AP |
299 | /* PMU counter state */ |
300 | PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; | |
621f35bb | 301 | |
3b57254d | 302 | /* PMU event selector configured values. First three are unused */ |
621f35bb AP |
303 | target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; |
304 | ||
3b57254d | 305 | /* PMU event selector configured values for RV32 */ |
14664483 AP |
306 | target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; |
307 | ||
dc5bd18f MC |
308 | target_ulong sscratch; |
309 | target_ulong mscratch; | |
310 | ||
43888c2f AP |
311 | /* Sstc CSRs */ |
312 | uint64_t stimecmp; | |
313 | ||
3ec0fe18 AP |
314 | uint64_t vstimecmp; |
315 | ||
dc5bd18f MC |
316 | /* physical memory protection */ |
317 | pmp_table_t pmp_state; | |
2582a95c | 318 | target_ulong mseccfg; |
753e3fe2 | 319 | |
95799e36 BM |
320 | /* trigger module */ |
321 | target_ulong trigger_cur; | |
9495c488 FC |
322 | target_ulong tdata1[RV_MAX_TRIGGERS]; |
323 | target_ulong tdata2[RV_MAX_TRIGGERS]; | |
324 | target_ulong tdata3[RV_MAX_TRIGGERS]; | |
325 | struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; | |
326 | struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; | |
5a4ae64c LZ |
327 | QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; |
328 | int64_t last_icount; | |
577f0286 | 329 | bool itrigger_enabled; |
95799e36 | 330 | |
c6957248 | 331 | /* machine specific rdtime callback */ |
e2f01f3c FC |
332 | uint64_t (*rdtime_fn)(void *); |
333 | void *rdtime_fn_arg; | |
c6957248 | 334 | |
69077dd6 AP |
335 | /* machine specific AIA ireg read-modify-write callback */ |
336 | #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ | |
337 | ((((__xlen) & 0xff) << 24) | \ | |
338 | (((__vgein) & 0x3f) << 20) | \ | |
339 | (((__virt) & 0x1) << 18) | \ | |
340 | (((__priv) & 0x3) << 16) | \ | |
341 | (__isel & 0xffff)) | |
342 | #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) | |
343 | #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) | |
344 | #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) | |
345 | #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) | |
346 | #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) | |
347 | int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, | |
348 | target_ulong *val, target_ulong new_val, target_ulong write_mask); | |
349 | void *aia_ireg_rmw_fn_arg[4]; | |
350 | ||
753e3fe2 JW |
351 | /* True if in debugger mode. */ |
352 | bool debugger; | |
4bbe8033 AB |
353 | |
354 | /* | |
355 | * CSRs for PointerMasking extension | |
356 | */ | |
357 | target_ulong mmte; | |
358 | target_ulong mpmmask; | |
359 | target_ulong mpmbase; | |
360 | target_ulong spmmask; | |
361 | target_ulong spmbase; | |
362 | target_ulong upmmask; | |
363 | target_ulong upmbase; | |
29a9ec9b AP |
364 | |
365 | /* CSRs for execution enviornment configuration */ | |
366 | uint64_t menvcfg; | |
3bee0e40 MC |
367 | uint64_t mstateen[SMSTATEEN_MAX_COUNT]; |
368 | uint64_t hstateen[SMSTATEEN_MAX_COUNT]; | |
369 | uint64_t sstateen[SMSTATEEN_MAX_COUNT]; | |
29a9ec9b AP |
370 | target_ulong senvcfg; |
371 | uint64_t henvcfg; | |
dc5bd18f | 372 | #endif |
40bfa5f6 LZ |
373 | target_ulong cur_pmmask; |
374 | target_ulong cur_pmbase; | |
dc5bd18f | 375 | |
dc5bd18f | 376 | /* Fields from here on are preserved across CPU reset. */ |
43888c2f | 377 | QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ |
3ec0fe18 AP |
378 | QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */ |
379 | bool vstime_irq; | |
ad40be27 YJ |
380 | |
381 | hwaddr kernel_addr; | |
382 | hwaddr fdt_addr; | |
27abe66f YJ |
383 | |
384 | /* kvm timer */ | |
385 | bool kvm_timer_dirty; | |
386 | uint64_t kvm_timer_time; | |
387 | uint64_t kvm_timer_compare; | |
388 | uint64_t kvm_timer_state; | |
389 | uint64_t kvm_timer_frequency; | |
dc5bd18f MC |
390 | }; |
391 | ||
9295b1aa | 392 | OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) |
dc5bd18f | 393 | |
3b57254d | 394 | /* |
dc5bd18f MC |
395 | * RISCVCPUClass: |
396 | * @parent_realize: The parent class' realize handler. | |
4fa485a7 | 397 | * @parent_phases: The parent class' reset phase handlers. |
dc5bd18f MC |
398 | * |
399 | * A RISCV CPU model. | |
400 | */ | |
db1015e9 | 401 | struct RISCVCPUClass { |
3b57254d | 402 | /* < private > */ |
dc5bd18f | 403 | CPUClass parent_class; |
3b57254d | 404 | /* < public > */ |
dc5bd18f | 405 | DeviceRealize parent_realize; |
4fa485a7 | 406 | ResettablePhases parent_phases; |
db1015e9 | 407 | }; |
dc5bd18f | 408 | |
6f23aaeb AG |
409 | /* |
410 | * map is a 16-bit bitmap: the most significant set bit in map is the maximum | |
6df3747a AG |
411 | * satp mode that is supported. It may be chosen by the user and must respect |
412 | * what qemu implements (valid_1_10_32/64) and what the hw is capable of | |
413 | * (supported bitmap below). | |
6f23aaeb AG |
414 | * |
415 | * init is a 16-bit bitmap used to make sure the user selected a correct | |
416 | * configuration as per the specification. | |
6df3747a AG |
417 | * |
418 | * supported is a 16-bit bitmap used to reflect the hw capabilities. | |
6f23aaeb AG |
419 | */ |
420 | typedef struct { | |
6df3747a | 421 | uint16_t map, init, supported; |
6f23aaeb AG |
422 | } RISCVSATPMap; |
423 | ||
466292bd PT |
424 | struct RISCVCPUConfig { |
425 | bool ext_i; | |
426 | bool ext_e; | |
427 | bool ext_g; | |
428 | bool ext_m; | |
429 | bool ext_a; | |
430 | bool ext_f; | |
431 | bool ext_d; | |
432 | bool ext_c; | |
433 | bool ext_s; | |
434 | bool ext_u; | |
435 | bool ext_h; | |
436 | bool ext_j; | |
437 | bool ext_v; | |
438 | bool ext_zba; | |
439 | bool ext_zbb; | |
440 | bool ext_zbc; | |
eef82872 WL |
441 | bool ext_zbkb; |
442 | bool ext_zbkc; | |
443 | bool ext_zbkx; | |
466292bd | 444 | bool ext_zbs; |
2288a5ce WL |
445 | bool ext_zca; |
446 | bool ext_zcb; | |
447 | bool ext_zcd; | |
00d312bd | 448 | bool ext_zce; |
2288a5ce WL |
449 | bool ext_zcf; |
450 | bool ext_zcmp; | |
451 | bool ext_zcmt; | |
eef82872 WL |
452 | bool ext_zk; |
453 | bool ext_zkn; | |
454 | bool ext_zknd; | |
455 | bool ext_zkne; | |
456 | bool ext_zknh; | |
457 | bool ext_zkr; | |
458 | bool ext_zks; | |
459 | bool ext_zksed; | |
460 | bool ext_zksh; | |
461 | bool ext_zkt; | |
466292bd PT |
462 | bool ext_ifencei; |
463 | bool ext_icsr; | |
e05da09b | 464 | bool ext_icbom; |
a939c500 | 465 | bool ext_icboz; |
b8e1f32c | 466 | bool ext_zicond; |
4696f0ab | 467 | bool ext_zihintpause; |
3bee0e40 | 468 | bool ext_smstateen; |
43888c2f | 469 | bool ext_sstc; |
0d190bd3 | 470 | bool ext_svadu; |
c5d77ddd | 471 | bool ext_svinval; |
05e6ca5e GR |
472 | bool ext_svnapot; |
473 | bool ext_svpbmt; | |
89ffdcec | 474 | bool ext_zdinx; |
260b594d | 475 | bool ext_zawrs; |
466292bd PT |
476 | bool ext_zfh; |
477 | bool ext_zfhmin; | |
89ffdcec WL |
478 | bool ext_zfinx; |
479 | bool ext_zhinx; | |
480 | bool ext_zhinxmin; | |
466292bd PT |
481 | bool ext_zve32f; |
482 | bool ext_zve64f; | |
a7336161 | 483 | bool ext_zve64d; |
de799beb | 484 | bool ext_zmmul; |
a7336161 WL |
485 | bool ext_zvfh; |
486 | bool ext_zvfhmin; | |
dc9acc9c AP |
487 | bool ext_smaia; |
488 | bool ext_ssaia; | |
14664483 | 489 | bool ext_sscofpmf; |
f1eed927 | 490 | bool rvv_ta_all_1s; |
355d5584 | 491 | bool rvv_ma_all_1s; |
466292bd | 492 | |
9951ba94 FC |
493 | uint32_t mvendorid; |
494 | uint64_t marchid; | |
075eeda9 | 495 | uint64_t mimpid; |
9951ba94 | 496 | |
0d429bd2 | 497 | /* Vendor-specific custom extensions */ |
c9410a68 | 498 | bool ext_xtheadba; |
426c0491 | 499 | bool ext_xtheadbb; |
fa134585 | 500 | bool ext_xtheadbs; |
49a7f3aa | 501 | bool ext_xtheadcmo; |
32909338 | 502 | bool ext_xtheadcondmov; |
d4d90115 | 503 | bool ext_xtheadfmemidx; |
578086ba | 504 | bool ext_xtheadfmv; |
b8a5832b | 505 | bool ext_xtheadmac; |
45f9df86 | 506 | bool ext_xtheadmemidx; |
af99aa72 | 507 | bool ext_xtheadmempair; |
134c3ffa | 508 | bool ext_xtheadsync; |
0d429bd2 PT |
509 | bool ext_XVentanaCondOps; |
510 | ||
18d6d89e | 511 | uint8_t pmu_num; |
466292bd PT |
512 | char *priv_spec; |
513 | char *user_spec; | |
514 | char *bext_spec; | |
515 | char *vext_spec; | |
516 | uint16_t vlen; | |
517 | uint16_t elen; | |
e05da09b | 518 | uint16_t cbom_blocksize; |
a939c500 | 519 | uint16_t cboz_blocksize; |
466292bd PT |
520 | bool mmu; |
521 | bool pmp; | |
522 | bool epmp; | |
1acdb3b0 | 523 | bool debug; |
54bd9b6e | 524 | bool misa_w; |
a4a9a443 TO |
525 | |
526 | bool short_isa_string; | |
6f23aaeb AG |
527 | |
528 | #ifndef CONFIG_USER_ONLY | |
529 | RISCVSATPMap satp_mode; | |
530 | #endif | |
466292bd PT |
531 | }; |
532 | ||
533 | typedef struct RISCVCPUConfig RISCVCPUConfig; | |
534 | ||
3b57254d | 535 | /* |
dc5bd18f MC |
536 | * RISCVCPU: |
537 | * @env: #CPURISCVState | |
538 | * | |
539 | * A RISCV CPU. | |
540 | */ | |
b36e239e | 541 | struct ArchCPU { |
3b57254d | 542 | /* < private > */ |
dc5bd18f | 543 | CPUState parent_obj; |
3b57254d | 544 | /* < public > */ |
5b146dc7 | 545 | CPUNegativeOffsetState neg; |
dc5bd18f | 546 | CPURISCVState env; |
c4e95030 | 547 | |
b93777e1 | 548 | char *dyn_csr_xml; |
719d3561 | 549 | char *dyn_vreg_xml; |
b93777e1 | 550 | |
c4e95030 | 551 | /* Configuration Settings */ |
466292bd | 552 | RISCVCPUConfig cfg; |
14664483 AP |
553 | |
554 | QEMUTimer *pmu_timer; | |
555 | /* A bitmask of Available programmable counters */ | |
556 | uint32_t pmu_avail_ctrs; | |
557 | /* Mapping of events to counters */ | |
558 | GHashTable *pmu_event_ctr_map; | |
db1015e9 | 559 | }; |
dc5bd18f | 560 | |
dc5bd18f MC |
561 | static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) |
562 | { | |
e91a7227 | 563 | return (env->misa_ext & ext) != 0; |
dc5bd18f MC |
564 | } |
565 | ||
dc5bd18f | 566 | #include "cpu_user.h" |
dc5bd18f MC |
567 | |
568 | extern const char * const riscv_int_regnames[]; | |
2b547084 | 569 | extern const char * const riscv_int_regnamesh[]; |
dc5bd18f | 570 | extern const char * const riscv_fpr_regnames[]; |
dc5bd18f | 571 | |
c51a3f5d | 572 | const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); |
dc5bd18f | 573 | void riscv_cpu_do_interrupt(CPUState *cpu); |
43a96588 | 574 | int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, |
1af0006a | 575 | int cpuid, DumpState *s); |
43a96588 | 576 | int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, |
1af0006a | 577 | int cpuid, DumpState *s); |
a010bdbe | 578 | int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); |
dc5bd18f | 579 | int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); |
43dc93af AP |
580 | int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); |
581 | uint8_t riscv_cpu_default_priority(int irq); | |
8f42415f | 582 | uint64_t riscv_cpu_all_pending(CPURISCVState *env); |
43dc93af AP |
583 | int riscv_cpu_mirq_pending(CPURISCVState *env); |
584 | int riscv_cpu_sirq_pending(CPURISCVState *env); | |
585 | int riscv_cpu_vsirq_pending(CPURISCVState *env); | |
b345b480 | 586 | bool riscv_cpu_fp_enabled(CPURISCVState *env); |
cd032fe7 AP |
587 | target_ulong riscv_cpu_get_geilen(CPURISCVState *env); |
588 | void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); | |
61b4b69d | 589 | bool riscv_cpu_vector_enabled(CPURISCVState *env); |
ef6bb7b6 | 590 | void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); |
1c1c060a | 591 | bool riscv_cpu_two_stage_lookup(int mmu_idx); |
dc5bd18f | 592 | int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); |
8905770b MAL |
593 | G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, |
594 | MMUAccessType access_type, int mmu_idx, | |
595 | uintptr_t retaddr); | |
8a4ca3c1 RH |
596 | bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
597 | MMUAccessType access_type, int mmu_idx, | |
598 | bool probe, uintptr_t retaddr); | |
dc5bd18f | 599 | char *riscv_isa_string(RISCVCPU *cpu); |
0442428a | 600 | void riscv_cpu_list(void); |
dc5bd18f | 601 | |
dc5bd18f MC |
602 | #define cpu_list riscv_cpu_list |
603 | #define cpu_mmu_index riscv_cpu_mmu_index | |
604 | ||
85ba724f | 605 | #ifndef CONFIG_USER_ONLY |
d90ebc47 PMD |
606 | void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, |
607 | vaddr addr, unsigned size, | |
608 | MMUAccessType access_type, | |
609 | int mmu_idx, MemTxAttrs attrs, | |
610 | MemTxResult response, uintptr_t retaddr); | |
6d2d454a | 611 | hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); |
17b3c353 | 612 | bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); |
66e594f2 | 613 | void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); |
d028ac75 | 614 | int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); |
bbb9fc25 WL |
615 | uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, |
616 | uint64_t value); | |
85ba724f | 617 | #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ |
e2f01f3c FC |
618 | void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), |
619 | void *arg); | |
69077dd6 AP |
620 | void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, |
621 | int (*rmw_fn)(void *arg, | |
622 | target_ulong reg, | |
623 | target_ulong *val, | |
624 | target_ulong new_val, | |
625 | target_ulong write_mask), | |
626 | void *rmw_fn_arg); | |
ce3af0bb WL |
627 | |
628 | RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit); | |
85ba724f | 629 | #endif |
fb738839 | 630 | void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); |
dc5bd18f MC |
631 | |
632 | void riscv_translate_init(void); | |
8905770b MAL |
633 | G_NORETURN void riscv_raise_exception(CPURISCVState *env, |
634 | uint32_t exception, uintptr_t pc); | |
dc5bd18f | 635 | |
fb738839 MC |
636 | target_ulong riscv_cpu_get_fflags(CPURISCVState *env); |
637 | void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); | |
dc5bd18f | 638 | |
c445593d AF |
639 | #define TB_FLAGS_PRIV_MMU_MASK 3 |
640 | #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) | |
83a71719 | 641 | #define TB_FLAGS_MSTATUS_FS MSTATUS_FS |
61b4b69d | 642 | #define TB_FLAGS_MSTATUS_VS MSTATUS_VS |
dc5bd18f | 643 | |
2b7168fc LZ |
644 | #include "exec/cpu-all.h" |
645 | ||
61d56494 | 646 | FIELD(TB_FLAGS, MEM_IDX, 0, 3) |
33f1beaf | 647 | FIELD(TB_FLAGS, LMUL, 3, 3) |
61d56494 | 648 | FIELD(TB_FLAGS, SEW, 6, 3) |
33f1beaf FC |
649 | /* Skip MSTATUS_VS (0x600) bits */ |
650 | FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) | |
651 | FIELD(TB_FLAGS, VILL, 12, 1) | |
652 | /* Skip MSTATUS_FS (0x6000) bits */ | |
743077b3 | 653 | /* Is a Hypervisor instruction load/store allowed? */ |
33f1beaf FC |
654 | FIELD(TB_FLAGS, HLSX, 15, 1) |
655 | FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) | |
656 | FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) | |
92371bd9 | 657 | /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ |
33f1beaf | 658 | FIELD(TB_FLAGS, XL, 20, 2) |
0774a7a1 | 659 | /* If PointerMasking should be applied */ |
4208dc7e LZ |
660 | FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1) |
661 | FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1) | |
f1eed927 | 662 | FIELD(TB_FLAGS, VTA, 24, 1) |
355d5584 | 663 | FIELD(TB_FLAGS, VMA, 25, 1) |
2c9d7471 LZ |
664 | /* Native debug itrigger */ |
665 | FIELD(TB_FLAGS, ITRIGGER, 26, 1) | |
2b7168fc | 666 | |
db23e5d9 RH |
667 | #ifdef TARGET_RISCV32 |
668 | #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) | |
669 | #else | |
670 | static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) | |
671 | { | |
672 | return env->misa_mxl; | |
673 | } | |
674 | #endif | |
2b602398 | 675 | #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) |
51ae0cab | 676 | |
d4ea7117 DHB |
677 | static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) |
678 | { | |
679 | return &env_archcpu(env)->cfg; | |
680 | } | |
681 | ||
440544e1 LZ |
682 | #if defined(TARGET_RISCV32) |
683 | #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) | |
684 | #else | |
685 | static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) | |
686 | { | |
687 | RISCVMXL xl = env->misa_mxl; | |
688 | #if !defined(CONFIG_USER_ONLY) | |
689 | /* | |
690 | * When emulating a 32-bit-only cpu, use RV32. | |
691 | * When emulating a 64-bit cpu, and MXL has been reduced to RV32, | |
692 | * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened | |
693 | * back to RV64 for lower privs. | |
694 | */ | |
695 | if (xl != MXL_RV32) { | |
696 | switch (env->priv) { | |
697 | case PRV_M: | |
698 | break; | |
699 | case PRV_U: | |
700 | xl = get_field(env->mstatus, MSTATUS64_UXL); | |
701 | break; | |
702 | default: /* PRV_S | PRV_H */ | |
703 | xl = get_field(env->mstatus, MSTATUS64_SXL); | |
704 | break; | |
705 | } | |
706 | } | |
707 | #endif | |
708 | return xl; | |
709 | } | |
710 | #endif | |
711 | ||
31961cfe LZ |
712 | static inline int riscv_cpu_xlen(CPURISCVState *env) |
713 | { | |
714 | return 16 << env->xl; | |
715 | } | |
716 | ||
05e6ca5e GR |
717 | #ifdef TARGET_RISCV32 |
718 | #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) | |
719 | #else | |
720 | static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) | |
721 | { | |
722 | #ifdef CONFIG_USER_ONLY | |
723 | return env->misa_mxl; | |
724 | #else | |
725 | return get_field(env->mstatus, MSTATUS64_SXL); | |
726 | #endif | |
727 | } | |
728 | #endif | |
729 | ||
2b7168fc | 730 | /* |
a689a82b FC |
731 | * Encode LMUL to lmul as follows: |
732 | * LMUL vlmul lmul | |
733 | * 1 000 0 | |
734 | * 2 001 1 | |
735 | * 4 010 2 | |
736 | * 8 011 3 | |
737 | * - 100 - | |
738 | * 1/8 101 -3 | |
739 | * 1/4 110 -2 | |
740 | * 1/2 111 -1 | |
741 | * | |
742 | * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) | |
743 | * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 | |
744 | * => VLMAX = vlen >> (1 + 3 - (-3)) | |
745 | * = 256 >> 7 | |
746 | * = 2 | |
2b7168fc LZ |
747 | */ |
748 | static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) | |
749 | { | |
a689a82b FC |
750 | uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); |
751 | int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); | |
2b7168fc LZ |
752 | return cpu->cfg.vlen >> (sew + 3 - lmul); |
753 | } | |
754 | ||
53677acf RH |
755 | void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, |
756 | target_ulong *cs_base, uint32_t *pflags); | |
dc5bd18f | 757 | |
40bfa5f6 LZ |
758 | void riscv_cpu_update_mask(CPURISCVState *env); |
759 | ||
533c91e8 AF |
760 | RISCVException riscv_csrrw(CPURISCVState *env, int csrno, |
761 | target_ulong *ret_value, | |
762 | target_ulong new_value, target_ulong write_mask); | |
763 | RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, | |
764 | target_ulong *ret_value, | |
765 | target_ulong new_value, | |
766 | target_ulong write_mask); | |
c7b95171 | 767 | |
fb738839 MC |
768 | static inline void riscv_csr_write(CPURISCVState *env, int csrno, |
769 | target_ulong val) | |
c7b95171 MC |
770 | { |
771 | riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); | |
772 | } | |
773 | ||
fb738839 | 774 | static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) |
c7b95171 MC |
775 | { |
776 | target_ulong val = 0; | |
777 | riscv_csrrw(env, csrno, &val, 0, 0); | |
778 | return val; | |
779 | } | |
780 | ||
0e62f92e AF |
781 | typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, |
782 | int csrno); | |
605def6e AF |
783 | typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, |
784 | target_ulong *ret_value); | |
785 | typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, | |
786 | target_ulong new_value); | |
787 | typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, | |
788 | target_ulong *ret_value, | |
789 | target_ulong new_value, | |
790 | target_ulong write_mask); | |
c7b95171 | 791 | |
961738ff FP |
792 | RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, |
793 | Int128 *ret_value, | |
794 | Int128 new_value, Int128 write_mask); | |
795 | ||
457c360f FP |
796 | typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, |
797 | Int128 *ret_value); | |
798 | typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, | |
799 | Int128 new_value); | |
800 | ||
c7b95171 | 801 | typedef struct { |
8ceac5dc | 802 | const char *name; |
a88365c1 | 803 | riscv_csr_predicate_fn predicate; |
c7b95171 MC |
804 | riscv_csr_read_fn read; |
805 | riscv_csr_write_fn write; | |
806 | riscv_csr_op_fn op; | |
457c360f FP |
807 | riscv_csr_read128_fn read128; |
808 | riscv_csr_write128_fn write128; | |
a4b2fa43 AP |
809 | /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ |
810 | uint32_t min_priv_ver; | |
c7b95171 MC |
811 | } riscv_csr_operations; |
812 | ||
56118ee8 BM |
813 | /* CSR function table constants */ |
814 | enum { | |
815 | CSR_TABLE_SIZE = 0x1000 | |
816 | }; | |
817 | ||
3b57254d | 818 | /* |
14664483 AP |
819 | * The event id are encoded based on the encoding specified in the |
820 | * SBI specification v0.3 | |
821 | */ | |
822 | ||
823 | enum riscv_pmu_event_idx { | |
824 | RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01, | |
825 | RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02, | |
826 | RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019, | |
827 | RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B, | |
828 | RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021, | |
829 | }; | |
830 | ||
56118ee8 | 831 | /* CSR function table */ |
6f03770d | 832 | extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; |
56118ee8 | 833 | |
6f23aaeb AG |
834 | extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; |
835 | ||
c7b95171 MC |
836 | void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); |
837 | void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); | |
dc5bd18f | 838 | |
5371f5cd JW |
839 | void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); |
840 | ||
6f23aaeb AG |
841 | uint8_t satp_mode_max_from_map(uint32_t map); |
842 | const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); | |
843 | ||
dc5bd18f | 844 | #endif /* RISCV_CPU_H */ |