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target/riscv: Implement AIA local interrupt priorities
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CommitLineData
dc5bd18f
MC
1/*
2 * QEMU RISC-V CPU
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#ifndef RISCV_CPU_H
21#define RISCV_CPU_H
22
2e5b09fd 23#include "hw/core/cpu.h"
2b7168fc 24#include "hw/registerfields.h"
dc5bd18f 25#include "exec/cpu-defs.h"
135b03cb 26#include "fpu/softfloat-types.h"
db1015e9 27#include "qom/object.h"
961738ff 28#include "qemu/int128.h"
e91a7227 29#include "cpu_bits.h"
dc5bd18f 30
74433bf0
RH
31#define TCG_GUEST_DEFAULT_MO 0
32
dc5bd18f
MC
33#define TYPE_RISCV_CPU "riscv-cpu"
34
35#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
36#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
0dacec87 37#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
dc5bd18f
MC
38
39#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
8903bf6e
AF
40#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
41#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
332dab68 42#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128")
36b80ad9 43#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
6ddc7069 44#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
dc5bd18f 45#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
d784733b 46#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
dc5bd18f
MC
47#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
48#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
49#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
10f1ca27 50#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
dc5bd18f 51
c0a635f3
AF
52#if defined(TARGET_RISCV32)
53# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32
54#elif defined(TARGET_RISCV64)
55# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64
56#endif
57
dc5bd18f
MC
58#define RV(x) ((target_ulong)1 << (x - 'A'))
59
60#define RVI RV('I')
79f86934 61#define RVE RV('E') /* E and I are mutually exclusive */
dc5bd18f
MC
62#define RVM RV('M')
63#define RVA RV('A')
64#define RVF RV('F')
65#define RVD RV('D')
ad9e5aa2 66#define RVV RV('V')
dc5bd18f
MC
67#define RVC RV('C')
68#define RVS RV('S')
69#define RVU RV('U')
af1fa003 70#define RVH RV('H')
53dcea58 71#define RVJ RV('J')
dc5bd18f
MC
72
73/* S extension denotes that Supervisor mode exists, however it is possible
74 to have a core that support S mode but does not have an MMU and there
75 is currently no bit in misa to indicate whether an MMU exists or not
a88365c1 76 so a cpu features bitfield is required, likewise for optional PMP support */
dc5bd18f 77enum {
a88365c1 78 RISCV_FEATURE_MMU,
f18637cd 79 RISCV_FEATURE_PMP,
4a345b2a 80 RISCV_FEATURE_EPMP,
32b0ada0
AP
81 RISCV_FEATURE_MISA,
82 RISCV_FEATURE_AIA
dc5bd18f
MC
83};
84
dc5bd18f 85#define PRIV_VERSION_1_10_0 0x00011000
6729dbbd 86#define PRIV_VERSION_1_11_0 0x00011100
dc5bd18f 87
9ec6622d 88#define VEXT_VERSION_1_00_0 0x00010000
32931383 89
33a9a57d
YJ
90enum {
91 TRANSLATE_SUCCESS,
92 TRANSLATE_FAIL,
93 TRANSLATE_PMP_FAIL,
94 TRANSLATE_G_STAGE_FAIL
95};
96
dc5bd18f
MC
97#define MMU_USER_IDX 3
98
99#define MAX_RISCV_PMPS (16)
100
101typedef struct CPURISCVState CPURISCVState;
102
bbf3d1b4 103#if !defined(CONFIG_USER_ONLY)
dc5bd18f 104#include "pmp.h"
bbf3d1b4 105#endif
dc5bd18f 106
8a4b5257 107#define RV_VLEN_MAX 1024
ad9e5aa2 108
33f1beaf
FC
109FIELD(VTYPE, VLMUL, 0, 3)
110FIELD(VTYPE, VSEW, 3, 3)
3479a814
FC
111FIELD(VTYPE, VTA, 6, 1)
112FIELD(VTYPE, VMA, 7, 1)
33f1beaf
FC
113FIELD(VTYPE, VEDIV, 8, 2)
114FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
2b7168fc 115
dc5bd18f
MC
116struct CPURISCVState {
117 target_ulong gpr[32];
2b547084 118 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */
dc5bd18f 119 uint64_t fpr[32]; /* assume both F and D extensions */
ad9e5aa2
LZ
120
121 /* vector coprocessor state. */
122 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16);
123 target_ulong vxrm;
124 target_ulong vxsat;
125 target_ulong vl;
126 target_ulong vstart;
127 target_ulong vtype;
d96a271a 128 bool vill;
ad9e5aa2 129
dc5bd18f
MC
130 target_ulong pc;
131 target_ulong load_res;
132 target_ulong load_val;
133
134 target_ulong frm;
135
136 target_ulong badaddr;
48eaeb56
AF
137 uint32_t bins;
138
36a18664 139 target_ulong guest_phys_fault_addr;
dc5bd18f 140
dc5bd18f 141 target_ulong priv_ver;
d2c1a177 142 target_ulong bext_ver;
32931383 143 target_ulong vext_ver;
e91a7227
RH
144
145 /* RISCVMXL, but uint32_t for vmstate migration */
146 uint32_t misa_mxl; /* current mxl */
147 uint32_t misa_mxl_max; /* max mxl for this cpu */
148 uint32_t misa_ext; /* current extensions */
149 uint32_t misa_ext_mask; /* max ext for this cpu */
440544e1 150 uint32_t xl; /* current xlen */
dc5bd18f 151
b3a5d1fb
FP
152 /* 128-bit helpers upper part return value */
153 target_ulong retxh;
154
dc5bd18f
MC
155 uint32_t features;
156
5836c3ec
KC
157#ifdef CONFIG_USER_ONLY
158 uint32_t elf_flags;
159#endif
160
dc5bd18f
MC
161#ifndef CONFIG_USER_ONLY
162 target_ulong priv;
ef6bb7b6
AF
163 /* This contains QEMU specific information about the virt state. */
164 target_ulong virt;
cd032fe7 165 target_ulong geilen;
dc5bd18f
MC
166 target_ulong resetvec;
167
168 target_ulong mhartid;
284d697c
YJ
169 /*
170 * For RV32 this is 32-bit mstatus and 32-bit mstatush.
171 * For RV64 this is a 64-bit mstatus.
172 */
173 uint64_t mstatus;
85ba724f 174
02861613 175 target_ulong mip;
66e594f2 176
e3e7039c 177 uint32_t miclaim;
85ba724f 178
dc5bd18f
MC
179 target_ulong mie;
180 target_ulong mideleg;
181
dc5bd18f 182 target_ulong satp; /* since: priv-1.10.0 */
ac12b601 183 target_ulong stval;
dc5bd18f
MC
184 target_ulong medeleg;
185
186 target_ulong stvec;
187 target_ulong sepc;
188 target_ulong scause;
189
190 target_ulong mtvec;
191 target_ulong mepc;
192 target_ulong mcause;
193 target_ulong mtval; /* since: priv-1.10.0 */
194
43dc93af
AP
195 /* Machine and Supervisor interrupt priorities */
196 uint8_t miprio[64];
197 uint8_t siprio[64];
198
bd023ce3
AF
199 /* Hypervisor CSRs */
200 target_ulong hstatus;
201 target_ulong hedeleg;
202 target_ulong hideleg;
203 target_ulong hcounteren;
204 target_ulong htval;
205 target_ulong htinst;
206 target_ulong hgatp;
cd032fe7
AP
207 target_ulong hgeie;
208 target_ulong hgeip;
c6957248 209 uint64_t htimedelta;
bd023ce3 210
43dc93af
AP
211 /* Hypervisor controlled virtual interrupt priorities */
212 uint8_t hviprio[64];
213
2c64ab66
FP
214 /* Upper 64-bits of 128-bit CSRs */
215 uint64_t mscratchh;
216 uint64_t sscratchh;
217
bd023ce3 218 /* Virtual CSRs */
284d697c
YJ
219 /*
220 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush.
221 * For RV64 this is a 64-bit vsstatus.
222 */
223 uint64_t vsstatus;
bd023ce3
AF
224 target_ulong vstvec;
225 target_ulong vsscratch;
226 target_ulong vsepc;
227 target_ulong vscause;
228 target_ulong vstval;
229 target_ulong vsatp;
230
231 target_ulong mtval2;
232 target_ulong mtinst;
233
66e594f2
AF
234 /* HS Backup CSRs */
235 target_ulong stvec_hs;
236 target_ulong sscratch_hs;
237 target_ulong sepc_hs;
238 target_ulong scause_hs;
239 target_ulong stval_hs;
240 target_ulong satp_hs;
284d697c 241 uint64_t mstatus_hs;
66e594f2 242
ec352d0c
GK
243 /* Signals whether the current exception occurred with two-stage address
244 translation active. */
245 bool two_stage_lookup;
246
8c59f5c1
MC
247 target_ulong scounteren;
248 target_ulong mcounteren;
dc5bd18f
MC
249
250 target_ulong sscratch;
251 target_ulong mscratch;
252
253 /* temporary htif regs */
254 uint64_t mfromhost;
255 uint64_t mtohost;
256 uint64_t timecmp;
257
258 /* physical memory protection */
259 pmp_table_t pmp_state;
2582a95c 260 target_ulong mseccfg;
753e3fe2 261
c6957248 262 /* machine specific rdtime callback */
a47ef6e9
BM
263 uint64_t (*rdtime_fn)(uint32_t);
264 uint32_t rdtime_fn_arg;
c6957248 265
69077dd6
AP
266 /* machine specific AIA ireg read-modify-write callback */
267#define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \
268 ((((__xlen) & 0xff) << 24) | \
269 (((__vgein) & 0x3f) << 20) | \
270 (((__virt) & 0x1) << 18) | \
271 (((__priv) & 0x3) << 16) | \
272 (__isel & 0xffff))
273#define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff)
274#define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3)
275#define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1)
276#define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f)
277#define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff)
278 int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg,
279 target_ulong *val, target_ulong new_val, target_ulong write_mask);
280 void *aia_ireg_rmw_fn_arg[4];
281
753e3fe2
JW
282 /* True if in debugger mode. */
283 bool debugger;
4bbe8033
AB
284
285 /*
286 * CSRs for PointerMasking extension
287 */
288 target_ulong mmte;
289 target_ulong mpmmask;
290 target_ulong mpmbase;
291 target_ulong spmmask;
292 target_ulong spmbase;
293 target_ulong upmmask;
294 target_ulong upmbase;
dc5bd18f 295#endif
40bfa5f6
LZ
296 target_ulong cur_pmmask;
297 target_ulong cur_pmbase;
dc5bd18f
MC
298
299 float_status fp_status;
300
dc5bd18f
MC
301 /* Fields from here on are preserved across CPU reset. */
302 QEMUTimer *timer; /* Internal timer */
ad40be27
YJ
303
304 hwaddr kernel_addr;
305 hwaddr fdt_addr;
27abe66f
YJ
306
307 /* kvm timer */
308 bool kvm_timer_dirty;
309 uint64_t kvm_timer_time;
310 uint64_t kvm_timer_compare;
311 uint64_t kvm_timer_state;
312 uint64_t kvm_timer_frequency;
dc5bd18f
MC
313};
314
c821774a 315OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass,
30b5707c 316 RISCV_CPU)
dc5bd18f
MC
317
318/**
319 * RISCVCPUClass:
320 * @parent_realize: The parent class' realize handler.
321 * @parent_reset: The parent class' reset handler.
322 *
323 * A RISCV CPU model.
324 */
db1015e9 325struct RISCVCPUClass {
dc5bd18f
MC
326 /*< private >*/
327 CPUClass parent_class;
328 /*< public >*/
329 DeviceRealize parent_realize;
781c67ca 330 DeviceReset parent_reset;
db1015e9 331};
dc5bd18f 332
466292bd
PT
333struct RISCVCPUConfig {
334 bool ext_i;
335 bool ext_e;
336 bool ext_g;
337 bool ext_m;
338 bool ext_a;
339 bool ext_f;
340 bool ext_d;
341 bool ext_c;
342 bool ext_s;
343 bool ext_u;
344 bool ext_h;
345 bool ext_j;
346 bool ext_v;
347 bool ext_zba;
348 bool ext_zbb;
349 bool ext_zbc;
350 bool ext_zbs;
351 bool ext_counters;
352 bool ext_ifencei;
353 bool ext_icsr;
354 bool ext_zfh;
355 bool ext_zfhmin;
356 bool ext_zve32f;
357 bool ext_zve64f;
358
0d429bd2
PT
359 /* Vendor-specific custom extensions */
360 bool ext_XVentanaCondOps;
361
466292bd
PT
362 char *priv_spec;
363 char *user_spec;
364 char *bext_spec;
365 char *vext_spec;
366 uint16_t vlen;
367 uint16_t elen;
368 bool mmu;
369 bool pmp;
370 bool epmp;
371 uint64_t resetvec;
372};
373
374typedef struct RISCVCPUConfig RISCVCPUConfig;
375
dc5bd18f
MC
376/**
377 * RISCVCPU:
378 * @env: #CPURISCVState
379 *
380 * A RISCV CPU.
381 */
db1015e9 382struct RISCVCPU {
dc5bd18f
MC
383 /*< private >*/
384 CPUState parent_obj;
385 /*< public >*/
5b146dc7 386 CPUNegativeOffsetState neg;
dc5bd18f 387 CPURISCVState env;
c4e95030 388
b93777e1 389 char *dyn_csr_xml;
719d3561 390 char *dyn_vreg_xml;
b93777e1 391
c4e95030 392 /* Configuration Settings */
466292bd 393 RISCVCPUConfig cfg;
db1015e9 394};
dc5bd18f 395
dc5bd18f
MC
396static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
397{
e91a7227 398 return (env->misa_ext & ext) != 0;
dc5bd18f
MC
399}
400
401static inline bool riscv_feature(CPURISCVState *env, int feature)
402{
403 return env->features & (1ULL << feature);
404}
405
f87adf23
AP
406static inline void riscv_set_feature(CPURISCVState *env, int feature)
407{
408 env->features |= (1ULL << feature);
409}
410
dc5bd18f 411#include "cpu_user.h"
dc5bd18f
MC
412
413extern const char * const riscv_int_regnames[];
2b547084 414extern const char * const riscv_int_regnamesh[];
dc5bd18f 415extern const char * const riscv_fpr_regnames[];
dc5bd18f 416
c51a3f5d 417const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);
dc5bd18f 418void riscv_cpu_do_interrupt(CPUState *cpu);
43a96588
YJ
419int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
420 int cpuid, void *opaque);
421int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
422 int cpuid, void *opaque);
a010bdbe 423int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
dc5bd18f 424int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
43dc93af
AP
425int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero);
426uint8_t riscv_cpu_default_priority(int irq);
427int riscv_cpu_mirq_pending(CPURISCVState *env);
428int riscv_cpu_sirq_pending(CPURISCVState *env);
429int riscv_cpu_vsirq_pending(CPURISCVState *env);
b345b480 430bool riscv_cpu_fp_enabled(CPURISCVState *env);
cd032fe7
AP
431target_ulong riscv_cpu_get_geilen(CPURISCVState *env);
432void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen);
61b4b69d 433bool riscv_cpu_vector_enabled(CPURISCVState *env);
ef6bb7b6
AF
434bool riscv_cpu_virt_enabled(CPURISCVState *env);
435void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
1c1c060a 436bool riscv_cpu_two_stage_lookup(int mmu_idx);
dc5bd18f
MC
437int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
438hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
439void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
440 MMUAccessType access_type, int mmu_idx,
fa947a66 441 uintptr_t retaddr) QEMU_NORETURN;
8a4ca3c1
RH
442bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
443 MMUAccessType access_type, int mmu_idx,
444 bool probe, uintptr_t retaddr);
37207e12
PD
445void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
446 vaddr addr, unsigned size,
447 MMUAccessType access_type,
448 int mmu_idx, MemTxAttrs attrs,
449 MemTxResult response, uintptr_t retaddr);
dc5bd18f 450char *riscv_isa_string(RISCVCPU *cpu);
0442428a 451void riscv_cpu_list(void);
dc5bd18f 452
dc5bd18f
MC
453#define cpu_list riscv_cpu_list
454#define cpu_mmu_index riscv_cpu_mmu_index
455
85ba724f 456#ifndef CONFIG_USER_ONLY
17b3c353 457bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
66e594f2 458void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
e3e7039c 459int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts);
85ba724f
MC
460uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
461#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
a47ef6e9
BM
462void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
463 uint32_t arg);
69077dd6
AP
464void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
465 int (*rmw_fn)(void *arg,
466 target_ulong reg,
467 target_ulong *val,
468 target_ulong new_val,
469 target_ulong write_mask),
470 void *rmw_fn_arg);
85ba724f 471#endif
fb738839 472void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
dc5bd18f
MC
473
474void riscv_translate_init(void);
fb738839
MC
475void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
476 uint32_t exception, uintptr_t pc);
dc5bd18f 477
fb738839
MC
478target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
479void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
dc5bd18f 480
c445593d
AF
481#define TB_FLAGS_PRIV_MMU_MASK 3
482#define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2)
83a71719 483#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
61b4b69d 484#define TB_FLAGS_MSTATUS_VS MSTATUS_VS
dc5bd18f 485
2b7168fc
LZ
486typedef CPURISCVState CPUArchState;
487typedef RISCVCPU ArchCPU;
488#include "exec/cpu-all.h"
489
61d56494 490FIELD(TB_FLAGS, MEM_IDX, 0, 3)
33f1beaf 491FIELD(TB_FLAGS, LMUL, 3, 3)
61d56494 492FIELD(TB_FLAGS, SEW, 6, 3)
33f1beaf
FC
493/* Skip MSTATUS_VS (0x600) bits */
494FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1)
495FIELD(TB_FLAGS, VILL, 12, 1)
496/* Skip MSTATUS_FS (0x6000) bits */
743077b3 497/* Is a Hypervisor instruction load/store allowed? */
33f1beaf
FC
498FIELD(TB_FLAGS, HLSX, 15, 1)
499FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2)
500FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2)
92371bd9 501/* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
33f1beaf 502FIELD(TB_FLAGS, XL, 20, 2)
0774a7a1 503/* If PointerMasking should be applied */
4208dc7e
LZ
504FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1)
505FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1)
2b7168fc 506
db23e5d9
RH
507#ifdef TARGET_RISCV32
508#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
509#else
510static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
511{
512 return env->misa_mxl;
513}
514#endif
51ae0cab 515
440544e1
LZ
516#if defined(TARGET_RISCV32)
517#define cpu_recompute_xl(env) ((void)(env), MXL_RV32)
518#else
519static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env)
520{
521 RISCVMXL xl = env->misa_mxl;
522#if !defined(CONFIG_USER_ONLY)
523 /*
524 * When emulating a 32-bit-only cpu, use RV32.
525 * When emulating a 64-bit cpu, and MXL has been reduced to RV32,
526 * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened
527 * back to RV64 for lower privs.
528 */
529 if (xl != MXL_RV32) {
530 switch (env->priv) {
531 case PRV_M:
532 break;
533 case PRV_U:
534 xl = get_field(env->mstatus, MSTATUS64_UXL);
535 break;
536 default: /* PRV_S | PRV_H */
537 xl = get_field(env->mstatus, MSTATUS64_SXL);
538 break;
539 }
540 }
541#endif
542 return xl;
543}
544#endif
545
31961cfe
LZ
546static inline int riscv_cpu_xlen(CPURISCVState *env)
547{
548 return 16 << env->xl;
549}
550
2b7168fc 551/*
a689a82b
FC
552 * Encode LMUL to lmul as follows:
553 * LMUL vlmul lmul
554 * 1 000 0
555 * 2 001 1
556 * 4 010 2
557 * 8 011 3
558 * - 100 -
559 * 1/8 101 -3
560 * 1/4 110 -2
561 * 1/2 111 -1
562 *
563 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul)
564 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8
565 * => VLMAX = vlen >> (1 + 3 - (-3))
566 * = 256 >> 7
567 * = 2
2b7168fc
LZ
568 */
569static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
570{
a689a82b
FC
571 uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW);
572 int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3);
2b7168fc
LZ
573 return cpu->cfg.vlen >> (sew + 3 - lmul);
574}
575
53677acf
RH
576void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
577 target_ulong *cs_base, uint32_t *pflags);
dc5bd18f 578
40bfa5f6
LZ
579void riscv_cpu_update_mask(CPURISCVState *env);
580
533c91e8
AF
581RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
582 target_ulong *ret_value,
583 target_ulong new_value, target_ulong write_mask);
584RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
585 target_ulong *ret_value,
586 target_ulong new_value,
587 target_ulong write_mask);
c7b95171 588
fb738839
MC
589static inline void riscv_csr_write(CPURISCVState *env, int csrno,
590 target_ulong val)
c7b95171
MC
591{
592 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
593}
594
fb738839 595static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
c7b95171
MC
596{
597 target_ulong val = 0;
598 riscv_csrrw(env, csrno, &val, 0, 0);
599 return val;
600}
601
0e62f92e
AF
602typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env,
603 int csrno);
605def6e
AF
604typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
605 target_ulong *ret_value);
606typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
607 target_ulong new_value);
608typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
609 target_ulong *ret_value,
610 target_ulong new_value,
611 target_ulong write_mask);
c7b95171 612
961738ff
FP
613RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
614 Int128 *ret_value,
615 Int128 new_value, Int128 write_mask);
616
457c360f
FP
617typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno,
618 Int128 *ret_value);
619typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno,
620 Int128 new_value);
621
c7b95171 622typedef struct {
8ceac5dc 623 const char *name;
a88365c1 624 riscv_csr_predicate_fn predicate;
c7b95171
MC
625 riscv_csr_read_fn read;
626 riscv_csr_write_fn write;
627 riscv_csr_op_fn op;
457c360f
FP
628 riscv_csr_read128_fn read128;
629 riscv_csr_write128_fn write128;
c7b95171
MC
630} riscv_csr_operations;
631
56118ee8
BM
632/* CSR function table constants */
633enum {
634 CSR_TABLE_SIZE = 0x1000
635};
636
637/* CSR function table */
6f03770d 638extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
56118ee8 639
c7b95171
MC
640void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
641void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
dc5bd18f 642
5371f5cd
JW
643void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
644
dc5bd18f 645#endif /* RISCV_CPU_H */