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dc5bd18f MC |
1 | /* |
2 | * QEMU RISC-V CPU | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #ifndef RISCV_CPU_H | |
21 | #define RISCV_CPU_H | |
22 | ||
2e5b09fd | 23 | #include "hw/core/cpu.h" |
2b7168fc | 24 | #include "hw/registerfields.h" |
32fa1776 | 25 | #include "hw/qdev-properties.h" |
dc5bd18f | 26 | #include "exec/cpu-defs.h" |
69242e7e | 27 | #include "qemu/cpu-float.h" |
db1015e9 | 28 | #include "qom/object.h" |
961738ff | 29 | #include "qemu/int128.h" |
e91a7227 | 30 | #include "cpu_bits.h" |
b902ff29 | 31 | #include "cpu_cfg.h" |
6f23aaeb | 32 | #include "qapi/qapi-types-common.h" |
85840bd2 | 33 | #include "cpu-qom.h" |
dc5bd18f | 34 | |
9348028e PMD |
35 | typedef struct CPUArchState CPURISCVState; |
36 | ||
66125f93 PMD |
37 | #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU |
38 | ||
27a6e78e PMD |
39 | #if defined(TARGET_RISCV32) |
40 | # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 | |
41 | #elif defined(TARGET_RISCV64) | |
42 | # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 | |
43 | #endif | |
44 | ||
74433bf0 RH |
45 | #define TCG_GUEST_DEFAULT_MO 0 |
46 | ||
62cf0245 AP |
47 | /* |
48 | * RISC-V-specific extra insn start words: | |
49 | * 1: Original instruction opcode | |
50 | */ | |
51 | #define TARGET_INSN_START_EXTRA_WORDS 1 | |
52 | ||
dc5bd18f MC |
53 | #define RV(x) ((target_ulong)1 << (x - 'A')) |
54 | ||
ed7e6182 | 55 | /* |
efa365b7 | 56 | * Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[] |
ed7e6182 DHB |
57 | * when adding new MISA bits here. |
58 | */ | |
dc5bd18f | 59 | #define RVI RV('I') |
79f86934 | 60 | #define RVE RV('E') /* E and I are mutually exclusive */ |
dc5bd18f MC |
61 | #define RVM RV('M') |
62 | #define RVA RV('A') | |
63 | #define RVF RV('F') | |
64 | #define RVD RV('D') | |
ad9e5aa2 | 65 | #define RVV RV('V') |
dc5bd18f MC |
66 | #define RVC RV('C') |
67 | #define RVS RV('S') | |
68 | #define RVU RV('U') | |
af1fa003 | 69 | #define RVH RV('H') |
53dcea58 | 70 | #define RVJ RV('J') |
4f13abcb | 71 | #define RVG RV('G') |
dc5bd18f | 72 | |
efa365b7 | 73 | extern const uint32_t misa_bits[]; |
ed7e6182 DHB |
74 | const char *riscv_get_misa_ext_name(uint32_t bit); |
75 | const char *riscv_get_misa_ext_description(uint32_t bit); | |
dc5bd18f | 76 | |
238fd586 DHB |
77 | #define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop) |
78 | ||
3f361847 DHB |
79 | typedef struct riscv_cpu_profile { |
80 | const char *name; | |
81 | uint32_t misa_ext; | |
82 | bool enabled; | |
83 | bool user_set; | |
84 | const int32_t ext_offsets[]; | |
85 | } RISCVCPUProfile; | |
86 | ||
87 | #define RISCV_PROFILE_EXT_LIST_END -1 | |
88 | ||
89 | extern RISCVCPUProfile *riscv_profiles[]; | |
90 | ||
a46d410c AP |
91 | /* Privileged specification version */ |
92 | enum { | |
93 | PRIV_VERSION_1_10_0 = 0, | |
94 | PRIV_VERSION_1_11_0, | |
3a4af26d | 95 | PRIV_VERSION_1_12_0, |
b9a2b98e DHB |
96 | |
97 | PRIV_VERSION_LATEST = PRIV_VERSION_1_12_0, | |
a46d410c | 98 | }; |
dc5bd18f | 99 | |
9ec6622d | 100 | #define VEXT_VERSION_1_00_0 0x00010000 |
32931383 | 101 | |
33a9a57d YJ |
102 | enum { |
103 | TRANSLATE_SUCCESS, | |
104 | TRANSLATE_FAIL, | |
105 | TRANSLATE_PMP_FAIL, | |
106 | TRANSLATE_G_STAGE_FAIL | |
107 | }; | |
108 | ||
42967f40 LZ |
109 | /* Extension context status */ |
110 | typedef enum { | |
111 | EXT_STATUS_DISABLED = 0, | |
112 | EXT_STATUS_INITIAL, | |
113 | EXT_STATUS_CLEAN, | |
114 | EXT_STATUS_DIRTY, | |
115 | } RISCVExtStatus; | |
116 | ||
dc5bd18f MC |
117 | #define MMU_USER_IDX 3 |
118 | ||
119 | #define MAX_RISCV_PMPS (16) | |
120 | ||
bbf3d1b4 | 121 | #if !defined(CONFIG_USER_ONLY) |
dc5bd18f | 122 | #include "pmp.h" |
95799e36 | 123 | #include "debug.h" |
bbf3d1b4 | 124 | #endif |
dc5bd18f | 125 | |
8a4b5257 | 126 | #define RV_VLEN_MAX 1024 |
3780e337 | 127 | #define RV_MAX_MHPMEVENTS 32 |
621f35bb | 128 | #define RV_MAX_MHPMCOUNTERS 32 |
ad9e5aa2 | 129 | |
33f1beaf FC |
130 | FIELD(VTYPE, VLMUL, 0, 3) |
131 | FIELD(VTYPE, VSEW, 3, 3) | |
3479a814 FC |
132 | FIELD(VTYPE, VTA, 6, 1) |
133 | FIELD(VTYPE, VMA, 7, 1) | |
33f1beaf FC |
134 | FIELD(VTYPE, VEDIV, 8, 2) |
135 | FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) | |
2b7168fc | 136 | |
3780e337 AP |
137 | typedef struct PMUCTRState { |
138 | /* Current value of a counter */ | |
139 | target_ulong mhpmcounter_val; | |
3b57254d | 140 | /* Current value of a counter in RV32 */ |
3780e337 AP |
141 | target_ulong mhpmcounterh_val; |
142 | /* Snapshot values of counter */ | |
143 | target_ulong mhpmcounter_prev; | |
144 | /* Snapshort value of a counter in RV32 */ | |
145 | target_ulong mhpmcounterh_prev; | |
146 | bool started; | |
14664483 AP |
147 | /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */ |
148 | target_ulong irq_overflow_left; | |
3780e337 AP |
149 | } PMUCTRState; |
150 | ||
1ea4a06a | 151 | struct CPUArchState { |
dc5bd18f | 152 | target_ulong gpr[32]; |
2b547084 | 153 | target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ |
ad9e5aa2 LZ |
154 | |
155 | /* vector coprocessor state. */ | |
156 | uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); | |
157 | target_ulong vxrm; | |
158 | target_ulong vxsat; | |
159 | target_ulong vl; | |
160 | target_ulong vstart; | |
161 | target_ulong vtype; | |
d96a271a | 162 | bool vill; |
ad9e5aa2 | 163 | |
dc5bd18f MC |
164 | target_ulong pc; |
165 | target_ulong load_res; | |
166 | target_ulong load_val; | |
167 | ||
04bc3027 PMD |
168 | /* Floating-Point state */ |
169 | uint64_t fpr[32]; /* assume both F and D extensions */ | |
dc5bd18f | 170 | target_ulong frm; |
04bc3027 | 171 | float_status fp_status; |
dc5bd18f MC |
172 | |
173 | target_ulong badaddr; | |
62cf0245 | 174 | target_ulong bins; |
48eaeb56 | 175 | |
36a18664 | 176 | target_ulong guest_phys_fault_addr; |
dc5bd18f | 177 | |
dc5bd18f | 178 | target_ulong priv_ver; |
d2c1a177 | 179 | target_ulong bext_ver; |
32931383 | 180 | target_ulong vext_ver; |
e91a7227 RH |
181 | |
182 | /* RISCVMXL, but uint32_t for vmstate migration */ | |
183 | uint32_t misa_mxl; /* current mxl */ | |
184 | uint32_t misa_mxl_max; /* max mxl for this cpu */ | |
185 | uint32_t misa_ext; /* current extensions */ | |
186 | uint32_t misa_ext_mask; /* max ext for this cpu */ | |
440544e1 | 187 | uint32_t xl; /* current xlen */ |
dc5bd18f | 188 | |
b3a5d1fb FP |
189 | /* 128-bit helpers upper part return value */ |
190 | target_ulong retxh; | |
191 | ||
ce3af0bb WL |
192 | target_ulong jvt; |
193 | ||
5836c3ec KC |
194 | #ifdef CONFIG_USER_ONLY |
195 | uint32_t elf_flags; | |
196 | #endif | |
197 | ||
dc5bd18f MC |
198 | #ifndef CONFIG_USER_ONLY |
199 | target_ulong priv; | |
ef6bb7b6 | 200 | /* This contains QEMU specific information about the virt state. */ |
b3c5077b | 201 | bool virt_enabled; |
cd032fe7 | 202 | target_ulong geilen; |
277b210d | 203 | uint64_t resetvec; |
dc5bd18f MC |
204 | |
205 | target_ulong mhartid; | |
284d697c YJ |
206 | /* |
207 | * For RV32 this is 32-bit mstatus and 32-bit mstatush. | |
208 | * For RV64 this is a 64-bit mstatus. | |
209 | */ | |
210 | uint64_t mstatus; | |
85ba724f | 211 | |
d028ac75 | 212 | uint64_t mip; |
33fe584f AF |
213 | /* |
214 | * MIP contains the software writable version of SEIP ORed with the | |
215 | * external interrupt value. The MIP register is always up-to-date. | |
216 | * To keep track of the current source, we also save booleans of the values | |
217 | * here. | |
218 | */ | |
219 | bool external_seip; | |
220 | bool software_seip; | |
66e594f2 | 221 | |
d028ac75 | 222 | uint64_t miclaim; |
85ba724f | 223 | |
d028ac75 AP |
224 | uint64_t mie; |
225 | uint64_t mideleg; | |
dc5bd18f | 226 | |
1697837e RK |
227 | /* |
228 | * When mideleg[i]=0 and mvien[i]=1, sie[i] is no more | |
3a4e5601 | 229 | * alias of mie[i] and needs to be maintained separately. |
1697837e RK |
230 | */ |
231 | uint64_t sie; | |
232 | ||
40336d5b RK |
233 | /* |
234 | * When hideleg[i]=0 and hvien[i]=1, vsie[i] is no more | |
3a4e5601 | 235 | * alias of sie[i] (mie[i]) and needs to be maintained separately. |
40336d5b RK |
236 | */ |
237 | uint64_t vsie; | |
238 | ||
dc5bd18f | 239 | target_ulong satp; /* since: priv-1.10.0 */ |
ac12b601 | 240 | target_ulong stval; |
dc5bd18f MC |
241 | target_ulong medeleg; |
242 | ||
243 | target_ulong stvec; | |
244 | target_ulong sepc; | |
245 | target_ulong scause; | |
246 | ||
247 | target_ulong mtvec; | |
248 | target_ulong mepc; | |
249 | target_ulong mcause; | |
250 | target_ulong mtval; /* since: priv-1.10.0 */ | |
251 | ||
43dc93af AP |
252 | /* Machine and Supervisor interrupt priorities */ |
253 | uint8_t miprio[64]; | |
254 | uint8_t siprio[64]; | |
255 | ||
d1ceff40 AP |
256 | /* AIA CSRs */ |
257 | target_ulong miselect; | |
258 | target_ulong siselect; | |
1697837e RK |
259 | uint64_t mvien; |
260 | uint64_t mvip; | |
d1ceff40 | 261 | |
bd023ce3 AF |
262 | /* Hypervisor CSRs */ |
263 | target_ulong hstatus; | |
264 | target_ulong hedeleg; | |
d028ac75 | 265 | uint64_t hideleg; |
bd023ce3 AF |
266 | target_ulong hcounteren; |
267 | target_ulong htval; | |
268 | target_ulong htinst; | |
269 | target_ulong hgatp; | |
cd032fe7 AP |
270 | target_ulong hgeie; |
271 | target_ulong hgeip; | |
c6957248 | 272 | uint64_t htimedelta; |
40336d5b RK |
273 | uint64_t hvien; |
274 | ||
275 | /* | |
276 | * Bits VSSIP, VSTIP and VSEIP in hvip are maintained in mip. Other bits | |
277 | * from 0:12 are reserved. Bits 13:63 are not aliased and must be separately | |
278 | * maintain in hvip. | |
279 | */ | |
280 | uint64_t hvip; | |
bd023ce3 | 281 | |
43dc93af | 282 | /* Hypervisor controlled virtual interrupt priorities */ |
2b602398 | 283 | target_ulong hvictl; |
43dc93af AP |
284 | uint8_t hviprio[64]; |
285 | ||
2c64ab66 FP |
286 | /* Upper 64-bits of 128-bit CSRs */ |
287 | uint64_t mscratchh; | |
288 | uint64_t sscratchh; | |
289 | ||
bd023ce3 | 290 | /* Virtual CSRs */ |
284d697c YJ |
291 | /* |
292 | * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. | |
293 | * For RV64 this is a 64-bit vsstatus. | |
294 | */ | |
295 | uint64_t vsstatus; | |
bd023ce3 AF |
296 | target_ulong vstvec; |
297 | target_ulong vsscratch; | |
298 | target_ulong vsepc; | |
299 | target_ulong vscause; | |
300 | target_ulong vstval; | |
301 | target_ulong vsatp; | |
302 | ||
d1ceff40 AP |
303 | /* AIA VS-mode CSRs */ |
304 | target_ulong vsiselect; | |
305 | ||
bd023ce3 AF |
306 | target_ulong mtval2; |
307 | target_ulong mtinst; | |
308 | ||
66e594f2 AF |
309 | /* HS Backup CSRs */ |
310 | target_ulong stvec_hs; | |
311 | target_ulong sscratch_hs; | |
312 | target_ulong sepc_hs; | |
313 | target_ulong scause_hs; | |
314 | target_ulong stval_hs; | |
315 | target_ulong satp_hs; | |
284d697c | 316 | uint64_t mstatus_hs; |
66e594f2 | 317 | |
3b57254d WL |
318 | /* |
319 | * Signals whether the current exception occurred with two-stage address | |
320 | * translation active. | |
321 | */ | |
ec352d0c | 322 | bool two_stage_lookup; |
8e2aa21b AP |
323 | /* |
324 | * Signals whether the current exception occurred while doing two-stage | |
325 | * address translation for the VS-stage page table walk. | |
326 | */ | |
327 | bool two_stage_indirect_lookup; | |
ec352d0c | 328 | |
8c59f5c1 MC |
329 | target_ulong scounteren; |
330 | target_ulong mcounteren; | |
dc5bd18f | 331 | |
b1675eeb AP |
332 | target_ulong mcountinhibit; |
333 | ||
3780e337 AP |
334 | /* PMU counter state */ |
335 | PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; | |
621f35bb | 336 | |
3b57254d | 337 | /* PMU event selector configured values. First three are unused */ |
621f35bb AP |
338 | target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; |
339 | ||
3b57254d | 340 | /* PMU event selector configured values for RV32 */ |
14664483 AP |
341 | target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; |
342 | ||
dc5bd18f MC |
343 | target_ulong sscratch; |
344 | target_ulong mscratch; | |
345 | ||
43888c2f AP |
346 | /* Sstc CSRs */ |
347 | uint64_t stimecmp; | |
348 | ||
3ec0fe18 AP |
349 | uint64_t vstimecmp; |
350 | ||
dc5bd18f MC |
351 | /* physical memory protection */ |
352 | pmp_table_t pmp_state; | |
2582a95c | 353 | target_ulong mseccfg; |
753e3fe2 | 354 | |
95799e36 BM |
355 | /* trigger module */ |
356 | target_ulong trigger_cur; | |
9495c488 FC |
357 | target_ulong tdata1[RV_MAX_TRIGGERS]; |
358 | target_ulong tdata2[RV_MAX_TRIGGERS]; | |
359 | target_ulong tdata3[RV_MAX_TRIGGERS]; | |
360 | struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; | |
361 | struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; | |
5a4ae64c LZ |
362 | QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; |
363 | int64_t last_icount; | |
577f0286 | 364 | bool itrigger_enabled; |
95799e36 | 365 | |
c6957248 | 366 | /* machine specific rdtime callback */ |
e2f01f3c FC |
367 | uint64_t (*rdtime_fn)(void *); |
368 | void *rdtime_fn_arg; | |
c6957248 | 369 | |
69077dd6 AP |
370 | /* machine specific AIA ireg read-modify-write callback */ |
371 | #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ | |
372 | ((((__xlen) & 0xff) << 24) | \ | |
373 | (((__vgein) & 0x3f) << 20) | \ | |
374 | (((__virt) & 0x1) << 18) | \ | |
375 | (((__priv) & 0x3) << 16) | \ | |
376 | (__isel & 0xffff)) | |
377 | #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) | |
378 | #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) | |
379 | #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) | |
380 | #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) | |
381 | #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) | |
382 | int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, | |
383 | target_ulong *val, target_ulong new_val, target_ulong write_mask); | |
384 | void *aia_ireg_rmw_fn_arg[4]; | |
385 | ||
753e3fe2 JW |
386 | /* True if in debugger mode. */ |
387 | bool debugger; | |
4bbe8033 AB |
388 | |
389 | /* | |
390 | * CSRs for PointerMasking extension | |
391 | */ | |
392 | target_ulong mmte; | |
393 | target_ulong mpmmask; | |
394 | target_ulong mpmbase; | |
395 | target_ulong spmmask; | |
396 | target_ulong spmbase; | |
397 | target_ulong upmmask; | |
398 | target_ulong upmbase; | |
29a9ec9b | 399 | |
42fe7499 | 400 | /* CSRs for execution environment configuration */ |
29a9ec9b | 401 | uint64_t menvcfg; |
3bee0e40 MC |
402 | uint64_t mstateen[SMSTATEEN_MAX_COUNT]; |
403 | uint64_t hstateen[SMSTATEEN_MAX_COUNT]; | |
404 | uint64_t sstateen[SMSTATEEN_MAX_COUNT]; | |
29a9ec9b AP |
405 | target_ulong senvcfg; |
406 | uint64_t henvcfg; | |
dc5bd18f | 407 | #endif |
40bfa5f6 LZ |
408 | target_ulong cur_pmmask; |
409 | target_ulong cur_pmbase; | |
dc5bd18f | 410 | |
dc5bd18f | 411 | /* Fields from here on are preserved across CPU reset. */ |
43888c2f | 412 | QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ |
3ec0fe18 AP |
413 | QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */ |
414 | bool vstime_irq; | |
ad40be27 YJ |
415 | |
416 | hwaddr kernel_addr; | |
417 | hwaddr fdt_addr; | |
27abe66f | 418 | |
9638cbde | 419 | #ifdef CONFIG_KVM |
27abe66f YJ |
420 | /* kvm timer */ |
421 | bool kvm_timer_dirty; | |
422 | uint64_t kvm_timer_time; | |
423 | uint64_t kvm_timer_compare; | |
424 | uint64_t kvm_timer_state; | |
425 | uint64_t kvm_timer_frequency; | |
9638cbde | 426 | #endif /* CONFIG_KVM */ |
dc5bd18f MC |
427 | }; |
428 | ||
3b57254d | 429 | /* |
dc5bd18f MC |
430 | * RISCVCPU: |
431 | * @env: #CPURISCVState | |
432 | * | |
433 | * A RISCV CPU. | |
434 | */ | |
b36e239e | 435 | struct ArchCPU { |
dc5bd18f | 436 | CPUState parent_obj; |
3b3d7df5 | 437 | |
dc5bd18f | 438 | CPURISCVState env; |
c4e95030 | 439 | |
b93777e1 | 440 | char *dyn_csr_xml; |
719d3561 | 441 | char *dyn_vreg_xml; |
b93777e1 | 442 | |
c4e95030 | 443 | /* Configuration Settings */ |
466292bd | 444 | RISCVCPUConfig cfg; |
14664483 AP |
445 | |
446 | QEMUTimer *pmu_timer; | |
447 | /* A bitmask of Available programmable counters */ | |
448 | uint32_t pmu_avail_ctrs; | |
449 | /* Mapping of events to counters */ | |
450 | GHashTable *pmu_event_ctr_map; | |
db1015e9 | 451 | }; |
dc5bd18f | 452 | |
9348028e PMD |
453 | /** |
454 | * RISCVCPUClass: | |
455 | * @parent_realize: The parent class' realize handler. | |
456 | * @parent_phases: The parent class' reset phase handlers. | |
457 | * | |
458 | * A RISCV CPU model. | |
459 | */ | |
460 | struct RISCVCPUClass { | |
461 | CPUClass parent_class; | |
462 | ||
463 | DeviceRealize parent_realize; | |
464 | ResettablePhases parent_phases; | |
465 | }; | |
466 | ||
dc5bd18f MC |
467 | static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) |
468 | { | |
e91a7227 | 469 | return (env->misa_ext & ext) != 0; |
dc5bd18f MC |
470 | } |
471 | ||
dc5bd18f | 472 | #include "cpu_user.h" |
dc5bd18f MC |
473 | |
474 | extern const char * const riscv_int_regnames[]; | |
2b547084 | 475 | extern const char * const riscv_int_regnamesh[]; |
dc5bd18f | 476 | extern const char * const riscv_fpr_regnames[]; |
dc5bd18f | 477 | |
c51a3f5d | 478 | const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); |
dc5bd18f | 479 | void riscv_cpu_do_interrupt(CPUState *cpu); |
43a96588 | 480 | int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, |
1af0006a | 481 | int cpuid, DumpState *s); |
43a96588 | 482 | int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, |
1af0006a | 483 | int cpuid, DumpState *s); |
a010bdbe | 484 | int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); |
dc5bd18f | 485 | int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); |
43dc93af AP |
486 | int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); |
487 | uint8_t riscv_cpu_default_priority(int irq); | |
8f42415f | 488 | uint64_t riscv_cpu_all_pending(CPURISCVState *env); |
43dc93af AP |
489 | int riscv_cpu_mirq_pending(CPURISCVState *env); |
490 | int riscv_cpu_sirq_pending(CPURISCVState *env); | |
491 | int riscv_cpu_vsirq_pending(CPURISCVState *env); | |
b345b480 | 492 | bool riscv_cpu_fp_enabled(CPURISCVState *env); |
cd032fe7 AP |
493 | target_ulong riscv_cpu_get_geilen(CPURISCVState *env); |
494 | void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); | |
61b4b69d | 495 | bool riscv_cpu_vector_enabled(CPURISCVState *env); |
ef6bb7b6 | 496 | void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); |
dc5bd18f | 497 | int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); |
8905770b | 498 | G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, |
246f8796 WL |
499 | MMUAccessType access_type, |
500 | int mmu_idx, uintptr_t retaddr); | |
8a4ca3c1 RH |
501 | bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
502 | MMUAccessType access_type, int mmu_idx, | |
503 | bool probe, uintptr_t retaddr); | |
dc5bd18f | 504 | char *riscv_isa_string(RISCVCPU *cpu); |
dc5bd18f | 505 | |
dc5bd18f MC |
506 | #define cpu_mmu_index riscv_cpu_mmu_index |
507 | ||
85ba724f | 508 | #ifndef CONFIG_USER_ONLY |
d90ebc47 PMD |
509 | void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, |
510 | vaddr addr, unsigned size, | |
511 | MMUAccessType access_type, | |
512 | int mmu_idx, MemTxAttrs attrs, | |
513 | MemTxResult response, uintptr_t retaddr); | |
6d2d454a | 514 | hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); |
17b3c353 | 515 | bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); |
66e594f2 | 516 | void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); |
d028ac75 | 517 | int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); |
bbb9fc25 WL |
518 | uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, |
519 | uint64_t value); | |
1ebad505 | 520 | void riscv_cpu_interrupt(CPURISCVState *env); |
85ba724f | 521 | #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ |
e2f01f3c FC |
522 | void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), |
523 | void *arg); | |
69077dd6 AP |
524 | void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, |
525 | int (*rmw_fn)(void *arg, | |
526 | target_ulong reg, | |
527 | target_ulong *val, | |
528 | target_ulong new_val, | |
529 | target_ulong write_mask), | |
530 | void *rmw_fn_arg); | |
ce3af0bb WL |
531 | |
532 | RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit); | |
85ba724f | 533 | #endif |
fb738839 | 534 | void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); |
dc5bd18f MC |
535 | |
536 | void riscv_translate_init(void); | |
8905770b MAL |
537 | G_NORETURN void riscv_raise_exception(CPURISCVState *env, |
538 | uint32_t exception, uintptr_t pc); | |
dc5bd18f | 539 | |
fb738839 MC |
540 | target_ulong riscv_cpu_get_fflags(CPURISCVState *env); |
541 | void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); | |
dc5bd18f | 542 | |
2b7168fc LZ |
543 | #include "exec/cpu-all.h" |
544 | ||
61d56494 | 545 | FIELD(TB_FLAGS, MEM_IDX, 0, 3) |
ebd47648 LZ |
546 | FIELD(TB_FLAGS, FS, 3, 2) |
547 | /* Vector flags */ | |
548 | FIELD(TB_FLAGS, VS, 5, 2) | |
549 | FIELD(TB_FLAGS, LMUL, 7, 3) | |
550 | FIELD(TB_FLAGS, SEW, 10, 3) | |
551 | FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1) | |
552 | FIELD(TB_FLAGS, VILL, 14, 1) | |
0f58cbbe | 553 | FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1) |
92371bd9 | 554 | /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ |
25f3ddff | 555 | FIELD(TB_FLAGS, XL, 16, 2) |
0774a7a1 | 556 | /* If PointerMasking should be applied */ |
25f3ddff RH |
557 | FIELD(TB_FLAGS, PM_MASK_ENABLED, 18, 1) |
558 | FIELD(TB_FLAGS, PM_BASE_ENABLED, 19, 1) | |
559 | FIELD(TB_FLAGS, VTA, 20, 1) | |
560 | FIELD(TB_FLAGS, VMA, 21, 1) | |
2c9d7471 | 561 | /* Native debug itrigger */ |
25f3ddff | 562 | FIELD(TB_FLAGS, ITRIGGER, 22, 1) |
f1966390 | 563 | /* Virtual mode enabled */ |
25f3ddff | 564 | FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1) |
0f58cbbe | 565 | FIELD(TB_FLAGS, PRIV, 24, 2) |
3a610f54 | 566 | FIELD(TB_FLAGS, AXL, 26, 2) |
2b7168fc | 567 | |
db23e5d9 RH |
568 | #ifdef TARGET_RISCV32 |
569 | #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) | |
570 | #else | |
571 | static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) | |
572 | { | |
573 | return env->misa_mxl; | |
574 | } | |
575 | #endif | |
2b602398 | 576 | #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) |
51ae0cab | 577 | |
d4ea7117 DHB |
578 | static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) |
579 | { | |
580 | return &env_archcpu(env)->cfg; | |
581 | } | |
582 | ||
3a610f54 WL |
583 | #if !defined(CONFIG_USER_ONLY) |
584 | static inline int cpu_address_mode(CPURISCVState *env) | |
585 | { | |
586 | int mode = env->priv; | |
587 | ||
588 | if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) { | |
589 | mode = get_field(env->mstatus, MSTATUS_MPP); | |
590 | } | |
591 | return mode; | |
592 | } | |
593 | ||
594 | static inline RISCVMXL cpu_get_xl(CPURISCVState *env, target_ulong mode) | |
440544e1 LZ |
595 | { |
596 | RISCVMXL xl = env->misa_mxl; | |
440544e1 LZ |
597 | /* |
598 | * When emulating a 32-bit-only cpu, use RV32. | |
599 | * When emulating a 64-bit cpu, and MXL has been reduced to RV32, | |
600 | * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened | |
601 | * back to RV64 for lower privs. | |
602 | */ | |
603 | if (xl != MXL_RV32) { | |
3a610f54 | 604 | switch (mode) { |
440544e1 LZ |
605 | case PRV_M: |
606 | break; | |
607 | case PRV_U: | |
608 | xl = get_field(env->mstatus, MSTATUS64_UXL); | |
609 | break; | |
44b8f74b | 610 | default: /* PRV_S */ |
440544e1 LZ |
611 | xl = get_field(env->mstatus, MSTATUS64_SXL); |
612 | break; | |
613 | } | |
614 | } | |
440544e1 LZ |
615 | return xl; |
616 | } | |
617 | #endif | |
618 | ||
3a610f54 WL |
619 | #if defined(TARGET_RISCV32) |
620 | #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) | |
621 | #else | |
622 | static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) | |
623 | { | |
624 | #if !defined(CONFIG_USER_ONLY) | |
625 | return cpu_get_xl(env, env->priv); | |
626 | #else | |
627 | return env->misa_mxl; | |
628 | #endif | |
629 | } | |
630 | #endif | |
631 | ||
632 | #if defined(TARGET_RISCV32) | |
633 | #define cpu_address_xl(env) ((void)(env), MXL_RV32) | |
634 | #else | |
635 | static inline RISCVMXL cpu_address_xl(CPURISCVState *env) | |
636 | { | |
637 | #ifdef CONFIG_USER_ONLY | |
638 | return env->xl; | |
639 | #else | |
640 | int mode = cpu_address_mode(env); | |
641 | ||
642 | return cpu_get_xl(env, mode); | |
643 | #endif | |
644 | } | |
645 | #endif | |
646 | ||
31961cfe LZ |
647 | static inline int riscv_cpu_xlen(CPURISCVState *env) |
648 | { | |
649 | return 16 << env->xl; | |
650 | } | |
651 | ||
05e6ca5e GR |
652 | #ifdef TARGET_RISCV32 |
653 | #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) | |
654 | #else | |
655 | static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) | |
656 | { | |
657 | #ifdef CONFIG_USER_ONLY | |
658 | return env->misa_mxl; | |
659 | #else | |
660 | return get_field(env->mstatus, MSTATUS64_SXL); | |
661 | #endif | |
662 | } | |
663 | #endif | |
664 | ||
2b7168fc | 665 | /* |
a689a82b FC |
666 | * Encode LMUL to lmul as follows: |
667 | * LMUL vlmul lmul | |
668 | * 1 000 0 | |
669 | * 2 001 1 | |
670 | * 4 010 2 | |
671 | * 8 011 3 | |
672 | * - 100 - | |
673 | * 1/8 101 -3 | |
674 | * 1/4 110 -2 | |
675 | * 1/2 111 -1 | |
676 | * | |
677 | * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) | |
678 | * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 | |
679 | * => VLMAX = vlen >> (1 + 3 - (-3)) | |
680 | * = 256 >> 7 | |
681 | * = 2 | |
2b7168fc LZ |
682 | */ |
683 | static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) | |
684 | { | |
a689a82b FC |
685 | uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); |
686 | int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); | |
2b7168fc LZ |
687 | return cpu->cfg.vlen >> (sew + 3 - lmul); |
688 | } | |
689 | ||
bb5de525 AJ |
690 | void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, |
691 | uint64_t *cs_base, uint32_t *pflags); | |
dc5bd18f | 692 | |
40bfa5f6 LZ |
693 | void riscv_cpu_update_mask(CPURISCVState *env); |
694 | ||
533c91e8 AF |
695 | RISCVException riscv_csrrw(CPURISCVState *env, int csrno, |
696 | target_ulong *ret_value, | |
697 | target_ulong new_value, target_ulong write_mask); | |
698 | RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, | |
699 | target_ulong *ret_value, | |
700 | target_ulong new_value, | |
701 | target_ulong write_mask); | |
c7b95171 | 702 | |
fb738839 MC |
703 | static inline void riscv_csr_write(CPURISCVState *env, int csrno, |
704 | target_ulong val) | |
c7b95171 MC |
705 | { |
706 | riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); | |
707 | } | |
708 | ||
fb738839 | 709 | static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) |
c7b95171 MC |
710 | { |
711 | target_ulong val = 0; | |
712 | riscv_csrrw(env, csrno, &val, 0, 0); | |
713 | return val; | |
714 | } | |
715 | ||
0e62f92e AF |
716 | typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, |
717 | int csrno); | |
605def6e AF |
718 | typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, |
719 | target_ulong *ret_value); | |
720 | typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, | |
721 | target_ulong new_value); | |
722 | typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, | |
723 | target_ulong *ret_value, | |
724 | target_ulong new_value, | |
725 | target_ulong write_mask); | |
c7b95171 | 726 | |
961738ff FP |
727 | RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, |
728 | Int128 *ret_value, | |
729 | Int128 new_value, Int128 write_mask); | |
730 | ||
457c360f FP |
731 | typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, |
732 | Int128 *ret_value); | |
733 | typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, | |
734 | Int128 new_value); | |
735 | ||
c7b95171 | 736 | typedef struct { |
8ceac5dc | 737 | const char *name; |
a88365c1 | 738 | riscv_csr_predicate_fn predicate; |
c7b95171 MC |
739 | riscv_csr_read_fn read; |
740 | riscv_csr_write_fn write; | |
741 | riscv_csr_op_fn op; | |
457c360f FP |
742 | riscv_csr_read128_fn read128; |
743 | riscv_csr_write128_fn write128; | |
a4b2fa43 AP |
744 | /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ |
745 | uint32_t min_priv_ver; | |
c7b95171 MC |
746 | } riscv_csr_operations; |
747 | ||
56118ee8 BM |
748 | /* CSR function table constants */ |
749 | enum { | |
750 | CSR_TABLE_SIZE = 0x1000 | |
751 | }; | |
752 | ||
3b57254d | 753 | /* |
14664483 AP |
754 | * The event id are encoded based on the encoding specified in the |
755 | * SBI specification v0.3 | |
756 | */ | |
757 | ||
758 | enum riscv_pmu_event_idx { | |
759 | RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01, | |
760 | RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02, | |
761 | RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019, | |
762 | RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B, | |
763 | RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021, | |
764 | }; | |
765 | ||
36c1118d DHB |
766 | /* used by tcg/tcg-cpu.c*/ |
767 | void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); | |
36c1118d | 768 | bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); |
f51d03b0 | 769 | void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext); |
36c1118d | 770 | |
32fa1776 DHB |
771 | typedef struct RISCVCPUMultiExtConfig { |
772 | const char *name; | |
773 | uint32_t offset; | |
774 | bool enabled; | |
775 | } RISCVCPUMultiExtConfig; | |
776 | ||
777 | extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[]; | |
778 | extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[]; | |
779 | extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; | |
5fe2800b | 780 | extern const RISCVCPUMultiExtConfig riscv_cpu_named_features[]; |
8043effd | 781 | extern const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[]; |
32fa1776 DHB |
782 | extern Property riscv_cpu_options[]; |
783 | ||
7935e2c4 DHB |
784 | typedef struct isa_ext_data { |
785 | const char *name; | |
786 | int min_version; | |
787 | int ext_enable_offset; | |
788 | } RISCVIsaExtData; | |
789 | extern const RISCVIsaExtData isa_edata_arr[]; | |
b933720b | 790 | char *riscv_cpu_get_name(RISCVCPU *cpu); |
7935e2c4 | 791 | |
a13a6082 | 792 | void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp); |
7d0c302c | 793 | void riscv_add_satp_mode_properties(Object *obj); |
ef58fad0 | 794 | bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu); |
32fa1776 | 795 | |
56118ee8 | 796 | /* CSR function table */ |
6f03770d | 797 | extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; |
56118ee8 | 798 | |
6f23aaeb AG |
799 | extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; |
800 | ||
c7b95171 MC |
801 | void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); |
802 | void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); | |
dc5bd18f | 803 | |
5371f5cd JW |
804 | void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); |
805 | ||
6f23aaeb AG |
806 | uint8_t satp_mode_max_from_map(uint32_t map); |
807 | const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); | |
808 | ||
dc5bd18f | 809 | #endif /* RISCV_CPU_H */ |