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dc5bd18f MC |
1 | /* |
2 | * QEMU RISC-V CPU | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #ifndef RISCV_CPU_H | |
21 | #define RISCV_CPU_H | |
22 | ||
2e5b09fd | 23 | #include "hw/core/cpu.h" |
2b7168fc | 24 | #include "hw/registerfields.h" |
dc5bd18f | 25 | #include "exec/cpu-defs.h" |
135b03cb | 26 | #include "fpu/softfloat-types.h" |
db1015e9 | 27 | #include "qom/object.h" |
dc5bd18f | 28 | |
74433bf0 RH |
29 | #define TCG_GUEST_DEFAULT_MO 0 |
30 | ||
dc5bd18f MC |
31 | #define TYPE_RISCV_CPU "riscv-cpu" |
32 | ||
33 | #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU | |
34 | #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) | |
0dacec87 | 35 | #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU |
dc5bd18f MC |
36 | |
37 | #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") | |
8903bf6e AF |
38 | #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") |
39 | #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") | |
36b80ad9 | 40 | #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") |
6ddc7069 | 41 | #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") |
dc5bd18f | 42 | #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") |
d784733b | 43 | #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") |
dc5bd18f MC |
44 | #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") |
45 | #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") | |
46 | #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") | |
47 | ||
c0a635f3 AF |
48 | #if defined(TARGET_RISCV32) |
49 | # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 | |
50 | #elif defined(TARGET_RISCV64) | |
51 | # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 | |
52 | #endif | |
53 | ||
dc5bd18f MC |
54 | #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) |
55 | #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) | |
56 | ||
57 | #if defined(TARGET_RISCV32) | |
58 | #define RVXLEN RV32 | |
59 | #elif defined(TARGET_RISCV64) | |
60 | #define RVXLEN RV64 | |
61 | #endif | |
62 | ||
63 | #define RV(x) ((target_ulong)1 << (x - 'A')) | |
64 | ||
65 | #define RVI RV('I') | |
79f86934 | 66 | #define RVE RV('E') /* E and I are mutually exclusive */ |
dc5bd18f MC |
67 | #define RVM RV('M') |
68 | #define RVA RV('A') | |
69 | #define RVF RV('F') | |
70 | #define RVD RV('D') | |
ad9e5aa2 | 71 | #define RVV RV('V') |
dc5bd18f MC |
72 | #define RVC RV('C') |
73 | #define RVS RV('S') | |
74 | #define RVU RV('U') | |
af1fa003 | 75 | #define RVH RV('H') |
dc5bd18f MC |
76 | |
77 | /* S extension denotes that Supervisor mode exists, however it is possible | |
78 | to have a core that support S mode but does not have an MMU and there | |
79 | is currently no bit in misa to indicate whether an MMU exists or not | |
a88365c1 | 80 | so a cpu features bitfield is required, likewise for optional PMP support */ |
dc5bd18f | 81 | enum { |
a88365c1 | 82 | RISCV_FEATURE_MMU, |
f18637cd MC |
83 | RISCV_FEATURE_PMP, |
84 | RISCV_FEATURE_MISA | |
dc5bd18f MC |
85 | }; |
86 | ||
dc5bd18f | 87 | #define PRIV_VERSION_1_10_0 0x00011000 |
6729dbbd | 88 | #define PRIV_VERSION_1_11_0 0x00011100 |
dc5bd18f | 89 | |
32931383 LZ |
90 | #define VEXT_VERSION_0_07_1 0x00000701 |
91 | ||
33a9a57d YJ |
92 | enum { |
93 | TRANSLATE_SUCCESS, | |
94 | TRANSLATE_FAIL, | |
95 | TRANSLATE_PMP_FAIL, | |
96 | TRANSLATE_G_STAGE_FAIL | |
97 | }; | |
98 | ||
dc5bd18f MC |
99 | #define MMU_USER_IDX 3 |
100 | ||
101 | #define MAX_RISCV_PMPS (16) | |
102 | ||
103 | typedef struct CPURISCVState CPURISCVState; | |
104 | ||
105 | #include "pmp.h" | |
106 | ||
6bf91617 | 107 | #define RV_VLEN_MAX 256 |
ad9e5aa2 | 108 | |
2b7168fc LZ |
109 | FIELD(VTYPE, VLMUL, 0, 2) |
110 | FIELD(VTYPE, VSEW, 2, 3) | |
111 | FIELD(VTYPE, VEDIV, 5, 2) | |
112 | FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9) | |
fbcbafa2 | 113 | FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) |
2b7168fc | 114 | |
dc5bd18f MC |
115 | struct CPURISCVState { |
116 | target_ulong gpr[32]; | |
117 | uint64_t fpr[32]; /* assume both F and D extensions */ | |
ad9e5aa2 LZ |
118 | |
119 | /* vector coprocessor state. */ | |
120 | uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); | |
121 | target_ulong vxrm; | |
122 | target_ulong vxsat; | |
123 | target_ulong vl; | |
124 | target_ulong vstart; | |
125 | target_ulong vtype; | |
126 | ||
dc5bd18f MC |
127 | target_ulong pc; |
128 | target_ulong load_res; | |
129 | target_ulong load_val; | |
130 | ||
131 | target_ulong frm; | |
132 | ||
133 | target_ulong badaddr; | |
36a18664 | 134 | target_ulong guest_phys_fault_addr; |
dc5bd18f | 135 | |
dc5bd18f | 136 | target_ulong priv_ver; |
32931383 | 137 | target_ulong vext_ver; |
dc5bd18f | 138 | target_ulong misa; |
f18637cd | 139 | target_ulong misa_mask; |
dc5bd18f MC |
140 | |
141 | uint32_t features; | |
142 | ||
5836c3ec KC |
143 | #ifdef CONFIG_USER_ONLY |
144 | uint32_t elf_flags; | |
145 | #endif | |
146 | ||
dc5bd18f MC |
147 | #ifndef CONFIG_USER_ONLY |
148 | target_ulong priv; | |
ef6bb7b6 AF |
149 | /* This contains QEMU specific information about the virt state. */ |
150 | target_ulong virt; | |
dc5bd18f MC |
151 | target_ulong resetvec; |
152 | ||
153 | target_ulong mhartid; | |
284d697c YJ |
154 | /* |
155 | * For RV32 this is 32-bit mstatus and 32-bit mstatush. | |
156 | * For RV64 this is a 64-bit mstatus. | |
157 | */ | |
158 | uint64_t mstatus; | |
85ba724f | 159 | |
02861613 | 160 | target_ulong mip; |
66e594f2 | 161 | |
e3e7039c | 162 | uint32_t miclaim; |
85ba724f | 163 | |
dc5bd18f MC |
164 | target_ulong mie; |
165 | target_ulong mideleg; | |
166 | ||
dc5bd18f | 167 | target_ulong satp; /* since: priv-1.10.0 */ |
ac12b601 | 168 | target_ulong stval; |
dc5bd18f MC |
169 | target_ulong medeleg; |
170 | ||
171 | target_ulong stvec; | |
172 | target_ulong sepc; | |
173 | target_ulong scause; | |
174 | ||
175 | target_ulong mtvec; | |
176 | target_ulong mepc; | |
177 | target_ulong mcause; | |
178 | target_ulong mtval; /* since: priv-1.10.0 */ | |
179 | ||
bd023ce3 AF |
180 | /* Hypervisor CSRs */ |
181 | target_ulong hstatus; | |
182 | target_ulong hedeleg; | |
183 | target_ulong hideleg; | |
184 | target_ulong hcounteren; | |
185 | target_ulong htval; | |
186 | target_ulong htinst; | |
187 | target_ulong hgatp; | |
c6957248 | 188 | uint64_t htimedelta; |
bd023ce3 AF |
189 | |
190 | /* Virtual CSRs */ | |
284d697c YJ |
191 | /* |
192 | * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. | |
193 | * For RV64 this is a 64-bit vsstatus. | |
194 | */ | |
195 | uint64_t vsstatus; | |
bd023ce3 AF |
196 | target_ulong vstvec; |
197 | target_ulong vsscratch; | |
198 | target_ulong vsepc; | |
199 | target_ulong vscause; | |
200 | target_ulong vstval; | |
201 | target_ulong vsatp; | |
202 | ||
203 | target_ulong mtval2; | |
204 | target_ulong mtinst; | |
205 | ||
66e594f2 AF |
206 | /* HS Backup CSRs */ |
207 | target_ulong stvec_hs; | |
208 | target_ulong sscratch_hs; | |
209 | target_ulong sepc_hs; | |
210 | target_ulong scause_hs; | |
211 | target_ulong stval_hs; | |
212 | target_ulong satp_hs; | |
284d697c | 213 | uint64_t mstatus_hs; |
66e594f2 | 214 | |
ec352d0c GK |
215 | /* Signals whether the current exception occurred with two-stage address |
216 | translation active. */ | |
217 | bool two_stage_lookup; | |
218 | ||
8c59f5c1 MC |
219 | target_ulong scounteren; |
220 | target_ulong mcounteren; | |
dc5bd18f MC |
221 | |
222 | target_ulong sscratch; | |
223 | target_ulong mscratch; | |
224 | ||
225 | /* temporary htif regs */ | |
226 | uint64_t mfromhost; | |
227 | uint64_t mtohost; | |
228 | uint64_t timecmp; | |
229 | ||
230 | /* physical memory protection */ | |
231 | pmp_table_t pmp_state; | |
753e3fe2 | 232 | |
c6957248 | 233 | /* machine specific rdtime callback */ |
a47ef6e9 BM |
234 | uint64_t (*rdtime_fn)(uint32_t); |
235 | uint32_t rdtime_fn_arg; | |
c6957248 | 236 | |
753e3fe2 JW |
237 | /* True if in debugger mode. */ |
238 | bool debugger; | |
dc5bd18f MC |
239 | #endif |
240 | ||
241 | float_status fp_status; | |
242 | ||
dc5bd18f MC |
243 | /* Fields from here on are preserved across CPU reset. */ |
244 | QEMUTimer *timer; /* Internal timer */ | |
245 | }; | |
246 | ||
c821774a | 247 | OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass, |
30b5707c | 248 | RISCV_CPU) |
dc5bd18f MC |
249 | |
250 | /** | |
251 | * RISCVCPUClass: | |
252 | * @parent_realize: The parent class' realize handler. | |
253 | * @parent_reset: The parent class' reset handler. | |
254 | * | |
255 | * A RISCV CPU model. | |
256 | */ | |
db1015e9 | 257 | struct RISCVCPUClass { |
dc5bd18f MC |
258 | /*< private >*/ |
259 | CPUClass parent_class; | |
260 | /*< public >*/ | |
261 | DeviceRealize parent_realize; | |
781c67ca | 262 | DeviceReset parent_reset; |
db1015e9 | 263 | }; |
dc5bd18f MC |
264 | |
265 | /** | |
266 | * RISCVCPU: | |
267 | * @env: #CPURISCVState | |
268 | * | |
269 | * A RISCV CPU. | |
270 | */ | |
db1015e9 | 271 | struct RISCVCPU { |
dc5bd18f MC |
272 | /*< private >*/ |
273 | CPUState parent_obj; | |
274 | /*< public >*/ | |
5b146dc7 | 275 | CPUNegativeOffsetState neg; |
dc5bd18f | 276 | CPURISCVState env; |
c4e95030 | 277 | |
b93777e1 BM |
278 | char *dyn_csr_xml; |
279 | ||
c4e95030 AF |
280 | /* Configuration Settings */ |
281 | struct { | |
b55d7d34 AF |
282 | bool ext_i; |
283 | bool ext_e; | |
284 | bool ext_g; | |
285 | bool ext_m; | |
286 | bool ext_a; | |
287 | bool ext_f; | |
288 | bool ext_d; | |
289 | bool ext_c; | |
290 | bool ext_s; | |
291 | bool ext_u; | |
c9eefe05 | 292 | bool ext_h; |
6bf91617 | 293 | bool ext_v; |
0a13a5b8 | 294 | bool ext_counters; |
50fba816 | 295 | bool ext_ifencei; |
591bddea | 296 | bool ext_icsr; |
b55d7d34 | 297 | |
c4e95030 AF |
298 | char *priv_spec; |
299 | char *user_spec; | |
6bf91617 | 300 | char *vext_spec; |
32931383 LZ |
301 | uint16_t vlen; |
302 | uint16_t elen; | |
c4e95030 AF |
303 | bool mmu; |
304 | bool pmp; | |
9b4c9b2b | 305 | uint64_t resetvec; |
c4e95030 | 306 | } cfg; |
db1015e9 | 307 | }; |
dc5bd18f | 308 | |
dc5bd18f MC |
309 | static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) |
310 | { | |
311 | return (env->misa & ext) != 0; | |
312 | } | |
313 | ||
314 | static inline bool riscv_feature(CPURISCVState *env, int feature) | |
315 | { | |
316 | return env->features & (1ULL << feature); | |
317 | } | |
318 | ||
319 | #include "cpu_user.h" | |
320 | #include "cpu_bits.h" | |
321 | ||
322 | extern const char * const riscv_int_regnames[]; | |
323 | extern const char * const riscv_fpr_regnames[]; | |
324 | extern const char * const riscv_excp_names[]; | |
325 | extern const char * const riscv_intr_names[]; | |
326 | ||
c51a3f5d | 327 | const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); |
dc5bd18f | 328 | void riscv_cpu_do_interrupt(CPUState *cpu); |
43a96588 YJ |
329 | int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, |
330 | int cpuid, void *opaque); | |
331 | int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, | |
332 | int cpuid, void *opaque); | |
a010bdbe | 333 | int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); |
dc5bd18f MC |
334 | int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); |
335 | bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); | |
b345b480 | 336 | bool riscv_cpu_fp_enabled(CPURISCVState *env); |
ef6bb7b6 AF |
337 | bool riscv_cpu_virt_enabled(CPURISCVState *env); |
338 | void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); | |
c7b1bbc8 AF |
339 | bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); |
340 | void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable); | |
1c1c060a | 341 | bool riscv_cpu_two_stage_lookup(int mmu_idx); |
dc5bd18f MC |
342 | int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); |
343 | hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); | |
344 | void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, | |
345 | MMUAccessType access_type, int mmu_idx, | |
346 | uintptr_t retaddr); | |
8a4ca3c1 RH |
347 | bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
348 | MMUAccessType access_type, int mmu_idx, | |
349 | bool probe, uintptr_t retaddr); | |
37207e12 PD |
350 | void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, |
351 | vaddr addr, unsigned size, | |
352 | MMUAccessType access_type, | |
353 | int mmu_idx, MemTxAttrs attrs, | |
354 | MemTxResult response, uintptr_t retaddr); | |
dc5bd18f | 355 | char *riscv_isa_string(RISCVCPU *cpu); |
0442428a | 356 | void riscv_cpu_list(void); |
dc5bd18f | 357 | |
fb738839 | 358 | #define cpu_signal_handler riscv_cpu_signal_handler |
dc5bd18f MC |
359 | #define cpu_list riscv_cpu_list |
360 | #define cpu_mmu_index riscv_cpu_mmu_index | |
361 | ||
85ba724f | 362 | #ifndef CONFIG_USER_ONLY |
66e594f2 | 363 | void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); |
e3e7039c | 364 | int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); |
85ba724f MC |
365 | uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); |
366 | #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ | |
a47ef6e9 BM |
367 | void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), |
368 | uint32_t arg); | |
85ba724f | 369 | #endif |
fb738839 | 370 | void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); |
dc5bd18f MC |
371 | |
372 | void riscv_translate_init(void); | |
fb738839 MC |
373 | int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc); |
374 | void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, | |
375 | uint32_t exception, uintptr_t pc); | |
dc5bd18f | 376 | |
fb738839 MC |
377 | target_ulong riscv_cpu_get_fflags(CPURISCVState *env); |
378 | void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); | |
dc5bd18f | 379 | |
c445593d AF |
380 | #define TB_FLAGS_MMU_MASK 7 |
381 | #define TB_FLAGS_PRIV_MMU_MASK 3 | |
382 | #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) | |
83a71719 | 383 | #define TB_FLAGS_MSTATUS_FS MSTATUS_FS |
dc5bd18f | 384 | |
2b7168fc LZ |
385 | typedef CPURISCVState CPUArchState; |
386 | typedef RISCVCPU ArchCPU; | |
387 | #include "exec/cpu-all.h" | |
388 | ||
389 | FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1) | |
390 | FIELD(TB_FLAGS, LMUL, 3, 2) | |
391 | FIELD(TB_FLAGS, SEW, 5, 3) | |
392 | FIELD(TB_FLAGS, VILL, 8, 1) | |
743077b3 AF |
393 | /* Is a Hypervisor instruction load/store allowed? */ |
394 | FIELD(TB_FLAGS, HLSX, 9, 1) | |
2b7168fc | 395 | |
51ae0cab AF |
396 | bool riscv_cpu_is_32bit(CPURISCVState *env); |
397 | ||
2b7168fc LZ |
398 | /* |
399 | * A simplification for VLMAX | |
400 | * = (1 << LMUL) * VLEN / (8 * (1 << SEW)) | |
401 | * = (VLEN << LMUL) / (8 << SEW) | |
402 | * = (VLEN << LMUL) >> (SEW + 3) | |
403 | * = VLEN >> (SEW + 3 - LMUL) | |
404 | */ | |
405 | static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) | |
406 | { | |
407 | uint8_t sew, lmul; | |
408 | ||
409 | sew = FIELD_EX64(vtype, VTYPE, VSEW); | |
410 | lmul = FIELD_EX64(vtype, VTYPE, VLMUL); | |
411 | return cpu->cfg.vlen >> (sew + 3 - lmul); | |
412 | } | |
413 | ||
dc5bd18f | 414 | static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, |
2b7168fc | 415 | target_ulong *cs_base, uint32_t *pflags) |
dc5bd18f | 416 | { |
2b7168fc LZ |
417 | uint32_t flags = 0; |
418 | ||
dc5bd18f MC |
419 | *pc = env->pc; |
420 | *cs_base = 0; | |
2b7168fc LZ |
421 | |
422 | if (riscv_has_ext(env, RVV)) { | |
423 | uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype); | |
424 | bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl); | |
425 | flags = FIELD_DP32(flags, TB_FLAGS, VILL, | |
426 | FIELD_EX64(env->vtype, VTYPE, VILL)); | |
427 | flags = FIELD_DP32(flags, TB_FLAGS, SEW, | |
428 | FIELD_EX64(env->vtype, VTYPE, VSEW)); | |
429 | flags = FIELD_DP32(flags, TB_FLAGS, LMUL, | |
430 | FIELD_EX64(env->vtype, VTYPE, VLMUL)); | |
431 | flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); | |
432 | } else { | |
433 | flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); | |
434 | } | |
435 | ||
dc5bd18f | 436 | #ifdef CONFIG_USER_ONLY |
2b7168fc | 437 | flags |= TB_FLAGS_MSTATUS_FS; |
dc5bd18f | 438 | #else |
2b7168fc | 439 | flags |= cpu_mmu_index(env, 0); |
e28eaed8 | 440 | if (riscv_cpu_fp_enabled(env)) { |
2b7168fc | 441 | flags |= env->mstatus & MSTATUS_FS; |
e28eaed8 | 442 | } |
743077b3 AF |
443 | |
444 | if (riscv_has_ext(env, RVH)) { | |
445 | if (env->priv == PRV_M || | |
446 | (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || | |
447 | (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && | |
448 | get_field(env->hstatus, HSTATUS_HU))) { | |
449 | flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); | |
450 | } | |
451 | } | |
dc5bd18f | 452 | #endif |
743077b3 | 453 | |
2b7168fc | 454 | *pflags = flags; |
dc5bd18f MC |
455 | } |
456 | ||
533c91e8 AF |
457 | RISCVException riscv_csrrw(CPURISCVState *env, int csrno, |
458 | target_ulong *ret_value, | |
459 | target_ulong new_value, target_ulong write_mask); | |
460 | RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, | |
461 | target_ulong *ret_value, | |
462 | target_ulong new_value, | |
463 | target_ulong write_mask); | |
c7b95171 | 464 | |
fb738839 MC |
465 | static inline void riscv_csr_write(CPURISCVState *env, int csrno, |
466 | target_ulong val) | |
c7b95171 MC |
467 | { |
468 | riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); | |
469 | } | |
470 | ||
fb738839 | 471 | static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) |
c7b95171 MC |
472 | { |
473 | target_ulong val = 0; | |
474 | riscv_csrrw(env, csrno, &val, 0, 0); | |
475 | return val; | |
476 | } | |
477 | ||
0e62f92e AF |
478 | typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, |
479 | int csrno); | |
605def6e AF |
480 | typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, |
481 | target_ulong *ret_value); | |
482 | typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, | |
483 | target_ulong new_value); | |
484 | typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, | |
485 | target_ulong *ret_value, | |
486 | target_ulong new_value, | |
487 | target_ulong write_mask); | |
c7b95171 MC |
488 | |
489 | typedef struct { | |
8ceac5dc | 490 | const char *name; |
a88365c1 | 491 | riscv_csr_predicate_fn predicate; |
c7b95171 MC |
492 | riscv_csr_read_fn read; |
493 | riscv_csr_write_fn write; | |
494 | riscv_csr_op_fn op; | |
495 | } riscv_csr_operations; | |
496 | ||
56118ee8 BM |
497 | /* CSR function table constants */ |
498 | enum { | |
499 | CSR_TABLE_SIZE = 0x1000 | |
500 | }; | |
501 | ||
502 | /* CSR function table */ | |
6f03770d | 503 | extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; |
56118ee8 | 504 | |
c7b95171 MC |
505 | void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); |
506 | void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); | |
dc5bd18f | 507 | |
5371f5cd JW |
508 | void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); |
509 | ||
dc5bd18f | 510 | #endif /* RISCV_CPU_H */ |