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dc5bd18f MC |
1 | /* |
2 | * QEMU RISC-V CPU | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #ifndef RISCV_CPU_H | |
21 | #define RISCV_CPU_H | |
22 | ||
23 | /* QEMU addressing/paging config */ | |
24 | #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ | |
25 | #if defined(TARGET_RISCV64) | |
26 | #define TARGET_LONG_BITS 64 | |
718a941e MC |
27 | #define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */ |
28 | #define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */ | |
dc5bd18f MC |
29 | #elif defined(TARGET_RISCV32) |
30 | #define TARGET_LONG_BITS 32 | |
718a941e MC |
31 | #define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */ |
32 | #define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */ | |
dc5bd18f MC |
33 | #endif |
34 | ||
35 | #define TCG_GUEST_DEFAULT_MO 0 | |
36 | ||
dc5bd18f MC |
37 | #define CPUArchState struct CPURISCVState |
38 | ||
39 | #include "qemu-common.h" | |
40 | #include "qom/cpu.h" | |
41 | #include "exec/cpu-defs.h" | |
42 | #include "fpu/softfloat.h" | |
43 | ||
44 | #define TYPE_RISCV_CPU "riscv-cpu" | |
45 | ||
46 | #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU | |
47 | #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) | |
0dacec87 | 48 | #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU |
dc5bd18f MC |
49 | |
50 | #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") | |
51 | #define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1") | |
52 | #define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0") | |
53 | #define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nommu") | |
54 | #define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1") | |
55 | #define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0") | |
56 | #define TYPE_RISCV_CPU_RV64IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv64imacu-nommu") | |
57 | #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") | |
58 | #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") | |
59 | #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") | |
60 | #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") | |
61 | ||
62 | #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) | |
63 | #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) | |
64 | ||
65 | #if defined(TARGET_RISCV32) | |
66 | #define RVXLEN RV32 | |
67 | #elif defined(TARGET_RISCV64) | |
68 | #define RVXLEN RV64 | |
69 | #endif | |
70 | ||
71 | #define RV(x) ((target_ulong)1 << (x - 'A')) | |
72 | ||
73 | #define RVI RV('I') | |
79f86934 | 74 | #define RVE RV('E') /* E and I are mutually exclusive */ |
dc5bd18f MC |
75 | #define RVM RV('M') |
76 | #define RVA RV('A') | |
77 | #define RVF RV('F') | |
78 | #define RVD RV('D') | |
79 | #define RVC RV('C') | |
80 | #define RVS RV('S') | |
81 | #define RVU RV('U') | |
82 | ||
83 | /* S extension denotes that Supervisor mode exists, however it is possible | |
84 | to have a core that support S mode but does not have an MMU and there | |
85 | is currently no bit in misa to indicate whether an MMU exists or not | |
a88365c1 | 86 | so a cpu features bitfield is required, likewise for optional PMP support */ |
dc5bd18f | 87 | enum { |
a88365c1 MC |
88 | RISCV_FEATURE_MMU, |
89 | RISCV_FEATURE_PMP | |
dc5bd18f MC |
90 | }; |
91 | ||
92 | #define USER_VERSION_2_02_0 0x00020200 | |
93 | #define PRIV_VERSION_1_09_1 0x00010901 | |
94 | #define PRIV_VERSION_1_10_0 0x00011000 | |
95 | ||
96 | #define TRANSLATE_FAIL 1 | |
97 | #define TRANSLATE_SUCCESS 0 | |
98 | #define NB_MMU_MODES 4 | |
99 | #define MMU_USER_IDX 3 | |
100 | ||
101 | #define MAX_RISCV_PMPS (16) | |
102 | ||
103 | typedef struct CPURISCVState CPURISCVState; | |
104 | ||
105 | #include "pmp.h" | |
106 | ||
107 | struct CPURISCVState { | |
108 | target_ulong gpr[32]; | |
109 | uint64_t fpr[32]; /* assume both F and D extensions */ | |
110 | target_ulong pc; | |
111 | target_ulong load_res; | |
112 | target_ulong load_val; | |
113 | ||
114 | target_ulong frm; | |
115 | ||
116 | target_ulong badaddr; | |
117 | ||
118 | target_ulong user_ver; | |
119 | target_ulong priv_ver; | |
120 | target_ulong misa; | |
121 | ||
122 | uint32_t features; | |
123 | ||
124 | #ifndef CONFIG_USER_ONLY | |
125 | target_ulong priv; | |
126 | target_ulong resetvec; | |
127 | ||
128 | target_ulong mhartid; | |
129 | target_ulong mstatus; | |
85ba724f | 130 | |
dc5bd18f MC |
131 | /* |
132 | * CAUTION! Unlike the rest of this struct, mip is accessed asynchonously | |
85ba724f MC |
133 | * by I/O threads. It should be read with atomic_read. It should be updated |
134 | * using riscv_cpu_update_mip with the iothread mutex held. The iothread | |
135 | * mutex must be held because mip must be consistent with the CPU inturrept | |
136 | * state. riscv_cpu_update_mip calls cpu_interrupt or cpu_reset_interrupt | |
137 | * wuth the invariant that CPU_INTERRUPT_HARD is set iff mip is non-zero. | |
138 | * mip is 32-bits to allow atomic_read on 32-bit hosts. | |
dc5bd18f | 139 | */ |
85ba724f MC |
140 | uint32_t mip; |
141 | ||
dc5bd18f MC |
142 | target_ulong mie; |
143 | target_ulong mideleg; | |
144 | ||
145 | target_ulong sptbr; /* until: priv-1.9.1 */ | |
146 | target_ulong satp; /* since: priv-1.10.0 */ | |
147 | target_ulong sbadaddr; | |
148 | target_ulong mbadaddr; | |
149 | target_ulong medeleg; | |
150 | ||
151 | target_ulong stvec; | |
152 | target_ulong sepc; | |
153 | target_ulong scause; | |
154 | ||
155 | target_ulong mtvec; | |
156 | target_ulong mepc; | |
157 | target_ulong mcause; | |
158 | target_ulong mtval; /* since: priv-1.10.0 */ | |
159 | ||
8c59f5c1 MC |
160 | target_ulong scounteren; |
161 | target_ulong mcounteren; | |
dc5bd18f MC |
162 | |
163 | target_ulong sscratch; | |
164 | target_ulong mscratch; | |
165 | ||
166 | /* temporary htif regs */ | |
167 | uint64_t mfromhost; | |
168 | uint64_t mtohost; | |
169 | uint64_t timecmp; | |
170 | ||
171 | /* physical memory protection */ | |
172 | pmp_table_t pmp_state; | |
173 | #endif | |
174 | ||
175 | float_status fp_status; | |
176 | ||
177 | /* QEMU */ | |
178 | CPU_COMMON | |
179 | ||
180 | /* Fields from here on are preserved across CPU reset. */ | |
181 | QEMUTimer *timer; /* Internal timer */ | |
182 | }; | |
183 | ||
184 | #define RISCV_CPU_CLASS(klass) \ | |
185 | OBJECT_CLASS_CHECK(RISCVCPUClass, (klass), TYPE_RISCV_CPU) | |
186 | #define RISCV_CPU(obj) \ | |
187 | OBJECT_CHECK(RISCVCPU, (obj), TYPE_RISCV_CPU) | |
188 | #define RISCV_CPU_GET_CLASS(obj) \ | |
189 | OBJECT_GET_CLASS(RISCVCPUClass, (obj), TYPE_RISCV_CPU) | |
190 | ||
191 | /** | |
192 | * RISCVCPUClass: | |
193 | * @parent_realize: The parent class' realize handler. | |
194 | * @parent_reset: The parent class' reset handler. | |
195 | * | |
196 | * A RISCV CPU model. | |
197 | */ | |
198 | typedef struct RISCVCPUClass { | |
199 | /*< private >*/ | |
200 | CPUClass parent_class; | |
201 | /*< public >*/ | |
202 | DeviceRealize parent_realize; | |
203 | void (*parent_reset)(CPUState *cpu); | |
204 | } RISCVCPUClass; | |
205 | ||
206 | /** | |
207 | * RISCVCPU: | |
208 | * @env: #CPURISCVState | |
209 | * | |
210 | * A RISCV CPU. | |
211 | */ | |
212 | typedef struct RISCVCPU { | |
213 | /*< private >*/ | |
214 | CPUState parent_obj; | |
215 | /*< public >*/ | |
216 | CPURISCVState env; | |
217 | } RISCVCPU; | |
218 | ||
219 | static inline RISCVCPU *riscv_env_get_cpu(CPURISCVState *env) | |
220 | { | |
221 | return container_of(env, RISCVCPU, env); | |
222 | } | |
223 | ||
224 | static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) | |
225 | { | |
226 | return (env->misa & ext) != 0; | |
227 | } | |
228 | ||
229 | static inline bool riscv_feature(CPURISCVState *env, int feature) | |
230 | { | |
231 | return env->features & (1ULL << feature); | |
232 | } | |
233 | ||
234 | #include "cpu_user.h" | |
235 | #include "cpu_bits.h" | |
236 | ||
237 | extern const char * const riscv_int_regnames[]; | |
238 | extern const char * const riscv_fpr_regnames[]; | |
239 | extern const char * const riscv_excp_names[]; | |
240 | extern const char * const riscv_intr_names[]; | |
241 | ||
242 | #define ENV_GET_CPU(e) CPU(riscv_env_get_cpu(e)) | |
243 | #define ENV_OFFSET offsetof(RISCVCPU, env) | |
244 | ||
245 | void riscv_cpu_do_interrupt(CPUState *cpu); | |
246 | int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); | |
247 | int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); | |
248 | bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); | |
249 | int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); | |
250 | hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); | |
251 | void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, | |
252 | MMUAccessType access_type, int mmu_idx, | |
253 | uintptr_t retaddr); | |
254 | int riscv_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, | |
255 | int rw, int mmu_idx); | |
dc5bd18f MC |
256 | char *riscv_isa_string(RISCVCPU *cpu); |
257 | void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf); | |
258 | ||
dc5bd18f MC |
259 | #define cpu_signal_handler cpu_riscv_signal_handler |
260 | #define cpu_list riscv_cpu_list | |
261 | #define cpu_mmu_index riscv_cpu_mmu_index | |
262 | ||
85ba724f MC |
263 | #ifndef CONFIG_USER_ONLY |
264 | uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); | |
265 | #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ | |
266 | #endif | |
dc5bd18f MC |
267 | void riscv_set_mode(CPURISCVState *env, target_ulong newpriv); |
268 | ||
269 | void riscv_translate_init(void); | |
270 | RISCVCPU *cpu_riscv_init(const char *cpu_model); | |
271 | int cpu_riscv_signal_handler(int host_signum, void *pinfo, void *puc); | |
272 | void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env, | |
273 | uint32_t exception, uintptr_t pc); | |
274 | ||
275 | target_ulong cpu_riscv_get_fflags(CPURISCVState *env); | |
276 | void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong); | |
277 | ||
83a71719 RH |
278 | #define TB_FLAGS_MMU_MASK 3 |
279 | #define TB_FLAGS_MSTATUS_FS MSTATUS_FS | |
dc5bd18f MC |
280 | |
281 | static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, | |
282 | target_ulong *cs_base, uint32_t *flags) | |
283 | { | |
284 | *pc = env->pc; | |
285 | *cs_base = 0; | |
286 | #ifdef CONFIG_USER_ONLY | |
83a71719 | 287 | *flags = TB_FLAGS_MSTATUS_FS; |
dc5bd18f MC |
288 | #else |
289 | *flags = cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS); | |
290 | #endif | |
291 | } | |
292 | ||
c7b95171 MC |
293 | int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, |
294 | target_ulong new_value, target_ulong write_mask); | |
295 | ||
296 | static inline void csr_write_helper(CPURISCVState *env, target_ulong val, | |
297 | int csrno) | |
298 | { | |
299 | riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); | |
300 | } | |
301 | ||
302 | static inline target_ulong csr_read_helper(CPURISCVState *env, int csrno) | |
303 | { | |
304 | target_ulong val = 0; | |
305 | riscv_csrrw(env, csrno, &val, 0, 0); | |
306 | return val; | |
307 | } | |
308 | ||
309 | typedef int (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno); | |
310 | typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, | |
311 | target_ulong *ret_value); | |
312 | typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, | |
313 | target_ulong new_value); | |
314 | typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, | |
315 | target_ulong *ret_value, target_ulong new_value, target_ulong write_mask); | |
316 | ||
317 | typedef struct { | |
a88365c1 | 318 | riscv_csr_predicate_fn predicate; |
c7b95171 MC |
319 | riscv_csr_read_fn read; |
320 | riscv_csr_write_fn write; | |
321 | riscv_csr_op_fn op; | |
322 | } riscv_csr_operations; | |
323 | ||
324 | void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); | |
325 | void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); | |
dc5bd18f | 326 | |
dc5bd18f MC |
327 | #include "exec/cpu-all.h" |
328 | ||
329 | #endif /* RISCV_CPU_H */ |