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dc5bd18f MC |
1 | /* |
2 | * QEMU RISC-V CPU | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #ifndef RISCV_CPU_H | |
21 | #define RISCV_CPU_H | |
22 | ||
2e5b09fd | 23 | #include "hw/core/cpu.h" |
2b7168fc | 24 | #include "hw/registerfields.h" |
dc5bd18f | 25 | #include "exec/cpu-defs.h" |
135b03cb | 26 | #include "fpu/softfloat-types.h" |
db1015e9 | 27 | #include "qom/object.h" |
961738ff | 28 | #include "qemu/int128.h" |
e91a7227 | 29 | #include "cpu_bits.h" |
dc5bd18f | 30 | |
74433bf0 RH |
31 | #define TCG_GUEST_DEFAULT_MO 0 |
32 | ||
dc5bd18f MC |
33 | #define TYPE_RISCV_CPU "riscv-cpu" |
34 | ||
35 | #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU | |
36 | #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) | |
0dacec87 | 37 | #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU |
dc5bd18f MC |
38 | |
39 | #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") | |
8903bf6e AF |
40 | #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") |
41 | #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") | |
332dab68 | 42 | #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") |
36b80ad9 | 43 | #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") |
6ddc7069 | 44 | #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") |
dc5bd18f | 45 | #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") |
d784733b | 46 | #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") |
dc5bd18f MC |
47 | #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") |
48 | #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") | |
49 | #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") | |
10f1ca27 | 50 | #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") |
dc5bd18f | 51 | |
c0a635f3 AF |
52 | #if defined(TARGET_RISCV32) |
53 | # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 | |
54 | #elif defined(TARGET_RISCV64) | |
55 | # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 | |
56 | #endif | |
57 | ||
dc5bd18f MC |
58 | #define RV(x) ((target_ulong)1 << (x - 'A')) |
59 | ||
60 | #define RVI RV('I') | |
79f86934 | 61 | #define RVE RV('E') /* E and I are mutually exclusive */ |
dc5bd18f MC |
62 | #define RVM RV('M') |
63 | #define RVA RV('A') | |
64 | #define RVF RV('F') | |
65 | #define RVD RV('D') | |
ad9e5aa2 | 66 | #define RVV RV('V') |
dc5bd18f MC |
67 | #define RVC RV('C') |
68 | #define RVS RV('S') | |
69 | #define RVU RV('U') | |
af1fa003 | 70 | #define RVH RV('H') |
53dcea58 | 71 | #define RVJ RV('J') |
dc5bd18f MC |
72 | |
73 | /* S extension denotes that Supervisor mode exists, however it is possible | |
74 | to have a core that support S mode but does not have an MMU and there | |
75 | is currently no bit in misa to indicate whether an MMU exists or not | |
a88365c1 | 76 | so a cpu features bitfield is required, likewise for optional PMP support */ |
dc5bd18f | 77 | enum { |
a88365c1 | 78 | RISCV_FEATURE_MMU, |
f18637cd | 79 | RISCV_FEATURE_PMP, |
4a345b2a | 80 | RISCV_FEATURE_EPMP, |
f18637cd | 81 | RISCV_FEATURE_MISA |
dc5bd18f MC |
82 | }; |
83 | ||
dc5bd18f | 84 | #define PRIV_VERSION_1_10_0 0x00011000 |
6729dbbd | 85 | #define PRIV_VERSION_1_11_0 0x00011100 |
dc5bd18f | 86 | |
9ec6622d | 87 | #define VEXT_VERSION_1_00_0 0x00010000 |
32931383 | 88 | |
33a9a57d YJ |
89 | enum { |
90 | TRANSLATE_SUCCESS, | |
91 | TRANSLATE_FAIL, | |
92 | TRANSLATE_PMP_FAIL, | |
93 | TRANSLATE_G_STAGE_FAIL | |
94 | }; | |
95 | ||
dc5bd18f MC |
96 | #define MMU_USER_IDX 3 |
97 | ||
98 | #define MAX_RISCV_PMPS (16) | |
99 | ||
100 | typedef struct CPURISCVState CPURISCVState; | |
101 | ||
bbf3d1b4 | 102 | #if !defined(CONFIG_USER_ONLY) |
dc5bd18f | 103 | #include "pmp.h" |
bbf3d1b4 | 104 | #endif |
dc5bd18f | 105 | |
8a4b5257 | 106 | #define RV_VLEN_MAX 1024 |
ad9e5aa2 | 107 | |
33f1beaf FC |
108 | FIELD(VTYPE, VLMUL, 0, 3) |
109 | FIELD(VTYPE, VSEW, 3, 3) | |
3479a814 FC |
110 | FIELD(VTYPE, VTA, 6, 1) |
111 | FIELD(VTYPE, VMA, 7, 1) | |
33f1beaf FC |
112 | FIELD(VTYPE, VEDIV, 8, 2) |
113 | FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) | |
2b7168fc | 114 | |
dc5bd18f MC |
115 | struct CPURISCVState { |
116 | target_ulong gpr[32]; | |
2b547084 | 117 | target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ |
dc5bd18f | 118 | uint64_t fpr[32]; /* assume both F and D extensions */ |
ad9e5aa2 LZ |
119 | |
120 | /* vector coprocessor state. */ | |
121 | uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); | |
122 | target_ulong vxrm; | |
123 | target_ulong vxsat; | |
124 | target_ulong vl; | |
125 | target_ulong vstart; | |
126 | target_ulong vtype; | |
d96a271a | 127 | bool vill; |
ad9e5aa2 | 128 | |
dc5bd18f MC |
129 | target_ulong pc; |
130 | target_ulong load_res; | |
131 | target_ulong load_val; | |
132 | ||
133 | target_ulong frm; | |
134 | ||
135 | target_ulong badaddr; | |
48eaeb56 AF |
136 | uint32_t bins; |
137 | ||
36a18664 | 138 | target_ulong guest_phys_fault_addr; |
dc5bd18f | 139 | |
dc5bd18f | 140 | target_ulong priv_ver; |
d2c1a177 | 141 | target_ulong bext_ver; |
32931383 | 142 | target_ulong vext_ver; |
e91a7227 RH |
143 | |
144 | /* RISCVMXL, but uint32_t for vmstate migration */ | |
145 | uint32_t misa_mxl; /* current mxl */ | |
146 | uint32_t misa_mxl_max; /* max mxl for this cpu */ | |
147 | uint32_t misa_ext; /* current extensions */ | |
148 | uint32_t misa_ext_mask; /* max ext for this cpu */ | |
440544e1 | 149 | uint32_t xl; /* current xlen */ |
dc5bd18f | 150 | |
b3a5d1fb FP |
151 | /* 128-bit helpers upper part return value */ |
152 | target_ulong retxh; | |
153 | ||
dc5bd18f MC |
154 | uint32_t features; |
155 | ||
5836c3ec KC |
156 | #ifdef CONFIG_USER_ONLY |
157 | uint32_t elf_flags; | |
158 | #endif | |
159 | ||
dc5bd18f MC |
160 | #ifndef CONFIG_USER_ONLY |
161 | target_ulong priv; | |
ef6bb7b6 AF |
162 | /* This contains QEMU specific information about the virt state. */ |
163 | target_ulong virt; | |
dc5bd18f MC |
164 | target_ulong resetvec; |
165 | ||
166 | target_ulong mhartid; | |
284d697c YJ |
167 | /* |
168 | * For RV32 this is 32-bit mstatus and 32-bit mstatush. | |
169 | * For RV64 this is a 64-bit mstatus. | |
170 | */ | |
171 | uint64_t mstatus; | |
85ba724f | 172 | |
02861613 | 173 | target_ulong mip; |
66e594f2 | 174 | |
e3e7039c | 175 | uint32_t miclaim; |
85ba724f | 176 | |
dc5bd18f MC |
177 | target_ulong mie; |
178 | target_ulong mideleg; | |
179 | ||
dc5bd18f | 180 | target_ulong satp; /* since: priv-1.10.0 */ |
ac12b601 | 181 | target_ulong stval; |
dc5bd18f MC |
182 | target_ulong medeleg; |
183 | ||
184 | target_ulong stvec; | |
185 | target_ulong sepc; | |
186 | target_ulong scause; | |
187 | ||
188 | target_ulong mtvec; | |
189 | target_ulong mepc; | |
190 | target_ulong mcause; | |
191 | target_ulong mtval; /* since: priv-1.10.0 */ | |
192 | ||
bd023ce3 AF |
193 | /* Hypervisor CSRs */ |
194 | target_ulong hstatus; | |
195 | target_ulong hedeleg; | |
196 | target_ulong hideleg; | |
197 | target_ulong hcounteren; | |
198 | target_ulong htval; | |
199 | target_ulong htinst; | |
200 | target_ulong hgatp; | |
c6957248 | 201 | uint64_t htimedelta; |
bd023ce3 | 202 | |
2c64ab66 FP |
203 | /* Upper 64-bits of 128-bit CSRs */ |
204 | uint64_t mscratchh; | |
205 | uint64_t sscratchh; | |
206 | ||
bd023ce3 | 207 | /* Virtual CSRs */ |
284d697c YJ |
208 | /* |
209 | * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. | |
210 | * For RV64 this is a 64-bit vsstatus. | |
211 | */ | |
212 | uint64_t vsstatus; | |
bd023ce3 AF |
213 | target_ulong vstvec; |
214 | target_ulong vsscratch; | |
215 | target_ulong vsepc; | |
216 | target_ulong vscause; | |
217 | target_ulong vstval; | |
218 | target_ulong vsatp; | |
219 | ||
220 | target_ulong mtval2; | |
221 | target_ulong mtinst; | |
222 | ||
66e594f2 AF |
223 | /* HS Backup CSRs */ |
224 | target_ulong stvec_hs; | |
225 | target_ulong sscratch_hs; | |
226 | target_ulong sepc_hs; | |
227 | target_ulong scause_hs; | |
228 | target_ulong stval_hs; | |
229 | target_ulong satp_hs; | |
284d697c | 230 | uint64_t mstatus_hs; |
66e594f2 | 231 | |
ec352d0c GK |
232 | /* Signals whether the current exception occurred with two-stage address |
233 | translation active. */ | |
234 | bool two_stage_lookup; | |
235 | ||
8c59f5c1 MC |
236 | target_ulong scounteren; |
237 | target_ulong mcounteren; | |
dc5bd18f MC |
238 | |
239 | target_ulong sscratch; | |
240 | target_ulong mscratch; | |
241 | ||
242 | /* temporary htif regs */ | |
243 | uint64_t mfromhost; | |
244 | uint64_t mtohost; | |
245 | uint64_t timecmp; | |
246 | ||
247 | /* physical memory protection */ | |
248 | pmp_table_t pmp_state; | |
2582a95c | 249 | target_ulong mseccfg; |
753e3fe2 | 250 | |
c6957248 | 251 | /* machine specific rdtime callback */ |
a47ef6e9 BM |
252 | uint64_t (*rdtime_fn)(uint32_t); |
253 | uint32_t rdtime_fn_arg; | |
c6957248 | 254 | |
753e3fe2 JW |
255 | /* True if in debugger mode. */ |
256 | bool debugger; | |
4bbe8033 AB |
257 | |
258 | /* | |
259 | * CSRs for PointerMasking extension | |
260 | */ | |
261 | target_ulong mmte; | |
262 | target_ulong mpmmask; | |
263 | target_ulong mpmbase; | |
264 | target_ulong spmmask; | |
265 | target_ulong spmbase; | |
266 | target_ulong upmmask; | |
267 | target_ulong upmbase; | |
dc5bd18f | 268 | #endif |
40bfa5f6 LZ |
269 | target_ulong cur_pmmask; |
270 | target_ulong cur_pmbase; | |
dc5bd18f MC |
271 | |
272 | float_status fp_status; | |
273 | ||
dc5bd18f MC |
274 | /* Fields from here on are preserved across CPU reset. */ |
275 | QEMUTimer *timer; /* Internal timer */ | |
ad40be27 YJ |
276 | |
277 | hwaddr kernel_addr; | |
278 | hwaddr fdt_addr; | |
27abe66f YJ |
279 | |
280 | /* kvm timer */ | |
281 | bool kvm_timer_dirty; | |
282 | uint64_t kvm_timer_time; | |
283 | uint64_t kvm_timer_compare; | |
284 | uint64_t kvm_timer_state; | |
285 | uint64_t kvm_timer_frequency; | |
dc5bd18f MC |
286 | }; |
287 | ||
c821774a | 288 | OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass, |
30b5707c | 289 | RISCV_CPU) |
dc5bd18f MC |
290 | |
291 | /** | |
292 | * RISCVCPUClass: | |
293 | * @parent_realize: The parent class' realize handler. | |
294 | * @parent_reset: The parent class' reset handler. | |
295 | * | |
296 | * A RISCV CPU model. | |
297 | */ | |
db1015e9 | 298 | struct RISCVCPUClass { |
dc5bd18f MC |
299 | /*< private >*/ |
300 | CPUClass parent_class; | |
301 | /*< public >*/ | |
302 | DeviceRealize parent_realize; | |
781c67ca | 303 | DeviceReset parent_reset; |
db1015e9 | 304 | }; |
dc5bd18f | 305 | |
466292bd PT |
306 | struct RISCVCPUConfig { |
307 | bool ext_i; | |
308 | bool ext_e; | |
309 | bool ext_g; | |
310 | bool ext_m; | |
311 | bool ext_a; | |
312 | bool ext_f; | |
313 | bool ext_d; | |
314 | bool ext_c; | |
315 | bool ext_s; | |
316 | bool ext_u; | |
317 | bool ext_h; | |
318 | bool ext_j; | |
319 | bool ext_v; | |
320 | bool ext_zba; | |
321 | bool ext_zbb; | |
322 | bool ext_zbc; | |
323 | bool ext_zbs; | |
324 | bool ext_counters; | |
325 | bool ext_ifencei; | |
326 | bool ext_icsr; | |
327 | bool ext_zfh; | |
328 | bool ext_zfhmin; | |
329 | bool ext_zve32f; | |
330 | bool ext_zve64f; | |
331 | ||
0d429bd2 PT |
332 | /* Vendor-specific custom extensions */ |
333 | bool ext_XVentanaCondOps; | |
334 | ||
466292bd PT |
335 | char *priv_spec; |
336 | char *user_spec; | |
337 | char *bext_spec; | |
338 | char *vext_spec; | |
339 | uint16_t vlen; | |
340 | uint16_t elen; | |
341 | bool mmu; | |
342 | bool pmp; | |
343 | bool epmp; | |
344 | uint64_t resetvec; | |
345 | }; | |
346 | ||
347 | typedef struct RISCVCPUConfig RISCVCPUConfig; | |
348 | ||
dc5bd18f MC |
349 | /** |
350 | * RISCVCPU: | |
351 | * @env: #CPURISCVState | |
352 | * | |
353 | * A RISCV CPU. | |
354 | */ | |
db1015e9 | 355 | struct RISCVCPU { |
dc5bd18f MC |
356 | /*< private >*/ |
357 | CPUState parent_obj; | |
358 | /*< public >*/ | |
5b146dc7 | 359 | CPUNegativeOffsetState neg; |
dc5bd18f | 360 | CPURISCVState env; |
c4e95030 | 361 | |
b93777e1 | 362 | char *dyn_csr_xml; |
719d3561 | 363 | char *dyn_vreg_xml; |
b93777e1 | 364 | |
c4e95030 | 365 | /* Configuration Settings */ |
466292bd | 366 | RISCVCPUConfig cfg; |
db1015e9 | 367 | }; |
dc5bd18f | 368 | |
dc5bd18f MC |
369 | static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) |
370 | { | |
e91a7227 | 371 | return (env->misa_ext & ext) != 0; |
dc5bd18f MC |
372 | } |
373 | ||
374 | static inline bool riscv_feature(CPURISCVState *env, int feature) | |
375 | { | |
376 | return env->features & (1ULL << feature); | |
377 | } | |
378 | ||
379 | #include "cpu_user.h" | |
dc5bd18f MC |
380 | |
381 | extern const char * const riscv_int_regnames[]; | |
2b547084 | 382 | extern const char * const riscv_int_regnamesh[]; |
dc5bd18f | 383 | extern const char * const riscv_fpr_regnames[]; |
dc5bd18f | 384 | |
c51a3f5d | 385 | const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); |
dc5bd18f | 386 | void riscv_cpu_do_interrupt(CPUState *cpu); |
43a96588 YJ |
387 | int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, |
388 | int cpuid, void *opaque); | |
389 | int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, | |
390 | int cpuid, void *opaque); | |
a010bdbe | 391 | int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); |
dc5bd18f | 392 | int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); |
b345b480 | 393 | bool riscv_cpu_fp_enabled(CPURISCVState *env); |
61b4b69d | 394 | bool riscv_cpu_vector_enabled(CPURISCVState *env); |
ef6bb7b6 AF |
395 | bool riscv_cpu_virt_enabled(CPURISCVState *env); |
396 | void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); | |
1c1c060a | 397 | bool riscv_cpu_two_stage_lookup(int mmu_idx); |
dc5bd18f MC |
398 | int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); |
399 | hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); | |
400 | void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, | |
401 | MMUAccessType access_type, int mmu_idx, | |
fa947a66 | 402 | uintptr_t retaddr) QEMU_NORETURN; |
8a4ca3c1 RH |
403 | bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
404 | MMUAccessType access_type, int mmu_idx, | |
405 | bool probe, uintptr_t retaddr); | |
37207e12 PD |
406 | void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, |
407 | vaddr addr, unsigned size, | |
408 | MMUAccessType access_type, | |
409 | int mmu_idx, MemTxAttrs attrs, | |
410 | MemTxResult response, uintptr_t retaddr); | |
dc5bd18f | 411 | char *riscv_isa_string(RISCVCPU *cpu); |
0442428a | 412 | void riscv_cpu_list(void); |
dc5bd18f | 413 | |
dc5bd18f MC |
414 | #define cpu_list riscv_cpu_list |
415 | #define cpu_mmu_index riscv_cpu_mmu_index | |
416 | ||
85ba724f | 417 | #ifndef CONFIG_USER_ONLY |
17b3c353 | 418 | bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); |
66e594f2 | 419 | void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); |
e3e7039c | 420 | int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); |
85ba724f MC |
421 | uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); |
422 | #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ | |
a47ef6e9 BM |
423 | void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), |
424 | uint32_t arg); | |
85ba724f | 425 | #endif |
fb738839 | 426 | void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); |
dc5bd18f MC |
427 | |
428 | void riscv_translate_init(void); | |
fb738839 MC |
429 | void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, |
430 | uint32_t exception, uintptr_t pc); | |
dc5bd18f | 431 | |
fb738839 MC |
432 | target_ulong riscv_cpu_get_fflags(CPURISCVState *env); |
433 | void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); | |
dc5bd18f | 434 | |
c445593d AF |
435 | #define TB_FLAGS_PRIV_MMU_MASK 3 |
436 | #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) | |
83a71719 | 437 | #define TB_FLAGS_MSTATUS_FS MSTATUS_FS |
61b4b69d | 438 | #define TB_FLAGS_MSTATUS_VS MSTATUS_VS |
dc5bd18f | 439 | |
2b7168fc LZ |
440 | typedef CPURISCVState CPUArchState; |
441 | typedef RISCVCPU ArchCPU; | |
442 | #include "exec/cpu-all.h" | |
443 | ||
61d56494 | 444 | FIELD(TB_FLAGS, MEM_IDX, 0, 3) |
33f1beaf | 445 | FIELD(TB_FLAGS, LMUL, 3, 3) |
61d56494 | 446 | FIELD(TB_FLAGS, SEW, 6, 3) |
33f1beaf FC |
447 | /* Skip MSTATUS_VS (0x600) bits */ |
448 | FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) | |
449 | FIELD(TB_FLAGS, VILL, 12, 1) | |
450 | /* Skip MSTATUS_FS (0x6000) bits */ | |
743077b3 | 451 | /* Is a Hypervisor instruction load/store allowed? */ |
33f1beaf FC |
452 | FIELD(TB_FLAGS, HLSX, 15, 1) |
453 | FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) | |
454 | FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) | |
92371bd9 | 455 | /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ |
33f1beaf | 456 | FIELD(TB_FLAGS, XL, 20, 2) |
0774a7a1 | 457 | /* If PointerMasking should be applied */ |
4208dc7e LZ |
458 | FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1) |
459 | FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1) | |
2b7168fc | 460 | |
db23e5d9 RH |
461 | #ifdef TARGET_RISCV32 |
462 | #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) | |
463 | #else | |
464 | static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) | |
465 | { | |
466 | return env->misa_mxl; | |
467 | } | |
468 | #endif | |
51ae0cab | 469 | |
440544e1 LZ |
470 | #if defined(TARGET_RISCV32) |
471 | #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) | |
472 | #else | |
473 | static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) | |
474 | { | |
475 | RISCVMXL xl = env->misa_mxl; | |
476 | #if !defined(CONFIG_USER_ONLY) | |
477 | /* | |
478 | * When emulating a 32-bit-only cpu, use RV32. | |
479 | * When emulating a 64-bit cpu, and MXL has been reduced to RV32, | |
480 | * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened | |
481 | * back to RV64 for lower privs. | |
482 | */ | |
483 | if (xl != MXL_RV32) { | |
484 | switch (env->priv) { | |
485 | case PRV_M: | |
486 | break; | |
487 | case PRV_U: | |
488 | xl = get_field(env->mstatus, MSTATUS64_UXL); | |
489 | break; | |
490 | default: /* PRV_S | PRV_H */ | |
491 | xl = get_field(env->mstatus, MSTATUS64_SXL); | |
492 | break; | |
493 | } | |
494 | } | |
495 | #endif | |
496 | return xl; | |
497 | } | |
498 | #endif | |
499 | ||
31961cfe LZ |
500 | static inline int riscv_cpu_xlen(CPURISCVState *env) |
501 | { | |
502 | return 16 << env->xl; | |
503 | } | |
504 | ||
2b7168fc | 505 | /* |
a689a82b FC |
506 | * Encode LMUL to lmul as follows: |
507 | * LMUL vlmul lmul | |
508 | * 1 000 0 | |
509 | * 2 001 1 | |
510 | * 4 010 2 | |
511 | * 8 011 3 | |
512 | * - 100 - | |
513 | * 1/8 101 -3 | |
514 | * 1/4 110 -2 | |
515 | * 1/2 111 -1 | |
516 | * | |
517 | * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) | |
518 | * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 | |
519 | * => VLMAX = vlen >> (1 + 3 - (-3)) | |
520 | * = 256 >> 7 | |
521 | * = 2 | |
2b7168fc LZ |
522 | */ |
523 | static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) | |
524 | { | |
a689a82b FC |
525 | uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); |
526 | int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); | |
2b7168fc LZ |
527 | return cpu->cfg.vlen >> (sew + 3 - lmul); |
528 | } | |
529 | ||
53677acf RH |
530 | void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, |
531 | target_ulong *cs_base, uint32_t *pflags); | |
dc5bd18f | 532 | |
40bfa5f6 LZ |
533 | void riscv_cpu_update_mask(CPURISCVState *env); |
534 | ||
533c91e8 AF |
535 | RISCVException riscv_csrrw(CPURISCVState *env, int csrno, |
536 | target_ulong *ret_value, | |
537 | target_ulong new_value, target_ulong write_mask); | |
538 | RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, | |
539 | target_ulong *ret_value, | |
540 | target_ulong new_value, | |
541 | target_ulong write_mask); | |
c7b95171 | 542 | |
fb738839 MC |
543 | static inline void riscv_csr_write(CPURISCVState *env, int csrno, |
544 | target_ulong val) | |
c7b95171 MC |
545 | { |
546 | riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); | |
547 | } | |
548 | ||
fb738839 | 549 | static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) |
c7b95171 MC |
550 | { |
551 | target_ulong val = 0; | |
552 | riscv_csrrw(env, csrno, &val, 0, 0); | |
553 | return val; | |
554 | } | |
555 | ||
0e62f92e AF |
556 | typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, |
557 | int csrno); | |
605def6e AF |
558 | typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, |
559 | target_ulong *ret_value); | |
560 | typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, | |
561 | target_ulong new_value); | |
562 | typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, | |
563 | target_ulong *ret_value, | |
564 | target_ulong new_value, | |
565 | target_ulong write_mask); | |
c7b95171 | 566 | |
961738ff FP |
567 | RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, |
568 | Int128 *ret_value, | |
569 | Int128 new_value, Int128 write_mask); | |
570 | ||
457c360f FP |
571 | typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, |
572 | Int128 *ret_value); | |
573 | typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, | |
574 | Int128 new_value); | |
575 | ||
c7b95171 | 576 | typedef struct { |
8ceac5dc | 577 | const char *name; |
a88365c1 | 578 | riscv_csr_predicate_fn predicate; |
c7b95171 MC |
579 | riscv_csr_read_fn read; |
580 | riscv_csr_write_fn write; | |
581 | riscv_csr_op_fn op; | |
457c360f FP |
582 | riscv_csr_read128_fn read128; |
583 | riscv_csr_write128_fn write128; | |
c7b95171 MC |
584 | } riscv_csr_operations; |
585 | ||
56118ee8 BM |
586 | /* CSR function table constants */ |
587 | enum { | |
588 | CSR_TABLE_SIZE = 0x1000 | |
589 | }; | |
590 | ||
591 | /* CSR function table */ | |
6f03770d | 592 | extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; |
56118ee8 | 593 | |
c7b95171 MC |
594 | void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); |
595 | void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); | |
dc5bd18f | 596 | |
5371f5cd JW |
597 | void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); |
598 | ||
dc5bd18f | 599 | #endif /* RISCV_CPU_H */ |