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dc5bd18f MC |
1 | /* |
2 | * QEMU RISC-V CPU | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #ifndef RISCV_CPU_H | |
21 | #define RISCV_CPU_H | |
22 | ||
2e5b09fd | 23 | #include "hw/core/cpu.h" |
2b7168fc | 24 | #include "hw/registerfields.h" |
dc5bd18f | 25 | #include "exec/cpu-defs.h" |
69242e7e | 26 | #include "qemu/cpu-float.h" |
db1015e9 | 27 | #include "qom/object.h" |
961738ff | 28 | #include "qemu/int128.h" |
e91a7227 | 29 | #include "cpu_bits.h" |
6f23aaeb | 30 | #include "qapi/qapi-types-common.h" |
85840bd2 | 31 | #include "cpu-qom.h" |
dc5bd18f | 32 | |
74433bf0 RH |
33 | #define TCG_GUEST_DEFAULT_MO 0 |
34 | ||
62cf0245 AP |
35 | /* |
36 | * RISC-V-specific extra insn start words: | |
37 | * 1: Original instruction opcode | |
38 | */ | |
39 | #define TARGET_INSN_START_EXTRA_WORDS 1 | |
40 | ||
dc5bd18f MC |
41 | #define RV(x) ((target_ulong)1 << (x - 'A')) |
42 | ||
dd8f244f | 43 | /* Consider updating misa_ext_cfgs[] when adding new MISA bits here */ |
dc5bd18f | 44 | #define RVI RV('I') |
79f86934 | 45 | #define RVE RV('E') /* E and I are mutually exclusive */ |
dc5bd18f MC |
46 | #define RVM RV('M') |
47 | #define RVA RV('A') | |
48 | #define RVF RV('F') | |
49 | #define RVD RV('D') | |
ad9e5aa2 | 50 | #define RVV RV('V') |
dc5bd18f MC |
51 | #define RVC RV('C') |
52 | #define RVS RV('S') | |
53 | #define RVU RV('U') | |
af1fa003 | 54 | #define RVH RV('H') |
53dcea58 | 55 | #define RVJ RV('J') |
4f13abcb | 56 | #define RVG RV('G') |
dc5bd18f | 57 | |
dc5bd18f | 58 | |
a46d410c AP |
59 | /* Privileged specification version */ |
60 | enum { | |
61 | PRIV_VERSION_1_10_0 = 0, | |
62 | PRIV_VERSION_1_11_0, | |
3a4af26d | 63 | PRIV_VERSION_1_12_0, |
a46d410c | 64 | }; |
dc5bd18f | 65 | |
9ec6622d | 66 | #define VEXT_VERSION_1_00_0 0x00010000 |
32931383 | 67 | |
33a9a57d YJ |
68 | enum { |
69 | TRANSLATE_SUCCESS, | |
70 | TRANSLATE_FAIL, | |
71 | TRANSLATE_PMP_FAIL, | |
72 | TRANSLATE_G_STAGE_FAIL | |
73 | }; | |
74 | ||
42967f40 LZ |
75 | /* Extension context status */ |
76 | typedef enum { | |
77 | EXT_STATUS_DISABLED = 0, | |
78 | EXT_STATUS_INITIAL, | |
79 | EXT_STATUS_CLEAN, | |
80 | EXT_STATUS_DIRTY, | |
81 | } RISCVExtStatus; | |
82 | ||
dc5bd18f MC |
83 | #define MMU_USER_IDX 3 |
84 | ||
85 | #define MAX_RISCV_PMPS (16) | |
86 | ||
bbf3d1b4 | 87 | #if !defined(CONFIG_USER_ONLY) |
dc5bd18f | 88 | #include "pmp.h" |
95799e36 | 89 | #include "debug.h" |
bbf3d1b4 | 90 | #endif |
dc5bd18f | 91 | |
8a4b5257 | 92 | #define RV_VLEN_MAX 1024 |
3780e337 | 93 | #define RV_MAX_MHPMEVENTS 32 |
621f35bb | 94 | #define RV_MAX_MHPMCOUNTERS 32 |
ad9e5aa2 | 95 | |
33f1beaf FC |
96 | FIELD(VTYPE, VLMUL, 0, 3) |
97 | FIELD(VTYPE, VSEW, 3, 3) | |
3479a814 FC |
98 | FIELD(VTYPE, VTA, 6, 1) |
99 | FIELD(VTYPE, VMA, 7, 1) | |
33f1beaf FC |
100 | FIELD(VTYPE, VEDIV, 8, 2) |
101 | FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) | |
2b7168fc | 102 | |
3780e337 AP |
103 | typedef struct PMUCTRState { |
104 | /* Current value of a counter */ | |
105 | target_ulong mhpmcounter_val; | |
3b57254d | 106 | /* Current value of a counter in RV32 */ |
3780e337 AP |
107 | target_ulong mhpmcounterh_val; |
108 | /* Snapshot values of counter */ | |
109 | target_ulong mhpmcounter_prev; | |
110 | /* Snapshort value of a counter in RV32 */ | |
111 | target_ulong mhpmcounterh_prev; | |
112 | bool started; | |
14664483 AP |
113 | /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */ |
114 | target_ulong irq_overflow_left; | |
3780e337 AP |
115 | } PMUCTRState; |
116 | ||
1ea4a06a | 117 | struct CPUArchState { |
dc5bd18f | 118 | target_ulong gpr[32]; |
2b547084 | 119 | target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ |
ad9e5aa2 LZ |
120 | |
121 | /* vector coprocessor state. */ | |
122 | uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); | |
123 | target_ulong vxrm; | |
124 | target_ulong vxsat; | |
125 | target_ulong vl; | |
126 | target_ulong vstart; | |
127 | target_ulong vtype; | |
d96a271a | 128 | bool vill; |
ad9e5aa2 | 129 | |
dc5bd18f MC |
130 | target_ulong pc; |
131 | target_ulong load_res; | |
132 | target_ulong load_val; | |
133 | ||
04bc3027 PMD |
134 | /* Floating-Point state */ |
135 | uint64_t fpr[32]; /* assume both F and D extensions */ | |
dc5bd18f | 136 | target_ulong frm; |
04bc3027 | 137 | float_status fp_status; |
dc5bd18f MC |
138 | |
139 | target_ulong badaddr; | |
62cf0245 | 140 | target_ulong bins; |
48eaeb56 | 141 | |
36a18664 | 142 | target_ulong guest_phys_fault_addr; |
dc5bd18f | 143 | |
dc5bd18f | 144 | target_ulong priv_ver; |
d2c1a177 | 145 | target_ulong bext_ver; |
32931383 | 146 | target_ulong vext_ver; |
e91a7227 RH |
147 | |
148 | /* RISCVMXL, but uint32_t for vmstate migration */ | |
149 | uint32_t misa_mxl; /* current mxl */ | |
150 | uint32_t misa_mxl_max; /* max mxl for this cpu */ | |
151 | uint32_t misa_ext; /* current extensions */ | |
152 | uint32_t misa_ext_mask; /* max ext for this cpu */ | |
440544e1 | 153 | uint32_t xl; /* current xlen */ |
dc5bd18f | 154 | |
b3a5d1fb FP |
155 | /* 128-bit helpers upper part return value */ |
156 | target_ulong retxh; | |
157 | ||
ce3af0bb WL |
158 | target_ulong jvt; |
159 | ||
5836c3ec KC |
160 | #ifdef CONFIG_USER_ONLY |
161 | uint32_t elf_flags; | |
162 | #endif | |
163 | ||
dc5bd18f MC |
164 | #ifndef CONFIG_USER_ONLY |
165 | target_ulong priv; | |
ef6bb7b6 | 166 | /* This contains QEMU specific information about the virt state. */ |
b3c5077b | 167 | bool virt_enabled; |
cd032fe7 | 168 | target_ulong geilen; |
277b210d | 169 | uint64_t resetvec; |
dc5bd18f MC |
170 | |
171 | target_ulong mhartid; | |
284d697c YJ |
172 | /* |
173 | * For RV32 this is 32-bit mstatus and 32-bit mstatush. | |
174 | * For RV64 this is a 64-bit mstatus. | |
175 | */ | |
176 | uint64_t mstatus; | |
85ba724f | 177 | |
d028ac75 | 178 | uint64_t mip; |
33fe584f AF |
179 | /* |
180 | * MIP contains the software writable version of SEIP ORed with the | |
181 | * external interrupt value. The MIP register is always up-to-date. | |
182 | * To keep track of the current source, we also save booleans of the values | |
183 | * here. | |
184 | */ | |
185 | bool external_seip; | |
186 | bool software_seip; | |
66e594f2 | 187 | |
d028ac75 | 188 | uint64_t miclaim; |
85ba724f | 189 | |
d028ac75 AP |
190 | uint64_t mie; |
191 | uint64_t mideleg; | |
dc5bd18f | 192 | |
dc5bd18f | 193 | target_ulong satp; /* since: priv-1.10.0 */ |
ac12b601 | 194 | target_ulong stval; |
dc5bd18f MC |
195 | target_ulong medeleg; |
196 | ||
197 | target_ulong stvec; | |
198 | target_ulong sepc; | |
199 | target_ulong scause; | |
200 | ||
201 | target_ulong mtvec; | |
202 | target_ulong mepc; | |
203 | target_ulong mcause; | |
204 | target_ulong mtval; /* since: priv-1.10.0 */ | |
205 | ||
43dc93af AP |
206 | /* Machine and Supervisor interrupt priorities */ |
207 | uint8_t miprio[64]; | |
208 | uint8_t siprio[64]; | |
209 | ||
d1ceff40 AP |
210 | /* AIA CSRs */ |
211 | target_ulong miselect; | |
212 | target_ulong siselect; | |
213 | ||
bd023ce3 AF |
214 | /* Hypervisor CSRs */ |
215 | target_ulong hstatus; | |
216 | target_ulong hedeleg; | |
d028ac75 | 217 | uint64_t hideleg; |
bd023ce3 AF |
218 | target_ulong hcounteren; |
219 | target_ulong htval; | |
220 | target_ulong htinst; | |
221 | target_ulong hgatp; | |
cd032fe7 AP |
222 | target_ulong hgeie; |
223 | target_ulong hgeip; | |
c6957248 | 224 | uint64_t htimedelta; |
bd023ce3 | 225 | |
43dc93af | 226 | /* Hypervisor controlled virtual interrupt priorities */ |
2b602398 | 227 | target_ulong hvictl; |
43dc93af AP |
228 | uint8_t hviprio[64]; |
229 | ||
2c64ab66 FP |
230 | /* Upper 64-bits of 128-bit CSRs */ |
231 | uint64_t mscratchh; | |
232 | uint64_t sscratchh; | |
233 | ||
bd023ce3 | 234 | /* Virtual CSRs */ |
284d697c YJ |
235 | /* |
236 | * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. | |
237 | * For RV64 this is a 64-bit vsstatus. | |
238 | */ | |
239 | uint64_t vsstatus; | |
bd023ce3 AF |
240 | target_ulong vstvec; |
241 | target_ulong vsscratch; | |
242 | target_ulong vsepc; | |
243 | target_ulong vscause; | |
244 | target_ulong vstval; | |
245 | target_ulong vsatp; | |
246 | ||
d1ceff40 AP |
247 | /* AIA VS-mode CSRs */ |
248 | target_ulong vsiselect; | |
249 | ||
bd023ce3 AF |
250 | target_ulong mtval2; |
251 | target_ulong mtinst; | |
252 | ||
66e594f2 AF |
253 | /* HS Backup CSRs */ |
254 | target_ulong stvec_hs; | |
255 | target_ulong sscratch_hs; | |
256 | target_ulong sepc_hs; | |
257 | target_ulong scause_hs; | |
258 | target_ulong stval_hs; | |
259 | target_ulong satp_hs; | |
284d697c | 260 | uint64_t mstatus_hs; |
66e594f2 | 261 | |
3b57254d WL |
262 | /* |
263 | * Signals whether the current exception occurred with two-stage address | |
264 | * translation active. | |
265 | */ | |
ec352d0c | 266 | bool two_stage_lookup; |
8e2aa21b AP |
267 | /* |
268 | * Signals whether the current exception occurred while doing two-stage | |
269 | * address translation for the VS-stage page table walk. | |
270 | */ | |
271 | bool two_stage_indirect_lookup; | |
ec352d0c | 272 | |
8c59f5c1 MC |
273 | target_ulong scounteren; |
274 | target_ulong mcounteren; | |
dc5bd18f | 275 | |
b1675eeb AP |
276 | target_ulong mcountinhibit; |
277 | ||
3780e337 AP |
278 | /* PMU counter state */ |
279 | PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; | |
621f35bb | 280 | |
3b57254d | 281 | /* PMU event selector configured values. First three are unused */ |
621f35bb AP |
282 | target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; |
283 | ||
3b57254d | 284 | /* PMU event selector configured values for RV32 */ |
14664483 AP |
285 | target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; |
286 | ||
dc5bd18f MC |
287 | target_ulong sscratch; |
288 | target_ulong mscratch; | |
289 | ||
43888c2f AP |
290 | /* Sstc CSRs */ |
291 | uint64_t stimecmp; | |
292 | ||
3ec0fe18 AP |
293 | uint64_t vstimecmp; |
294 | ||
dc5bd18f MC |
295 | /* physical memory protection */ |
296 | pmp_table_t pmp_state; | |
2582a95c | 297 | target_ulong mseccfg; |
753e3fe2 | 298 | |
95799e36 BM |
299 | /* trigger module */ |
300 | target_ulong trigger_cur; | |
9495c488 FC |
301 | target_ulong tdata1[RV_MAX_TRIGGERS]; |
302 | target_ulong tdata2[RV_MAX_TRIGGERS]; | |
303 | target_ulong tdata3[RV_MAX_TRIGGERS]; | |
304 | struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; | |
305 | struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; | |
5a4ae64c LZ |
306 | QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; |
307 | int64_t last_icount; | |
577f0286 | 308 | bool itrigger_enabled; |
95799e36 | 309 | |
c6957248 | 310 | /* machine specific rdtime callback */ |
e2f01f3c FC |
311 | uint64_t (*rdtime_fn)(void *); |
312 | void *rdtime_fn_arg; | |
c6957248 | 313 | |
69077dd6 AP |
314 | /* machine specific AIA ireg read-modify-write callback */ |
315 | #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ | |
316 | ((((__xlen) & 0xff) << 24) | \ | |
317 | (((__vgein) & 0x3f) << 20) | \ | |
318 | (((__virt) & 0x1) << 18) | \ | |
319 | (((__priv) & 0x3) << 16) | \ | |
320 | (__isel & 0xffff)) | |
321 | #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) | |
322 | #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) | |
323 | #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) | |
324 | #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) | |
325 | #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) | |
326 | int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, | |
327 | target_ulong *val, target_ulong new_val, target_ulong write_mask); | |
328 | void *aia_ireg_rmw_fn_arg[4]; | |
329 | ||
753e3fe2 JW |
330 | /* True if in debugger mode. */ |
331 | bool debugger; | |
4bbe8033 AB |
332 | |
333 | /* | |
334 | * CSRs for PointerMasking extension | |
335 | */ | |
336 | target_ulong mmte; | |
337 | target_ulong mpmmask; | |
338 | target_ulong mpmbase; | |
339 | target_ulong spmmask; | |
340 | target_ulong spmbase; | |
341 | target_ulong upmmask; | |
342 | target_ulong upmbase; | |
29a9ec9b AP |
343 | |
344 | /* CSRs for execution enviornment configuration */ | |
345 | uint64_t menvcfg; | |
3bee0e40 MC |
346 | uint64_t mstateen[SMSTATEEN_MAX_COUNT]; |
347 | uint64_t hstateen[SMSTATEEN_MAX_COUNT]; | |
348 | uint64_t sstateen[SMSTATEEN_MAX_COUNT]; | |
29a9ec9b AP |
349 | target_ulong senvcfg; |
350 | uint64_t henvcfg; | |
dc5bd18f | 351 | #endif |
40bfa5f6 LZ |
352 | target_ulong cur_pmmask; |
353 | target_ulong cur_pmbase; | |
dc5bd18f | 354 | |
dc5bd18f | 355 | /* Fields from here on are preserved across CPU reset. */ |
43888c2f | 356 | QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ |
3ec0fe18 AP |
357 | QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */ |
358 | bool vstime_irq; | |
ad40be27 YJ |
359 | |
360 | hwaddr kernel_addr; | |
361 | hwaddr fdt_addr; | |
27abe66f YJ |
362 | |
363 | /* kvm timer */ | |
364 | bool kvm_timer_dirty; | |
365 | uint64_t kvm_timer_time; | |
366 | uint64_t kvm_timer_compare; | |
367 | uint64_t kvm_timer_state; | |
368 | uint64_t kvm_timer_frequency; | |
dc5bd18f MC |
369 | }; |
370 | ||
6f23aaeb AG |
371 | /* |
372 | * map is a 16-bit bitmap: the most significant set bit in map is the maximum | |
6df3747a AG |
373 | * satp mode that is supported. It may be chosen by the user and must respect |
374 | * what qemu implements (valid_1_10_32/64) and what the hw is capable of | |
375 | * (supported bitmap below). | |
6f23aaeb AG |
376 | * |
377 | * init is a 16-bit bitmap used to make sure the user selected a correct | |
378 | * configuration as per the specification. | |
6df3747a AG |
379 | * |
380 | * supported is a 16-bit bitmap used to reflect the hw capabilities. | |
6f23aaeb AG |
381 | */ |
382 | typedef struct { | |
6df3747a | 383 | uint16_t map, init, supported; |
6f23aaeb AG |
384 | } RISCVSATPMap; |
385 | ||
466292bd | 386 | struct RISCVCPUConfig { |
466292bd PT |
387 | bool ext_zba; |
388 | bool ext_zbb; | |
389 | bool ext_zbc; | |
eef82872 WL |
390 | bool ext_zbkb; |
391 | bool ext_zbkc; | |
392 | bool ext_zbkx; | |
466292bd | 393 | bool ext_zbs; |
2288a5ce WL |
394 | bool ext_zca; |
395 | bool ext_zcb; | |
396 | bool ext_zcd; | |
00d312bd | 397 | bool ext_zce; |
2288a5ce WL |
398 | bool ext_zcf; |
399 | bool ext_zcmp; | |
400 | bool ext_zcmt; | |
eef82872 WL |
401 | bool ext_zk; |
402 | bool ext_zkn; | |
403 | bool ext_zknd; | |
404 | bool ext_zkne; | |
405 | bool ext_zknh; | |
406 | bool ext_zkr; | |
407 | bool ext_zks; | |
408 | bool ext_zksed; | |
409 | bool ext_zksh; | |
410 | bool ext_zkt; | |
466292bd PT |
411 | bool ext_ifencei; |
412 | bool ext_icsr; | |
e05da09b | 413 | bool ext_icbom; |
a939c500 | 414 | bool ext_icboz; |
b8e1f32c | 415 | bool ext_zicond; |
4696f0ab | 416 | bool ext_zihintpause; |
3bee0e40 | 417 | bool ext_smstateen; |
43888c2f | 418 | bool ext_sstc; |
0d190bd3 | 419 | bool ext_svadu; |
c5d77ddd | 420 | bool ext_svinval; |
05e6ca5e GR |
421 | bool ext_svnapot; |
422 | bool ext_svpbmt; | |
89ffdcec | 423 | bool ext_zdinx; |
260b594d | 424 | bool ext_zawrs; |
466292bd PT |
425 | bool ext_zfh; |
426 | bool ext_zfhmin; | |
89ffdcec WL |
427 | bool ext_zfinx; |
428 | bool ext_zhinx; | |
429 | bool ext_zhinxmin; | |
466292bd PT |
430 | bool ext_zve32f; |
431 | bool ext_zve64f; | |
a7336161 | 432 | bool ext_zve64d; |
de799beb | 433 | bool ext_zmmul; |
a7336161 WL |
434 | bool ext_zvfh; |
435 | bool ext_zvfhmin; | |
dc9acc9c AP |
436 | bool ext_smaia; |
437 | bool ext_ssaia; | |
14664483 | 438 | bool ext_sscofpmf; |
f1eed927 | 439 | bool rvv_ta_all_1s; |
355d5584 | 440 | bool rvv_ma_all_1s; |
466292bd | 441 | |
9951ba94 FC |
442 | uint32_t mvendorid; |
443 | uint64_t marchid; | |
075eeda9 | 444 | uint64_t mimpid; |
9951ba94 | 445 | |
0d429bd2 | 446 | /* Vendor-specific custom extensions */ |
c9410a68 | 447 | bool ext_xtheadba; |
426c0491 | 448 | bool ext_xtheadbb; |
fa134585 | 449 | bool ext_xtheadbs; |
49a7f3aa | 450 | bool ext_xtheadcmo; |
32909338 | 451 | bool ext_xtheadcondmov; |
d4d90115 | 452 | bool ext_xtheadfmemidx; |
578086ba | 453 | bool ext_xtheadfmv; |
b8a5832b | 454 | bool ext_xtheadmac; |
45f9df86 | 455 | bool ext_xtheadmemidx; |
af99aa72 | 456 | bool ext_xtheadmempair; |
134c3ffa | 457 | bool ext_xtheadsync; |
0d429bd2 PT |
458 | bool ext_XVentanaCondOps; |
459 | ||
18d6d89e | 460 | uint8_t pmu_num; |
466292bd PT |
461 | char *priv_spec; |
462 | char *user_spec; | |
463 | char *bext_spec; | |
464 | char *vext_spec; | |
465 | uint16_t vlen; | |
466 | uint16_t elen; | |
e05da09b | 467 | uint16_t cbom_blocksize; |
a939c500 | 468 | uint16_t cboz_blocksize; |
466292bd PT |
469 | bool mmu; |
470 | bool pmp; | |
471 | bool epmp; | |
1acdb3b0 | 472 | bool debug; |
54bd9b6e | 473 | bool misa_w; |
a4a9a443 TO |
474 | |
475 | bool short_isa_string; | |
6f23aaeb AG |
476 | |
477 | #ifndef CONFIG_USER_ONLY | |
478 | RISCVSATPMap satp_mode; | |
479 | #endif | |
466292bd PT |
480 | }; |
481 | ||
482 | typedef struct RISCVCPUConfig RISCVCPUConfig; | |
483 | ||
3b57254d | 484 | /* |
dc5bd18f MC |
485 | * RISCVCPU: |
486 | * @env: #CPURISCVState | |
487 | * | |
488 | * A RISCV CPU. | |
489 | */ | |
b36e239e | 490 | struct ArchCPU { |
3b57254d | 491 | /* < private > */ |
dc5bd18f | 492 | CPUState parent_obj; |
3b57254d | 493 | /* < public > */ |
5b146dc7 | 494 | CPUNegativeOffsetState neg; |
dc5bd18f | 495 | CPURISCVState env; |
c4e95030 | 496 | |
b93777e1 | 497 | char *dyn_csr_xml; |
719d3561 | 498 | char *dyn_vreg_xml; |
b93777e1 | 499 | |
c4e95030 | 500 | /* Configuration Settings */ |
466292bd | 501 | RISCVCPUConfig cfg; |
14664483 AP |
502 | |
503 | QEMUTimer *pmu_timer; | |
504 | /* A bitmask of Available programmable counters */ | |
505 | uint32_t pmu_avail_ctrs; | |
506 | /* Mapping of events to counters */ | |
507 | GHashTable *pmu_event_ctr_map; | |
db1015e9 | 508 | }; |
dc5bd18f | 509 | |
dc5bd18f MC |
510 | static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) |
511 | { | |
e91a7227 | 512 | return (env->misa_ext & ext) != 0; |
dc5bd18f MC |
513 | } |
514 | ||
dc5bd18f | 515 | #include "cpu_user.h" |
dc5bd18f MC |
516 | |
517 | extern const char * const riscv_int_regnames[]; | |
2b547084 | 518 | extern const char * const riscv_int_regnamesh[]; |
dc5bd18f | 519 | extern const char * const riscv_fpr_regnames[]; |
dc5bd18f | 520 | |
c51a3f5d | 521 | const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); |
dc5bd18f | 522 | void riscv_cpu_do_interrupt(CPUState *cpu); |
43a96588 | 523 | int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, |
1af0006a | 524 | int cpuid, DumpState *s); |
43a96588 | 525 | int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, |
1af0006a | 526 | int cpuid, DumpState *s); |
a010bdbe | 527 | int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); |
dc5bd18f | 528 | int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); |
43dc93af AP |
529 | int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); |
530 | uint8_t riscv_cpu_default_priority(int irq); | |
8f42415f | 531 | uint64_t riscv_cpu_all_pending(CPURISCVState *env); |
43dc93af AP |
532 | int riscv_cpu_mirq_pending(CPURISCVState *env); |
533 | int riscv_cpu_sirq_pending(CPURISCVState *env); | |
534 | int riscv_cpu_vsirq_pending(CPURISCVState *env); | |
b345b480 | 535 | bool riscv_cpu_fp_enabled(CPURISCVState *env); |
cd032fe7 AP |
536 | target_ulong riscv_cpu_get_geilen(CPURISCVState *env); |
537 | void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); | |
61b4b69d | 538 | bool riscv_cpu_vector_enabled(CPURISCVState *env); |
ef6bb7b6 | 539 | void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); |
dc5bd18f | 540 | int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); |
8905770b | 541 | G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, |
246f8796 WL |
542 | MMUAccessType access_type, |
543 | int mmu_idx, uintptr_t retaddr); | |
8a4ca3c1 RH |
544 | bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
545 | MMUAccessType access_type, int mmu_idx, | |
546 | bool probe, uintptr_t retaddr); | |
dc5bd18f | 547 | char *riscv_isa_string(RISCVCPU *cpu); |
0442428a | 548 | void riscv_cpu_list(void); |
dc5bd18f | 549 | |
dc5bd18f MC |
550 | #define cpu_list riscv_cpu_list |
551 | #define cpu_mmu_index riscv_cpu_mmu_index | |
552 | ||
85ba724f | 553 | #ifndef CONFIG_USER_ONLY |
d90ebc47 PMD |
554 | void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, |
555 | vaddr addr, unsigned size, | |
556 | MMUAccessType access_type, | |
557 | int mmu_idx, MemTxAttrs attrs, | |
558 | MemTxResult response, uintptr_t retaddr); | |
6d2d454a | 559 | hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); |
17b3c353 | 560 | bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); |
66e594f2 | 561 | void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); |
d028ac75 | 562 | int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); |
bbb9fc25 WL |
563 | uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, |
564 | uint64_t value); | |
85ba724f | 565 | #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ |
e2f01f3c FC |
566 | void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), |
567 | void *arg); | |
69077dd6 AP |
568 | void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, |
569 | int (*rmw_fn)(void *arg, | |
570 | target_ulong reg, | |
571 | target_ulong *val, | |
572 | target_ulong new_val, | |
573 | target_ulong write_mask), | |
574 | void *rmw_fn_arg); | |
ce3af0bb WL |
575 | |
576 | RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit); | |
85ba724f | 577 | #endif |
fb738839 | 578 | void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); |
dc5bd18f MC |
579 | |
580 | void riscv_translate_init(void); | |
8905770b MAL |
581 | G_NORETURN void riscv_raise_exception(CPURISCVState *env, |
582 | uint32_t exception, uintptr_t pc); | |
dc5bd18f | 583 | |
fb738839 MC |
584 | target_ulong riscv_cpu_get_fflags(CPURISCVState *env); |
585 | void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); | |
dc5bd18f | 586 | |
2b7168fc LZ |
587 | #include "exec/cpu-all.h" |
588 | ||
61d56494 | 589 | FIELD(TB_FLAGS, MEM_IDX, 0, 3) |
ebd47648 LZ |
590 | FIELD(TB_FLAGS, FS, 3, 2) |
591 | /* Vector flags */ | |
592 | FIELD(TB_FLAGS, VS, 5, 2) | |
593 | FIELD(TB_FLAGS, LMUL, 7, 3) | |
594 | FIELD(TB_FLAGS, SEW, 10, 3) | |
595 | FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1) | |
596 | FIELD(TB_FLAGS, VILL, 14, 1) | |
0f58cbbe | 597 | FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1) |
92371bd9 | 598 | /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ |
25f3ddff | 599 | FIELD(TB_FLAGS, XL, 16, 2) |
0774a7a1 | 600 | /* If PointerMasking should be applied */ |
25f3ddff RH |
601 | FIELD(TB_FLAGS, PM_MASK_ENABLED, 18, 1) |
602 | FIELD(TB_FLAGS, PM_BASE_ENABLED, 19, 1) | |
603 | FIELD(TB_FLAGS, VTA, 20, 1) | |
604 | FIELD(TB_FLAGS, VMA, 21, 1) | |
2c9d7471 | 605 | /* Native debug itrigger */ |
25f3ddff | 606 | FIELD(TB_FLAGS, ITRIGGER, 22, 1) |
f1966390 | 607 | /* Virtual mode enabled */ |
25f3ddff | 608 | FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1) |
0f58cbbe | 609 | FIELD(TB_FLAGS, PRIV, 24, 2) |
2b7168fc | 610 | |
db23e5d9 RH |
611 | #ifdef TARGET_RISCV32 |
612 | #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) | |
613 | #else | |
614 | static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) | |
615 | { | |
616 | return env->misa_mxl; | |
617 | } | |
618 | #endif | |
2b602398 | 619 | #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) |
51ae0cab | 620 | |
d4ea7117 DHB |
621 | static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) |
622 | { | |
623 | return &env_archcpu(env)->cfg; | |
624 | } | |
625 | ||
440544e1 LZ |
626 | #if defined(TARGET_RISCV32) |
627 | #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) | |
628 | #else | |
629 | static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) | |
630 | { | |
631 | RISCVMXL xl = env->misa_mxl; | |
632 | #if !defined(CONFIG_USER_ONLY) | |
633 | /* | |
634 | * When emulating a 32-bit-only cpu, use RV32. | |
635 | * When emulating a 64-bit cpu, and MXL has been reduced to RV32, | |
636 | * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened | |
637 | * back to RV64 for lower privs. | |
638 | */ | |
639 | if (xl != MXL_RV32) { | |
640 | switch (env->priv) { | |
641 | case PRV_M: | |
642 | break; | |
643 | case PRV_U: | |
644 | xl = get_field(env->mstatus, MSTATUS64_UXL); | |
645 | break; | |
44b8f74b | 646 | default: /* PRV_S */ |
440544e1 LZ |
647 | xl = get_field(env->mstatus, MSTATUS64_SXL); |
648 | break; | |
649 | } | |
650 | } | |
651 | #endif | |
652 | return xl; | |
653 | } | |
654 | #endif | |
655 | ||
31961cfe LZ |
656 | static inline int riscv_cpu_xlen(CPURISCVState *env) |
657 | { | |
658 | return 16 << env->xl; | |
659 | } | |
660 | ||
05e6ca5e GR |
661 | #ifdef TARGET_RISCV32 |
662 | #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) | |
663 | #else | |
664 | static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) | |
665 | { | |
666 | #ifdef CONFIG_USER_ONLY | |
667 | return env->misa_mxl; | |
668 | #else | |
669 | return get_field(env->mstatus, MSTATUS64_SXL); | |
670 | #endif | |
671 | } | |
672 | #endif | |
673 | ||
2b7168fc | 674 | /* |
a689a82b FC |
675 | * Encode LMUL to lmul as follows: |
676 | * LMUL vlmul lmul | |
677 | * 1 000 0 | |
678 | * 2 001 1 | |
679 | * 4 010 2 | |
680 | * 8 011 3 | |
681 | * - 100 - | |
682 | * 1/8 101 -3 | |
683 | * 1/4 110 -2 | |
684 | * 1/2 111 -1 | |
685 | * | |
686 | * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) | |
687 | * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 | |
688 | * => VLMAX = vlen >> (1 + 3 - (-3)) | |
689 | * = 256 >> 7 | |
690 | * = 2 | |
2b7168fc LZ |
691 | */ |
692 | static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) | |
693 | { | |
a689a82b FC |
694 | uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); |
695 | int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); | |
2b7168fc LZ |
696 | return cpu->cfg.vlen >> (sew + 3 - lmul); |
697 | } | |
698 | ||
53677acf RH |
699 | void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, |
700 | target_ulong *cs_base, uint32_t *pflags); | |
dc5bd18f | 701 | |
40bfa5f6 LZ |
702 | void riscv_cpu_update_mask(CPURISCVState *env); |
703 | ||
533c91e8 AF |
704 | RISCVException riscv_csrrw(CPURISCVState *env, int csrno, |
705 | target_ulong *ret_value, | |
706 | target_ulong new_value, target_ulong write_mask); | |
707 | RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, | |
708 | target_ulong *ret_value, | |
709 | target_ulong new_value, | |
710 | target_ulong write_mask); | |
c7b95171 | 711 | |
fb738839 MC |
712 | static inline void riscv_csr_write(CPURISCVState *env, int csrno, |
713 | target_ulong val) | |
c7b95171 MC |
714 | { |
715 | riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); | |
716 | } | |
717 | ||
fb738839 | 718 | static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) |
c7b95171 MC |
719 | { |
720 | target_ulong val = 0; | |
721 | riscv_csrrw(env, csrno, &val, 0, 0); | |
722 | return val; | |
723 | } | |
724 | ||
0e62f92e AF |
725 | typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, |
726 | int csrno); | |
605def6e AF |
727 | typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, |
728 | target_ulong *ret_value); | |
729 | typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, | |
730 | target_ulong new_value); | |
731 | typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, | |
732 | target_ulong *ret_value, | |
733 | target_ulong new_value, | |
734 | target_ulong write_mask); | |
c7b95171 | 735 | |
961738ff FP |
736 | RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, |
737 | Int128 *ret_value, | |
738 | Int128 new_value, Int128 write_mask); | |
739 | ||
457c360f FP |
740 | typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, |
741 | Int128 *ret_value); | |
742 | typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, | |
743 | Int128 new_value); | |
744 | ||
c7b95171 | 745 | typedef struct { |
8ceac5dc | 746 | const char *name; |
a88365c1 | 747 | riscv_csr_predicate_fn predicate; |
c7b95171 MC |
748 | riscv_csr_read_fn read; |
749 | riscv_csr_write_fn write; | |
750 | riscv_csr_op_fn op; | |
457c360f FP |
751 | riscv_csr_read128_fn read128; |
752 | riscv_csr_write128_fn write128; | |
a4b2fa43 AP |
753 | /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ |
754 | uint32_t min_priv_ver; | |
c7b95171 MC |
755 | } riscv_csr_operations; |
756 | ||
56118ee8 BM |
757 | /* CSR function table constants */ |
758 | enum { | |
759 | CSR_TABLE_SIZE = 0x1000 | |
760 | }; | |
761 | ||
3b57254d | 762 | /* |
14664483 AP |
763 | * The event id are encoded based on the encoding specified in the |
764 | * SBI specification v0.3 | |
765 | */ | |
766 | ||
767 | enum riscv_pmu_event_idx { | |
768 | RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01, | |
769 | RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02, | |
770 | RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019, | |
771 | RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B, | |
772 | RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021, | |
773 | }; | |
774 | ||
56118ee8 | 775 | /* CSR function table */ |
6f03770d | 776 | extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; |
56118ee8 | 777 | |
6f23aaeb AG |
778 | extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; |
779 | ||
c7b95171 MC |
780 | void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); |
781 | void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); | |
dc5bd18f | 782 | |
5371f5cd JW |
783 | void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); |
784 | ||
6f23aaeb AG |
785 | uint8_t satp_mode_max_from_map(uint32_t map); |
786 | const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); | |
787 | ||
dc5bd18f | 788 | #endif /* RISCV_CPU_H */ |