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dc5bd18f MC |
1 | /* |
2 | * QEMU RISC-V CPU | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #ifndef RISCV_CPU_H | |
21 | #define RISCV_CPU_H | |
22 | ||
2e5b09fd | 23 | #include "hw/core/cpu.h" |
dc5bd18f | 24 | #include "exec/cpu-defs.h" |
135b03cb | 25 | #include "fpu/softfloat-types.h" |
dc5bd18f | 26 | |
74433bf0 RH |
27 | #define TCG_GUEST_DEFAULT_MO 0 |
28 | ||
dc5bd18f MC |
29 | #define TYPE_RISCV_CPU "riscv-cpu" |
30 | ||
31 | #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU | |
32 | #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) | |
0dacec87 | 33 | #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU |
dc5bd18f MC |
34 | |
35 | #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") | |
8903bf6e AF |
36 | #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") |
37 | #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") | |
36b80ad9 | 38 | #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") |
dc5bd18f | 39 | #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") |
d784733b | 40 | #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") |
dc5bd18f MC |
41 | #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") |
42 | #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") | |
43 | #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") | |
44 | ||
45 | #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) | |
46 | #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) | |
47 | ||
48 | #if defined(TARGET_RISCV32) | |
49 | #define RVXLEN RV32 | |
50 | #elif defined(TARGET_RISCV64) | |
51 | #define RVXLEN RV64 | |
52 | #endif | |
53 | ||
54 | #define RV(x) ((target_ulong)1 << (x - 'A')) | |
55 | ||
56 | #define RVI RV('I') | |
79f86934 | 57 | #define RVE RV('E') /* E and I are mutually exclusive */ |
dc5bd18f MC |
58 | #define RVM RV('M') |
59 | #define RVA RV('A') | |
60 | #define RVF RV('F') | |
61 | #define RVD RV('D') | |
ad9e5aa2 | 62 | #define RVV RV('V') |
dc5bd18f MC |
63 | #define RVC RV('C') |
64 | #define RVS RV('S') | |
65 | #define RVU RV('U') | |
af1fa003 | 66 | #define RVH RV('H') |
dc5bd18f MC |
67 | |
68 | /* S extension denotes that Supervisor mode exists, however it is possible | |
69 | to have a core that support S mode but does not have an MMU and there | |
70 | is currently no bit in misa to indicate whether an MMU exists or not | |
a88365c1 | 71 | so a cpu features bitfield is required, likewise for optional PMP support */ |
dc5bd18f | 72 | enum { |
a88365c1 | 73 | RISCV_FEATURE_MMU, |
f18637cd MC |
74 | RISCV_FEATURE_PMP, |
75 | RISCV_FEATURE_MISA | |
dc5bd18f MC |
76 | }; |
77 | ||
dc5bd18f | 78 | #define PRIV_VERSION_1_10_0 0x00011000 |
6729dbbd | 79 | #define PRIV_VERSION_1_11_0 0x00011100 |
dc5bd18f | 80 | |
32931383 LZ |
81 | #define VEXT_VERSION_0_07_1 0x00000701 |
82 | ||
1f447aec | 83 | #define TRANSLATE_PMP_FAIL 2 |
dc5bd18f MC |
84 | #define TRANSLATE_FAIL 1 |
85 | #define TRANSLATE_SUCCESS 0 | |
dc5bd18f MC |
86 | #define MMU_USER_IDX 3 |
87 | ||
88 | #define MAX_RISCV_PMPS (16) | |
89 | ||
90 | typedef struct CPURISCVState CPURISCVState; | |
91 | ||
92 | #include "pmp.h" | |
93 | ||
ad9e5aa2 LZ |
94 | #define RV_VLEN_MAX 512 |
95 | ||
dc5bd18f MC |
96 | struct CPURISCVState { |
97 | target_ulong gpr[32]; | |
98 | uint64_t fpr[32]; /* assume both F and D extensions */ | |
ad9e5aa2 LZ |
99 | |
100 | /* vector coprocessor state. */ | |
101 | uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); | |
102 | target_ulong vxrm; | |
103 | target_ulong vxsat; | |
104 | target_ulong vl; | |
105 | target_ulong vstart; | |
106 | target_ulong vtype; | |
107 | ||
dc5bd18f MC |
108 | target_ulong pc; |
109 | target_ulong load_res; | |
110 | target_ulong load_val; | |
111 | ||
112 | target_ulong frm; | |
113 | ||
114 | target_ulong badaddr; | |
36a18664 | 115 | target_ulong guest_phys_fault_addr; |
dc5bd18f | 116 | |
dc5bd18f | 117 | target_ulong priv_ver; |
32931383 | 118 | target_ulong vext_ver; |
dc5bd18f | 119 | target_ulong misa; |
f18637cd | 120 | target_ulong misa_mask; |
dc5bd18f MC |
121 | |
122 | uint32_t features; | |
123 | ||
5836c3ec KC |
124 | #ifdef CONFIG_USER_ONLY |
125 | uint32_t elf_flags; | |
126 | #endif | |
127 | ||
dc5bd18f MC |
128 | #ifndef CONFIG_USER_ONLY |
129 | target_ulong priv; | |
ef6bb7b6 AF |
130 | /* This contains QEMU specific information about the virt state. */ |
131 | target_ulong virt; | |
dc5bd18f MC |
132 | target_ulong resetvec; |
133 | ||
134 | target_ulong mhartid; | |
135 | target_ulong mstatus; | |
85ba724f | 136 | |
02861613 | 137 | target_ulong mip; |
66e594f2 | 138 | |
551fa7e8 AF |
139 | #ifdef TARGET_RISCV32 |
140 | target_ulong mstatush; | |
141 | #endif | |
142 | ||
e3e7039c | 143 | uint32_t miclaim; |
85ba724f | 144 | |
dc5bd18f MC |
145 | target_ulong mie; |
146 | target_ulong mideleg; | |
147 | ||
148 | target_ulong sptbr; /* until: priv-1.9.1 */ | |
149 | target_ulong satp; /* since: priv-1.10.0 */ | |
150 | target_ulong sbadaddr; | |
151 | target_ulong mbadaddr; | |
152 | target_ulong medeleg; | |
153 | ||
154 | target_ulong stvec; | |
155 | target_ulong sepc; | |
156 | target_ulong scause; | |
157 | ||
158 | target_ulong mtvec; | |
159 | target_ulong mepc; | |
160 | target_ulong mcause; | |
161 | target_ulong mtval; /* since: priv-1.10.0 */ | |
162 | ||
bd023ce3 AF |
163 | /* Hypervisor CSRs */ |
164 | target_ulong hstatus; | |
165 | target_ulong hedeleg; | |
166 | target_ulong hideleg; | |
167 | target_ulong hcounteren; | |
168 | target_ulong htval; | |
169 | target_ulong htinst; | |
170 | target_ulong hgatp; | |
c6957248 | 171 | uint64_t htimedelta; |
bd023ce3 AF |
172 | |
173 | /* Virtual CSRs */ | |
174 | target_ulong vsstatus; | |
175 | target_ulong vstvec; | |
176 | target_ulong vsscratch; | |
177 | target_ulong vsepc; | |
178 | target_ulong vscause; | |
179 | target_ulong vstval; | |
180 | target_ulong vsatp; | |
551fa7e8 AF |
181 | #ifdef TARGET_RISCV32 |
182 | target_ulong vsstatush; | |
183 | #endif | |
bd023ce3 AF |
184 | |
185 | target_ulong mtval2; | |
186 | target_ulong mtinst; | |
187 | ||
66e594f2 AF |
188 | /* HS Backup CSRs */ |
189 | target_ulong stvec_hs; | |
190 | target_ulong sscratch_hs; | |
191 | target_ulong sepc_hs; | |
192 | target_ulong scause_hs; | |
193 | target_ulong stval_hs; | |
194 | target_ulong satp_hs; | |
195 | target_ulong mstatus_hs; | |
551fa7e8 AF |
196 | #ifdef TARGET_RISCV32 |
197 | target_ulong mstatush_hs; | |
198 | #endif | |
66e594f2 | 199 | |
8c59f5c1 MC |
200 | target_ulong scounteren; |
201 | target_ulong mcounteren; | |
dc5bd18f MC |
202 | |
203 | target_ulong sscratch; | |
204 | target_ulong mscratch; | |
205 | ||
206 | /* temporary htif regs */ | |
207 | uint64_t mfromhost; | |
208 | uint64_t mtohost; | |
209 | uint64_t timecmp; | |
210 | ||
211 | /* physical memory protection */ | |
212 | pmp_table_t pmp_state; | |
753e3fe2 | 213 | |
c6957248 AP |
214 | /* machine specific rdtime callback */ |
215 | uint64_t (*rdtime_fn)(void); | |
216 | ||
753e3fe2 JW |
217 | /* True if in debugger mode. */ |
218 | bool debugger; | |
dc5bd18f MC |
219 | #endif |
220 | ||
221 | float_status fp_status; | |
222 | ||
dc5bd18f MC |
223 | /* Fields from here on are preserved across CPU reset. */ |
224 | QEMUTimer *timer; /* Internal timer */ | |
225 | }; | |
226 | ||
227 | #define RISCV_CPU_CLASS(klass) \ | |
228 | OBJECT_CLASS_CHECK(RISCVCPUClass, (klass), TYPE_RISCV_CPU) | |
229 | #define RISCV_CPU(obj) \ | |
230 | OBJECT_CHECK(RISCVCPU, (obj), TYPE_RISCV_CPU) | |
231 | #define RISCV_CPU_GET_CLASS(obj) \ | |
232 | OBJECT_GET_CLASS(RISCVCPUClass, (obj), TYPE_RISCV_CPU) | |
233 | ||
234 | /** | |
235 | * RISCVCPUClass: | |
236 | * @parent_realize: The parent class' realize handler. | |
237 | * @parent_reset: The parent class' reset handler. | |
238 | * | |
239 | * A RISCV CPU model. | |
240 | */ | |
241 | typedef struct RISCVCPUClass { | |
242 | /*< private >*/ | |
243 | CPUClass parent_class; | |
244 | /*< public >*/ | |
245 | DeviceRealize parent_realize; | |
781c67ca | 246 | DeviceReset parent_reset; |
dc5bd18f MC |
247 | } RISCVCPUClass; |
248 | ||
249 | /** | |
250 | * RISCVCPU: | |
251 | * @env: #CPURISCVState | |
252 | * | |
253 | * A RISCV CPU. | |
254 | */ | |
255 | typedef struct RISCVCPU { | |
256 | /*< private >*/ | |
257 | CPUState parent_obj; | |
258 | /*< public >*/ | |
5b146dc7 | 259 | CPUNegativeOffsetState neg; |
dc5bd18f | 260 | CPURISCVState env; |
c4e95030 AF |
261 | |
262 | /* Configuration Settings */ | |
263 | struct { | |
b55d7d34 AF |
264 | bool ext_i; |
265 | bool ext_e; | |
266 | bool ext_g; | |
267 | bool ext_m; | |
268 | bool ext_a; | |
269 | bool ext_f; | |
270 | bool ext_d; | |
271 | bool ext_c; | |
272 | bool ext_s; | |
273 | bool ext_u; | |
c9eefe05 | 274 | bool ext_h; |
0a13a5b8 | 275 | bool ext_counters; |
50fba816 | 276 | bool ext_ifencei; |
591bddea | 277 | bool ext_icsr; |
b55d7d34 | 278 | |
c4e95030 AF |
279 | char *priv_spec; |
280 | char *user_spec; | |
32931383 LZ |
281 | uint16_t vlen; |
282 | uint16_t elen; | |
c4e95030 AF |
283 | bool mmu; |
284 | bool pmp; | |
285 | } cfg; | |
dc5bd18f MC |
286 | } RISCVCPU; |
287 | ||
dc5bd18f MC |
288 | static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) |
289 | { | |
290 | return (env->misa & ext) != 0; | |
291 | } | |
292 | ||
293 | static inline bool riscv_feature(CPURISCVState *env, int feature) | |
294 | { | |
295 | return env->features & (1ULL << feature); | |
296 | } | |
297 | ||
298 | #include "cpu_user.h" | |
299 | #include "cpu_bits.h" | |
300 | ||
301 | extern const char * const riscv_int_regnames[]; | |
302 | extern const char * const riscv_fpr_regnames[]; | |
303 | extern const char * const riscv_excp_names[]; | |
304 | extern const char * const riscv_intr_names[]; | |
305 | ||
dc5bd18f | 306 | void riscv_cpu_do_interrupt(CPUState *cpu); |
a010bdbe | 307 | int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); |
dc5bd18f MC |
308 | int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); |
309 | bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); | |
b345b480 | 310 | bool riscv_cpu_fp_enabled(CPURISCVState *env); |
ef6bb7b6 AF |
311 | bool riscv_cpu_virt_enabled(CPURISCVState *env); |
312 | void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); | |
c7b1bbc8 AF |
313 | bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); |
314 | void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable); | |
dc5bd18f MC |
315 | int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); |
316 | hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); | |
317 | void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, | |
318 | MMUAccessType access_type, int mmu_idx, | |
319 | uintptr_t retaddr); | |
8a4ca3c1 RH |
320 | bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
321 | MMUAccessType access_type, int mmu_idx, | |
322 | bool probe, uintptr_t retaddr); | |
37207e12 PD |
323 | void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, |
324 | vaddr addr, unsigned size, | |
325 | MMUAccessType access_type, | |
326 | int mmu_idx, MemTxAttrs attrs, | |
327 | MemTxResult response, uintptr_t retaddr); | |
dc5bd18f | 328 | char *riscv_isa_string(RISCVCPU *cpu); |
0442428a | 329 | void riscv_cpu_list(void); |
dc5bd18f | 330 | |
fb738839 | 331 | #define cpu_signal_handler riscv_cpu_signal_handler |
dc5bd18f MC |
332 | #define cpu_list riscv_cpu_list |
333 | #define cpu_mmu_index riscv_cpu_mmu_index | |
334 | ||
85ba724f | 335 | #ifndef CONFIG_USER_ONLY |
66e594f2 | 336 | void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); |
e3e7039c | 337 | int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); |
85ba724f MC |
338 | uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); |
339 | #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ | |
c6957248 | 340 | void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void)); |
85ba724f | 341 | #endif |
fb738839 | 342 | void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); |
dc5bd18f MC |
343 | |
344 | void riscv_translate_init(void); | |
fb738839 MC |
345 | int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc); |
346 | void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, | |
347 | uint32_t exception, uintptr_t pc); | |
dc5bd18f | 348 | |
fb738839 MC |
349 | target_ulong riscv_cpu_get_fflags(CPURISCVState *env); |
350 | void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); | |
dc5bd18f | 351 | |
83a71719 RH |
352 | #define TB_FLAGS_MMU_MASK 3 |
353 | #define TB_FLAGS_MSTATUS_FS MSTATUS_FS | |
dc5bd18f MC |
354 | |
355 | static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, | |
356 | target_ulong *cs_base, uint32_t *flags) | |
357 | { | |
358 | *pc = env->pc; | |
359 | *cs_base = 0; | |
360 | #ifdef CONFIG_USER_ONLY | |
83a71719 | 361 | *flags = TB_FLAGS_MSTATUS_FS; |
dc5bd18f | 362 | #else |
e28eaed8 AF |
363 | *flags = cpu_mmu_index(env, 0); |
364 | if (riscv_cpu_fp_enabled(env)) { | |
365 | *flags |= env->mstatus & MSTATUS_FS; | |
366 | } | |
dc5bd18f MC |
367 | #endif |
368 | } | |
369 | ||
c7b95171 MC |
370 | int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, |
371 | target_ulong new_value, target_ulong write_mask); | |
753e3fe2 JW |
372 | int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value, |
373 | target_ulong new_value, target_ulong write_mask); | |
c7b95171 | 374 | |
fb738839 MC |
375 | static inline void riscv_csr_write(CPURISCVState *env, int csrno, |
376 | target_ulong val) | |
c7b95171 MC |
377 | { |
378 | riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); | |
379 | } | |
380 | ||
fb738839 | 381 | static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) |
c7b95171 MC |
382 | { |
383 | target_ulong val = 0; | |
384 | riscv_csrrw(env, csrno, &val, 0, 0); | |
385 | return val; | |
386 | } | |
387 | ||
388 | typedef int (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno); | |
389 | typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, | |
390 | target_ulong *ret_value); | |
391 | typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, | |
392 | target_ulong new_value); | |
393 | typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, | |
394 | target_ulong *ret_value, target_ulong new_value, target_ulong write_mask); | |
395 | ||
396 | typedef struct { | |
a88365c1 | 397 | riscv_csr_predicate_fn predicate; |
c7b95171 MC |
398 | riscv_csr_read_fn read; |
399 | riscv_csr_write_fn write; | |
400 | riscv_csr_op_fn op; | |
401 | } riscv_csr_operations; | |
402 | ||
403 | void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); | |
404 | void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); | |
dc5bd18f | 405 | |
5371f5cd JW |
406 | void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); |
407 | ||
4f7c64b3 | 408 | typedef CPURISCVState CPUArchState; |
2161a612 | 409 | typedef RISCVCPU ArchCPU; |
4f7c64b3 | 410 | |
dc5bd18f MC |
411 | #include "exec/cpu-all.h" |
412 | ||
413 | #endif /* RISCV_CPU_H */ |