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dc5bd18f MC |
1 | /* |
2 | * QEMU RISC-V CPU | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #ifndef RISCV_CPU_H | |
21 | #define RISCV_CPU_H | |
22 | ||
2e5b09fd | 23 | #include "hw/core/cpu.h" |
2b7168fc | 24 | #include "hw/registerfields.h" |
dc5bd18f | 25 | #include "exec/cpu-defs.h" |
69242e7e | 26 | #include "qemu/cpu-float.h" |
db1015e9 | 27 | #include "qom/object.h" |
961738ff | 28 | #include "qemu/int128.h" |
e91a7227 | 29 | #include "cpu_bits.h" |
dc5bd18f | 30 | |
74433bf0 RH |
31 | #define TCG_GUEST_DEFAULT_MO 0 |
32 | ||
62cf0245 AP |
33 | /* |
34 | * RISC-V-specific extra insn start words: | |
35 | * 1: Original instruction opcode | |
36 | */ | |
37 | #define TARGET_INSN_START_EXTRA_WORDS 1 | |
38 | ||
dc5bd18f MC |
39 | #define TYPE_RISCV_CPU "riscv-cpu" |
40 | ||
41 | #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU | |
42 | #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) | |
0dacec87 | 43 | #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU |
dc5bd18f MC |
44 | |
45 | #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") | |
8903bf6e AF |
46 | #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") |
47 | #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") | |
332dab68 | 48 | #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") |
36b80ad9 | 49 | #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") |
6ddc7069 | 50 | #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") |
dc5bd18f | 51 | #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") |
d784733b | 52 | #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") |
dc5bd18f MC |
53 | #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") |
54 | #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") | |
55 | #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") | |
95bd8daa | 56 | #define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") |
10f1ca27 | 57 | #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") |
dc5bd18f | 58 | |
c0a635f3 AF |
59 | #if defined(TARGET_RISCV32) |
60 | # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 | |
61 | #elif defined(TARGET_RISCV64) | |
62 | # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 | |
63 | #endif | |
64 | ||
dc5bd18f MC |
65 | #define RV(x) ((target_ulong)1 << (x - 'A')) |
66 | ||
c66ffcd5 DHB |
67 | /* |
68 | * Consider updating register_cpu_props() when adding | |
69 | * new MISA bits here. | |
70 | */ | |
dc5bd18f | 71 | #define RVI RV('I') |
79f86934 | 72 | #define RVE RV('E') /* E and I are mutually exclusive */ |
dc5bd18f MC |
73 | #define RVM RV('M') |
74 | #define RVA RV('A') | |
75 | #define RVF RV('F') | |
76 | #define RVD RV('D') | |
ad9e5aa2 | 77 | #define RVV RV('V') |
dc5bd18f MC |
78 | #define RVC RV('C') |
79 | #define RVS RV('S') | |
80 | #define RVU RV('U') | |
af1fa003 | 81 | #define RVH RV('H') |
53dcea58 | 82 | #define RVJ RV('J') |
dc5bd18f MC |
83 | |
84 | /* S extension denotes that Supervisor mode exists, however it is possible | |
85 | to have a core that support S mode but does not have an MMU and there | |
86 | is currently no bit in misa to indicate whether an MMU exists or not | |
a88365c1 | 87 | so a cpu features bitfield is required, likewise for optional PMP support */ |
dc5bd18f | 88 | enum { |
a88365c1 | 89 | RISCV_FEATURE_MMU, |
f18637cd | 90 | RISCV_FEATURE_PMP, |
4a345b2a | 91 | RISCV_FEATURE_EPMP, |
32b0ada0 | 92 | RISCV_FEATURE_MISA, |
1acdb3b0 | 93 | RISCV_FEATURE_DEBUG |
dc5bd18f MC |
94 | }; |
95 | ||
a46d410c AP |
96 | /* Privileged specification version */ |
97 | enum { | |
98 | PRIV_VERSION_1_10_0 = 0, | |
99 | PRIV_VERSION_1_11_0, | |
3a4af26d | 100 | PRIV_VERSION_1_12_0, |
a46d410c | 101 | }; |
dc5bd18f | 102 | |
9ec6622d | 103 | #define VEXT_VERSION_1_00_0 0x00010000 |
32931383 | 104 | |
33a9a57d YJ |
105 | enum { |
106 | TRANSLATE_SUCCESS, | |
107 | TRANSLATE_FAIL, | |
108 | TRANSLATE_PMP_FAIL, | |
109 | TRANSLATE_G_STAGE_FAIL | |
110 | }; | |
111 | ||
dc5bd18f MC |
112 | #define MMU_USER_IDX 3 |
113 | ||
114 | #define MAX_RISCV_PMPS (16) | |
115 | ||
1ea4a06a | 116 | typedef struct CPUArchState CPURISCVState; |
dc5bd18f | 117 | |
bbf3d1b4 | 118 | #if !defined(CONFIG_USER_ONLY) |
dc5bd18f | 119 | #include "pmp.h" |
95799e36 | 120 | #include "debug.h" |
bbf3d1b4 | 121 | #endif |
dc5bd18f | 122 | |
8a4b5257 | 123 | #define RV_VLEN_MAX 1024 |
3780e337 | 124 | #define RV_MAX_MHPMEVENTS 32 |
621f35bb | 125 | #define RV_MAX_MHPMCOUNTERS 32 |
ad9e5aa2 | 126 | |
33f1beaf FC |
127 | FIELD(VTYPE, VLMUL, 0, 3) |
128 | FIELD(VTYPE, VSEW, 3, 3) | |
3479a814 FC |
129 | FIELD(VTYPE, VTA, 6, 1) |
130 | FIELD(VTYPE, VMA, 7, 1) | |
33f1beaf FC |
131 | FIELD(VTYPE, VEDIV, 8, 2) |
132 | FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) | |
2b7168fc | 133 | |
3780e337 AP |
134 | typedef struct PMUCTRState { |
135 | /* Current value of a counter */ | |
136 | target_ulong mhpmcounter_val; | |
137 | /* Current value of a counter in RV32*/ | |
138 | target_ulong mhpmcounterh_val; | |
139 | /* Snapshot values of counter */ | |
140 | target_ulong mhpmcounter_prev; | |
141 | /* Snapshort value of a counter in RV32 */ | |
142 | target_ulong mhpmcounterh_prev; | |
143 | bool started; | |
14664483 AP |
144 | /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */ |
145 | target_ulong irq_overflow_left; | |
3780e337 AP |
146 | } PMUCTRState; |
147 | ||
1ea4a06a | 148 | struct CPUArchState { |
dc5bd18f | 149 | target_ulong gpr[32]; |
2b547084 | 150 | target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ |
dc5bd18f | 151 | uint64_t fpr[32]; /* assume both F and D extensions */ |
ad9e5aa2 LZ |
152 | |
153 | /* vector coprocessor state. */ | |
154 | uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); | |
155 | target_ulong vxrm; | |
156 | target_ulong vxsat; | |
157 | target_ulong vl; | |
158 | target_ulong vstart; | |
159 | target_ulong vtype; | |
d96a271a | 160 | bool vill; |
ad9e5aa2 | 161 | |
dc5bd18f MC |
162 | target_ulong pc; |
163 | target_ulong load_res; | |
164 | target_ulong load_val; | |
165 | ||
166 | target_ulong frm; | |
167 | ||
168 | target_ulong badaddr; | |
62cf0245 | 169 | target_ulong bins; |
48eaeb56 | 170 | |
36a18664 | 171 | target_ulong guest_phys_fault_addr; |
dc5bd18f | 172 | |
dc5bd18f | 173 | target_ulong priv_ver; |
d2c1a177 | 174 | target_ulong bext_ver; |
32931383 | 175 | target_ulong vext_ver; |
e91a7227 RH |
176 | |
177 | /* RISCVMXL, but uint32_t for vmstate migration */ | |
178 | uint32_t misa_mxl; /* current mxl */ | |
179 | uint32_t misa_mxl_max; /* max mxl for this cpu */ | |
180 | uint32_t misa_ext; /* current extensions */ | |
181 | uint32_t misa_ext_mask; /* max ext for this cpu */ | |
440544e1 | 182 | uint32_t xl; /* current xlen */ |
dc5bd18f | 183 | |
b3a5d1fb FP |
184 | /* 128-bit helpers upper part return value */ |
185 | target_ulong retxh; | |
186 | ||
dc5bd18f MC |
187 | uint32_t features; |
188 | ||
5836c3ec KC |
189 | #ifdef CONFIG_USER_ONLY |
190 | uint32_t elf_flags; | |
191 | #endif | |
192 | ||
dc5bd18f MC |
193 | #ifndef CONFIG_USER_ONLY |
194 | target_ulong priv; | |
ef6bb7b6 AF |
195 | /* This contains QEMU specific information about the virt state. */ |
196 | target_ulong virt; | |
cd032fe7 | 197 | target_ulong geilen; |
277b210d | 198 | uint64_t resetvec; |
dc5bd18f MC |
199 | |
200 | target_ulong mhartid; | |
284d697c YJ |
201 | /* |
202 | * For RV32 this is 32-bit mstatus and 32-bit mstatush. | |
203 | * For RV64 this is a 64-bit mstatus. | |
204 | */ | |
205 | uint64_t mstatus; | |
85ba724f | 206 | |
d028ac75 | 207 | uint64_t mip; |
33fe584f AF |
208 | /* |
209 | * MIP contains the software writable version of SEIP ORed with the | |
210 | * external interrupt value. The MIP register is always up-to-date. | |
211 | * To keep track of the current source, we also save booleans of the values | |
212 | * here. | |
213 | */ | |
214 | bool external_seip; | |
215 | bool software_seip; | |
66e594f2 | 216 | |
d028ac75 | 217 | uint64_t miclaim; |
85ba724f | 218 | |
d028ac75 AP |
219 | uint64_t mie; |
220 | uint64_t mideleg; | |
dc5bd18f | 221 | |
dc5bd18f | 222 | target_ulong satp; /* since: priv-1.10.0 */ |
ac12b601 | 223 | target_ulong stval; |
dc5bd18f MC |
224 | target_ulong medeleg; |
225 | ||
226 | target_ulong stvec; | |
227 | target_ulong sepc; | |
228 | target_ulong scause; | |
229 | ||
230 | target_ulong mtvec; | |
231 | target_ulong mepc; | |
232 | target_ulong mcause; | |
233 | target_ulong mtval; /* since: priv-1.10.0 */ | |
234 | ||
43dc93af AP |
235 | /* Machine and Supervisor interrupt priorities */ |
236 | uint8_t miprio[64]; | |
237 | uint8_t siprio[64]; | |
238 | ||
d1ceff40 AP |
239 | /* AIA CSRs */ |
240 | target_ulong miselect; | |
241 | target_ulong siselect; | |
242 | ||
bd023ce3 AF |
243 | /* Hypervisor CSRs */ |
244 | target_ulong hstatus; | |
245 | target_ulong hedeleg; | |
d028ac75 | 246 | uint64_t hideleg; |
bd023ce3 AF |
247 | target_ulong hcounteren; |
248 | target_ulong htval; | |
249 | target_ulong htinst; | |
250 | target_ulong hgatp; | |
cd032fe7 AP |
251 | target_ulong hgeie; |
252 | target_ulong hgeip; | |
c6957248 | 253 | uint64_t htimedelta; |
bd023ce3 | 254 | |
43dc93af | 255 | /* Hypervisor controlled virtual interrupt priorities */ |
2b602398 | 256 | target_ulong hvictl; |
43dc93af AP |
257 | uint8_t hviprio[64]; |
258 | ||
2c64ab66 FP |
259 | /* Upper 64-bits of 128-bit CSRs */ |
260 | uint64_t mscratchh; | |
261 | uint64_t sscratchh; | |
262 | ||
bd023ce3 | 263 | /* Virtual CSRs */ |
284d697c YJ |
264 | /* |
265 | * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. | |
266 | * For RV64 this is a 64-bit vsstatus. | |
267 | */ | |
268 | uint64_t vsstatus; | |
bd023ce3 AF |
269 | target_ulong vstvec; |
270 | target_ulong vsscratch; | |
271 | target_ulong vsepc; | |
272 | target_ulong vscause; | |
273 | target_ulong vstval; | |
274 | target_ulong vsatp; | |
275 | ||
d1ceff40 AP |
276 | /* AIA VS-mode CSRs */ |
277 | target_ulong vsiselect; | |
278 | ||
bd023ce3 AF |
279 | target_ulong mtval2; |
280 | target_ulong mtinst; | |
281 | ||
66e594f2 AF |
282 | /* HS Backup CSRs */ |
283 | target_ulong stvec_hs; | |
284 | target_ulong sscratch_hs; | |
285 | target_ulong sepc_hs; | |
286 | target_ulong scause_hs; | |
287 | target_ulong stval_hs; | |
288 | target_ulong satp_hs; | |
284d697c | 289 | uint64_t mstatus_hs; |
66e594f2 | 290 | |
ec352d0c GK |
291 | /* Signals whether the current exception occurred with two-stage address |
292 | translation active. */ | |
293 | bool two_stage_lookup; | |
8e2aa21b AP |
294 | /* |
295 | * Signals whether the current exception occurred while doing two-stage | |
296 | * address translation for the VS-stage page table walk. | |
297 | */ | |
298 | bool two_stage_indirect_lookup; | |
ec352d0c | 299 | |
8c59f5c1 MC |
300 | target_ulong scounteren; |
301 | target_ulong mcounteren; | |
dc5bd18f | 302 | |
b1675eeb AP |
303 | target_ulong mcountinhibit; |
304 | ||
3780e337 AP |
305 | /* PMU counter state */ |
306 | PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; | |
621f35bb | 307 | |
3780e337 | 308 | /* PMU event selector configured values. First three are unused*/ |
621f35bb AP |
309 | target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; |
310 | ||
14664483 AP |
311 | /* PMU event selector configured values for RV32*/ |
312 | target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; | |
313 | ||
dc5bd18f MC |
314 | target_ulong sscratch; |
315 | target_ulong mscratch; | |
316 | ||
43888c2f AP |
317 | /* Sstc CSRs */ |
318 | uint64_t stimecmp; | |
319 | ||
3ec0fe18 AP |
320 | uint64_t vstimecmp; |
321 | ||
dc5bd18f MC |
322 | /* physical memory protection */ |
323 | pmp_table_t pmp_state; | |
2582a95c | 324 | target_ulong mseccfg; |
753e3fe2 | 325 | |
95799e36 BM |
326 | /* trigger module */ |
327 | target_ulong trigger_cur; | |
9495c488 FC |
328 | target_ulong tdata1[RV_MAX_TRIGGERS]; |
329 | target_ulong tdata2[RV_MAX_TRIGGERS]; | |
330 | target_ulong tdata3[RV_MAX_TRIGGERS]; | |
331 | struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; | |
332 | struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; | |
5a4ae64c LZ |
333 | QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; |
334 | int64_t last_icount; | |
577f0286 | 335 | bool itrigger_enabled; |
95799e36 | 336 | |
c6957248 | 337 | /* machine specific rdtime callback */ |
e2f01f3c FC |
338 | uint64_t (*rdtime_fn)(void *); |
339 | void *rdtime_fn_arg; | |
c6957248 | 340 | |
69077dd6 AP |
341 | /* machine specific AIA ireg read-modify-write callback */ |
342 | #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ | |
343 | ((((__xlen) & 0xff) << 24) | \ | |
344 | (((__vgein) & 0x3f) << 20) | \ | |
345 | (((__virt) & 0x1) << 18) | \ | |
346 | (((__priv) & 0x3) << 16) | \ | |
347 | (__isel & 0xffff)) | |
348 | #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) | |
349 | #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) | |
350 | #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) | |
351 | #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) | |
352 | #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) | |
353 | int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, | |
354 | target_ulong *val, target_ulong new_val, target_ulong write_mask); | |
355 | void *aia_ireg_rmw_fn_arg[4]; | |
356 | ||
753e3fe2 JW |
357 | /* True if in debugger mode. */ |
358 | bool debugger; | |
4bbe8033 AB |
359 | |
360 | /* | |
361 | * CSRs for PointerMasking extension | |
362 | */ | |
363 | target_ulong mmte; | |
364 | target_ulong mpmmask; | |
365 | target_ulong mpmbase; | |
366 | target_ulong spmmask; | |
367 | target_ulong spmbase; | |
368 | target_ulong upmmask; | |
369 | target_ulong upmbase; | |
29a9ec9b AP |
370 | |
371 | /* CSRs for execution enviornment configuration */ | |
372 | uint64_t menvcfg; | |
3bee0e40 MC |
373 | uint64_t mstateen[SMSTATEEN_MAX_COUNT]; |
374 | uint64_t hstateen[SMSTATEEN_MAX_COUNT]; | |
375 | uint64_t sstateen[SMSTATEEN_MAX_COUNT]; | |
29a9ec9b AP |
376 | target_ulong senvcfg; |
377 | uint64_t henvcfg; | |
dc5bd18f | 378 | #endif |
40bfa5f6 LZ |
379 | target_ulong cur_pmmask; |
380 | target_ulong cur_pmbase; | |
dc5bd18f MC |
381 | |
382 | float_status fp_status; | |
383 | ||
dc5bd18f | 384 | /* Fields from here on are preserved across CPU reset. */ |
43888c2f | 385 | QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ |
3ec0fe18 AP |
386 | QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */ |
387 | bool vstime_irq; | |
ad40be27 YJ |
388 | |
389 | hwaddr kernel_addr; | |
390 | hwaddr fdt_addr; | |
27abe66f YJ |
391 | |
392 | /* kvm timer */ | |
393 | bool kvm_timer_dirty; | |
394 | uint64_t kvm_timer_time; | |
395 | uint64_t kvm_timer_compare; | |
396 | uint64_t kvm_timer_state; | |
397 | uint64_t kvm_timer_frequency; | |
dc5bd18f MC |
398 | }; |
399 | ||
9295b1aa | 400 | OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) |
dc5bd18f MC |
401 | |
402 | /** | |
403 | * RISCVCPUClass: | |
404 | * @parent_realize: The parent class' realize handler. | |
4fa485a7 | 405 | * @parent_phases: The parent class' reset phase handlers. |
dc5bd18f MC |
406 | * |
407 | * A RISCV CPU model. | |
408 | */ | |
db1015e9 | 409 | struct RISCVCPUClass { |
dc5bd18f MC |
410 | /*< private >*/ |
411 | CPUClass parent_class; | |
412 | /*< public >*/ | |
413 | DeviceRealize parent_realize; | |
4fa485a7 | 414 | ResettablePhases parent_phases; |
db1015e9 | 415 | }; |
dc5bd18f | 416 | |
466292bd PT |
417 | struct RISCVCPUConfig { |
418 | bool ext_i; | |
419 | bool ext_e; | |
420 | bool ext_g; | |
421 | bool ext_m; | |
422 | bool ext_a; | |
423 | bool ext_f; | |
424 | bool ext_d; | |
425 | bool ext_c; | |
426 | bool ext_s; | |
427 | bool ext_u; | |
428 | bool ext_h; | |
429 | bool ext_j; | |
430 | bool ext_v; | |
431 | bool ext_zba; | |
432 | bool ext_zbb; | |
433 | bool ext_zbc; | |
eef82872 WL |
434 | bool ext_zbkb; |
435 | bool ext_zbkc; | |
436 | bool ext_zbkx; | |
466292bd | 437 | bool ext_zbs; |
eef82872 WL |
438 | bool ext_zk; |
439 | bool ext_zkn; | |
440 | bool ext_zknd; | |
441 | bool ext_zkne; | |
442 | bool ext_zknh; | |
443 | bool ext_zkr; | |
444 | bool ext_zks; | |
445 | bool ext_zksed; | |
446 | bool ext_zksh; | |
447 | bool ext_zkt; | |
466292bd PT |
448 | bool ext_ifencei; |
449 | bool ext_icsr; | |
4696f0ab | 450 | bool ext_zihintpause; |
3bee0e40 | 451 | bool ext_smstateen; |
43888c2f | 452 | bool ext_sstc; |
c5d77ddd | 453 | bool ext_svinval; |
05e6ca5e GR |
454 | bool ext_svnapot; |
455 | bool ext_svpbmt; | |
89ffdcec | 456 | bool ext_zdinx; |
260b594d | 457 | bool ext_zawrs; |
466292bd PT |
458 | bool ext_zfh; |
459 | bool ext_zfhmin; | |
89ffdcec WL |
460 | bool ext_zfinx; |
461 | bool ext_zhinx; | |
462 | bool ext_zhinxmin; | |
466292bd PT |
463 | bool ext_zve32f; |
464 | bool ext_zve64f; | |
de799beb | 465 | bool ext_zmmul; |
dc9acc9c AP |
466 | bool ext_smaia; |
467 | bool ext_ssaia; | |
14664483 | 468 | bool ext_sscofpmf; |
f1eed927 | 469 | bool rvv_ta_all_1s; |
355d5584 | 470 | bool rvv_ma_all_1s; |
466292bd | 471 | |
9951ba94 FC |
472 | uint32_t mvendorid; |
473 | uint64_t marchid; | |
075eeda9 | 474 | uint64_t mimpid; |
9951ba94 | 475 | |
0d429bd2 | 476 | /* Vendor-specific custom extensions */ |
c9410a68 | 477 | bool ext_xtheadba; |
426c0491 | 478 | bool ext_xtheadbb; |
fa134585 | 479 | bool ext_xtheadbs; |
49a7f3aa | 480 | bool ext_xtheadcmo; |
32909338 | 481 | bool ext_xtheadcondmov; |
d4d90115 | 482 | bool ext_xtheadfmemidx; |
b8a5832b | 483 | bool ext_xtheadmac; |
45f9df86 | 484 | bool ext_xtheadmemidx; |
af99aa72 | 485 | bool ext_xtheadmempair; |
134c3ffa | 486 | bool ext_xtheadsync; |
0d429bd2 PT |
487 | bool ext_XVentanaCondOps; |
488 | ||
18d6d89e | 489 | uint8_t pmu_num; |
466292bd PT |
490 | char *priv_spec; |
491 | char *user_spec; | |
492 | char *bext_spec; | |
493 | char *vext_spec; | |
494 | uint16_t vlen; | |
495 | uint16_t elen; | |
496 | bool mmu; | |
497 | bool pmp; | |
498 | bool epmp; | |
1acdb3b0 | 499 | bool debug; |
a4a9a443 TO |
500 | |
501 | bool short_isa_string; | |
466292bd PT |
502 | }; |
503 | ||
504 | typedef struct RISCVCPUConfig RISCVCPUConfig; | |
505 | ||
dc5bd18f MC |
506 | /** |
507 | * RISCVCPU: | |
508 | * @env: #CPURISCVState | |
509 | * | |
510 | * A RISCV CPU. | |
511 | */ | |
b36e239e | 512 | struct ArchCPU { |
dc5bd18f MC |
513 | /*< private >*/ |
514 | CPUState parent_obj; | |
515 | /*< public >*/ | |
5b146dc7 | 516 | CPUNegativeOffsetState neg; |
dc5bd18f | 517 | CPURISCVState env; |
c4e95030 | 518 | |
b93777e1 | 519 | char *dyn_csr_xml; |
719d3561 | 520 | char *dyn_vreg_xml; |
b93777e1 | 521 | |
c4e95030 | 522 | /* Configuration Settings */ |
466292bd | 523 | RISCVCPUConfig cfg; |
14664483 AP |
524 | |
525 | QEMUTimer *pmu_timer; | |
526 | /* A bitmask of Available programmable counters */ | |
527 | uint32_t pmu_avail_ctrs; | |
528 | /* Mapping of events to counters */ | |
529 | GHashTable *pmu_event_ctr_map; | |
db1015e9 | 530 | }; |
dc5bd18f | 531 | |
dc5bd18f MC |
532 | static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) |
533 | { | |
e91a7227 | 534 | return (env->misa_ext & ext) != 0; |
dc5bd18f MC |
535 | } |
536 | ||
537 | static inline bool riscv_feature(CPURISCVState *env, int feature) | |
538 | { | |
539 | return env->features & (1ULL << feature); | |
540 | } | |
541 | ||
f87adf23 AP |
542 | static inline void riscv_set_feature(CPURISCVState *env, int feature) |
543 | { | |
544 | env->features |= (1ULL << feature); | |
545 | } | |
546 | ||
dc5bd18f | 547 | #include "cpu_user.h" |
dc5bd18f MC |
548 | |
549 | extern const char * const riscv_int_regnames[]; | |
2b547084 | 550 | extern const char * const riscv_int_regnamesh[]; |
dc5bd18f | 551 | extern const char * const riscv_fpr_regnames[]; |
dc5bd18f | 552 | |
c51a3f5d | 553 | const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); |
dc5bd18f | 554 | void riscv_cpu_do_interrupt(CPUState *cpu); |
43a96588 | 555 | int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, |
1af0006a | 556 | int cpuid, DumpState *s); |
43a96588 | 557 | int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, |
1af0006a | 558 | int cpuid, DumpState *s); |
a010bdbe | 559 | int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); |
dc5bd18f | 560 | int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); |
43dc93af AP |
561 | int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); |
562 | uint8_t riscv_cpu_default_priority(int irq); | |
8f42415f | 563 | uint64_t riscv_cpu_all_pending(CPURISCVState *env); |
43dc93af AP |
564 | int riscv_cpu_mirq_pending(CPURISCVState *env); |
565 | int riscv_cpu_sirq_pending(CPURISCVState *env); | |
566 | int riscv_cpu_vsirq_pending(CPURISCVState *env); | |
b345b480 | 567 | bool riscv_cpu_fp_enabled(CPURISCVState *env); |
cd032fe7 AP |
568 | target_ulong riscv_cpu_get_geilen(CPURISCVState *env); |
569 | void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); | |
61b4b69d | 570 | bool riscv_cpu_vector_enabled(CPURISCVState *env); |
ef6bb7b6 AF |
571 | bool riscv_cpu_virt_enabled(CPURISCVState *env); |
572 | void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); | |
1c1c060a | 573 | bool riscv_cpu_two_stage_lookup(int mmu_idx); |
dc5bd18f MC |
574 | int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); |
575 | hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); | |
8905770b MAL |
576 | G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, |
577 | MMUAccessType access_type, int mmu_idx, | |
578 | uintptr_t retaddr); | |
8a4ca3c1 RH |
579 | bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
580 | MMUAccessType access_type, int mmu_idx, | |
581 | bool probe, uintptr_t retaddr); | |
37207e12 PD |
582 | void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, |
583 | vaddr addr, unsigned size, | |
584 | MMUAccessType access_type, | |
585 | int mmu_idx, MemTxAttrs attrs, | |
586 | MemTxResult response, uintptr_t retaddr); | |
dc5bd18f | 587 | char *riscv_isa_string(RISCVCPU *cpu); |
0442428a | 588 | void riscv_cpu_list(void); |
dc5bd18f | 589 | |
dc5bd18f MC |
590 | #define cpu_list riscv_cpu_list |
591 | #define cpu_mmu_index riscv_cpu_mmu_index | |
592 | ||
85ba724f | 593 | #ifndef CONFIG_USER_ONLY |
17b3c353 | 594 | bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); |
66e594f2 | 595 | void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); |
d028ac75 AP |
596 | int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); |
597 | uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value); | |
85ba724f | 598 | #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ |
e2f01f3c FC |
599 | void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), |
600 | void *arg); | |
69077dd6 AP |
601 | void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, |
602 | int (*rmw_fn)(void *arg, | |
603 | target_ulong reg, | |
604 | target_ulong *val, | |
605 | target_ulong new_val, | |
606 | target_ulong write_mask), | |
607 | void *rmw_fn_arg); | |
85ba724f | 608 | #endif |
fb738839 | 609 | void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); |
dc5bd18f MC |
610 | |
611 | void riscv_translate_init(void); | |
8905770b MAL |
612 | G_NORETURN void riscv_raise_exception(CPURISCVState *env, |
613 | uint32_t exception, uintptr_t pc); | |
dc5bd18f | 614 | |
fb738839 MC |
615 | target_ulong riscv_cpu_get_fflags(CPURISCVState *env); |
616 | void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); | |
dc5bd18f | 617 | |
c445593d AF |
618 | #define TB_FLAGS_PRIV_MMU_MASK 3 |
619 | #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) | |
83a71719 | 620 | #define TB_FLAGS_MSTATUS_FS MSTATUS_FS |
61b4b69d | 621 | #define TB_FLAGS_MSTATUS_VS MSTATUS_VS |
dc5bd18f | 622 | |
2b7168fc LZ |
623 | #include "exec/cpu-all.h" |
624 | ||
61d56494 | 625 | FIELD(TB_FLAGS, MEM_IDX, 0, 3) |
33f1beaf | 626 | FIELD(TB_FLAGS, LMUL, 3, 3) |
61d56494 | 627 | FIELD(TB_FLAGS, SEW, 6, 3) |
33f1beaf FC |
628 | /* Skip MSTATUS_VS (0x600) bits */ |
629 | FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) | |
630 | FIELD(TB_FLAGS, VILL, 12, 1) | |
631 | /* Skip MSTATUS_FS (0x6000) bits */ | |
743077b3 | 632 | /* Is a Hypervisor instruction load/store allowed? */ |
33f1beaf FC |
633 | FIELD(TB_FLAGS, HLSX, 15, 1) |
634 | FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) | |
635 | FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) | |
92371bd9 | 636 | /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ |
33f1beaf | 637 | FIELD(TB_FLAGS, XL, 20, 2) |
0774a7a1 | 638 | /* If PointerMasking should be applied */ |
4208dc7e LZ |
639 | FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1) |
640 | FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1) | |
f1eed927 | 641 | FIELD(TB_FLAGS, VTA, 24, 1) |
355d5584 | 642 | FIELD(TB_FLAGS, VMA, 25, 1) |
2c9d7471 LZ |
643 | /* Native debug itrigger */ |
644 | FIELD(TB_FLAGS, ITRIGGER, 26, 1) | |
2b7168fc | 645 | |
db23e5d9 RH |
646 | #ifdef TARGET_RISCV32 |
647 | #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) | |
648 | #else | |
649 | static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) | |
650 | { | |
651 | return env->misa_mxl; | |
652 | } | |
653 | #endif | |
2b602398 | 654 | #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) |
51ae0cab | 655 | |
440544e1 LZ |
656 | #if defined(TARGET_RISCV32) |
657 | #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) | |
658 | #else | |
659 | static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) | |
660 | { | |
661 | RISCVMXL xl = env->misa_mxl; | |
662 | #if !defined(CONFIG_USER_ONLY) | |
663 | /* | |
664 | * When emulating a 32-bit-only cpu, use RV32. | |
665 | * When emulating a 64-bit cpu, and MXL has been reduced to RV32, | |
666 | * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened | |
667 | * back to RV64 for lower privs. | |
668 | */ | |
669 | if (xl != MXL_RV32) { | |
670 | switch (env->priv) { | |
671 | case PRV_M: | |
672 | break; | |
673 | case PRV_U: | |
674 | xl = get_field(env->mstatus, MSTATUS64_UXL); | |
675 | break; | |
676 | default: /* PRV_S | PRV_H */ | |
677 | xl = get_field(env->mstatus, MSTATUS64_SXL); | |
678 | break; | |
679 | } | |
680 | } | |
681 | #endif | |
682 | return xl; | |
683 | } | |
684 | #endif | |
685 | ||
31961cfe LZ |
686 | static inline int riscv_cpu_xlen(CPURISCVState *env) |
687 | { | |
688 | return 16 << env->xl; | |
689 | } | |
690 | ||
05e6ca5e GR |
691 | #ifdef TARGET_RISCV32 |
692 | #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) | |
693 | #else | |
694 | static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) | |
695 | { | |
696 | #ifdef CONFIG_USER_ONLY | |
697 | return env->misa_mxl; | |
698 | #else | |
699 | return get_field(env->mstatus, MSTATUS64_SXL); | |
700 | #endif | |
701 | } | |
702 | #endif | |
703 | ||
2b7168fc | 704 | /* |
a689a82b FC |
705 | * Encode LMUL to lmul as follows: |
706 | * LMUL vlmul lmul | |
707 | * 1 000 0 | |
708 | * 2 001 1 | |
709 | * 4 010 2 | |
710 | * 8 011 3 | |
711 | * - 100 - | |
712 | * 1/8 101 -3 | |
713 | * 1/4 110 -2 | |
714 | * 1/2 111 -1 | |
715 | * | |
716 | * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) | |
717 | * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 | |
718 | * => VLMAX = vlen >> (1 + 3 - (-3)) | |
719 | * = 256 >> 7 | |
720 | * = 2 | |
2b7168fc LZ |
721 | */ |
722 | static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) | |
723 | { | |
a689a82b FC |
724 | uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); |
725 | int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); | |
2b7168fc LZ |
726 | return cpu->cfg.vlen >> (sew + 3 - lmul); |
727 | } | |
728 | ||
53677acf RH |
729 | void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, |
730 | target_ulong *cs_base, uint32_t *pflags); | |
dc5bd18f | 731 | |
40bfa5f6 LZ |
732 | void riscv_cpu_update_mask(CPURISCVState *env); |
733 | ||
533c91e8 AF |
734 | RISCVException riscv_csrrw(CPURISCVState *env, int csrno, |
735 | target_ulong *ret_value, | |
736 | target_ulong new_value, target_ulong write_mask); | |
737 | RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, | |
738 | target_ulong *ret_value, | |
739 | target_ulong new_value, | |
740 | target_ulong write_mask); | |
c7b95171 | 741 | |
fb738839 MC |
742 | static inline void riscv_csr_write(CPURISCVState *env, int csrno, |
743 | target_ulong val) | |
c7b95171 MC |
744 | { |
745 | riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); | |
746 | } | |
747 | ||
fb738839 | 748 | static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) |
c7b95171 MC |
749 | { |
750 | target_ulong val = 0; | |
751 | riscv_csrrw(env, csrno, &val, 0, 0); | |
752 | return val; | |
753 | } | |
754 | ||
0e62f92e AF |
755 | typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, |
756 | int csrno); | |
605def6e AF |
757 | typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, |
758 | target_ulong *ret_value); | |
759 | typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, | |
760 | target_ulong new_value); | |
761 | typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, | |
762 | target_ulong *ret_value, | |
763 | target_ulong new_value, | |
764 | target_ulong write_mask); | |
c7b95171 | 765 | |
961738ff FP |
766 | RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, |
767 | Int128 *ret_value, | |
768 | Int128 new_value, Int128 write_mask); | |
769 | ||
457c360f FP |
770 | typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, |
771 | Int128 *ret_value); | |
772 | typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, | |
773 | Int128 new_value); | |
774 | ||
c7b95171 | 775 | typedef struct { |
8ceac5dc | 776 | const char *name; |
a88365c1 | 777 | riscv_csr_predicate_fn predicate; |
c7b95171 MC |
778 | riscv_csr_read_fn read; |
779 | riscv_csr_write_fn write; | |
780 | riscv_csr_op_fn op; | |
457c360f FP |
781 | riscv_csr_read128_fn read128; |
782 | riscv_csr_write128_fn write128; | |
a4b2fa43 AP |
783 | /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ |
784 | uint32_t min_priv_ver; | |
c7b95171 MC |
785 | } riscv_csr_operations; |
786 | ||
56118ee8 BM |
787 | /* CSR function table constants */ |
788 | enum { | |
789 | CSR_TABLE_SIZE = 0x1000 | |
790 | }; | |
791 | ||
14664483 AP |
792 | /** |
793 | * The event id are encoded based on the encoding specified in the | |
794 | * SBI specification v0.3 | |
795 | */ | |
796 | ||
797 | enum riscv_pmu_event_idx { | |
798 | RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01, | |
799 | RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02, | |
800 | RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019, | |
801 | RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B, | |
802 | RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021, | |
803 | }; | |
804 | ||
56118ee8 | 805 | /* CSR function table */ |
6f03770d | 806 | extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; |
56118ee8 | 807 | |
c7b95171 MC |
808 | void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); |
809 | void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); | |
dc5bd18f | 810 | |
5371f5cd JW |
811 | void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); |
812 | ||
dc5bd18f | 813 | #endif /* RISCV_CPU_H */ |