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dc5bd18f MC |
1 | /* |
2 | * QEMU RISC-V CPU | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #ifndef RISCV_CPU_H | |
21 | #define RISCV_CPU_H | |
22 | ||
2e5b09fd | 23 | #include "hw/core/cpu.h" |
2b7168fc | 24 | #include "hw/registerfields.h" |
dc5bd18f | 25 | #include "exec/cpu-defs.h" |
135b03cb | 26 | #include "fpu/softfloat-types.h" |
db1015e9 | 27 | #include "qom/object.h" |
e91a7227 | 28 | #include "cpu_bits.h" |
dc5bd18f | 29 | |
74433bf0 RH |
30 | #define TCG_GUEST_DEFAULT_MO 0 |
31 | ||
dc5bd18f MC |
32 | #define TYPE_RISCV_CPU "riscv-cpu" |
33 | ||
34 | #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU | |
35 | #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) | |
0dacec87 | 36 | #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU |
dc5bd18f MC |
37 | |
38 | #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") | |
8903bf6e AF |
39 | #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") |
40 | #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") | |
332dab68 | 41 | #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") |
36b80ad9 | 42 | #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") |
6ddc7069 | 43 | #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") |
dc5bd18f | 44 | #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") |
d784733b | 45 | #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") |
dc5bd18f MC |
46 | #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") |
47 | #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") | |
48 | #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") | |
49 | ||
c0a635f3 AF |
50 | #if defined(TARGET_RISCV32) |
51 | # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 | |
52 | #elif defined(TARGET_RISCV64) | |
53 | # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 | |
54 | #endif | |
55 | ||
dc5bd18f MC |
56 | #define RV(x) ((target_ulong)1 << (x - 'A')) |
57 | ||
58 | #define RVI RV('I') | |
79f86934 | 59 | #define RVE RV('E') /* E and I are mutually exclusive */ |
dc5bd18f MC |
60 | #define RVM RV('M') |
61 | #define RVA RV('A') | |
62 | #define RVF RV('F') | |
63 | #define RVD RV('D') | |
ad9e5aa2 | 64 | #define RVV RV('V') |
dc5bd18f MC |
65 | #define RVC RV('C') |
66 | #define RVS RV('S') | |
67 | #define RVU RV('U') | |
af1fa003 | 68 | #define RVH RV('H') |
53dcea58 | 69 | #define RVJ RV('J') |
dc5bd18f MC |
70 | |
71 | /* S extension denotes that Supervisor mode exists, however it is possible | |
72 | to have a core that support S mode but does not have an MMU and there | |
73 | is currently no bit in misa to indicate whether an MMU exists or not | |
a88365c1 | 74 | so a cpu features bitfield is required, likewise for optional PMP support */ |
dc5bd18f | 75 | enum { |
a88365c1 | 76 | RISCV_FEATURE_MMU, |
f18637cd | 77 | RISCV_FEATURE_PMP, |
4a345b2a | 78 | RISCV_FEATURE_EPMP, |
f18637cd | 79 | RISCV_FEATURE_MISA |
dc5bd18f MC |
80 | }; |
81 | ||
dc5bd18f | 82 | #define PRIV_VERSION_1_10_0 0x00011000 |
6729dbbd | 83 | #define PRIV_VERSION_1_11_0 0x00011100 |
dc5bd18f | 84 | |
9ec6622d | 85 | #define VEXT_VERSION_1_00_0 0x00010000 |
32931383 | 86 | |
33a9a57d YJ |
87 | enum { |
88 | TRANSLATE_SUCCESS, | |
89 | TRANSLATE_FAIL, | |
90 | TRANSLATE_PMP_FAIL, | |
91 | TRANSLATE_G_STAGE_FAIL | |
92 | }; | |
93 | ||
dc5bd18f MC |
94 | #define MMU_USER_IDX 3 |
95 | ||
96 | #define MAX_RISCV_PMPS (16) | |
97 | ||
98 | typedef struct CPURISCVState CPURISCVState; | |
99 | ||
bbf3d1b4 | 100 | #if !defined(CONFIG_USER_ONLY) |
dc5bd18f | 101 | #include "pmp.h" |
bbf3d1b4 | 102 | #endif |
dc5bd18f | 103 | |
8a4b5257 | 104 | #define RV_VLEN_MAX 1024 |
ad9e5aa2 | 105 | |
33f1beaf FC |
106 | FIELD(VTYPE, VLMUL, 0, 3) |
107 | FIELD(VTYPE, VSEW, 3, 3) | |
3479a814 FC |
108 | FIELD(VTYPE, VTA, 6, 1) |
109 | FIELD(VTYPE, VMA, 7, 1) | |
33f1beaf FC |
110 | FIELD(VTYPE, VEDIV, 8, 2) |
111 | FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) | |
fbcbafa2 | 112 | FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) |
2b7168fc | 113 | |
dc5bd18f MC |
114 | struct CPURISCVState { |
115 | target_ulong gpr[32]; | |
2b547084 | 116 | target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ |
dc5bd18f | 117 | uint64_t fpr[32]; /* assume both F and D extensions */ |
ad9e5aa2 LZ |
118 | |
119 | /* vector coprocessor state. */ | |
120 | uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); | |
121 | target_ulong vxrm; | |
122 | target_ulong vxsat; | |
123 | target_ulong vl; | |
124 | target_ulong vstart; | |
125 | target_ulong vtype; | |
126 | ||
dc5bd18f MC |
127 | target_ulong pc; |
128 | target_ulong load_res; | |
129 | target_ulong load_val; | |
130 | ||
131 | target_ulong frm; | |
132 | ||
133 | target_ulong badaddr; | |
36a18664 | 134 | target_ulong guest_phys_fault_addr; |
dc5bd18f | 135 | |
dc5bd18f | 136 | target_ulong priv_ver; |
d2c1a177 | 137 | target_ulong bext_ver; |
32931383 | 138 | target_ulong vext_ver; |
e91a7227 RH |
139 | |
140 | /* RISCVMXL, but uint32_t for vmstate migration */ | |
141 | uint32_t misa_mxl; /* current mxl */ | |
142 | uint32_t misa_mxl_max; /* max mxl for this cpu */ | |
143 | uint32_t misa_ext; /* current extensions */ | |
144 | uint32_t misa_ext_mask; /* max ext for this cpu */ | |
dc5bd18f | 145 | |
b3a5d1fb FP |
146 | /* 128-bit helpers upper part return value */ |
147 | target_ulong retxh; | |
148 | ||
dc5bd18f MC |
149 | uint32_t features; |
150 | ||
5836c3ec KC |
151 | #ifdef CONFIG_USER_ONLY |
152 | uint32_t elf_flags; | |
153 | #endif | |
154 | ||
dc5bd18f MC |
155 | #ifndef CONFIG_USER_ONLY |
156 | target_ulong priv; | |
ef6bb7b6 AF |
157 | /* This contains QEMU specific information about the virt state. */ |
158 | target_ulong virt; | |
dc5bd18f MC |
159 | target_ulong resetvec; |
160 | ||
161 | target_ulong mhartid; | |
284d697c YJ |
162 | /* |
163 | * For RV32 this is 32-bit mstatus and 32-bit mstatush. | |
164 | * For RV64 this is a 64-bit mstatus. | |
165 | */ | |
166 | uint64_t mstatus; | |
85ba724f | 167 | |
02861613 | 168 | target_ulong mip; |
66e594f2 | 169 | |
e3e7039c | 170 | uint32_t miclaim; |
85ba724f | 171 | |
dc5bd18f MC |
172 | target_ulong mie; |
173 | target_ulong mideleg; | |
174 | ||
dc5bd18f | 175 | target_ulong satp; /* since: priv-1.10.0 */ |
ac12b601 | 176 | target_ulong stval; |
dc5bd18f MC |
177 | target_ulong medeleg; |
178 | ||
179 | target_ulong stvec; | |
180 | target_ulong sepc; | |
181 | target_ulong scause; | |
182 | ||
183 | target_ulong mtvec; | |
184 | target_ulong mepc; | |
185 | target_ulong mcause; | |
186 | target_ulong mtval; /* since: priv-1.10.0 */ | |
187 | ||
bd023ce3 AF |
188 | /* Hypervisor CSRs */ |
189 | target_ulong hstatus; | |
190 | target_ulong hedeleg; | |
191 | target_ulong hideleg; | |
192 | target_ulong hcounteren; | |
193 | target_ulong htval; | |
194 | target_ulong htinst; | |
195 | target_ulong hgatp; | |
c6957248 | 196 | uint64_t htimedelta; |
bd023ce3 AF |
197 | |
198 | /* Virtual CSRs */ | |
284d697c YJ |
199 | /* |
200 | * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. | |
201 | * For RV64 this is a 64-bit vsstatus. | |
202 | */ | |
203 | uint64_t vsstatus; | |
bd023ce3 AF |
204 | target_ulong vstvec; |
205 | target_ulong vsscratch; | |
206 | target_ulong vsepc; | |
207 | target_ulong vscause; | |
208 | target_ulong vstval; | |
209 | target_ulong vsatp; | |
210 | ||
211 | target_ulong mtval2; | |
212 | target_ulong mtinst; | |
213 | ||
66e594f2 AF |
214 | /* HS Backup CSRs */ |
215 | target_ulong stvec_hs; | |
216 | target_ulong sscratch_hs; | |
217 | target_ulong sepc_hs; | |
218 | target_ulong scause_hs; | |
219 | target_ulong stval_hs; | |
220 | target_ulong satp_hs; | |
284d697c | 221 | uint64_t mstatus_hs; |
66e594f2 | 222 | |
ec352d0c GK |
223 | /* Signals whether the current exception occurred with two-stage address |
224 | translation active. */ | |
225 | bool two_stage_lookup; | |
226 | ||
8c59f5c1 MC |
227 | target_ulong scounteren; |
228 | target_ulong mcounteren; | |
dc5bd18f MC |
229 | |
230 | target_ulong sscratch; | |
231 | target_ulong mscratch; | |
232 | ||
233 | /* temporary htif regs */ | |
234 | uint64_t mfromhost; | |
235 | uint64_t mtohost; | |
236 | uint64_t timecmp; | |
237 | ||
238 | /* physical memory protection */ | |
239 | pmp_table_t pmp_state; | |
2582a95c | 240 | target_ulong mseccfg; |
753e3fe2 | 241 | |
c6957248 | 242 | /* machine specific rdtime callback */ |
a47ef6e9 BM |
243 | uint64_t (*rdtime_fn)(uint32_t); |
244 | uint32_t rdtime_fn_arg; | |
c6957248 | 245 | |
753e3fe2 JW |
246 | /* True if in debugger mode. */ |
247 | bool debugger; | |
4bbe8033 AB |
248 | |
249 | /* | |
250 | * CSRs for PointerMasking extension | |
251 | */ | |
252 | target_ulong mmte; | |
253 | target_ulong mpmmask; | |
254 | target_ulong mpmbase; | |
255 | target_ulong spmmask; | |
256 | target_ulong spmbase; | |
257 | target_ulong upmmask; | |
258 | target_ulong upmbase; | |
dc5bd18f MC |
259 | #endif |
260 | ||
261 | float_status fp_status; | |
262 | ||
dc5bd18f MC |
263 | /* Fields from here on are preserved across CPU reset. */ |
264 | QEMUTimer *timer; /* Internal timer */ | |
265 | }; | |
266 | ||
c821774a | 267 | OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass, |
30b5707c | 268 | RISCV_CPU) |
dc5bd18f MC |
269 | |
270 | /** | |
271 | * RISCVCPUClass: | |
272 | * @parent_realize: The parent class' realize handler. | |
273 | * @parent_reset: The parent class' reset handler. | |
274 | * | |
275 | * A RISCV CPU model. | |
276 | */ | |
db1015e9 | 277 | struct RISCVCPUClass { |
dc5bd18f MC |
278 | /*< private >*/ |
279 | CPUClass parent_class; | |
280 | /*< public >*/ | |
281 | DeviceRealize parent_realize; | |
781c67ca | 282 | DeviceReset parent_reset; |
db1015e9 | 283 | }; |
dc5bd18f MC |
284 | |
285 | /** | |
286 | * RISCVCPU: | |
287 | * @env: #CPURISCVState | |
288 | * | |
289 | * A RISCV CPU. | |
290 | */ | |
db1015e9 | 291 | struct RISCVCPU { |
dc5bd18f MC |
292 | /*< private >*/ |
293 | CPUState parent_obj; | |
294 | /*< public >*/ | |
5b146dc7 | 295 | CPUNegativeOffsetState neg; |
dc5bd18f | 296 | CPURISCVState env; |
c4e95030 | 297 | |
b93777e1 | 298 | char *dyn_csr_xml; |
719d3561 | 299 | char *dyn_vreg_xml; |
b93777e1 | 300 | |
c4e95030 AF |
301 | /* Configuration Settings */ |
302 | struct { | |
b55d7d34 AF |
303 | bool ext_i; |
304 | bool ext_e; | |
305 | bool ext_g; | |
306 | bool ext_m; | |
307 | bool ext_a; | |
308 | bool ext_f; | |
309 | bool ext_d; | |
310 | bool ext_c; | |
311 | bool ext_s; | |
312 | bool ext_u; | |
c9eefe05 | 313 | bool ext_h; |
53dcea58 | 314 | bool ext_j; |
6bf91617 | 315 | bool ext_v; |
878dd0e9 PT |
316 | bool ext_zba; |
317 | bool ext_zbb; | |
318 | bool ext_zbc; | |
319 | bool ext_zbs; | |
0a13a5b8 | 320 | bool ext_counters; |
50fba816 | 321 | bool ext_ifencei; |
591bddea | 322 | bool ext_icsr; |
915f77b2 | 323 | bool ext_zfh; |
2d258b42 | 324 | bool ext_zfhmin; |
b55d7d34 | 325 | |
c4e95030 AF |
326 | char *priv_spec; |
327 | char *user_spec; | |
d2c1a177 | 328 | char *bext_spec; |
6bf91617 | 329 | char *vext_spec; |
32931383 LZ |
330 | uint16_t vlen; |
331 | uint16_t elen; | |
c4e95030 AF |
332 | bool mmu; |
333 | bool pmp; | |
5da9514e | 334 | bool epmp; |
9b4c9b2b | 335 | uint64_t resetvec; |
c4e95030 | 336 | } cfg; |
db1015e9 | 337 | }; |
dc5bd18f | 338 | |
dc5bd18f MC |
339 | static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) |
340 | { | |
e91a7227 | 341 | return (env->misa_ext & ext) != 0; |
dc5bd18f MC |
342 | } |
343 | ||
344 | static inline bool riscv_feature(CPURISCVState *env, int feature) | |
345 | { | |
346 | return env->features & (1ULL << feature); | |
347 | } | |
348 | ||
349 | #include "cpu_user.h" | |
dc5bd18f MC |
350 | |
351 | extern const char * const riscv_int_regnames[]; | |
2b547084 | 352 | extern const char * const riscv_int_regnamesh[]; |
dc5bd18f | 353 | extern const char * const riscv_fpr_regnames[]; |
dc5bd18f | 354 | |
c51a3f5d | 355 | const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); |
dc5bd18f | 356 | void riscv_cpu_do_interrupt(CPUState *cpu); |
43a96588 YJ |
357 | int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, |
358 | int cpuid, void *opaque); | |
359 | int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, | |
360 | int cpuid, void *opaque); | |
a010bdbe | 361 | int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); |
dc5bd18f | 362 | int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); |
b345b480 | 363 | bool riscv_cpu_fp_enabled(CPURISCVState *env); |
61b4b69d | 364 | bool riscv_cpu_vector_enabled(CPURISCVState *env); |
ef6bb7b6 AF |
365 | bool riscv_cpu_virt_enabled(CPURISCVState *env); |
366 | void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); | |
1c1c060a | 367 | bool riscv_cpu_two_stage_lookup(int mmu_idx); |
dc5bd18f MC |
368 | int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); |
369 | hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); | |
370 | void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, | |
371 | MMUAccessType access_type, int mmu_idx, | |
fa947a66 | 372 | uintptr_t retaddr) QEMU_NORETURN; |
8a4ca3c1 RH |
373 | bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
374 | MMUAccessType access_type, int mmu_idx, | |
375 | bool probe, uintptr_t retaddr); | |
37207e12 PD |
376 | void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, |
377 | vaddr addr, unsigned size, | |
378 | MMUAccessType access_type, | |
379 | int mmu_idx, MemTxAttrs attrs, | |
380 | MemTxResult response, uintptr_t retaddr); | |
dc5bd18f | 381 | char *riscv_isa_string(RISCVCPU *cpu); |
0442428a | 382 | void riscv_cpu_list(void); |
dc5bd18f | 383 | |
dc5bd18f MC |
384 | #define cpu_list riscv_cpu_list |
385 | #define cpu_mmu_index riscv_cpu_mmu_index | |
386 | ||
85ba724f | 387 | #ifndef CONFIG_USER_ONLY |
17b3c353 | 388 | bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); |
66e594f2 | 389 | void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); |
e3e7039c | 390 | int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); |
85ba724f MC |
391 | uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); |
392 | #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ | |
a47ef6e9 BM |
393 | void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), |
394 | uint32_t arg); | |
85ba724f | 395 | #endif |
fb738839 | 396 | void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); |
dc5bd18f MC |
397 | |
398 | void riscv_translate_init(void); | |
fb738839 MC |
399 | void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, |
400 | uint32_t exception, uintptr_t pc); | |
dc5bd18f | 401 | |
fb738839 MC |
402 | target_ulong riscv_cpu_get_fflags(CPURISCVState *env); |
403 | void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); | |
dc5bd18f | 404 | |
c445593d AF |
405 | #define TB_FLAGS_PRIV_MMU_MASK 3 |
406 | #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) | |
83a71719 | 407 | #define TB_FLAGS_MSTATUS_FS MSTATUS_FS |
61b4b69d | 408 | #define TB_FLAGS_MSTATUS_VS MSTATUS_VS |
dc5bd18f | 409 | |
2b7168fc LZ |
410 | typedef CPURISCVState CPUArchState; |
411 | typedef RISCVCPU ArchCPU; | |
412 | #include "exec/cpu-all.h" | |
413 | ||
61d56494 | 414 | FIELD(TB_FLAGS, MEM_IDX, 0, 3) |
33f1beaf | 415 | FIELD(TB_FLAGS, LMUL, 3, 3) |
61d56494 | 416 | FIELD(TB_FLAGS, SEW, 6, 3) |
33f1beaf FC |
417 | /* Skip MSTATUS_VS (0x600) bits */ |
418 | FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) | |
419 | FIELD(TB_FLAGS, VILL, 12, 1) | |
420 | /* Skip MSTATUS_FS (0x6000) bits */ | |
743077b3 | 421 | /* Is a Hypervisor instruction load/store allowed? */ |
33f1beaf FC |
422 | FIELD(TB_FLAGS, HLSX, 15, 1) |
423 | FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) | |
424 | FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) | |
92371bd9 | 425 | /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ |
33f1beaf | 426 | FIELD(TB_FLAGS, XL, 20, 2) |
0774a7a1 | 427 | /* If PointerMasking should be applied */ |
33f1beaf | 428 | FIELD(TB_FLAGS, PM_ENABLED, 22, 1) |
2b7168fc | 429 | |
db23e5d9 RH |
430 | #ifdef TARGET_RISCV32 |
431 | #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) | |
432 | #else | |
433 | static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) | |
434 | { | |
435 | return env->misa_mxl; | |
436 | } | |
437 | #endif | |
51ae0cab | 438 | |
2b7168fc | 439 | /* |
a689a82b FC |
440 | * Encode LMUL to lmul as follows: |
441 | * LMUL vlmul lmul | |
442 | * 1 000 0 | |
443 | * 2 001 1 | |
444 | * 4 010 2 | |
445 | * 8 011 3 | |
446 | * - 100 - | |
447 | * 1/8 101 -3 | |
448 | * 1/4 110 -2 | |
449 | * 1/2 111 -1 | |
450 | * | |
451 | * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) | |
452 | * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 | |
453 | * => VLMAX = vlen >> (1 + 3 - (-3)) | |
454 | * = 256 >> 7 | |
455 | * = 2 | |
2b7168fc LZ |
456 | */ |
457 | static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) | |
458 | { | |
a689a82b FC |
459 | uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); |
460 | int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); | |
2b7168fc LZ |
461 | return cpu->cfg.vlen >> (sew + 3 - lmul); |
462 | } | |
463 | ||
53677acf RH |
464 | void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, |
465 | target_ulong *cs_base, uint32_t *pflags); | |
dc5bd18f | 466 | |
533c91e8 AF |
467 | RISCVException riscv_csrrw(CPURISCVState *env, int csrno, |
468 | target_ulong *ret_value, | |
469 | target_ulong new_value, target_ulong write_mask); | |
470 | RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, | |
471 | target_ulong *ret_value, | |
472 | target_ulong new_value, | |
473 | target_ulong write_mask); | |
c7b95171 | 474 | |
fb738839 MC |
475 | static inline void riscv_csr_write(CPURISCVState *env, int csrno, |
476 | target_ulong val) | |
c7b95171 MC |
477 | { |
478 | riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); | |
479 | } | |
480 | ||
fb738839 | 481 | static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) |
c7b95171 MC |
482 | { |
483 | target_ulong val = 0; | |
484 | riscv_csrrw(env, csrno, &val, 0, 0); | |
485 | return val; | |
486 | } | |
487 | ||
0e62f92e AF |
488 | typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, |
489 | int csrno); | |
605def6e AF |
490 | typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, |
491 | target_ulong *ret_value); | |
492 | typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, | |
493 | target_ulong new_value); | |
494 | typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, | |
495 | target_ulong *ret_value, | |
496 | target_ulong new_value, | |
497 | target_ulong write_mask); | |
c7b95171 MC |
498 | |
499 | typedef struct { | |
8ceac5dc | 500 | const char *name; |
a88365c1 | 501 | riscv_csr_predicate_fn predicate; |
c7b95171 MC |
502 | riscv_csr_read_fn read; |
503 | riscv_csr_write_fn write; | |
504 | riscv_csr_op_fn op; | |
505 | } riscv_csr_operations; | |
506 | ||
56118ee8 BM |
507 | /* CSR function table constants */ |
508 | enum { | |
509 | CSR_TABLE_SIZE = 0x1000 | |
510 | }; | |
511 | ||
512 | /* CSR function table */ | |
6f03770d | 513 | extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; |
56118ee8 | 514 | |
c7b95171 MC |
515 | void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); |
516 | void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); | |
dc5bd18f | 517 | |
5371f5cd JW |
518 | void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); |
519 | ||
dc5bd18f | 520 | #endif /* RISCV_CPU_H */ |