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dc5bd18f MC |
1 | /* |
2 | * QEMU RISC-V CPU | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #ifndef RISCV_CPU_H | |
21 | #define RISCV_CPU_H | |
22 | ||
2e5b09fd | 23 | #include "hw/core/cpu.h" |
2b7168fc | 24 | #include "hw/registerfields.h" |
dc5bd18f | 25 | #include "exec/cpu-defs.h" |
135b03cb | 26 | #include "fpu/softfloat-types.h" |
db1015e9 | 27 | #include "qom/object.h" |
961738ff | 28 | #include "qemu/int128.h" |
e91a7227 | 29 | #include "cpu_bits.h" |
dc5bd18f | 30 | |
74433bf0 RH |
31 | #define TCG_GUEST_DEFAULT_MO 0 |
32 | ||
dc5bd18f MC |
33 | #define TYPE_RISCV_CPU "riscv-cpu" |
34 | ||
35 | #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU | |
36 | #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) | |
0dacec87 | 37 | #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU |
dc5bd18f MC |
38 | |
39 | #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") | |
8903bf6e AF |
40 | #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") |
41 | #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") | |
332dab68 | 42 | #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") |
36b80ad9 | 43 | #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") |
6ddc7069 | 44 | #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") |
dc5bd18f | 45 | #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") |
d784733b | 46 | #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") |
dc5bd18f MC |
47 | #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") |
48 | #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") | |
49 | #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") | |
10f1ca27 | 50 | #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") |
dc5bd18f | 51 | |
c0a635f3 AF |
52 | #if defined(TARGET_RISCV32) |
53 | # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 | |
54 | #elif defined(TARGET_RISCV64) | |
55 | # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 | |
56 | #endif | |
57 | ||
dc5bd18f MC |
58 | #define RV(x) ((target_ulong)1 << (x - 'A')) |
59 | ||
60 | #define RVI RV('I') | |
79f86934 | 61 | #define RVE RV('E') /* E and I are mutually exclusive */ |
dc5bd18f MC |
62 | #define RVM RV('M') |
63 | #define RVA RV('A') | |
64 | #define RVF RV('F') | |
65 | #define RVD RV('D') | |
ad9e5aa2 | 66 | #define RVV RV('V') |
dc5bd18f MC |
67 | #define RVC RV('C') |
68 | #define RVS RV('S') | |
69 | #define RVU RV('U') | |
af1fa003 | 70 | #define RVH RV('H') |
53dcea58 | 71 | #define RVJ RV('J') |
dc5bd18f MC |
72 | |
73 | /* S extension denotes that Supervisor mode exists, however it is possible | |
74 | to have a core that support S mode but does not have an MMU and there | |
75 | is currently no bit in misa to indicate whether an MMU exists or not | |
a88365c1 | 76 | so a cpu features bitfield is required, likewise for optional PMP support */ |
dc5bd18f | 77 | enum { |
a88365c1 | 78 | RISCV_FEATURE_MMU, |
f18637cd | 79 | RISCV_FEATURE_PMP, |
4a345b2a | 80 | RISCV_FEATURE_EPMP, |
32b0ada0 AP |
81 | RISCV_FEATURE_MISA, |
82 | RISCV_FEATURE_AIA | |
dc5bd18f MC |
83 | }; |
84 | ||
dc5bd18f | 85 | #define PRIV_VERSION_1_10_0 0x00011000 |
6729dbbd | 86 | #define PRIV_VERSION_1_11_0 0x00011100 |
dc5bd18f | 87 | |
9ec6622d | 88 | #define VEXT_VERSION_1_00_0 0x00010000 |
32931383 | 89 | |
33a9a57d YJ |
90 | enum { |
91 | TRANSLATE_SUCCESS, | |
92 | TRANSLATE_FAIL, | |
93 | TRANSLATE_PMP_FAIL, | |
94 | TRANSLATE_G_STAGE_FAIL | |
95 | }; | |
96 | ||
dc5bd18f MC |
97 | #define MMU_USER_IDX 3 |
98 | ||
99 | #define MAX_RISCV_PMPS (16) | |
100 | ||
101 | typedef struct CPURISCVState CPURISCVState; | |
102 | ||
bbf3d1b4 | 103 | #if !defined(CONFIG_USER_ONLY) |
dc5bd18f | 104 | #include "pmp.h" |
bbf3d1b4 | 105 | #endif |
dc5bd18f | 106 | |
8a4b5257 | 107 | #define RV_VLEN_MAX 1024 |
ad9e5aa2 | 108 | |
33f1beaf FC |
109 | FIELD(VTYPE, VLMUL, 0, 3) |
110 | FIELD(VTYPE, VSEW, 3, 3) | |
3479a814 FC |
111 | FIELD(VTYPE, VTA, 6, 1) |
112 | FIELD(VTYPE, VMA, 7, 1) | |
33f1beaf FC |
113 | FIELD(VTYPE, VEDIV, 8, 2) |
114 | FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) | |
2b7168fc | 115 | |
dc5bd18f MC |
116 | struct CPURISCVState { |
117 | target_ulong gpr[32]; | |
2b547084 | 118 | target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ |
dc5bd18f | 119 | uint64_t fpr[32]; /* assume both F and D extensions */ |
ad9e5aa2 LZ |
120 | |
121 | /* vector coprocessor state. */ | |
122 | uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); | |
123 | target_ulong vxrm; | |
124 | target_ulong vxsat; | |
125 | target_ulong vl; | |
126 | target_ulong vstart; | |
127 | target_ulong vtype; | |
d96a271a | 128 | bool vill; |
ad9e5aa2 | 129 | |
dc5bd18f MC |
130 | target_ulong pc; |
131 | target_ulong load_res; | |
132 | target_ulong load_val; | |
133 | ||
134 | target_ulong frm; | |
135 | ||
136 | target_ulong badaddr; | |
48eaeb56 AF |
137 | uint32_t bins; |
138 | ||
36a18664 | 139 | target_ulong guest_phys_fault_addr; |
dc5bd18f | 140 | |
dc5bd18f | 141 | target_ulong priv_ver; |
d2c1a177 | 142 | target_ulong bext_ver; |
32931383 | 143 | target_ulong vext_ver; |
e91a7227 RH |
144 | |
145 | /* RISCVMXL, but uint32_t for vmstate migration */ | |
146 | uint32_t misa_mxl; /* current mxl */ | |
147 | uint32_t misa_mxl_max; /* max mxl for this cpu */ | |
148 | uint32_t misa_ext; /* current extensions */ | |
149 | uint32_t misa_ext_mask; /* max ext for this cpu */ | |
440544e1 | 150 | uint32_t xl; /* current xlen */ |
dc5bd18f | 151 | |
b3a5d1fb FP |
152 | /* 128-bit helpers upper part return value */ |
153 | target_ulong retxh; | |
154 | ||
dc5bd18f MC |
155 | uint32_t features; |
156 | ||
5836c3ec KC |
157 | #ifdef CONFIG_USER_ONLY |
158 | uint32_t elf_flags; | |
159 | #endif | |
160 | ||
dc5bd18f MC |
161 | #ifndef CONFIG_USER_ONLY |
162 | target_ulong priv; | |
ef6bb7b6 AF |
163 | /* This contains QEMU specific information about the virt state. */ |
164 | target_ulong virt; | |
cd032fe7 | 165 | target_ulong geilen; |
dc5bd18f MC |
166 | target_ulong resetvec; |
167 | ||
168 | target_ulong mhartid; | |
284d697c YJ |
169 | /* |
170 | * For RV32 this is 32-bit mstatus and 32-bit mstatush. | |
171 | * For RV64 this is a 64-bit mstatus. | |
172 | */ | |
173 | uint64_t mstatus; | |
85ba724f | 174 | |
d028ac75 | 175 | uint64_t mip; |
66e594f2 | 176 | |
d028ac75 | 177 | uint64_t miclaim; |
85ba724f | 178 | |
d028ac75 AP |
179 | uint64_t mie; |
180 | uint64_t mideleg; | |
dc5bd18f | 181 | |
dc5bd18f | 182 | target_ulong satp; /* since: priv-1.10.0 */ |
ac12b601 | 183 | target_ulong stval; |
dc5bd18f MC |
184 | target_ulong medeleg; |
185 | ||
186 | target_ulong stvec; | |
187 | target_ulong sepc; | |
188 | target_ulong scause; | |
189 | ||
190 | target_ulong mtvec; | |
191 | target_ulong mepc; | |
192 | target_ulong mcause; | |
193 | target_ulong mtval; /* since: priv-1.10.0 */ | |
194 | ||
43dc93af AP |
195 | /* Machine and Supervisor interrupt priorities */ |
196 | uint8_t miprio[64]; | |
197 | uint8_t siprio[64]; | |
198 | ||
bd023ce3 AF |
199 | /* Hypervisor CSRs */ |
200 | target_ulong hstatus; | |
201 | target_ulong hedeleg; | |
d028ac75 | 202 | uint64_t hideleg; |
bd023ce3 AF |
203 | target_ulong hcounteren; |
204 | target_ulong htval; | |
205 | target_ulong htinst; | |
206 | target_ulong hgatp; | |
cd032fe7 AP |
207 | target_ulong hgeie; |
208 | target_ulong hgeip; | |
c6957248 | 209 | uint64_t htimedelta; |
bd023ce3 | 210 | |
43dc93af | 211 | /* Hypervisor controlled virtual interrupt priorities */ |
2b602398 | 212 | target_ulong hvictl; |
43dc93af AP |
213 | uint8_t hviprio[64]; |
214 | ||
2c64ab66 FP |
215 | /* Upper 64-bits of 128-bit CSRs */ |
216 | uint64_t mscratchh; | |
217 | uint64_t sscratchh; | |
218 | ||
bd023ce3 | 219 | /* Virtual CSRs */ |
284d697c YJ |
220 | /* |
221 | * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. | |
222 | * For RV64 this is a 64-bit vsstatus. | |
223 | */ | |
224 | uint64_t vsstatus; | |
bd023ce3 AF |
225 | target_ulong vstvec; |
226 | target_ulong vsscratch; | |
227 | target_ulong vsepc; | |
228 | target_ulong vscause; | |
229 | target_ulong vstval; | |
230 | target_ulong vsatp; | |
231 | ||
232 | target_ulong mtval2; | |
233 | target_ulong mtinst; | |
234 | ||
66e594f2 AF |
235 | /* HS Backup CSRs */ |
236 | target_ulong stvec_hs; | |
237 | target_ulong sscratch_hs; | |
238 | target_ulong sepc_hs; | |
239 | target_ulong scause_hs; | |
240 | target_ulong stval_hs; | |
241 | target_ulong satp_hs; | |
284d697c | 242 | uint64_t mstatus_hs; |
66e594f2 | 243 | |
ec352d0c GK |
244 | /* Signals whether the current exception occurred with two-stage address |
245 | translation active. */ | |
246 | bool two_stage_lookup; | |
247 | ||
8c59f5c1 MC |
248 | target_ulong scounteren; |
249 | target_ulong mcounteren; | |
dc5bd18f MC |
250 | |
251 | target_ulong sscratch; | |
252 | target_ulong mscratch; | |
253 | ||
254 | /* temporary htif regs */ | |
255 | uint64_t mfromhost; | |
256 | uint64_t mtohost; | |
257 | uint64_t timecmp; | |
258 | ||
259 | /* physical memory protection */ | |
260 | pmp_table_t pmp_state; | |
2582a95c | 261 | target_ulong mseccfg; |
753e3fe2 | 262 | |
c6957248 | 263 | /* machine specific rdtime callback */ |
a47ef6e9 BM |
264 | uint64_t (*rdtime_fn)(uint32_t); |
265 | uint32_t rdtime_fn_arg; | |
c6957248 | 266 | |
69077dd6 AP |
267 | /* machine specific AIA ireg read-modify-write callback */ |
268 | #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ | |
269 | ((((__xlen) & 0xff) << 24) | \ | |
270 | (((__vgein) & 0x3f) << 20) | \ | |
271 | (((__virt) & 0x1) << 18) | \ | |
272 | (((__priv) & 0x3) << 16) | \ | |
273 | (__isel & 0xffff)) | |
274 | #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) | |
275 | #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) | |
276 | #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) | |
277 | #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) | |
278 | #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) | |
279 | int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, | |
280 | target_ulong *val, target_ulong new_val, target_ulong write_mask); | |
281 | void *aia_ireg_rmw_fn_arg[4]; | |
282 | ||
753e3fe2 JW |
283 | /* True if in debugger mode. */ |
284 | bool debugger; | |
4bbe8033 AB |
285 | |
286 | /* | |
287 | * CSRs for PointerMasking extension | |
288 | */ | |
289 | target_ulong mmte; | |
290 | target_ulong mpmmask; | |
291 | target_ulong mpmbase; | |
292 | target_ulong spmmask; | |
293 | target_ulong spmbase; | |
294 | target_ulong upmmask; | |
295 | target_ulong upmbase; | |
dc5bd18f | 296 | #endif |
40bfa5f6 LZ |
297 | target_ulong cur_pmmask; |
298 | target_ulong cur_pmbase; | |
dc5bd18f MC |
299 | |
300 | float_status fp_status; | |
301 | ||
dc5bd18f MC |
302 | /* Fields from here on are preserved across CPU reset. */ |
303 | QEMUTimer *timer; /* Internal timer */ | |
ad40be27 YJ |
304 | |
305 | hwaddr kernel_addr; | |
306 | hwaddr fdt_addr; | |
27abe66f YJ |
307 | |
308 | /* kvm timer */ | |
309 | bool kvm_timer_dirty; | |
310 | uint64_t kvm_timer_time; | |
311 | uint64_t kvm_timer_compare; | |
312 | uint64_t kvm_timer_state; | |
313 | uint64_t kvm_timer_frequency; | |
dc5bd18f MC |
314 | }; |
315 | ||
c821774a | 316 | OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass, |
30b5707c | 317 | RISCV_CPU) |
dc5bd18f MC |
318 | |
319 | /** | |
320 | * RISCVCPUClass: | |
321 | * @parent_realize: The parent class' realize handler. | |
322 | * @parent_reset: The parent class' reset handler. | |
323 | * | |
324 | * A RISCV CPU model. | |
325 | */ | |
db1015e9 | 326 | struct RISCVCPUClass { |
dc5bd18f MC |
327 | /*< private >*/ |
328 | CPUClass parent_class; | |
329 | /*< public >*/ | |
330 | DeviceRealize parent_realize; | |
781c67ca | 331 | DeviceReset parent_reset; |
db1015e9 | 332 | }; |
dc5bd18f | 333 | |
466292bd PT |
334 | struct RISCVCPUConfig { |
335 | bool ext_i; | |
336 | bool ext_e; | |
337 | bool ext_g; | |
338 | bool ext_m; | |
339 | bool ext_a; | |
340 | bool ext_f; | |
341 | bool ext_d; | |
342 | bool ext_c; | |
343 | bool ext_s; | |
344 | bool ext_u; | |
345 | bool ext_h; | |
346 | bool ext_j; | |
347 | bool ext_v; | |
348 | bool ext_zba; | |
349 | bool ext_zbb; | |
350 | bool ext_zbc; | |
351 | bool ext_zbs; | |
352 | bool ext_counters; | |
353 | bool ext_ifencei; | |
354 | bool ext_icsr; | |
355 | bool ext_zfh; | |
356 | bool ext_zfhmin; | |
357 | bool ext_zve32f; | |
358 | bool ext_zve64f; | |
359 | ||
0d429bd2 PT |
360 | /* Vendor-specific custom extensions */ |
361 | bool ext_XVentanaCondOps; | |
362 | ||
466292bd PT |
363 | char *priv_spec; |
364 | char *user_spec; | |
365 | char *bext_spec; | |
366 | char *vext_spec; | |
367 | uint16_t vlen; | |
368 | uint16_t elen; | |
369 | bool mmu; | |
370 | bool pmp; | |
371 | bool epmp; | |
372 | uint64_t resetvec; | |
373 | }; | |
374 | ||
375 | typedef struct RISCVCPUConfig RISCVCPUConfig; | |
376 | ||
dc5bd18f MC |
377 | /** |
378 | * RISCVCPU: | |
379 | * @env: #CPURISCVState | |
380 | * | |
381 | * A RISCV CPU. | |
382 | */ | |
db1015e9 | 383 | struct RISCVCPU { |
dc5bd18f MC |
384 | /*< private >*/ |
385 | CPUState parent_obj; | |
386 | /*< public >*/ | |
5b146dc7 | 387 | CPUNegativeOffsetState neg; |
dc5bd18f | 388 | CPURISCVState env; |
c4e95030 | 389 | |
b93777e1 | 390 | char *dyn_csr_xml; |
719d3561 | 391 | char *dyn_vreg_xml; |
b93777e1 | 392 | |
c4e95030 | 393 | /* Configuration Settings */ |
466292bd | 394 | RISCVCPUConfig cfg; |
db1015e9 | 395 | }; |
dc5bd18f | 396 | |
dc5bd18f MC |
397 | static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) |
398 | { | |
e91a7227 | 399 | return (env->misa_ext & ext) != 0; |
dc5bd18f MC |
400 | } |
401 | ||
402 | static inline bool riscv_feature(CPURISCVState *env, int feature) | |
403 | { | |
404 | return env->features & (1ULL << feature); | |
405 | } | |
406 | ||
f87adf23 AP |
407 | static inline void riscv_set_feature(CPURISCVState *env, int feature) |
408 | { | |
409 | env->features |= (1ULL << feature); | |
410 | } | |
411 | ||
dc5bd18f | 412 | #include "cpu_user.h" |
dc5bd18f MC |
413 | |
414 | extern const char * const riscv_int_regnames[]; | |
2b547084 | 415 | extern const char * const riscv_int_regnamesh[]; |
dc5bd18f | 416 | extern const char * const riscv_fpr_regnames[]; |
dc5bd18f | 417 | |
c51a3f5d | 418 | const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); |
dc5bd18f | 419 | void riscv_cpu_do_interrupt(CPUState *cpu); |
43a96588 YJ |
420 | int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, |
421 | int cpuid, void *opaque); | |
422 | int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, | |
423 | int cpuid, void *opaque); | |
a010bdbe | 424 | int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); |
dc5bd18f | 425 | int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); |
43dc93af AP |
426 | int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); |
427 | uint8_t riscv_cpu_default_priority(int irq); | |
428 | int riscv_cpu_mirq_pending(CPURISCVState *env); | |
429 | int riscv_cpu_sirq_pending(CPURISCVState *env); | |
430 | int riscv_cpu_vsirq_pending(CPURISCVState *env); | |
b345b480 | 431 | bool riscv_cpu_fp_enabled(CPURISCVState *env); |
cd032fe7 AP |
432 | target_ulong riscv_cpu_get_geilen(CPURISCVState *env); |
433 | void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); | |
61b4b69d | 434 | bool riscv_cpu_vector_enabled(CPURISCVState *env); |
ef6bb7b6 AF |
435 | bool riscv_cpu_virt_enabled(CPURISCVState *env); |
436 | void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); | |
1c1c060a | 437 | bool riscv_cpu_two_stage_lookup(int mmu_idx); |
dc5bd18f MC |
438 | int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); |
439 | hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); | |
440 | void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, | |
441 | MMUAccessType access_type, int mmu_idx, | |
fa947a66 | 442 | uintptr_t retaddr) QEMU_NORETURN; |
8a4ca3c1 RH |
443 | bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
444 | MMUAccessType access_type, int mmu_idx, | |
445 | bool probe, uintptr_t retaddr); | |
37207e12 PD |
446 | void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, |
447 | vaddr addr, unsigned size, | |
448 | MMUAccessType access_type, | |
449 | int mmu_idx, MemTxAttrs attrs, | |
450 | MemTxResult response, uintptr_t retaddr); | |
dc5bd18f | 451 | char *riscv_isa_string(RISCVCPU *cpu); |
0442428a | 452 | void riscv_cpu_list(void); |
dc5bd18f | 453 | |
dc5bd18f MC |
454 | #define cpu_list riscv_cpu_list |
455 | #define cpu_mmu_index riscv_cpu_mmu_index | |
456 | ||
85ba724f | 457 | #ifndef CONFIG_USER_ONLY |
17b3c353 | 458 | bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); |
66e594f2 | 459 | void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); |
d028ac75 AP |
460 | int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); |
461 | uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value); | |
85ba724f | 462 | #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ |
a47ef6e9 BM |
463 | void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), |
464 | uint32_t arg); | |
69077dd6 AP |
465 | void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, |
466 | int (*rmw_fn)(void *arg, | |
467 | target_ulong reg, | |
468 | target_ulong *val, | |
469 | target_ulong new_val, | |
470 | target_ulong write_mask), | |
471 | void *rmw_fn_arg); | |
85ba724f | 472 | #endif |
fb738839 | 473 | void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); |
dc5bd18f MC |
474 | |
475 | void riscv_translate_init(void); | |
fb738839 MC |
476 | void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, |
477 | uint32_t exception, uintptr_t pc); | |
dc5bd18f | 478 | |
fb738839 MC |
479 | target_ulong riscv_cpu_get_fflags(CPURISCVState *env); |
480 | void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); | |
dc5bd18f | 481 | |
c445593d AF |
482 | #define TB_FLAGS_PRIV_MMU_MASK 3 |
483 | #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) | |
83a71719 | 484 | #define TB_FLAGS_MSTATUS_FS MSTATUS_FS |
61b4b69d | 485 | #define TB_FLAGS_MSTATUS_VS MSTATUS_VS |
dc5bd18f | 486 | |
2b7168fc LZ |
487 | typedef CPURISCVState CPUArchState; |
488 | typedef RISCVCPU ArchCPU; | |
489 | #include "exec/cpu-all.h" | |
490 | ||
61d56494 | 491 | FIELD(TB_FLAGS, MEM_IDX, 0, 3) |
33f1beaf | 492 | FIELD(TB_FLAGS, LMUL, 3, 3) |
61d56494 | 493 | FIELD(TB_FLAGS, SEW, 6, 3) |
33f1beaf FC |
494 | /* Skip MSTATUS_VS (0x600) bits */ |
495 | FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) | |
496 | FIELD(TB_FLAGS, VILL, 12, 1) | |
497 | /* Skip MSTATUS_FS (0x6000) bits */ | |
743077b3 | 498 | /* Is a Hypervisor instruction load/store allowed? */ |
33f1beaf FC |
499 | FIELD(TB_FLAGS, HLSX, 15, 1) |
500 | FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) | |
501 | FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) | |
92371bd9 | 502 | /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ |
33f1beaf | 503 | FIELD(TB_FLAGS, XL, 20, 2) |
0774a7a1 | 504 | /* If PointerMasking should be applied */ |
4208dc7e LZ |
505 | FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1) |
506 | FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1) | |
2b7168fc | 507 | |
db23e5d9 RH |
508 | #ifdef TARGET_RISCV32 |
509 | #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) | |
510 | #else | |
511 | static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) | |
512 | { | |
513 | return env->misa_mxl; | |
514 | } | |
515 | #endif | |
2b602398 | 516 | #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) |
51ae0cab | 517 | |
440544e1 LZ |
518 | #if defined(TARGET_RISCV32) |
519 | #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) | |
520 | #else | |
521 | static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) | |
522 | { | |
523 | RISCVMXL xl = env->misa_mxl; | |
524 | #if !defined(CONFIG_USER_ONLY) | |
525 | /* | |
526 | * When emulating a 32-bit-only cpu, use RV32. | |
527 | * When emulating a 64-bit cpu, and MXL has been reduced to RV32, | |
528 | * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened | |
529 | * back to RV64 for lower privs. | |
530 | */ | |
531 | if (xl != MXL_RV32) { | |
532 | switch (env->priv) { | |
533 | case PRV_M: | |
534 | break; | |
535 | case PRV_U: | |
536 | xl = get_field(env->mstatus, MSTATUS64_UXL); | |
537 | break; | |
538 | default: /* PRV_S | PRV_H */ | |
539 | xl = get_field(env->mstatus, MSTATUS64_SXL); | |
540 | break; | |
541 | } | |
542 | } | |
543 | #endif | |
544 | return xl; | |
545 | } | |
546 | #endif | |
547 | ||
31961cfe LZ |
548 | static inline int riscv_cpu_xlen(CPURISCVState *env) |
549 | { | |
550 | return 16 << env->xl; | |
551 | } | |
552 | ||
2b7168fc | 553 | /* |
a689a82b FC |
554 | * Encode LMUL to lmul as follows: |
555 | * LMUL vlmul lmul | |
556 | * 1 000 0 | |
557 | * 2 001 1 | |
558 | * 4 010 2 | |
559 | * 8 011 3 | |
560 | * - 100 - | |
561 | * 1/8 101 -3 | |
562 | * 1/4 110 -2 | |
563 | * 1/2 111 -1 | |
564 | * | |
565 | * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) | |
566 | * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 | |
567 | * => VLMAX = vlen >> (1 + 3 - (-3)) | |
568 | * = 256 >> 7 | |
569 | * = 2 | |
2b7168fc LZ |
570 | */ |
571 | static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) | |
572 | { | |
a689a82b FC |
573 | uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); |
574 | int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); | |
2b7168fc LZ |
575 | return cpu->cfg.vlen >> (sew + 3 - lmul); |
576 | } | |
577 | ||
53677acf RH |
578 | void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, |
579 | target_ulong *cs_base, uint32_t *pflags); | |
dc5bd18f | 580 | |
40bfa5f6 LZ |
581 | void riscv_cpu_update_mask(CPURISCVState *env); |
582 | ||
533c91e8 AF |
583 | RISCVException riscv_csrrw(CPURISCVState *env, int csrno, |
584 | target_ulong *ret_value, | |
585 | target_ulong new_value, target_ulong write_mask); | |
586 | RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, | |
587 | target_ulong *ret_value, | |
588 | target_ulong new_value, | |
589 | target_ulong write_mask); | |
c7b95171 | 590 | |
fb738839 MC |
591 | static inline void riscv_csr_write(CPURISCVState *env, int csrno, |
592 | target_ulong val) | |
c7b95171 MC |
593 | { |
594 | riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); | |
595 | } | |
596 | ||
fb738839 | 597 | static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) |
c7b95171 MC |
598 | { |
599 | target_ulong val = 0; | |
600 | riscv_csrrw(env, csrno, &val, 0, 0); | |
601 | return val; | |
602 | } | |
603 | ||
0e62f92e AF |
604 | typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, |
605 | int csrno); | |
605def6e AF |
606 | typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, |
607 | target_ulong *ret_value); | |
608 | typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, | |
609 | target_ulong new_value); | |
610 | typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, | |
611 | target_ulong *ret_value, | |
612 | target_ulong new_value, | |
613 | target_ulong write_mask); | |
c7b95171 | 614 | |
961738ff FP |
615 | RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, |
616 | Int128 *ret_value, | |
617 | Int128 new_value, Int128 write_mask); | |
618 | ||
457c360f FP |
619 | typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, |
620 | Int128 *ret_value); | |
621 | typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, | |
622 | Int128 new_value); | |
623 | ||
c7b95171 | 624 | typedef struct { |
8ceac5dc | 625 | const char *name; |
a88365c1 | 626 | riscv_csr_predicate_fn predicate; |
c7b95171 MC |
627 | riscv_csr_read_fn read; |
628 | riscv_csr_write_fn write; | |
629 | riscv_csr_op_fn op; | |
457c360f FP |
630 | riscv_csr_read128_fn read128; |
631 | riscv_csr_write128_fn write128; | |
c7b95171 MC |
632 | } riscv_csr_operations; |
633 | ||
56118ee8 BM |
634 | /* CSR function table constants */ |
635 | enum { | |
636 | CSR_TABLE_SIZE = 0x1000 | |
637 | }; | |
638 | ||
639 | /* CSR function table */ | |
6f03770d | 640 | extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; |
56118ee8 | 641 | |
c7b95171 MC |
642 | void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); |
643 | void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); | |
dc5bd18f | 644 | |
5371f5cd JW |
645 | void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); |
646 | ||
dc5bd18f | 647 | #endif /* RISCV_CPU_H */ |