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dc5bd18f MC |
1 | /* |
2 | * QEMU RISC-V CPU | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #ifndef RISCV_CPU_H | |
21 | #define RISCV_CPU_H | |
22 | ||
2e5b09fd | 23 | #include "hw/core/cpu.h" |
2b7168fc | 24 | #include "hw/registerfields.h" |
dc5bd18f | 25 | #include "exec/cpu-defs.h" |
69242e7e | 26 | #include "qemu/cpu-float.h" |
db1015e9 | 27 | #include "qom/object.h" |
961738ff | 28 | #include "qemu/int128.h" |
e91a7227 | 29 | #include "cpu_bits.h" |
6f23aaeb | 30 | #include "qapi/qapi-types-common.h" |
dc5bd18f | 31 | |
74433bf0 RH |
32 | #define TCG_GUEST_DEFAULT_MO 0 |
33 | ||
62cf0245 AP |
34 | /* |
35 | * RISC-V-specific extra insn start words: | |
36 | * 1: Original instruction opcode | |
37 | */ | |
38 | #define TARGET_INSN_START_EXTRA_WORDS 1 | |
39 | ||
dc5bd18f MC |
40 | #define TYPE_RISCV_CPU "riscv-cpu" |
41 | ||
42 | #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU | |
43 | #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) | |
0dacec87 | 44 | #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU |
dc5bd18f MC |
45 | |
46 | #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") | |
8903bf6e AF |
47 | #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") |
48 | #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") | |
332dab68 | 49 | #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") |
36b80ad9 | 50 | #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") |
6ddc7069 | 51 | #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") |
dc5bd18f | 52 | #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") |
d784733b | 53 | #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") |
dc5bd18f MC |
54 | #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") |
55 | #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") | |
56 | #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") | |
95bd8daa | 57 | #define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") |
10f1ca27 | 58 | #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") |
dc5bd18f | 59 | |
c0a635f3 AF |
60 | #if defined(TARGET_RISCV32) |
61 | # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 | |
62 | #elif defined(TARGET_RISCV64) | |
63 | # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 | |
64 | #endif | |
65 | ||
dc5bd18f MC |
66 | #define RV(x) ((target_ulong)1 << (x - 'A')) |
67 | ||
dd8f244f | 68 | /* Consider updating misa_ext_cfgs[] when adding new MISA bits here */ |
dc5bd18f | 69 | #define RVI RV('I') |
79f86934 | 70 | #define RVE RV('E') /* E and I are mutually exclusive */ |
dc5bd18f MC |
71 | #define RVM RV('M') |
72 | #define RVA RV('A') | |
73 | #define RVF RV('F') | |
74 | #define RVD RV('D') | |
ad9e5aa2 | 75 | #define RVV RV('V') |
dc5bd18f MC |
76 | #define RVC RV('C') |
77 | #define RVS RV('S') | |
78 | #define RVU RV('U') | |
af1fa003 | 79 | #define RVH RV('H') |
53dcea58 | 80 | #define RVJ RV('J') |
4f13abcb | 81 | #define RVG RV('G') |
dc5bd18f | 82 | |
dc5bd18f | 83 | |
a46d410c AP |
84 | /* Privileged specification version */ |
85 | enum { | |
86 | PRIV_VERSION_1_10_0 = 0, | |
87 | PRIV_VERSION_1_11_0, | |
3a4af26d | 88 | PRIV_VERSION_1_12_0, |
a46d410c | 89 | }; |
dc5bd18f | 90 | |
9ec6622d | 91 | #define VEXT_VERSION_1_00_0 0x00010000 |
32931383 | 92 | |
33a9a57d YJ |
93 | enum { |
94 | TRANSLATE_SUCCESS, | |
95 | TRANSLATE_FAIL, | |
96 | TRANSLATE_PMP_FAIL, | |
97 | TRANSLATE_G_STAGE_FAIL | |
98 | }; | |
99 | ||
42967f40 LZ |
100 | /* Extension context status */ |
101 | typedef enum { | |
102 | EXT_STATUS_DISABLED = 0, | |
103 | EXT_STATUS_INITIAL, | |
104 | EXT_STATUS_CLEAN, | |
105 | EXT_STATUS_DIRTY, | |
106 | } RISCVExtStatus; | |
107 | ||
dc5bd18f MC |
108 | #define MMU_USER_IDX 3 |
109 | ||
110 | #define MAX_RISCV_PMPS (16) | |
111 | ||
1ea4a06a | 112 | typedef struct CPUArchState CPURISCVState; |
dc5bd18f | 113 | |
bbf3d1b4 | 114 | #if !defined(CONFIG_USER_ONLY) |
dc5bd18f | 115 | #include "pmp.h" |
95799e36 | 116 | #include "debug.h" |
bbf3d1b4 | 117 | #endif |
dc5bd18f | 118 | |
8a4b5257 | 119 | #define RV_VLEN_MAX 1024 |
3780e337 | 120 | #define RV_MAX_MHPMEVENTS 32 |
621f35bb | 121 | #define RV_MAX_MHPMCOUNTERS 32 |
ad9e5aa2 | 122 | |
33f1beaf FC |
123 | FIELD(VTYPE, VLMUL, 0, 3) |
124 | FIELD(VTYPE, VSEW, 3, 3) | |
3479a814 FC |
125 | FIELD(VTYPE, VTA, 6, 1) |
126 | FIELD(VTYPE, VMA, 7, 1) | |
33f1beaf FC |
127 | FIELD(VTYPE, VEDIV, 8, 2) |
128 | FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) | |
2b7168fc | 129 | |
3780e337 AP |
130 | typedef struct PMUCTRState { |
131 | /* Current value of a counter */ | |
132 | target_ulong mhpmcounter_val; | |
3b57254d | 133 | /* Current value of a counter in RV32 */ |
3780e337 AP |
134 | target_ulong mhpmcounterh_val; |
135 | /* Snapshot values of counter */ | |
136 | target_ulong mhpmcounter_prev; | |
137 | /* Snapshort value of a counter in RV32 */ | |
138 | target_ulong mhpmcounterh_prev; | |
139 | bool started; | |
14664483 AP |
140 | /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */ |
141 | target_ulong irq_overflow_left; | |
3780e337 AP |
142 | } PMUCTRState; |
143 | ||
1ea4a06a | 144 | struct CPUArchState { |
dc5bd18f | 145 | target_ulong gpr[32]; |
2b547084 | 146 | target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ |
ad9e5aa2 LZ |
147 | |
148 | /* vector coprocessor state. */ | |
149 | uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); | |
150 | target_ulong vxrm; | |
151 | target_ulong vxsat; | |
152 | target_ulong vl; | |
153 | target_ulong vstart; | |
154 | target_ulong vtype; | |
d96a271a | 155 | bool vill; |
ad9e5aa2 | 156 | |
dc5bd18f MC |
157 | target_ulong pc; |
158 | target_ulong load_res; | |
159 | target_ulong load_val; | |
160 | ||
04bc3027 PMD |
161 | /* Floating-Point state */ |
162 | uint64_t fpr[32]; /* assume both F and D extensions */ | |
dc5bd18f | 163 | target_ulong frm; |
04bc3027 | 164 | float_status fp_status; |
dc5bd18f MC |
165 | |
166 | target_ulong badaddr; | |
62cf0245 | 167 | target_ulong bins; |
48eaeb56 | 168 | |
36a18664 | 169 | target_ulong guest_phys_fault_addr; |
dc5bd18f | 170 | |
dc5bd18f | 171 | target_ulong priv_ver; |
d2c1a177 | 172 | target_ulong bext_ver; |
32931383 | 173 | target_ulong vext_ver; |
e91a7227 RH |
174 | |
175 | /* RISCVMXL, but uint32_t for vmstate migration */ | |
176 | uint32_t misa_mxl; /* current mxl */ | |
177 | uint32_t misa_mxl_max; /* max mxl for this cpu */ | |
178 | uint32_t misa_ext; /* current extensions */ | |
179 | uint32_t misa_ext_mask; /* max ext for this cpu */ | |
440544e1 | 180 | uint32_t xl; /* current xlen */ |
dc5bd18f | 181 | |
b3a5d1fb FP |
182 | /* 128-bit helpers upper part return value */ |
183 | target_ulong retxh; | |
184 | ||
ce3af0bb WL |
185 | target_ulong jvt; |
186 | ||
5836c3ec KC |
187 | #ifdef CONFIG_USER_ONLY |
188 | uint32_t elf_flags; | |
189 | #endif | |
190 | ||
dc5bd18f MC |
191 | #ifndef CONFIG_USER_ONLY |
192 | target_ulong priv; | |
ef6bb7b6 | 193 | /* This contains QEMU specific information about the virt state. */ |
b3c5077b | 194 | bool virt_enabled; |
cd032fe7 | 195 | target_ulong geilen; |
277b210d | 196 | uint64_t resetvec; |
dc5bd18f MC |
197 | |
198 | target_ulong mhartid; | |
284d697c YJ |
199 | /* |
200 | * For RV32 this is 32-bit mstatus and 32-bit mstatush. | |
201 | * For RV64 this is a 64-bit mstatus. | |
202 | */ | |
203 | uint64_t mstatus; | |
85ba724f | 204 | |
d028ac75 | 205 | uint64_t mip; |
33fe584f AF |
206 | /* |
207 | * MIP contains the software writable version of SEIP ORed with the | |
208 | * external interrupt value. The MIP register is always up-to-date. | |
209 | * To keep track of the current source, we also save booleans of the values | |
210 | * here. | |
211 | */ | |
212 | bool external_seip; | |
213 | bool software_seip; | |
66e594f2 | 214 | |
d028ac75 | 215 | uint64_t miclaim; |
85ba724f | 216 | |
d028ac75 AP |
217 | uint64_t mie; |
218 | uint64_t mideleg; | |
dc5bd18f | 219 | |
dc5bd18f | 220 | target_ulong satp; /* since: priv-1.10.0 */ |
ac12b601 | 221 | target_ulong stval; |
dc5bd18f MC |
222 | target_ulong medeleg; |
223 | ||
224 | target_ulong stvec; | |
225 | target_ulong sepc; | |
226 | target_ulong scause; | |
227 | ||
228 | target_ulong mtvec; | |
229 | target_ulong mepc; | |
230 | target_ulong mcause; | |
231 | target_ulong mtval; /* since: priv-1.10.0 */ | |
232 | ||
43dc93af AP |
233 | /* Machine and Supervisor interrupt priorities */ |
234 | uint8_t miprio[64]; | |
235 | uint8_t siprio[64]; | |
236 | ||
d1ceff40 AP |
237 | /* AIA CSRs */ |
238 | target_ulong miselect; | |
239 | target_ulong siselect; | |
240 | ||
bd023ce3 AF |
241 | /* Hypervisor CSRs */ |
242 | target_ulong hstatus; | |
243 | target_ulong hedeleg; | |
d028ac75 | 244 | uint64_t hideleg; |
bd023ce3 AF |
245 | target_ulong hcounteren; |
246 | target_ulong htval; | |
247 | target_ulong htinst; | |
248 | target_ulong hgatp; | |
cd032fe7 AP |
249 | target_ulong hgeie; |
250 | target_ulong hgeip; | |
c6957248 | 251 | uint64_t htimedelta; |
bd023ce3 | 252 | |
43dc93af | 253 | /* Hypervisor controlled virtual interrupt priorities */ |
2b602398 | 254 | target_ulong hvictl; |
43dc93af AP |
255 | uint8_t hviprio[64]; |
256 | ||
2c64ab66 FP |
257 | /* Upper 64-bits of 128-bit CSRs */ |
258 | uint64_t mscratchh; | |
259 | uint64_t sscratchh; | |
260 | ||
bd023ce3 | 261 | /* Virtual CSRs */ |
284d697c YJ |
262 | /* |
263 | * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. | |
264 | * For RV64 this is a 64-bit vsstatus. | |
265 | */ | |
266 | uint64_t vsstatus; | |
bd023ce3 AF |
267 | target_ulong vstvec; |
268 | target_ulong vsscratch; | |
269 | target_ulong vsepc; | |
270 | target_ulong vscause; | |
271 | target_ulong vstval; | |
272 | target_ulong vsatp; | |
273 | ||
d1ceff40 AP |
274 | /* AIA VS-mode CSRs */ |
275 | target_ulong vsiselect; | |
276 | ||
bd023ce3 AF |
277 | target_ulong mtval2; |
278 | target_ulong mtinst; | |
279 | ||
66e594f2 AF |
280 | /* HS Backup CSRs */ |
281 | target_ulong stvec_hs; | |
282 | target_ulong sscratch_hs; | |
283 | target_ulong sepc_hs; | |
284 | target_ulong scause_hs; | |
285 | target_ulong stval_hs; | |
286 | target_ulong satp_hs; | |
284d697c | 287 | uint64_t mstatus_hs; |
66e594f2 | 288 | |
3b57254d WL |
289 | /* |
290 | * Signals whether the current exception occurred with two-stage address | |
291 | * translation active. | |
292 | */ | |
ec352d0c | 293 | bool two_stage_lookup; |
8e2aa21b AP |
294 | /* |
295 | * Signals whether the current exception occurred while doing two-stage | |
296 | * address translation for the VS-stage page table walk. | |
297 | */ | |
298 | bool two_stage_indirect_lookup; | |
ec352d0c | 299 | |
8c59f5c1 MC |
300 | target_ulong scounteren; |
301 | target_ulong mcounteren; | |
dc5bd18f | 302 | |
b1675eeb AP |
303 | target_ulong mcountinhibit; |
304 | ||
3780e337 AP |
305 | /* PMU counter state */ |
306 | PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; | |
621f35bb | 307 | |
3b57254d | 308 | /* PMU event selector configured values. First three are unused */ |
621f35bb AP |
309 | target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; |
310 | ||
3b57254d | 311 | /* PMU event selector configured values for RV32 */ |
14664483 AP |
312 | target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; |
313 | ||
dc5bd18f MC |
314 | target_ulong sscratch; |
315 | target_ulong mscratch; | |
316 | ||
43888c2f AP |
317 | /* Sstc CSRs */ |
318 | uint64_t stimecmp; | |
319 | ||
3ec0fe18 AP |
320 | uint64_t vstimecmp; |
321 | ||
dc5bd18f MC |
322 | /* physical memory protection */ |
323 | pmp_table_t pmp_state; | |
2582a95c | 324 | target_ulong mseccfg; |
753e3fe2 | 325 | |
95799e36 BM |
326 | /* trigger module */ |
327 | target_ulong trigger_cur; | |
9495c488 FC |
328 | target_ulong tdata1[RV_MAX_TRIGGERS]; |
329 | target_ulong tdata2[RV_MAX_TRIGGERS]; | |
330 | target_ulong tdata3[RV_MAX_TRIGGERS]; | |
331 | struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; | |
332 | struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; | |
5a4ae64c LZ |
333 | QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; |
334 | int64_t last_icount; | |
577f0286 | 335 | bool itrigger_enabled; |
95799e36 | 336 | |
c6957248 | 337 | /* machine specific rdtime callback */ |
e2f01f3c FC |
338 | uint64_t (*rdtime_fn)(void *); |
339 | void *rdtime_fn_arg; | |
c6957248 | 340 | |
69077dd6 AP |
341 | /* machine specific AIA ireg read-modify-write callback */ |
342 | #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ | |
343 | ((((__xlen) & 0xff) << 24) | \ | |
344 | (((__vgein) & 0x3f) << 20) | \ | |
345 | (((__virt) & 0x1) << 18) | \ | |
346 | (((__priv) & 0x3) << 16) | \ | |
347 | (__isel & 0xffff)) | |
348 | #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) | |
349 | #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) | |
350 | #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) | |
351 | #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) | |
352 | #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) | |
353 | int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, | |
354 | target_ulong *val, target_ulong new_val, target_ulong write_mask); | |
355 | void *aia_ireg_rmw_fn_arg[4]; | |
356 | ||
753e3fe2 JW |
357 | /* True if in debugger mode. */ |
358 | bool debugger; | |
4bbe8033 AB |
359 | |
360 | /* | |
361 | * CSRs for PointerMasking extension | |
362 | */ | |
363 | target_ulong mmte; | |
364 | target_ulong mpmmask; | |
365 | target_ulong mpmbase; | |
366 | target_ulong spmmask; | |
367 | target_ulong spmbase; | |
368 | target_ulong upmmask; | |
369 | target_ulong upmbase; | |
29a9ec9b AP |
370 | |
371 | /* CSRs for execution enviornment configuration */ | |
372 | uint64_t menvcfg; | |
3bee0e40 MC |
373 | uint64_t mstateen[SMSTATEEN_MAX_COUNT]; |
374 | uint64_t hstateen[SMSTATEEN_MAX_COUNT]; | |
375 | uint64_t sstateen[SMSTATEEN_MAX_COUNT]; | |
29a9ec9b AP |
376 | target_ulong senvcfg; |
377 | uint64_t henvcfg; | |
dc5bd18f | 378 | #endif |
40bfa5f6 LZ |
379 | target_ulong cur_pmmask; |
380 | target_ulong cur_pmbase; | |
dc5bd18f | 381 | |
dc5bd18f | 382 | /* Fields from here on are preserved across CPU reset. */ |
43888c2f | 383 | QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ |
3ec0fe18 AP |
384 | QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */ |
385 | bool vstime_irq; | |
ad40be27 YJ |
386 | |
387 | hwaddr kernel_addr; | |
388 | hwaddr fdt_addr; | |
27abe66f YJ |
389 | |
390 | /* kvm timer */ | |
391 | bool kvm_timer_dirty; | |
392 | uint64_t kvm_timer_time; | |
393 | uint64_t kvm_timer_compare; | |
394 | uint64_t kvm_timer_state; | |
395 | uint64_t kvm_timer_frequency; | |
dc5bd18f MC |
396 | }; |
397 | ||
9295b1aa | 398 | OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) |
dc5bd18f | 399 | |
3b57254d | 400 | /* |
dc5bd18f MC |
401 | * RISCVCPUClass: |
402 | * @parent_realize: The parent class' realize handler. | |
4fa485a7 | 403 | * @parent_phases: The parent class' reset phase handlers. |
dc5bd18f MC |
404 | * |
405 | * A RISCV CPU model. | |
406 | */ | |
db1015e9 | 407 | struct RISCVCPUClass { |
3b57254d | 408 | /* < private > */ |
dc5bd18f | 409 | CPUClass parent_class; |
3b57254d | 410 | /* < public > */ |
dc5bd18f | 411 | DeviceRealize parent_realize; |
4fa485a7 | 412 | ResettablePhases parent_phases; |
db1015e9 | 413 | }; |
dc5bd18f | 414 | |
6f23aaeb AG |
415 | /* |
416 | * map is a 16-bit bitmap: the most significant set bit in map is the maximum | |
6df3747a AG |
417 | * satp mode that is supported. It may be chosen by the user and must respect |
418 | * what qemu implements (valid_1_10_32/64) and what the hw is capable of | |
419 | * (supported bitmap below). | |
6f23aaeb AG |
420 | * |
421 | * init is a 16-bit bitmap used to make sure the user selected a correct | |
422 | * configuration as per the specification. | |
6df3747a AG |
423 | * |
424 | * supported is a 16-bit bitmap used to reflect the hw capabilities. | |
6f23aaeb AG |
425 | */ |
426 | typedef struct { | |
6df3747a | 427 | uint16_t map, init, supported; |
6f23aaeb AG |
428 | } RISCVSATPMap; |
429 | ||
466292bd | 430 | struct RISCVCPUConfig { |
466292bd PT |
431 | bool ext_zba; |
432 | bool ext_zbb; | |
433 | bool ext_zbc; | |
eef82872 WL |
434 | bool ext_zbkb; |
435 | bool ext_zbkc; | |
436 | bool ext_zbkx; | |
466292bd | 437 | bool ext_zbs; |
2288a5ce WL |
438 | bool ext_zca; |
439 | bool ext_zcb; | |
440 | bool ext_zcd; | |
00d312bd | 441 | bool ext_zce; |
2288a5ce WL |
442 | bool ext_zcf; |
443 | bool ext_zcmp; | |
444 | bool ext_zcmt; | |
eef82872 WL |
445 | bool ext_zk; |
446 | bool ext_zkn; | |
447 | bool ext_zknd; | |
448 | bool ext_zkne; | |
449 | bool ext_zknh; | |
450 | bool ext_zkr; | |
451 | bool ext_zks; | |
452 | bool ext_zksed; | |
453 | bool ext_zksh; | |
454 | bool ext_zkt; | |
466292bd PT |
455 | bool ext_ifencei; |
456 | bool ext_icsr; | |
e05da09b | 457 | bool ext_icbom; |
a939c500 | 458 | bool ext_icboz; |
b8e1f32c | 459 | bool ext_zicond; |
4696f0ab | 460 | bool ext_zihintpause; |
3bee0e40 | 461 | bool ext_smstateen; |
43888c2f | 462 | bool ext_sstc; |
0d190bd3 | 463 | bool ext_svadu; |
c5d77ddd | 464 | bool ext_svinval; |
05e6ca5e GR |
465 | bool ext_svnapot; |
466 | bool ext_svpbmt; | |
89ffdcec | 467 | bool ext_zdinx; |
260b594d | 468 | bool ext_zawrs; |
466292bd PT |
469 | bool ext_zfh; |
470 | bool ext_zfhmin; | |
89ffdcec WL |
471 | bool ext_zfinx; |
472 | bool ext_zhinx; | |
473 | bool ext_zhinxmin; | |
466292bd PT |
474 | bool ext_zve32f; |
475 | bool ext_zve64f; | |
a7336161 | 476 | bool ext_zve64d; |
de799beb | 477 | bool ext_zmmul; |
a7336161 WL |
478 | bool ext_zvfh; |
479 | bool ext_zvfhmin; | |
dc9acc9c AP |
480 | bool ext_smaia; |
481 | bool ext_ssaia; | |
14664483 | 482 | bool ext_sscofpmf; |
f1eed927 | 483 | bool rvv_ta_all_1s; |
355d5584 | 484 | bool rvv_ma_all_1s; |
466292bd | 485 | |
9951ba94 FC |
486 | uint32_t mvendorid; |
487 | uint64_t marchid; | |
075eeda9 | 488 | uint64_t mimpid; |
9951ba94 | 489 | |
0d429bd2 | 490 | /* Vendor-specific custom extensions */ |
c9410a68 | 491 | bool ext_xtheadba; |
426c0491 | 492 | bool ext_xtheadbb; |
fa134585 | 493 | bool ext_xtheadbs; |
49a7f3aa | 494 | bool ext_xtheadcmo; |
32909338 | 495 | bool ext_xtheadcondmov; |
d4d90115 | 496 | bool ext_xtheadfmemidx; |
578086ba | 497 | bool ext_xtheadfmv; |
b8a5832b | 498 | bool ext_xtheadmac; |
45f9df86 | 499 | bool ext_xtheadmemidx; |
af99aa72 | 500 | bool ext_xtheadmempair; |
134c3ffa | 501 | bool ext_xtheadsync; |
0d429bd2 PT |
502 | bool ext_XVentanaCondOps; |
503 | ||
18d6d89e | 504 | uint8_t pmu_num; |
466292bd PT |
505 | char *priv_spec; |
506 | char *user_spec; | |
507 | char *bext_spec; | |
508 | char *vext_spec; | |
509 | uint16_t vlen; | |
510 | uint16_t elen; | |
e05da09b | 511 | uint16_t cbom_blocksize; |
a939c500 | 512 | uint16_t cboz_blocksize; |
466292bd PT |
513 | bool mmu; |
514 | bool pmp; | |
515 | bool epmp; | |
1acdb3b0 | 516 | bool debug; |
54bd9b6e | 517 | bool misa_w; |
a4a9a443 TO |
518 | |
519 | bool short_isa_string; | |
6f23aaeb AG |
520 | |
521 | #ifndef CONFIG_USER_ONLY | |
522 | RISCVSATPMap satp_mode; | |
523 | #endif | |
466292bd PT |
524 | }; |
525 | ||
526 | typedef struct RISCVCPUConfig RISCVCPUConfig; | |
527 | ||
3b57254d | 528 | /* |
dc5bd18f MC |
529 | * RISCVCPU: |
530 | * @env: #CPURISCVState | |
531 | * | |
532 | * A RISCV CPU. | |
533 | */ | |
b36e239e | 534 | struct ArchCPU { |
3b57254d | 535 | /* < private > */ |
dc5bd18f | 536 | CPUState parent_obj; |
3b57254d | 537 | /* < public > */ |
5b146dc7 | 538 | CPUNegativeOffsetState neg; |
dc5bd18f | 539 | CPURISCVState env; |
c4e95030 | 540 | |
b93777e1 | 541 | char *dyn_csr_xml; |
719d3561 | 542 | char *dyn_vreg_xml; |
b93777e1 | 543 | |
c4e95030 | 544 | /* Configuration Settings */ |
466292bd | 545 | RISCVCPUConfig cfg; |
14664483 AP |
546 | |
547 | QEMUTimer *pmu_timer; | |
548 | /* A bitmask of Available programmable counters */ | |
549 | uint32_t pmu_avail_ctrs; | |
550 | /* Mapping of events to counters */ | |
551 | GHashTable *pmu_event_ctr_map; | |
db1015e9 | 552 | }; |
dc5bd18f | 553 | |
dc5bd18f MC |
554 | static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) |
555 | { | |
e91a7227 | 556 | return (env->misa_ext & ext) != 0; |
dc5bd18f MC |
557 | } |
558 | ||
dc5bd18f | 559 | #include "cpu_user.h" |
dc5bd18f MC |
560 | |
561 | extern const char * const riscv_int_regnames[]; | |
2b547084 | 562 | extern const char * const riscv_int_regnamesh[]; |
dc5bd18f | 563 | extern const char * const riscv_fpr_regnames[]; |
dc5bd18f | 564 | |
c51a3f5d | 565 | const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); |
dc5bd18f | 566 | void riscv_cpu_do_interrupt(CPUState *cpu); |
43a96588 | 567 | int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, |
1af0006a | 568 | int cpuid, DumpState *s); |
43a96588 | 569 | int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, |
1af0006a | 570 | int cpuid, DumpState *s); |
a010bdbe | 571 | int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); |
dc5bd18f | 572 | int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); |
43dc93af AP |
573 | int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); |
574 | uint8_t riscv_cpu_default_priority(int irq); | |
8f42415f | 575 | uint64_t riscv_cpu_all_pending(CPURISCVState *env); |
43dc93af AP |
576 | int riscv_cpu_mirq_pending(CPURISCVState *env); |
577 | int riscv_cpu_sirq_pending(CPURISCVState *env); | |
578 | int riscv_cpu_vsirq_pending(CPURISCVState *env); | |
b345b480 | 579 | bool riscv_cpu_fp_enabled(CPURISCVState *env); |
cd032fe7 AP |
580 | target_ulong riscv_cpu_get_geilen(CPURISCVState *env); |
581 | void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); | |
61b4b69d | 582 | bool riscv_cpu_vector_enabled(CPURISCVState *env); |
ef6bb7b6 | 583 | void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); |
1c1c060a | 584 | bool riscv_cpu_two_stage_lookup(int mmu_idx); |
dc5bd18f | 585 | int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); |
8905770b | 586 | G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, |
246f8796 WL |
587 | MMUAccessType access_type, |
588 | int mmu_idx, uintptr_t retaddr); | |
8a4ca3c1 RH |
589 | bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
590 | MMUAccessType access_type, int mmu_idx, | |
591 | bool probe, uintptr_t retaddr); | |
dc5bd18f | 592 | char *riscv_isa_string(RISCVCPU *cpu); |
0442428a | 593 | void riscv_cpu_list(void); |
dc5bd18f | 594 | |
dc5bd18f MC |
595 | #define cpu_list riscv_cpu_list |
596 | #define cpu_mmu_index riscv_cpu_mmu_index | |
597 | ||
85ba724f | 598 | #ifndef CONFIG_USER_ONLY |
d90ebc47 PMD |
599 | void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, |
600 | vaddr addr, unsigned size, | |
601 | MMUAccessType access_type, | |
602 | int mmu_idx, MemTxAttrs attrs, | |
603 | MemTxResult response, uintptr_t retaddr); | |
6d2d454a | 604 | hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); |
17b3c353 | 605 | bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); |
66e594f2 | 606 | void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); |
d028ac75 | 607 | int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); |
bbb9fc25 WL |
608 | uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, |
609 | uint64_t value); | |
85ba724f | 610 | #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ |
e2f01f3c FC |
611 | void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), |
612 | void *arg); | |
69077dd6 AP |
613 | void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, |
614 | int (*rmw_fn)(void *arg, | |
615 | target_ulong reg, | |
616 | target_ulong *val, | |
617 | target_ulong new_val, | |
618 | target_ulong write_mask), | |
619 | void *rmw_fn_arg); | |
ce3af0bb WL |
620 | |
621 | RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit); | |
85ba724f | 622 | #endif |
fb738839 | 623 | void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); |
dc5bd18f MC |
624 | |
625 | void riscv_translate_init(void); | |
8905770b MAL |
626 | G_NORETURN void riscv_raise_exception(CPURISCVState *env, |
627 | uint32_t exception, uintptr_t pc); | |
dc5bd18f | 628 | |
fb738839 MC |
629 | target_ulong riscv_cpu_get_fflags(CPURISCVState *env); |
630 | void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); | |
dc5bd18f | 631 | |
2b7168fc LZ |
632 | #include "exec/cpu-all.h" |
633 | ||
61d56494 | 634 | FIELD(TB_FLAGS, MEM_IDX, 0, 3) |
ebd47648 LZ |
635 | FIELD(TB_FLAGS, FS, 3, 2) |
636 | /* Vector flags */ | |
637 | FIELD(TB_FLAGS, VS, 5, 2) | |
638 | FIELD(TB_FLAGS, LMUL, 7, 3) | |
639 | FIELD(TB_FLAGS, SEW, 10, 3) | |
640 | FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1) | |
641 | FIELD(TB_FLAGS, VILL, 14, 1) | |
743077b3 | 642 | /* Is a Hypervisor instruction load/store allowed? */ |
33f1beaf | 643 | FIELD(TB_FLAGS, HLSX, 15, 1) |
92371bd9 | 644 | /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ |
25f3ddff | 645 | FIELD(TB_FLAGS, XL, 16, 2) |
0774a7a1 | 646 | /* If PointerMasking should be applied */ |
25f3ddff RH |
647 | FIELD(TB_FLAGS, PM_MASK_ENABLED, 18, 1) |
648 | FIELD(TB_FLAGS, PM_BASE_ENABLED, 19, 1) | |
649 | FIELD(TB_FLAGS, VTA, 20, 1) | |
650 | FIELD(TB_FLAGS, VMA, 21, 1) | |
2c9d7471 | 651 | /* Native debug itrigger */ |
25f3ddff | 652 | FIELD(TB_FLAGS, ITRIGGER, 22, 1) |
f1966390 | 653 | /* Virtual mode enabled */ |
25f3ddff | 654 | FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1) |
4acaa133 | 655 | FIELD(TB_FLAGS, VSTART_EQ_ZERO, 24, 1) |
47debc72 | 656 | FIELD(TB_FLAGS, PRIV, 25, 2) |
2b7168fc | 657 | |
db23e5d9 RH |
658 | #ifdef TARGET_RISCV32 |
659 | #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) | |
660 | #else | |
661 | static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) | |
662 | { | |
663 | return env->misa_mxl; | |
664 | } | |
665 | #endif | |
2b602398 | 666 | #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) |
51ae0cab | 667 | |
d4ea7117 DHB |
668 | static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) |
669 | { | |
670 | return &env_archcpu(env)->cfg; | |
671 | } | |
672 | ||
440544e1 LZ |
673 | #if defined(TARGET_RISCV32) |
674 | #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) | |
675 | #else | |
676 | static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) | |
677 | { | |
678 | RISCVMXL xl = env->misa_mxl; | |
679 | #if !defined(CONFIG_USER_ONLY) | |
680 | /* | |
681 | * When emulating a 32-bit-only cpu, use RV32. | |
682 | * When emulating a 64-bit cpu, and MXL has been reduced to RV32, | |
683 | * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened | |
684 | * back to RV64 for lower privs. | |
685 | */ | |
686 | if (xl != MXL_RV32) { | |
687 | switch (env->priv) { | |
688 | case PRV_M: | |
689 | break; | |
690 | case PRV_U: | |
691 | xl = get_field(env->mstatus, MSTATUS64_UXL); | |
692 | break; | |
44b8f74b | 693 | default: /* PRV_S */ |
440544e1 LZ |
694 | xl = get_field(env->mstatus, MSTATUS64_SXL); |
695 | break; | |
696 | } | |
697 | } | |
698 | #endif | |
699 | return xl; | |
700 | } | |
701 | #endif | |
702 | ||
31961cfe LZ |
703 | static inline int riscv_cpu_xlen(CPURISCVState *env) |
704 | { | |
705 | return 16 << env->xl; | |
706 | } | |
707 | ||
05e6ca5e GR |
708 | #ifdef TARGET_RISCV32 |
709 | #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) | |
710 | #else | |
711 | static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) | |
712 | { | |
713 | #ifdef CONFIG_USER_ONLY | |
714 | return env->misa_mxl; | |
715 | #else | |
716 | return get_field(env->mstatus, MSTATUS64_SXL); | |
717 | #endif | |
718 | } | |
719 | #endif | |
720 | ||
2b7168fc | 721 | /* |
a689a82b FC |
722 | * Encode LMUL to lmul as follows: |
723 | * LMUL vlmul lmul | |
724 | * 1 000 0 | |
725 | * 2 001 1 | |
726 | * 4 010 2 | |
727 | * 8 011 3 | |
728 | * - 100 - | |
729 | * 1/8 101 -3 | |
730 | * 1/4 110 -2 | |
731 | * 1/2 111 -1 | |
732 | * | |
733 | * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) | |
734 | * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 | |
735 | * => VLMAX = vlen >> (1 + 3 - (-3)) | |
736 | * = 256 >> 7 | |
737 | * = 2 | |
2b7168fc LZ |
738 | */ |
739 | static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) | |
740 | { | |
a689a82b FC |
741 | uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); |
742 | int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); | |
2b7168fc LZ |
743 | return cpu->cfg.vlen >> (sew + 3 - lmul); |
744 | } | |
745 | ||
53677acf RH |
746 | void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, |
747 | target_ulong *cs_base, uint32_t *pflags); | |
dc5bd18f | 748 | |
40bfa5f6 LZ |
749 | void riscv_cpu_update_mask(CPURISCVState *env); |
750 | ||
533c91e8 AF |
751 | RISCVException riscv_csrrw(CPURISCVState *env, int csrno, |
752 | target_ulong *ret_value, | |
753 | target_ulong new_value, target_ulong write_mask); | |
754 | RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, | |
755 | target_ulong *ret_value, | |
756 | target_ulong new_value, | |
757 | target_ulong write_mask); | |
c7b95171 | 758 | |
fb738839 MC |
759 | static inline void riscv_csr_write(CPURISCVState *env, int csrno, |
760 | target_ulong val) | |
c7b95171 MC |
761 | { |
762 | riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); | |
763 | } | |
764 | ||
fb738839 | 765 | static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) |
c7b95171 MC |
766 | { |
767 | target_ulong val = 0; | |
768 | riscv_csrrw(env, csrno, &val, 0, 0); | |
769 | return val; | |
770 | } | |
771 | ||
0e62f92e AF |
772 | typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, |
773 | int csrno); | |
605def6e AF |
774 | typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, |
775 | target_ulong *ret_value); | |
776 | typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, | |
777 | target_ulong new_value); | |
778 | typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, | |
779 | target_ulong *ret_value, | |
780 | target_ulong new_value, | |
781 | target_ulong write_mask); | |
c7b95171 | 782 | |
961738ff FP |
783 | RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, |
784 | Int128 *ret_value, | |
785 | Int128 new_value, Int128 write_mask); | |
786 | ||
457c360f FP |
787 | typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, |
788 | Int128 *ret_value); | |
789 | typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, | |
790 | Int128 new_value); | |
791 | ||
c7b95171 | 792 | typedef struct { |
8ceac5dc | 793 | const char *name; |
a88365c1 | 794 | riscv_csr_predicate_fn predicate; |
c7b95171 MC |
795 | riscv_csr_read_fn read; |
796 | riscv_csr_write_fn write; | |
797 | riscv_csr_op_fn op; | |
457c360f FP |
798 | riscv_csr_read128_fn read128; |
799 | riscv_csr_write128_fn write128; | |
a4b2fa43 AP |
800 | /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ |
801 | uint32_t min_priv_ver; | |
c7b95171 MC |
802 | } riscv_csr_operations; |
803 | ||
56118ee8 BM |
804 | /* CSR function table constants */ |
805 | enum { | |
806 | CSR_TABLE_SIZE = 0x1000 | |
807 | }; | |
808 | ||
3b57254d | 809 | /* |
14664483 AP |
810 | * The event id are encoded based on the encoding specified in the |
811 | * SBI specification v0.3 | |
812 | */ | |
813 | ||
814 | enum riscv_pmu_event_idx { | |
815 | RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01, | |
816 | RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02, | |
817 | RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019, | |
818 | RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B, | |
819 | RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021, | |
820 | }; | |
821 | ||
56118ee8 | 822 | /* CSR function table */ |
6f03770d | 823 | extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; |
56118ee8 | 824 | |
6f23aaeb AG |
825 | extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; |
826 | ||
c7b95171 MC |
827 | void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); |
828 | void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); | |
dc5bd18f | 829 | |
5371f5cd JW |
830 | void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); |
831 | ||
6f23aaeb AG |
832 | uint8_t satp_mode_max_from_map(uint32_t map); |
833 | const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); | |
834 | ||
dc5bd18f | 835 | #endif /* RISCV_CPU_H */ |