]>
Commit | Line | Data |
---|---|---|
dc5bd18f MC |
1 | /* |
2 | * QEMU RISC-V CPU | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #ifndef RISCV_CPU_H | |
21 | #define RISCV_CPU_H | |
22 | ||
2e5b09fd | 23 | #include "hw/core/cpu.h" |
2b7168fc | 24 | #include "hw/registerfields.h" |
dc5bd18f | 25 | #include "exec/cpu-defs.h" |
69242e7e | 26 | #include "qemu/cpu-float.h" |
db1015e9 | 27 | #include "qom/object.h" |
961738ff | 28 | #include "qemu/int128.h" |
e91a7227 | 29 | #include "cpu_bits.h" |
dc5bd18f | 30 | |
74433bf0 RH |
31 | #define TCG_GUEST_DEFAULT_MO 0 |
32 | ||
62cf0245 AP |
33 | /* |
34 | * RISC-V-specific extra insn start words: | |
35 | * 1: Original instruction opcode | |
36 | */ | |
37 | #define TARGET_INSN_START_EXTRA_WORDS 1 | |
38 | ||
dc5bd18f MC |
39 | #define TYPE_RISCV_CPU "riscv-cpu" |
40 | ||
41 | #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU | |
42 | #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) | |
0dacec87 | 43 | #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU |
dc5bd18f MC |
44 | |
45 | #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") | |
8903bf6e AF |
46 | #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") |
47 | #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") | |
332dab68 | 48 | #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") |
36b80ad9 | 49 | #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") |
6ddc7069 | 50 | #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") |
dc5bd18f | 51 | #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") |
d784733b | 52 | #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") |
dc5bd18f MC |
53 | #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") |
54 | #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") | |
55 | #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") | |
10f1ca27 | 56 | #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") |
dc5bd18f | 57 | |
c0a635f3 AF |
58 | #if defined(TARGET_RISCV32) |
59 | # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 | |
60 | #elif defined(TARGET_RISCV64) | |
61 | # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 | |
62 | #endif | |
63 | ||
dc5bd18f MC |
64 | #define RV(x) ((target_ulong)1 << (x - 'A')) |
65 | ||
66 | #define RVI RV('I') | |
79f86934 | 67 | #define RVE RV('E') /* E and I are mutually exclusive */ |
dc5bd18f MC |
68 | #define RVM RV('M') |
69 | #define RVA RV('A') | |
70 | #define RVF RV('F') | |
71 | #define RVD RV('D') | |
ad9e5aa2 | 72 | #define RVV RV('V') |
dc5bd18f MC |
73 | #define RVC RV('C') |
74 | #define RVS RV('S') | |
75 | #define RVU RV('U') | |
af1fa003 | 76 | #define RVH RV('H') |
53dcea58 | 77 | #define RVJ RV('J') |
dc5bd18f MC |
78 | |
79 | /* S extension denotes that Supervisor mode exists, however it is possible | |
80 | to have a core that support S mode but does not have an MMU and there | |
81 | is currently no bit in misa to indicate whether an MMU exists or not | |
a88365c1 | 82 | so a cpu features bitfield is required, likewise for optional PMP support */ |
dc5bd18f | 83 | enum { |
a88365c1 | 84 | RISCV_FEATURE_MMU, |
f18637cd | 85 | RISCV_FEATURE_PMP, |
4a345b2a | 86 | RISCV_FEATURE_EPMP, |
32b0ada0 | 87 | RISCV_FEATURE_MISA, |
1acdb3b0 | 88 | RISCV_FEATURE_DEBUG |
dc5bd18f MC |
89 | }; |
90 | ||
a46d410c AP |
91 | /* Privileged specification version */ |
92 | enum { | |
93 | PRIV_VERSION_1_10_0 = 0, | |
94 | PRIV_VERSION_1_11_0, | |
3a4af26d | 95 | PRIV_VERSION_1_12_0, |
a46d410c | 96 | }; |
dc5bd18f | 97 | |
9ec6622d | 98 | #define VEXT_VERSION_1_00_0 0x00010000 |
32931383 | 99 | |
33a9a57d YJ |
100 | enum { |
101 | TRANSLATE_SUCCESS, | |
102 | TRANSLATE_FAIL, | |
103 | TRANSLATE_PMP_FAIL, | |
104 | TRANSLATE_G_STAGE_FAIL | |
105 | }; | |
106 | ||
dc5bd18f MC |
107 | #define MMU_USER_IDX 3 |
108 | ||
109 | #define MAX_RISCV_PMPS (16) | |
110 | ||
1ea4a06a | 111 | typedef struct CPUArchState CPURISCVState; |
dc5bd18f | 112 | |
bbf3d1b4 | 113 | #if !defined(CONFIG_USER_ONLY) |
dc5bd18f | 114 | #include "pmp.h" |
95799e36 | 115 | #include "debug.h" |
bbf3d1b4 | 116 | #endif |
dc5bd18f | 117 | |
8a4b5257 | 118 | #define RV_VLEN_MAX 1024 |
3780e337 | 119 | #define RV_MAX_MHPMEVENTS 32 |
621f35bb | 120 | #define RV_MAX_MHPMCOUNTERS 32 |
ad9e5aa2 | 121 | |
33f1beaf FC |
122 | FIELD(VTYPE, VLMUL, 0, 3) |
123 | FIELD(VTYPE, VSEW, 3, 3) | |
3479a814 FC |
124 | FIELD(VTYPE, VTA, 6, 1) |
125 | FIELD(VTYPE, VMA, 7, 1) | |
33f1beaf FC |
126 | FIELD(VTYPE, VEDIV, 8, 2) |
127 | FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) | |
2b7168fc | 128 | |
3780e337 AP |
129 | typedef struct PMUCTRState { |
130 | /* Current value of a counter */ | |
131 | target_ulong mhpmcounter_val; | |
132 | /* Current value of a counter in RV32*/ | |
133 | target_ulong mhpmcounterh_val; | |
134 | /* Snapshot values of counter */ | |
135 | target_ulong mhpmcounter_prev; | |
136 | /* Snapshort value of a counter in RV32 */ | |
137 | target_ulong mhpmcounterh_prev; | |
138 | bool started; | |
14664483 AP |
139 | /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */ |
140 | target_ulong irq_overflow_left; | |
3780e337 AP |
141 | } PMUCTRState; |
142 | ||
1ea4a06a | 143 | struct CPUArchState { |
dc5bd18f | 144 | target_ulong gpr[32]; |
2b547084 | 145 | target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ |
dc5bd18f | 146 | uint64_t fpr[32]; /* assume both F and D extensions */ |
ad9e5aa2 LZ |
147 | |
148 | /* vector coprocessor state. */ | |
149 | uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); | |
150 | target_ulong vxrm; | |
151 | target_ulong vxsat; | |
152 | target_ulong vl; | |
153 | target_ulong vstart; | |
154 | target_ulong vtype; | |
d96a271a | 155 | bool vill; |
ad9e5aa2 | 156 | |
dc5bd18f MC |
157 | target_ulong pc; |
158 | target_ulong load_res; | |
159 | target_ulong load_val; | |
160 | ||
161 | target_ulong frm; | |
162 | ||
163 | target_ulong badaddr; | |
62cf0245 | 164 | target_ulong bins; |
48eaeb56 | 165 | |
36a18664 | 166 | target_ulong guest_phys_fault_addr; |
dc5bd18f | 167 | |
dc5bd18f | 168 | target_ulong priv_ver; |
d2c1a177 | 169 | target_ulong bext_ver; |
32931383 | 170 | target_ulong vext_ver; |
e91a7227 RH |
171 | |
172 | /* RISCVMXL, but uint32_t for vmstate migration */ | |
173 | uint32_t misa_mxl; /* current mxl */ | |
174 | uint32_t misa_mxl_max; /* max mxl for this cpu */ | |
175 | uint32_t misa_ext; /* current extensions */ | |
176 | uint32_t misa_ext_mask; /* max ext for this cpu */ | |
440544e1 | 177 | uint32_t xl; /* current xlen */ |
dc5bd18f | 178 | |
b3a5d1fb FP |
179 | /* 128-bit helpers upper part return value */ |
180 | target_ulong retxh; | |
181 | ||
dc5bd18f MC |
182 | uint32_t features; |
183 | ||
5836c3ec KC |
184 | #ifdef CONFIG_USER_ONLY |
185 | uint32_t elf_flags; | |
186 | #endif | |
187 | ||
dc5bd18f MC |
188 | #ifndef CONFIG_USER_ONLY |
189 | target_ulong priv; | |
ef6bb7b6 AF |
190 | /* This contains QEMU specific information about the virt state. */ |
191 | target_ulong virt; | |
cd032fe7 | 192 | target_ulong geilen; |
277b210d | 193 | uint64_t resetvec; |
dc5bd18f MC |
194 | |
195 | target_ulong mhartid; | |
284d697c YJ |
196 | /* |
197 | * For RV32 this is 32-bit mstatus and 32-bit mstatush. | |
198 | * For RV64 this is a 64-bit mstatus. | |
199 | */ | |
200 | uint64_t mstatus; | |
85ba724f | 201 | |
d028ac75 | 202 | uint64_t mip; |
33fe584f AF |
203 | /* |
204 | * MIP contains the software writable version of SEIP ORed with the | |
205 | * external interrupt value. The MIP register is always up-to-date. | |
206 | * To keep track of the current source, we also save booleans of the values | |
207 | * here. | |
208 | */ | |
209 | bool external_seip; | |
210 | bool software_seip; | |
66e594f2 | 211 | |
d028ac75 | 212 | uint64_t miclaim; |
85ba724f | 213 | |
d028ac75 AP |
214 | uint64_t mie; |
215 | uint64_t mideleg; | |
dc5bd18f | 216 | |
dc5bd18f | 217 | target_ulong satp; /* since: priv-1.10.0 */ |
ac12b601 | 218 | target_ulong stval; |
dc5bd18f MC |
219 | target_ulong medeleg; |
220 | ||
221 | target_ulong stvec; | |
222 | target_ulong sepc; | |
223 | target_ulong scause; | |
224 | ||
225 | target_ulong mtvec; | |
226 | target_ulong mepc; | |
227 | target_ulong mcause; | |
228 | target_ulong mtval; /* since: priv-1.10.0 */ | |
229 | ||
43dc93af AP |
230 | /* Machine and Supervisor interrupt priorities */ |
231 | uint8_t miprio[64]; | |
232 | uint8_t siprio[64]; | |
233 | ||
d1ceff40 AP |
234 | /* AIA CSRs */ |
235 | target_ulong miselect; | |
236 | target_ulong siselect; | |
237 | ||
bd023ce3 AF |
238 | /* Hypervisor CSRs */ |
239 | target_ulong hstatus; | |
240 | target_ulong hedeleg; | |
d028ac75 | 241 | uint64_t hideleg; |
bd023ce3 AF |
242 | target_ulong hcounteren; |
243 | target_ulong htval; | |
244 | target_ulong htinst; | |
245 | target_ulong hgatp; | |
cd032fe7 AP |
246 | target_ulong hgeie; |
247 | target_ulong hgeip; | |
c6957248 | 248 | uint64_t htimedelta; |
bd023ce3 | 249 | |
43dc93af | 250 | /* Hypervisor controlled virtual interrupt priorities */ |
2b602398 | 251 | target_ulong hvictl; |
43dc93af AP |
252 | uint8_t hviprio[64]; |
253 | ||
2c64ab66 FP |
254 | /* Upper 64-bits of 128-bit CSRs */ |
255 | uint64_t mscratchh; | |
256 | uint64_t sscratchh; | |
257 | ||
bd023ce3 | 258 | /* Virtual CSRs */ |
284d697c YJ |
259 | /* |
260 | * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. | |
261 | * For RV64 this is a 64-bit vsstatus. | |
262 | */ | |
263 | uint64_t vsstatus; | |
bd023ce3 AF |
264 | target_ulong vstvec; |
265 | target_ulong vsscratch; | |
266 | target_ulong vsepc; | |
267 | target_ulong vscause; | |
268 | target_ulong vstval; | |
269 | target_ulong vsatp; | |
270 | ||
d1ceff40 AP |
271 | /* AIA VS-mode CSRs */ |
272 | target_ulong vsiselect; | |
273 | ||
bd023ce3 AF |
274 | target_ulong mtval2; |
275 | target_ulong mtinst; | |
276 | ||
66e594f2 AF |
277 | /* HS Backup CSRs */ |
278 | target_ulong stvec_hs; | |
279 | target_ulong sscratch_hs; | |
280 | target_ulong sepc_hs; | |
281 | target_ulong scause_hs; | |
282 | target_ulong stval_hs; | |
283 | target_ulong satp_hs; | |
284d697c | 284 | uint64_t mstatus_hs; |
66e594f2 | 285 | |
ec352d0c GK |
286 | /* Signals whether the current exception occurred with two-stage address |
287 | translation active. */ | |
288 | bool two_stage_lookup; | |
8e2aa21b AP |
289 | /* |
290 | * Signals whether the current exception occurred while doing two-stage | |
291 | * address translation for the VS-stage page table walk. | |
292 | */ | |
293 | bool two_stage_indirect_lookup; | |
ec352d0c | 294 | |
8c59f5c1 MC |
295 | target_ulong scounteren; |
296 | target_ulong mcounteren; | |
dc5bd18f | 297 | |
b1675eeb AP |
298 | target_ulong mcountinhibit; |
299 | ||
3780e337 AP |
300 | /* PMU counter state */ |
301 | PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; | |
621f35bb | 302 | |
3780e337 | 303 | /* PMU event selector configured values. First three are unused*/ |
621f35bb AP |
304 | target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; |
305 | ||
14664483 AP |
306 | /* PMU event selector configured values for RV32*/ |
307 | target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; | |
308 | ||
dc5bd18f MC |
309 | target_ulong sscratch; |
310 | target_ulong mscratch; | |
311 | ||
312 | /* temporary htif regs */ | |
313 | uint64_t mfromhost; | |
314 | uint64_t mtohost; | |
dc5bd18f | 315 | |
43888c2f AP |
316 | /* Sstc CSRs */ |
317 | uint64_t stimecmp; | |
318 | ||
3ec0fe18 AP |
319 | uint64_t vstimecmp; |
320 | ||
dc5bd18f MC |
321 | /* physical memory protection */ |
322 | pmp_table_t pmp_state; | |
2582a95c | 323 | target_ulong mseccfg; |
753e3fe2 | 324 | |
95799e36 BM |
325 | /* trigger module */ |
326 | target_ulong trigger_cur; | |
9495c488 FC |
327 | target_ulong tdata1[RV_MAX_TRIGGERS]; |
328 | target_ulong tdata2[RV_MAX_TRIGGERS]; | |
329 | target_ulong tdata3[RV_MAX_TRIGGERS]; | |
330 | struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; | |
331 | struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; | |
95799e36 | 332 | |
c6957248 | 333 | /* machine specific rdtime callback */ |
e2f01f3c FC |
334 | uint64_t (*rdtime_fn)(void *); |
335 | void *rdtime_fn_arg; | |
c6957248 | 336 | |
69077dd6 AP |
337 | /* machine specific AIA ireg read-modify-write callback */ |
338 | #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ | |
339 | ((((__xlen) & 0xff) << 24) | \ | |
340 | (((__vgein) & 0x3f) << 20) | \ | |
341 | (((__virt) & 0x1) << 18) | \ | |
342 | (((__priv) & 0x3) << 16) | \ | |
343 | (__isel & 0xffff)) | |
344 | #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) | |
345 | #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) | |
346 | #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) | |
347 | #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) | |
348 | #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) | |
349 | int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, | |
350 | target_ulong *val, target_ulong new_val, target_ulong write_mask); | |
351 | void *aia_ireg_rmw_fn_arg[4]; | |
352 | ||
753e3fe2 JW |
353 | /* True if in debugger mode. */ |
354 | bool debugger; | |
4bbe8033 AB |
355 | |
356 | /* | |
357 | * CSRs for PointerMasking extension | |
358 | */ | |
359 | target_ulong mmte; | |
360 | target_ulong mpmmask; | |
361 | target_ulong mpmbase; | |
362 | target_ulong spmmask; | |
363 | target_ulong spmbase; | |
364 | target_ulong upmmask; | |
365 | target_ulong upmbase; | |
29a9ec9b AP |
366 | |
367 | /* CSRs for execution enviornment configuration */ | |
368 | uint64_t menvcfg; | |
369 | target_ulong senvcfg; | |
370 | uint64_t henvcfg; | |
dc5bd18f | 371 | #endif |
40bfa5f6 LZ |
372 | target_ulong cur_pmmask; |
373 | target_ulong cur_pmbase; | |
dc5bd18f MC |
374 | |
375 | float_status fp_status; | |
376 | ||
dc5bd18f | 377 | /* Fields from here on are preserved across CPU reset. */ |
43888c2f | 378 | QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ |
3ec0fe18 AP |
379 | QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */ |
380 | bool vstime_irq; | |
ad40be27 YJ |
381 | |
382 | hwaddr kernel_addr; | |
383 | hwaddr fdt_addr; | |
27abe66f YJ |
384 | |
385 | /* kvm timer */ | |
386 | bool kvm_timer_dirty; | |
387 | uint64_t kvm_timer_time; | |
388 | uint64_t kvm_timer_compare; | |
389 | uint64_t kvm_timer_state; | |
390 | uint64_t kvm_timer_frequency; | |
dc5bd18f MC |
391 | }; |
392 | ||
9295b1aa | 393 | OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) |
dc5bd18f MC |
394 | |
395 | /** | |
396 | * RISCVCPUClass: | |
397 | * @parent_realize: The parent class' realize handler. | |
398 | * @parent_reset: The parent class' reset handler. | |
399 | * | |
400 | * A RISCV CPU model. | |
401 | */ | |
db1015e9 | 402 | struct RISCVCPUClass { |
dc5bd18f MC |
403 | /*< private >*/ |
404 | CPUClass parent_class; | |
405 | /*< public >*/ | |
406 | DeviceRealize parent_realize; | |
781c67ca | 407 | DeviceReset parent_reset; |
db1015e9 | 408 | }; |
dc5bd18f | 409 | |
466292bd PT |
410 | struct RISCVCPUConfig { |
411 | bool ext_i; | |
412 | bool ext_e; | |
413 | bool ext_g; | |
414 | bool ext_m; | |
415 | bool ext_a; | |
416 | bool ext_f; | |
417 | bool ext_d; | |
418 | bool ext_c; | |
419 | bool ext_s; | |
420 | bool ext_u; | |
421 | bool ext_h; | |
422 | bool ext_j; | |
423 | bool ext_v; | |
424 | bool ext_zba; | |
425 | bool ext_zbb; | |
426 | bool ext_zbc; | |
eef82872 WL |
427 | bool ext_zbkb; |
428 | bool ext_zbkc; | |
429 | bool ext_zbkx; | |
466292bd | 430 | bool ext_zbs; |
eef82872 WL |
431 | bool ext_zk; |
432 | bool ext_zkn; | |
433 | bool ext_zknd; | |
434 | bool ext_zkne; | |
435 | bool ext_zknh; | |
436 | bool ext_zkr; | |
437 | bool ext_zks; | |
438 | bool ext_zksed; | |
439 | bool ext_zksh; | |
440 | bool ext_zkt; | |
466292bd PT |
441 | bool ext_ifencei; |
442 | bool ext_icsr; | |
4696f0ab | 443 | bool ext_zihintpause; |
43888c2f | 444 | bool ext_sstc; |
c5d77ddd | 445 | bool ext_svinval; |
05e6ca5e GR |
446 | bool ext_svnapot; |
447 | bool ext_svpbmt; | |
89ffdcec | 448 | bool ext_zdinx; |
466292bd PT |
449 | bool ext_zfh; |
450 | bool ext_zfhmin; | |
89ffdcec WL |
451 | bool ext_zfinx; |
452 | bool ext_zhinx; | |
453 | bool ext_zhinxmin; | |
466292bd PT |
454 | bool ext_zve32f; |
455 | bool ext_zve64f; | |
de799beb | 456 | bool ext_zmmul; |
dc9acc9c AP |
457 | bool ext_smaia; |
458 | bool ext_ssaia; | |
14664483 | 459 | bool ext_sscofpmf; |
f1eed927 | 460 | bool rvv_ta_all_1s; |
355d5584 | 461 | bool rvv_ma_all_1s; |
466292bd | 462 | |
9951ba94 FC |
463 | uint32_t mvendorid; |
464 | uint64_t marchid; | |
075eeda9 | 465 | uint64_t mimpid; |
9951ba94 | 466 | |
0d429bd2 PT |
467 | /* Vendor-specific custom extensions */ |
468 | bool ext_XVentanaCondOps; | |
469 | ||
18d6d89e | 470 | uint8_t pmu_num; |
466292bd PT |
471 | char *priv_spec; |
472 | char *user_spec; | |
473 | char *bext_spec; | |
474 | char *vext_spec; | |
475 | uint16_t vlen; | |
476 | uint16_t elen; | |
477 | bool mmu; | |
478 | bool pmp; | |
479 | bool epmp; | |
1acdb3b0 | 480 | bool debug; |
a4a9a443 TO |
481 | |
482 | bool short_isa_string; | |
466292bd PT |
483 | }; |
484 | ||
485 | typedef struct RISCVCPUConfig RISCVCPUConfig; | |
486 | ||
dc5bd18f MC |
487 | /** |
488 | * RISCVCPU: | |
489 | * @env: #CPURISCVState | |
490 | * | |
491 | * A RISCV CPU. | |
492 | */ | |
b36e239e | 493 | struct ArchCPU { |
dc5bd18f MC |
494 | /*< private >*/ |
495 | CPUState parent_obj; | |
496 | /*< public >*/ | |
5b146dc7 | 497 | CPUNegativeOffsetState neg; |
dc5bd18f | 498 | CPURISCVState env; |
c4e95030 | 499 | |
b93777e1 | 500 | char *dyn_csr_xml; |
719d3561 | 501 | char *dyn_vreg_xml; |
b93777e1 | 502 | |
c4e95030 | 503 | /* Configuration Settings */ |
466292bd | 504 | RISCVCPUConfig cfg; |
14664483 AP |
505 | |
506 | QEMUTimer *pmu_timer; | |
507 | /* A bitmask of Available programmable counters */ | |
508 | uint32_t pmu_avail_ctrs; | |
509 | /* Mapping of events to counters */ | |
510 | GHashTable *pmu_event_ctr_map; | |
db1015e9 | 511 | }; |
dc5bd18f | 512 | |
dc5bd18f MC |
513 | static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) |
514 | { | |
e91a7227 | 515 | return (env->misa_ext & ext) != 0; |
dc5bd18f MC |
516 | } |
517 | ||
518 | static inline bool riscv_feature(CPURISCVState *env, int feature) | |
519 | { | |
520 | return env->features & (1ULL << feature); | |
521 | } | |
522 | ||
f87adf23 AP |
523 | static inline void riscv_set_feature(CPURISCVState *env, int feature) |
524 | { | |
525 | env->features |= (1ULL << feature); | |
526 | } | |
527 | ||
dc5bd18f | 528 | #include "cpu_user.h" |
dc5bd18f MC |
529 | |
530 | extern const char * const riscv_int_regnames[]; | |
2b547084 | 531 | extern const char * const riscv_int_regnamesh[]; |
dc5bd18f | 532 | extern const char * const riscv_fpr_regnames[]; |
dc5bd18f | 533 | |
c51a3f5d | 534 | const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); |
dc5bd18f | 535 | void riscv_cpu_do_interrupt(CPUState *cpu); |
43a96588 YJ |
536 | int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, |
537 | int cpuid, void *opaque); | |
538 | int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, | |
539 | int cpuid, void *opaque); | |
a010bdbe | 540 | int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); |
dc5bd18f | 541 | int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); |
43dc93af AP |
542 | int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); |
543 | uint8_t riscv_cpu_default_priority(int irq); | |
8f42415f | 544 | uint64_t riscv_cpu_all_pending(CPURISCVState *env); |
43dc93af AP |
545 | int riscv_cpu_mirq_pending(CPURISCVState *env); |
546 | int riscv_cpu_sirq_pending(CPURISCVState *env); | |
547 | int riscv_cpu_vsirq_pending(CPURISCVState *env); | |
b345b480 | 548 | bool riscv_cpu_fp_enabled(CPURISCVState *env); |
cd032fe7 AP |
549 | target_ulong riscv_cpu_get_geilen(CPURISCVState *env); |
550 | void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); | |
61b4b69d | 551 | bool riscv_cpu_vector_enabled(CPURISCVState *env); |
ef6bb7b6 AF |
552 | bool riscv_cpu_virt_enabled(CPURISCVState *env); |
553 | void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); | |
1c1c060a | 554 | bool riscv_cpu_two_stage_lookup(int mmu_idx); |
dc5bd18f MC |
555 | int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); |
556 | hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); | |
8905770b MAL |
557 | G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, |
558 | MMUAccessType access_type, int mmu_idx, | |
559 | uintptr_t retaddr); | |
8a4ca3c1 RH |
560 | bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
561 | MMUAccessType access_type, int mmu_idx, | |
562 | bool probe, uintptr_t retaddr); | |
37207e12 PD |
563 | void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, |
564 | vaddr addr, unsigned size, | |
565 | MMUAccessType access_type, | |
566 | int mmu_idx, MemTxAttrs attrs, | |
567 | MemTxResult response, uintptr_t retaddr); | |
dc5bd18f | 568 | char *riscv_isa_string(RISCVCPU *cpu); |
0442428a | 569 | void riscv_cpu_list(void); |
dc5bd18f | 570 | |
dc5bd18f MC |
571 | #define cpu_list riscv_cpu_list |
572 | #define cpu_mmu_index riscv_cpu_mmu_index | |
573 | ||
85ba724f | 574 | #ifndef CONFIG_USER_ONLY |
17b3c353 | 575 | bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); |
66e594f2 | 576 | void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); |
d028ac75 AP |
577 | int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); |
578 | uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value); | |
85ba724f | 579 | #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ |
e2f01f3c FC |
580 | void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), |
581 | void *arg); | |
69077dd6 AP |
582 | void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, |
583 | int (*rmw_fn)(void *arg, | |
584 | target_ulong reg, | |
585 | target_ulong *val, | |
586 | target_ulong new_val, | |
587 | target_ulong write_mask), | |
588 | void *rmw_fn_arg); | |
85ba724f | 589 | #endif |
fb738839 | 590 | void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); |
dc5bd18f MC |
591 | |
592 | void riscv_translate_init(void); | |
8905770b MAL |
593 | G_NORETURN void riscv_raise_exception(CPURISCVState *env, |
594 | uint32_t exception, uintptr_t pc); | |
dc5bd18f | 595 | |
fb738839 MC |
596 | target_ulong riscv_cpu_get_fflags(CPURISCVState *env); |
597 | void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); | |
dc5bd18f | 598 | |
c445593d AF |
599 | #define TB_FLAGS_PRIV_MMU_MASK 3 |
600 | #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) | |
83a71719 | 601 | #define TB_FLAGS_MSTATUS_FS MSTATUS_FS |
61b4b69d | 602 | #define TB_FLAGS_MSTATUS_VS MSTATUS_VS |
dc5bd18f | 603 | |
2b7168fc LZ |
604 | #include "exec/cpu-all.h" |
605 | ||
61d56494 | 606 | FIELD(TB_FLAGS, MEM_IDX, 0, 3) |
33f1beaf | 607 | FIELD(TB_FLAGS, LMUL, 3, 3) |
61d56494 | 608 | FIELD(TB_FLAGS, SEW, 6, 3) |
33f1beaf FC |
609 | /* Skip MSTATUS_VS (0x600) bits */ |
610 | FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) | |
611 | FIELD(TB_FLAGS, VILL, 12, 1) | |
612 | /* Skip MSTATUS_FS (0x6000) bits */ | |
743077b3 | 613 | /* Is a Hypervisor instruction load/store allowed? */ |
33f1beaf FC |
614 | FIELD(TB_FLAGS, HLSX, 15, 1) |
615 | FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) | |
616 | FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) | |
92371bd9 | 617 | /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ |
33f1beaf | 618 | FIELD(TB_FLAGS, XL, 20, 2) |
0774a7a1 | 619 | /* If PointerMasking should be applied */ |
4208dc7e LZ |
620 | FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1) |
621 | FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1) | |
f1eed927 | 622 | FIELD(TB_FLAGS, VTA, 24, 1) |
355d5584 | 623 | FIELD(TB_FLAGS, VMA, 25, 1) |
2b7168fc | 624 | |
db23e5d9 RH |
625 | #ifdef TARGET_RISCV32 |
626 | #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) | |
627 | #else | |
628 | static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) | |
629 | { | |
630 | return env->misa_mxl; | |
631 | } | |
632 | #endif | |
2b602398 | 633 | #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) |
51ae0cab | 634 | |
440544e1 LZ |
635 | #if defined(TARGET_RISCV32) |
636 | #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) | |
637 | #else | |
638 | static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) | |
639 | { | |
640 | RISCVMXL xl = env->misa_mxl; | |
641 | #if !defined(CONFIG_USER_ONLY) | |
642 | /* | |
643 | * When emulating a 32-bit-only cpu, use RV32. | |
644 | * When emulating a 64-bit cpu, and MXL has been reduced to RV32, | |
645 | * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened | |
646 | * back to RV64 for lower privs. | |
647 | */ | |
648 | if (xl != MXL_RV32) { | |
649 | switch (env->priv) { | |
650 | case PRV_M: | |
651 | break; | |
652 | case PRV_U: | |
653 | xl = get_field(env->mstatus, MSTATUS64_UXL); | |
654 | break; | |
655 | default: /* PRV_S | PRV_H */ | |
656 | xl = get_field(env->mstatus, MSTATUS64_SXL); | |
657 | break; | |
658 | } | |
659 | } | |
660 | #endif | |
661 | return xl; | |
662 | } | |
663 | #endif | |
664 | ||
31961cfe LZ |
665 | static inline int riscv_cpu_xlen(CPURISCVState *env) |
666 | { | |
667 | return 16 << env->xl; | |
668 | } | |
669 | ||
05e6ca5e GR |
670 | #ifdef TARGET_RISCV32 |
671 | #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) | |
672 | #else | |
673 | static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) | |
674 | { | |
675 | #ifdef CONFIG_USER_ONLY | |
676 | return env->misa_mxl; | |
677 | #else | |
678 | return get_field(env->mstatus, MSTATUS64_SXL); | |
679 | #endif | |
680 | } | |
681 | #endif | |
682 | ||
2b7168fc | 683 | /* |
a689a82b FC |
684 | * Encode LMUL to lmul as follows: |
685 | * LMUL vlmul lmul | |
686 | * 1 000 0 | |
687 | * 2 001 1 | |
688 | * 4 010 2 | |
689 | * 8 011 3 | |
690 | * - 100 - | |
691 | * 1/8 101 -3 | |
692 | * 1/4 110 -2 | |
693 | * 1/2 111 -1 | |
694 | * | |
695 | * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) | |
696 | * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 | |
697 | * => VLMAX = vlen >> (1 + 3 - (-3)) | |
698 | * = 256 >> 7 | |
699 | * = 2 | |
2b7168fc LZ |
700 | */ |
701 | static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) | |
702 | { | |
a689a82b FC |
703 | uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); |
704 | int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); | |
2b7168fc LZ |
705 | return cpu->cfg.vlen >> (sew + 3 - lmul); |
706 | } | |
707 | ||
53677acf RH |
708 | void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, |
709 | target_ulong *cs_base, uint32_t *pflags); | |
dc5bd18f | 710 | |
40bfa5f6 LZ |
711 | void riscv_cpu_update_mask(CPURISCVState *env); |
712 | ||
533c91e8 AF |
713 | RISCVException riscv_csrrw(CPURISCVState *env, int csrno, |
714 | target_ulong *ret_value, | |
715 | target_ulong new_value, target_ulong write_mask); | |
716 | RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, | |
717 | target_ulong *ret_value, | |
718 | target_ulong new_value, | |
719 | target_ulong write_mask); | |
c7b95171 | 720 | |
fb738839 MC |
721 | static inline void riscv_csr_write(CPURISCVState *env, int csrno, |
722 | target_ulong val) | |
c7b95171 MC |
723 | { |
724 | riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); | |
725 | } | |
726 | ||
fb738839 | 727 | static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) |
c7b95171 MC |
728 | { |
729 | target_ulong val = 0; | |
730 | riscv_csrrw(env, csrno, &val, 0, 0); | |
731 | return val; | |
732 | } | |
733 | ||
0e62f92e AF |
734 | typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, |
735 | int csrno); | |
605def6e AF |
736 | typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, |
737 | target_ulong *ret_value); | |
738 | typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, | |
739 | target_ulong new_value); | |
740 | typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, | |
741 | target_ulong *ret_value, | |
742 | target_ulong new_value, | |
743 | target_ulong write_mask); | |
c7b95171 | 744 | |
961738ff FP |
745 | RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, |
746 | Int128 *ret_value, | |
747 | Int128 new_value, Int128 write_mask); | |
748 | ||
457c360f FP |
749 | typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, |
750 | Int128 *ret_value); | |
751 | typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, | |
752 | Int128 new_value); | |
753 | ||
c7b95171 | 754 | typedef struct { |
8ceac5dc | 755 | const char *name; |
a88365c1 | 756 | riscv_csr_predicate_fn predicate; |
c7b95171 MC |
757 | riscv_csr_read_fn read; |
758 | riscv_csr_write_fn write; | |
759 | riscv_csr_op_fn op; | |
457c360f FP |
760 | riscv_csr_read128_fn read128; |
761 | riscv_csr_write128_fn write128; | |
a4b2fa43 AP |
762 | /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ |
763 | uint32_t min_priv_ver; | |
c7b95171 MC |
764 | } riscv_csr_operations; |
765 | ||
56118ee8 BM |
766 | /* CSR function table constants */ |
767 | enum { | |
768 | CSR_TABLE_SIZE = 0x1000 | |
769 | }; | |
770 | ||
14664483 AP |
771 | /** |
772 | * The event id are encoded based on the encoding specified in the | |
773 | * SBI specification v0.3 | |
774 | */ | |
775 | ||
776 | enum riscv_pmu_event_idx { | |
777 | RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01, | |
778 | RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02, | |
779 | RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019, | |
780 | RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B, | |
781 | RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021, | |
782 | }; | |
783 | ||
56118ee8 | 784 | /* CSR function table */ |
6f03770d | 785 | extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; |
56118ee8 | 786 | |
c7b95171 MC |
787 | void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); |
788 | void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); | |
dc5bd18f | 789 | |
5371f5cd JW |
790 | void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); |
791 | ||
dc5bd18f | 792 | #endif /* RISCV_CPU_H */ |