[mirror_qemu.git] / target / riscv / cpu.h

/*
 * QEMU RISC-V CPU
 *
 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
 * Copyright (c) 2017-2018 SiFive, Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2 or later, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef RISCV_CPU_H
#define RISCV_CPU_H

#include "hw/core/cpu.h"
#include "hw/registerfields.h"
#include "exec/cpu-defs.h"
#include "fpu/softfloat-types.h"
#include "qom/object.h"

#define TCG_GUEST_DEFAULT_MO 0

#define TYPE_RISCV_CPU "riscv-cpu"

#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU

#define TYPE_RISCV_CPU_ANY              RISCV_CPU_TYPE_NAME("any")
#define TYPE_RISCV_CPU_BASE32           RISCV_CPU_TYPE_NAME("rv32")
#define TYPE_RISCV_CPU_BASE64           RISCV_CPU_TYPE_NAME("rv64")
#define TYPE_RISCV_CPU_IBEX             RISCV_CPU_TYPE_NAME("lowrisc-ibex")
#define TYPE_RISCV_CPU_SHAKTI_C         RISCV_CPU_TYPE_NAME("shakti-c")
#define TYPE_RISCV_CPU_SIFIVE_E31       RISCV_CPU_TYPE_NAME("sifive-e31")
#define TYPE_RISCV_CPU_SIFIVE_E34       RISCV_CPU_TYPE_NAME("sifive-e34")
#define TYPE_RISCV_CPU_SIFIVE_E51       RISCV_CPU_TYPE_NAME("sifive-e51")
#define TYPE_RISCV_CPU_SIFIVE_U34       RISCV_CPU_TYPE_NAME("sifive-u34")
#define TYPE_RISCV_CPU_SIFIVE_U54       RISCV_CPU_TYPE_NAME("sifive-u54")

#if defined(TARGET_RISCV32)
# define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE32
#elif defined(TARGET_RISCV64)
# define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE64
#endif

#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))

#define RV(x) ((target_ulong)1 << (x - 'A'))

#define RVI RV('I')
#define RVE RV('E') /* E and I are mutually exclusive */
#define RVM RV('M')
#define RVA RV('A')
#define RVF RV('F')
#define RVD RV('D')
#define RVV RV('V')
#define RVC RV('C')
#define RVS RV('S')
#define RVU RV('U')
#define RVH RV('H')
#define RVB RV('B')

/* S extension denotes that Supervisor mode exists, however it is possible
   to have a core that support S mode but does not have an MMU and there
   is currently no bit in misa to indicate whether an MMU exists or not
   so a cpu features bitfield is required, likewise for optional PMP support */
enum {
    RISCV_FEATURE_MMU,
    RISCV_FEATURE_PMP,
    RISCV_FEATURE_EPMP,
    RISCV_FEATURE_MISA
};

#define PRIV_VERSION_1_10_0 0x00011000
#define PRIV_VERSION_1_11_0 0x00011100

#define BEXT_VERSION_0_93_0 0x00009300
#define VEXT_VERSION_0_07_1 0x00000701

enum {
    TRANSLATE_SUCCESS,
    TRANSLATE_FAIL,
    TRANSLATE_PMP_FAIL,
    TRANSLATE_G_STAGE_FAIL
};

#define MMU_USER_IDX 3

#define MAX_RISCV_PMPS (16)

typedef struct CPURISCVState CPURISCVState;

#if !defined(CONFIG_USER_ONLY)
#include "pmp.h"
#endif

#define RV_VLEN_MAX 256

FIELD(VTYPE, VLMUL, 0, 2)
FIELD(VTYPE, VSEW, 2, 3)
FIELD(VTYPE, VEDIV, 5, 2)
FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9)
FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)

struct CPURISCVState {
    target_ulong gpr[32];
    uint64_t fpr[32]; /* assume both F and D extensions */

    /* vector coprocessor state. */
    uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16);
    target_ulong vxrm;
    target_ulong vxsat;
    target_ulong vl;
    target_ulong vstart;
    target_ulong vtype;

    target_ulong pc;
    target_ulong load_res;
    target_ulong load_val;

    target_ulong frm;

    target_ulong badaddr;
    target_ulong guest_phys_fault_addr;

    target_ulong priv_ver;
    target_ulong bext_ver;
    target_ulong vext_ver;
    target_ulong misa;
    target_ulong misa_mask;

    uint32_t features;

#ifdef CONFIG_USER_ONLY
    uint32_t elf_flags;
#endif

#ifndef CONFIG_USER_ONLY
    target_ulong priv;
    /* This contains QEMU specific information about the virt state. */
    target_ulong virt;
    target_ulong resetvec;

    target_ulong mhartid;
    /*
     * For RV32 this is 32-bit mstatus and 32-bit mstatush.
     * For RV64 this is a 64-bit mstatus.
     */
    uint64_t mstatus;

    target_ulong mip;

    uint32_t miclaim;

    target_ulong mie;
    target_ulong mideleg;

    target_ulong satp;   /* since: priv-1.10.0 */
    target_ulong stval;
    target_ulong medeleg;

    target_ulong stvec;
    target_ulong sepc;
    target_ulong scause;

    target_ulong mtvec;
    target_ulong mepc;
    target_ulong mcause;
    target_ulong mtval;  /* since: priv-1.10.0 */

    /* Hypervisor CSRs */
    target_ulong hstatus;
    target_ulong hedeleg;
    target_ulong hideleg;
    target_ulong hcounteren;
    target_ulong htval;
    target_ulong htinst;
    target_ulong hgatp;
    uint64_t htimedelta;

    /* Virtual CSRs */
    /*
     * For RV32 this is 32-bit vsstatus and 32-bit vsstatush.
     * For RV64 this is a 64-bit vsstatus.
     */
    uint64_t vsstatus;
    target_ulong vstvec;
    target_ulong vsscratch;
    target_ulong vsepc;
    target_ulong vscause;
    target_ulong vstval;
    target_ulong vsatp;

    target_ulong mtval2;
    target_ulong mtinst;

    /* HS Backup CSRs */
    target_ulong stvec_hs;
    target_ulong sscratch_hs;
    target_ulong sepc_hs;
    target_ulong scause_hs;
    target_ulong stval_hs;
    target_ulong satp_hs;
    uint64_t mstatus_hs;

    /* Signals whether the current exception occurred with two-stage address
       translation active. */
    bool two_stage_lookup;

    target_ulong scounteren;
    target_ulong mcounteren;

    target_ulong sscratch;
    target_ulong mscratch;

    /* temporary htif regs */
    uint64_t mfromhost;
    uint64_t mtohost;
    uint64_t timecmp;

    /* physical memory protection */
    pmp_table_t pmp_state;
    target_ulong mseccfg;

    /* machine specific rdtime callback */
    uint64_t (*rdtime_fn)(uint32_t);
    uint32_t rdtime_fn_arg;

    /* True if in debugger mode.  */
    bool debugger;
#endif

    float_status fp_status;

    /* Fields from here on are preserved across CPU reset. */
    QEMUTimer *timer; /* Internal timer */
};

OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass,
                    RISCV_CPU)

/**
 * RISCVCPUClass:
 * @parent_realize: The parent class' realize handler.
 * @parent_reset: The parent class' reset handler.
 *
 * A RISCV CPU model.
 */
struct RISCVCPUClass {
    /*< private >*/
    CPUClass parent_class;
    /*< public >*/
    DeviceRealize parent_realize;
    DeviceReset parent_reset;
};

/**
 * RISCVCPU:
 * @env: #CPURISCVState
 *
 * A RISCV CPU.
 */
struct RISCVCPU {
    /*< private >*/
    CPUState parent_obj;
    /*< public >*/
    CPUNegativeOffsetState neg;
    CPURISCVState env;

    char *dyn_csr_xml;

    /* Configuration Settings */
    struct {
        bool ext_i;
        bool ext_e;
        bool ext_g;
        bool ext_m;
        bool ext_a;
        bool ext_f;
        bool ext_d;
        bool ext_c;
        bool ext_b;
        bool ext_s;
        bool ext_u;
        bool ext_h;
        bool ext_v;
        bool ext_counters;
        bool ext_ifencei;
        bool ext_icsr;

        char *priv_spec;
        char *user_spec;
        char *bext_spec;
        char *vext_spec;
        uint16_t vlen;
        uint16_t elen;
        bool mmu;
        bool pmp;
        bool epmp;
        uint64_t resetvec;
    } cfg;
};

static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
{
    return (env->misa & ext) != 0;
}

static inline bool riscv_feature(CPURISCVState *env, int feature)
{
    return env->features & (1ULL << feature);
}

#include "cpu_user.h"
#include "cpu_bits.h"

extern const char * const riscv_int_regnames[];
extern const char * const riscv_fpr_regnames[];

const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);
void riscv_cpu_do_interrupt(CPUState *cpu);
int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
                               int cpuid, void *opaque);
int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
                               int cpuid, void *opaque);
int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
bool riscv_cpu_fp_enabled(CPURISCVState *env);
bool riscv_cpu_virt_enabled(CPURISCVState *env);
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env);
void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable);
bool riscv_cpu_two_stage_lookup(int mmu_idx);
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
void  riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
                                    MMUAccessType access_type, int mmu_idx,
                                    uintptr_t retaddr);
bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                        MMUAccessType access_type, int mmu_idx,
                        bool probe, uintptr_t retaddr);
void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
                                     vaddr addr, unsigned size,
                                     MMUAccessType access_type,
                                     int mmu_idx, MemTxAttrs attrs,
                                     MemTxResult response, uintptr_t retaddr);
char *riscv_isa_string(RISCVCPU *cpu);
void riscv_cpu_list(void);

#define cpu_signal_handler riscv_cpu_signal_handler
#define cpu_list riscv_cpu_list
#define cpu_mmu_index riscv_cpu_mmu_index

#ifndef CONFIG_USER_ONLY
void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts);
uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
                             uint32_t arg);
#endif
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);

void riscv_translate_init(void);
int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
                                         uint32_t exception, uintptr_t pc);

target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);

#define TB_FLAGS_MMU_MASK   7
#define TB_FLAGS_PRIV_MMU_MASK                3
#define TB_FLAGS_PRIV_HYP_ACCESS_MASK   (1 << 2)
#define TB_FLAGS_MSTATUS_FS MSTATUS_FS

typedef CPURISCVState CPUArchState;
typedef RISCVCPU ArchCPU;
#include "exec/cpu-all.h"

FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1)
FIELD(TB_FLAGS, LMUL, 3, 2)
FIELD(TB_FLAGS, SEW, 5, 3)
FIELD(TB_FLAGS, VILL, 8, 1)
/* Is a Hypervisor instruction load/store allowed? */
FIELD(TB_FLAGS, HLSX, 9, 1)

bool riscv_cpu_is_32bit(CPURISCVState *env);

/*
 * A simplification for VLMAX
 * = (1 << LMUL) * VLEN / (8 * (1 << SEW))
 * = (VLEN << LMUL) / (8 << SEW)
 * = (VLEN << LMUL) >> (SEW + 3)
 * = VLEN >> (SEW + 3 - LMUL)
 */
static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
{
    uint8_t sew, lmul;

    sew = FIELD_EX64(vtype, VTYPE, VSEW);
    lmul = FIELD_EX64(vtype, VTYPE, VLMUL);
    return cpu->cfg.vlen >> (sew + 3 - lmul);
}

static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
                                        target_ulong *cs_base, uint32_t *pflags)
{
    uint32_t flags = 0;

    *pc = env->pc;
    *cs_base = 0;

    if (riscv_has_ext(env, RVV)) {
        uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);
        bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl);
        flags = FIELD_DP32(flags, TB_FLAGS, VILL,
                    FIELD_EX64(env->vtype, VTYPE, VILL));
        flags = FIELD_DP32(flags, TB_FLAGS, SEW,
                    FIELD_EX64(env->vtype, VTYPE, VSEW));
        flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
                    FIELD_EX64(env->vtype, VTYPE, VLMUL));
        flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
    } else {
        flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
    }

#ifdef CONFIG_USER_ONLY
    flags |= TB_FLAGS_MSTATUS_FS;
#else
    flags |= cpu_mmu_index(env, 0);
    if (riscv_cpu_fp_enabled(env)) {
        flags |= env->mstatus & MSTATUS_FS;
    }

    if (riscv_has_ext(env, RVH)) {
        if (env->priv == PRV_M ||
            (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
            (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
                get_field(env->hstatus, HSTATUS_HU))) {
            flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
        }
    }
#endif

    *pflags = flags;
}

RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
                           target_ulong *ret_value,
                           target_ulong new_value, target_ulong write_mask);
RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
                                 target_ulong *ret_value,
                                 target_ulong new_value,
                                 target_ulong write_mask);

static inline void riscv_csr_write(CPURISCVState *env, int csrno,
                                   target_ulong val)
{
    riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
}

static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
{
    target_ulong val = 0;
    riscv_csrrw(env, csrno, &val, 0, 0);
    return val;
}

typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env,
                                                 int csrno);
typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
                                            target_ulong *ret_value);
typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
                                             target_ulong new_value);
typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
                                          target_ulong *ret_value,
                                          target_ulong new_value,
                                          target_ulong write_mask);

typedef struct {
    const char *name;
    riscv_csr_predicate_fn predicate;
    riscv_csr_read_fn read;
    riscv_csr_write_fn write;
    riscv_csr_op_fn op;
} riscv_csr_operations;

/* CSR function table constants */
enum {
    CSR_TABLE_SIZE = 0x1000
};

/* CSR function table */
extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];

void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);

void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);

#endif /* RISCV_CPU_H */
Commit	Line	Data
dc5bd18f MC	1	/*
	2	* QEMU RISC-V CPU
	3	*
	4	* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
	5	* Copyright (c) 2017-2018 SiFive, Inc.
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms and conditions of the GNU General Public License,
	9	* version 2 or later, as published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope it will be useful, but WITHOUT
	12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	* more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along with
	17	* this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#ifndef RISCV_CPU_H
	21	#define RISCV_CPU_H
	22
2e5b09fd	23	#include "hw/core/cpu.h"
2b7168fc	24	#include "hw/registerfields.h"
dc5bd18f	25	#include "exec/cpu-defs.h"
135b03cb	26	#include "fpu/softfloat-types.h"
db1015e9	27	#include "qom/object.h"
dc5bd18f	28
74433bf0 RH	29	#define TCG_GUEST_DEFAULT_MO 0
74433bf0 RH	30
dc5bd18f MC	31	#define TYPE_RISCV_CPU "riscv-cpu"
	32
	33	#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
	34	#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
0dacec87	35	#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
dc5bd18f MC	36
dc5bd18f MC	37	#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
8903bf6e AF	38	#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
8903bf6e AF	39	#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
36b80ad9	40	#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
6ddc7069	41	#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
dc5bd18f	42	#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
d784733b	43	#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
dc5bd18f MC	44	#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
	45	#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
	46	#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
	47
c0a635f3 AF	48	#if defined(TARGET_RISCV32)
	49	# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32
	50	#elif defined(TARGET_RISCV64)
	51	# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64
	52	#endif
	53
dc5bd18f MC	54	#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
	55	#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
	56
dc5bd18f MC	57	#define RV(x) ((target_ulong)1 << (x - 'A'))
	58
	59	#define RVI RV('I')
79f86934	60	#define RVE RV('E') /* E and I are mutually exclusive */
dc5bd18f MC	61	#define RVM RV('M')
	62	#define RVA RV('A')
	63	#define RVF RV('F')
	64	#define RVD RV('D')
ad9e5aa2	65	#define RVV RV('V')
dc5bd18f MC	66	#define RVC RV('C')
	67	#define RVS RV('S')
	68	#define RVU RV('U')
af1fa003	69	#define RVH RV('H')
43824018	70	#define RVB RV('B')
dc5bd18f MC	71
	72	/* S extension denotes that Supervisor mode exists, however it is possible
	73	to have a core that support S mode but does not have an MMU and there
	74	is currently no bit in misa to indicate whether an MMU exists or not
a88365c1	75	so a cpu features bitfield is required, likewise for optional PMP support */
dc5bd18f	76	enum {
a88365c1	77	RISCV_FEATURE_MMU,
f18637cd	78	RISCV_FEATURE_PMP,
4a345b2a	79	RISCV_FEATURE_EPMP,
f18637cd	80	RISCV_FEATURE_MISA
dc5bd18f MC	81	};
dc5bd18f MC	82
dc5bd18f	83	#define PRIV_VERSION_1_10_0 0x00011000
6729dbbd	84	#define PRIV_VERSION_1_11_0 0x00011100
dc5bd18f	85
d2c1a177	86	#define BEXT_VERSION_0_93_0 0x00009300
32931383 LZ	87	#define VEXT_VERSION_0_07_1 0x00000701
32931383 LZ	88
33a9a57d YJ	89	enum {
	90	TRANSLATE_SUCCESS,
	91	TRANSLATE_FAIL,
	92	TRANSLATE_PMP_FAIL,
	93	TRANSLATE_G_STAGE_FAIL
	94	};
	95
dc5bd18f MC	96	#define MMU_USER_IDX 3
	97
	98	#define MAX_RISCV_PMPS (16)
	99
	100	typedef struct CPURISCVState CPURISCVState;
	101
bbf3d1b4	102	#if !defined(CONFIG_USER_ONLY)
dc5bd18f	103	#include "pmp.h"
bbf3d1b4	104	#endif
dc5bd18f	105
6bf91617	106	#define RV_VLEN_MAX 256
ad9e5aa2	107
2b7168fc LZ	108	FIELD(VTYPE, VLMUL, 0, 2)
	109	FIELD(VTYPE, VSEW, 2, 3)
	110	FIELD(VTYPE, VEDIV, 5, 2)
	111	FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9)
fbcbafa2	112	FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
2b7168fc	113
dc5bd18f MC	114	struct CPURISCVState {
	115	target_ulong gpr[32];
	116	uint64_t fpr[32]; /* assume both F and D extensions */
ad9e5aa2 LZ	117
	118	/* vector coprocessor state. */
	119	uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16);
	120	target_ulong vxrm;
	121	target_ulong vxsat;
	122	target_ulong vl;
	123	target_ulong vstart;
	124	target_ulong vtype;
	125
dc5bd18f MC	126	target_ulong pc;
	127	target_ulong load_res;
	128	target_ulong load_val;
	129
	130	target_ulong frm;
	131
	132	target_ulong badaddr;
36a18664	133	target_ulong guest_phys_fault_addr;
dc5bd18f	134
dc5bd18f	135	target_ulong priv_ver;
d2c1a177	136	target_ulong bext_ver;
32931383	137	target_ulong vext_ver;
dc5bd18f	138	target_ulong misa;
f18637cd	139	target_ulong misa_mask;
dc5bd18f MC	140
	141	uint32_t features;
	142
5836c3ec KC	143	#ifdef CONFIG_USER_ONLY
	144	uint32_t elf_flags;
	145	#endif
	146
dc5bd18f MC	147	#ifndef CONFIG_USER_ONLY
dc5bd18f MC	148	target_ulong priv;
ef6bb7b6 AF	149	/* This contains QEMU specific information about the virt state. */
ef6bb7b6 AF	150	target_ulong virt;
dc5bd18f MC	151	target_ulong resetvec;
	152
	153	target_ulong mhartid;
284d697c YJ	154	/*
	155	* For RV32 this is 32-bit mstatus and 32-bit mstatush.
	156	* For RV64 this is a 64-bit mstatus.
	157	*/
	158	uint64_t mstatus;
85ba724f	159
02861613	160	target_ulong mip;
66e594f2	161
e3e7039c	162	uint32_t miclaim;
85ba724f	163
dc5bd18f MC	164	target_ulong mie;
	165	target_ulong mideleg;
	166
dc5bd18f	167	target_ulong satp; /* since: priv-1.10.0 */
ac12b601	168	target_ulong stval;
dc5bd18f MC	169	target_ulong medeleg;
	170
	171	target_ulong stvec;
	172	target_ulong sepc;
	173	target_ulong scause;
	174
	175	target_ulong mtvec;
	176	target_ulong mepc;
	177	target_ulong mcause;
	178	target_ulong mtval; /* since: priv-1.10.0 */
	179
bd023ce3 AF	180	/* Hypervisor CSRs */
	181	target_ulong hstatus;
	182	target_ulong hedeleg;
	183	target_ulong hideleg;
	184	target_ulong hcounteren;
	185	target_ulong htval;
	186	target_ulong htinst;
	187	target_ulong hgatp;
c6957248	188	uint64_t htimedelta;
bd023ce3 AF	189
bd023ce3 AF	190	/* Virtual CSRs */
284d697c YJ	191	/*
	192	* For RV32 this is 32-bit vsstatus and 32-bit vsstatush.
	193	* For RV64 this is a 64-bit vsstatus.
	194	*/
	195	uint64_t vsstatus;
bd023ce3 AF	196	target_ulong vstvec;
	197	target_ulong vsscratch;
	198	target_ulong vsepc;
	199	target_ulong vscause;
	200	target_ulong vstval;
	201	target_ulong vsatp;
	202
	203	target_ulong mtval2;
	204	target_ulong mtinst;
	205
66e594f2 AF	206	/* HS Backup CSRs */
	207	target_ulong stvec_hs;
	208	target_ulong sscratch_hs;
	209	target_ulong sepc_hs;
	210	target_ulong scause_hs;
	211	target_ulong stval_hs;
	212	target_ulong satp_hs;
284d697c	213	uint64_t mstatus_hs;
66e594f2	214
ec352d0c GK	215	/* Signals whether the current exception occurred with two-stage address
	216	translation active. */
	217	bool two_stage_lookup;
	218
8c59f5c1 MC	219	target_ulong scounteren;
8c59f5c1 MC	220	target_ulong mcounteren;
dc5bd18f MC	221
	222	target_ulong sscratch;
	223	target_ulong mscratch;
	224
	225	/* temporary htif regs */
	226	uint64_t mfromhost;
	227	uint64_t mtohost;
	228	uint64_t timecmp;
	229
	230	/* physical memory protection */
	231	pmp_table_t pmp_state;
2582a95c	232	target_ulong mseccfg;
753e3fe2	233
c6957248	234	/* machine specific rdtime callback */
a47ef6e9 BM	235	uint64_t (*rdtime_fn)(uint32_t);
a47ef6e9 BM	236	uint32_t rdtime_fn_arg;
c6957248	237
753e3fe2 JW	238	/* True if in debugger mode. */
753e3fe2 JW	239	bool debugger;
dc5bd18f MC	240	#endif
	241
	242	float_status fp_status;
	243
dc5bd18f MC	244	/* Fields from here on are preserved across CPU reset. */
	245	QEMUTimer timer; / Internal timer */
	246	};
	247
c821774a	248	OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass,
30b5707c	249	RISCV_CPU)
dc5bd18f MC	250
	251	/**
	252	* RISCVCPUClass:
	253	* @parent_realize: The parent class' realize handler.
	254	* @parent_reset: The parent class' reset handler.
	255	*
	256	* A RISCV CPU model.
	257	*/
db1015e9	258	struct RISCVCPUClass {
dc5bd18f MC	259	/< private >/
	260	CPUClass parent_class;
	261	/< public >/
	262	DeviceRealize parent_realize;
781c67ca	263	DeviceReset parent_reset;
db1015e9	264	};
dc5bd18f MC	265
	266	/**
	267	* RISCVCPU:
	268	* @env: #CPURISCVState
	269	*
	270	* A RISCV CPU.
	271	*/
db1015e9	272	struct RISCVCPU {
dc5bd18f MC	273	/< private >/
	274	CPUState parent_obj;
	275	/< public >/
5b146dc7	276	CPUNegativeOffsetState neg;
dc5bd18f	277	CPURISCVState env;
c4e95030	278
b93777e1 BM	279	char *dyn_csr_xml;
b93777e1 BM	280
c4e95030 AF	281	/* Configuration Settings */
c4e95030 AF	282	struct {
b55d7d34 AF	283	bool ext_i;
	284	bool ext_e;
	285	bool ext_g;
	286	bool ext_m;
	287	bool ext_a;
	288	bool ext_f;
	289	bool ext_d;
	290	bool ext_c;
d52e9408	291	bool ext_b;
b55d7d34 AF	292	bool ext_s;
b55d7d34 AF	293	bool ext_u;
c9eefe05	294	bool ext_h;
6bf91617	295	bool ext_v;
0a13a5b8	296	bool ext_counters;
50fba816	297	bool ext_ifencei;
591bddea	298	bool ext_icsr;
b55d7d34	299
c4e95030 AF	300	char *priv_spec;
c4e95030 AF	301	char *user_spec;
d2c1a177	302	char *bext_spec;
6bf91617	303	char *vext_spec;
32931383 LZ	304	uint16_t vlen;
32931383 LZ	305	uint16_t elen;
c4e95030 AF	306	bool mmu;
c4e95030 AF	307	bool pmp;
5da9514e	308	bool epmp;
9b4c9b2b	309	uint64_t resetvec;
c4e95030	310	} cfg;
db1015e9	311	};
dc5bd18f	312
dc5bd18f MC	313	static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
	314	{
	315	return (env->misa & ext) != 0;
	316	}
	317
	318	static inline bool riscv_feature(CPURISCVState *env, int feature)
	319	{
	320	return env->features & (1ULL << feature);
	321	}
	322
	323	#include "cpu_user.h"
	324	#include "cpu_bits.h"
	325
	326	extern const char * const riscv_int_regnames[];
	327	extern const char * const riscv_fpr_regnames[];
dc5bd18f	328
c51a3f5d	329	const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);
dc5bd18f	330	void riscv_cpu_do_interrupt(CPUState *cpu);
43a96588 YJ	331	int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
	332	int cpuid, void *opaque);
	333	int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
	334	int cpuid, void *opaque);
a010bdbe	335	int riscv_cpu_gdb_read_register(CPUState cpu, GByteArray buf, int reg);
dc5bd18f MC	336	int riscv_cpu_gdb_write_register(CPUState cpu, uint8_t buf, int reg);
dc5bd18f MC	337	bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
b345b480	338	bool riscv_cpu_fp_enabled(CPURISCVState *env);
ef6bb7b6 AF	339	bool riscv_cpu_virt_enabled(CPURISCVState *env);
ef6bb7b6 AF	340	void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
c7b1bbc8 AF	341	bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env);
c7b1bbc8 AF	342	void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable);
1c1c060a	343	bool riscv_cpu_two_stage_lookup(int mmu_idx);
dc5bd18f MC	344	int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
	345	hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
	346	void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
	347	MMUAccessType access_type, int mmu_idx,
	348	uintptr_t retaddr);
8a4ca3c1 RH	349	bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
	350	MMUAccessType access_type, int mmu_idx,
	351	bool probe, uintptr_t retaddr);
37207e12 PD	352	void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
	353	vaddr addr, unsigned size,
	354	MMUAccessType access_type,
	355	int mmu_idx, MemTxAttrs attrs,
	356	MemTxResult response, uintptr_t retaddr);
dc5bd18f	357	char riscv_isa_string(RISCVCPU cpu);
0442428a	358	void riscv_cpu_list(void);
dc5bd18f	359
fb738839	360	#define cpu_signal_handler riscv_cpu_signal_handler
dc5bd18f MC	361	#define cpu_list riscv_cpu_list
	362	#define cpu_mmu_index riscv_cpu_mmu_index
	363
85ba724f	364	#ifndef CONFIG_USER_ONLY
66e594f2	365	void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
e3e7039c	366	int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts);
85ba724f MC	367	uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
85ba724f MC	368	#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
a47ef6e9 BM	369	void riscv_cpu_set_rdtime_fn(CPURISCVState env, uint64_t (fn)(uint32_t),
a47ef6e9 BM	370	uint32_t arg);
85ba724f	371	#endif
fb738839	372	void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
dc5bd18f MC	373
dc5bd18f MC	374	void riscv_translate_init(void);
fb738839 MC	375	int riscv_cpu_signal_handler(int host_signum, void pinfo, void puc);
	376	void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
	377	uint32_t exception, uintptr_t pc);
dc5bd18f	378
fb738839 MC	379	target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
fb738839 MC	380	void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
dc5bd18f	381
c445593d AF	382	#define TB_FLAGS_MMU_MASK 7
	383	#define TB_FLAGS_PRIV_MMU_MASK 3
	384	#define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2)
83a71719	385	#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
dc5bd18f	386
2b7168fc LZ	387	typedef CPURISCVState CPUArchState;
	388	typedef RISCVCPU ArchCPU;
	389	#include "exec/cpu-all.h"
	390
	391	FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1)
	392	FIELD(TB_FLAGS, LMUL, 3, 2)
	393	FIELD(TB_FLAGS, SEW, 5, 3)
	394	FIELD(TB_FLAGS, VILL, 8, 1)
743077b3 AF	395	/* Is a Hypervisor instruction load/store allowed? */
743077b3 AF	396	FIELD(TB_FLAGS, HLSX, 9, 1)
2b7168fc	397
51ae0cab AF	398	bool riscv_cpu_is_32bit(CPURISCVState *env);
51ae0cab AF	399
2b7168fc LZ	400	/*
	401	* A simplification for VLMAX
	402	* = (1 << LMUL) * VLEN / (8 * (1 << SEW))
	403	* = (VLEN << LMUL) / (8 << SEW)
	404	* = (VLEN << LMUL) >> (SEW + 3)
	405	* = VLEN >> (SEW + 3 - LMUL)
	406	*/
	407	static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
	408	{
	409	uint8_t sew, lmul;
	410
	411	sew = FIELD_EX64(vtype, VTYPE, VSEW);
	412	lmul = FIELD_EX64(vtype, VTYPE, VLMUL);
	413	return cpu->cfg.vlen >> (sew + 3 - lmul);
	414	}
	415
dc5bd18f	416	static inline void cpu_get_tb_cpu_state(CPURISCVState env, target_ulong pc,
2b7168fc	417	target_ulong cs_base, uint32_t pflags)
dc5bd18f	418	{
2b7168fc LZ	419	uint32_t flags = 0;
2b7168fc LZ	420
dc5bd18f MC	421	*pc = env->pc;
dc5bd18f MC	422	*cs_base = 0;
2b7168fc LZ	423
	424	if (riscv_has_ext(env, RVV)) {
	425	uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);
	426	bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl);
	427	flags = FIELD_DP32(flags, TB_FLAGS, VILL,
	428	FIELD_EX64(env->vtype, VTYPE, VILL));
	429	flags = FIELD_DP32(flags, TB_FLAGS, SEW,
	430	FIELD_EX64(env->vtype, VTYPE, VSEW));
	431	flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
	432	FIELD_EX64(env->vtype, VTYPE, VLMUL));
	433	flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
	434	} else {
	435	flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
	436	}
	437
dc5bd18f	438	#ifdef CONFIG_USER_ONLY
2b7168fc	439	flags \|= TB_FLAGS_MSTATUS_FS;
dc5bd18f	440	#else
2b7168fc	441	flags \|= cpu_mmu_index(env, 0);
e28eaed8	442	if (riscv_cpu_fp_enabled(env)) {
2b7168fc	443	flags \|= env->mstatus & MSTATUS_FS;
e28eaed8	444	}
743077b3 AF	445
	446	if (riscv_has_ext(env, RVH)) {
	447	if (env->priv == PRV_M \|\|
	448	(env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) \|\|
	449	(env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
	450	get_field(env->hstatus, HSTATUS_HU))) {
	451	flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
	452	}
	453	}
dc5bd18f	454	#endif
743077b3	455
2b7168fc	456	*pflags = flags;
dc5bd18f MC	457	}
dc5bd18f MC	458
533c91e8 AF	459	RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
	460	target_ulong *ret_value,
	461	target_ulong new_value, target_ulong write_mask);
	462	RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
	463	target_ulong *ret_value,
	464	target_ulong new_value,
	465	target_ulong write_mask);
c7b95171	466
fb738839 MC	467	static inline void riscv_csr_write(CPURISCVState *env, int csrno,
fb738839 MC	468	target_ulong val)
c7b95171 MC	469	{
	470	riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
	471	}
	472
fb738839	473	static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
c7b95171 MC	474	{
	475	target_ulong val = 0;
	476	riscv_csrrw(env, csrno, &val, 0, 0);
	477	return val;
	478	}
	479
0e62f92e AF	480	typedef RISCVException (riscv_csr_predicate_fn)(CPURISCVState env,
0e62f92e AF	481	int csrno);
605def6e AF	482	typedef RISCVException (riscv_csr_read_fn)(CPURISCVState env, int csrno,
	483	target_ulong *ret_value);
	484	typedef RISCVException (riscv_csr_write_fn)(CPURISCVState env, int csrno,
	485	target_ulong new_value);
	486	typedef RISCVException (riscv_csr_op_fn)(CPURISCVState env, int csrno,
	487	target_ulong *ret_value,
	488	target_ulong new_value,
	489	target_ulong write_mask);
c7b95171 MC	490
c7b95171 MC	491	typedef struct {
8ceac5dc	492	const char *name;
a88365c1	493	riscv_csr_predicate_fn predicate;
c7b95171 MC	494	riscv_csr_read_fn read;
	495	riscv_csr_write_fn write;
	496	riscv_csr_op_fn op;
	497	} riscv_csr_operations;
	498
56118ee8 BM	499	/* CSR function table constants */
	500	enum {
	501	CSR_TABLE_SIZE = 0x1000
	502	};
	503
	504	/* CSR function table */
6f03770d	505	extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
56118ee8	506
c7b95171 MC	507	void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
c7b95171 MC	508	void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
dc5bd18f	509
5371f5cd JW	510	void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
5371f5cd JW	511
dc5bd18f	512	#endif /* RISCV_CPU_H */