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Commit | Line | Data |
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dc5bd18f MC |
1 | /* RISC-V ISA constants */ |
2 | ||
f91005e1 MA |
3 | #ifndef TARGET_RISCV_CPU_BITS_H |
4 | #define TARGET_RISCV_CPU_BITS_H | |
5 | ||
dc5bd18f MC |
6 | #define get_field(reg, mask) (((reg) & \ |
7 | (target_ulong)(mask)) / ((mask) & ~((mask) << 1))) | |
8 | #define set_field(reg, mask, val) (((reg) & ~(target_ulong)(mask)) | \ | |
9 | (((target_ulong)(val) * ((mask) & ~((mask) << 1))) & \ | |
10 | (target_ulong)(mask))) | |
11 | ||
426f0348 MC |
12 | /* Floating point round mode */ |
13 | #define FSR_RD_SHIFT 5 | |
14 | #define FSR_RD (0x7 << FSR_RD_SHIFT) | |
15 | ||
16 | /* Floating point accrued exception flags */ | |
17 | #define FPEXC_NX 0x01 | |
18 | #define FPEXC_UF 0x02 | |
19 | #define FPEXC_OF 0x04 | |
20 | #define FPEXC_DZ 0x08 | |
21 | #define FPEXC_NV 0x10 | |
22 | ||
23 | /* Floating point status register bits */ | |
24 | #define FSR_AEXC_SHIFT 0 | |
25 | #define FSR_NVA (FPEXC_NV << FSR_AEXC_SHIFT) | |
26 | #define FSR_OFA (FPEXC_OF << FSR_AEXC_SHIFT) | |
27 | #define FSR_UFA (FPEXC_UF << FSR_AEXC_SHIFT) | |
28 | #define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT) | |
29 | #define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT) | |
30 | #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) | |
31 | ||
8e3a1f18 LZ |
32 | /* Vector Fixed-Point round model */ |
33 | #define FSR_VXRM_SHIFT 9 | |
34 | #define FSR_VXRM (0x3 << FSR_VXRM_SHIFT) | |
35 | ||
36 | /* Vector Fixed-Point saturation flag */ | |
37 | #define FSR_VXSAT_SHIFT 8 | |
38 | #define FSR_VXSAT (0x1 << FSR_VXSAT_SHIFT) | |
39 | ||
426f0348 MC |
40 | /* Control and Status Registers */ |
41 | ||
42 | /* User Trap Setup */ | |
43 | #define CSR_USTATUS 0x000 | |
44 | #define CSR_UIE 0x004 | |
45 | #define CSR_UTVEC 0x005 | |
46 | ||
47 | /* User Trap Handling */ | |
48 | #define CSR_USCRATCH 0x040 | |
49 | #define CSR_UEPC 0x041 | |
50 | #define CSR_UCAUSE 0x042 | |
51 | #define CSR_UTVAL 0x043 | |
52 | #define CSR_UIP 0x044 | |
53 | ||
54 | /* User Floating-Point CSRs */ | |
55 | #define CSR_FFLAGS 0x001 | |
56 | #define CSR_FRM 0x002 | |
57 | #define CSR_FCSR 0x003 | |
58 | ||
8e3a1f18 LZ |
59 | /* User Vector CSRs */ |
60 | #define CSR_VSTART 0x008 | |
61 | #define CSR_VXSAT 0x009 | |
62 | #define CSR_VXRM 0x00a | |
63 | #define CSR_VL 0xc20 | |
64 | #define CSR_VTYPE 0xc21 | |
65 | ||
426f0348 MC |
66 | /* User Timers and Counters */ |
67 | #define CSR_CYCLE 0xc00 | |
68 | #define CSR_TIME 0xc01 | |
69 | #define CSR_INSTRET 0xc02 | |
70 | #define CSR_HPMCOUNTER3 0xc03 | |
71 | #define CSR_HPMCOUNTER4 0xc04 | |
72 | #define CSR_HPMCOUNTER5 0xc05 | |
73 | #define CSR_HPMCOUNTER6 0xc06 | |
74 | #define CSR_HPMCOUNTER7 0xc07 | |
75 | #define CSR_HPMCOUNTER8 0xc08 | |
76 | #define CSR_HPMCOUNTER9 0xc09 | |
77 | #define CSR_HPMCOUNTER10 0xc0a | |
78 | #define CSR_HPMCOUNTER11 0xc0b | |
79 | #define CSR_HPMCOUNTER12 0xc0c | |
80 | #define CSR_HPMCOUNTER13 0xc0d | |
81 | #define CSR_HPMCOUNTER14 0xc0e | |
82 | #define CSR_HPMCOUNTER15 0xc0f | |
83 | #define CSR_HPMCOUNTER16 0xc10 | |
84 | #define CSR_HPMCOUNTER17 0xc11 | |
85 | #define CSR_HPMCOUNTER18 0xc12 | |
86 | #define CSR_HPMCOUNTER19 0xc13 | |
87 | #define CSR_HPMCOUNTER20 0xc14 | |
88 | #define CSR_HPMCOUNTER21 0xc15 | |
89 | #define CSR_HPMCOUNTER22 0xc16 | |
90 | #define CSR_HPMCOUNTER23 0xc17 | |
91 | #define CSR_HPMCOUNTER24 0xc18 | |
92 | #define CSR_HPMCOUNTER25 0xc19 | |
93 | #define CSR_HPMCOUNTER26 0xc1a | |
94 | #define CSR_HPMCOUNTER27 0xc1b | |
95 | #define CSR_HPMCOUNTER28 0xc1c | |
96 | #define CSR_HPMCOUNTER29 0xc1d | |
97 | #define CSR_HPMCOUNTER30 0xc1e | |
98 | #define CSR_HPMCOUNTER31 0xc1f | |
99 | #define CSR_CYCLEH 0xc80 | |
100 | #define CSR_TIMEH 0xc81 | |
101 | #define CSR_INSTRETH 0xc82 | |
102 | #define CSR_HPMCOUNTER3H 0xc83 | |
103 | #define CSR_HPMCOUNTER4H 0xc84 | |
104 | #define CSR_HPMCOUNTER5H 0xc85 | |
105 | #define CSR_HPMCOUNTER6H 0xc86 | |
106 | #define CSR_HPMCOUNTER7H 0xc87 | |
107 | #define CSR_HPMCOUNTER8H 0xc88 | |
108 | #define CSR_HPMCOUNTER9H 0xc89 | |
109 | #define CSR_HPMCOUNTER10H 0xc8a | |
110 | #define CSR_HPMCOUNTER11H 0xc8b | |
111 | #define CSR_HPMCOUNTER12H 0xc8c | |
112 | #define CSR_HPMCOUNTER13H 0xc8d | |
113 | #define CSR_HPMCOUNTER14H 0xc8e | |
114 | #define CSR_HPMCOUNTER15H 0xc8f | |
115 | #define CSR_HPMCOUNTER16H 0xc90 | |
116 | #define CSR_HPMCOUNTER17H 0xc91 | |
117 | #define CSR_HPMCOUNTER18H 0xc92 | |
118 | #define CSR_HPMCOUNTER19H 0xc93 | |
119 | #define CSR_HPMCOUNTER20H 0xc94 | |
120 | #define CSR_HPMCOUNTER21H 0xc95 | |
121 | #define CSR_HPMCOUNTER22H 0xc96 | |
122 | #define CSR_HPMCOUNTER23H 0xc97 | |
123 | #define CSR_HPMCOUNTER24H 0xc98 | |
124 | #define CSR_HPMCOUNTER25H 0xc99 | |
125 | #define CSR_HPMCOUNTER26H 0xc9a | |
126 | #define CSR_HPMCOUNTER27H 0xc9b | |
127 | #define CSR_HPMCOUNTER28H 0xc9c | |
128 | #define CSR_HPMCOUNTER29H 0xc9d | |
129 | #define CSR_HPMCOUNTER30H 0xc9e | |
130 | #define CSR_HPMCOUNTER31H 0xc9f | |
131 | ||
132 | /* Machine Timers and Counters */ | |
133 | #define CSR_MCYCLE 0xb00 | |
134 | #define CSR_MINSTRET 0xb02 | |
135 | #define CSR_MCYCLEH 0xb80 | |
136 | #define CSR_MINSTRETH 0xb82 | |
137 | ||
138 | /* Machine Information Registers */ | |
139 | #define CSR_MVENDORID 0xf11 | |
140 | #define CSR_MARCHID 0xf12 | |
141 | #define CSR_MIMPID 0xf13 | |
142 | #define CSR_MHARTID 0xf14 | |
143 | ||
144 | /* Machine Trap Setup */ | |
145 | #define CSR_MSTATUS 0x300 | |
146 | #define CSR_MISA 0x301 | |
147 | #define CSR_MEDELEG 0x302 | |
148 | #define CSR_MIDELEG 0x303 | |
149 | #define CSR_MIE 0x304 | |
150 | #define CSR_MTVEC 0x305 | |
151 | #define CSR_MCOUNTEREN 0x306 | |
152 | ||
551fa7e8 AF |
153 | /* 32-bit only */ |
154 | #define CSR_MSTATUSH 0x310 | |
155 | ||
426f0348 | 156 | /* Legacy Counter Setup (priv v1.9.1) */ |
747a43e8 | 157 | /* Update to #define CSR_MCOUNTINHIBIT 0x320 for 1.11.0 */ |
426f0348 MC |
158 | #define CSR_MUCOUNTEREN 0x320 |
159 | #define CSR_MSCOUNTEREN 0x321 | |
8e73df6a | 160 | #define CSR_MHCOUNTEREN 0x322 |
426f0348 MC |
161 | |
162 | /* Machine Trap Handling */ | |
163 | #define CSR_MSCRATCH 0x340 | |
164 | #define CSR_MEPC 0x341 | |
165 | #define CSR_MCAUSE 0x342 | |
8e73df6a | 166 | #define CSR_MTVAL 0x343 |
426f0348 MC |
167 | #define CSR_MIP 0x344 |
168 | ||
8e73df6a JW |
169 | /* Legacy Machine Trap Handling (priv v1.9.1) */ |
170 | #define CSR_MBADADDR 0x343 | |
171 | ||
426f0348 MC |
172 | /* Supervisor Trap Setup */ |
173 | #define CSR_SSTATUS 0x100 | |
8e73df6a JW |
174 | #define CSR_SEDELEG 0x102 |
175 | #define CSR_SIDELEG 0x103 | |
426f0348 MC |
176 | #define CSR_SIE 0x104 |
177 | #define CSR_STVEC 0x105 | |
178 | #define CSR_SCOUNTEREN 0x106 | |
179 | ||
180 | /* Supervisor Trap Handling */ | |
181 | #define CSR_SSCRATCH 0x140 | |
182 | #define CSR_SEPC 0x141 | |
183 | #define CSR_SCAUSE 0x142 | |
8e73df6a | 184 | #define CSR_STVAL 0x143 |
426f0348 MC |
185 | #define CSR_SIP 0x144 |
186 | ||
8e73df6a JW |
187 | /* Legacy Supervisor Trap Handling (priv v1.9.1) */ |
188 | #define CSR_SBADADDR 0x143 | |
189 | ||
426f0348 MC |
190 | /* Supervisor Protection and Translation */ |
191 | #define CSR_SPTBR 0x180 | |
192 | #define CSR_SATP 0x180 | |
193 | ||
7f8dcfeb AF |
194 | /* Hpervisor CSRs */ |
195 | #define CSR_HSTATUS 0x600 | |
196 | #define CSR_HEDELEG 0x602 | |
197 | #define CSR_HIDELEG 0x603 | |
bd023ce3 AF |
198 | #define CSR_HIE 0x604 |
199 | #define CSR_HCOUNTEREN 0x606 | |
200 | #define CSR_HTVAL 0x643 | |
201 | #define CSR_HIP 0x644 | |
202 | #define CSR_HTINST 0x64A | |
7f8dcfeb | 203 | #define CSR_HGATP 0x680 |
bd023ce3 AF |
204 | #define CSR_HTIMEDELTA 0x605 |
205 | #define CSR_HTIMEDELTAH 0x615 | |
7f8dcfeb AF |
206 | |
207 | #if defined(TARGET_RISCV32) | |
208 | #define HGATP_MODE SATP32_MODE | |
209 | #define HGATP_VMID SATP32_ASID | |
210 | #define HGATP_PPN SATP32_PPN | |
211 | #endif | |
212 | #if defined(TARGET_RISCV64) | |
213 | #define HGATP_MODE SATP64_MODE | |
214 | #define HGATP_VMID SATP64_ASID | |
215 | #define HGATP_PPN SATP64_PPN | |
216 | #endif | |
217 | ||
bd023ce3 AF |
218 | /* Virtual CSRs */ |
219 | #define CSR_VSSTATUS 0x200 | |
220 | #define CSR_VSIE 0x204 | |
221 | #define CSR_VSTVEC 0x205 | |
222 | #define CSR_VSSCRATCH 0x240 | |
223 | #define CSR_VSEPC 0x241 | |
224 | #define CSR_VSCAUSE 0x242 | |
225 | #define CSR_VSTVAL 0x243 | |
226 | #define CSR_VSIP 0x244 | |
227 | #define CSR_VSATP 0x280 | |
228 | ||
229 | #define CSR_MTINST 0x34a | |
230 | #define CSR_MTVAL2 0x34b | |
231 | ||
426f0348 MC |
232 | /* Physical Memory Protection */ |
233 | #define CSR_PMPCFG0 0x3a0 | |
234 | #define CSR_PMPCFG1 0x3a1 | |
235 | #define CSR_PMPCFG2 0x3a2 | |
236 | #define CSR_PMPCFG3 0x3a3 | |
237 | #define CSR_PMPADDR0 0x3b0 | |
238 | #define CSR_PMPADDR1 0x3b1 | |
239 | #define CSR_PMPADDR2 0x3b2 | |
240 | #define CSR_PMPADDR3 0x3b3 | |
241 | #define CSR_PMPADDR4 0x3b4 | |
242 | #define CSR_PMPADDR5 0x3b5 | |
243 | #define CSR_PMPADDR6 0x3b6 | |
244 | #define CSR_PMPADDR7 0x3b7 | |
245 | #define CSR_PMPADDR8 0x3b8 | |
246 | #define CSR_PMPADDR9 0x3b9 | |
247 | #define CSR_PMPADDR10 0x3ba | |
248 | #define CSR_PMPADDR11 0x3bb | |
249 | #define CSR_PMPADDR12 0x3bc | |
250 | #define CSR_PMPADDR13 0x3bd | |
251 | #define CSR_PMPADDR14 0x3be | |
252 | #define CSR_PMPADDR15 0x3bf | |
253 | ||
254 | /* Debug/Trace Registers (shared with Debug Mode) */ | |
255 | #define CSR_TSELECT 0x7a0 | |
256 | #define CSR_TDATA1 0x7a1 | |
257 | #define CSR_TDATA2 0x7a2 | |
258 | #define CSR_TDATA3 0x7a3 | |
259 | ||
260 | /* Debug Mode Registers */ | |
261 | #define CSR_DCSR 0x7b0 | |
262 | #define CSR_DPC 0x7b1 | |
263 | #define CSR_DSCRATCH 0x7b2 | |
264 | ||
265 | /* Performance Counters */ | |
266 | #define CSR_MHPMCOUNTER3 0xb03 | |
267 | #define CSR_MHPMCOUNTER4 0xb04 | |
268 | #define CSR_MHPMCOUNTER5 0xb05 | |
269 | #define CSR_MHPMCOUNTER6 0xb06 | |
270 | #define CSR_MHPMCOUNTER7 0xb07 | |
271 | #define CSR_MHPMCOUNTER8 0xb08 | |
272 | #define CSR_MHPMCOUNTER9 0xb09 | |
273 | #define CSR_MHPMCOUNTER10 0xb0a | |
274 | #define CSR_MHPMCOUNTER11 0xb0b | |
275 | #define CSR_MHPMCOUNTER12 0xb0c | |
276 | #define CSR_MHPMCOUNTER13 0xb0d | |
277 | #define CSR_MHPMCOUNTER14 0xb0e | |
278 | #define CSR_MHPMCOUNTER15 0xb0f | |
279 | #define CSR_MHPMCOUNTER16 0xb10 | |
280 | #define CSR_MHPMCOUNTER17 0xb11 | |
281 | #define CSR_MHPMCOUNTER18 0xb12 | |
282 | #define CSR_MHPMCOUNTER19 0xb13 | |
283 | #define CSR_MHPMCOUNTER20 0xb14 | |
284 | #define CSR_MHPMCOUNTER21 0xb15 | |
285 | #define CSR_MHPMCOUNTER22 0xb16 | |
286 | #define CSR_MHPMCOUNTER23 0xb17 | |
287 | #define CSR_MHPMCOUNTER24 0xb18 | |
288 | #define CSR_MHPMCOUNTER25 0xb19 | |
289 | #define CSR_MHPMCOUNTER26 0xb1a | |
290 | #define CSR_MHPMCOUNTER27 0xb1b | |
291 | #define CSR_MHPMCOUNTER28 0xb1c | |
292 | #define CSR_MHPMCOUNTER29 0xb1d | |
293 | #define CSR_MHPMCOUNTER30 0xb1e | |
294 | #define CSR_MHPMCOUNTER31 0xb1f | |
295 | #define CSR_MHPMEVENT3 0x323 | |
296 | #define CSR_MHPMEVENT4 0x324 | |
297 | #define CSR_MHPMEVENT5 0x325 | |
298 | #define CSR_MHPMEVENT6 0x326 | |
299 | #define CSR_MHPMEVENT7 0x327 | |
300 | #define CSR_MHPMEVENT8 0x328 | |
301 | #define CSR_MHPMEVENT9 0x329 | |
302 | #define CSR_MHPMEVENT10 0x32a | |
303 | #define CSR_MHPMEVENT11 0x32b | |
304 | #define CSR_MHPMEVENT12 0x32c | |
305 | #define CSR_MHPMEVENT13 0x32d | |
306 | #define CSR_MHPMEVENT14 0x32e | |
307 | #define CSR_MHPMEVENT15 0x32f | |
308 | #define CSR_MHPMEVENT16 0x330 | |
309 | #define CSR_MHPMEVENT17 0x331 | |
310 | #define CSR_MHPMEVENT18 0x332 | |
311 | #define CSR_MHPMEVENT19 0x333 | |
312 | #define CSR_MHPMEVENT20 0x334 | |
313 | #define CSR_MHPMEVENT21 0x335 | |
314 | #define CSR_MHPMEVENT22 0x336 | |
315 | #define CSR_MHPMEVENT23 0x337 | |
316 | #define CSR_MHPMEVENT24 0x338 | |
317 | #define CSR_MHPMEVENT25 0x339 | |
318 | #define CSR_MHPMEVENT26 0x33a | |
319 | #define CSR_MHPMEVENT27 0x33b | |
320 | #define CSR_MHPMEVENT28 0x33c | |
321 | #define CSR_MHPMEVENT29 0x33d | |
322 | #define CSR_MHPMEVENT30 0x33e | |
323 | #define CSR_MHPMEVENT31 0x33f | |
324 | #define CSR_MHPMCOUNTER3H 0xb83 | |
325 | #define CSR_MHPMCOUNTER4H 0xb84 | |
326 | #define CSR_MHPMCOUNTER5H 0xb85 | |
327 | #define CSR_MHPMCOUNTER6H 0xb86 | |
328 | #define CSR_MHPMCOUNTER7H 0xb87 | |
329 | #define CSR_MHPMCOUNTER8H 0xb88 | |
330 | #define CSR_MHPMCOUNTER9H 0xb89 | |
331 | #define CSR_MHPMCOUNTER10H 0xb8a | |
332 | #define CSR_MHPMCOUNTER11H 0xb8b | |
333 | #define CSR_MHPMCOUNTER12H 0xb8c | |
334 | #define CSR_MHPMCOUNTER13H 0xb8d | |
335 | #define CSR_MHPMCOUNTER14H 0xb8e | |
336 | #define CSR_MHPMCOUNTER15H 0xb8f | |
337 | #define CSR_MHPMCOUNTER16H 0xb90 | |
338 | #define CSR_MHPMCOUNTER17H 0xb91 | |
339 | #define CSR_MHPMCOUNTER18H 0xb92 | |
340 | #define CSR_MHPMCOUNTER19H 0xb93 | |
341 | #define CSR_MHPMCOUNTER20H 0xb94 | |
342 | #define CSR_MHPMCOUNTER21H 0xb95 | |
343 | #define CSR_MHPMCOUNTER22H 0xb96 | |
344 | #define CSR_MHPMCOUNTER23H 0xb97 | |
345 | #define CSR_MHPMCOUNTER24H 0xb98 | |
346 | #define CSR_MHPMCOUNTER25H 0xb99 | |
347 | #define CSR_MHPMCOUNTER26H 0xb9a | |
348 | #define CSR_MHPMCOUNTER27H 0xb9b | |
349 | #define CSR_MHPMCOUNTER28H 0xb9c | |
350 | #define CSR_MHPMCOUNTER29H 0xb9d | |
351 | #define CSR_MHPMCOUNTER30H 0xb9e | |
352 | #define CSR_MHPMCOUNTER31H 0xb9f | |
353 | ||
8e73df6a JW |
354 | /* Legacy Machine Protection and Translation (priv v1.9.1) */ |
355 | #define CSR_MBASE 0x380 | |
356 | #define CSR_MBOUND 0x381 | |
357 | #define CSR_MIBASE 0x382 | |
358 | #define CSR_MIBOUND 0x383 | |
359 | #define CSR_MDBASE 0x384 | |
360 | #define CSR_MDBOUND 0x385 | |
361 | ||
426f0348 | 362 | /* mstatus CSR bits */ |
dc5bd18f MC |
363 | #define MSTATUS_UIE 0x00000001 |
364 | #define MSTATUS_SIE 0x00000002 | |
dc5bd18f MC |
365 | #define MSTATUS_MIE 0x00000008 |
366 | #define MSTATUS_UPIE 0x00000010 | |
367 | #define MSTATUS_SPIE 0x00000020 | |
dc5bd18f MC |
368 | #define MSTATUS_MPIE 0x00000080 |
369 | #define MSTATUS_SPP 0x00000100 | |
dc5bd18f MC |
370 | #define MSTATUS_MPP 0x00001800 |
371 | #define MSTATUS_FS 0x00006000 | |
372 | #define MSTATUS_XS 0x00018000 | |
373 | #define MSTATUS_MPRV 0x00020000 | |
374 | #define MSTATUS_PUM 0x00040000 /* until: priv-1.9.1 */ | |
375 | #define MSTATUS_SUM 0x00040000 /* since: priv-1.10 */ | |
376 | #define MSTATUS_MXR 0x00080000 | |
377 | #define MSTATUS_VM 0x1F000000 /* until: priv-1.9.1 */ | |
378 | #define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */ | |
379 | #define MSTATUS_TW 0x20000000 /* since: priv-1.10 */ | |
380 | #define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */ | |
e44b50b5 | 381 | #if defined(TARGET_RISCV64) |
9034e90a | 382 | #define MSTATUS_GVA 0x4000000000ULL |
49aaa3e5 | 383 | #define MSTATUS_MPV 0x8000000000ULL |
e44b50b5 | 384 | #elif defined(TARGET_RISCV32) |
9034e90a | 385 | #define MSTATUS_GVA 0x00000040 |
e44b50b5 AF |
386 | #define MSTATUS_MPV 0x00000080 |
387 | #endif | |
388 | ||
389 | #ifdef TARGET_RISCV32 | |
390 | # define MSTATUS_MPV_ISSET(env) get_field(env->mstatush, MSTATUS_MPV) | |
391 | #else | |
392 | # define MSTATUS_MPV_ISSET(env) get_field(env->mstatus, MSTATUS_MPV) | |
393 | #endif | |
dc5bd18f MC |
394 | |
395 | #define MSTATUS64_UXL 0x0000000300000000ULL | |
396 | #define MSTATUS64_SXL 0x0000000C00000000ULL | |
397 | ||
398 | #define MSTATUS32_SD 0x80000000 | |
399 | #define MSTATUS64_SD 0x8000000000000000ULL | |
400 | ||
f18637cd MC |
401 | #define MISA32_MXL 0xC0000000 |
402 | #define MISA64_MXL 0xC000000000000000ULL | |
403 | ||
404 | #define MXL_RV32 1 | |
405 | #define MXL_RV64 2 | |
406 | #define MXL_RV128 3 | |
407 | ||
dc5bd18f MC |
408 | #if defined(TARGET_RISCV32) |
409 | #define MSTATUS_SD MSTATUS32_SD | |
f18637cd MC |
410 | #define MISA_MXL MISA32_MXL |
411 | #define MXL_VAL MXL_RV32 | |
dc5bd18f MC |
412 | #elif defined(TARGET_RISCV64) |
413 | #define MSTATUS_SD MSTATUS64_SD | |
f18637cd MC |
414 | #define MISA_MXL MISA64_MXL |
415 | #define MXL_VAL MXL_RV64 | |
dc5bd18f MC |
416 | #endif |
417 | ||
426f0348 | 418 | /* sstatus CSR bits */ |
dc5bd18f MC |
419 | #define SSTATUS_UIE 0x00000001 |
420 | #define SSTATUS_SIE 0x00000002 | |
421 | #define SSTATUS_UPIE 0x00000010 | |
422 | #define SSTATUS_SPIE 0x00000020 | |
423 | #define SSTATUS_SPP 0x00000100 | |
424 | #define SSTATUS_FS 0x00006000 | |
425 | #define SSTATUS_XS 0x00018000 | |
426 | #define SSTATUS_PUM 0x00040000 /* until: priv-1.9.1 */ | |
427 | #define SSTATUS_SUM 0x00040000 /* since: priv-1.10 */ | |
428 | #define SSTATUS_MXR 0x00080000 | |
429 | ||
430 | #define SSTATUS32_SD 0x80000000 | |
431 | #define SSTATUS64_SD 0x8000000000000000ULL | |
432 | ||
433 | #if defined(TARGET_RISCV32) | |
434 | #define SSTATUS_SD SSTATUS32_SD | |
435 | #elif defined(TARGET_RISCV64) | |
436 | #define SSTATUS_SD SSTATUS64_SD | |
437 | #endif | |
438 | ||
d28b15a4 | 439 | /* hstatus CSR bits */ |
543ba531 AF |
440 | #define HSTATUS_VSBE 0x00000020 |
441 | #define HSTATUS_GVA 0x00000040 | |
d28b15a4 | 442 | #define HSTATUS_SPV 0x00000080 |
543ba531 AF |
443 | #define HSTATUS_SPVP 0x00000100 |
444 | #define HSTATUS_HU 0x00000200 | |
445 | #define HSTATUS_VGEIN 0x0003F000 | |
d28b15a4 AF |
446 | #define HSTATUS_VTVM 0x00100000 |
447 | #define HSTATUS_VTSR 0x00400000 | |
543ba531 AF |
448 | #if defined(TARGET_RISCV64) |
449 | #define HSTATUS_VSXL 0x300000000 | |
450 | #endif | |
d28b15a4 AF |
451 | |
452 | #define HSTATUS32_WPRI 0xFF8FF87E | |
453 | #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL | |
454 | ||
455 | #if defined(TARGET_RISCV32) | |
456 | #define HSTATUS_WPRI HSTATUS32_WPRI | |
457 | #elif defined(TARGET_RISCV64) | |
458 | #define HSTATUS_WPRI HSTATUS64_WPRI | |
459 | #endif | |
460 | ||
426f0348 | 461 | /* Privilege modes */ |
dc5bd18f MC |
462 | #define PRV_U 0 |
463 | #define PRV_S 1 | |
356d7419 | 464 | #define PRV_H 2 /* Reserved */ |
dc5bd18f MC |
465 | #define PRV_M 3 |
466 | ||
ef6bb7b6 AF |
467 | /* Virtulisation Register Fields */ |
468 | #define VIRT_ONOFF 1 | |
c7b1bbc8 AF |
469 | /* This is used to save state for when we take an exception. If this is set |
470 | * that means that we want to force a HS level exception (no matter what the | |
471 | * delegation is set to). This will occur for things such as a second level | |
472 | * page table fault. | |
473 | */ | |
474 | #define FORCE_HS_EXCEP 2 | |
5a894dd7 | 475 | #define HS_TWO_STAGE 4 |
ef6bb7b6 | 476 | |
426f0348 MC |
477 | /* RV32 satp CSR field masks */ |
478 | #define SATP32_MODE 0x80000000 | |
479 | #define SATP32_ASID 0x7fc00000 | |
480 | #define SATP32_PPN 0x003fffff | |
481 | ||
482 | /* RV64 satp CSR field masks */ | |
483 | #define SATP64_MODE 0xF000000000000000ULL | |
484 | #define SATP64_ASID 0x0FFFF00000000000ULL | |
485 | #define SATP64_PPN 0x00000FFFFFFFFFFFULL | |
dc5bd18f MC |
486 | |
487 | #if defined(TARGET_RISCV32) | |
426f0348 MC |
488 | #define SATP_MODE SATP32_MODE |
489 | #define SATP_ASID SATP32_ASID | |
490 | #define SATP_PPN SATP32_PPN | |
dc5bd18f MC |
491 | #endif |
492 | #if defined(TARGET_RISCV64) | |
426f0348 MC |
493 | #define SATP_MODE SATP64_MODE |
494 | #define SATP_ASID SATP64_ASID | |
495 | #define SATP_PPN SATP64_PPN | |
dc5bd18f MC |
496 | #endif |
497 | ||
426f0348 MC |
498 | /* VM modes (mstatus.vm) privileged ISA 1.9.1 */ |
499 | #define VM_1_09_MBARE 0 | |
500 | #define VM_1_09_MBB 1 | |
501 | #define VM_1_09_MBBID 2 | |
502 | #define VM_1_09_SV32 8 | |
503 | #define VM_1_09_SV39 9 | |
504 | #define VM_1_09_SV48 10 | |
505 | ||
506 | /* VM modes (satp.mode) privileged ISA 1.10 */ | |
507 | #define VM_1_10_MBARE 0 | |
508 | #define VM_1_10_SV32 1 | |
509 | #define VM_1_10_SV39 8 | |
510 | #define VM_1_10_SV48 9 | |
511 | #define VM_1_10_SV57 10 | |
512 | #define VM_1_10_SV64 11 | |
513 | ||
514 | /* Page table entry (PTE) fields */ | |
515 | #define PTE_V 0x001 /* Valid */ | |
516 | #define PTE_R 0x002 /* Read */ | |
517 | #define PTE_W 0x004 /* Write */ | |
518 | #define PTE_X 0x008 /* Execute */ | |
519 | #define PTE_U 0x010 /* User */ | |
520 | #define PTE_G 0x020 /* Global */ | |
521 | #define PTE_A 0x040 /* Accessed */ | |
522 | #define PTE_D 0x080 /* Dirty */ | |
523 | #define PTE_SOFT 0x300 /* Reserved for Software */ | |
524 | ||
525 | /* Page table PPN shift amount */ | |
526 | #define PTE_PPN_SHIFT 10 | |
527 | ||
528 | /* Leaf page shift amount */ | |
529 | #define PGSHIFT 12 | |
530 | ||
531 | /* Default Reset Vector adress */ | |
532 | #define DEFAULT_RSTVEC 0x1000 | |
533 | ||
534 | /* Exception causes */ | |
ab67a1d0 AF |
535 | #define EXCP_NONE -1 /* sentinel value */ |
536 | #define RISCV_EXCP_INST_ADDR_MIS 0x0 | |
537 | #define RISCV_EXCP_INST_ACCESS_FAULT 0x1 | |
538 | #define RISCV_EXCP_ILLEGAL_INST 0x2 | |
539 | #define RISCV_EXCP_BREAKPOINT 0x3 | |
540 | #define RISCV_EXCP_LOAD_ADDR_MIS 0x4 | |
541 | #define RISCV_EXCP_LOAD_ACCESS_FAULT 0x5 | |
542 | #define RISCV_EXCP_STORE_AMO_ADDR_MIS 0x6 | |
543 | #define RISCV_EXCP_STORE_AMO_ACCESS_FAULT 0x7 | |
544 | #define RISCV_EXCP_U_ECALL 0x8 | |
545 | #define RISCV_EXCP_S_ECALL 0x9 | |
546 | #define RISCV_EXCP_VS_ECALL 0xa | |
547 | #define RISCV_EXCP_M_ECALL 0xb | |
548 | #define RISCV_EXCP_INST_PAGE_FAULT 0xc /* since: priv-1.10.0 */ | |
549 | #define RISCV_EXCP_LOAD_PAGE_FAULT 0xd /* since: priv-1.10.0 */ | |
550 | #define RISCV_EXCP_STORE_PAGE_FAULT 0xf /* since: priv-1.10.0 */ | |
551 | #define RISCV_EXCP_INST_GUEST_PAGE_FAULT 0x14 | |
552 | #define RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT 0x15 | |
553 | #define RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT 0x17 | |
dc5bd18f MC |
554 | |
555 | #define RISCV_EXCP_INT_FLAG 0x80000000 | |
556 | #define RISCV_EXCP_INT_MASK 0x7fffffff | |
557 | ||
426f0348 MC |
558 | /* Interrupt causes */ |
559 | #define IRQ_U_SOFT 0 | |
560 | #define IRQ_S_SOFT 1 | |
205377f8 | 561 | #define IRQ_VS_SOFT 2 |
426f0348 MC |
562 | #define IRQ_M_SOFT 3 |
563 | #define IRQ_U_TIMER 4 | |
564 | #define IRQ_S_TIMER 5 | |
205377f8 | 565 | #define IRQ_VS_TIMER 6 |
426f0348 MC |
566 | #define IRQ_M_TIMER 7 |
567 | #define IRQ_U_EXT 8 | |
568 | #define IRQ_S_EXT 9 | |
205377f8 | 569 | #define IRQ_VS_EXT 10 |
426f0348 MC |
570 | #define IRQ_M_EXT 11 |
571 | ||
572 | /* mip masks */ | |
573 | #define MIP_USIP (1 << IRQ_U_SOFT) | |
574 | #define MIP_SSIP (1 << IRQ_S_SOFT) | |
205377f8 | 575 | #define MIP_VSSIP (1 << IRQ_VS_SOFT) |
426f0348 MC |
576 | #define MIP_MSIP (1 << IRQ_M_SOFT) |
577 | #define MIP_UTIP (1 << IRQ_U_TIMER) | |
578 | #define MIP_STIP (1 << IRQ_S_TIMER) | |
205377f8 | 579 | #define MIP_VSTIP (1 << IRQ_VS_TIMER) |
426f0348 MC |
580 | #define MIP_MTIP (1 << IRQ_M_TIMER) |
581 | #define MIP_UEIP (1 << IRQ_U_EXT) | |
582 | #define MIP_SEIP (1 << IRQ_S_EXT) | |
205377f8 | 583 | #define MIP_VSEIP (1 << IRQ_VS_EXT) |
426f0348 MC |
584 | #define MIP_MEIP (1 << IRQ_M_EXT) |
585 | ||
586 | /* sip masks */ | |
587 | #define SIP_SSIP MIP_SSIP | |
588 | #define SIP_STIP MIP_STIP | |
589 | #define SIP_SEIP MIP_SEIP | |
f91005e1 | 590 | |
66e594f2 AF |
591 | /* MIE masks */ |
592 | #define MIE_SEIE (1 << IRQ_S_EXT) | |
593 | #define MIE_UEIE (1 << IRQ_U_EXT) | |
594 | #define MIE_STIE (1 << IRQ_S_TIMER) | |
595 | #define MIE_UTIE (1 << IRQ_U_TIMER) | |
596 | #define MIE_SSIE (1 << IRQ_S_SOFT) | |
597 | #define MIE_USIE (1 << IRQ_U_SOFT) | |
f91005e1 | 598 | #endif |