[mirror_qemu.git] / target / riscv / cpu_bits.h

/* RISC-V ISA constants */

#ifndef TARGET_RISCV_CPU_BITS_H
#define TARGET_RISCV_CPU_BITS_H

#define get_field(reg, mask) (((reg) & \
                 (uint64_t)(mask)) / ((mask) & ~((mask) << 1)))
#define set_field(reg, mask, val) (((reg) & ~(uint64_t)(mask)) | \
                 (((uint64_t)(val) * ((mask) & ~((mask) << 1))) & \
                 (uint64_t)(mask)))

/* Floating point round mode */
#define FSR_RD_SHIFT        5
#define FSR_RD              (0x7 << FSR_RD_SHIFT)

/* Floating point accrued exception flags */
#define FPEXC_NX            0x01
#define FPEXC_UF            0x02
#define FPEXC_OF            0x04
#define FPEXC_DZ            0x08
#define FPEXC_NV            0x10

/* Floating point status register bits */
#define FSR_AEXC_SHIFT      0
#define FSR_NVA             (FPEXC_NV << FSR_AEXC_SHIFT)
#define FSR_OFA             (FPEXC_OF << FSR_AEXC_SHIFT)
#define FSR_UFA             (FPEXC_UF << FSR_AEXC_SHIFT)
#define FSR_DZA             (FPEXC_DZ << FSR_AEXC_SHIFT)
#define FSR_NXA             (FPEXC_NX << FSR_AEXC_SHIFT)
#define FSR_AEXC            (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)

/* Vector Fixed-Point round model */
#define FSR_VXRM_SHIFT      9
#define FSR_VXRM            (0x3 << FSR_VXRM_SHIFT)

/* Vector Fixed-Point saturation flag */
#define FSR_VXSAT_SHIFT     8
#define FSR_VXSAT           (0x1 << FSR_VXSAT_SHIFT)

/* Control and Status Registers */

/* User Trap Setup */
#define CSR_USTATUS         0x000
#define CSR_UIE             0x004
#define CSR_UTVEC           0x005

/* User Trap Handling */
#define CSR_USCRATCH        0x040
#define CSR_UEPC            0x041
#define CSR_UCAUSE          0x042
#define CSR_UTVAL           0x043
#define CSR_UIP             0x044

/* User Floating-Point CSRs */
#define CSR_FFLAGS          0x001
#define CSR_FRM             0x002
#define CSR_FCSR            0x003

/* User Vector CSRs */
#define CSR_VSTART          0x008
#define CSR_VXSAT           0x009
#define CSR_VXRM            0x00a
#define CSR_VL              0xc20
#define CSR_VTYPE           0xc21

/* User Timers and Counters */
#define CSR_CYCLE           0xc00
#define CSR_TIME            0xc01
#define CSR_INSTRET         0xc02
#define CSR_HPMCOUNTER3     0xc03
#define CSR_HPMCOUNTER4     0xc04
#define CSR_HPMCOUNTER5     0xc05
#define CSR_HPMCOUNTER6     0xc06
#define CSR_HPMCOUNTER7     0xc07
#define CSR_HPMCOUNTER8     0xc08
#define CSR_HPMCOUNTER9     0xc09
#define CSR_HPMCOUNTER10    0xc0a
#define CSR_HPMCOUNTER11    0xc0b
#define CSR_HPMCOUNTER12    0xc0c
#define CSR_HPMCOUNTER13    0xc0d
#define CSR_HPMCOUNTER14    0xc0e
#define CSR_HPMCOUNTER15    0xc0f
#define CSR_HPMCOUNTER16    0xc10
#define CSR_HPMCOUNTER17    0xc11
#define CSR_HPMCOUNTER18    0xc12
#define CSR_HPMCOUNTER19    0xc13
#define CSR_HPMCOUNTER20    0xc14
#define CSR_HPMCOUNTER21    0xc15
#define CSR_HPMCOUNTER22    0xc16
#define CSR_HPMCOUNTER23    0xc17
#define CSR_HPMCOUNTER24    0xc18
#define CSR_HPMCOUNTER25    0xc19
#define CSR_HPMCOUNTER26    0xc1a
#define CSR_HPMCOUNTER27    0xc1b
#define CSR_HPMCOUNTER28    0xc1c
#define CSR_HPMCOUNTER29    0xc1d
#define CSR_HPMCOUNTER30    0xc1e
#define CSR_HPMCOUNTER31    0xc1f
#define CSR_CYCLEH          0xc80
#define CSR_TIMEH           0xc81
#define CSR_INSTRETH        0xc82
#define CSR_HPMCOUNTER3H    0xc83
#define CSR_HPMCOUNTER4H    0xc84
#define CSR_HPMCOUNTER5H    0xc85
#define CSR_HPMCOUNTER6H    0xc86
#define CSR_HPMCOUNTER7H    0xc87
#define CSR_HPMCOUNTER8H    0xc88
#define CSR_HPMCOUNTER9H    0xc89
#define CSR_HPMCOUNTER10H   0xc8a
#define CSR_HPMCOUNTER11H   0xc8b
#define CSR_HPMCOUNTER12H   0xc8c
#define CSR_HPMCOUNTER13H   0xc8d
#define CSR_HPMCOUNTER14H   0xc8e
#define CSR_HPMCOUNTER15H   0xc8f
#define CSR_HPMCOUNTER16H   0xc90
#define CSR_HPMCOUNTER17H   0xc91
#define CSR_HPMCOUNTER18H   0xc92
#define CSR_HPMCOUNTER19H   0xc93
#define CSR_HPMCOUNTER20H   0xc94
#define CSR_HPMCOUNTER21H   0xc95
#define CSR_HPMCOUNTER22H   0xc96
#define CSR_HPMCOUNTER23H   0xc97
#define CSR_HPMCOUNTER24H   0xc98
#define CSR_HPMCOUNTER25H   0xc99
#define CSR_HPMCOUNTER26H   0xc9a
#define CSR_HPMCOUNTER27H   0xc9b
#define CSR_HPMCOUNTER28H   0xc9c
#define CSR_HPMCOUNTER29H   0xc9d
#define CSR_HPMCOUNTER30H   0xc9e
#define CSR_HPMCOUNTER31H   0xc9f

/* Machine Timers and Counters */
#define CSR_MCYCLE          0xb00
#define CSR_MINSTRET        0xb02
#define CSR_MCYCLEH         0xb80
#define CSR_MINSTRETH       0xb82

/* Machine Information Registers */
#define CSR_MVENDORID       0xf11
#define CSR_MARCHID         0xf12
#define CSR_MIMPID          0xf13
#define CSR_MHARTID         0xf14

/* Machine Trap Setup */
#define CSR_MSTATUS         0x300
#define CSR_MISA            0x301
#define CSR_MEDELEG         0x302
#define CSR_MIDELEG         0x303
#define CSR_MIE             0x304
#define CSR_MTVEC           0x305
#define CSR_MCOUNTEREN      0x306

/* 32-bit only */
#define CSR_MSTATUSH        0x310

/* Machine Trap Handling */
#define CSR_MSCRATCH        0x340
#define CSR_MEPC            0x341
#define CSR_MCAUSE          0x342
#define CSR_MTVAL           0x343
#define CSR_MIP             0x344

/* Supervisor Trap Setup */
#define CSR_SSTATUS         0x100
#define CSR_SEDELEG         0x102
#define CSR_SIDELEG         0x103
#define CSR_SIE             0x104
#define CSR_STVEC           0x105
#define CSR_SCOUNTEREN      0x106

/* Supervisor Trap Handling */
#define CSR_SSCRATCH        0x140
#define CSR_SEPC            0x141
#define CSR_SCAUSE          0x142
#define CSR_STVAL           0x143
#define CSR_SIP             0x144

/* Supervisor Protection and Translation */
#define CSR_SPTBR           0x180
#define CSR_SATP            0x180

/* Hpervisor CSRs */
#define CSR_HSTATUS         0x600
#define CSR_HEDELEG         0x602
#define CSR_HIDELEG         0x603
#define CSR_HIE             0x604
#define CSR_HCOUNTEREN      0x606
#define CSR_HGEIE           0x607
#define CSR_HTVAL           0x643
#define CSR_HVIP            0x645
#define CSR_HIP             0x644
#define CSR_HTINST          0x64A
#define CSR_HGEIP           0xE12
#define CSR_HGATP           0x680
#define CSR_HTIMEDELTA      0x605
#define CSR_HTIMEDELTAH     0x615

/* Virtual CSRs */
#define CSR_VSSTATUS        0x200
#define CSR_VSIE            0x204
#define CSR_VSTVEC          0x205
#define CSR_VSSCRATCH       0x240
#define CSR_VSEPC           0x241
#define CSR_VSCAUSE         0x242
#define CSR_VSTVAL          0x243
#define CSR_VSIP            0x244
#define CSR_VSATP           0x280

#define CSR_MTINST          0x34a
#define CSR_MTVAL2          0x34b

/* Enhanced Physical Memory Protection (ePMP) */
#define CSR_MSECCFG         0x747
#define CSR_MSECCFGH        0x757
/* Physical Memory Protection */
#define CSR_PMPCFG0         0x3a0
#define CSR_PMPCFG1         0x3a1
#define CSR_PMPCFG2         0x3a2
#define CSR_PMPCFG3         0x3a3
#define CSR_PMPADDR0        0x3b0
#define CSR_PMPADDR1        0x3b1
#define CSR_PMPADDR2        0x3b2
#define CSR_PMPADDR3        0x3b3
#define CSR_PMPADDR4        0x3b4
#define CSR_PMPADDR5        0x3b5
#define CSR_PMPADDR6        0x3b6
#define CSR_PMPADDR7        0x3b7
#define CSR_PMPADDR8        0x3b8
#define CSR_PMPADDR9        0x3b9
#define CSR_PMPADDR10       0x3ba
#define CSR_PMPADDR11       0x3bb
#define CSR_PMPADDR12       0x3bc
#define CSR_PMPADDR13       0x3bd
#define CSR_PMPADDR14       0x3be
#define CSR_PMPADDR15       0x3bf

/* Debug/Trace Registers (shared with Debug Mode) */
#define CSR_TSELECT         0x7a0
#define CSR_TDATA1          0x7a1
#define CSR_TDATA2          0x7a2
#define CSR_TDATA3          0x7a3

/* Debug Mode Registers */
#define CSR_DCSR            0x7b0
#define CSR_DPC             0x7b1
#define CSR_DSCRATCH        0x7b2

/* Performance Counters */
#define CSR_MHPMCOUNTER3    0xb03
#define CSR_MHPMCOUNTER4    0xb04
#define CSR_MHPMCOUNTER5    0xb05
#define CSR_MHPMCOUNTER6    0xb06
#define CSR_MHPMCOUNTER7    0xb07
#define CSR_MHPMCOUNTER8    0xb08
#define CSR_MHPMCOUNTER9    0xb09
#define CSR_MHPMCOUNTER10   0xb0a
#define CSR_MHPMCOUNTER11   0xb0b
#define CSR_MHPMCOUNTER12   0xb0c
#define CSR_MHPMCOUNTER13   0xb0d
#define CSR_MHPMCOUNTER14   0xb0e
#define CSR_MHPMCOUNTER15   0xb0f
#define CSR_MHPMCOUNTER16   0xb10
#define CSR_MHPMCOUNTER17   0xb11
#define CSR_MHPMCOUNTER18   0xb12
#define CSR_MHPMCOUNTER19   0xb13
#define CSR_MHPMCOUNTER20   0xb14
#define CSR_MHPMCOUNTER21   0xb15
#define CSR_MHPMCOUNTER22   0xb16
#define CSR_MHPMCOUNTER23   0xb17
#define CSR_MHPMCOUNTER24   0xb18
#define CSR_MHPMCOUNTER25   0xb19
#define CSR_MHPMCOUNTER26   0xb1a
#define CSR_MHPMCOUNTER27   0xb1b
#define CSR_MHPMCOUNTER28   0xb1c
#define CSR_MHPMCOUNTER29   0xb1d
#define CSR_MHPMCOUNTER30   0xb1e
#define CSR_MHPMCOUNTER31   0xb1f
#define CSR_MHPMEVENT3      0x323
#define CSR_MHPMEVENT4      0x324
#define CSR_MHPMEVENT5      0x325
#define CSR_MHPMEVENT6      0x326
#define CSR_MHPMEVENT7      0x327
#define CSR_MHPMEVENT8      0x328
#define CSR_MHPMEVENT9      0x329
#define CSR_MHPMEVENT10     0x32a
#define CSR_MHPMEVENT11     0x32b
#define CSR_MHPMEVENT12     0x32c
#define CSR_MHPMEVENT13     0x32d
#define CSR_MHPMEVENT14     0x32e
#define CSR_MHPMEVENT15     0x32f
#define CSR_MHPMEVENT16     0x330
#define CSR_MHPMEVENT17     0x331
#define CSR_MHPMEVENT18     0x332
#define CSR_MHPMEVENT19     0x333
#define CSR_MHPMEVENT20     0x334
#define CSR_MHPMEVENT21     0x335
#define CSR_MHPMEVENT22     0x336
#define CSR_MHPMEVENT23     0x337
#define CSR_MHPMEVENT24     0x338
#define CSR_MHPMEVENT25     0x339
#define CSR_MHPMEVENT26     0x33a
#define CSR_MHPMEVENT27     0x33b
#define CSR_MHPMEVENT28     0x33c
#define CSR_MHPMEVENT29     0x33d
#define CSR_MHPMEVENT30     0x33e
#define CSR_MHPMEVENT31     0x33f
#define CSR_MHPMCOUNTER3H   0xb83
#define CSR_MHPMCOUNTER4H   0xb84
#define CSR_MHPMCOUNTER5H   0xb85
#define CSR_MHPMCOUNTER6H   0xb86
#define CSR_MHPMCOUNTER7H   0xb87
#define CSR_MHPMCOUNTER8H   0xb88
#define CSR_MHPMCOUNTER9H   0xb89
#define CSR_MHPMCOUNTER10H  0xb8a
#define CSR_MHPMCOUNTER11H  0xb8b
#define CSR_MHPMCOUNTER12H  0xb8c
#define CSR_MHPMCOUNTER13H  0xb8d
#define CSR_MHPMCOUNTER14H  0xb8e
#define CSR_MHPMCOUNTER15H  0xb8f
#define CSR_MHPMCOUNTER16H  0xb90
#define CSR_MHPMCOUNTER17H  0xb91
#define CSR_MHPMCOUNTER18H  0xb92
#define CSR_MHPMCOUNTER19H  0xb93
#define CSR_MHPMCOUNTER20H  0xb94
#define CSR_MHPMCOUNTER21H  0xb95
#define CSR_MHPMCOUNTER22H  0xb96
#define CSR_MHPMCOUNTER23H  0xb97
#define CSR_MHPMCOUNTER24H  0xb98
#define CSR_MHPMCOUNTER25H  0xb99
#define CSR_MHPMCOUNTER26H  0xb9a
#define CSR_MHPMCOUNTER27H  0xb9b
#define CSR_MHPMCOUNTER28H  0xb9c
#define CSR_MHPMCOUNTER29H  0xb9d
#define CSR_MHPMCOUNTER30H  0xb9e
#define CSR_MHPMCOUNTER31H  0xb9f

/*
 * User PointerMasking registers
 * NB: actual CSR numbers might be changed in future
 */
#define CSR_UMTE            0x4c0
#define CSR_UPMMASK         0x4c1
#define CSR_UPMBASE         0x4c2

/*
 * Machine PointerMasking registers
 * NB: actual CSR numbers might be changed in future
 */
#define CSR_MMTE            0x3c0
#define CSR_MPMMASK         0x3c1
#define CSR_MPMBASE         0x3c2

/*
 * Supervisor PointerMaster registers
 * NB: actual CSR numbers might be changed in future
 */
#define CSR_SMTE            0x1c0
#define CSR_SPMMASK         0x1c1
#define CSR_SPMBASE         0x1c2

/*
 * Hypervisor PointerMaster registers
 * NB: actual CSR numbers might be changed in future
 */
#define CSR_VSMTE           0x2c0
#define CSR_VSPMMASK        0x2c1
#define CSR_VSPMBASE        0x2c2

/* mstatus CSR bits */
#define MSTATUS_UIE         0x00000001
#define MSTATUS_SIE         0x00000002
#define MSTATUS_MIE         0x00000008
#define MSTATUS_UPIE        0x00000010
#define MSTATUS_SPIE        0x00000020
#define MSTATUS_UBE         0x00000040
#define MSTATUS_MPIE        0x00000080
#define MSTATUS_SPP         0x00000100
#define MSTATUS_VS          0x00000600
#define MSTATUS_MPP         0x00001800
#define MSTATUS_FS          0x00006000
#define MSTATUS_XS          0x00018000
#define MSTATUS_MPRV        0x00020000
#define MSTATUS_SUM         0x00040000 /* since: priv-1.10 */
#define MSTATUS_MXR         0x00080000
#define MSTATUS_TVM         0x00100000 /* since: priv-1.10 */
#define MSTATUS_TW          0x00200000 /* since: priv-1.10 */
#define MSTATUS_TSR         0x00400000 /* since: priv-1.10 */
#define MSTATUS_GVA         0x4000000000ULL
#define MSTATUS_MPV         0x8000000000ULL

#define MSTATUS64_UXL       0x0000000300000000ULL
#define MSTATUS64_SXL       0x0000000C00000000ULL

#define MSTATUS32_SD        0x80000000
#define MSTATUS64_SD        0x8000000000000000ULL

#define MISA32_MXL          0xC0000000
#define MISA64_MXL          0xC000000000000000ULL

typedef enum {
    MXL_RV32  = 1,
    MXL_RV64  = 2,
    MXL_RV128 = 3,
} RISCVMXL;

/* sstatus CSR bits */
#define SSTATUS_UIE         0x00000001
#define SSTATUS_SIE         0x00000002
#define SSTATUS_UPIE        0x00000010
#define SSTATUS_SPIE        0x00000020
#define SSTATUS_SPP         0x00000100
#define SSTATUS_VS          0x00000600
#define SSTATUS_FS          0x00006000
#define SSTATUS_XS          0x00018000
#define SSTATUS_SUM         0x00040000 /* since: priv-1.10 */
#define SSTATUS_MXR         0x00080000

#define SSTATUS32_SD        0x80000000
#define SSTATUS64_SD        0x8000000000000000ULL

/* hstatus CSR bits */
#define HSTATUS_VSBE         0x00000020
#define HSTATUS_GVA          0x00000040
#define HSTATUS_SPV          0x00000080
#define HSTATUS_SPVP         0x00000100
#define HSTATUS_HU           0x00000200
#define HSTATUS_VGEIN        0x0003F000
#define HSTATUS_VTVM         0x00100000
#define HSTATUS_VTW          0x00200000
#define HSTATUS_VTSR         0x00400000
#define HSTATUS_VSXL         0x300000000

#define HSTATUS32_WPRI       0xFF8FF87E
#define HSTATUS64_WPRI       0xFFFFFFFFFF8FF87EULL

#define COUNTEREN_CY         (1 << 0)
#define COUNTEREN_TM         (1 << 1)
#define COUNTEREN_IR         (1 << 2)
#define COUNTEREN_HPM3       (1 << 3)

/* Privilege modes */
#define PRV_U 0
#define PRV_S 1
#define PRV_H 2 /* Reserved */
#define PRV_M 3

/* Virtulisation Register Fields */
#define VIRT_ONOFF          1

/* RV32 satp CSR field masks */
#define SATP32_MODE         0x80000000
#define SATP32_ASID         0x7fc00000
#define SATP32_PPN          0x003fffff

/* RV64 satp CSR field masks */
#define SATP64_MODE         0xF000000000000000ULL
#define SATP64_ASID         0x0FFFF00000000000ULL
#define SATP64_PPN          0x00000FFFFFFFFFFFULL

/* VM modes (satp.mode) privileged ISA 1.10 */
#define VM_1_10_MBARE       0
#define VM_1_10_SV32        1
#define VM_1_10_SV39        8
#define VM_1_10_SV48        9
#define VM_1_10_SV57        10
#define VM_1_10_SV64        11

/* Page table entry (PTE) fields */
#define PTE_V               0x001 /* Valid */
#define PTE_R               0x002 /* Read */
#define PTE_W               0x004 /* Write */
#define PTE_X               0x008 /* Execute */
#define PTE_U               0x010 /* User */
#define PTE_G               0x020 /* Global */
#define PTE_A               0x040 /* Accessed */
#define PTE_D               0x080 /* Dirty */
#define PTE_SOFT            0x300 /* Reserved for Software */

/* Page table PPN shift amount */
#define PTE_PPN_SHIFT       10

/* Leaf page shift amount */
#define PGSHIFT             12

/* Default Reset Vector adress */
#define DEFAULT_RSTVEC      0x1000

/* Exception causes */
typedef enum RISCVException {
    RISCV_EXCP_NONE = -1, /* sentinel value */
    RISCV_EXCP_INST_ADDR_MIS = 0x0,
    RISCV_EXCP_INST_ACCESS_FAULT = 0x1,
    RISCV_EXCP_ILLEGAL_INST = 0x2,
    RISCV_EXCP_BREAKPOINT = 0x3,
    RISCV_EXCP_LOAD_ADDR_MIS = 0x4,
    RISCV_EXCP_LOAD_ACCESS_FAULT = 0x5,
    RISCV_EXCP_STORE_AMO_ADDR_MIS = 0x6,
    RISCV_EXCP_STORE_AMO_ACCESS_FAULT = 0x7,
    RISCV_EXCP_U_ECALL = 0x8,
    RISCV_EXCP_S_ECALL = 0x9,
    RISCV_EXCP_VS_ECALL = 0xa,
    RISCV_EXCP_M_ECALL = 0xb,
    RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
    RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
    RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
    RISCV_EXCP_SEMIHOST = 0x10,
    RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
    RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
    RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
    RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
} RISCVException;

#define RISCV_EXCP_INT_FLAG                0x80000000
#define RISCV_EXCP_INT_MASK                0x7fffffff

/* Interrupt causes */
#define IRQ_U_SOFT                         0
#define IRQ_S_SOFT                         1
#define IRQ_VS_SOFT                        2
#define IRQ_M_SOFT                         3
#define IRQ_U_TIMER                        4
#define IRQ_S_TIMER                        5
#define IRQ_VS_TIMER                       6
#define IRQ_M_TIMER                        7
#define IRQ_U_EXT                          8
#define IRQ_S_EXT                          9
#define IRQ_VS_EXT                         10
#define IRQ_M_EXT                          11

/* mip masks */
#define MIP_USIP                           (1 << IRQ_U_SOFT)
#define MIP_SSIP                           (1 << IRQ_S_SOFT)
#define MIP_VSSIP                          (1 << IRQ_VS_SOFT)
#define MIP_MSIP                           (1 << IRQ_M_SOFT)
#define MIP_UTIP                           (1 << IRQ_U_TIMER)
#define MIP_STIP                           (1 << IRQ_S_TIMER)
#define MIP_VSTIP                          (1 << IRQ_VS_TIMER)
#define MIP_MTIP                           (1 << IRQ_M_TIMER)
#define MIP_UEIP                           (1 << IRQ_U_EXT)
#define MIP_SEIP                           (1 << IRQ_S_EXT)
#define MIP_VSEIP                          (1 << IRQ_VS_EXT)
#define MIP_MEIP                           (1 << IRQ_M_EXT)

/* sip masks */
#define SIP_SSIP                           MIP_SSIP
#define SIP_STIP                           MIP_STIP
#define SIP_SEIP                           MIP_SEIP

/* MIE masks */
#define MIE_SEIE                           (1 << IRQ_S_EXT)
#define MIE_UEIE                           (1 << IRQ_U_EXT)
#define MIE_STIE                           (1 << IRQ_S_TIMER)
#define MIE_UTIE                           (1 << IRQ_U_TIMER)
#define MIE_SSIE                           (1 << IRQ_S_SOFT)
#define MIE_USIE                           (1 << IRQ_U_SOFT)

/* General PointerMasking CSR bits*/
#define PM_ENABLE       0x00000001ULL
#define PM_CURRENT      0x00000002ULL
#define PM_INSN         0x00000004ULL
#define PM_XS_MASK      0x00000003ULL

/* PointerMasking XS bits values */
#define PM_EXT_DISABLE  0x00000000ULL
#define PM_EXT_INITIAL  0x00000001ULL
#define PM_EXT_CLEAN    0x00000002ULL
#define PM_EXT_DIRTY    0x00000003ULL

/* Offsets for every pair of control bits per each priv level */
#define XS_OFFSET    0ULL
#define U_OFFSET     2ULL
#define S_OFFSET     5ULL
#define M_OFFSET     8ULL

#define PM_XS_BITS   (PM_XS_MASK << XS_OFFSET)
#define U_PM_ENABLE  (PM_ENABLE  << U_OFFSET)
#define U_PM_CURRENT (PM_CURRENT << U_OFFSET)
#define U_PM_INSN    (PM_INSN    << U_OFFSET)
#define S_PM_ENABLE  (PM_ENABLE  << S_OFFSET)
#define S_PM_CURRENT (PM_CURRENT << S_OFFSET)
#define S_PM_INSN    (PM_INSN    << S_OFFSET)
#define M_PM_ENABLE  (PM_ENABLE  << M_OFFSET)
#define M_PM_CURRENT (PM_CURRENT << M_OFFSET)
#define M_PM_INSN    (PM_INSN    << M_OFFSET)

/* mmte CSR bits */
#define MMTE_PM_XS_BITS     PM_XS_BITS
#define MMTE_U_PM_ENABLE    U_PM_ENABLE
#define MMTE_U_PM_CURRENT   U_PM_CURRENT
#define MMTE_U_PM_INSN      U_PM_INSN
#define MMTE_S_PM_ENABLE    S_PM_ENABLE
#define MMTE_S_PM_CURRENT   S_PM_CURRENT
#define MMTE_S_PM_INSN      S_PM_INSN
#define MMTE_M_PM_ENABLE    M_PM_ENABLE
#define MMTE_M_PM_CURRENT   M_PM_CURRENT
#define MMTE_M_PM_INSN      M_PM_INSN
#define MMTE_MASK    (MMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | MMTE_U_PM_INSN | \
                      MMTE_S_PM_ENABLE | MMTE_S_PM_CURRENT | MMTE_S_PM_INSN | \
                      MMTE_M_PM_ENABLE | MMTE_M_PM_CURRENT | MMTE_M_PM_INSN | \
                      MMTE_PM_XS_BITS)

/* (v)smte CSR bits */
#define SMTE_PM_XS_BITS     PM_XS_BITS
#define SMTE_U_PM_ENABLE    U_PM_ENABLE
#define SMTE_U_PM_CURRENT   U_PM_CURRENT
#define SMTE_U_PM_INSN      U_PM_INSN
#define SMTE_S_PM_ENABLE    S_PM_ENABLE
#define SMTE_S_PM_CURRENT   S_PM_CURRENT
#define SMTE_S_PM_INSN      S_PM_INSN
#define SMTE_MASK    (SMTE_U_PM_ENABLE | SMTE_U_PM_CURRENT | SMTE_U_PM_INSN | \
                      SMTE_S_PM_ENABLE | SMTE_S_PM_CURRENT | SMTE_S_PM_INSN | \
                      SMTE_PM_XS_BITS)

/* umte CSR bits */
#define UMTE_U_PM_ENABLE    U_PM_ENABLE
#define UMTE_U_PM_CURRENT   U_PM_CURRENT
#define UMTE_U_PM_INSN      U_PM_INSN
#define UMTE_MASK     (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_INSN)

#endif
Commit	Line	Data
dc5bd18f MC	1	/* RISC-V ISA constants */
dc5bd18f MC	2
f91005e1 MA	3	#ifndef TARGET_RISCV_CPU_BITS_H
	4	#define TARGET_RISCV_CPU_BITS_H
	5
dc5bd18f	6	#define get_field(reg, mask) (((reg) & \
284d697c YJ	7	(uint64_t)(mask)) / ((mask) & ~((mask) << 1)))
	8	#define set_field(reg, mask, val) (((reg) & ~(uint64_t)(mask)) \| \
	9	(((uint64_t)(val) * ((mask) & ~((mask) << 1))) & \
	10	(uint64_t)(mask)))
dc5bd18f	11
426f0348 MC	12	/* Floating point round mode */
	13	#define FSR_RD_SHIFT 5
	14	#define FSR_RD (0x7 << FSR_RD_SHIFT)
	15
	16	/* Floating point accrued exception flags */
	17	#define FPEXC_NX 0x01
	18	#define FPEXC_UF 0x02
	19	#define FPEXC_OF 0x04
	20	#define FPEXC_DZ 0x08
	21	#define FPEXC_NV 0x10
	22
	23	/* Floating point status register bits */
	24	#define FSR_AEXC_SHIFT 0
	25	#define FSR_NVA (FPEXC_NV << FSR_AEXC_SHIFT)
	26	#define FSR_OFA (FPEXC_OF << FSR_AEXC_SHIFT)
	27	#define FSR_UFA (FPEXC_UF << FSR_AEXC_SHIFT)
	28	#define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT)
	29	#define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT)
	30	#define FSR_AEXC (FSR_NVA \| FSR_OFA \| FSR_UFA \| FSR_DZA \| FSR_NXA)
	31
8e3a1f18 LZ	32	/* Vector Fixed-Point round model */
	33	#define FSR_VXRM_SHIFT 9
	34	#define FSR_VXRM (0x3 << FSR_VXRM_SHIFT)
	35
	36	/* Vector Fixed-Point saturation flag */
	37	#define FSR_VXSAT_SHIFT 8
	38	#define FSR_VXSAT (0x1 << FSR_VXSAT_SHIFT)
	39
426f0348 MC	40	/* Control and Status Registers */
	41
	42	/* User Trap Setup */
	43	#define CSR_USTATUS 0x000
	44	#define CSR_UIE 0x004
	45	#define CSR_UTVEC 0x005
	46
	47	/* User Trap Handling */
	48	#define CSR_USCRATCH 0x040
	49	#define CSR_UEPC 0x041
	50	#define CSR_UCAUSE 0x042
	51	#define CSR_UTVAL 0x043
	52	#define CSR_UIP 0x044
	53
	54	/* User Floating-Point CSRs */
	55	#define CSR_FFLAGS 0x001
	56	#define CSR_FRM 0x002
	57	#define CSR_FCSR 0x003
	58
8e3a1f18 LZ	59	/* User Vector CSRs */
	60	#define CSR_VSTART 0x008
	61	#define CSR_VXSAT 0x009
	62	#define CSR_VXRM 0x00a
	63	#define CSR_VL 0xc20
	64	#define CSR_VTYPE 0xc21
	65
426f0348 MC	66	/* User Timers and Counters */
	67	#define CSR_CYCLE 0xc00
	68	#define CSR_TIME 0xc01
	69	#define CSR_INSTRET 0xc02
	70	#define CSR_HPMCOUNTER3 0xc03
	71	#define CSR_HPMCOUNTER4 0xc04
	72	#define CSR_HPMCOUNTER5 0xc05
	73	#define CSR_HPMCOUNTER6 0xc06
	74	#define CSR_HPMCOUNTER7 0xc07
	75	#define CSR_HPMCOUNTER8 0xc08
	76	#define CSR_HPMCOUNTER9 0xc09
	77	#define CSR_HPMCOUNTER10 0xc0a
	78	#define CSR_HPMCOUNTER11 0xc0b
	79	#define CSR_HPMCOUNTER12 0xc0c
	80	#define CSR_HPMCOUNTER13 0xc0d
	81	#define CSR_HPMCOUNTER14 0xc0e
	82	#define CSR_HPMCOUNTER15 0xc0f
	83	#define CSR_HPMCOUNTER16 0xc10
	84	#define CSR_HPMCOUNTER17 0xc11
	85	#define CSR_HPMCOUNTER18 0xc12
	86	#define CSR_HPMCOUNTER19 0xc13
	87	#define CSR_HPMCOUNTER20 0xc14
	88	#define CSR_HPMCOUNTER21 0xc15
	89	#define CSR_HPMCOUNTER22 0xc16
	90	#define CSR_HPMCOUNTER23 0xc17
	91	#define CSR_HPMCOUNTER24 0xc18
	92	#define CSR_HPMCOUNTER25 0xc19
	93	#define CSR_HPMCOUNTER26 0xc1a
	94	#define CSR_HPMCOUNTER27 0xc1b
	95	#define CSR_HPMCOUNTER28 0xc1c
	96	#define CSR_HPMCOUNTER29 0xc1d
	97	#define CSR_HPMCOUNTER30 0xc1e
	98	#define CSR_HPMCOUNTER31 0xc1f
	99	#define CSR_CYCLEH 0xc80
	100	#define CSR_TIMEH 0xc81
	101	#define CSR_INSTRETH 0xc82
	102	#define CSR_HPMCOUNTER3H 0xc83
	103	#define CSR_HPMCOUNTER4H 0xc84
	104	#define CSR_HPMCOUNTER5H 0xc85
	105	#define CSR_HPMCOUNTER6H 0xc86
	106	#define CSR_HPMCOUNTER7H 0xc87
	107	#define CSR_HPMCOUNTER8H 0xc88
	108	#define CSR_HPMCOUNTER9H 0xc89
	109	#define CSR_HPMCOUNTER10H 0xc8a
	110	#define CSR_HPMCOUNTER11H 0xc8b
	111	#define CSR_HPMCOUNTER12H 0xc8c
	112	#define CSR_HPMCOUNTER13H 0xc8d
	113	#define CSR_HPMCOUNTER14H 0xc8e
	114	#define CSR_HPMCOUNTER15H 0xc8f
	115	#define CSR_HPMCOUNTER16H 0xc90
	116	#define CSR_HPMCOUNTER17H 0xc91
	117	#define CSR_HPMCOUNTER18H 0xc92
	118	#define CSR_HPMCOUNTER19H 0xc93
	119	#define CSR_HPMCOUNTER20H 0xc94
	120	#define CSR_HPMCOUNTER21H 0xc95
	121	#define CSR_HPMCOUNTER22H 0xc96
	122	#define CSR_HPMCOUNTER23H 0xc97
	123	#define CSR_HPMCOUNTER24H 0xc98
	124	#define CSR_HPMCOUNTER25H 0xc99
	125	#define CSR_HPMCOUNTER26H 0xc9a
	126	#define CSR_HPMCOUNTER27H 0xc9b
	127	#define CSR_HPMCOUNTER28H 0xc9c
	128	#define CSR_HPMCOUNTER29H 0xc9d
	129	#define CSR_HPMCOUNTER30H 0xc9e
130	#define CSR_HPMCOUNTER31H 0xc9f
131
132	/* Machine Timers and Counters */
133	#define CSR_MCYCLE 0xb00
134	#define CSR_MINSTRET 0xb02
135	#define CSR_MCYCLEH 0xb80
136	#define CSR_MINSTRETH 0xb82
137
138	/* Machine Information Registers */
139	#define CSR_MVENDORID 0xf11
140	#define CSR_MARCHID 0xf12
141	#define CSR_MIMPID 0xf13
142	#define CSR_MHARTID 0xf14
143
144	/* Machine Trap Setup */
145	#define CSR_MSTATUS 0x300
146	#define CSR_MISA 0x301
147	#define CSR_MEDELEG 0x302
148	#define CSR_MIDELEG 0x303
149	#define CSR_MIE 0x304
150	#define CSR_MTVEC 0x305
151	#define CSR_MCOUNTEREN 0x306
152
551fa7e8 AF	153	/* 32-bit only */
	154	#define CSR_MSTATUSH 0x310
	155
426f0348 MC	156	/* Machine Trap Handling */
	157	#define CSR_MSCRATCH 0x340
	158	#define CSR_MEPC 0x341
	159	#define CSR_MCAUSE 0x342
8e73df6a	160	#define CSR_MTVAL 0x343
426f0348 MC	161	#define CSR_MIP 0x344
	162
	163	/* Supervisor Trap Setup */
	164	#define CSR_SSTATUS 0x100
8e73df6a JW	165	#define CSR_SEDELEG 0x102
8e73df6a JW	166	#define CSR_SIDELEG 0x103
426f0348 MC	167	#define CSR_SIE 0x104
	168	#define CSR_STVEC 0x105
	169	#define CSR_SCOUNTEREN 0x106
	170
	171	/* Supervisor Trap Handling */
	172	#define CSR_SSCRATCH 0x140
	173	#define CSR_SEPC 0x141
	174	#define CSR_SCAUSE 0x142
8e73df6a	175	#define CSR_STVAL 0x143
426f0348 MC	176	#define CSR_SIP 0x144
	177
	178	/* Supervisor Protection and Translation */
	179	#define CSR_SPTBR 0x180
	180	#define CSR_SATP 0x180
	181
7f8dcfeb AF	182	/* Hpervisor CSRs */
	183	#define CSR_HSTATUS 0x600
	184	#define CSR_HEDELEG 0x602
	185	#define CSR_HIDELEG 0x603
bd023ce3 AF	186	#define CSR_HIE 0x604
bd023ce3 AF	187	#define CSR_HCOUNTEREN 0x606
83028098	188	#define CSR_HGEIE 0x607
bd023ce3	189	#define CSR_HTVAL 0x643
83028098	190	#define CSR_HVIP 0x645
bd023ce3 AF	191	#define CSR_HIP 0x644
bd023ce3 AF	192	#define CSR_HTINST 0x64A
83028098	193	#define CSR_HGEIP 0xE12
7f8dcfeb	194	#define CSR_HGATP 0x680
bd023ce3 AF	195	#define CSR_HTIMEDELTA 0x605
bd023ce3 AF	196	#define CSR_HTIMEDELTAH 0x615
7f8dcfeb	197
bd023ce3 AF	198	/* Virtual CSRs */
	199	#define CSR_VSSTATUS 0x200
	200	#define CSR_VSIE 0x204
	201	#define CSR_VSTVEC 0x205
	202	#define CSR_VSSCRATCH 0x240
	203	#define CSR_VSEPC 0x241
	204	#define CSR_VSCAUSE 0x242
	205	#define CSR_VSTVAL 0x243
	206	#define CSR_VSIP 0x244
	207	#define CSR_VSATP 0x280
	208
	209	#define CSR_MTINST 0x34a
	210	#define CSR_MTVAL2 0x34b
	211
db9f1dac	212	/* Enhanced Physical Memory Protection (ePMP) */
a44da25a AF	213	#define CSR_MSECCFG 0x747
a44da25a AF	214	#define CSR_MSECCFGH 0x757
426f0348 MC	215	/* Physical Memory Protection */
	216	#define CSR_PMPCFG0 0x3a0
	217	#define CSR_PMPCFG1 0x3a1
	218	#define CSR_PMPCFG2 0x3a2
	219	#define CSR_PMPCFG3 0x3a3
	220	#define CSR_PMPADDR0 0x3b0
	221	#define CSR_PMPADDR1 0x3b1
	222	#define CSR_PMPADDR2 0x3b2
	223	#define CSR_PMPADDR3 0x3b3
	224	#define CSR_PMPADDR4 0x3b4
	225	#define CSR_PMPADDR5 0x3b5
	226	#define CSR_PMPADDR6 0x3b6
	227	#define CSR_PMPADDR7 0x3b7
	228	#define CSR_PMPADDR8 0x3b8
	229	#define CSR_PMPADDR9 0x3b9
	230	#define CSR_PMPADDR10 0x3ba
	231	#define CSR_PMPADDR11 0x3bb
	232	#define CSR_PMPADDR12 0x3bc
	233	#define CSR_PMPADDR13 0x3bd
	234	#define CSR_PMPADDR14 0x3be
	235	#define CSR_PMPADDR15 0x3bf
	236
	237	/* Debug/Trace Registers (shared with Debug Mode) */
	238	#define CSR_TSELECT 0x7a0
	239	#define CSR_TDATA1 0x7a1
	240	#define CSR_TDATA2 0x7a2
	241	#define CSR_TDATA3 0x7a3
	242
	243	/* Debug Mode Registers */
	244	#define CSR_DCSR 0x7b0
	245	#define CSR_DPC 0x7b1
	246	#define CSR_DSCRATCH 0x7b2
	247
	248	/* Performance Counters */
	249	#define CSR_MHPMCOUNTER3 0xb03
	250	#define CSR_MHPMCOUNTER4 0xb04
	251	#define CSR_MHPMCOUNTER5 0xb05
	252	#define CSR_MHPMCOUNTER6 0xb06
	253	#define CSR_MHPMCOUNTER7 0xb07
	254	#define CSR_MHPMCOUNTER8 0xb08
	255	#define CSR_MHPMCOUNTER9 0xb09
	256	#define CSR_MHPMCOUNTER10 0xb0a
	257	#define CSR_MHPMCOUNTER11 0xb0b
	258	#define CSR_MHPMCOUNTER12 0xb0c
	259	#define CSR_MHPMCOUNTER13 0xb0d
	260	#define CSR_MHPMCOUNTER14 0xb0e
	261	#define CSR_MHPMCOUNTER15 0xb0f
	262	#define CSR_MHPMCOUNTER16 0xb10
	263	#define CSR_MHPMCOUNTER17 0xb11
	264	#define CSR_MHPMCOUNTER18 0xb12
	265	#define CSR_MHPMCOUNTER19 0xb13
	266	#define CSR_MHPMCOUNTER20 0xb14
	267	#define CSR_MHPMCOUNTER21 0xb15
	268	#define CSR_MHPMCOUNTER22 0xb16
	269	#define CSR_MHPMCOUNTER23 0xb17
	270	#define CSR_MHPMCOUNTER24 0xb18
	271	#define CSR_MHPMCOUNTER25 0xb19
	272	#define CSR_MHPMCOUNTER26 0xb1a
	273	#define CSR_MHPMCOUNTER27 0xb1b
	274	#define CSR_MHPMCOUNTER28 0xb1c
	275	#define CSR_MHPMCOUNTER29 0xb1d
	276	#define CSR_MHPMCOUNTER30 0xb1e
	277	#define CSR_MHPMCOUNTER31 0xb1f
	278	#define CSR_MHPMEVENT3 0x323
279	#define CSR_MHPMEVENT4 0x324
280	#define CSR_MHPMEVENT5 0x325
281	#define CSR_MHPMEVENT6 0x326
282	#define CSR_MHPMEVENT7 0x327
283	#define CSR_MHPMEVENT8 0x328
284	#define CSR_MHPMEVENT9 0x329
285	#define CSR_MHPMEVENT10 0x32a
286	#define CSR_MHPMEVENT11 0x32b
287	#define CSR_MHPMEVENT12 0x32c
288	#define CSR_MHPMEVENT13 0x32d
289	#define CSR_MHPMEVENT14 0x32e
290	#define CSR_MHPMEVENT15 0x32f
291	#define CSR_MHPMEVENT16 0x330
292	#define CSR_MHPMEVENT17 0x331
293	#define CSR_MHPMEVENT18 0x332
294	#define CSR_MHPMEVENT19 0x333
295	#define CSR_MHPMEVENT20 0x334
296	#define CSR_MHPMEVENT21 0x335
297	#define CSR_MHPMEVENT22 0x336
298	#define CSR_MHPMEVENT23 0x337
299	#define CSR_MHPMEVENT24 0x338
300	#define CSR_MHPMEVENT25 0x339
301	#define CSR_MHPMEVENT26 0x33a
302	#define CSR_MHPMEVENT27 0x33b
303	#define CSR_MHPMEVENT28 0x33c
304	#define CSR_MHPMEVENT29 0x33d
305	#define CSR_MHPMEVENT30 0x33e
306	#define CSR_MHPMEVENT31 0x33f
307	#define CSR_MHPMCOUNTER3H 0xb83
308	#define CSR_MHPMCOUNTER4H 0xb84
309	#define CSR_MHPMCOUNTER5H 0xb85
310	#define CSR_MHPMCOUNTER6H 0xb86
311	#define CSR_MHPMCOUNTER7H 0xb87
312	#define CSR_MHPMCOUNTER8H 0xb88
313	#define CSR_MHPMCOUNTER9H 0xb89
314	#define CSR_MHPMCOUNTER10H 0xb8a
315	#define CSR_MHPMCOUNTER11H 0xb8b
316	#define CSR_MHPMCOUNTER12H 0xb8c
317	#define CSR_MHPMCOUNTER13H 0xb8d
318	#define CSR_MHPMCOUNTER14H 0xb8e
319	#define CSR_MHPMCOUNTER15H 0xb8f
320	#define CSR_MHPMCOUNTER16H 0xb90
321	#define CSR_MHPMCOUNTER17H 0xb91
322	#define CSR_MHPMCOUNTER18H 0xb92
323	#define CSR_MHPMCOUNTER19H 0xb93
324	#define CSR_MHPMCOUNTER20H 0xb94
325	#define CSR_MHPMCOUNTER21H 0xb95
326	#define CSR_MHPMCOUNTER22H 0xb96
327	#define CSR_MHPMCOUNTER23H 0xb97
328	#define CSR_MHPMCOUNTER24H 0xb98
329	#define CSR_MHPMCOUNTER25H 0xb99
330	#define CSR_MHPMCOUNTER26H 0xb9a
331	#define CSR_MHPMCOUNTER27H 0xb9b
332	#define CSR_MHPMCOUNTER28H 0xb9c
333	#define CSR_MHPMCOUNTER29H 0xb9d
334	#define CSR_MHPMCOUNTER30H 0xb9e
335	#define CSR_MHPMCOUNTER31H 0xb9f
336
138b5c5f AB	337	/*
	338	* User PointerMasking registers
	339	* NB: actual CSR numbers might be changed in future
	340	*/
	341	#define CSR_UMTE 0x4c0
	342	#define CSR_UPMMASK 0x4c1
	343	#define CSR_UPMBASE 0x4c2
	344
	345	/*
	346	* Machine PointerMasking registers
	347	* NB: actual CSR numbers might be changed in future
	348	*/
	349	#define CSR_MMTE 0x3c0
	350	#define CSR_MPMMASK 0x3c1
	351	#define CSR_MPMBASE 0x3c2
	352
	353	/*
	354	* Supervisor PointerMaster registers
	355	* NB: actual CSR numbers might be changed in future
	356	*/
	357	#define CSR_SMTE 0x1c0
	358	#define CSR_SPMMASK 0x1c1
	359	#define CSR_SPMBASE 0x1c2
	360
	361	/*
	362	* Hypervisor PointerMaster registers
	363	* NB: actual CSR numbers might be changed in future
	364	*/
	365	#define CSR_VSMTE 0x2c0
	366	#define CSR_VSPMMASK 0x2c1
	367	#define CSR_VSPMBASE 0x2c2
	368
426f0348	369	/* mstatus CSR bits */
dc5bd18f MC	370	#define MSTATUS_UIE 0x00000001
dc5bd18f MC	371	#define MSTATUS_SIE 0x00000002
dc5bd18f MC	372	#define MSTATUS_MIE 0x00000008
	373	#define MSTATUS_UPIE 0x00000010
	374	#define MSTATUS_SPIE 0x00000020
43a96588	375	#define MSTATUS_UBE 0x00000040
dc5bd18f MC	376	#define MSTATUS_MPIE 0x00000080
dc5bd18f MC	377	#define MSTATUS_SPP 0x00000100
61b4b69d	378	#define MSTATUS_VS 0x00000600
dc5bd18f MC	379	#define MSTATUS_MPP 0x00001800
	380	#define MSTATUS_FS 0x00006000
	381	#define MSTATUS_XS 0x00018000
	382	#define MSTATUS_MPRV 0x00020000
dc5bd18f MC	383	#define MSTATUS_SUM 0x00040000 /* since: priv-1.10 */
dc5bd18f MC	384	#define MSTATUS_MXR 0x00080000
dc5bd18f	385	#define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */
52957745 AR	386	#define MSTATUS_TW 0x00200000 /* since: priv-1.10 */
52957745 AR	387	#define MSTATUS_TSR 0x00400000 /* since: priv-1.10 */
9034e90a	388	#define MSTATUS_GVA 0x4000000000ULL
49aaa3e5	389	#define MSTATUS_MPV 0x8000000000ULL
dc5bd18f MC	390
	391	#define MSTATUS64_UXL 0x0000000300000000ULL
	392	#define MSTATUS64_SXL 0x0000000C00000000ULL
	393
	394	#define MSTATUS32_SD 0x80000000
	395	#define MSTATUS64_SD 0x8000000000000000ULL
	396
f18637cd MC	397	#define MISA32_MXL 0xC0000000
	398	#define MISA64_MXL 0xC000000000000000ULL
	399
99bc874f RH	400	typedef enum {
	401	MXL_RV32 = 1,
	402	MXL_RV64 = 2,
	403	MXL_RV128 = 3,
	404	} RISCVMXL;
f18637cd	405
426f0348	406	/* sstatus CSR bits */
dc5bd18f MC	407	#define SSTATUS_UIE 0x00000001
	408	#define SSTATUS_SIE 0x00000002
	409	#define SSTATUS_UPIE 0x00000010
	410	#define SSTATUS_SPIE 0x00000020
	411	#define SSTATUS_SPP 0x00000100
89a81e37	412	#define SSTATUS_VS 0x00000600
dc5bd18f MC	413	#define SSTATUS_FS 0x00006000
dc5bd18f MC	414	#define SSTATUS_XS 0x00018000
dc5bd18f MC	415	#define SSTATUS_SUM 0x00040000 /* since: priv-1.10 */
	416	#define SSTATUS_MXR 0x00080000
	417
	418	#define SSTATUS32_SD 0x80000000
	419	#define SSTATUS64_SD 0x8000000000000000ULL
	420
d28b15a4	421	/* hstatus CSR bits */
543ba531 AF	422	#define HSTATUS_VSBE 0x00000020
543ba531 AF	423	#define HSTATUS_GVA 0x00000040
d28b15a4	424	#define HSTATUS_SPV 0x00000080
543ba531 AF	425	#define HSTATUS_SPVP 0x00000100
	426	#define HSTATUS_HU 0x00000200
	427	#define HSTATUS_VGEIN 0x0003F000
d28b15a4	428	#define HSTATUS_VTVM 0x00100000
719f0f60	429	#define HSTATUS_VTW 0x00200000
d28b15a4	430	#define HSTATUS_VTSR 0x00400000
8987cdc4	431	#define HSTATUS_VSXL 0x300000000
d28b15a4 AF	432
	433	#define HSTATUS32_WPRI 0xFF8FF87E
	434	#define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL
	435
db70794e BM	436	#define COUNTEREN_CY (1 << 0)
	437	#define COUNTEREN_TM (1 << 1)
	438	#define COUNTEREN_IR (1 << 2)
	439	#define COUNTEREN_HPM3 (1 << 3)
e39a8320	440
426f0348	441	/* Privilege modes */
dc5bd18f MC	442	#define PRV_U 0
dc5bd18f MC	443	#define PRV_S 1
356d7419	444	#define PRV_H 2 /* Reserved */
dc5bd18f MC	445	#define PRV_M 3
dc5bd18f MC	446
ef6bb7b6 AF	447	/* Virtulisation Register Fields */
	448	#define VIRT_ONOFF 1
	449
426f0348 MC	450	/* RV32 satp CSR field masks */
	451	#define SATP32_MODE 0x80000000
	452	#define SATP32_ASID 0x7fc00000
	453	#define SATP32_PPN 0x003fffff
	454
	455	/* RV64 satp CSR field masks */
	456	#define SATP64_MODE 0xF000000000000000ULL
	457	#define SATP64_ASID 0x0FFFF00000000000ULL
	458	#define SATP64_PPN 0x00000FFFFFFFFFFFULL
dc5bd18f	459
426f0348 MC	460	/* VM modes (satp.mode) privileged ISA 1.10 */
	461	#define VM_1_10_MBARE 0
	462	#define VM_1_10_SV32 1
	463	#define VM_1_10_SV39 8
	464	#define VM_1_10_SV48 9
	465	#define VM_1_10_SV57 10
	466	#define VM_1_10_SV64 11
	467
	468	/* Page table entry (PTE) fields */
	469	#define PTE_V 0x001 /* Valid */
	470	#define PTE_R 0x002 /* Read */
	471	#define PTE_W 0x004 /* Write */
	472	#define PTE_X 0x008 /* Execute */
	473	#define PTE_U 0x010 /* User */
	474	#define PTE_G 0x020 /* Global */
	475	#define PTE_A 0x040 /* Accessed */
	476	#define PTE_D 0x080 /* Dirty */
	477	#define PTE_SOFT 0x300 /* Reserved for Software */
	478
	479	/* Page table PPN shift amount */
	480	#define PTE_PPN_SHIFT 10
	481
	482	/* Leaf page shift amount */
	483	#define PGSHIFT 12
	484
	485	/* Default Reset Vector adress */
	486	#define DEFAULT_RSTVEC 0x1000
	487
	488	/* Exception causes */
330d2ae3 AF	489	typedef enum RISCVException {
	490	RISCV_EXCP_NONE = -1, /* sentinel value */
	491	RISCV_EXCP_INST_ADDR_MIS = 0x0,
	492	RISCV_EXCP_INST_ACCESS_FAULT = 0x1,
	493	RISCV_EXCP_ILLEGAL_INST = 0x2,
	494	RISCV_EXCP_BREAKPOINT = 0x3,
	495	RISCV_EXCP_LOAD_ADDR_MIS = 0x4,
	496	RISCV_EXCP_LOAD_ACCESS_FAULT = 0x5,
	497	RISCV_EXCP_STORE_AMO_ADDR_MIS = 0x6,
	498	RISCV_EXCP_STORE_AMO_ACCESS_FAULT = 0x7,
	499	RISCV_EXCP_U_ECALL = 0x8,
	500	RISCV_EXCP_S_ECALL = 0x9,
	501	RISCV_EXCP_VS_ECALL = 0xa,
	502	RISCV_EXCP_M_ECALL = 0xb,
	503	RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
	504	RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
	505	RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
	506	RISCV_EXCP_SEMIHOST = 0x10,
	507	RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
	508	RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
	509	RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
	510	RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
	511	} RISCVException;
dc5bd18f MC	512
	513	#define RISCV_EXCP_INT_FLAG 0x80000000
	514	#define RISCV_EXCP_INT_MASK 0x7fffffff
	515
426f0348 MC	516	/* Interrupt causes */
	517	#define IRQ_U_SOFT 0
	518	#define IRQ_S_SOFT 1
205377f8	519	#define IRQ_VS_SOFT 2
426f0348 MC	520	#define IRQ_M_SOFT 3
	521	#define IRQ_U_TIMER 4
	522	#define IRQ_S_TIMER 5
205377f8	523	#define IRQ_VS_TIMER 6
426f0348 MC	524	#define IRQ_M_TIMER 7
	525	#define IRQ_U_EXT 8
	526	#define IRQ_S_EXT 9
205377f8	527	#define IRQ_VS_EXT 10
426f0348 MC	528	#define IRQ_M_EXT 11
	529
	530	/* mip masks */
	531	#define MIP_USIP (1 << IRQ_U_SOFT)
	532	#define MIP_SSIP (1 << IRQ_S_SOFT)
205377f8	533	#define MIP_VSSIP (1 << IRQ_VS_SOFT)
426f0348 MC	534	#define MIP_MSIP (1 << IRQ_M_SOFT)
	535	#define MIP_UTIP (1 << IRQ_U_TIMER)
	536	#define MIP_STIP (1 << IRQ_S_TIMER)
205377f8	537	#define MIP_VSTIP (1 << IRQ_VS_TIMER)
426f0348 MC	538	#define MIP_MTIP (1 << IRQ_M_TIMER)
	539	#define MIP_UEIP (1 << IRQ_U_EXT)
	540	#define MIP_SEIP (1 << IRQ_S_EXT)
205377f8	541	#define MIP_VSEIP (1 << IRQ_VS_EXT)
426f0348 MC	542	#define MIP_MEIP (1 << IRQ_M_EXT)
	543
	544	/* sip masks */
	545	#define SIP_SSIP MIP_SSIP
	546	#define SIP_STIP MIP_STIP
	547	#define SIP_SEIP MIP_SEIP
f91005e1	548
66e594f2 AF	549	/* MIE masks */
	550	#define MIE_SEIE (1 << IRQ_S_EXT)
	551	#define MIE_UEIE (1 << IRQ_U_EXT)
	552	#define MIE_STIE (1 << IRQ_S_TIMER)
	553	#define MIE_UTIE (1 << IRQ_U_TIMER)
	554	#define MIE_SSIE (1 << IRQ_S_SOFT)
	555	#define MIE_USIE (1 << IRQ_U_SOFT)
138b5c5f AB	556
	557	/* General PointerMasking CSR bits*/
	558	#define PM_ENABLE 0x00000001ULL
	559	#define PM_CURRENT 0x00000002ULL
	560	#define PM_INSN 0x00000004ULL
	561	#define PM_XS_MASK 0x00000003ULL
	562
	563	/* PointerMasking XS bits values */
	564	#define PM_EXT_DISABLE 0x00000000ULL
	565	#define PM_EXT_INITIAL 0x00000001ULL
	566	#define PM_EXT_CLEAN 0x00000002ULL
	567	#define PM_EXT_DIRTY 0x00000003ULL
	568
	569	/* Offsets for every pair of control bits per each priv level */
	570	#define XS_OFFSET 0ULL
	571	#define U_OFFSET 2ULL
	572	#define S_OFFSET 5ULL
	573	#define M_OFFSET 8ULL
	574
	575	#define PM_XS_BITS (PM_XS_MASK << XS_OFFSET)
	576	#define U_PM_ENABLE (PM_ENABLE << U_OFFSET)
	577	#define U_PM_CURRENT (PM_CURRENT << U_OFFSET)
	578	#define U_PM_INSN (PM_INSN << U_OFFSET)
	579	#define S_PM_ENABLE (PM_ENABLE << S_OFFSET)
	580	#define S_PM_CURRENT (PM_CURRENT << S_OFFSET)
	581	#define S_PM_INSN (PM_INSN << S_OFFSET)
	582	#define M_PM_ENABLE (PM_ENABLE << M_OFFSET)
	583	#define M_PM_CURRENT (PM_CURRENT << M_OFFSET)
	584	#define M_PM_INSN (PM_INSN << M_OFFSET)
	585
	586	/* mmte CSR bits */
	587	#define MMTE_PM_XS_BITS PM_XS_BITS
	588	#define MMTE_U_PM_ENABLE U_PM_ENABLE
	589	#define MMTE_U_PM_CURRENT U_PM_CURRENT
	590	#define MMTE_U_PM_INSN U_PM_INSN
	591	#define MMTE_S_PM_ENABLE S_PM_ENABLE
	592	#define MMTE_S_PM_CURRENT S_PM_CURRENT
	593	#define MMTE_S_PM_INSN S_PM_INSN
	594	#define MMTE_M_PM_ENABLE M_PM_ENABLE
	595	#define MMTE_M_PM_CURRENT M_PM_CURRENT
	596	#define MMTE_M_PM_INSN M_PM_INSN
	597	#define MMTE_MASK (MMTE_U_PM_ENABLE \| MMTE_U_PM_CURRENT \| MMTE_U_PM_INSN \| \
	598	MMTE_S_PM_ENABLE \| MMTE_S_PM_CURRENT \| MMTE_S_PM_INSN \| \
	599	MMTE_M_PM_ENABLE \| MMTE_M_PM_CURRENT \| MMTE_M_PM_INSN \| \
	600	MMTE_PM_XS_BITS)
	601
	602	/* (v)smte CSR bits */
	603	#define SMTE_PM_XS_BITS PM_XS_BITS
	604	#define SMTE_U_PM_ENABLE U_PM_ENABLE
	605	#define SMTE_U_PM_CURRENT U_PM_CURRENT
	606	#define SMTE_U_PM_INSN U_PM_INSN
	607	#define SMTE_S_PM_ENABLE S_PM_ENABLE
	608	#define SMTE_S_PM_CURRENT S_PM_CURRENT
	609	#define SMTE_S_PM_INSN S_PM_INSN
	610	#define SMTE_MASK (SMTE_U_PM_ENABLE \| SMTE_U_PM_CURRENT \| SMTE_U_PM_INSN \| \
	611	SMTE_S_PM_ENABLE \| SMTE_S_PM_CURRENT \| SMTE_S_PM_INSN \| \
	612	SMTE_PM_XS_BITS)
	613
	614	/* umte CSR bits */
	615	#define UMTE_U_PM_ENABLE U_PM_ENABLE
	616	#define UMTE_U_PM_CURRENT U_PM_CURRENT
	617	#define UMTE_U_PM_INSN U_PM_INSN
	618	#define UMTE_MASK (UMTE_U_PM_ENABLE \| MMTE_U_PM_CURRENT \| UMTE_U_PM_INSN)
	619
f91005e1	620	#endif