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b902ff29 WL |
1 | /* |
2 | * QEMU RISC-V CPU CFG | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * Copyright (c) 2021-2023 PLCT Lab | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms and conditions of the GNU General Public License, | |
10 | * version 2 or later, as published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
21 | #ifndef RISCV_CPU_CFG_H | |
22 | #define RISCV_CPU_CFG_H | |
23 | ||
24 | /* | |
25 | * map is a 16-bit bitmap: the most significant set bit in map is the maximum | |
26 | * satp mode that is supported. It may be chosen by the user and must respect | |
27 | * what qemu implements (valid_1_10_32/64) and what the hw is capable of | |
28 | * (supported bitmap below). | |
29 | * | |
30 | * init is a 16-bit bitmap used to make sure the user selected a correct | |
31 | * configuration as per the specification. | |
32 | * | |
33 | * supported is a 16-bit bitmap used to reflect the hw capabilities. | |
34 | */ | |
35 | typedef struct { | |
36 | uint16_t map, init, supported; | |
37 | } RISCVSATPMap; | |
38 | ||
39 | struct RISCVCPUConfig { | |
40 | bool ext_zba; | |
41 | bool ext_zbb; | |
42 | bool ext_zbc; | |
43 | bool ext_zbkb; | |
44 | bool ext_zbkc; | |
45 | bool ext_zbkx; | |
46 | bool ext_zbs; | |
47 | bool ext_zca; | |
48 | bool ext_zcb; | |
49 | bool ext_zcd; | |
50 | bool ext_zce; | |
51 | bool ext_zcf; | |
52 | bool ext_zcmp; | |
53 | bool ext_zcmt; | |
54 | bool ext_zk; | |
55 | bool ext_zkn; | |
56 | bool ext_zknd; | |
57 | bool ext_zkne; | |
58 | bool ext_zknh; | |
59 | bool ext_zkr; | |
60 | bool ext_zks; | |
61 | bool ext_zksed; | |
62 | bool ext_zksh; | |
63 | bool ext_zkt; | |
64 | bool ext_ifencei; | |
65 | bool ext_icsr; | |
66 | bool ext_icbom; | |
67 | bool ext_icboz; | |
68 | bool ext_zicond; | |
69 | bool ext_zihintpause; | |
70 | bool ext_smstateen; | |
71 | bool ext_sstc; | |
72 | bool ext_svadu; | |
73 | bool ext_svinval; | |
74 | bool ext_svnapot; | |
75 | bool ext_svpbmt; | |
76 | bool ext_zdinx; | |
77 | bool ext_zawrs; | |
a47842d1 | 78 | bool ext_zfa; |
4556fdaa | 79 | bool ext_zfbfmin; |
b902ff29 WL |
80 | bool ext_zfh; |
81 | bool ext_zfhmin; | |
82 | bool ext_zfinx; | |
83 | bool ext_zhinx; | |
84 | bool ext_zhinxmin; | |
85 | bool ext_zve32f; | |
86 | bool ext_zve64f; | |
87 | bool ext_zve64d; | |
06028472 | 88 | bool ext_zvbb; |
e13c7d3b | 89 | bool ext_zvbc; |
e972bf22 | 90 | bool ext_zvkned; |
fcf19433 KO |
91 | bool ext_zvknha; |
92 | bool ext_zvknhb; | |
b902ff29 | 93 | bool ext_zmmul; |
4556fdaa WL |
94 | bool ext_zvfbfmin; |
95 | bool ext_zvfbfwma; | |
b902ff29 WL |
96 | bool ext_zvfh; |
97 | bool ext_zvfhmin; | |
98 | bool ext_smaia; | |
99 | bool ext_ssaia; | |
100 | bool ext_sscofpmf; | |
101 | bool rvv_ta_all_1s; | |
102 | bool rvv_ma_all_1s; | |
103 | ||
104 | uint32_t mvendorid; | |
105 | uint64_t marchid; | |
106 | uint64_t mimpid; | |
107 | ||
108 | /* Vendor-specific custom extensions */ | |
109 | bool ext_xtheadba; | |
110 | bool ext_xtheadbb; | |
111 | bool ext_xtheadbs; | |
112 | bool ext_xtheadcmo; | |
113 | bool ext_xtheadcondmov; | |
114 | bool ext_xtheadfmemidx; | |
115 | bool ext_xtheadfmv; | |
116 | bool ext_xtheadmac; | |
117 | bool ext_xtheadmemidx; | |
118 | bool ext_xtheadmempair; | |
119 | bool ext_xtheadsync; | |
120 | bool ext_XVentanaCondOps; | |
121 | ||
122 | uint8_t pmu_num; | |
123 | char *priv_spec; | |
124 | char *user_spec; | |
125 | char *bext_spec; | |
126 | char *vext_spec; | |
127 | uint16_t vlen; | |
128 | uint16_t elen; | |
129 | uint16_t cbom_blocksize; | |
130 | uint16_t cboz_blocksize; | |
131 | bool mmu; | |
132 | bool pmp; | |
133 | bool epmp; | |
134 | bool debug; | |
135 | bool misa_w; | |
136 | ||
137 | bool short_isa_string; | |
138 | ||
139 | #ifndef CONFIG_USER_ONLY | |
140 | RISCVSATPMap satp_mode; | |
141 | #endif | |
142 | }; | |
143 | ||
144 | typedef struct RISCVCPUConfig RISCVCPUConfig; | |
2e8c1e02 CM |
145 | |
146 | /* Helper functions to test for extensions. */ | |
147 | ||
148 | static inline bool always_true_p(const RISCVCPUConfig *cfg __attribute__((__unused__))) | |
149 | { | |
150 | return true; | |
151 | } | |
152 | ||
153 | static inline bool has_xthead_p(const RISCVCPUConfig *cfg) | |
154 | { | |
155 | return cfg->ext_xtheadba || cfg->ext_xtheadbb || | |
156 | cfg->ext_xtheadbs || cfg->ext_xtheadcmo || | |
157 | cfg->ext_xtheadcondmov || | |
158 | cfg->ext_xtheadfmemidx || cfg->ext_xtheadfmv || | |
159 | cfg->ext_xtheadmac || cfg->ext_xtheadmemidx || | |
160 | cfg->ext_xtheadmempair || cfg->ext_xtheadsync; | |
161 | } | |
162 | ||
163 | #define MATERIALISE_EXT_PREDICATE(ext) \ | |
164 | static inline bool has_ ## ext ## _p(const RISCVCPUConfig *cfg) \ | |
165 | { \ | |
166 | return cfg->ext_ ## ext ; \ | |
167 | } | |
168 | ||
318df723 CM |
169 | MATERIALISE_EXT_PREDICATE(xtheadba) |
170 | MATERIALISE_EXT_PREDICATE(xtheadbb) | |
171 | MATERIALISE_EXT_PREDICATE(xtheadbs) | |
172 | MATERIALISE_EXT_PREDICATE(xtheadcmo) | |
173 | MATERIALISE_EXT_PREDICATE(xtheadcondmov) | |
174 | MATERIALISE_EXT_PREDICATE(xtheadfmemidx) | |
175 | MATERIALISE_EXT_PREDICATE(xtheadfmv) | |
176 | MATERIALISE_EXT_PREDICATE(xtheadmac) | |
177 | MATERIALISE_EXT_PREDICATE(xtheadmemidx) | |
178 | MATERIALISE_EXT_PREDICATE(xtheadmempair) | |
179 | MATERIALISE_EXT_PREDICATE(xtheadsync) | |
2e8c1e02 CM |
180 | MATERIALISE_EXT_PREDICATE(XVentanaCondOps) |
181 | ||
b902ff29 | 182 | #endif |