[mirror_qemu.git] / target / riscv / cpu_cfg.h

/*
 * QEMU RISC-V CPU CFG
 *
 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
 * Copyright (c) 2017-2018 SiFive, Inc.
 * Copyright (c) 2021-2023 PLCT Lab
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2 or later, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef RISCV_CPU_CFG_H
#define RISCV_CPU_CFG_H

/*
 * map is a 16-bit bitmap: the most significant set bit in map is the maximum
 * satp mode that is supported. It may be chosen by the user and must respect
 * what qemu implements (valid_1_10_32/64) and what the hw is capable of
 * (supported bitmap below).
 *
 * init is a 16-bit bitmap used to make sure the user selected a correct
 * configuration as per the specification.
 *
 * supported is a 16-bit bitmap used to reflect the hw capabilities.
 */
typedef struct {
    uint16_t map, init, supported;
} RISCVSATPMap;

struct RISCVCPUConfig {
    bool ext_zba;
    bool ext_zbb;
    bool ext_zbc;
    bool ext_zbkb;
    bool ext_zbkc;
    bool ext_zbkx;
    bool ext_zbs;
    bool ext_zca;
    bool ext_zcb;
    bool ext_zcd;
    bool ext_zce;
    bool ext_zcf;
    bool ext_zcmp;
    bool ext_zcmt;
    bool ext_zk;
    bool ext_zkn;
    bool ext_zknd;
    bool ext_zkne;
    bool ext_zknh;
    bool ext_zkr;
    bool ext_zks;
    bool ext_zksed;
    bool ext_zksh;
    bool ext_zkt;
    bool ext_zifencei;
    bool ext_zicntr;
    bool ext_zicsr;
    bool ext_zicbom;
    bool ext_zicbop;
    bool ext_zicboz;
    bool ext_zicond;
    bool ext_zihintntl;
    bool ext_zihintpause;
    bool ext_zihpm;
    bool ext_ztso;
    bool ext_smstateen;
    bool ext_sstc;
    bool ext_svadu;
    bool ext_svinval;
    bool ext_svnapot;
    bool ext_svpbmt;
    bool ext_zdinx;
    bool ext_zaamo;
    bool ext_zacas;
    bool ext_zalrsc;
    bool ext_zawrs;
    bool ext_zfa;
    bool ext_zfbfmin;
    bool ext_zfh;
    bool ext_zfhmin;
    bool ext_zfinx;
    bool ext_zhinx;
    bool ext_zhinxmin;
    bool ext_zve32f;
    bool ext_zve64f;
    bool ext_zve64d;
    bool ext_zvbb;
    bool ext_zvbc;
    bool ext_zvkb;
    bool ext_zvkg;
    bool ext_zvkned;
    bool ext_zvknha;
    bool ext_zvknhb;
    bool ext_zvksed;
    bool ext_zvksh;
    bool ext_zvkt;
    bool ext_zvkn;
    bool ext_zvknc;
    bool ext_zvkng;
    bool ext_zvks;
    bool ext_zvksc;
    bool ext_zvksg;
    bool ext_zmmul;
    bool ext_zvfbfmin;
    bool ext_zvfbfwma;
    bool ext_zvfh;
    bool ext_zvfhmin;
    bool ext_smaia;
    bool ext_ssaia;
    bool ext_sscofpmf;
    bool ext_smepmp;
    bool rvv_ta_all_1s;
    bool rvv_ma_all_1s;

    uint32_t mvendorid;
    uint64_t marchid;
    uint64_t mimpid;

    /* Named features  */
    bool ext_svade;
    bool ext_zic64b;

    /*
     * Always 'true' booleans for named features
     * TCG always implement/can't be user disabled,
     * based on spec version.
     */
    bool has_priv_1_12;
    bool has_priv_1_11;

    /* Vendor-specific custom extensions */
    bool ext_xtheadba;
    bool ext_xtheadbb;
    bool ext_xtheadbs;
    bool ext_xtheadcmo;
    bool ext_xtheadcondmov;
    bool ext_xtheadfmemidx;
    bool ext_xtheadfmv;
    bool ext_xtheadmac;
    bool ext_xtheadmemidx;
    bool ext_xtheadmempair;
    bool ext_xtheadsync;
    bool ext_XVentanaCondOps;

    uint32_t pmu_mask;
    uint16_t vlenb;
    uint16_t elen;
    uint16_t cbom_blocksize;
    uint16_t cbop_blocksize;
    uint16_t cboz_blocksize;
    bool mmu;
    bool pmp;
    bool debug;
    bool misa_w;

    bool short_isa_string;

#ifndef CONFIG_USER_ONLY
    RISCVSATPMap satp_mode;
#endif
};

typedef struct RISCVCPUConfig RISCVCPUConfig;

/* Helper functions to test for extensions.  */

static inline bool always_true_p(const RISCVCPUConfig *cfg __attribute__((__unused__)))
{
    return true;
}

static inline bool has_xthead_p(const RISCVCPUConfig *cfg)
{
    return cfg->ext_xtheadba || cfg->ext_xtheadbb ||
           cfg->ext_xtheadbs || cfg->ext_xtheadcmo ||
           cfg->ext_xtheadcondmov ||
           cfg->ext_xtheadfmemidx || cfg->ext_xtheadfmv ||
           cfg->ext_xtheadmac || cfg->ext_xtheadmemidx ||
           cfg->ext_xtheadmempair || cfg->ext_xtheadsync;
}

#define MATERIALISE_EXT_PREDICATE(ext) \
    static inline bool has_ ## ext ## _p(const RISCVCPUConfig *cfg) \
    { \
        return cfg->ext_ ## ext ; \
    }

MATERIALISE_EXT_PREDICATE(xtheadba)
MATERIALISE_EXT_PREDICATE(xtheadbb)
MATERIALISE_EXT_PREDICATE(xtheadbs)
MATERIALISE_EXT_PREDICATE(xtheadcmo)
MATERIALISE_EXT_PREDICATE(xtheadcondmov)
MATERIALISE_EXT_PREDICATE(xtheadfmemidx)
MATERIALISE_EXT_PREDICATE(xtheadfmv)
MATERIALISE_EXT_PREDICATE(xtheadmac)
MATERIALISE_EXT_PREDICATE(xtheadmemidx)
MATERIALISE_EXT_PREDICATE(xtheadmempair)
MATERIALISE_EXT_PREDICATE(xtheadsync)
MATERIALISE_EXT_PREDICATE(XVentanaCondOps)

#endif
Commit	Line	Data
b902ff29 WL	1	/*
	2	* QEMU RISC-V CPU CFG
	3	*
	4	* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
	5	* Copyright (c) 2017-2018 SiFive, Inc.
	6	* Copyright (c) 2021-2023 PLCT Lab
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms and conditions of the GNU General Public License,
	10	* version 2 or later, as published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	15	* more details.
	16	*
	17	* You should have received a copy of the GNU General Public License along with
	18	* this program. If not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
	21	#ifndef RISCV_CPU_CFG_H
	22	#define RISCV_CPU_CFG_H
	23
	24	/*
	25	* map is a 16-bit bitmap: the most significant set bit in map is the maximum
	26	* satp mode that is supported. It may be chosen by the user and must respect
	27	* what qemu implements (valid_1_10_32/64) and what the hw is capable of
	28	* (supported bitmap below).
	29	*
	30	* init is a 16-bit bitmap used to make sure the user selected a correct
	31	* configuration as per the specification.
	32	*
	33	* supported is a 16-bit bitmap used to reflect the hw capabilities.
	34	*/
	35	typedef struct {
	36	uint16_t map, init, supported;
	37	} RISCVSATPMap;
	38
	39	struct RISCVCPUConfig {
	40	bool ext_zba;
	41	bool ext_zbb;
	42	bool ext_zbc;
	43	bool ext_zbkb;
	44	bool ext_zbkc;
	45	bool ext_zbkx;
	46	bool ext_zbs;
	47	bool ext_zca;
	48	bool ext_zcb;
	49	bool ext_zcd;
	50	bool ext_zce;
	51	bool ext_zcf;
	52	bool ext_zcmp;
	53	bool ext_zcmt;
	54	bool ext_zk;
	55	bool ext_zkn;
	56	bool ext_zknd;
	57	bool ext_zkne;
	58	bool ext_zknh;
	59	bool ext_zkr;
	60	bool ext_zks;
	61	bool ext_zksed;
	62	bool ext_zksh;
	63	bool ext_zkt;
12b12a14	64	bool ext_zifencei;
c0040993	65	bool ext_zicntr;
960b389b	66	bool ext_zicsr;
a326a2b0	67	bool ext_zicbom;
cc2bf69a	68	bool ext_zicbop;
e57039dd	69	bool ext_zicboz;
b902ff29	70	bool ext_zicond;
0228aca2	71	bool ext_zihintntl;
b902ff29	72	bool ext_zihintpause;
08241216	73	bool ext_zihpm;
09c4e887	74	bool ext_ztso;
b902ff29 WL	75	bool ext_smstateen;
	76	bool ext_sstc;
	77	bool ext_svadu;
	78	bool ext_svinval;
	79	bool ext_svnapot;
	80	bool ext_svpbmt;
	81	bool ext_zdinx;
8caeda5b	82	bool ext_zaamo;
b52d49e9	83	bool ext_zacas;
8caeda5b	84	bool ext_zalrsc;
b902ff29	85	bool ext_zawrs;
a47842d1	86	bool ext_zfa;
4556fdaa	87	bool ext_zfbfmin;
b902ff29 WL	88	bool ext_zfh;
	89	bool ext_zfhmin;
	90	bool ext_zfinx;
	91	bool ext_zhinx;
	92	bool ext_zhinxmin;
	93	bool ext_zve32f;
	94	bool ext_zve64f;
	95	bool ext_zve64d;
06028472	96	bool ext_zvbb;
e13c7d3b	97	bool ext_zvbc;
389b2e70	98	bool ext_zvkb;
767eb035	99	bool ext_zvkg;
e972bf22	100	bool ext_zvkned;
fcf19433 KO	101	bool ext_zvknha;
fcf19433 KO	102	bool ext_zvknhb;
8b045ff4	103	bool ext_zvksed;
2350881c	104	bool ext_zvksh;
5ddbc83f	105	bool ext_zvkt;
7cdc8ddb MC	106	bool ext_zvkn;
	107	bool ext_zvknc;
	108	bool ext_zvkng;
8f913d10 MC	109	bool ext_zvks;
	110	bool ext_zvksc;
	111	bool ext_zvksg;
b902ff29	112	bool ext_zmmul;
4556fdaa WL	113	bool ext_zvfbfmin;
4556fdaa WL	114	bool ext_zvfbfwma;
b902ff29 WL	115	bool ext_zvfh;
	116	bool ext_zvfhmin;
	117	bool ext_smaia;
	118	bool ext_ssaia;
	119	bool ext_sscofpmf;
095fe72a	120	bool ext_smepmp;
b902ff29 WL	121	bool rvv_ta_all_1s;
	122	bool rvv_ma_all_1s;
	123
	124	uint32_t mvendorid;
	125	uint64_t marchid;
	126	uint64_t mimpid;
	127
3b802226 DHB	128	/* Named features */
	129	bool ext_svade;
	130	bool ext_zic64b;
	131
a0952c15	132	/*
68c9e54b DHB	133	* Always 'true' booleans for named features
	134	* TCG always implement/can't be user disabled,
	135	* based on spec version.
a0952c15	136	*/
68c9e54b DHB	137	bool has_priv_1_12;
68c9e54b DHB	138	bool has_priv_1_11;
a0952c15	139
b902ff29 WL	140	/* Vendor-specific custom extensions */
	141	bool ext_xtheadba;
	142	bool ext_xtheadbb;
	143	bool ext_xtheadbs;
	144	bool ext_xtheadcmo;
	145	bool ext_xtheadcondmov;
	146	bool ext_xtheadfmemidx;
	147	bool ext_xtheadfmv;
	148	bool ext_xtheadmac;
	149	bool ext_xtheadmemidx;
	150	bool ext_xtheadmempair;
	151	bool ext_xtheadsync;
	152	bool ext_XVentanaCondOps;
	153
69b3849b	154	uint32_t pmu_mask;
04eb30a0	155	uint16_t vlenb;
b902ff29 WL	156	uint16_t elen;
b902ff29 WL	157	uint16_t cbom_blocksize;
cc2bf69a	158	uint16_t cbop_blocksize;
b902ff29 WL	159	uint16_t cboz_blocksize;
	160	bool mmu;
	161	bool pmp;
b902ff29 WL	162	bool debug;
	163	bool misa_w;
	164
	165	bool short_isa_string;
	166
	167	#ifndef CONFIG_USER_ONLY
	168	RISCVSATPMap satp_mode;
	169	#endif
	170	};
	171
	172	typedef struct RISCVCPUConfig RISCVCPUConfig;
2e8c1e02 CM	173
	174	/* Helper functions to test for extensions. */
	175
	176	static inline bool always_true_p(const RISCVCPUConfig *cfg __attribute__((__unused__)))
	177	{
	178	return true;
	179	}
	180
	181	static inline bool has_xthead_p(const RISCVCPUConfig *cfg)
	182	{
	183	return cfg->ext_xtheadba \|\| cfg->ext_xtheadbb \|\|
	184	cfg->ext_xtheadbs \|\| cfg->ext_xtheadcmo \|\|
	185	cfg->ext_xtheadcondmov \|\|
	186	cfg->ext_xtheadfmemidx \|\| cfg->ext_xtheadfmv \|\|
	187	cfg->ext_xtheadmac \|\| cfg->ext_xtheadmemidx \|\|
	188	cfg->ext_xtheadmempair \|\| cfg->ext_xtheadsync;
	189	}
	190
	191	#define MATERIALISE_EXT_PREDICATE(ext) \
	192	static inline bool has_ ## ext ## _p(const RISCVCPUConfig *cfg) \
	193	{ \
	194	return cfg->ext_ ## ext ; \
	195	}
	196
318df723 CM	197	MATERIALISE_EXT_PREDICATE(xtheadba)
	198	MATERIALISE_EXT_PREDICATE(xtheadbb)
	199	MATERIALISE_EXT_PREDICATE(xtheadbs)
	200	MATERIALISE_EXT_PREDICATE(xtheadcmo)
	201	MATERIALISE_EXT_PREDICATE(xtheadcondmov)
	202	MATERIALISE_EXT_PREDICATE(xtheadfmemidx)
	203	MATERIALISE_EXT_PREDICATE(xtheadfmv)
	204	MATERIALISE_EXT_PREDICATE(xtheadmac)
	205	MATERIALISE_EXT_PREDICATE(xtheadmemidx)
	206	MATERIALISE_EXT_PREDICATE(xtheadmempair)
	207	MATERIALISE_EXT_PREDICATE(xtheadsync)
2e8c1e02 CM	208	MATERIALISE_EXT_PREDICATE(XVentanaCondOps)
2e8c1e02 CM	209
b902ff29	210	#endif