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0c3e702a | 1 | /* |
df354dd4 | 2 | * RISC-V CPU helpers for qemu. |
0c3e702a MC |
3 | * |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
21 | #include "qemu/log.h" | |
7ec5d303 | 22 | #include "qemu/main-loop.h" |
0c3e702a | 23 | #include "cpu.h" |
892320fa | 24 | #include "pmu.h" |
0c3e702a | 25 | #include "exec/exec-all.h" |
8e2aa21b | 26 | #include "instmap.h" |
dcb32f1d | 27 | #include "tcg/tcg-op.h" |
929f0a7f | 28 | #include "trace.h" |
6b5fe137 | 29 | #include "semihosting/common-semi.h" |
2c9d7471 | 30 | #include "sysemu/cpu-timers.h" |
892320fa | 31 | #include "cpu_bits.h" |
2c9d7471 | 32 | #include "debug.h" |
0c3e702a MC |
33 | |
34 | int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) | |
35 | { | |
36 | #ifdef CONFIG_USER_ONLY | |
37 | return 0; | |
38 | #else | |
39 | return env->priv; | |
40 | #endif | |
41 | } | |
42 | ||
53677acf RH |
43 | void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, |
44 | target_ulong *cs_base, uint32_t *pflags) | |
45 | { | |
b4a99d40 FC |
46 | CPUState *cs = env_cpu(env); |
47 | RISCVCPU *cpu = RISCV_CPU(cs); | |
48 | ||
53677acf RH |
49 | uint32_t flags = 0; |
50 | ||
8c796f1a | 51 | *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc; |
53677acf RH |
52 | *cs_base = 0; |
53 | ||
3f4a5a53 | 54 | if (cpu->cfg.ext_zve32f) { |
a689a82b FC |
55 | /* |
56 | * If env->vl equals to VLMAX, we can use generic vector operation | |
57 | * expanders (GVEC) to accerlate the vector operations. | |
58 | * However, as LMUL could be a fractional number. The maximum | |
59 | * vector size can be operated might be less than 8 bytes, | |
60 | * which is not supported by GVEC. So we set vl_eq_vlmax flag to true | |
61 | * only when maxsz >= 8 bytes. | |
62 | */ | |
718942ae | 63 | uint32_t vlmax = vext_get_vlmax(cpu, env->vtype); |
a689a82b FC |
64 | uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW); |
65 | uint32_t maxsz = vlmax << sew; | |
66 | bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) && | |
67 | (maxsz >= 8); | |
d96a271a | 68 | flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); |
a689a82b | 69 | flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew); |
53677acf RH |
70 | flags = FIELD_DP32(flags, TB_FLAGS, LMUL, |
71 | FIELD_EX64(env->vtype, VTYPE, VLMUL)); | |
72 | flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); | |
f1eed927 | 73 | flags = FIELD_DP32(flags, TB_FLAGS, VTA, |
74 | FIELD_EX64(env->vtype, VTYPE, VTA)); | |
355d5584 YTC |
75 | flags = FIELD_DP32(flags, TB_FLAGS, VMA, |
76 | FIELD_EX64(env->vtype, VTYPE, VMA)); | |
53677acf RH |
77 | } else { |
78 | flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); | |
79 | } | |
80 | ||
81 | #ifdef CONFIG_USER_ONLY | |
82 | flags |= TB_FLAGS_MSTATUS_FS; | |
61b4b69d | 83 | flags |= TB_FLAGS_MSTATUS_VS; |
53677acf RH |
84 | #else |
85 | flags |= cpu_mmu_index(env, 0); | |
86 | if (riscv_cpu_fp_enabled(env)) { | |
87 | flags |= env->mstatus & MSTATUS_FS; | |
88 | } | |
89 | ||
61b4b69d LZ |
90 | if (riscv_cpu_vector_enabled(env)) { |
91 | flags |= env->mstatus & MSTATUS_VS; | |
92 | } | |
93 | ||
53677acf RH |
94 | if (riscv_has_ext(env, RVH)) { |
95 | if (env->priv == PRV_M || | |
96 | (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || | |
97 | (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && | |
98 | get_field(env->hstatus, HSTATUS_HU))) { | |
99 | flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); | |
100 | } | |
101 | ||
102 | flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, | |
103 | get_field(env->mstatus_hs, MSTATUS_FS)); | |
8e1ee1fb FC |
104 | |
105 | flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS, | |
106 | get_field(env->mstatus_hs, MSTATUS_VS)); | |
53677acf | 107 | } |
cdfb2905 | 108 | if (cpu->cfg.debug && !icount_enabled()) { |
577f0286 | 109 | flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled); |
2c9d7471 | 110 | } |
53677acf RH |
111 | #endif |
112 | ||
440544e1 | 113 | flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl); |
4208dc7e LZ |
114 | if (env->cur_pmmask < (env->xl == MXL_RV32 ? UINT32_MAX : UINT64_MAX)) { |
115 | flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); | |
116 | } | |
117 | if (env->cur_pmbase != 0) { | |
118 | flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1); | |
119 | } | |
92371bd9 | 120 | |
53677acf RH |
121 | *pflags = flags; |
122 | } | |
123 | ||
40bfa5f6 LZ |
124 | void riscv_cpu_update_mask(CPURISCVState *env) |
125 | { | |
126 | target_ulong mask = -1, base = 0; | |
127 | /* | |
128 | * TODO: Current RVJ spec does not specify | |
129 | * how the extension interacts with XLEN. | |
130 | */ | |
131 | #ifndef CONFIG_USER_ONLY | |
132 | if (riscv_has_ext(env, RVJ)) { | |
133 | switch (env->priv) { | |
134 | case PRV_M: | |
135 | if (env->mmte & M_PM_ENABLE) { | |
136 | mask = env->mpmmask; | |
137 | base = env->mpmbase; | |
138 | } | |
139 | break; | |
140 | case PRV_S: | |
141 | if (env->mmte & S_PM_ENABLE) { | |
142 | mask = env->spmmask; | |
143 | base = env->spmbase; | |
144 | } | |
145 | break; | |
146 | case PRV_U: | |
147 | if (env->mmte & U_PM_ENABLE) { | |
148 | mask = env->upmmask; | |
149 | base = env->upmbase; | |
150 | } | |
151 | break; | |
152 | default: | |
153 | g_assert_not_reached(); | |
154 | } | |
155 | } | |
156 | #endif | |
157 | if (env->xl == MXL_RV32) { | |
158 | env->cur_pmmask = mask & UINT32_MAX; | |
159 | env->cur_pmbase = base & UINT32_MAX; | |
160 | } else { | |
161 | env->cur_pmmask = mask; | |
162 | env->cur_pmbase = base; | |
163 | } | |
164 | } | |
165 | ||
0c3e702a | 166 | #ifndef CONFIG_USER_ONLY |
43dc93af AP |
167 | |
168 | /* | |
169 | * The HS-mode is allowed to configure priority only for the | |
170 | * following VS-mode local interrupts: | |
171 | * | |
172 | * 0 (Reserved interrupt, reads as zero) | |
173 | * 1 Supervisor software interrupt | |
174 | * 4 (Reserved interrupt, reads as zero) | |
175 | * 5 Supervisor timer interrupt | |
176 | * 8 (Reserved interrupt, reads as zero) | |
177 | * 13 (Reserved interrupt) | |
178 | * 14 " | |
179 | * 15 " | |
180 | * 16 " | |
43577499 AP |
181 | * 17 " |
182 | * 18 " | |
183 | * 19 " | |
184 | * 20 " | |
185 | * 21 " | |
43dc93af | 186 | * 22 " |
43577499 | 187 | * 23 " |
43dc93af AP |
188 | */ |
189 | ||
190 | static const int hviprio_index2irq[] = { | |
43577499 | 191 | 0, 1, 4, 5, 8, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 }; |
43dc93af AP |
192 | static const int hviprio_index2rdzero[] = { |
193 | 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; | |
194 | ||
195 | int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero) | |
0c3e702a | 196 | { |
43dc93af AP |
197 | if (index < 0 || ARRAY_SIZE(hviprio_index2irq) <= index) { |
198 | return -EINVAL; | |
199 | } | |
3ef10a09 | 200 | |
43dc93af AP |
201 | if (out_irq) { |
202 | *out_irq = hviprio_index2irq[index]; | |
203 | } | |
3ef10a09 | 204 | |
43dc93af AP |
205 | if (out_rdzero) { |
206 | *out_rdzero = hviprio_index2rdzero[index]; | |
207 | } | |
cd032fe7 | 208 | |
43dc93af AP |
209 | return 0; |
210 | } | |
3ef10a09 | 211 | |
43dc93af AP |
212 | /* |
213 | * Default priorities of local interrupts are defined in the | |
214 | * RISC-V Advanced Interrupt Architecture specification. | |
215 | * | |
216 | * ---------------------------------------------------------------- | |
217 | * Default | | |
218 | * Priority | Major Interrupt Numbers | |
219 | * ---------------------------------------------------------------- | |
43577499 AP |
220 | * Highest | 47, 23, 46, 45, 22, 44, |
221 | * | 43, 21, 42, 41, 20, 40 | |
43dc93af AP |
222 | * | |
223 | * | 11 (0b), 3 (03), 7 (07) | |
224 | * | 9 (09), 1 (01), 5 (05) | |
225 | * | 12 (0c) | |
226 | * | 10 (0a), 2 (02), 6 (06) | |
227 | * | | |
43577499 AP |
228 | * | 39, 19, 38, 37, 18, 36, |
229 | * Lowest | 35, 17, 34, 33, 16, 32 | |
43dc93af AP |
230 | * ---------------------------------------------------------------- |
231 | */ | |
232 | static const uint8_t default_iprio[64] = { | |
43577499 AP |
233 | /* Custom interrupts 48 to 63 */ |
234 | [63] = IPRIO_MMAXIPRIO, | |
235 | [62] = IPRIO_MMAXIPRIO, | |
236 | [61] = IPRIO_MMAXIPRIO, | |
237 | [60] = IPRIO_MMAXIPRIO, | |
238 | [59] = IPRIO_MMAXIPRIO, | |
239 | [58] = IPRIO_MMAXIPRIO, | |
240 | [57] = IPRIO_MMAXIPRIO, | |
241 | [56] = IPRIO_MMAXIPRIO, | |
242 | [55] = IPRIO_MMAXIPRIO, | |
243 | [54] = IPRIO_MMAXIPRIO, | |
244 | [53] = IPRIO_MMAXIPRIO, | |
245 | [52] = IPRIO_MMAXIPRIO, | |
246 | [51] = IPRIO_MMAXIPRIO, | |
247 | [50] = IPRIO_MMAXIPRIO, | |
248 | [49] = IPRIO_MMAXIPRIO, | |
249 | [48] = IPRIO_MMAXIPRIO, | |
250 | ||
251 | /* Custom interrupts 24 to 31 */ | |
252 | [31] = IPRIO_MMAXIPRIO, | |
253 | [30] = IPRIO_MMAXIPRIO, | |
254 | [29] = IPRIO_MMAXIPRIO, | |
255 | [28] = IPRIO_MMAXIPRIO, | |
256 | [27] = IPRIO_MMAXIPRIO, | |
257 | [26] = IPRIO_MMAXIPRIO, | |
258 | [25] = IPRIO_MMAXIPRIO, | |
259 | [24] = IPRIO_MMAXIPRIO, | |
260 | ||
261 | [47] = IPRIO_DEFAULT_UPPER, | |
262 | [23] = IPRIO_DEFAULT_UPPER + 1, | |
263 | [46] = IPRIO_DEFAULT_UPPER + 2, | |
264 | [45] = IPRIO_DEFAULT_UPPER + 3, | |
265 | [22] = IPRIO_DEFAULT_UPPER + 4, | |
266 | [44] = IPRIO_DEFAULT_UPPER + 5, | |
267 | ||
268 | [43] = IPRIO_DEFAULT_UPPER + 6, | |
269 | [21] = IPRIO_DEFAULT_UPPER + 7, | |
270 | [42] = IPRIO_DEFAULT_UPPER + 8, | |
271 | [41] = IPRIO_DEFAULT_UPPER + 9, | |
272 | [20] = IPRIO_DEFAULT_UPPER + 10, | |
273 | [40] = IPRIO_DEFAULT_UPPER + 11, | |
43dc93af AP |
274 | |
275 | [11] = IPRIO_DEFAULT_M, | |
276 | [3] = IPRIO_DEFAULT_M + 1, | |
277 | [7] = IPRIO_DEFAULT_M + 2, | |
278 | ||
279 | [9] = IPRIO_DEFAULT_S, | |
280 | [1] = IPRIO_DEFAULT_S + 1, | |
281 | [5] = IPRIO_DEFAULT_S + 2, | |
282 | ||
283 | [12] = IPRIO_DEFAULT_SGEXT, | |
284 | ||
285 | [10] = IPRIO_DEFAULT_VS, | |
286 | [2] = IPRIO_DEFAULT_VS + 1, | |
287 | [6] = IPRIO_DEFAULT_VS + 2, | |
288 | ||
43577499 AP |
289 | [39] = IPRIO_DEFAULT_LOWER, |
290 | [19] = IPRIO_DEFAULT_LOWER + 1, | |
291 | [38] = IPRIO_DEFAULT_LOWER + 2, | |
292 | [37] = IPRIO_DEFAULT_LOWER + 3, | |
293 | [18] = IPRIO_DEFAULT_LOWER + 4, | |
294 | [36] = IPRIO_DEFAULT_LOWER + 5, | |
295 | ||
296 | [35] = IPRIO_DEFAULT_LOWER + 6, | |
297 | [17] = IPRIO_DEFAULT_LOWER + 7, | |
298 | [34] = IPRIO_DEFAULT_LOWER + 8, | |
299 | [33] = IPRIO_DEFAULT_LOWER + 9, | |
300 | [16] = IPRIO_DEFAULT_LOWER + 10, | |
301 | [32] = IPRIO_DEFAULT_LOWER + 11, | |
43dc93af AP |
302 | }; |
303 | ||
304 | uint8_t riscv_cpu_default_priority(int irq) | |
305 | { | |
306 | if (irq < 0 || irq > 63) { | |
307 | return IPRIO_MMAXIPRIO; | |
308 | } | |
309 | ||
310 | return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO; | |
311 | }; | |
312 | ||
313 | static int riscv_cpu_pending_to_irq(CPURISCVState *env, | |
314 | int extirq, unsigned int extirq_def_prio, | |
315 | uint64_t pending, uint8_t *iprio) | |
316 | { | |
317 | int irq, best_irq = RISCV_EXCP_NONE; | |
318 | unsigned int prio, best_prio = UINT_MAX; | |
319 | ||
320 | if (!pending) { | |
321 | return RISCV_EXCP_NONE; | |
322 | } | |
323 | ||
324 | irq = ctz64(pending); | |
9c33e08b WL |
325 | if (!((extirq == IRQ_M_EXT) ? riscv_cpu_cfg(env)->ext_smaia : |
326 | riscv_cpu_cfg(env)->ext_ssaia)) { | |
43dc93af AP |
327 | return irq; |
328 | } | |
329 | ||
330 | pending = pending >> irq; | |
331 | while (pending) { | |
332 | prio = iprio[irq]; | |
333 | if (!prio) { | |
334 | if (irq == extirq) { | |
335 | prio = extirq_def_prio; | |
336 | } else { | |
337 | prio = (riscv_cpu_default_priority(irq) < extirq_def_prio) ? | |
338 | 1 : IPRIO_MMAXIPRIO; | |
339 | } | |
340 | } | |
341 | if ((pending & 0x1) && (prio <= best_prio)) { | |
342 | best_irq = irq; | |
343 | best_prio = prio; | |
344 | } | |
345 | irq++; | |
346 | pending = pending >> 1; | |
347 | } | |
348 | ||
349 | return best_irq; | |
350 | } | |
351 | ||
8f42415f | 352 | uint64_t riscv_cpu_all_pending(CPURISCVState *env) |
43dc93af AP |
353 | { |
354 | uint32_t gein = get_field(env->hstatus, HSTATUS_VGEIN); | |
355 | uint64_t vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; | |
3ec0fe18 | 356 | uint64_t vstip = (env->vstime_irq) ? MIP_VSTIP : 0; |
43dc93af | 357 | |
3ec0fe18 | 358 | return (env->mip | vsgein | vstip) & env->mie; |
43dc93af AP |
359 | } |
360 | ||
361 | int riscv_cpu_mirq_pending(CPURISCVState *env) | |
362 | { | |
363 | uint64_t irqs = riscv_cpu_all_pending(env) & ~env->mideleg & | |
364 | ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); | |
365 | ||
366 | return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, | |
367 | irqs, env->miprio); | |
368 | } | |
369 | ||
370 | int riscv_cpu_sirq_pending(CPURISCVState *env) | |
371 | { | |
372 | uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & | |
373 | ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); | |
374 | ||
375 | return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, | |
376 | irqs, env->siprio); | |
377 | } | |
378 | ||
379 | int riscv_cpu_vsirq_pending(CPURISCVState *env) | |
380 | { | |
381 | uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & | |
382 | (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); | |
383 | ||
384 | return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, | |
385 | irqs >> 1, env->hviprio); | |
386 | } | |
387 | ||
388 | static int riscv_cpu_local_irq_pending(CPURISCVState *env) | |
389 | { | |
390 | int virq; | |
391 | uint64_t irqs, pending, mie, hsie, vsie; | |
392 | ||
393 | /* Determine interrupt enable state of all privilege modes */ | |
394 | if (riscv_cpu_virt_enabled(env)) { | |
395 | mie = 1; | |
396 | hsie = 1; | |
397 | vsie = (env->priv < PRV_S) || | |
398 | (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE)); | |
0c3e702a | 399 | } else { |
43dc93af AP |
400 | mie = (env->priv < PRV_M) || |
401 | (env->priv == PRV_M && get_field(env->mstatus, MSTATUS_MIE)); | |
402 | hsie = (env->priv < PRV_S) || | |
403 | (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE)); | |
404 | vsie = 0; | |
405 | } | |
406 | ||
407 | /* Determine all pending interrupts */ | |
408 | pending = riscv_cpu_all_pending(env); | |
409 | ||
410 | /* Check M-mode interrupts */ | |
411 | irqs = pending & ~env->mideleg & -mie; | |
412 | if (irqs) { | |
413 | return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, | |
414 | irqs, env->miprio); | |
415 | } | |
416 | ||
417 | /* Check HS-mode interrupts */ | |
418 | irqs = pending & env->mideleg & ~env->hideleg & -hsie; | |
419 | if (irqs) { | |
420 | return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, | |
421 | irqs, env->siprio); | |
0c3e702a | 422 | } |
43dc93af AP |
423 | |
424 | /* Check VS-mode interrupts */ | |
425 | irqs = pending & env->mideleg & env->hideleg & -vsie; | |
426 | if (irqs) { | |
427 | virq = riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, | |
428 | irqs >> 1, env->hviprio); | |
429 | return (virq <= 0) ? virq : virq + 1; | |
430 | } | |
431 | ||
432 | /* Indicate no pending interrupt */ | |
433 | return RISCV_EXCP_NONE; | |
0c3e702a | 434 | } |
0c3e702a MC |
435 | |
436 | bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) | |
437 | { | |
0c3e702a MC |
438 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
439 | RISCVCPU *cpu = RISCV_CPU(cs); | |
440 | CPURISCVState *env = &cpu->env; | |
efbdbc26 | 441 | int interruptno = riscv_cpu_local_irq_pending(env); |
0c3e702a MC |
442 | if (interruptno >= 0) { |
443 | cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno; | |
444 | riscv_cpu_do_interrupt(cs); | |
445 | return true; | |
446 | } | |
447 | } | |
0c3e702a MC |
448 | return false; |
449 | } | |
450 | ||
b345b480 AF |
451 | /* Return true is floating point support is currently enabled */ |
452 | bool riscv_cpu_fp_enabled(CPURISCVState *env) | |
453 | { | |
454 | if (env->mstatus & MSTATUS_FS) { | |
29409c1d AF |
455 | if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_FS)) { |
456 | return false; | |
457 | } | |
b345b480 AF |
458 | return true; |
459 | } | |
460 | ||
461 | return false; | |
462 | } | |
463 | ||
61b4b69d LZ |
464 | /* Return true is vector support is currently enabled */ |
465 | bool riscv_cpu_vector_enabled(CPURISCVState *env) | |
466 | { | |
467 | if (env->mstatus & MSTATUS_VS) { | |
468 | if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_VS)) { | |
469 | return false; | |
470 | } | |
471 | return true; | |
472 | } | |
473 | ||
474 | return false; | |
475 | } | |
476 | ||
66e594f2 AF |
477 | void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) |
478 | { | |
c163b3ba | 479 | uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | |
284d697c | 480 | MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | |
61b4b69d | 481 | MSTATUS64_UXL | MSTATUS_VS; |
c163b3ba WL |
482 | |
483 | if (riscv_has_ext(env, RVF)) { | |
484 | mstatus_mask |= MSTATUS_FS; | |
485 | } | |
66e594f2 AF |
486 | bool current_virt = riscv_cpu_virt_enabled(env); |
487 | ||
488 | g_assert(riscv_has_ext(env, RVH)); | |
489 | ||
66e594f2 AF |
490 | if (current_virt) { |
491 | /* Current V=1 and we are about to change to V=0 */ | |
492 | env->vsstatus = env->mstatus & mstatus_mask; | |
493 | env->mstatus &= ~mstatus_mask; | |
494 | env->mstatus |= env->mstatus_hs; | |
495 | ||
496 | env->vstvec = env->stvec; | |
497 | env->stvec = env->stvec_hs; | |
498 | ||
499 | env->vsscratch = env->sscratch; | |
500 | env->sscratch = env->sscratch_hs; | |
501 | ||
502 | env->vsepc = env->sepc; | |
503 | env->sepc = env->sepc_hs; | |
504 | ||
505 | env->vscause = env->scause; | |
506 | env->scause = env->scause_hs; | |
507 | ||
ac12b601 AP |
508 | env->vstval = env->stval; |
509 | env->stval = env->stval_hs; | |
66e594f2 AF |
510 | |
511 | env->vsatp = env->satp; | |
512 | env->satp = env->satp_hs; | |
513 | } else { | |
514 | /* Current V=0 and we are about to change to V=1 */ | |
515 | env->mstatus_hs = env->mstatus & mstatus_mask; | |
516 | env->mstatus &= ~mstatus_mask; | |
517 | env->mstatus |= env->vsstatus; | |
518 | ||
519 | env->stvec_hs = env->stvec; | |
520 | env->stvec = env->vstvec; | |
521 | ||
522 | env->sscratch_hs = env->sscratch; | |
523 | env->sscratch = env->vsscratch; | |
524 | ||
525 | env->sepc_hs = env->sepc; | |
526 | env->sepc = env->vsepc; | |
527 | ||
528 | env->scause_hs = env->scause; | |
529 | env->scause = env->vscause; | |
530 | ||
ac12b601 AP |
531 | env->stval_hs = env->stval; |
532 | env->stval = env->vstval; | |
66e594f2 AF |
533 | |
534 | env->satp_hs = env->satp; | |
535 | env->satp = env->vsatp; | |
536 | } | |
537 | } | |
538 | ||
cd032fe7 AP |
539 | target_ulong riscv_cpu_get_geilen(CPURISCVState *env) |
540 | { | |
541 | if (!riscv_has_ext(env, RVH)) { | |
542 | return 0; | |
543 | } | |
544 | ||
545 | return env->geilen; | |
546 | } | |
547 | ||
548 | void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen) | |
549 | { | |
550 | if (!riscv_has_ext(env, RVH)) { | |
551 | return; | |
552 | } | |
553 | ||
554 | if (geilen > (TARGET_LONG_BITS - 1)) { | |
555 | return; | |
556 | } | |
557 | ||
558 | env->geilen = geilen; | |
559 | } | |
560 | ||
ef6bb7b6 AF |
561 | bool riscv_cpu_virt_enabled(CPURISCVState *env) |
562 | { | |
563 | if (!riscv_has_ext(env, RVH)) { | |
564 | return false; | |
565 | } | |
566 | ||
567 | return get_field(env->virt, VIRT_ONOFF); | |
568 | } | |
569 | ||
570 | void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) | |
571 | { | |
572 | if (!riscv_has_ext(env, RVH)) { | |
573 | return; | |
574 | } | |
575 | ||
eccc5a12 AF |
576 | /* Flush the TLB on all virt mode changes. */ |
577 | if (get_field(env->virt, VIRT_ONOFF) != enable) { | |
578 | tlb_flush(env_cpu(env)); | |
579 | } | |
580 | ||
ef6bb7b6 | 581 | env->virt = set_field(env->virt, VIRT_ONOFF, enable); |
02d9565b AP |
582 | |
583 | if (enable) { | |
584 | /* | |
585 | * The guest external interrupts from an interrupt controller are | |
586 | * delivered only when the Guest/VM is running (i.e. V=1). This means | |
587 | * any guest external interrupt which is triggered while the Guest/VM | |
588 | * is not running (i.e. V=0) will be missed on QEMU resulting in guest | |
589 | * with sluggish response to serial console input and other I/O events. | |
590 | * | |
591 | * To solve this, we check and inject interrupt after setting V=1. | |
592 | */ | |
bbb9fc25 | 593 | riscv_cpu_update_mip(env, 0, 0); |
02d9565b | 594 | } |
ef6bb7b6 AF |
595 | } |
596 | ||
1c1c060a | 597 | bool riscv_cpu_two_stage_lookup(int mmu_idx) |
5a894dd7 | 598 | { |
1c1c060a | 599 | return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK; |
5a894dd7 AF |
600 | } |
601 | ||
d028ac75 | 602 | int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts) |
e3e7039c MC |
603 | { |
604 | CPURISCVState *env = &cpu->env; | |
605 | if (env->miclaim & interrupts) { | |
606 | return -1; | |
607 | } else { | |
608 | env->miclaim |= interrupts; | |
609 | return 0; | |
610 | } | |
611 | } | |
612 | ||
bbb9fc25 WL |
613 | uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, |
614 | uint64_t value) | |
df354dd4 | 615 | { |
bbb9fc25 | 616 | CPUState *cs = env_cpu(env); |
3ec0fe18 | 617 | uint64_t gein, vsgein = 0, vstip = 0, old = env->mip; |
7ec5d303 | 618 | |
cd032fe7 AP |
619 | if (riscv_cpu_virt_enabled(env)) { |
620 | gein = get_field(env->hstatus, HSTATUS_VGEIN); | |
621 | vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; | |
622 | } | |
623 | ||
3ec0fe18 AP |
624 | vstip = env->vstime_irq ? MIP_VSTIP : 0; |
625 | ||
b3eb5b86 | 626 | QEMU_IOTHREAD_LOCK_GUARD(); |
df354dd4 | 627 | |
7ec5d303 | 628 | env->mip = (env->mip & ~mask) | (value & mask); |
df354dd4 | 629 | |
3ec0fe18 | 630 | if (env->mip | vsgein | vstip) { |
7ec5d303 AF |
631 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
632 | } else { | |
633 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); | |
634 | } | |
0a01f2ee | 635 | |
df354dd4 MC |
636 | return old; |
637 | } | |
638 | ||
e2f01f3c FC |
639 | void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), |
640 | void *arg) | |
c6957248 AP |
641 | { |
642 | env->rdtime_fn = fn; | |
a47ef6e9 | 643 | env->rdtime_fn_arg = arg; |
c6957248 AP |
644 | } |
645 | ||
69077dd6 AP |
646 | void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, |
647 | int (*rmw_fn)(void *arg, | |
648 | target_ulong reg, | |
649 | target_ulong *val, | |
650 | target_ulong new_val, | |
651 | target_ulong write_mask), | |
652 | void *rmw_fn_arg) | |
653 | { | |
654 | if (priv <= PRV_M) { | |
655 | env->aia_ireg_rmw_fn[priv] = rmw_fn; | |
656 | env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg; | |
657 | } | |
658 | } | |
659 | ||
fb738839 | 660 | void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) |
df354dd4 MC |
661 | { |
662 | if (newpriv > PRV_M) { | |
663 | g_assert_not_reached(); | |
664 | } | |
665 | if (newpriv == PRV_H) { | |
666 | newpriv = PRV_U; | |
667 | } | |
5a4ae64c LZ |
668 | if (icount_enabled() && newpriv != env->priv) { |
669 | riscv_itrigger_update_priv(env); | |
670 | } | |
df354dd4 MC |
671 | /* tlb_flush is unnecessary as mode is contained in mmu_idx */ |
672 | env->priv = newpriv; | |
440544e1 | 673 | env->xl = cpu_recompute_xl(env); |
40bfa5f6 | 674 | riscv_cpu_update_mask(env); |
c13b169f JS |
675 | |
676 | /* | |
677 | * Clear the load reservation - otherwise a reservation placed in one | |
678 | * context/process can be used by another, resulting in an SC succeeding | |
679 | * incorrectly. Version 2.2 of the ISA specification explicitly requires | |
680 | * this behaviour, while later revisions say that the kernel "should" use | |
681 | * an SC instruction to force the yielding of a load reservation on a | |
682 | * preemptive context switch. As a result, do both. | |
683 | */ | |
684 | env->load_res = -1; | |
df354dd4 MC |
685 | } |
686 | ||
b297129a JS |
687 | /* |
688 | * get_physical_address_pmp - check PMP permission for this physical address | |
689 | * | |
690 | * Match the PMP region and check permission for this physical address and it's | |
691 | * TLB page. Returns 0 if the permission checking was successful | |
692 | * | |
693 | * @env: CPURISCVState | |
694 | * @prot: The returned protection attributes | |
695 | * @tlb_size: TLB page size containing addr. It could be modified after PMP | |
696 | * permission checking. NULL if not set TLB page for addr. | |
697 | * @addr: The physical address to be checked permission | |
698 | * @access_type: The type of MMU access | |
699 | * @mode: Indicates current privilege level. | |
700 | */ | |
701 | static int get_physical_address_pmp(CPURISCVState *env, int *prot, | |
702 | target_ulong *tlb_size, hwaddr addr, | |
703 | int size, MMUAccessType access_type, | |
704 | int mode) | |
705 | { | |
706 | pmp_priv_t pmp_priv; | |
824cac68 | 707 | int pmp_index = -1; |
b297129a | 708 | |
3fe40ef5 | 709 | if (!riscv_cpu_cfg(env)->pmp) { |
b297129a JS |
710 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
711 | return TRANSLATE_SUCCESS; | |
712 | } | |
713 | ||
824cac68 LZ |
714 | pmp_index = pmp_hart_has_privs(env, addr, size, 1 << access_type, |
715 | &pmp_priv, mode); | |
716 | if (pmp_index < 0) { | |
b297129a JS |
717 | *prot = 0; |
718 | return TRANSLATE_PMP_FAIL; | |
719 | } | |
720 | ||
721 | *prot = pmp_priv_to_page_prot(pmp_priv); | |
824cac68 LZ |
722 | if ((tlb_size != NULL) && pmp_index != MAX_RISCV_PMPS) { |
723 | target_ulong tlb_sa = addr & ~(TARGET_PAGE_SIZE - 1); | |
724 | target_ulong tlb_ea = tlb_sa + TARGET_PAGE_SIZE - 1; | |
725 | ||
726 | *tlb_size = pmp_get_tlb_size(env, pmp_index, tlb_sa, tlb_ea); | |
b297129a JS |
727 | } |
728 | ||
729 | return TRANSLATE_SUCCESS; | |
730 | } | |
731 | ||
0c3e702a MC |
732 | /* get_physical_address - get the physical address for this virtual address |
733 | * | |
734 | * Do a page table walk to obtain the physical address corresponding to a | |
735 | * virtual address. Returns 0 if the translation was successful | |
736 | * | |
737 | * Adapted from Spike's mmu_t::translate and mmu_t::walk | |
738 | * | |
1448689c AF |
739 | * @env: CPURISCVState |
740 | * @physical: This will be set to the calculated physical address | |
741 | * @prot: The returned protection attributes | |
742 | * @addr: The virtual address to be translated | |
33a9a57d YJ |
743 | * @fault_pte_addr: If not NULL, this will be set to fault pte address |
744 | * when a error occurs on pte address translation. | |
745 | * This will already be shifted to match htval. | |
1448689c AF |
746 | * @access_type: The type of MMU access |
747 | * @mmu_idx: Indicates current privilege level | |
748 | * @first_stage: Are we in first stage translation? | |
749 | * Second stage is used for hypervisor guest translation | |
36a18664 | 750 | * @two_stage: Are we going to perform two stage translation |
11c27c6d | 751 | * @is_debug: Is this access from a debugger or the monitor? |
0c3e702a MC |
752 | */ |
753 | static int get_physical_address(CPURISCVState *env, hwaddr *physical, | |
754 | int *prot, target_ulong addr, | |
33a9a57d | 755 | target_ulong *fault_pte_addr, |
1448689c | 756 | int access_type, int mmu_idx, |
11c27c6d JF |
757 | bool first_stage, bool two_stage, |
758 | bool is_debug) | |
0c3e702a MC |
759 | { |
760 | /* NOTE: the env->pc value visible here will not be | |
761 | * correct, but the value visible to the exception handler | |
762 | * (riscv_cpu_do_interrupt) is correct */ | |
aacb578f PD |
763 | MemTxResult res; |
764 | MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; | |
c445593d | 765 | int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK; |
36a18664 | 766 | bool use_background = false; |
05e6ca5e | 767 | hwaddr ppn; |
2bacb224 WL |
768 | int napot_bits = 0; |
769 | target_ulong napot_mask; | |
0c3e702a | 770 | |
36a18664 AF |
771 | /* |
772 | * Check if we should use the background registers for the two | |
773 | * stage translation. We don't need to check if we actually need | |
774 | * two stage translation as that happened before this function | |
775 | * was called. Background registers will be used if the guest has | |
776 | * forced a two stage translation to be on (in HS or M mode). | |
777 | */ | |
db9ab38b | 778 | if (!riscv_cpu_virt_enabled(env) && two_stage) { |
29b3361b AF |
779 | use_background = true; |
780 | } | |
781 | ||
90ec1cff GK |
782 | /* MPRV does not affect the virtual-machine load/store |
783 | instructions, HLV, HLVX, and HSV. */ | |
784 | if (riscv_cpu_two_stage_lookup(mmu_idx)) { | |
785 | mode = get_field(env->hstatus, HSTATUS_SPVP); | |
786 | } else if (mode == PRV_M && access_type != MMU_INST_FETCH) { | |
0c3e702a MC |
787 | if (get_field(env->mstatus, MSTATUS_MPRV)) { |
788 | mode = get_field(env->mstatus, MSTATUS_MPP); | |
789 | } | |
790 | } | |
791 | ||
36a18664 AF |
792 | if (first_stage == false) { |
793 | /* We are in stage 2 translation, this is similar to stage 1. */ | |
794 | /* Stage 2 is always taken as U-mode */ | |
795 | mode = PRV_U; | |
796 | } | |
797 | ||
dcf654a3 | 798 | if (mode == PRV_M || !riscv_cpu_cfg(env)->mmu) { |
0c3e702a MC |
799 | *physical = addr; |
800 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
801 | return TRANSLATE_SUCCESS; | |
802 | } | |
803 | ||
804 | *prot = 0; | |
805 | ||
ddf78132 | 806 | hwaddr base; |
36a18664 AF |
807 | int levels, ptidxbits, ptesize, vm, sum, mxr, widened; |
808 | ||
809 | if (first_stage == true) { | |
810 | mxr = get_field(env->mstatus, MSTATUS_MXR); | |
811 | } else { | |
812 | mxr = get_field(env->vsstatus, MSTATUS_MXR); | |
813 | } | |
0c3e702a | 814 | |
1a9540d1 AF |
815 | if (first_stage == true) { |
816 | if (use_background) { | |
db23e5d9 | 817 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
419ddf00 AF |
818 | base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT; |
819 | vm = get_field(env->vsatp, SATP32_MODE); | |
820 | } else { | |
821 | base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT; | |
822 | vm = get_field(env->vsatp, SATP64_MODE); | |
823 | } | |
36a18664 | 824 | } else { |
db23e5d9 | 825 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
419ddf00 AF |
826 | base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; |
827 | vm = get_field(env->satp, SATP32_MODE); | |
828 | } else { | |
829 | base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT; | |
830 | vm = get_field(env->satp, SATP64_MODE); | |
831 | } | |
0c3e702a | 832 | } |
36a18664 | 833 | widened = 0; |
1a9540d1 | 834 | } else { |
db23e5d9 | 835 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
994b6bb2 AF |
836 | base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT; |
837 | vm = get_field(env->hgatp, SATP32_MODE); | |
838 | } else { | |
839 | base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT; | |
840 | vm = get_field(env->hgatp, SATP64_MODE); | |
841 | } | |
1a9540d1 AF |
842 | widened = 2; |
843 | } | |
c63ca4ff | 844 | /* status.SUM will be ignored if execute on background */ |
11c27c6d | 845 | sum = get_field(env->mstatus, MSTATUS_SUM) || use_background || is_debug; |
1a9540d1 AF |
846 | switch (vm) { |
847 | case VM_1_10_SV32: | |
848 | levels = 2; ptidxbits = 10; ptesize = 4; break; | |
849 | case VM_1_10_SV39: | |
850 | levels = 3; ptidxbits = 9; ptesize = 8; break; | |
851 | case VM_1_10_SV48: | |
852 | levels = 4; ptidxbits = 9; ptesize = 8; break; | |
853 | case VM_1_10_SV57: | |
854 | levels = 5; ptidxbits = 9; ptesize = 8; break; | |
855 | case VM_1_10_MBARE: | |
856 | *physical = addr; | |
857 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
858 | return TRANSLATE_SUCCESS; | |
859 | default: | |
860 | g_assert_not_reached(); | |
0c3e702a MC |
861 | } |
862 | ||
3109cd98 | 863 | CPUState *cs = env_cpu(env); |
36a18664 AF |
864 | int va_bits = PGSHIFT + levels * ptidxbits + widened; |
865 | target_ulong mask, masked_msbs; | |
866 | ||
867 | if (TARGET_LONG_BITS > (va_bits - 1)) { | |
868 | mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; | |
869 | } else { | |
870 | mask = 0; | |
871 | } | |
872 | masked_msbs = (addr >> (va_bits - 1)) & mask; | |
873 | ||
0c3e702a MC |
874 | if (masked_msbs != 0 && masked_msbs != mask) { |
875 | return TRANSLATE_FAIL; | |
876 | } | |
877 | ||
878 | int ptshift = (levels - 1) * ptidxbits; | |
879 | int i; | |
880 | ||
881 | #if !TCG_OVERSIZED_GUEST | |
882 | restart: | |
883 | #endif | |
884 | for (i = 0; i < levels; i++, ptshift -= ptidxbits) { | |
36a18664 AF |
885 | target_ulong idx; |
886 | if (i == 0) { | |
887 | idx = (addr >> (PGSHIFT + ptshift)) & | |
888 | ((1 << (ptidxbits + widened)) - 1); | |
889 | } else { | |
890 | idx = (addr >> (PGSHIFT + ptshift)) & | |
0c3e702a | 891 | ((1 << ptidxbits) - 1); |
36a18664 | 892 | } |
0c3e702a MC |
893 | |
894 | /* check that physical address of PTE is legal */ | |
36a18664 AF |
895 | hwaddr pte_addr; |
896 | ||
897 | if (two_stage && first_stage) { | |
38472890 | 898 | int vbase_prot; |
36a18664 AF |
899 | hwaddr vbase; |
900 | ||
901 | /* Do the second stage translation on the base PTE address. */ | |
88914473 | 902 | int vbase_ret = get_physical_address(env, &vbase, &vbase_prot, |
33a9a57d | 903 | base, NULL, MMU_DATA_LOAD, |
11c27c6d JF |
904 | mmu_idx, false, true, |
905 | is_debug); | |
88914473 AF |
906 | |
907 | if (vbase_ret != TRANSLATE_SUCCESS) { | |
33a9a57d YJ |
908 | if (fault_pte_addr) { |
909 | *fault_pte_addr = (base + idx * ptesize) >> 2; | |
910 | } | |
911 | return TRANSLATE_G_STAGE_FAIL; | |
88914473 | 912 | } |
36a18664 AF |
913 | |
914 | pte_addr = vbase + idx * ptesize; | |
915 | } else { | |
916 | pte_addr = base + idx * ptesize; | |
917 | } | |
1f447aec | 918 | |
b297129a JS |
919 | int pmp_prot; |
920 | int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr, | |
921 | sizeof(target_ulong), | |
922 | MMU_DATA_LOAD, PRV_S); | |
923 | if (pmp_ret != TRANSLATE_SUCCESS) { | |
1f447aec HA |
924 | return TRANSLATE_PMP_FAIL; |
925 | } | |
aacb578f | 926 | |
f08c7ff3 | 927 | target_ulong pte; |
db23e5d9 | 928 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
f08c7ff3 AF |
929 | pte = address_space_ldl(cs->as, pte_addr, attrs, &res); |
930 | } else { | |
931 | pte = address_space_ldq(cs->as, pte_addr, attrs, &res); | |
932 | } | |
933 | ||
aacb578f PD |
934 | if (res != MEMTX_OK) { |
935 | return TRANSLATE_FAIL; | |
936 | } | |
937 | ||
7a6613da | 938 | bool pbmte = env->menvcfg & MENVCFG_PBMTE; |
0af3f115 | 939 | bool hade = env->menvcfg & MENVCFG_HADE; |
7a6613da WL |
940 | |
941 | if (first_stage && two_stage && riscv_cpu_virt_enabled(env)) { | |
942 | pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE); | |
0af3f115 | 943 | hade = hade && (env->henvcfg & HENVCFG_HADE); |
7a6613da WL |
944 | } |
945 | ||
05e6ca5e GR |
946 | if (riscv_cpu_sxl(env) == MXL_RV32) { |
947 | ppn = pte >> PTE_PPN_SHIFT; | |
9c33e08b | 948 | } else if (pbmte || riscv_cpu_cfg(env)->ext_svnapot) { |
05e6ca5e GR |
949 | ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT; |
950 | } else { | |
951 | ppn = pte >> PTE_PPN_SHIFT; | |
952 | if ((pte & ~(target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT) { | |
953 | return TRANSLATE_FAIL; | |
954 | } | |
955 | } | |
0c3e702a | 956 | |
c3b03e58 MC |
957 | if (!(pte & PTE_V)) { |
958 | /* Invalid PTE */ | |
959 | return TRANSLATE_FAIL; | |
7a6613da | 960 | } else if (!pbmte && (pte & PTE_PBMT)) { |
bbce8ba8 | 961 | return TRANSLATE_FAIL; |
c3b03e58 MC |
962 | } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { |
963 | /* Inner PTE, continue walking */ | |
bbce8ba8 | 964 | if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) { |
b6ecc63c WL |
965 | return TRANSLATE_FAIL; |
966 | } | |
0c3e702a | 967 | base = ppn << PGSHIFT; |
c3b03e58 MC |
968 | } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) { |
969 | /* Reserved leaf PTE flags: PTE_W */ | |
970 | return TRANSLATE_FAIL; | |
971 | } else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) { | |
972 | /* Reserved leaf PTE flags: PTE_W + PTE_X */ | |
973 | return TRANSLATE_FAIL; | |
974 | } else if ((pte & PTE_U) && ((mode != PRV_U) && | |
975 | (!sum || access_type == MMU_INST_FETCH))) { | |
976 | /* User PTE flags when not U mode and mstatus.SUM is not set, | |
977 | or the access type is an instruction fetch */ | |
978 | return TRANSLATE_FAIL; | |
979 | } else if (!(pte & PTE_U) && (mode != PRV_S)) { | |
980 | /* Supervisor PTE flags when not S mode */ | |
981 | return TRANSLATE_FAIL; | |
982 | } else if (ppn & ((1ULL << ptshift) - 1)) { | |
983 | /* Misaligned PPN */ | |
984 | return TRANSLATE_FAIL; | |
985 | } else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) || | |
986 | ((pte & PTE_X) && mxr))) { | |
987 | /* Read access check failed */ | |
988 | return TRANSLATE_FAIL; | |
989 | } else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) { | |
990 | /* Write access check failed */ | |
991 | return TRANSLATE_FAIL; | |
992 | } else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) { | |
993 | /* Fetch access check failed */ | |
994 | return TRANSLATE_FAIL; | |
0c3e702a MC |
995 | } else { |
996 | /* if necessary, set accessed and dirty bits. */ | |
997 | target_ulong updated_pte = pte | PTE_A | | |
998 | (access_type == MMU_DATA_STORE ? PTE_D : 0); | |
999 | ||
1000 | /* Page table updates need to be atomic with MTTCG enabled */ | |
1001 | if (updated_pte != pte) { | |
0af3f115 WL |
1002 | if (!hade) { |
1003 | return TRANSLATE_FAIL; | |
1004 | } | |
1005 | ||
c3b03e58 MC |
1006 | /* |
1007 | * - if accessed or dirty bits need updating, and the PTE is | |
1008 | * in RAM, then we do so atomically with a compare and swap. | |
1009 | * - if the PTE is in IO space or ROM, then it can't be updated | |
1010 | * and we return TRANSLATE_FAIL. | |
1011 | * - if the PTE changed by the time we went to update it, then | |
1012 | * it is no longer valid and we must re-walk the page table. | |
1013 | */ | |
0c3e702a MC |
1014 | MemoryRegion *mr; |
1015 | hwaddr l = sizeof(target_ulong), addr1; | |
1016 | mr = address_space_translate(cs->as, pte_addr, | |
bc6b1cec | 1017 | &addr1, &l, false, MEMTXATTRS_UNSPECIFIED); |
c3b03e58 | 1018 | if (memory_region_is_ram(mr)) { |
0c3e702a MC |
1019 | target_ulong *pte_pa = |
1020 | qemu_map_ram_ptr(mr->ram_block, addr1); | |
1021 | #if TCG_OVERSIZED_GUEST | |
1022 | /* MTTCG is not enabled on oversized TCG guests so | |
1023 | * page table updates do not need to be atomic */ | |
1024 | *pte_pa = pte = updated_pte; | |
1025 | #else | |
1026 | target_ulong old_pte = | |
d73415a3 | 1027 | qatomic_cmpxchg(pte_pa, pte, updated_pte); |
0c3e702a MC |
1028 | if (old_pte != pte) { |
1029 | goto restart; | |
1030 | } else { | |
1031 | pte = updated_pte; | |
1032 | } | |
1033 | #endif | |
1034 | } else { | |
1035 | /* misconfigured PTE in ROM (AD bits are not preset) or | |
1036 | * PTE is in IO space and can't be updated atomically */ | |
1037 | return TRANSLATE_FAIL; | |
1038 | } | |
1039 | } | |
1040 | ||
1041 | /* for superpage mappings, make a fake leaf PTE for the TLB's | |
1042 | benefit. */ | |
1043 | target_ulong vpn = addr >> PGSHIFT; | |
2bacb224 | 1044 | |
9c33e08b | 1045 | if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { |
2bacb224 WL |
1046 | napot_bits = ctzl(ppn) + 1; |
1047 | if ((i != (levels - 1)) || (napot_bits != 4)) { | |
1048 | return TRANSLATE_FAIL; | |
1049 | } | |
1050 | } | |
1051 | ||
1052 | napot_mask = (1 << napot_bits) - 1; | |
1053 | *physical = (((ppn & ~napot_mask) | (vpn & napot_mask) | | |
1054 | (vpn & (((target_ulong)1 << ptshift) - 1)) | |
1055 | ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK); | |
0c3e702a | 1056 | |
c3b03e58 MC |
1057 | /* set permissions on the TLB entry */ |
1058 | if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { | |
0c3e702a MC |
1059 | *prot |= PAGE_READ; |
1060 | } | |
1061 | if ((pte & PTE_X)) { | |
1062 | *prot |= PAGE_EXEC; | |
1063 | } | |
c3b03e58 MC |
1064 | /* add write permission on stores or if the page is already dirty, |
1065 | so that we TLB miss on later writes to update the dirty bit */ | |
0c3e702a MC |
1066 | if ((pte & PTE_W) && |
1067 | (access_type == MMU_DATA_STORE || (pte & PTE_D))) { | |
1068 | *prot |= PAGE_WRITE; | |
1069 | } | |
1070 | return TRANSLATE_SUCCESS; | |
1071 | } | |
1072 | } | |
1073 | return TRANSLATE_FAIL; | |
1074 | } | |
1075 | ||
1076 | static void raise_mmu_exception(CPURISCVState *env, target_ulong address, | |
1448689c | 1077 | MMUAccessType access_type, bool pmp_violation, |
8e2aa21b AP |
1078 | bool first_stage, bool two_stage, |
1079 | bool two_stage_indirect) | |
0c3e702a | 1080 | { |
3109cd98 | 1081 | CPUState *cs = env_cpu(env); |
994b6bb2 | 1082 | int page_fault_exceptions, vm; |
419ddf00 AF |
1083 | uint64_t stap_mode; |
1084 | ||
db23e5d9 | 1085 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
419ddf00 AF |
1086 | stap_mode = SATP32_MODE; |
1087 | } else { | |
1088 | stap_mode = SATP64_MODE; | |
1089 | } | |
994b6bb2 | 1090 | |
1448689c | 1091 | if (first_stage) { |
419ddf00 | 1092 | vm = get_field(env->satp, stap_mode); |
1448689c | 1093 | } else { |
419ddf00 | 1094 | vm = get_field(env->hgatp, stap_mode); |
1448689c | 1095 | } |
419ddf00 | 1096 | |
994b6bb2 AF |
1097 | page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation; |
1098 | ||
0c3e702a MC |
1099 | switch (access_type) { |
1100 | case MMU_INST_FETCH: | |
b2ef6ab9 AF |
1101 | if (riscv_cpu_virt_enabled(env) && !first_stage) { |
1102 | cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT; | |
1103 | } else { | |
1104 | cs->exception_index = page_fault_exceptions ? | |
1105 | RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT; | |
1106 | } | |
0c3e702a MC |
1107 | break; |
1108 | case MMU_DATA_LOAD: | |
1c1c060a | 1109 | if (two_stage && !first_stage) { |
b2ef6ab9 AF |
1110 | cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; |
1111 | } else { | |
1112 | cs->exception_index = page_fault_exceptions ? | |
1113 | RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT; | |
1114 | } | |
0c3e702a MC |
1115 | break; |
1116 | case MMU_DATA_STORE: | |
1c1c060a | 1117 | if (two_stage && !first_stage) { |
b2ef6ab9 AF |
1118 | cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT; |
1119 | } else { | |
1120 | cs->exception_index = page_fault_exceptions ? | |
1121 | RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_FAULT; | |
1122 | } | |
0c3e702a MC |
1123 | break; |
1124 | default: | |
1125 | g_assert_not_reached(); | |
1126 | } | |
1127 | env->badaddr = address; | |
ec352d0c | 1128 | env->two_stage_lookup = two_stage; |
8e2aa21b | 1129 | env->two_stage_indirect_lookup = two_stage_indirect; |
0c3e702a MC |
1130 | } |
1131 | ||
1132 | hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) | |
1133 | { | |
1134 | RISCVCPU *cpu = RISCV_CPU(cs); | |
36a18664 | 1135 | CPURISCVState *env = &cpu->env; |
0c3e702a MC |
1136 | hwaddr phys_addr; |
1137 | int prot; | |
1138 | int mmu_idx = cpu_mmu_index(&cpu->env, false); | |
1139 | ||
33a9a57d | 1140 | if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx, |
11c27c6d | 1141 | true, riscv_cpu_virt_enabled(env), true)) { |
0c3e702a MC |
1142 | return -1; |
1143 | } | |
36a18664 AF |
1144 | |
1145 | if (riscv_cpu_virt_enabled(env)) { | |
33a9a57d | 1146 | if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL, |
11c27c6d | 1147 | 0, mmu_idx, false, true, true)) { |
36a18664 AF |
1148 | return -1; |
1149 | } | |
1150 | } | |
1151 | ||
9ef82119 | 1152 | return phys_addr & TARGET_PAGE_MASK; |
0c3e702a MC |
1153 | } |
1154 | ||
37207e12 PD |
1155 | void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, |
1156 | vaddr addr, unsigned size, | |
1157 | MMUAccessType access_type, | |
1158 | int mmu_idx, MemTxAttrs attrs, | |
1159 | MemTxResult response, uintptr_t retaddr) | |
cbf58276 MC |
1160 | { |
1161 | RISCVCPU *cpu = RISCV_CPU(cs); | |
1162 | CPURISCVState *env = &cpu->env; | |
1163 | ||
37207e12 | 1164 | if (access_type == MMU_DATA_STORE) { |
cbf58276 | 1165 | cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; |
f9e580c1 | 1166 | } else if (access_type == MMU_DATA_LOAD) { |
cbf58276 | 1167 | cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; |
f9e580c1 EB |
1168 | } else { |
1169 | cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT; | |
cbf58276 MC |
1170 | } |
1171 | ||
1172 | env->badaddr = addr; | |
ec352d0c GK |
1173 | env->two_stage_lookup = riscv_cpu_virt_enabled(env) || |
1174 | riscv_cpu_two_stage_lookup(mmu_idx); | |
8e2aa21b | 1175 | env->two_stage_indirect_lookup = false; |
ac684717 | 1176 | cpu_loop_exit_restore(cs, retaddr); |
cbf58276 MC |
1177 | } |
1178 | ||
0c3e702a MC |
1179 | void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, |
1180 | MMUAccessType access_type, int mmu_idx, | |
1181 | uintptr_t retaddr) | |
1182 | { | |
1183 | RISCVCPU *cpu = RISCV_CPU(cs); | |
1184 | CPURISCVState *env = &cpu->env; | |
1185 | switch (access_type) { | |
1186 | case MMU_INST_FETCH: | |
1187 | cs->exception_index = RISCV_EXCP_INST_ADDR_MIS; | |
1188 | break; | |
1189 | case MMU_DATA_LOAD: | |
1190 | cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS; | |
1191 | break; | |
1192 | case MMU_DATA_STORE: | |
1193 | cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS; | |
1194 | break; | |
1195 | default: | |
1196 | g_assert_not_reached(); | |
1197 | } | |
1198 | env->badaddr = addr; | |
ec352d0c GK |
1199 | env->two_stage_lookup = riscv_cpu_virt_enabled(env) || |
1200 | riscv_cpu_two_stage_lookup(mmu_idx); | |
8e2aa21b | 1201 | env->two_stage_indirect_lookup = false; |
ac684717 | 1202 | cpu_loop_exit_restore(cs, retaddr); |
0c3e702a | 1203 | } |
0c3e702a | 1204 | |
892320fa AP |
1205 | |
1206 | static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type) | |
1207 | { | |
1208 | enum riscv_pmu_event_idx pmu_event_type; | |
1209 | ||
1210 | switch (access_type) { | |
1211 | case MMU_INST_FETCH: | |
1212 | pmu_event_type = RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS; | |
1213 | break; | |
1214 | case MMU_DATA_LOAD: | |
1215 | pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS; | |
1216 | break; | |
1217 | case MMU_DATA_STORE: | |
1218 | pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS; | |
1219 | break; | |
1220 | default: | |
1221 | return; | |
1222 | } | |
1223 | ||
1224 | riscv_pmu_incr_ctr(cpu, pmu_event_type); | |
1225 | } | |
1226 | ||
8a4ca3c1 RH |
1227 | bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
1228 | MMUAccessType access_type, int mmu_idx, | |
1229 | bool probe, uintptr_t retaddr) | |
0c3e702a MC |
1230 | { |
1231 | RISCVCPU *cpu = RISCV_CPU(cs); | |
1232 | CPURISCVState *env = &cpu->env; | |
36a18664 | 1233 | vaddr im_address; |
0c3e702a | 1234 | hwaddr pa = 0; |
b297129a | 1235 | int prot, prot2, prot_pmp; |
635b0b0e | 1236 | bool pmp_violation = false; |
36a18664 | 1237 | bool first_stage_error = true; |
1c1c060a | 1238 | bool two_stage_lookup = false; |
8e2aa21b | 1239 | bool two_stage_indirect_error = false; |
0c3e702a | 1240 | int ret = TRANSLATE_FAIL; |
cc0fdb29 | 1241 | int mode = mmu_idx; |
b297129a JS |
1242 | /* default TLB page size */ |
1243 | target_ulong tlb_size = TARGET_PAGE_SIZE; | |
0c3e702a | 1244 | |
36a18664 AF |
1245 | env->guest_phys_fault_addr = 0; |
1246 | ||
8a4ca3c1 RH |
1247 | qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", |
1248 | __func__, address, access_type, mmu_idx); | |
1249 | ||
90ec1cff GK |
1250 | /* MPRV does not affect the virtual-machine load/store |
1251 | instructions, HLV, HLVX, and HSV. */ | |
1252 | if (riscv_cpu_two_stage_lookup(mmu_idx)) { | |
1253 | mode = get_field(env->hstatus, HSTATUS_SPVP); | |
1254 | } else if (mode == PRV_M && access_type != MMU_INST_FETCH && | |
1255 | get_field(env->mstatus, MSTATUS_MPRV)) { | |
1256 | mode = get_field(env->mstatus, MSTATUS_MPP); | |
1257 | if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) { | |
1258 | two_stage_lookup = true; | |
cc0fdb29 HA |
1259 | } |
1260 | } | |
1261 | ||
eacd03cb | 1262 | pmu_tlb_fill_incr_ctr(cpu, access_type); |
29b3361b | 1263 | if (riscv_cpu_virt_enabled(env) || |
1c1c060a AF |
1264 | ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) && |
1265 | access_type != MMU_INST_FETCH)) { | |
36a18664 | 1266 | /* Two stage lookup */ |
33a9a57d YJ |
1267 | ret = get_physical_address(env, &pa, &prot, address, |
1268 | &env->guest_phys_fault_addr, access_type, | |
11c27c6d | 1269 | mmu_idx, true, true, false); |
36a18664 | 1270 | |
33a9a57d YJ |
1271 | /* |
1272 | * A G-stage exception may be triggered during two state lookup. | |
1273 | * And the env->guest_phys_fault_addr has already been set in | |
1274 | * get_physical_address(). | |
1275 | */ | |
1276 | if (ret == TRANSLATE_G_STAGE_FAIL) { | |
1277 | first_stage_error = false; | |
8e2aa21b | 1278 | two_stage_indirect_error = true; |
33a9a57d YJ |
1279 | access_type = MMU_DATA_LOAD; |
1280 | } | |
1281 | ||
36a18664 AF |
1282 | qemu_log_mask(CPU_LOG_MMU, |
1283 | "%s 1st-stage address=%" VADDR_PRIx " ret %d physical " | |
883f2c59 | 1284 | HWADDR_FMT_plx " prot %d\n", |
36a18664 AF |
1285 | __func__, address, ret, pa, prot); |
1286 | ||
33a9a57d | 1287 | if (ret == TRANSLATE_SUCCESS) { |
36a18664 AF |
1288 | /* Second stage lookup */ |
1289 | im_address = pa; | |
1290 | ||
33a9a57d | 1291 | ret = get_physical_address(env, &pa, &prot2, im_address, NULL, |
11c27c6d JF |
1292 | access_type, mmu_idx, false, true, |
1293 | false); | |
36a18664 AF |
1294 | |
1295 | qemu_log_mask(CPU_LOG_MMU, | |
1296 | "%s 2nd-stage address=%" VADDR_PRIx " ret %d physical " | |
883f2c59 | 1297 | HWADDR_FMT_plx " prot %d\n", |
8f67cd6d AF |
1298 | __func__, im_address, ret, pa, prot2); |
1299 | ||
1300 | prot &= prot2; | |
36a18664 | 1301 | |
b297129a JS |
1302 | if (ret == TRANSLATE_SUCCESS) { |
1303 | ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, | |
1304 | size, access_type, mode); | |
663e1193 JS |
1305 | |
1306 | qemu_log_mask(CPU_LOG_MMU, | |
883f2c59 | 1307 | "%s PMP address=" HWADDR_FMT_plx " ret %d prot" |
663e1193 JS |
1308 | " %d tlb_size " TARGET_FMT_lu "\n", |
1309 | __func__, pa, ret, prot_pmp, tlb_size); | |
1310 | ||
b297129a | 1311 | prot &= prot_pmp; |
36a18664 AF |
1312 | } |
1313 | ||
1314 | if (ret != TRANSLATE_SUCCESS) { | |
1315 | /* | |
1316 | * Guest physical address translation failed, this is a HS | |
1317 | * level exception | |
1318 | */ | |
1319 | first_stage_error = false; | |
1320 | env->guest_phys_fault_addr = (im_address | | |
1321 | (address & | |
1322 | (TARGET_PAGE_SIZE - 1))) >> 2; | |
1323 | } | |
1324 | } | |
1325 | } else { | |
1326 | /* Single stage lookup */ | |
33a9a57d | 1327 | ret = get_physical_address(env, &pa, &prot, address, NULL, |
11c27c6d | 1328 | access_type, mmu_idx, true, false, false); |
36a18664 AF |
1329 | |
1330 | qemu_log_mask(CPU_LOG_MMU, | |
1331 | "%s address=%" VADDR_PRIx " ret %d physical " | |
883f2c59 | 1332 | HWADDR_FMT_plx " prot %d\n", |
36a18664 | 1333 | __func__, address, ret, pa, prot); |
8a4ca3c1 | 1334 | |
b297129a JS |
1335 | if (ret == TRANSLATE_SUCCESS) { |
1336 | ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, | |
1337 | size, access_type, mode); | |
663e1193 JS |
1338 | |
1339 | qemu_log_mask(CPU_LOG_MMU, | |
883f2c59 | 1340 | "%s PMP address=" HWADDR_FMT_plx " ret %d prot" |
663e1193 JS |
1341 | " %d tlb_size " TARGET_FMT_lu "\n", |
1342 | __func__, pa, ret, prot_pmp, tlb_size); | |
1343 | ||
b297129a JS |
1344 | prot &= prot_pmp; |
1345 | } | |
1f447aec | 1346 | } |
b297129a | 1347 | |
1f447aec | 1348 | if (ret == TRANSLATE_PMP_FAIL) { |
635b0b0e | 1349 | pmp_violation = true; |
0c3e702a | 1350 | } |
36a18664 | 1351 | |
0c3e702a | 1352 | if (ret == TRANSLATE_SUCCESS) { |
b297129a JS |
1353 | tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1), |
1354 | prot, mmu_idx, tlb_size); | |
8a4ca3c1 RH |
1355 | return true; |
1356 | } else if (probe) { | |
1357 | return false; | |
1358 | } else { | |
1c1c060a AF |
1359 | raise_mmu_exception(env, address, access_type, pmp_violation, |
1360 | first_stage_error, | |
1361 | riscv_cpu_virt_enabled(env) || | |
8e2aa21b AP |
1362 | riscv_cpu_two_stage_lookup(mmu_idx), |
1363 | two_stage_indirect_error); | |
ac684717 | 1364 | cpu_loop_exit_restore(cs, retaddr); |
0c3e702a | 1365 | } |
36a18664 AF |
1366 | |
1367 | return true; | |
0c3e702a | 1368 | } |
8e2aa21b AP |
1369 | |
1370 | static target_ulong riscv_transformed_insn(CPURISCVState *env, | |
1371 | target_ulong insn, | |
1372 | target_ulong taddr) | |
1373 | { | |
1374 | target_ulong xinsn = 0; | |
1375 | target_ulong access_rs1 = 0, access_imm = 0, access_size = 0; | |
1376 | ||
1377 | /* | |
1378 | * Only Quadrant 0 and Quadrant 2 of RVC instruction space need to | |
1379 | * be uncompressed. The Quadrant 1 of RVC instruction space need | |
1380 | * not be transformed because these instructions won't generate | |
1381 | * any load/store trap. | |
1382 | */ | |
1383 | ||
1384 | if ((insn & 0x3) != 0x3) { | |
1385 | /* Transform 16bit instruction into 32bit instruction */ | |
1386 | switch (GET_C_OP(insn)) { | |
1387 | case OPC_RISC_C_OP_QUAD0: /* Quadrant 0 */ | |
1388 | switch (GET_C_FUNC(insn)) { | |
1389 | case OPC_RISC_C_FUNC_FLD_LQ: | |
1390 | if (riscv_cpu_xlen(env) != 128) { /* C.FLD (RV32/64) */ | |
1391 | xinsn = OPC_RISC_FLD; | |
1392 | xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); | |
1393 | access_rs1 = GET_C_RS1S(insn); | |
1394 | access_imm = GET_C_LD_IMM(insn); | |
1395 | access_size = 8; | |
1396 | } | |
1397 | break; | |
1398 | case OPC_RISC_C_FUNC_LW: /* C.LW */ | |
1399 | xinsn = OPC_RISC_LW; | |
1400 | xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); | |
1401 | access_rs1 = GET_C_RS1S(insn); | |
1402 | access_imm = GET_C_LW_IMM(insn); | |
1403 | access_size = 4; | |
1404 | break; | |
1405 | case OPC_RISC_C_FUNC_FLW_LD: | |
1406 | if (riscv_cpu_xlen(env) == 32) { /* C.FLW (RV32) */ | |
1407 | xinsn = OPC_RISC_FLW; | |
1408 | xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); | |
1409 | access_rs1 = GET_C_RS1S(insn); | |
1410 | access_imm = GET_C_LW_IMM(insn); | |
1411 | access_size = 4; | |
1412 | } else { /* C.LD (RV64/RV128) */ | |
1413 | xinsn = OPC_RISC_LD; | |
1414 | xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); | |
1415 | access_rs1 = GET_C_RS1S(insn); | |
1416 | access_imm = GET_C_LD_IMM(insn); | |
1417 | access_size = 8; | |
1418 | } | |
1419 | break; | |
1420 | case OPC_RISC_C_FUNC_FSD_SQ: | |
1421 | if (riscv_cpu_xlen(env) != 128) { /* C.FSD (RV32/64) */ | |
1422 | xinsn = OPC_RISC_FSD; | |
1423 | xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); | |
1424 | access_rs1 = GET_C_RS1S(insn); | |
1425 | access_imm = GET_C_SD_IMM(insn); | |
1426 | access_size = 8; | |
1427 | } | |
1428 | break; | |
1429 | case OPC_RISC_C_FUNC_SW: /* C.SW */ | |
1430 | xinsn = OPC_RISC_SW; | |
1431 | xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); | |
1432 | access_rs1 = GET_C_RS1S(insn); | |
1433 | access_imm = GET_C_SW_IMM(insn); | |
1434 | access_size = 4; | |
1435 | break; | |
1436 | case OPC_RISC_C_FUNC_FSW_SD: | |
1437 | if (riscv_cpu_xlen(env) == 32) { /* C.FSW (RV32) */ | |
1438 | xinsn = OPC_RISC_FSW; | |
1439 | xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); | |
1440 | access_rs1 = GET_C_RS1S(insn); | |
1441 | access_imm = GET_C_SW_IMM(insn); | |
1442 | access_size = 4; | |
1443 | } else { /* C.SD (RV64/RV128) */ | |
1444 | xinsn = OPC_RISC_SD; | |
1445 | xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); | |
1446 | access_rs1 = GET_C_RS1S(insn); | |
1447 | access_imm = GET_C_SD_IMM(insn); | |
1448 | access_size = 8; | |
1449 | } | |
1450 | break; | |
1451 | default: | |
1452 | break; | |
1453 | } | |
1454 | break; | |
1455 | case OPC_RISC_C_OP_QUAD2: /* Quadrant 2 */ | |
1456 | switch (GET_C_FUNC(insn)) { | |
1457 | case OPC_RISC_C_FUNC_FLDSP_LQSP: | |
1458 | if (riscv_cpu_xlen(env) != 128) { /* C.FLDSP (RV32/64) */ | |
1459 | xinsn = OPC_RISC_FLD; | |
1460 | xinsn = SET_RD(xinsn, GET_C_RD(insn)); | |
1461 | access_rs1 = 2; | |
1462 | access_imm = GET_C_LDSP_IMM(insn); | |
1463 | access_size = 8; | |
1464 | } | |
1465 | break; | |
1466 | case OPC_RISC_C_FUNC_LWSP: /* C.LWSP */ | |
1467 | xinsn = OPC_RISC_LW; | |
1468 | xinsn = SET_RD(xinsn, GET_C_RD(insn)); | |
1469 | access_rs1 = 2; | |
1470 | access_imm = GET_C_LWSP_IMM(insn); | |
1471 | access_size = 4; | |
1472 | break; | |
1473 | case OPC_RISC_C_FUNC_FLWSP_LDSP: | |
1474 | if (riscv_cpu_xlen(env) == 32) { /* C.FLWSP (RV32) */ | |
1475 | xinsn = OPC_RISC_FLW; | |
1476 | xinsn = SET_RD(xinsn, GET_C_RD(insn)); | |
1477 | access_rs1 = 2; | |
1478 | access_imm = GET_C_LWSP_IMM(insn); | |
1479 | access_size = 4; | |
1480 | } else { /* C.LDSP (RV64/RV128) */ | |
1481 | xinsn = OPC_RISC_LD; | |
1482 | xinsn = SET_RD(xinsn, GET_C_RD(insn)); | |
1483 | access_rs1 = 2; | |
1484 | access_imm = GET_C_LDSP_IMM(insn); | |
1485 | access_size = 8; | |
1486 | } | |
1487 | break; | |
1488 | case OPC_RISC_C_FUNC_FSDSP_SQSP: | |
1489 | if (riscv_cpu_xlen(env) != 128) { /* C.FSDSP (RV32/64) */ | |
1490 | xinsn = OPC_RISC_FSD; | |
1491 | xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); | |
1492 | access_rs1 = 2; | |
1493 | access_imm = GET_C_SDSP_IMM(insn); | |
1494 | access_size = 8; | |
1495 | } | |
1496 | break; | |
1497 | case OPC_RISC_C_FUNC_SWSP: /* C.SWSP */ | |
1498 | xinsn = OPC_RISC_SW; | |
1499 | xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); | |
1500 | access_rs1 = 2; | |
1501 | access_imm = GET_C_SWSP_IMM(insn); | |
1502 | access_size = 4; | |
1503 | break; | |
1504 | case 7: | |
1505 | if (riscv_cpu_xlen(env) == 32) { /* C.FSWSP (RV32) */ | |
1506 | xinsn = OPC_RISC_FSW; | |
1507 | xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); | |
1508 | access_rs1 = 2; | |
1509 | access_imm = GET_C_SWSP_IMM(insn); | |
1510 | access_size = 4; | |
1511 | } else { /* C.SDSP (RV64/RV128) */ | |
1512 | xinsn = OPC_RISC_SD; | |
1513 | xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); | |
1514 | access_rs1 = 2; | |
1515 | access_imm = GET_C_SDSP_IMM(insn); | |
1516 | access_size = 8; | |
1517 | } | |
1518 | break; | |
1519 | default: | |
1520 | break; | |
1521 | } | |
1522 | break; | |
1523 | default: | |
1524 | break; | |
1525 | } | |
1526 | ||
1527 | /* | |
1528 | * Clear Bit1 of transformed instruction to indicate that | |
1529 | * original insruction was a 16bit instruction | |
1530 | */ | |
1531 | xinsn &= ~((target_ulong)0x2); | |
1532 | } else { | |
1533 | /* Transform 32bit (or wider) instructions */ | |
1534 | switch (MASK_OP_MAJOR(insn)) { | |
1535 | case OPC_RISC_ATOMIC: | |
1536 | xinsn = insn; | |
1537 | access_rs1 = GET_RS1(insn); | |
1538 | access_size = 1 << GET_FUNCT3(insn); | |
1539 | break; | |
1540 | case OPC_RISC_LOAD: | |
1541 | case OPC_RISC_FP_LOAD: | |
1542 | xinsn = SET_I_IMM(insn, 0); | |
1543 | access_rs1 = GET_RS1(insn); | |
1544 | access_imm = GET_IMM(insn); | |
1545 | access_size = 1 << GET_FUNCT3(insn); | |
1546 | break; | |
1547 | case OPC_RISC_STORE: | |
1548 | case OPC_RISC_FP_STORE: | |
1549 | xinsn = SET_S_IMM(insn, 0); | |
1550 | access_rs1 = GET_RS1(insn); | |
1551 | access_imm = GET_STORE_IMM(insn); | |
1552 | access_size = 1 << GET_FUNCT3(insn); | |
1553 | break; | |
1554 | case OPC_RISC_SYSTEM: | |
1555 | if (MASK_OP_SYSTEM(insn) == OPC_RISC_HLVHSV) { | |
1556 | xinsn = insn; | |
1557 | access_rs1 = GET_RS1(insn); | |
1558 | access_size = 1 << ((GET_FUNCT7(insn) >> 1) & 0x3); | |
1559 | access_size = 1 << access_size; | |
1560 | } | |
1561 | break; | |
1562 | default: | |
1563 | break; | |
1564 | } | |
1565 | } | |
1566 | ||
1567 | if (access_size) { | |
1568 | xinsn = SET_RS1(xinsn, (taddr - (env->gpr[access_rs1] + access_imm)) & | |
1569 | (access_size - 1)); | |
1570 | } | |
1571 | ||
1572 | return xinsn; | |
1573 | } | |
263e2ab2 | 1574 | #endif /* !CONFIG_USER_ONLY */ |
0c3e702a MC |
1575 | |
1576 | /* | |
1577 | * Handle Traps | |
1578 | * | |
1579 | * Adapted from Spike's processor_t::take_trap. | |
1580 | * | |
1581 | */ | |
1582 | void riscv_cpu_do_interrupt(CPUState *cs) | |
1583 | { | |
1584 | #if !defined(CONFIG_USER_ONLY) | |
1585 | ||
1586 | RISCVCPU *cpu = RISCV_CPU(cs); | |
1587 | CPURISCVState *env = &cpu->env; | |
86d0c457 | 1588 | bool write_gva = false; |
284d697c | 1589 | uint64_t s; |
0c3e702a | 1590 | |
acbbb94e MC |
1591 | /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide |
1592 | * so we mask off the MSB and separate into trap type and cause. | |
1593 | */ | |
1594 | bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG); | |
1595 | target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; | |
d028ac75 | 1596 | uint64_t deleg = async ? env->mideleg : env->medeleg; |
acbbb94e | 1597 | target_ulong tval = 0; |
8e2aa21b | 1598 | target_ulong tinst = 0; |
30675539 AF |
1599 | target_ulong htval = 0; |
1600 | target_ulong mtval2 = 0; | |
acbbb94e | 1601 | |
a10b9d93 | 1602 | if (cause == RISCV_EXCP_SEMIHOST) { |
7d7fb116 PM |
1603 | do_common_semihosting(cs); |
1604 | env->pc += 4; | |
1605 | return; | |
a10b9d93 KP |
1606 | } |
1607 | ||
acbbb94e MC |
1608 | if (!async) { |
1609 | /* set tval to badaddr for traps with address information */ | |
1610 | switch (cause) { | |
ab67a1d0 AF |
1611 | case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: |
1612 | case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: | |
acbbb94e MC |
1613 | case RISCV_EXCP_LOAD_ADDR_MIS: |
1614 | case RISCV_EXCP_STORE_AMO_ADDR_MIS: | |
1615 | case RISCV_EXCP_LOAD_ACCESS_FAULT: | |
1616 | case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: | |
acbbb94e MC |
1617 | case RISCV_EXCP_LOAD_PAGE_FAULT: |
1618 | case RISCV_EXCP_STORE_PAGE_FAULT: | |
24826da0 | 1619 | write_gva = env->two_stage_lookup; |
acbbb94e | 1620 | tval = env->badaddr; |
8e2aa21b AP |
1621 | if (env->two_stage_indirect_lookup) { |
1622 | /* | |
1623 | * special pseudoinstruction for G-stage fault taken while | |
1624 | * doing VS-stage page table walk. | |
1625 | */ | |
1626 | tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000; | |
1627 | } else { | |
1628 | /* | |
1629 | * The "Addr. Offset" field in transformed instruction is | |
1630 | * non-zero only for misaligned access. | |
1631 | */ | |
1632 | tinst = riscv_transformed_insn(env, env->bins, tval); | |
1633 | } | |
1634 | break; | |
1635 | case RISCV_EXCP_INST_GUEST_PAGE_FAULT: | |
1636 | case RISCV_EXCP_INST_ADDR_MIS: | |
1637 | case RISCV_EXCP_INST_ACCESS_FAULT: | |
1638 | case RISCV_EXCP_INST_PAGE_FAULT: | |
1639 | write_gva = env->two_stage_lookup; | |
1640 | tval = env->badaddr; | |
1641 | if (env->two_stage_indirect_lookup) { | |
1642 | /* | |
1643 | * special pseudoinstruction for G-stage fault taken while | |
1644 | * doing VS-stage page table walk. | |
1645 | */ | |
1646 | tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000; | |
1647 | } | |
acbbb94e | 1648 | break; |
48eaeb56 | 1649 | case RISCV_EXCP_ILLEGAL_INST: |
62cf0245 | 1650 | case RISCV_EXCP_VIRT_INSTRUCTION_FAULT: |
48eaeb56 AF |
1651 | tval = env->bins; |
1652 | break; | |
26934f9a SM |
1653 | case RISCV_EXCP_BREAKPOINT: |
1654 | if (cs->watchpoint_hit) { | |
1655 | tval = cs->watchpoint_hit->hitaddr; | |
1656 | cs->watchpoint_hit = NULL; | |
1657 | } | |
1658 | break; | |
acbbb94e MC |
1659 | default: |
1660 | break; | |
0c3e702a | 1661 | } |
acbbb94e MC |
1662 | /* ecall is dispatched as one cause so translate based on mode */ |
1663 | if (cause == RISCV_EXCP_U_ECALL) { | |
1664 | assert(env->priv <= 3); | |
5eb9e782 AF |
1665 | |
1666 | if (env->priv == PRV_M) { | |
1667 | cause = RISCV_EXCP_M_ECALL; | |
1668 | } else if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) { | |
1669 | cause = RISCV_EXCP_VS_ECALL; | |
1670 | } else if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) { | |
1671 | cause = RISCV_EXCP_S_ECALL; | |
1672 | } else if (env->priv == PRV_U) { | |
1673 | cause = RISCV_EXCP_U_ECALL; | |
1674 | } | |
0c3e702a MC |
1675 | } |
1676 | } | |
1677 | ||
c51a3f5d | 1678 | trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, |
69430111 AF |
1679 | riscv_cpu_get_trap_name(cause, async)); |
1680 | ||
1681 | qemu_log_mask(CPU_LOG_INT, | |
1682 | "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", " | |
1683 | "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n", | |
1684 | __func__, env->mhartid, async, cause, env->pc, tval, | |
1685 | riscv_cpu_get_trap_name(cause, async)); | |
0c3e702a | 1686 | |
acbbb94e MC |
1687 | if (env->priv <= PRV_S && |
1688 | cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { | |
0c3e702a | 1689 | /* handle the trap in S-mode */ |
5eb9e782 | 1690 | if (riscv_has_ext(env, RVH)) { |
d028ac75 | 1691 | uint64_t hdeleg = async ? env->hideleg : env->hedeleg; |
1c1c060a | 1692 | |
50d16087 | 1693 | if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1)) { |
84b1c04b | 1694 | /* Trap to VS mode */ |
c5969a3a RK |
1695 | /* |
1696 | * See if we need to adjust cause. Yes if its VS mode interrupt | |
1697 | * no if hypervisor has delegated one of hs mode's interrupt | |
1698 | */ | |
1699 | if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || | |
84b1c04b | 1700 | cause == IRQ_VS_EXT) { |
c5969a3a | 1701 | cause = cause - 1; |
84b1c04b | 1702 | } |
86d0c457 | 1703 | write_gva = false; |
5eb9e782 AF |
1704 | } else if (riscv_cpu_virt_enabled(env)) { |
1705 | /* Trap into HS mode, from virt */ | |
1706 | riscv_cpu_swap_hypervisor_regs(env); | |
f2d5850f | 1707 | env->hstatus = set_field(env->hstatus, HSTATUS_SPVP, |
ace54453 | 1708 | env->priv); |
5eb9e782 AF |
1709 | env->hstatus = set_field(env->hstatus, HSTATUS_SPV, |
1710 | riscv_cpu_virt_enabled(env)); | |
1711 | ||
86d0c457 | 1712 | |
30675539 AF |
1713 | htval = env->guest_phys_fault_addr; |
1714 | ||
5eb9e782 | 1715 | riscv_cpu_set_virt_enabled(env, 0); |
5eb9e782 AF |
1716 | } else { |
1717 | /* Trap into HS mode */ | |
ec352d0c | 1718 | env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false); |
30675539 | 1719 | htval = env->guest_phys_fault_addr; |
5eb9e782 | 1720 | } |
86d0c457 | 1721 | env->hstatus = set_field(env->hstatus, HSTATUS_GVA, write_gva); |
5eb9e782 AF |
1722 | } |
1723 | ||
1724 | s = env->mstatus; | |
1a9540d1 | 1725 | s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); |
0c3e702a MC |
1726 | s = set_field(s, MSTATUS_SPP, env->priv); |
1727 | s = set_field(s, MSTATUS_SIE, 0); | |
c7b95171 | 1728 | env->mstatus = s; |
16fdb8ff | 1729 | env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1)); |
acbbb94e | 1730 | env->sepc = env->pc; |
ac12b601 | 1731 | env->stval = tval; |
30675539 | 1732 | env->htval = htval; |
8e2aa21b | 1733 | env->htinst = tinst; |
acbbb94e MC |
1734 | env->pc = (env->stvec >> 2 << 2) + |
1735 | ((async && (env->stvec & 3) == 1) ? cause * 4 : 0); | |
fb738839 | 1736 | riscv_cpu_set_mode(env, PRV_S); |
0c3e702a | 1737 | } else { |
acbbb94e | 1738 | /* handle the trap in M-mode */ |
5eb9e782 AF |
1739 | if (riscv_has_ext(env, RVH)) { |
1740 | if (riscv_cpu_virt_enabled(env)) { | |
1741 | riscv_cpu_swap_hypervisor_regs(env); | |
1742 | } | |
1743 | env->mstatus = set_field(env->mstatus, MSTATUS_MPV, | |
284d697c | 1744 | riscv_cpu_virt_enabled(env)); |
9034e90a AF |
1745 | if (riscv_cpu_virt_enabled(env) && tval) { |
1746 | env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1); | |
1747 | } | |
5eb9e782 | 1748 | |
30675539 AF |
1749 | mtval2 = env->guest_phys_fault_addr; |
1750 | ||
5eb9e782 AF |
1751 | /* Trapping to M mode, virt is disabled */ |
1752 | riscv_cpu_set_virt_enabled(env, 0); | |
5eb9e782 AF |
1753 | } |
1754 | ||
1755 | s = env->mstatus; | |
1a9540d1 | 1756 | s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); |
0c3e702a MC |
1757 | s = set_field(s, MSTATUS_MPP, env->priv); |
1758 | s = set_field(s, MSTATUS_MIE, 0); | |
c7b95171 | 1759 | env->mstatus = s; |
acbbb94e MC |
1760 | env->mcause = cause | ~(((target_ulong)-1) >> async); |
1761 | env->mepc = env->pc; | |
ac12b601 | 1762 | env->mtval = tval; |
30675539 | 1763 | env->mtval2 = mtval2; |
8e2aa21b | 1764 | env->mtinst = tinst; |
acbbb94e MC |
1765 | env->pc = (env->mtvec >> 2 << 2) + |
1766 | ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); | |
fb738839 | 1767 | riscv_cpu_set_mode(env, PRV_M); |
0c3e702a | 1768 | } |
d9360e96 MC |
1769 | |
1770 | /* NOTE: it is not necessary to yield load reservations here. It is only | |
1771 | * necessary for an SC from "another hart" to cause a load reservation | |
1772 | * to be yielded. Refer to the memory consistency model section of the | |
1773 | * RISC-V ISA Specification. | |
1774 | */ | |
1775 | ||
ec352d0c | 1776 | env->two_stage_lookup = false; |
8e2aa21b | 1777 | env->two_stage_indirect_lookup = false; |
0c3e702a | 1778 | #endif |
330d2ae3 | 1779 | cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */ |
0c3e702a | 1780 | } |