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0c3e702a | 1 | /* |
df354dd4 | 2 | * RISC-V CPU helpers for qemu. |
0c3e702a MC |
3 | * |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
21 | #include "qemu/log.h" | |
7ec5d303 | 22 | #include "qemu/main-loop.h" |
0c3e702a | 23 | #include "cpu.h" |
c8f8a995 | 24 | #include "internals.h" |
892320fa | 25 | #include "pmu.h" |
0c3e702a | 26 | #include "exec/exec-all.h" |
8e2aa21b | 27 | #include "instmap.h" |
dcb32f1d | 28 | #include "tcg/tcg-op.h" |
929f0a7f | 29 | #include "trace.h" |
6b5fe137 | 30 | #include "semihosting/common-semi.h" |
2c9d7471 | 31 | #include "sysemu/cpu-timers.h" |
892320fa | 32 | #include "cpu_bits.h" |
2c9d7471 | 33 | #include "debug.h" |
70f168f8 | 34 | #include "tcg/oversized-guest.h" |
0c3e702a MC |
35 | |
36 | int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) | |
37 | { | |
38 | #ifdef CONFIG_USER_ONLY | |
39 | return 0; | |
40 | #else | |
696bacde RH |
41 | bool virt = env->virt_enabled; |
42 | int mode = env->priv; | |
c8f8a995 FW |
43 | |
44 | /* All priv -> mmu_idx mapping are here */ | |
696bacde | 45 | if (!ifetch) { |
eaecd473 RH |
46 | uint64_t status = env->mstatus; |
47 | ||
48 | if (mode == PRV_M && get_field(status, MSTATUS_MPRV)) { | |
696bacde | 49 | mode = get_field(env->mstatus, MSTATUS_MPP); |
869d76f2 WL |
50 | virt = get_field(env->mstatus, MSTATUS_MPV) && |
51 | (mode != PRV_M); | |
eaecd473 RH |
52 | if (virt) { |
53 | status = env->vsstatus; | |
54 | } | |
696bacde | 55 | } |
eaecd473 | 56 | if (mode == PRV_S && get_field(status, MSTATUS_SUM)) { |
696bacde RH |
57 | mode = MMUIdx_S_SUM; |
58 | } | |
c8f8a995 | 59 | } |
696bacde RH |
60 | |
61 | return mode | (virt ? MMU_2STAGE_BIT : 0); | |
0c3e702a MC |
62 | #endif |
63 | } | |
64 | ||
bb5de525 AJ |
65 | void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, |
66 | uint64_t *cs_base, uint32_t *pflags) | |
53677acf | 67 | { |
b4a99d40 FC |
68 | CPUState *cs = env_cpu(env); |
69 | RISCVCPU *cpu = RISCV_CPU(cs); | |
25f3ddff | 70 | RISCVExtStatus fs, vs; |
53677acf RH |
71 | uint32_t flags = 0; |
72 | ||
8c796f1a | 73 | *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc; |
53677acf RH |
74 | *cs_base = 0; |
75 | ||
3f4a5a53 | 76 | if (cpu->cfg.ext_zve32f) { |
a689a82b FC |
77 | /* |
78 | * If env->vl equals to VLMAX, we can use generic vector operation | |
79 | * expanders (GVEC) to accerlate the vector operations. | |
80 | * However, as LMUL could be a fractional number. The maximum | |
81 | * vector size can be operated might be less than 8 bytes, | |
82 | * which is not supported by GVEC. So we set vl_eq_vlmax flag to true | |
83 | * only when maxsz >= 8 bytes. | |
84 | */ | |
718942ae | 85 | uint32_t vlmax = vext_get_vlmax(cpu, env->vtype); |
a689a82b FC |
86 | uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW); |
87 | uint32_t maxsz = vlmax << sew; | |
88 | bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) && | |
89 | (maxsz >= 8); | |
d96a271a | 90 | flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); |
a689a82b | 91 | flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew); |
53677acf | 92 | flags = FIELD_DP32(flags, TB_FLAGS, LMUL, |
c45eff30 | 93 | FIELD_EX64(env->vtype, VTYPE, VLMUL)); |
53677acf | 94 | flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); |
f1eed927 | 95 | flags = FIELD_DP32(flags, TB_FLAGS, VTA, |
c45eff30 | 96 | FIELD_EX64(env->vtype, VTYPE, VTA)); |
355d5584 | 97 | flags = FIELD_DP32(flags, TB_FLAGS, VMA, |
c45eff30 | 98 | FIELD_EX64(env->vtype, VTYPE, VMA)); |
4acaa133 | 99 | flags = FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart == 0); |
53677acf RH |
100 | } else { |
101 | flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); | |
102 | } | |
103 | ||
104 | #ifdef CONFIG_USER_ONLY | |
25f3ddff RH |
105 | fs = EXT_STATUS_DIRTY; |
106 | vs = EXT_STATUS_DIRTY; | |
53677acf | 107 | #else |
47debc72 FW |
108 | flags = FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv); |
109 | ||
53677acf | 110 | flags |= cpu_mmu_index(env, 0); |
25f3ddff RH |
111 | fs = get_field(env->mstatus, MSTATUS_FS); |
112 | vs = get_field(env->mstatus, MSTATUS_VS); | |
61b4b69d | 113 | |
0f58cbbe RH |
114 | if (env->virt_enabled) { |
115 | flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1); | |
116 | /* | |
117 | * Merge DISABLED and !DIRTY states using MIN. | |
118 | * We will set both fields when dirtying. | |
119 | */ | |
120 | fs = MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS)); | |
121 | vs = MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS)); | |
53677acf | 122 | } |
0f58cbbe | 123 | |
e0b343b5 MC |
124 | /* With Zfinx, floating point is enabled/disabled by Smstateen. */ |
125 | if (!riscv_has_ext(env, RVF)) { | |
126 | fs = (smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR) == RISCV_EXCP_NONE) | |
127 | ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED; | |
128 | } | |
129 | ||
cdfb2905 | 130 | if (cpu->cfg.debug && !icount_enabled()) { |
577f0286 | 131 | flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled); |
2c9d7471 | 132 | } |
53677acf RH |
133 | #endif |
134 | ||
25f3ddff RH |
135 | flags = FIELD_DP32(flags, TB_FLAGS, FS, fs); |
136 | flags = FIELD_DP32(flags, TB_FLAGS, VS, vs); | |
440544e1 | 137 | flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl); |
b83e4f1d | 138 | if (env->cur_pmmask != 0) { |
4208dc7e LZ |
139 | flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); |
140 | } | |
141 | if (env->cur_pmbase != 0) { | |
142 | flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1); | |
143 | } | |
92371bd9 | 144 | |
53677acf RH |
145 | *pflags = flags; |
146 | } | |
147 | ||
40bfa5f6 LZ |
148 | void riscv_cpu_update_mask(CPURISCVState *env) |
149 | { | |
b83e4f1d | 150 | target_ulong mask = 0, base = 0; |
40bfa5f6 LZ |
151 | /* |
152 | * TODO: Current RVJ spec does not specify | |
153 | * how the extension interacts with XLEN. | |
154 | */ | |
155 | #ifndef CONFIG_USER_ONLY | |
156 | if (riscv_has_ext(env, RVJ)) { | |
157 | switch (env->priv) { | |
158 | case PRV_M: | |
159 | if (env->mmte & M_PM_ENABLE) { | |
160 | mask = env->mpmmask; | |
161 | base = env->mpmbase; | |
162 | } | |
163 | break; | |
164 | case PRV_S: | |
165 | if (env->mmte & S_PM_ENABLE) { | |
166 | mask = env->spmmask; | |
167 | base = env->spmbase; | |
168 | } | |
169 | break; | |
170 | case PRV_U: | |
171 | if (env->mmte & U_PM_ENABLE) { | |
172 | mask = env->upmmask; | |
173 | base = env->upmbase; | |
174 | } | |
175 | break; | |
176 | default: | |
177 | g_assert_not_reached(); | |
178 | } | |
179 | } | |
180 | #endif | |
181 | if (env->xl == MXL_RV32) { | |
182 | env->cur_pmmask = mask & UINT32_MAX; | |
183 | env->cur_pmbase = base & UINT32_MAX; | |
184 | } else { | |
185 | env->cur_pmmask = mask; | |
186 | env->cur_pmbase = base; | |
187 | } | |
188 | } | |
189 | ||
0c3e702a | 190 | #ifndef CONFIG_USER_ONLY |
43dc93af AP |
191 | |
192 | /* | |
193 | * The HS-mode is allowed to configure priority only for the | |
194 | * following VS-mode local interrupts: | |
195 | * | |
196 | * 0 (Reserved interrupt, reads as zero) | |
197 | * 1 Supervisor software interrupt | |
198 | * 4 (Reserved interrupt, reads as zero) | |
199 | * 5 Supervisor timer interrupt | |
200 | * 8 (Reserved interrupt, reads as zero) | |
201 | * 13 (Reserved interrupt) | |
202 | * 14 " | |
203 | * 15 " | |
204 | * 16 " | |
43577499 AP |
205 | * 17 " |
206 | * 18 " | |
207 | * 19 " | |
208 | * 20 " | |
209 | * 21 " | |
43dc93af | 210 | * 22 " |
43577499 | 211 | * 23 " |
43dc93af AP |
212 | */ |
213 | ||
214 | static const int hviprio_index2irq[] = { | |
43577499 | 215 | 0, 1, 4, 5, 8, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 }; |
43dc93af AP |
216 | static const int hviprio_index2rdzero[] = { |
217 | 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; | |
218 | ||
219 | int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero) | |
0c3e702a | 220 | { |
43dc93af AP |
221 | if (index < 0 || ARRAY_SIZE(hviprio_index2irq) <= index) { |
222 | return -EINVAL; | |
223 | } | |
3ef10a09 | 224 | |
43dc93af AP |
225 | if (out_irq) { |
226 | *out_irq = hviprio_index2irq[index]; | |
227 | } | |
3ef10a09 | 228 | |
43dc93af AP |
229 | if (out_rdzero) { |
230 | *out_rdzero = hviprio_index2rdzero[index]; | |
231 | } | |
cd032fe7 | 232 | |
43dc93af AP |
233 | return 0; |
234 | } | |
3ef10a09 | 235 | |
43dc93af AP |
236 | /* |
237 | * Default priorities of local interrupts are defined in the | |
238 | * RISC-V Advanced Interrupt Architecture specification. | |
239 | * | |
240 | * ---------------------------------------------------------------- | |
241 | * Default | | |
242 | * Priority | Major Interrupt Numbers | |
243 | * ---------------------------------------------------------------- | |
43577499 AP |
244 | * Highest | 47, 23, 46, 45, 22, 44, |
245 | * | 43, 21, 42, 41, 20, 40 | |
43dc93af AP |
246 | * | |
247 | * | 11 (0b), 3 (03), 7 (07) | |
248 | * | 9 (09), 1 (01), 5 (05) | |
249 | * | 12 (0c) | |
250 | * | 10 (0a), 2 (02), 6 (06) | |
251 | * | | |
43577499 AP |
252 | * | 39, 19, 38, 37, 18, 36, |
253 | * Lowest | 35, 17, 34, 33, 16, 32 | |
43dc93af AP |
254 | * ---------------------------------------------------------------- |
255 | */ | |
256 | static const uint8_t default_iprio[64] = { | |
c45eff30 WL |
257 | /* Custom interrupts 48 to 63 */ |
258 | [63] = IPRIO_MMAXIPRIO, | |
259 | [62] = IPRIO_MMAXIPRIO, | |
260 | [61] = IPRIO_MMAXIPRIO, | |
261 | [60] = IPRIO_MMAXIPRIO, | |
262 | [59] = IPRIO_MMAXIPRIO, | |
263 | [58] = IPRIO_MMAXIPRIO, | |
264 | [57] = IPRIO_MMAXIPRIO, | |
265 | [56] = IPRIO_MMAXIPRIO, | |
266 | [55] = IPRIO_MMAXIPRIO, | |
267 | [54] = IPRIO_MMAXIPRIO, | |
268 | [53] = IPRIO_MMAXIPRIO, | |
269 | [52] = IPRIO_MMAXIPRIO, | |
270 | [51] = IPRIO_MMAXIPRIO, | |
271 | [50] = IPRIO_MMAXIPRIO, | |
272 | [49] = IPRIO_MMAXIPRIO, | |
273 | [48] = IPRIO_MMAXIPRIO, | |
274 | ||
275 | /* Custom interrupts 24 to 31 */ | |
276 | [31] = IPRIO_MMAXIPRIO, | |
277 | [30] = IPRIO_MMAXIPRIO, | |
278 | [29] = IPRIO_MMAXIPRIO, | |
279 | [28] = IPRIO_MMAXIPRIO, | |
280 | [27] = IPRIO_MMAXIPRIO, | |
281 | [26] = IPRIO_MMAXIPRIO, | |
282 | [25] = IPRIO_MMAXIPRIO, | |
283 | [24] = IPRIO_MMAXIPRIO, | |
284 | ||
285 | [47] = IPRIO_DEFAULT_UPPER, | |
286 | [23] = IPRIO_DEFAULT_UPPER + 1, | |
287 | [46] = IPRIO_DEFAULT_UPPER + 2, | |
288 | [45] = IPRIO_DEFAULT_UPPER + 3, | |
289 | [22] = IPRIO_DEFAULT_UPPER + 4, | |
290 | [44] = IPRIO_DEFAULT_UPPER + 5, | |
291 | ||
292 | [43] = IPRIO_DEFAULT_UPPER + 6, | |
293 | [21] = IPRIO_DEFAULT_UPPER + 7, | |
294 | [42] = IPRIO_DEFAULT_UPPER + 8, | |
295 | [41] = IPRIO_DEFAULT_UPPER + 9, | |
296 | [20] = IPRIO_DEFAULT_UPPER + 10, | |
297 | [40] = IPRIO_DEFAULT_UPPER + 11, | |
298 | ||
299 | [11] = IPRIO_DEFAULT_M, | |
300 | [3] = IPRIO_DEFAULT_M + 1, | |
301 | [7] = IPRIO_DEFAULT_M + 2, | |
302 | ||
303 | [9] = IPRIO_DEFAULT_S, | |
304 | [1] = IPRIO_DEFAULT_S + 1, | |
305 | [5] = IPRIO_DEFAULT_S + 2, | |
306 | ||
307 | [12] = IPRIO_DEFAULT_SGEXT, | |
308 | ||
309 | [10] = IPRIO_DEFAULT_VS, | |
310 | [2] = IPRIO_DEFAULT_VS + 1, | |
311 | [6] = IPRIO_DEFAULT_VS + 2, | |
312 | ||
313 | [39] = IPRIO_DEFAULT_LOWER, | |
314 | [19] = IPRIO_DEFAULT_LOWER + 1, | |
315 | [38] = IPRIO_DEFAULT_LOWER + 2, | |
316 | [37] = IPRIO_DEFAULT_LOWER + 3, | |
317 | [18] = IPRIO_DEFAULT_LOWER + 4, | |
318 | [36] = IPRIO_DEFAULT_LOWER + 5, | |
319 | ||
320 | [35] = IPRIO_DEFAULT_LOWER + 6, | |
321 | [17] = IPRIO_DEFAULT_LOWER + 7, | |
322 | [34] = IPRIO_DEFAULT_LOWER + 8, | |
323 | [33] = IPRIO_DEFAULT_LOWER + 9, | |
324 | [16] = IPRIO_DEFAULT_LOWER + 10, | |
325 | [32] = IPRIO_DEFAULT_LOWER + 11, | |
43dc93af AP |
326 | }; |
327 | ||
328 | uint8_t riscv_cpu_default_priority(int irq) | |
329 | { | |
330 | if (irq < 0 || irq > 63) { | |
331 | return IPRIO_MMAXIPRIO; | |
332 | } | |
333 | ||
334 | return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO; | |
335 | }; | |
336 | ||
337 | static int riscv_cpu_pending_to_irq(CPURISCVState *env, | |
338 | int extirq, unsigned int extirq_def_prio, | |
339 | uint64_t pending, uint8_t *iprio) | |
340 | { | |
341 | int irq, best_irq = RISCV_EXCP_NONE; | |
342 | unsigned int prio, best_prio = UINT_MAX; | |
343 | ||
344 | if (!pending) { | |
345 | return RISCV_EXCP_NONE; | |
346 | } | |
347 | ||
348 | irq = ctz64(pending); | |
9c33e08b WL |
349 | if (!((extirq == IRQ_M_EXT) ? riscv_cpu_cfg(env)->ext_smaia : |
350 | riscv_cpu_cfg(env)->ext_ssaia)) { | |
43dc93af AP |
351 | return irq; |
352 | } | |
353 | ||
354 | pending = pending >> irq; | |
355 | while (pending) { | |
356 | prio = iprio[irq]; | |
357 | if (!prio) { | |
358 | if (irq == extirq) { | |
359 | prio = extirq_def_prio; | |
360 | } else { | |
361 | prio = (riscv_cpu_default_priority(irq) < extirq_def_prio) ? | |
362 | 1 : IPRIO_MMAXIPRIO; | |
363 | } | |
364 | } | |
365 | if ((pending & 0x1) && (prio <= best_prio)) { | |
366 | best_irq = irq; | |
367 | best_prio = prio; | |
368 | } | |
369 | irq++; | |
370 | pending = pending >> 1; | |
371 | } | |
372 | ||
373 | return best_irq; | |
374 | } | |
375 | ||
8f42415f | 376 | uint64_t riscv_cpu_all_pending(CPURISCVState *env) |
43dc93af AP |
377 | { |
378 | uint32_t gein = get_field(env->hstatus, HSTATUS_VGEIN); | |
379 | uint64_t vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; | |
3ec0fe18 | 380 | uint64_t vstip = (env->vstime_irq) ? MIP_VSTIP : 0; |
43dc93af | 381 | |
3ec0fe18 | 382 | return (env->mip | vsgein | vstip) & env->mie; |
43dc93af AP |
383 | } |
384 | ||
385 | int riscv_cpu_mirq_pending(CPURISCVState *env) | |
386 | { | |
387 | uint64_t irqs = riscv_cpu_all_pending(env) & ~env->mideleg & | |
388 | ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); | |
389 | ||
390 | return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, | |
391 | irqs, env->miprio); | |
392 | } | |
393 | ||
394 | int riscv_cpu_sirq_pending(CPURISCVState *env) | |
395 | { | |
396 | uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & | |
397 | ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); | |
398 | ||
399 | return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, | |
400 | irqs, env->siprio); | |
401 | } | |
402 | ||
403 | int riscv_cpu_vsirq_pending(CPURISCVState *env) | |
404 | { | |
405 | uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & | |
406 | (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); | |
407 | ||
408 | return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, | |
409 | irqs >> 1, env->hviprio); | |
410 | } | |
411 | ||
412 | static int riscv_cpu_local_irq_pending(CPURISCVState *env) | |
413 | { | |
414 | int virq; | |
415 | uint64_t irqs, pending, mie, hsie, vsie; | |
416 | ||
417 | /* Determine interrupt enable state of all privilege modes */ | |
38256529 | 418 | if (env->virt_enabled) { |
43dc93af AP |
419 | mie = 1; |
420 | hsie = 1; | |
421 | vsie = (env->priv < PRV_S) || | |
422 | (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE)); | |
0c3e702a | 423 | } else { |
43dc93af AP |
424 | mie = (env->priv < PRV_M) || |
425 | (env->priv == PRV_M && get_field(env->mstatus, MSTATUS_MIE)); | |
426 | hsie = (env->priv < PRV_S) || | |
427 | (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE)); | |
428 | vsie = 0; | |
429 | } | |
430 | ||
431 | /* Determine all pending interrupts */ | |
432 | pending = riscv_cpu_all_pending(env); | |
433 | ||
434 | /* Check M-mode interrupts */ | |
435 | irqs = pending & ~env->mideleg & -mie; | |
436 | if (irqs) { | |
437 | return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, | |
438 | irqs, env->miprio); | |
439 | } | |
440 | ||
441 | /* Check HS-mode interrupts */ | |
442 | irqs = pending & env->mideleg & ~env->hideleg & -hsie; | |
443 | if (irqs) { | |
444 | return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, | |
445 | irqs, env->siprio); | |
0c3e702a | 446 | } |
43dc93af AP |
447 | |
448 | /* Check VS-mode interrupts */ | |
449 | irqs = pending & env->mideleg & env->hideleg & -vsie; | |
450 | if (irqs) { | |
451 | virq = riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, | |
452 | irqs >> 1, env->hviprio); | |
453 | return (virq <= 0) ? virq : virq + 1; | |
454 | } | |
455 | ||
456 | /* Indicate no pending interrupt */ | |
457 | return RISCV_EXCP_NONE; | |
0c3e702a | 458 | } |
0c3e702a MC |
459 | |
460 | bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) | |
461 | { | |
0c3e702a MC |
462 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
463 | RISCVCPU *cpu = RISCV_CPU(cs); | |
464 | CPURISCVState *env = &cpu->env; | |
efbdbc26 | 465 | int interruptno = riscv_cpu_local_irq_pending(env); |
0c3e702a MC |
466 | if (interruptno >= 0) { |
467 | cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno; | |
468 | riscv_cpu_do_interrupt(cs); | |
469 | return true; | |
470 | } | |
471 | } | |
0c3e702a MC |
472 | return false; |
473 | } | |
474 | ||
b345b480 AF |
475 | /* Return true is floating point support is currently enabled */ |
476 | bool riscv_cpu_fp_enabled(CPURISCVState *env) | |
477 | { | |
478 | if (env->mstatus & MSTATUS_FS) { | |
38256529 | 479 | if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_FS)) { |
29409c1d AF |
480 | return false; |
481 | } | |
b345b480 AF |
482 | return true; |
483 | } | |
484 | ||
485 | return false; | |
486 | } | |
487 | ||
61b4b69d LZ |
488 | /* Return true is vector support is currently enabled */ |
489 | bool riscv_cpu_vector_enabled(CPURISCVState *env) | |
490 | { | |
491 | if (env->mstatus & MSTATUS_VS) { | |
38256529 | 492 | if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_VS)) { |
61b4b69d LZ |
493 | return false; |
494 | } | |
495 | return true; | |
496 | } | |
497 | ||
498 | return false; | |
499 | } | |
500 | ||
66e594f2 AF |
501 | void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) |
502 | { | |
c163b3ba | 503 | uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | |
284d697c | 504 | MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | |
61b4b69d | 505 | MSTATUS64_UXL | MSTATUS_VS; |
c163b3ba WL |
506 | |
507 | if (riscv_has_ext(env, RVF)) { | |
508 | mstatus_mask |= MSTATUS_FS; | |
509 | } | |
38256529 | 510 | bool current_virt = env->virt_enabled; |
66e594f2 AF |
511 | |
512 | g_assert(riscv_has_ext(env, RVH)); | |
513 | ||
66e594f2 AF |
514 | if (current_virt) { |
515 | /* Current V=1 and we are about to change to V=0 */ | |
516 | env->vsstatus = env->mstatus & mstatus_mask; | |
517 | env->mstatus &= ~mstatus_mask; | |
518 | env->mstatus |= env->mstatus_hs; | |
519 | ||
520 | env->vstvec = env->stvec; | |
521 | env->stvec = env->stvec_hs; | |
522 | ||
523 | env->vsscratch = env->sscratch; | |
524 | env->sscratch = env->sscratch_hs; | |
525 | ||
526 | env->vsepc = env->sepc; | |
527 | env->sepc = env->sepc_hs; | |
528 | ||
529 | env->vscause = env->scause; | |
530 | env->scause = env->scause_hs; | |
531 | ||
ac12b601 AP |
532 | env->vstval = env->stval; |
533 | env->stval = env->stval_hs; | |
66e594f2 AF |
534 | |
535 | env->vsatp = env->satp; | |
536 | env->satp = env->satp_hs; | |
537 | } else { | |
538 | /* Current V=0 and we are about to change to V=1 */ | |
539 | env->mstatus_hs = env->mstatus & mstatus_mask; | |
540 | env->mstatus &= ~mstatus_mask; | |
541 | env->mstatus |= env->vsstatus; | |
542 | ||
543 | env->stvec_hs = env->stvec; | |
544 | env->stvec = env->vstvec; | |
545 | ||
546 | env->sscratch_hs = env->sscratch; | |
547 | env->sscratch = env->vsscratch; | |
548 | ||
549 | env->sepc_hs = env->sepc; | |
550 | env->sepc = env->vsepc; | |
551 | ||
552 | env->scause_hs = env->scause; | |
553 | env->scause = env->vscause; | |
554 | ||
ac12b601 AP |
555 | env->stval_hs = env->stval; |
556 | env->stval = env->vstval; | |
66e594f2 AF |
557 | |
558 | env->satp_hs = env->satp; | |
559 | env->satp = env->vsatp; | |
560 | } | |
561 | } | |
562 | ||
cd032fe7 AP |
563 | target_ulong riscv_cpu_get_geilen(CPURISCVState *env) |
564 | { | |
565 | if (!riscv_has_ext(env, RVH)) { | |
566 | return 0; | |
567 | } | |
568 | ||
569 | return env->geilen; | |
570 | } | |
571 | ||
572 | void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen) | |
573 | { | |
574 | if (!riscv_has_ext(env, RVH)) { | |
575 | return; | |
576 | } | |
577 | ||
578 | if (geilen > (TARGET_LONG_BITS - 1)) { | |
579 | return; | |
580 | } | |
581 | ||
582 | env->geilen = geilen; | |
583 | } | |
584 | ||
c43732f5 | 585 | /* This function can only be called to set virt when RVH is enabled */ |
ef6bb7b6 AF |
586 | void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) |
587 | { | |
eccc5a12 | 588 | /* Flush the TLB on all virt mode changes. */ |
b3c5077b | 589 | if (env->virt_enabled != enable) { |
eccc5a12 AF |
590 | tlb_flush(env_cpu(env)); |
591 | } | |
592 | ||
b3c5077b | 593 | env->virt_enabled = enable; |
02d9565b AP |
594 | |
595 | if (enable) { | |
596 | /* | |
597 | * The guest external interrupts from an interrupt controller are | |
598 | * delivered only when the Guest/VM is running (i.e. V=1). This means | |
599 | * any guest external interrupt which is triggered while the Guest/VM | |
600 | * is not running (i.e. V=0) will be missed on QEMU resulting in guest | |
601 | * with sluggish response to serial console input and other I/O events. | |
602 | * | |
603 | * To solve this, we check and inject interrupt after setting V=1. | |
604 | */ | |
bbb9fc25 | 605 | riscv_cpu_update_mip(env, 0, 0); |
02d9565b | 606 | } |
ef6bb7b6 AF |
607 | } |
608 | ||
d028ac75 | 609 | int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts) |
e3e7039c MC |
610 | { |
611 | CPURISCVState *env = &cpu->env; | |
612 | if (env->miclaim & interrupts) { | |
613 | return -1; | |
614 | } else { | |
615 | env->miclaim |= interrupts; | |
616 | return 0; | |
617 | } | |
618 | } | |
619 | ||
bbb9fc25 WL |
620 | uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, |
621 | uint64_t value) | |
df354dd4 | 622 | { |
bbb9fc25 | 623 | CPUState *cs = env_cpu(env); |
3ec0fe18 | 624 | uint64_t gein, vsgein = 0, vstip = 0, old = env->mip; |
7ec5d303 | 625 | |
38256529 | 626 | if (env->virt_enabled) { |
cd032fe7 AP |
627 | gein = get_field(env->hstatus, HSTATUS_VGEIN); |
628 | vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; | |
629 | } | |
630 | ||
3ec0fe18 AP |
631 | vstip = env->vstime_irq ? MIP_VSTIP : 0; |
632 | ||
b3eb5b86 | 633 | QEMU_IOTHREAD_LOCK_GUARD(); |
df354dd4 | 634 | |
7ec5d303 | 635 | env->mip = (env->mip & ~mask) | (value & mask); |
df354dd4 | 636 | |
3ec0fe18 | 637 | if (env->mip | vsgein | vstip) { |
7ec5d303 AF |
638 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
639 | } else { | |
640 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); | |
641 | } | |
0a01f2ee | 642 | |
df354dd4 MC |
643 | return old; |
644 | } | |
645 | ||
e2f01f3c FC |
646 | void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), |
647 | void *arg) | |
c6957248 AP |
648 | { |
649 | env->rdtime_fn = fn; | |
a47ef6e9 | 650 | env->rdtime_fn_arg = arg; |
c6957248 AP |
651 | } |
652 | ||
69077dd6 AP |
653 | void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, |
654 | int (*rmw_fn)(void *arg, | |
655 | target_ulong reg, | |
656 | target_ulong *val, | |
657 | target_ulong new_val, | |
658 | target_ulong write_mask), | |
659 | void *rmw_fn_arg) | |
660 | { | |
661 | if (priv <= PRV_M) { | |
662 | env->aia_ireg_rmw_fn[priv] = rmw_fn; | |
663 | env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg; | |
664 | } | |
665 | } | |
666 | ||
fb738839 | 667 | void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) |
df354dd4 | 668 | { |
0c98ccef WL |
669 | g_assert(newpriv <= PRV_M && newpriv != PRV_RESERVED); |
670 | ||
5a4ae64c LZ |
671 | if (icount_enabled() && newpriv != env->priv) { |
672 | riscv_itrigger_update_priv(env); | |
673 | } | |
df354dd4 MC |
674 | /* tlb_flush is unnecessary as mode is contained in mmu_idx */ |
675 | env->priv = newpriv; | |
440544e1 | 676 | env->xl = cpu_recompute_xl(env); |
40bfa5f6 | 677 | riscv_cpu_update_mask(env); |
c13b169f JS |
678 | |
679 | /* | |
680 | * Clear the load reservation - otherwise a reservation placed in one | |
681 | * context/process can be used by another, resulting in an SC succeeding | |
682 | * incorrectly. Version 2.2 of the ISA specification explicitly requires | |
683 | * this behaviour, while later revisions say that the kernel "should" use | |
684 | * an SC instruction to force the yielding of a load reservation on a | |
685 | * preemptive context switch. As a result, do both. | |
686 | */ | |
687 | env->load_res = -1; | |
df354dd4 MC |
688 | } |
689 | ||
b297129a JS |
690 | /* |
691 | * get_physical_address_pmp - check PMP permission for this physical address | |
692 | * | |
693 | * Match the PMP region and check permission for this physical address and it's | |
694 | * TLB page. Returns 0 if the permission checking was successful | |
695 | * | |
696 | * @env: CPURISCVState | |
697 | * @prot: The returned protection attributes | |
b297129a JS |
698 | * @addr: The physical address to be checked permission |
699 | * @access_type: The type of MMU access | |
700 | * @mode: Indicates current privilege level. | |
701 | */ | |
bfc7ee12 | 702 | static int get_physical_address_pmp(CPURISCVState *env, int *prot, hwaddr addr, |
b297129a JS |
703 | int size, MMUAccessType access_type, |
704 | int mode) | |
705 | { | |
706 | pmp_priv_t pmp_priv; | |
e9c39713 | 707 | bool pmp_has_privs; |
b297129a | 708 | |
3fe40ef5 | 709 | if (!riscv_cpu_cfg(env)->pmp) { |
b297129a JS |
710 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
711 | return TRANSLATE_SUCCESS; | |
712 | } | |
713 | ||
e9c39713 WL |
714 | pmp_has_privs = pmp_hart_has_privs(env, addr, size, 1 << access_type, |
715 | &pmp_priv, mode); | |
716 | if (!pmp_has_privs) { | |
b297129a JS |
717 | *prot = 0; |
718 | return TRANSLATE_PMP_FAIL; | |
719 | } | |
720 | ||
721 | *prot = pmp_priv_to_page_prot(pmp_priv); | |
b297129a JS |
722 | |
723 | return TRANSLATE_SUCCESS; | |
724 | } | |
725 | ||
3b57254d WL |
726 | /* |
727 | * get_physical_address - get the physical address for this virtual address | |
0c3e702a MC |
728 | * |
729 | * Do a page table walk to obtain the physical address corresponding to a | |
730 | * virtual address. Returns 0 if the translation was successful | |
731 | * | |
732 | * Adapted from Spike's mmu_t::translate and mmu_t::walk | |
733 | * | |
1448689c AF |
734 | * @env: CPURISCVState |
735 | * @physical: This will be set to the calculated physical address | |
736 | * @prot: The returned protection attributes | |
77dff650 | 737 | * @addr: The virtual address or guest physical address to be translated |
33a9a57d YJ |
738 | * @fault_pte_addr: If not NULL, this will be set to fault pte address |
739 | * when a error occurs on pte address translation. | |
740 | * This will already be shifted to match htval. | |
1448689c AF |
741 | * @access_type: The type of MMU access |
742 | * @mmu_idx: Indicates current privilege level | |
743 | * @first_stage: Are we in first stage translation? | |
744 | * Second stage is used for hypervisor guest translation | |
36a18664 | 745 | * @two_stage: Are we going to perform two stage translation |
11c27c6d | 746 | * @is_debug: Is this access from a debugger or the monitor? |
0c3e702a MC |
747 | */ |
748 | static int get_physical_address(CPURISCVState *env, hwaddr *physical, | |
e1dd1507 | 749 | int *ret_prot, vaddr addr, |
33a9a57d | 750 | target_ulong *fault_pte_addr, |
1448689c | 751 | int access_type, int mmu_idx, |
11c27c6d JF |
752 | bool first_stage, bool two_stage, |
753 | bool is_debug) | |
0c3e702a | 754 | { |
3b57254d WL |
755 | /* |
756 | * NOTE: the env->pc value visible here will not be | |
0c3e702a | 757 | * correct, but the value visible to the exception handler |
3b57254d WL |
758 | * (riscv_cpu_do_interrupt) is correct |
759 | */ | |
aacb578f PD |
760 | MemTxResult res; |
761 | MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; | |
340b5805 | 762 | int mode = mmuidx_priv(mmu_idx); |
36a18664 | 763 | bool use_background = false; |
05e6ca5e | 764 | hwaddr ppn; |
2bacb224 WL |
765 | int napot_bits = 0; |
766 | target_ulong napot_mask; | |
0c3e702a | 767 | |
36a18664 AF |
768 | /* |
769 | * Check if we should use the background registers for the two | |
770 | * stage translation. We don't need to check if we actually need | |
771 | * two stage translation as that happened before this function | |
772 | * was called. Background registers will be used if the guest has | |
773 | * forced a two stage translation to be on (in HS or M mode). | |
774 | */ | |
38256529 | 775 | if (!env->virt_enabled && two_stage) { |
29b3361b AF |
776 | use_background = true; |
777 | } | |
778 | ||
dcf654a3 | 779 | if (mode == PRV_M || !riscv_cpu_cfg(env)->mmu) { |
0c3e702a | 780 | *physical = addr; |
e1dd1507 | 781 | *ret_prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
0c3e702a MC |
782 | return TRANSLATE_SUCCESS; |
783 | } | |
784 | ||
e1dd1507 | 785 | *ret_prot = 0; |
0c3e702a | 786 | |
ddf78132 | 787 | hwaddr base; |
38303e8a | 788 | int levels, ptidxbits, ptesize, vm, widened; |
0c3e702a | 789 | |
1a9540d1 AF |
790 | if (first_stage == true) { |
791 | if (use_background) { | |
db23e5d9 | 792 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
419ddf00 AF |
793 | base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT; |
794 | vm = get_field(env->vsatp, SATP32_MODE); | |
795 | } else { | |
796 | base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT; | |
797 | vm = get_field(env->vsatp, SATP64_MODE); | |
798 | } | |
36a18664 | 799 | } else { |
db23e5d9 | 800 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
419ddf00 AF |
801 | base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; |
802 | vm = get_field(env->satp, SATP32_MODE); | |
803 | } else { | |
804 | base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT; | |
805 | vm = get_field(env->satp, SATP64_MODE); | |
806 | } | |
0c3e702a | 807 | } |
36a18664 | 808 | widened = 0; |
1a9540d1 | 809 | } else { |
db23e5d9 | 810 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
994b6bb2 AF |
811 | base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT; |
812 | vm = get_field(env->hgatp, SATP32_MODE); | |
813 | } else { | |
814 | base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT; | |
815 | vm = get_field(env->hgatp, SATP64_MODE); | |
816 | } | |
1a9540d1 AF |
817 | widened = 2; |
818 | } | |
38303e8a | 819 | |
1a9540d1 AF |
820 | switch (vm) { |
821 | case VM_1_10_SV32: | |
822 | levels = 2; ptidxbits = 10; ptesize = 4; break; | |
823 | case VM_1_10_SV39: | |
824 | levels = 3; ptidxbits = 9; ptesize = 8; break; | |
825 | case VM_1_10_SV48: | |
826 | levels = 4; ptidxbits = 9; ptesize = 8; break; | |
827 | case VM_1_10_SV57: | |
828 | levels = 5; ptidxbits = 9; ptesize = 8; break; | |
829 | case VM_1_10_MBARE: | |
830 | *physical = addr; | |
e1dd1507 | 831 | *ret_prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
1a9540d1 AF |
832 | return TRANSLATE_SUCCESS; |
833 | default: | |
834 | g_assert_not_reached(); | |
0c3e702a MC |
835 | } |
836 | ||
3109cd98 | 837 | CPUState *cs = env_cpu(env); |
36a18664 | 838 | int va_bits = PGSHIFT + levels * ptidxbits + widened; |
36a18664 | 839 | |
7bf14a2f IR |
840 | if (first_stage == true) { |
841 | target_ulong mask, masked_msbs; | |
36a18664 | 842 | |
7bf14a2f IR |
843 | if (TARGET_LONG_BITS > (va_bits - 1)) { |
844 | mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; | |
845 | } else { | |
846 | mask = 0; | |
847 | } | |
848 | masked_msbs = (addr >> (va_bits - 1)) & mask; | |
849 | ||
850 | if (masked_msbs != 0 && masked_msbs != mask) { | |
851 | return TRANSLATE_FAIL; | |
852 | } | |
853 | } else { | |
854 | if (vm != VM_1_10_SV32 && addr >> va_bits != 0) { | |
855 | return TRANSLATE_FAIL; | |
856 | } | |
0c3e702a MC |
857 | } |
858 | ||
8d6a00cd RH |
859 | bool pbmte = env->menvcfg & MENVCFG_PBMTE; |
860 | bool hade = env->menvcfg & MENVCFG_HADE; | |
861 | ||
862 | if (first_stage && two_stage && env->virt_enabled) { | |
863 | pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE); | |
864 | hade = hade && (env->henvcfg & HENVCFG_HADE); | |
865 | } | |
866 | ||
0c3e702a | 867 | int ptshift = (levels - 1) * ptidxbits; |
59688aa0 RH |
868 | target_ulong pte; |
869 | hwaddr pte_addr; | |
0c3e702a MC |
870 | int i; |
871 | ||
872 | #if !TCG_OVERSIZED_GUEST | |
873 | restart: | |
874 | #endif | |
875 | for (i = 0; i < levels; i++, ptshift -= ptidxbits) { | |
36a18664 AF |
876 | target_ulong idx; |
877 | if (i == 0) { | |
878 | idx = (addr >> (PGSHIFT + ptshift)) & | |
879 | ((1 << (ptidxbits + widened)) - 1); | |
880 | } else { | |
881 | idx = (addr >> (PGSHIFT + ptshift)) & | |
0c3e702a | 882 | ((1 << ptidxbits) - 1); |
36a18664 | 883 | } |
0c3e702a MC |
884 | |
885 | /* check that physical address of PTE is legal */ | |
36a18664 AF |
886 | |
887 | if (two_stage && first_stage) { | |
38472890 | 888 | int vbase_prot; |
36a18664 AF |
889 | hwaddr vbase; |
890 | ||
891 | /* Do the second stage translation on the base PTE address. */ | |
88914473 | 892 | int vbase_ret = get_physical_address(env, &vbase, &vbase_prot, |
33a9a57d | 893 | base, NULL, MMU_DATA_LOAD, |
a427c836 | 894 | MMUIdx_U, false, true, |
11c27c6d | 895 | is_debug); |
88914473 AF |
896 | |
897 | if (vbase_ret != TRANSLATE_SUCCESS) { | |
33a9a57d YJ |
898 | if (fault_pte_addr) { |
899 | *fault_pte_addr = (base + idx * ptesize) >> 2; | |
900 | } | |
901 | return TRANSLATE_G_STAGE_FAIL; | |
88914473 | 902 | } |
36a18664 AF |
903 | |
904 | pte_addr = vbase + idx * ptesize; | |
905 | } else { | |
906 | pte_addr = base + idx * ptesize; | |
907 | } | |
1f447aec | 908 | |
b297129a | 909 | int pmp_prot; |
bfc7ee12 | 910 | int pmp_ret = get_physical_address_pmp(env, &pmp_prot, pte_addr, |
b297129a JS |
911 | sizeof(target_ulong), |
912 | MMU_DATA_LOAD, PRV_S); | |
913 | if (pmp_ret != TRANSLATE_SUCCESS) { | |
1f447aec HA |
914 | return TRANSLATE_PMP_FAIL; |
915 | } | |
aacb578f | 916 | |
db23e5d9 | 917 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
f08c7ff3 AF |
918 | pte = address_space_ldl(cs->as, pte_addr, attrs, &res); |
919 | } else { | |
920 | pte = address_space_ldq(cs->as, pte_addr, attrs, &res); | |
921 | } | |
922 | ||
aacb578f PD |
923 | if (res != MEMTX_OK) { |
924 | return TRANSLATE_FAIL; | |
925 | } | |
926 | ||
05e6ca5e GR |
927 | if (riscv_cpu_sxl(env) == MXL_RV32) { |
928 | ppn = pte >> PTE_PPN_SHIFT; | |
05e6ca5e | 929 | } else { |
190e9f8e AG |
930 | if (pte & PTE_RESERVED) { |
931 | return TRANSLATE_FAIL; | |
932 | } | |
933 | ||
934 | if (!pbmte && (pte & PTE_PBMT)) { | |
05e6ca5e GR |
935 | return TRANSLATE_FAIL; |
936 | } | |
190e9f8e AG |
937 | |
938 | if (!riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { | |
939 | return TRANSLATE_FAIL; | |
940 | } | |
941 | ||
942 | ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT; | |
05e6ca5e | 943 | } |
0c3e702a | 944 | |
c3b03e58 MC |
945 | if (!(pte & PTE_V)) { |
946 | /* Invalid PTE */ | |
947 | return TRANSLATE_FAIL; | |
59688aa0 RH |
948 | } |
949 | if (pte & (PTE_R | PTE_W | PTE_X)) { | |
950 | goto leaf; | |
951 | } | |
952 | ||
953 | /* Inner PTE, continue walking */ | |
954 | if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) { | |
c3b03e58 | 955 | return TRANSLATE_FAIL; |
59688aa0 RH |
956 | } |
957 | base = ppn << PGSHIFT; | |
958 | } | |
959 | ||
960 | /* No leaf pte at any translation level. */ | |
961 | return TRANSLATE_FAIL; | |
962 | ||
963 | leaf: | |
964 | if (ppn & ((1ULL << ptshift) - 1)) { | |
965 | /* Misaligned PPN */ | |
966 | return TRANSLATE_FAIL; | |
967 | } | |
968 | if (!pbmte && (pte & PTE_PBMT)) { | |
969 | /* Reserved without Svpbmt. */ | |
970 | return TRANSLATE_FAIL; | |
971 | } | |
a9d2e3ed RH |
972 | |
973 | /* Check for reserved combinations of RWX flags. */ | |
974 | switch (pte & (PTE_R | PTE_W | PTE_X)) { | |
975 | case PTE_W: | |
976 | case PTE_W | PTE_X: | |
59688aa0 RH |
977 | return TRANSLATE_FAIL; |
978 | } | |
a9d2e3ed | 979 | |
e1dd1507 RH |
980 | int prot = 0; |
981 | if (pte & PTE_R) { | |
982 | prot |= PAGE_READ; | |
983 | } | |
984 | if (pte & PTE_W) { | |
985 | prot |= PAGE_WRITE; | |
986 | } | |
987 | if (pte & PTE_X) { | |
988 | bool mxr; | |
989 | ||
990 | if (first_stage == true) { | |
991 | mxr = get_field(env->mstatus, MSTATUS_MXR); | |
992 | } else { | |
993 | mxr = get_field(env->vsstatus, MSTATUS_MXR); | |
994 | } | |
995 | if (mxr) { | |
996 | prot |= PAGE_READ; | |
997 | } | |
998 | prot |= PAGE_EXEC; | |
999 | } | |
1000 | ||
38303e8a RH |
1001 | if (pte & PTE_U) { |
1002 | if (mode != PRV_U) { | |
1003 | if (!mmuidx_sum(mmu_idx)) { | |
1004 | return TRANSLATE_FAIL; | |
1005 | } | |
1006 | /* SUM allows only read+write, not execute. */ | |
1007 | prot &= PAGE_READ | PAGE_WRITE; | |
1008 | } | |
1009 | } else if (mode != PRV_S) { | |
59688aa0 RH |
1010 | /* Supervisor PTE flags when not S mode */ |
1011 | return TRANSLATE_FAIL; | |
1012 | } | |
e1dd1507 RH |
1013 | |
1014 | if (!((prot >> access_type) & 1)) { | |
1015 | /* Access check failed */ | |
59688aa0 RH |
1016 | return TRANSLATE_FAIL; |
1017 | } | |
1018 | ||
1019 | /* If necessary, set accessed and dirty bits. */ | |
1020 | target_ulong updated_pte = pte | PTE_A | | |
0c3e702a MC |
1021 | (access_type == MMU_DATA_STORE ? PTE_D : 0); |
1022 | ||
59688aa0 | 1023 | /* Page table updates need to be atomic with MTTCG enabled */ |
0a19bf5e | 1024 | if (updated_pte != pte && !is_debug) { |
59688aa0 RH |
1025 | if (!hade) { |
1026 | return TRANSLATE_FAIL; | |
1027 | } | |
0af3f115 | 1028 | |
59688aa0 RH |
1029 | /* |
1030 | * - if accessed or dirty bits need updating, and the PTE is | |
1031 | * in RAM, then we do so atomically with a compare and swap. | |
1032 | * - if the PTE is in IO space or ROM, then it can't be updated | |
1033 | * and we return TRANSLATE_FAIL. | |
1034 | * - if the PTE changed by the time we went to update it, then | |
1035 | * it is no longer valid and we must re-walk the page table. | |
1036 | */ | |
1037 | MemoryRegion *mr; | |
1038 | hwaddr l = sizeof(target_ulong), addr1; | |
1039 | mr = address_space_translate(cs->as, pte_addr, &addr1, &l, | |
1040 | false, MEMTXATTRS_UNSPECIFIED); | |
1041 | if (memory_region_is_ram(mr)) { | |
1042 | target_ulong *pte_pa = qemu_map_ram_ptr(mr->ram_block, addr1); | |
0c3e702a | 1043 | #if TCG_OVERSIZED_GUEST |
59688aa0 RH |
1044 | /* |
1045 | * MTTCG is not enabled on oversized TCG guests so | |
1046 | * page table updates do not need to be atomic | |
1047 | */ | |
1048 | *pte_pa = pte = updated_pte; | |
0c3e702a | 1049 | #else |
59688aa0 RH |
1050 | target_ulong old_pte = qatomic_cmpxchg(pte_pa, pte, updated_pte); |
1051 | if (old_pte != pte) { | |
1052 | goto restart; | |
0c3e702a | 1053 | } |
59688aa0 RH |
1054 | pte = updated_pte; |
1055 | #endif | |
1056 | } else { | |
3b57254d | 1057 | /* |
59688aa0 RH |
1058 | * Misconfigured PTE in ROM (AD bits are not preset) or |
1059 | * PTE is in IO space and can't be updated atomically. | |
3b57254d | 1060 | */ |
59688aa0 RH |
1061 | return TRANSLATE_FAIL; |
1062 | } | |
1063 | } | |
2bacb224 | 1064 | |
59688aa0 RH |
1065 | /* For superpage mappings, make a fake leaf PTE for the TLB's benefit. */ |
1066 | target_ulong vpn = addr >> PGSHIFT; | |
0c3e702a | 1067 | |
59688aa0 RH |
1068 | if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { |
1069 | napot_bits = ctzl(ppn) + 1; | |
1070 | if ((i != (levels - 1)) || (napot_bits != 4)) { | |
1071 | return TRANSLATE_FAIL; | |
0c3e702a MC |
1072 | } |
1073 | } | |
59688aa0 RH |
1074 | |
1075 | napot_mask = (1 << napot_bits) - 1; | |
1076 | *physical = (((ppn & ~napot_mask) | (vpn & napot_mask) | | |
1077 | (vpn & (((target_ulong)1 << ptshift) - 1)) | |
1078 | ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK); | |
1079 | ||
59688aa0 | 1080 | /* |
e1dd1507 RH |
1081 | * Remove write permission unless this is a store, or the page is |
1082 | * already dirty, so that we TLB miss on later writes to update | |
1083 | * the dirty bit. | |
59688aa0 | 1084 | */ |
e1dd1507 RH |
1085 | if (access_type != MMU_DATA_STORE && !(pte & PTE_D)) { |
1086 | prot &= ~PAGE_WRITE; | |
59688aa0 | 1087 | } |
e1dd1507 RH |
1088 | *ret_prot = prot; |
1089 | ||
59688aa0 | 1090 | return TRANSLATE_SUCCESS; |
0c3e702a MC |
1091 | } |
1092 | ||
1093 | static void raise_mmu_exception(CPURISCVState *env, target_ulong address, | |
1448689c | 1094 | MMUAccessType access_type, bool pmp_violation, |
8e2aa21b AP |
1095 | bool first_stage, bool two_stage, |
1096 | bool two_stage_indirect) | |
0c3e702a | 1097 | { |
3109cd98 | 1098 | CPUState *cs = env_cpu(env); |
994b6bb2 | 1099 | int page_fault_exceptions, vm; |
419ddf00 AF |
1100 | uint64_t stap_mode; |
1101 | ||
db23e5d9 | 1102 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
419ddf00 AF |
1103 | stap_mode = SATP32_MODE; |
1104 | } else { | |
1105 | stap_mode = SATP64_MODE; | |
1106 | } | |
994b6bb2 | 1107 | |
1448689c | 1108 | if (first_stage) { |
419ddf00 | 1109 | vm = get_field(env->satp, stap_mode); |
1448689c | 1110 | } else { |
419ddf00 | 1111 | vm = get_field(env->hgatp, stap_mode); |
1448689c | 1112 | } |
419ddf00 | 1113 | |
994b6bb2 AF |
1114 | page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation; |
1115 | ||
0c3e702a MC |
1116 | switch (access_type) { |
1117 | case MMU_INST_FETCH: | |
38256529 | 1118 | if (env->virt_enabled && !first_stage) { |
b2ef6ab9 AF |
1119 | cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT; |
1120 | } else { | |
1121 | cs->exception_index = page_fault_exceptions ? | |
1122 | RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT; | |
1123 | } | |
0c3e702a MC |
1124 | break; |
1125 | case MMU_DATA_LOAD: | |
1c1c060a | 1126 | if (two_stage && !first_stage) { |
b2ef6ab9 AF |
1127 | cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; |
1128 | } else { | |
1129 | cs->exception_index = page_fault_exceptions ? | |
1130 | RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT; | |
1131 | } | |
0c3e702a MC |
1132 | break; |
1133 | case MMU_DATA_STORE: | |
1c1c060a | 1134 | if (two_stage && !first_stage) { |
b2ef6ab9 AF |
1135 | cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT; |
1136 | } else { | |
1137 | cs->exception_index = page_fault_exceptions ? | |
246f8796 WL |
1138 | RISCV_EXCP_STORE_PAGE_FAULT : |
1139 | RISCV_EXCP_STORE_AMO_ACCESS_FAULT; | |
b2ef6ab9 | 1140 | } |
0c3e702a MC |
1141 | break; |
1142 | default: | |
1143 | g_assert_not_reached(); | |
1144 | } | |
1145 | env->badaddr = address; | |
ec352d0c | 1146 | env->two_stage_lookup = two_stage; |
8e2aa21b | 1147 | env->two_stage_indirect_lookup = two_stage_indirect; |
0c3e702a MC |
1148 | } |
1149 | ||
1150 | hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) | |
1151 | { | |
1152 | RISCVCPU *cpu = RISCV_CPU(cs); | |
36a18664 | 1153 | CPURISCVState *env = &cpu->env; |
0c3e702a MC |
1154 | hwaddr phys_addr; |
1155 | int prot; | |
1156 | int mmu_idx = cpu_mmu_index(&cpu->env, false); | |
1157 | ||
33a9a57d | 1158 | if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx, |
38256529 | 1159 | true, env->virt_enabled, true)) { |
0c3e702a MC |
1160 | return -1; |
1161 | } | |
36a18664 | 1162 | |
38256529 | 1163 | if (env->virt_enabled) { |
33a9a57d | 1164 | if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL, |
11c27c6d | 1165 | 0, mmu_idx, false, true, true)) { |
36a18664 AF |
1166 | return -1; |
1167 | } | |
1168 | } | |
1169 | ||
9ef82119 | 1170 | return phys_addr & TARGET_PAGE_MASK; |
0c3e702a MC |
1171 | } |
1172 | ||
37207e12 PD |
1173 | void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, |
1174 | vaddr addr, unsigned size, | |
1175 | MMUAccessType access_type, | |
1176 | int mmu_idx, MemTxAttrs attrs, | |
1177 | MemTxResult response, uintptr_t retaddr) | |
cbf58276 MC |
1178 | { |
1179 | RISCVCPU *cpu = RISCV_CPU(cs); | |
1180 | CPURISCVState *env = &cpu->env; | |
1181 | ||
37207e12 | 1182 | if (access_type == MMU_DATA_STORE) { |
cbf58276 | 1183 | cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; |
f9e580c1 | 1184 | } else if (access_type == MMU_DATA_LOAD) { |
cbf58276 | 1185 | cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; |
f9e580c1 EB |
1186 | } else { |
1187 | cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT; | |
cbf58276 MC |
1188 | } |
1189 | ||
1190 | env->badaddr = addr; | |
696bacde | 1191 | env->two_stage_lookup = mmuidx_2stage(mmu_idx); |
8e2aa21b | 1192 | env->two_stage_indirect_lookup = false; |
ac684717 | 1193 | cpu_loop_exit_restore(cs, retaddr); |
cbf58276 MC |
1194 | } |
1195 | ||
0c3e702a MC |
1196 | void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, |
1197 | MMUAccessType access_type, int mmu_idx, | |
1198 | uintptr_t retaddr) | |
1199 | { | |
1200 | RISCVCPU *cpu = RISCV_CPU(cs); | |
1201 | CPURISCVState *env = &cpu->env; | |
1202 | switch (access_type) { | |
1203 | case MMU_INST_FETCH: | |
1204 | cs->exception_index = RISCV_EXCP_INST_ADDR_MIS; | |
1205 | break; | |
1206 | case MMU_DATA_LOAD: | |
1207 | cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS; | |
1208 | break; | |
1209 | case MMU_DATA_STORE: | |
1210 | cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS; | |
1211 | break; | |
1212 | default: | |
1213 | g_assert_not_reached(); | |
1214 | } | |
1215 | env->badaddr = addr; | |
696bacde | 1216 | env->two_stage_lookup = mmuidx_2stage(mmu_idx); |
8e2aa21b | 1217 | env->two_stage_indirect_lookup = false; |
ac684717 | 1218 | cpu_loop_exit_restore(cs, retaddr); |
0c3e702a | 1219 | } |
0c3e702a | 1220 | |
892320fa AP |
1221 | |
1222 | static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type) | |
1223 | { | |
1224 | enum riscv_pmu_event_idx pmu_event_type; | |
1225 | ||
1226 | switch (access_type) { | |
1227 | case MMU_INST_FETCH: | |
1228 | pmu_event_type = RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS; | |
1229 | break; | |
1230 | case MMU_DATA_LOAD: | |
1231 | pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS; | |
1232 | break; | |
1233 | case MMU_DATA_STORE: | |
1234 | pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS; | |
1235 | break; | |
1236 | default: | |
1237 | return; | |
1238 | } | |
1239 | ||
1240 | riscv_pmu_incr_ctr(cpu, pmu_event_type); | |
1241 | } | |
1242 | ||
8a4ca3c1 RH |
1243 | bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
1244 | MMUAccessType access_type, int mmu_idx, | |
1245 | bool probe, uintptr_t retaddr) | |
0c3e702a MC |
1246 | { |
1247 | RISCVCPU *cpu = RISCV_CPU(cs); | |
1248 | CPURISCVState *env = &cpu->env; | |
36a18664 | 1249 | vaddr im_address; |
0c3e702a | 1250 | hwaddr pa = 0; |
b297129a | 1251 | int prot, prot2, prot_pmp; |
635b0b0e | 1252 | bool pmp_violation = false; |
36a18664 | 1253 | bool first_stage_error = true; |
696bacde | 1254 | bool two_stage_lookup = mmuidx_2stage(mmu_idx); |
8e2aa21b | 1255 | bool two_stage_indirect_error = false; |
0c3e702a | 1256 | int ret = TRANSLATE_FAIL; |
cc0fdb29 | 1257 | int mode = mmu_idx; |
b297129a JS |
1258 | /* default TLB page size */ |
1259 | target_ulong tlb_size = TARGET_PAGE_SIZE; | |
0c3e702a | 1260 | |
36a18664 AF |
1261 | env->guest_phys_fault_addr = 0; |
1262 | ||
8a4ca3c1 RH |
1263 | qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", |
1264 | __func__, address, access_type, mmu_idx); | |
1265 | ||
eacd03cb | 1266 | pmu_tlb_fill_incr_ctr(cpu, access_type); |
696bacde | 1267 | if (two_stage_lookup) { |
36a18664 | 1268 | /* Two stage lookup */ |
33a9a57d YJ |
1269 | ret = get_physical_address(env, &pa, &prot, address, |
1270 | &env->guest_phys_fault_addr, access_type, | |
11c27c6d | 1271 | mmu_idx, true, true, false); |
36a18664 | 1272 | |
33a9a57d YJ |
1273 | /* |
1274 | * A G-stage exception may be triggered during two state lookup. | |
1275 | * And the env->guest_phys_fault_addr has already been set in | |
1276 | * get_physical_address(). | |
1277 | */ | |
1278 | if (ret == TRANSLATE_G_STAGE_FAIL) { | |
1279 | first_stage_error = false; | |
8e2aa21b | 1280 | two_stage_indirect_error = true; |
33a9a57d YJ |
1281 | access_type = MMU_DATA_LOAD; |
1282 | } | |
1283 | ||
36a18664 AF |
1284 | qemu_log_mask(CPU_LOG_MMU, |
1285 | "%s 1st-stage address=%" VADDR_PRIx " ret %d physical " | |
883f2c59 | 1286 | HWADDR_FMT_plx " prot %d\n", |
36a18664 AF |
1287 | __func__, address, ret, pa, prot); |
1288 | ||
33a9a57d | 1289 | if (ret == TRANSLATE_SUCCESS) { |
36a18664 AF |
1290 | /* Second stage lookup */ |
1291 | im_address = pa; | |
1292 | ||
33a9a57d | 1293 | ret = get_physical_address(env, &pa, &prot2, im_address, NULL, |
a427c836 | 1294 | access_type, MMUIdx_U, false, true, |
11c27c6d | 1295 | false); |
36a18664 AF |
1296 | |
1297 | qemu_log_mask(CPU_LOG_MMU, | |
c45eff30 WL |
1298 | "%s 2nd-stage address=%" VADDR_PRIx |
1299 | " ret %d physical " | |
1300 | HWADDR_FMT_plx " prot %d\n", | |
1301 | __func__, im_address, ret, pa, prot2); | |
8f67cd6d AF |
1302 | |
1303 | prot &= prot2; | |
36a18664 | 1304 | |
b297129a | 1305 | if (ret == TRANSLATE_SUCCESS) { |
bfc7ee12 | 1306 | ret = get_physical_address_pmp(env, &prot_pmp, pa, |
b297129a | 1307 | size, access_type, mode); |
bfc7ee12 | 1308 | tlb_size = pmp_get_tlb_size(env, pa); |
663e1193 JS |
1309 | |
1310 | qemu_log_mask(CPU_LOG_MMU, | |
883f2c59 | 1311 | "%s PMP address=" HWADDR_FMT_plx " ret %d prot" |
663e1193 JS |
1312 | " %d tlb_size " TARGET_FMT_lu "\n", |
1313 | __func__, pa, ret, prot_pmp, tlb_size); | |
1314 | ||
b297129a | 1315 | prot &= prot_pmp; |
36a18664 AF |
1316 | } |
1317 | ||
1318 | if (ret != TRANSLATE_SUCCESS) { | |
1319 | /* | |
1320 | * Guest physical address translation failed, this is a HS | |
1321 | * level exception | |
1322 | */ | |
1323 | first_stage_error = false; | |
1324 | env->guest_phys_fault_addr = (im_address | | |
1325 | (address & | |
1326 | (TARGET_PAGE_SIZE - 1))) >> 2; | |
1327 | } | |
1328 | } | |
1329 | } else { | |
1330 | /* Single stage lookup */ | |
33a9a57d | 1331 | ret = get_physical_address(env, &pa, &prot, address, NULL, |
11c27c6d | 1332 | access_type, mmu_idx, true, false, false); |
36a18664 AF |
1333 | |
1334 | qemu_log_mask(CPU_LOG_MMU, | |
1335 | "%s address=%" VADDR_PRIx " ret %d physical " | |
883f2c59 | 1336 | HWADDR_FMT_plx " prot %d\n", |
36a18664 | 1337 | __func__, address, ret, pa, prot); |
8a4ca3c1 | 1338 | |
b297129a | 1339 | if (ret == TRANSLATE_SUCCESS) { |
bfc7ee12 | 1340 | ret = get_physical_address_pmp(env, &prot_pmp, pa, |
b297129a | 1341 | size, access_type, mode); |
bfc7ee12 | 1342 | tlb_size = pmp_get_tlb_size(env, pa); |
663e1193 JS |
1343 | |
1344 | qemu_log_mask(CPU_LOG_MMU, | |
883f2c59 | 1345 | "%s PMP address=" HWADDR_FMT_plx " ret %d prot" |
663e1193 JS |
1346 | " %d tlb_size " TARGET_FMT_lu "\n", |
1347 | __func__, pa, ret, prot_pmp, tlb_size); | |
1348 | ||
b297129a JS |
1349 | prot &= prot_pmp; |
1350 | } | |
1f447aec | 1351 | } |
b297129a | 1352 | |
1f447aec | 1353 | if (ret == TRANSLATE_PMP_FAIL) { |
635b0b0e | 1354 | pmp_violation = true; |
0c3e702a | 1355 | } |
36a18664 | 1356 | |
0c3e702a | 1357 | if (ret == TRANSLATE_SUCCESS) { |
b297129a JS |
1358 | tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1), |
1359 | prot, mmu_idx, tlb_size); | |
8a4ca3c1 RH |
1360 | return true; |
1361 | } else if (probe) { | |
1362 | return false; | |
1363 | } else { | |
1c1c060a | 1364 | raise_mmu_exception(env, address, access_type, pmp_violation, |
696bacde | 1365 | first_stage_error, two_stage_lookup, |
8e2aa21b | 1366 | two_stage_indirect_error); |
ac684717 | 1367 | cpu_loop_exit_restore(cs, retaddr); |
0c3e702a | 1368 | } |
36a18664 AF |
1369 | |
1370 | return true; | |
0c3e702a | 1371 | } |
8e2aa21b AP |
1372 | |
1373 | static target_ulong riscv_transformed_insn(CPURISCVState *env, | |
1374 | target_ulong insn, | |
1375 | target_ulong taddr) | |
1376 | { | |
1377 | target_ulong xinsn = 0; | |
1378 | target_ulong access_rs1 = 0, access_imm = 0, access_size = 0; | |
1379 | ||
1380 | /* | |
1381 | * Only Quadrant 0 and Quadrant 2 of RVC instruction space need to | |
1382 | * be uncompressed. The Quadrant 1 of RVC instruction space need | |
1383 | * not be transformed because these instructions won't generate | |
1384 | * any load/store trap. | |
1385 | */ | |
1386 | ||
1387 | if ((insn & 0x3) != 0x3) { | |
1388 | /* Transform 16bit instruction into 32bit instruction */ | |
1389 | switch (GET_C_OP(insn)) { | |
1390 | case OPC_RISC_C_OP_QUAD0: /* Quadrant 0 */ | |
1391 | switch (GET_C_FUNC(insn)) { | |
1392 | case OPC_RISC_C_FUNC_FLD_LQ: | |
1393 | if (riscv_cpu_xlen(env) != 128) { /* C.FLD (RV32/64) */ | |
1394 | xinsn = OPC_RISC_FLD; | |
1395 | xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); | |
1396 | access_rs1 = GET_C_RS1S(insn); | |
1397 | access_imm = GET_C_LD_IMM(insn); | |
1398 | access_size = 8; | |
1399 | } | |
1400 | break; | |
1401 | case OPC_RISC_C_FUNC_LW: /* C.LW */ | |
1402 | xinsn = OPC_RISC_LW; | |
1403 | xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); | |
1404 | access_rs1 = GET_C_RS1S(insn); | |
1405 | access_imm = GET_C_LW_IMM(insn); | |
1406 | access_size = 4; | |
1407 | break; | |
1408 | case OPC_RISC_C_FUNC_FLW_LD: | |
1409 | if (riscv_cpu_xlen(env) == 32) { /* C.FLW (RV32) */ | |
1410 | xinsn = OPC_RISC_FLW; | |
1411 | xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); | |
1412 | access_rs1 = GET_C_RS1S(insn); | |
1413 | access_imm = GET_C_LW_IMM(insn); | |
1414 | access_size = 4; | |
1415 | } else { /* C.LD (RV64/RV128) */ | |
1416 | xinsn = OPC_RISC_LD; | |
1417 | xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); | |
1418 | access_rs1 = GET_C_RS1S(insn); | |
1419 | access_imm = GET_C_LD_IMM(insn); | |
1420 | access_size = 8; | |
1421 | } | |
1422 | break; | |
1423 | case OPC_RISC_C_FUNC_FSD_SQ: | |
1424 | if (riscv_cpu_xlen(env) != 128) { /* C.FSD (RV32/64) */ | |
1425 | xinsn = OPC_RISC_FSD; | |
1426 | xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); | |
1427 | access_rs1 = GET_C_RS1S(insn); | |
1428 | access_imm = GET_C_SD_IMM(insn); | |
1429 | access_size = 8; | |
1430 | } | |
1431 | break; | |
1432 | case OPC_RISC_C_FUNC_SW: /* C.SW */ | |
1433 | xinsn = OPC_RISC_SW; | |
1434 | xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); | |
1435 | access_rs1 = GET_C_RS1S(insn); | |
1436 | access_imm = GET_C_SW_IMM(insn); | |
1437 | access_size = 4; | |
1438 | break; | |
1439 | case OPC_RISC_C_FUNC_FSW_SD: | |
1440 | if (riscv_cpu_xlen(env) == 32) { /* C.FSW (RV32) */ | |
1441 | xinsn = OPC_RISC_FSW; | |
1442 | xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); | |
1443 | access_rs1 = GET_C_RS1S(insn); | |
1444 | access_imm = GET_C_SW_IMM(insn); | |
1445 | access_size = 4; | |
1446 | } else { /* C.SD (RV64/RV128) */ | |
1447 | xinsn = OPC_RISC_SD; | |
1448 | xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); | |
1449 | access_rs1 = GET_C_RS1S(insn); | |
1450 | access_imm = GET_C_SD_IMM(insn); | |
1451 | access_size = 8; | |
1452 | } | |
1453 | break; | |
1454 | default: | |
1455 | break; | |
1456 | } | |
1457 | break; | |
1458 | case OPC_RISC_C_OP_QUAD2: /* Quadrant 2 */ | |
1459 | switch (GET_C_FUNC(insn)) { | |
1460 | case OPC_RISC_C_FUNC_FLDSP_LQSP: | |
1461 | if (riscv_cpu_xlen(env) != 128) { /* C.FLDSP (RV32/64) */ | |
1462 | xinsn = OPC_RISC_FLD; | |
1463 | xinsn = SET_RD(xinsn, GET_C_RD(insn)); | |
1464 | access_rs1 = 2; | |
1465 | access_imm = GET_C_LDSP_IMM(insn); | |
1466 | access_size = 8; | |
1467 | } | |
1468 | break; | |
1469 | case OPC_RISC_C_FUNC_LWSP: /* C.LWSP */ | |
1470 | xinsn = OPC_RISC_LW; | |
1471 | xinsn = SET_RD(xinsn, GET_C_RD(insn)); | |
1472 | access_rs1 = 2; | |
1473 | access_imm = GET_C_LWSP_IMM(insn); | |
1474 | access_size = 4; | |
1475 | break; | |
1476 | case OPC_RISC_C_FUNC_FLWSP_LDSP: | |
1477 | if (riscv_cpu_xlen(env) == 32) { /* C.FLWSP (RV32) */ | |
1478 | xinsn = OPC_RISC_FLW; | |
1479 | xinsn = SET_RD(xinsn, GET_C_RD(insn)); | |
1480 | access_rs1 = 2; | |
1481 | access_imm = GET_C_LWSP_IMM(insn); | |
1482 | access_size = 4; | |
1483 | } else { /* C.LDSP (RV64/RV128) */ | |
1484 | xinsn = OPC_RISC_LD; | |
1485 | xinsn = SET_RD(xinsn, GET_C_RD(insn)); | |
1486 | access_rs1 = 2; | |
1487 | access_imm = GET_C_LDSP_IMM(insn); | |
1488 | access_size = 8; | |
1489 | } | |
1490 | break; | |
1491 | case OPC_RISC_C_FUNC_FSDSP_SQSP: | |
1492 | if (riscv_cpu_xlen(env) != 128) { /* C.FSDSP (RV32/64) */ | |
1493 | xinsn = OPC_RISC_FSD; | |
1494 | xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); | |
1495 | access_rs1 = 2; | |
1496 | access_imm = GET_C_SDSP_IMM(insn); | |
1497 | access_size = 8; | |
1498 | } | |
1499 | break; | |
1500 | case OPC_RISC_C_FUNC_SWSP: /* C.SWSP */ | |
1501 | xinsn = OPC_RISC_SW; | |
1502 | xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); | |
1503 | access_rs1 = 2; | |
1504 | access_imm = GET_C_SWSP_IMM(insn); | |
1505 | access_size = 4; | |
1506 | break; | |
1507 | case 7: | |
1508 | if (riscv_cpu_xlen(env) == 32) { /* C.FSWSP (RV32) */ | |
1509 | xinsn = OPC_RISC_FSW; | |
1510 | xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); | |
1511 | access_rs1 = 2; | |
1512 | access_imm = GET_C_SWSP_IMM(insn); | |
1513 | access_size = 4; | |
1514 | } else { /* C.SDSP (RV64/RV128) */ | |
1515 | xinsn = OPC_RISC_SD; | |
1516 | xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); | |
1517 | access_rs1 = 2; | |
1518 | access_imm = GET_C_SDSP_IMM(insn); | |
1519 | access_size = 8; | |
1520 | } | |
1521 | break; | |
1522 | default: | |
1523 | break; | |
1524 | } | |
1525 | break; | |
1526 | default: | |
1527 | break; | |
1528 | } | |
1529 | ||
1530 | /* | |
1531 | * Clear Bit1 of transformed instruction to indicate that | |
1532 | * original insruction was a 16bit instruction | |
1533 | */ | |
1534 | xinsn &= ~((target_ulong)0x2); | |
1535 | } else { | |
1536 | /* Transform 32bit (or wider) instructions */ | |
1537 | switch (MASK_OP_MAJOR(insn)) { | |
1538 | case OPC_RISC_ATOMIC: | |
1539 | xinsn = insn; | |
1540 | access_rs1 = GET_RS1(insn); | |
1541 | access_size = 1 << GET_FUNCT3(insn); | |
1542 | break; | |
1543 | case OPC_RISC_LOAD: | |
1544 | case OPC_RISC_FP_LOAD: | |
1545 | xinsn = SET_I_IMM(insn, 0); | |
1546 | access_rs1 = GET_RS1(insn); | |
1547 | access_imm = GET_IMM(insn); | |
1548 | access_size = 1 << GET_FUNCT3(insn); | |
1549 | break; | |
1550 | case OPC_RISC_STORE: | |
1551 | case OPC_RISC_FP_STORE: | |
1552 | xinsn = SET_S_IMM(insn, 0); | |
1553 | access_rs1 = GET_RS1(insn); | |
1554 | access_imm = GET_STORE_IMM(insn); | |
1555 | access_size = 1 << GET_FUNCT3(insn); | |
1556 | break; | |
1557 | case OPC_RISC_SYSTEM: | |
1558 | if (MASK_OP_SYSTEM(insn) == OPC_RISC_HLVHSV) { | |
1559 | xinsn = insn; | |
1560 | access_rs1 = GET_RS1(insn); | |
1561 | access_size = 1 << ((GET_FUNCT7(insn) >> 1) & 0x3); | |
1562 | access_size = 1 << access_size; | |
1563 | } | |
1564 | break; | |
1565 | default: | |
1566 | break; | |
1567 | } | |
1568 | } | |
1569 | ||
1570 | if (access_size) { | |
1571 | xinsn = SET_RS1(xinsn, (taddr - (env->gpr[access_rs1] + access_imm)) & | |
1572 | (access_size - 1)); | |
1573 | } | |
1574 | ||
1575 | return xinsn; | |
1576 | } | |
263e2ab2 | 1577 | #endif /* !CONFIG_USER_ONLY */ |
0c3e702a MC |
1578 | |
1579 | /* | |
1580 | * Handle Traps | |
1581 | * | |
1582 | * Adapted from Spike's processor_t::take_trap. | |
1583 | * | |
1584 | */ | |
1585 | void riscv_cpu_do_interrupt(CPUState *cs) | |
1586 | { | |
1587 | #if !defined(CONFIG_USER_ONLY) | |
1588 | ||
1589 | RISCVCPU *cpu = RISCV_CPU(cs); | |
1590 | CPURISCVState *env = &cpu->env; | |
86d0c457 | 1591 | bool write_gva = false; |
284d697c | 1592 | uint64_t s; |
0c3e702a | 1593 | |
3b57254d WL |
1594 | /* |
1595 | * cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide | |
acbbb94e MC |
1596 | * so we mask off the MSB and separate into trap type and cause. |
1597 | */ | |
1598 | bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG); | |
1599 | target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; | |
d028ac75 | 1600 | uint64_t deleg = async ? env->mideleg : env->medeleg; |
acbbb94e | 1601 | target_ulong tval = 0; |
8e2aa21b | 1602 | target_ulong tinst = 0; |
30675539 AF |
1603 | target_ulong htval = 0; |
1604 | target_ulong mtval2 = 0; | |
acbbb94e | 1605 | |
a10b9d93 | 1606 | if (cause == RISCV_EXCP_SEMIHOST) { |
7d7fb116 PM |
1607 | do_common_semihosting(cs); |
1608 | env->pc += 4; | |
1609 | return; | |
a10b9d93 KP |
1610 | } |
1611 | ||
acbbb94e MC |
1612 | if (!async) { |
1613 | /* set tval to badaddr for traps with address information */ | |
1614 | switch (cause) { | |
ab67a1d0 AF |
1615 | case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: |
1616 | case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: | |
acbbb94e MC |
1617 | case RISCV_EXCP_LOAD_ADDR_MIS: |
1618 | case RISCV_EXCP_STORE_AMO_ADDR_MIS: | |
1619 | case RISCV_EXCP_LOAD_ACCESS_FAULT: | |
1620 | case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: | |
acbbb94e MC |
1621 | case RISCV_EXCP_LOAD_PAGE_FAULT: |
1622 | case RISCV_EXCP_STORE_PAGE_FAULT: | |
24826da0 | 1623 | write_gva = env->two_stage_lookup; |
acbbb94e | 1624 | tval = env->badaddr; |
8e2aa21b AP |
1625 | if (env->two_stage_indirect_lookup) { |
1626 | /* | |
1627 | * special pseudoinstruction for G-stage fault taken while | |
1628 | * doing VS-stage page table walk. | |
1629 | */ | |
1630 | tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000; | |
1631 | } else { | |
1632 | /* | |
1633 | * The "Addr. Offset" field in transformed instruction is | |
1634 | * non-zero only for misaligned access. | |
1635 | */ | |
1636 | tinst = riscv_transformed_insn(env, env->bins, tval); | |
1637 | } | |
1638 | break; | |
1639 | case RISCV_EXCP_INST_GUEST_PAGE_FAULT: | |
1640 | case RISCV_EXCP_INST_ADDR_MIS: | |
1641 | case RISCV_EXCP_INST_ACCESS_FAULT: | |
1642 | case RISCV_EXCP_INST_PAGE_FAULT: | |
1643 | write_gva = env->two_stage_lookup; | |
1644 | tval = env->badaddr; | |
1645 | if (env->two_stage_indirect_lookup) { | |
1646 | /* | |
1647 | * special pseudoinstruction for G-stage fault taken while | |
1648 | * doing VS-stage page table walk. | |
1649 | */ | |
1650 | tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000; | |
1651 | } | |
acbbb94e | 1652 | break; |
48eaeb56 | 1653 | case RISCV_EXCP_ILLEGAL_INST: |
62cf0245 | 1654 | case RISCV_EXCP_VIRT_INSTRUCTION_FAULT: |
48eaeb56 AF |
1655 | tval = env->bins; |
1656 | break; | |
26934f9a SM |
1657 | case RISCV_EXCP_BREAKPOINT: |
1658 | if (cs->watchpoint_hit) { | |
1659 | tval = cs->watchpoint_hit->hitaddr; | |
1660 | cs->watchpoint_hit = NULL; | |
1661 | } | |
1662 | break; | |
acbbb94e MC |
1663 | default: |
1664 | break; | |
0c3e702a | 1665 | } |
acbbb94e MC |
1666 | /* ecall is dispatched as one cause so translate based on mode */ |
1667 | if (cause == RISCV_EXCP_U_ECALL) { | |
1668 | assert(env->priv <= 3); | |
5eb9e782 AF |
1669 | |
1670 | if (env->priv == PRV_M) { | |
1671 | cause = RISCV_EXCP_M_ECALL; | |
38256529 | 1672 | } else if (env->priv == PRV_S && env->virt_enabled) { |
5eb9e782 | 1673 | cause = RISCV_EXCP_VS_ECALL; |
38256529 | 1674 | } else if (env->priv == PRV_S && !env->virt_enabled) { |
5eb9e782 AF |
1675 | cause = RISCV_EXCP_S_ECALL; |
1676 | } else if (env->priv == PRV_U) { | |
1677 | cause = RISCV_EXCP_U_ECALL; | |
1678 | } | |
0c3e702a MC |
1679 | } |
1680 | } | |
1681 | ||
c51a3f5d | 1682 | trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, |
69430111 AF |
1683 | riscv_cpu_get_trap_name(cause, async)); |
1684 | ||
1685 | qemu_log_mask(CPU_LOG_INT, | |
1686 | "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", " | |
1687 | "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n", | |
1688 | __func__, env->mhartid, async, cause, env->pc, tval, | |
1689 | riscv_cpu_get_trap_name(cause, async)); | |
0c3e702a | 1690 | |
acbbb94e MC |
1691 | if (env->priv <= PRV_S && |
1692 | cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { | |
0c3e702a | 1693 | /* handle the trap in S-mode */ |
5eb9e782 | 1694 | if (riscv_has_ext(env, RVH)) { |
d028ac75 | 1695 | uint64_t hdeleg = async ? env->hideleg : env->hedeleg; |
1c1c060a | 1696 | |
38256529 | 1697 | if (env->virt_enabled && ((hdeleg >> cause) & 1)) { |
84b1c04b | 1698 | /* Trap to VS mode */ |
c5969a3a RK |
1699 | /* |
1700 | * See if we need to adjust cause. Yes if its VS mode interrupt | |
1701 | * no if hypervisor has delegated one of hs mode's interrupt | |
1702 | */ | |
1703 | if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || | |
84b1c04b | 1704 | cause == IRQ_VS_EXT) { |
c5969a3a | 1705 | cause = cause - 1; |
84b1c04b | 1706 | } |
86d0c457 | 1707 | write_gva = false; |
38256529 | 1708 | } else if (env->virt_enabled) { |
5eb9e782 AF |
1709 | /* Trap into HS mode, from virt */ |
1710 | riscv_cpu_swap_hypervisor_regs(env); | |
f2d5850f | 1711 | env->hstatus = set_field(env->hstatus, HSTATUS_SPVP, |
ace54453 | 1712 | env->priv); |
2136b6c3 | 1713 | env->hstatus = set_field(env->hstatus, HSTATUS_SPV, true); |
86d0c457 | 1714 | |
30675539 AF |
1715 | htval = env->guest_phys_fault_addr; |
1716 | ||
5eb9e782 | 1717 | riscv_cpu_set_virt_enabled(env, 0); |
5eb9e782 AF |
1718 | } else { |
1719 | /* Trap into HS mode */ | |
ec352d0c | 1720 | env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false); |
30675539 | 1721 | htval = env->guest_phys_fault_addr; |
5eb9e782 | 1722 | } |
86d0c457 | 1723 | env->hstatus = set_field(env->hstatus, HSTATUS_GVA, write_gva); |
5eb9e782 AF |
1724 | } |
1725 | ||
1726 | s = env->mstatus; | |
1a9540d1 | 1727 | s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); |
0c3e702a MC |
1728 | s = set_field(s, MSTATUS_SPP, env->priv); |
1729 | s = set_field(s, MSTATUS_SIE, 0); | |
c7b95171 | 1730 | env->mstatus = s; |
16fdb8ff | 1731 | env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1)); |
acbbb94e | 1732 | env->sepc = env->pc; |
ac12b601 | 1733 | env->stval = tval; |
30675539 | 1734 | env->htval = htval; |
8e2aa21b | 1735 | env->htinst = tinst; |
acbbb94e | 1736 | env->pc = (env->stvec >> 2 << 2) + |
c45eff30 | 1737 | ((async && (env->stvec & 3) == 1) ? cause * 4 : 0); |
fb738839 | 1738 | riscv_cpu_set_mode(env, PRV_S); |
0c3e702a | 1739 | } else { |
acbbb94e | 1740 | /* handle the trap in M-mode */ |
5eb9e782 | 1741 | if (riscv_has_ext(env, RVH)) { |
38256529 | 1742 | if (env->virt_enabled) { |
5eb9e782 AF |
1743 | riscv_cpu_swap_hypervisor_regs(env); |
1744 | } | |
1745 | env->mstatus = set_field(env->mstatus, MSTATUS_MPV, | |
38256529 WL |
1746 | env->virt_enabled); |
1747 | if (env->virt_enabled && tval) { | |
9034e90a AF |
1748 | env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1); |
1749 | } | |
5eb9e782 | 1750 | |
30675539 AF |
1751 | mtval2 = env->guest_phys_fault_addr; |
1752 | ||
5eb9e782 AF |
1753 | /* Trapping to M mode, virt is disabled */ |
1754 | riscv_cpu_set_virt_enabled(env, 0); | |
5eb9e782 AF |
1755 | } |
1756 | ||
1757 | s = env->mstatus; | |
1a9540d1 | 1758 | s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); |
0c3e702a MC |
1759 | s = set_field(s, MSTATUS_MPP, env->priv); |
1760 | s = set_field(s, MSTATUS_MIE, 0); | |
c7b95171 | 1761 | env->mstatus = s; |
acbbb94e MC |
1762 | env->mcause = cause | ~(((target_ulong)-1) >> async); |
1763 | env->mepc = env->pc; | |
ac12b601 | 1764 | env->mtval = tval; |
30675539 | 1765 | env->mtval2 = mtval2; |
8e2aa21b | 1766 | env->mtinst = tinst; |
acbbb94e | 1767 | env->pc = (env->mtvec >> 2 << 2) + |
c45eff30 | 1768 | ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); |
fb738839 | 1769 | riscv_cpu_set_mode(env, PRV_M); |
0c3e702a | 1770 | } |
d9360e96 | 1771 | |
3b57254d WL |
1772 | /* |
1773 | * NOTE: it is not necessary to yield load reservations here. It is only | |
d9360e96 MC |
1774 | * necessary for an SC from "another hart" to cause a load reservation |
1775 | * to be yielded. Refer to the memory consistency model section of the | |
1776 | * RISC-V ISA Specification. | |
1777 | */ | |
1778 | ||
ec352d0c | 1779 | env->two_stage_lookup = false; |
8e2aa21b | 1780 | env->two_stage_indirect_lookup = false; |
0c3e702a | 1781 | #endif |
330d2ae3 | 1782 | cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */ |
0c3e702a | 1783 | } |