]> git.proxmox.com Git - mirror_qemu.git/blame - target/riscv/cpu_helper.c
projects / mirror_qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
docs: List kvm as a supported accelerator on RISC-V
[mirror_qemu.git] / target / riscv / cpu_helper.c
CommitLineData
0c3e702a 1/*
df354dd4 2 * RISC-V CPU helpers for qemu.
0c3e702a
MC		 3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "qemu/osdep.h"
21#include "qemu/log.h"
7ec5d303 22#include "qemu/main-loop.h"
0c3e702a
MC		 23#include "cpu.h"
24#include "exec/exec-all.h"
8e2aa21b 25#include "instmap.h"
dcb32f1d 26#include "tcg/tcg-op.h"
929f0a7f 27#include "trace.h"
6b5fe137 28#include "semihosting/common-semi.h"
0c3e702a
MC		 29
30int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
31{
32#ifdef CONFIG_USER_ONLY
33 return 0;
34#else
35 return env->priv;
36#endif
37}
38
53677acf
RH		 39void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
40 target_ulong *cs_base, uint32_t *pflags)
41{
b4a99d40
FC		 42 CPUState *cs = env_cpu(env);
43 RISCVCPU *cpu = RISCV_CPU(cs);
44
53677acf
RH		 45 uint32_t flags = 0;
46
8c796f1a 47 *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
53677acf
RH		 48 *cs_base = 0;
49
32e579b8 50 if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) {
a689a82b
FC		 51 /*
52 * If env->vl equals to VLMAX, we can use generic vector operation
53 * expanders (GVEC) to accerlate the vector operations.
54 * However, as LMUL could be a fractional number. The maximum
55 * vector size can be operated might be less than 8 bytes,
56 * which is not supported by GVEC. So we set vl_eq_vlmax flag to true
57 * only when maxsz >= 8 bytes.
58 */
53677acf 59 uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);
a689a82b
FC		 60 uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW);
61 uint32_t maxsz = vlmax << sew;
62 bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) &&
63 (maxsz >= 8);
d96a271a 64 flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill);
a689a82b 65 flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew);
53677acf
RH		 66 flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
67 FIELD_EX64(env->vtype, VTYPE, VLMUL));
68 flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
f1eed927 69 flags = FIELD_DP32(flags, TB_FLAGS, VTA,
70 FIELD_EX64(env->vtype, VTYPE, VTA));
53677acf
RH		 71 } else {
72 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
73 }
74
75#ifdef CONFIG_USER_ONLY
76 flags |= TB_FLAGS_MSTATUS_FS;
61b4b69d 77 flags |= TB_FLAGS_MSTATUS_VS;
53677acf
RH		 78#else
79 flags |= cpu_mmu_index(env, 0);
80 if (riscv_cpu_fp_enabled(env)) {
81 flags |= env->mstatus & MSTATUS_FS;
82 }
83
61b4b69d
LZ		 84 if (riscv_cpu_vector_enabled(env)) {
85 flags |= env->mstatus & MSTATUS_VS;
86 }
87
53677acf
RH		 88 if (riscv_has_ext(env, RVH)) {
89 if (env->priv == PRV_M ||
90 (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
91 (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
92 get_field(env->hstatus, HSTATUS_HU))) {
93 flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
94 }
95
96 flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS,
97 get_field(env->mstatus_hs, MSTATUS_FS));
8e1ee1fb
FC		 98
99 flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS,
100 get_field(env->mstatus_hs, MSTATUS_VS));
53677acf
RH		 101 }
102#endif
103
440544e1 104 flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
4208dc7e
LZ		 105 if (env->cur_pmmask < (env->xl == MXL_RV32 ? UINT32_MAX : UINT64_MAX)) {
106 flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1);
107 }
108 if (env->cur_pmbase != 0) {
109 flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1);
110 }
92371bd9 111
53677acf
RH		 112 *pflags = flags;
113}
114
40bfa5f6
LZ		 115void riscv_cpu_update_mask(CPURISCVState *env)
116{
117 target_ulong mask = -1, base = 0;
118 /*
119 * TODO: Current RVJ spec does not specify
120 * how the extension interacts with XLEN.
121 */
122#ifndef CONFIG_USER_ONLY
123 if (riscv_has_ext(env, RVJ)) {
124 switch (env->priv) {
125 case PRV_M:
126 if (env->mmte & M_PM_ENABLE) {
127 mask = env->mpmmask;
128 base = env->mpmbase;
129 }
130 break;
131 case PRV_S:
132 if (env->mmte & S_PM_ENABLE) {
133 mask = env->spmmask;
134 base = env->spmbase;
135 }
136 break;
137 case PRV_U:
138 if (env->mmte & U_PM_ENABLE) {
139 mask = env->upmmask;
140 base = env->upmbase;
141 }
142 break;
143 default:
144 g_assert_not_reached();
145 }
146 }
147#endif
148 if (env->xl == MXL_RV32) {
149 env->cur_pmmask = mask & UINT32_MAX;
150 env->cur_pmbase = base & UINT32_MAX;
151 } else {
152 env->cur_pmmask = mask;
153 env->cur_pmbase = base;
154 }
155}
156
0c3e702a 157#ifndef CONFIG_USER_ONLY
43dc93af
AP		 158
159/*
160 * The HS-mode is allowed to configure priority only for the
161 * following VS-mode local interrupts:
162 *
163 * 0 (Reserved interrupt, reads as zero)
164 * 1 Supervisor software interrupt
165 * 4 (Reserved interrupt, reads as zero)
166 * 5 Supervisor timer interrupt
167 * 8 (Reserved interrupt, reads as zero)
168 * 13 (Reserved interrupt)
169 * 14 "
170 * 15 "
171 * 16 "
43577499
AP		 172 * 17 "
173 * 18 "
174 * 19 "
175 * 20 "
176 * 21 "
43dc93af 177 * 22 "
43577499 178 * 23 "
43dc93af
AP		 179 */
180
181static const int hviprio_index2irq[] = {
43577499 182 0, 1, 4, 5, 8, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 };
43dc93af
AP		 183static const int hviprio_index2rdzero[] = {
184 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
185
186int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero)
0c3e702a 187{
43dc93af
AP		 188 if (index < 0 || ARRAY_SIZE(hviprio_index2irq) <= index) {
189 return -EINVAL;
190 }
3ef10a09 191
43dc93af
AP		 192 if (out_irq) {
193 *out_irq = hviprio_index2irq[index];
194 }
3ef10a09 195
43dc93af
AP		 196 if (out_rdzero) {
197 *out_rdzero = hviprio_index2rdzero[index];
198 }
cd032fe7 199
43dc93af
AP		 200 return 0;
201}
3ef10a09 202
43dc93af
AP		 203/*
204 * Default priorities of local interrupts are defined in the
205 * RISC-V Advanced Interrupt Architecture specification.
206 *
207 * ----------------------------------------------------------------
208 * Default |
209 * Priority | Major Interrupt Numbers
210 * ----------------------------------------------------------------
43577499
AP		 211 * Highest | 47, 23, 46, 45, 22, 44,
212 * | 43, 21, 42, 41, 20, 40
43dc93af
AP		 213 * |
214 * | 11 (0b), 3 (03), 7 (07)
215 * | 9 (09), 1 (01), 5 (05)
216 * | 12 (0c)
217 * | 10 (0a), 2 (02), 6 (06)
218 * |
43577499
AP		 219 * | 39, 19, 38, 37, 18, 36,
220 * Lowest | 35, 17, 34, 33, 16, 32
43dc93af
AP		 221 * ----------------------------------------------------------------
222 */
223static const uint8_t default_iprio[64] = {
43577499
AP		 224 /* Custom interrupts 48 to 63 */
225 [63] = IPRIO_MMAXIPRIO,
226 [62] = IPRIO_MMAXIPRIO,
227 [61] = IPRIO_MMAXIPRIO,
228 [60] = IPRIO_MMAXIPRIO,
229 [59] = IPRIO_MMAXIPRIO,
230 [58] = IPRIO_MMAXIPRIO,
231 [57] = IPRIO_MMAXIPRIO,
232 [56] = IPRIO_MMAXIPRIO,
233 [55] = IPRIO_MMAXIPRIO,
234 [54] = IPRIO_MMAXIPRIO,
235 [53] = IPRIO_MMAXIPRIO,
236 [52] = IPRIO_MMAXIPRIO,
237 [51] = IPRIO_MMAXIPRIO,
238 [50] = IPRIO_MMAXIPRIO,
239 [49] = IPRIO_MMAXIPRIO,
240 [48] = IPRIO_MMAXIPRIO,
241
242 /* Custom interrupts 24 to 31 */
243 [31] = IPRIO_MMAXIPRIO,
244 [30] = IPRIO_MMAXIPRIO,
245 [29] = IPRIO_MMAXIPRIO,
246 [28] = IPRIO_MMAXIPRIO,
247 [27] = IPRIO_MMAXIPRIO,
248 [26] = IPRIO_MMAXIPRIO,
249 [25] = IPRIO_MMAXIPRIO,
250 [24] = IPRIO_MMAXIPRIO,
251
252 [47] = IPRIO_DEFAULT_UPPER,
253 [23] = IPRIO_DEFAULT_UPPER + 1,
254 [46] = IPRIO_DEFAULT_UPPER + 2,
255 [45] = IPRIO_DEFAULT_UPPER + 3,
256 [22] = IPRIO_DEFAULT_UPPER + 4,
257 [44] = IPRIO_DEFAULT_UPPER + 5,
258
259 [43] = IPRIO_DEFAULT_UPPER + 6,
260 [21] = IPRIO_DEFAULT_UPPER + 7,
261 [42] = IPRIO_DEFAULT_UPPER + 8,
262 [41] = IPRIO_DEFAULT_UPPER + 9,
263 [20] = IPRIO_DEFAULT_UPPER + 10,
264 [40] = IPRIO_DEFAULT_UPPER + 11,
43dc93af
AP		 265
266 [11] = IPRIO_DEFAULT_M,
267 [3] = IPRIO_DEFAULT_M + 1,
268 [7] = IPRIO_DEFAULT_M + 2,
269
270 [9] = IPRIO_DEFAULT_S,
271 [1] = IPRIO_DEFAULT_S + 1,
272 [5] = IPRIO_DEFAULT_S + 2,
273
274 [12] = IPRIO_DEFAULT_SGEXT,
275
276 [10] = IPRIO_DEFAULT_VS,
277 [2] = IPRIO_DEFAULT_VS + 1,
278 [6] = IPRIO_DEFAULT_VS + 2,
279
43577499
AP		 280 [39] = IPRIO_DEFAULT_LOWER,
281 [19] = IPRIO_DEFAULT_LOWER + 1,
282 [38] = IPRIO_DEFAULT_LOWER + 2,
283 [37] = IPRIO_DEFAULT_LOWER + 3,
284 [18] = IPRIO_DEFAULT_LOWER + 4,
285 [36] = IPRIO_DEFAULT_LOWER + 5,
286
287 [35] = IPRIO_DEFAULT_LOWER + 6,
288 [17] = IPRIO_DEFAULT_LOWER + 7,
289 [34] = IPRIO_DEFAULT_LOWER + 8,
290 [33] = IPRIO_DEFAULT_LOWER + 9,
291 [16] = IPRIO_DEFAULT_LOWER + 10,
292 [32] = IPRIO_DEFAULT_LOWER + 11,
43dc93af
AP		 293};
294
295uint8_t riscv_cpu_default_priority(int irq)
296{
297 if (irq < 0 || irq > 63) {
298 return IPRIO_MMAXIPRIO;
299 }
300
301 return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO;
302};
303
304static int riscv_cpu_pending_to_irq(CPURISCVState *env,
305 int extirq, unsigned int extirq_def_prio,
306 uint64_t pending, uint8_t *iprio)
307{
308 int irq, best_irq = RISCV_EXCP_NONE;
309 unsigned int prio, best_prio = UINT_MAX;
310
311 if (!pending) {
312 return RISCV_EXCP_NONE;
313 }
314
315 irq = ctz64(pending);
316 if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
317 return irq;
318 }
319
320 pending = pending >> irq;
321 while (pending) {
322 prio = iprio[irq];
323 if (!prio) {
324 if (irq == extirq) {
325 prio = extirq_def_prio;
326 } else {
327 prio = (riscv_cpu_default_priority(irq) < extirq_def_prio) ?
328 1 : IPRIO_MMAXIPRIO;
329 }
330 }
331 if ((pending & 0x1) && (prio <= best_prio)) {
332 best_irq = irq;
333 best_prio = prio;
334 }
335 irq++;
336 pending = pending >> 1;
337 }
338
339 return best_irq;
340}
341
8f42415f 342uint64_t riscv_cpu_all_pending(CPURISCVState *env)
43dc93af
AP		 343{
344 uint32_t gein = get_field(env->hstatus, HSTATUS_VGEIN);
345 uint64_t vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
346
347 return (env->mip | vsgein) & env->mie;
348}
349
350int riscv_cpu_mirq_pending(CPURISCVState *env)
351{
352 uint64_t irqs = riscv_cpu_all_pending(env) & ~env->mideleg &
353 ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
354
355 return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M,
356 irqs, env->miprio);
357}
358
359int riscv_cpu_sirq_pending(CPURISCVState *env)
360{
361 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg &
362 ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
363
364 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
365 irqs, env->siprio);
366}
367
368int riscv_cpu_vsirq_pending(CPURISCVState *env)
369{
370 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg &
371 (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
372
373 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
374 irqs >> 1, env->hviprio);
375}
376
377static int riscv_cpu_local_irq_pending(CPURISCVState *env)
378{
379 int virq;
380 uint64_t irqs, pending, mie, hsie, vsie;
381
382 /* Determine interrupt enable state of all privilege modes */
383 if (riscv_cpu_virt_enabled(env)) {
384 mie = 1;
385 hsie = 1;
386 vsie = (env->priv < PRV_S) ||
387 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE));
0c3e702a 388 } else {
43dc93af
AP		 389 mie = (env->priv < PRV_M) ||
390 (env->priv == PRV_M && get_field(env->mstatus, MSTATUS_MIE));
391 hsie = (env->priv < PRV_S) ||
392 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE));
393 vsie = 0;
394 }
395
396 /* Determine all pending interrupts */
397 pending = riscv_cpu_all_pending(env);
398
399 /* Check M-mode interrupts */
400 irqs = pending & ~env->mideleg & -mie;
401 if (irqs) {
402 return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M,
403 irqs, env->miprio);
404 }
405
406 /* Check HS-mode interrupts */
407 irqs = pending & env->mideleg & ~env->hideleg & -hsie;
408 if (irqs) {
409 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
410 irqs, env->siprio);
0c3e702a 411 }
43dc93af
AP		 412
413 /* Check VS-mode interrupts */
414 irqs = pending & env->mideleg & env->hideleg & -vsie;
415 if (irqs) {
416 virq = riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
417 irqs >> 1, env->hviprio);
418 return (virq <= 0) ? virq : virq + 1;
419 }
420
421 /* Indicate no pending interrupt */
422 return RISCV_EXCP_NONE;
0c3e702a 423}
0c3e702a
MC		 424
425bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
426{
0c3e702a
MC		 427 if (interrupt_request & CPU_INTERRUPT_HARD) {
428 RISCVCPU *cpu = RISCV_CPU(cs);
429 CPURISCVState *env = &cpu->env;
efbdbc26 430 int interruptno = riscv_cpu_local_irq_pending(env);
0c3e702a
MC		 431 if (interruptno >= 0) {
432 cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno;
433 riscv_cpu_do_interrupt(cs);
434 return true;
435 }
436 }
0c3e702a
MC		 437 return false;
438}
439
b345b480
AF		 440/* Return true is floating point support is currently enabled */
441bool riscv_cpu_fp_enabled(CPURISCVState *env)
442{
443 if (env->mstatus & MSTATUS_FS) {
29409c1d
AF		 444 if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_FS)) {
445 return false;
446 }
b345b480
AF		 447 return true;
448 }
449
450 return false;
451}
452
61b4b69d
LZ		 453/* Return true is vector support is currently enabled */
454bool riscv_cpu_vector_enabled(CPURISCVState *env)
455{
456 if (env->mstatus & MSTATUS_VS) {
457 if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_VS)) {
458 return false;
459 }
460 return true;
461 }
462
463 return false;
464}
465
66e594f2
AF		 466void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
467{
c163b3ba 468 uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM |
284d697c 469 MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE |
61b4b69d 470 MSTATUS64_UXL | MSTATUS_VS;
c163b3ba
WL		 471
472 if (riscv_has_ext(env, RVF)) {
473 mstatus_mask |= MSTATUS_FS;
474 }
66e594f2
AF		 475 bool current_virt = riscv_cpu_virt_enabled(env);
476
477 g_assert(riscv_has_ext(env, RVH));
478
66e594f2
AF		 479 if (current_virt) {
480 /* Current V=1 and we are about to change to V=0 */
481 env->vsstatus = env->mstatus & mstatus_mask;
482 env->mstatus &= ~mstatus_mask;
483 env->mstatus |= env->mstatus_hs;
484
485 env->vstvec = env->stvec;
486 env->stvec = env->stvec_hs;
487
488 env->vsscratch = env->sscratch;
489 env->sscratch = env->sscratch_hs;
490
491 env->vsepc = env->sepc;
492 env->sepc = env->sepc_hs;
493
494 env->vscause = env->scause;
495 env->scause = env->scause_hs;
496
ac12b601
AP		 497 env->vstval = env->stval;
498 env->stval = env->stval_hs;
66e594f2
AF		 499
500 env->vsatp = env->satp;
501 env->satp = env->satp_hs;
502 } else {
503 /* Current V=0 and we are about to change to V=1 */
504 env->mstatus_hs = env->mstatus & mstatus_mask;
505 env->mstatus &= ~mstatus_mask;
506 env->mstatus |= env->vsstatus;
507
508 env->stvec_hs = env->stvec;
509 env->stvec = env->vstvec;
510
511 env->sscratch_hs = env->sscratch;
512 env->sscratch = env->vsscratch;
513
514 env->sepc_hs = env->sepc;
515 env->sepc = env->vsepc;
516
517 env->scause_hs = env->scause;
518 env->scause = env->vscause;
519
ac12b601
AP		 520 env->stval_hs = env->stval;
521 env->stval = env->vstval;
66e594f2
AF		 522
523 env->satp_hs = env->satp;
524 env->satp = env->vsatp;
525 }
526}
527
cd032fe7
AP		 528target_ulong riscv_cpu_get_geilen(CPURISCVState *env)
529{
530 if (!riscv_has_ext(env, RVH)) {
531 return 0;
532 }
533
534 return env->geilen;
535}
536
537void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen)
538{
539 if (!riscv_has_ext(env, RVH)) {
540 return;
541 }
542
543 if (geilen > (TARGET_LONG_BITS - 1)) {
544 return;
545 }
546
547 env->geilen = geilen;
548}
549
ef6bb7b6
AF		 550bool riscv_cpu_virt_enabled(CPURISCVState *env)
551{
552 if (!riscv_has_ext(env, RVH)) {
553 return false;
554 }
555
556 return get_field(env->virt, VIRT_ONOFF);
557}
558
559void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
560{
561 if (!riscv_has_ext(env, RVH)) {
562 return;
563 }
564
eccc5a12
AF		 565 /* Flush the TLB on all virt mode changes. */
566 if (get_field(env->virt, VIRT_ONOFF) != enable) {
567 tlb_flush(env_cpu(env));
568 }
569
ef6bb7b6 570 env->virt = set_field(env->virt, VIRT_ONOFF, enable);
02d9565b
AP		 571
572 if (enable) {
573 /*
574 * The guest external interrupts from an interrupt controller are
575 * delivered only when the Guest/VM is running (i.e. V=1). This means
576 * any guest external interrupt which is triggered while the Guest/VM
577 * is not running (i.e. V=0) will be missed on QEMU resulting in guest
578 * with sluggish response to serial console input and other I/O events.
579 *
580 * To solve this, we check and inject interrupt after setting V=1.
581 */
582 riscv_cpu_update_mip(env_archcpu(env), 0, 0);
583 }
ef6bb7b6
AF		 584}
585
1c1c060a 586bool riscv_cpu_two_stage_lookup(int mmu_idx)
5a894dd7 587{
1c1c060a 588 return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK;
5a894dd7
AF		 589}
590
d028ac75 591int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts)
e3e7039c
MC		 592{
593 CPURISCVState *env = &cpu->env;
594 if (env->miclaim & interrupts) {
595 return -1;
596 } else {
597 env->miclaim |= interrupts;
598 return 0;
599 }
600}
601
d028ac75 602uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value)
df354dd4
MC		 603{
604 CPURISCVState *env = &cpu->env;
0a01f2ee 605 CPUState *cs = CPU(cpu);
d028ac75 606 uint64_t gein, vsgein = 0, old = env->mip;
7ec5d303
AF		 607 bool locked = false;
608
cd032fe7
AP		 609 if (riscv_cpu_virt_enabled(env)) {
610 gein = get_field(env->hstatus, HSTATUS_VGEIN);
611 vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
612 }
613
7ec5d303
AF		 614 if (!qemu_mutex_iothread_locked()) {
615 locked = true;
616 qemu_mutex_lock_iothread();
617 }
df354dd4 618
7ec5d303 619 env->mip = (env->mip & ~mask) | (value & mask);
df354dd4 620
cd032fe7 621 if (env->mip | vsgein) {
7ec5d303
AF		 622 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
623 } else {
624 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
625 }
0a01f2ee 626
7ec5d303
AF		 627 if (locked) {
628 qemu_mutex_unlock_iothread();
629 }
df354dd4
MC		 630
631 return old;
632}
633
e2f01f3c
FC		 634void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *),
635 void *arg)
c6957248
AP		 636{
637 env->rdtime_fn = fn;
a47ef6e9 638 env->rdtime_fn_arg = arg;
c6957248
AP		 639}
640
69077dd6
AP		 641void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
642 int (*rmw_fn)(void *arg,
643 target_ulong reg,
644 target_ulong *val,
645 target_ulong new_val,
646 target_ulong write_mask),
647 void *rmw_fn_arg)
648{
649 if (priv <= PRV_M) {
650 env->aia_ireg_rmw_fn[priv] = rmw_fn;
651 env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg;
652 }
653}
654
fb738839 655void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
df354dd4
MC		 656{
657 if (newpriv > PRV_M) {
658 g_assert_not_reached();
659 }
660 if (newpriv == PRV_H) {
661 newpriv = PRV_U;
662 }
663 /* tlb_flush is unnecessary as mode is contained in mmu_idx */
664 env->priv = newpriv;
440544e1 665 env->xl = cpu_recompute_xl(env);
40bfa5f6 666 riscv_cpu_update_mask(env);
c13b169f
JS		 667
668 /*
669 * Clear the load reservation - otherwise a reservation placed in one
670 * context/process can be used by another, resulting in an SC succeeding
671 * incorrectly. Version 2.2 of the ISA specification explicitly requires
672 * this behaviour, while later revisions say that the kernel "should" use
673 * an SC instruction to force the yielding of a load reservation on a
674 * preemptive context switch. As a result, do both.
675 */
676 env->load_res = -1;
df354dd4
MC		 677}
678
b297129a
JS		 679/*
680 * get_physical_address_pmp - check PMP permission for this physical address
681 *
682 * Match the PMP region and check permission for this physical address and it's
683 * TLB page. Returns 0 if the permission checking was successful
684 *
685 * @env: CPURISCVState
686 * @prot: The returned protection attributes
687 * @tlb_size: TLB page size containing addr. It could be modified after PMP
688 * permission checking. NULL if not set TLB page for addr.
689 * @addr: The physical address to be checked permission
690 * @access_type: The type of MMU access
691 * @mode: Indicates current privilege level.
692 */
693static int get_physical_address_pmp(CPURISCVState *env, int *prot,
694 target_ulong *tlb_size, hwaddr addr,
695 int size, MMUAccessType access_type,
696 int mode)
697{
698 pmp_priv_t pmp_priv;
699 target_ulong tlb_size_pmp = 0;
700
701 if (!riscv_feature(env, RISCV_FEATURE_PMP)) {
702 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
703 return TRANSLATE_SUCCESS;
704 }
705
706 if (!pmp_hart_has_privs(env, addr, size, 1 << access_type, &pmp_priv,
707 mode)) {
708 *prot = 0;
709 return TRANSLATE_PMP_FAIL;
710 }
711
712 *prot = pmp_priv_to_page_prot(pmp_priv);
713 if (tlb_size != NULL) {
714 if (pmp_is_range_in_tlb(env, addr & ~(*tlb_size - 1), &tlb_size_pmp)) {
715 *tlb_size = tlb_size_pmp;
716 }
717 }
718
719 return TRANSLATE_SUCCESS;
720}
721
0c3e702a
MC		 722/* get_physical_address - get the physical address for this virtual address
723 *
724 * Do a page table walk to obtain the physical address corresponding to a
725 * virtual address. Returns 0 if the translation was successful
726 *
727 * Adapted from Spike's mmu_t::translate and mmu_t::walk
728 *
1448689c
AF		 729 * @env: CPURISCVState
730 * @physical: This will be set to the calculated physical address
731 * @prot: The returned protection attributes
732 * @addr: The virtual address to be translated
33a9a57d
YJ		 733 * @fault_pte_addr: If not NULL, this will be set to fault pte address
734 * when a error occurs on pte address translation.
735 * This will already be shifted to match htval.
1448689c
AF		 736 * @access_type: The type of MMU access
737 * @mmu_idx: Indicates current privilege level
738 * @first_stage: Are we in first stage translation?
739 * Second stage is used for hypervisor guest translation
36a18664 740 * @two_stage: Are we going to perform two stage translation
11c27c6d 741 * @is_debug: Is this access from a debugger or the monitor?
0c3e702a
MC		 742 */
743static int get_physical_address(CPURISCVState *env, hwaddr *physical,
744 int *prot, target_ulong addr,
33a9a57d 745 target_ulong *fault_pte_addr,
1448689c 746 int access_type, int mmu_idx,
11c27c6d
JF		 747 bool first_stage, bool two_stage,
748 bool is_debug)
0c3e702a
MC		 749{
750 /* NOTE: the env->pc value visible here will not be
751 * correct, but the value visible to the exception handler
752 * (riscv_cpu_do_interrupt) is correct */
aacb578f
PD		 753 MemTxResult res;
754 MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
c445593d 755 int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK;
36a18664 756 bool use_background = false;
05e6ca5e
GR		 757 hwaddr ppn;
758 RISCVCPU *cpu = env_archcpu(env);
2bacb224
WL		 759 int napot_bits = 0;
760 target_ulong napot_mask;
0c3e702a 761
36a18664
AF		 762 /*
763 * Check if we should use the background registers for the two
764 * stage translation. We don't need to check if we actually need
765 * two stage translation as that happened before this function
766 * was called. Background registers will be used if the guest has
767 * forced a two stage translation to be on (in HS or M mode).
768 */
db9ab38b 769 if (!riscv_cpu_virt_enabled(env) && two_stage) {
29b3361b
AF		 770 use_background = true;
771 }
772
90ec1cff
GK		 773 /* MPRV does not affect the virtual-machine load/store
774 instructions, HLV, HLVX, and HSV. */
775 if (riscv_cpu_two_stage_lookup(mmu_idx)) {
776 mode = get_field(env->hstatus, HSTATUS_SPVP);
777 } else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
0c3e702a
MC		 778 if (get_field(env->mstatus, MSTATUS_MPRV)) {
779 mode = get_field(env->mstatus, MSTATUS_MPP);
780 }
781 }
782
36a18664
AF		 783 if (first_stage == false) {
784 /* We are in stage 2 translation, this is similar to stage 1. */
785 /* Stage 2 is always taken as U-mode */
786 mode = PRV_U;
787 }
788
0c3e702a
MC		 789 if (mode == PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) {
790 *physical = addr;
791 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
792 return TRANSLATE_SUCCESS;
793 }
794
795 *prot = 0;
796
ddf78132 797 hwaddr base;
36a18664
AF		 798 int levels, ptidxbits, ptesize, vm, sum, mxr, widened;
799
800 if (first_stage == true) {
801 mxr = get_field(env->mstatus, MSTATUS_MXR);
802 } else {
803 mxr = get_field(env->vsstatus, MSTATUS_MXR);
804 }
0c3e702a 805
1a9540d1
AF		 806 if (first_stage == true) {
807 if (use_background) {
db23e5d9 808 if (riscv_cpu_mxl(env) == MXL_RV32) {
419ddf00
AF		 809 base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT;
810 vm = get_field(env->vsatp, SATP32_MODE);
811 } else {
812 base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT;
813 vm = get_field(env->vsatp, SATP64_MODE);
814 }
36a18664 815 } else {
db23e5d9 816 if (riscv_cpu_mxl(env) == MXL_RV32) {
419ddf00
AF		 817 base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
818 vm = get_field(env->satp, SATP32_MODE);
819 } else {
820 base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT;
821 vm = get_field(env->satp, SATP64_MODE);
822 }
0c3e702a 823 }
36a18664 824 widened = 0;
1a9540d1 825 } else {
db23e5d9 826 if (riscv_cpu_mxl(env) == MXL_RV32) {
994b6bb2
AF		 827 base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT;
828 vm = get_field(env->hgatp, SATP32_MODE);
829 } else {
830 base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT;
831 vm = get_field(env->hgatp, SATP64_MODE);
832 }
1a9540d1
AF		 833 widened = 2;
834 }
c63ca4ff 835 /* status.SUM will be ignored if execute on background */
11c27c6d 836 sum = get_field(env->mstatus, MSTATUS_SUM) || use_background || is_debug;
1a9540d1
AF		 837 switch (vm) {
838 case VM_1_10_SV32:
839 levels = 2; ptidxbits = 10; ptesize = 4; break;
840 case VM_1_10_SV39:
841 levels = 3; ptidxbits = 9; ptesize = 8; break;
842 case VM_1_10_SV48:
843 levels = 4; ptidxbits = 9; ptesize = 8; break;
844 case VM_1_10_SV57:
845 levels = 5; ptidxbits = 9; ptesize = 8; break;
846 case VM_1_10_MBARE:
847 *physical = addr;
848 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
849 return TRANSLATE_SUCCESS;
850 default:
851 g_assert_not_reached();
0c3e702a
MC		 852 }
853
3109cd98 854 CPUState *cs = env_cpu(env);
36a18664
AF		 855 int va_bits = PGSHIFT + levels * ptidxbits + widened;
856 target_ulong mask, masked_msbs;
857
858 if (TARGET_LONG_BITS > (va_bits - 1)) {
859 mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1;
860 } else {
861 mask = 0;
862 }
863 masked_msbs = (addr >> (va_bits - 1)) & mask;
864
0c3e702a
MC		 865 if (masked_msbs != 0 && masked_msbs != mask) {
866 return TRANSLATE_FAIL;
867 }
868
869 int ptshift = (levels - 1) * ptidxbits;
870 int i;
871
872#if !TCG_OVERSIZED_GUEST
873restart:
874#endif
875 for (i = 0; i < levels; i++, ptshift -= ptidxbits) {
36a18664
AF		 876 target_ulong idx;
877 if (i == 0) {
878 idx = (addr >> (PGSHIFT + ptshift)) &
879 ((1 << (ptidxbits + widened)) - 1);
880 } else {
881 idx = (addr >> (PGSHIFT + ptshift)) &
0c3e702a 882 ((1 << ptidxbits) - 1);
36a18664 883 }
0c3e702a
MC		 884
885 /* check that physical address of PTE is legal */
36a18664
AF		 886 hwaddr pte_addr;
887
888 if (two_stage && first_stage) {
38472890 889 int vbase_prot;
36a18664
AF		 890 hwaddr vbase;
891
892 /* Do the second stage translation on the base PTE address. */
88914473 893 int vbase_ret = get_physical_address(env, &vbase, &vbase_prot,
33a9a57d 894 base, NULL, MMU_DATA_LOAD,
11c27c6d
JF		 895 mmu_idx, false, true,
896 is_debug);
88914473
AF		 897
898 if (vbase_ret != TRANSLATE_SUCCESS) {
33a9a57d
YJ		 899 if (fault_pte_addr) {
900 *fault_pte_addr = (base + idx * ptesize) >> 2;
901 }
902 return TRANSLATE_G_STAGE_FAIL;
88914473 903 }
36a18664
AF		 904
905 pte_addr = vbase + idx * ptesize;
906 } else {
907 pte_addr = base + idx * ptesize;
908 }
1f447aec 909
b297129a
JS		 910 int pmp_prot;
911 int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr,
912 sizeof(target_ulong),
913 MMU_DATA_LOAD, PRV_S);
914 if (pmp_ret != TRANSLATE_SUCCESS) {
1f447aec
HA		 915 return TRANSLATE_PMP_FAIL;
916 }
aacb578f 917
f08c7ff3 918 target_ulong pte;
db23e5d9 919 if (riscv_cpu_mxl(env) == MXL_RV32) {
f08c7ff3
AF		 920 pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
921 } else {
922 pte = address_space_ldq(cs->as, pte_addr, attrs, &res);
923 }
924
aacb578f
PD		 925 if (res != MEMTX_OK) {
926 return TRANSLATE_FAIL;
927 }
928
05e6ca5e
GR		 929 if (riscv_cpu_sxl(env) == MXL_RV32) {
930 ppn = pte >> PTE_PPN_SHIFT;
931 } else if (cpu->cfg.ext_svpbmt || cpu->cfg.ext_svnapot) {
932 ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT;
933 } else {
934 ppn = pte >> PTE_PPN_SHIFT;
935 if ((pte & ~(target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT) {
936 return TRANSLATE_FAIL;
937 }
938 }
0c3e702a 939
c3b03e58
MC		 940 if (!(pte & PTE_V)) {
941 /* Invalid PTE */
942 return TRANSLATE_FAIL;
bbce8ba8
WL		 943 } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT)) {
944 return TRANSLATE_FAIL;
c3b03e58
MC		 945 } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
946 /* Inner PTE, continue walking */
bbce8ba8 947 if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) {
b6ecc63c
WL		 948 return TRANSLATE_FAIL;
949 }
0c3e702a 950 base = ppn << PGSHIFT;
c3b03e58
MC		 951 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
952 /* Reserved leaf PTE flags: PTE_W */
953 return TRANSLATE_FAIL;
954 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) {
955 /* Reserved leaf PTE flags: PTE_W + PTE_X */
956 return TRANSLATE_FAIL;
957 } else if ((pte & PTE_U) && ((mode != PRV_U) &&
958 (!sum || access_type == MMU_INST_FETCH))) {
959 /* User PTE flags when not U mode and mstatus.SUM is not set,
960 or the access type is an instruction fetch */
961 return TRANSLATE_FAIL;
962 } else if (!(pte & PTE_U) && (mode != PRV_S)) {
963 /* Supervisor PTE flags when not S mode */
964 return TRANSLATE_FAIL;
965 } else if (ppn & ((1ULL << ptshift) - 1)) {
966 /* Misaligned PPN */
967 return TRANSLATE_FAIL;
968 } else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) ||
969 ((pte & PTE_X) && mxr))) {
970 /* Read access check failed */
971 return TRANSLATE_FAIL;
972 } else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) {
973 /* Write access check failed */
974 return TRANSLATE_FAIL;
975 } else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) {
976 /* Fetch access check failed */
977 return TRANSLATE_FAIL;
0c3e702a
MC		 978 } else {
979 /* if necessary, set accessed and dirty bits. */
980 target_ulong updated_pte = pte | PTE_A |
981 (access_type == MMU_DATA_STORE ? PTE_D : 0);
982
983 /* Page table updates need to be atomic with MTTCG enabled */
984 if (updated_pte != pte) {
c3b03e58
MC		 985 /*
986 * - if accessed or dirty bits need updating, and the PTE is
987 * in RAM, then we do so atomically with a compare and swap.
988 * - if the PTE is in IO space or ROM, then it can't be updated
989 * and we return TRANSLATE_FAIL.
990 * - if the PTE changed by the time we went to update it, then
991 * it is no longer valid and we must re-walk the page table.
992 */
0c3e702a
MC		 993 MemoryRegion *mr;
994 hwaddr l = sizeof(target_ulong), addr1;
995 mr = address_space_translate(cs->as, pte_addr,
bc6b1cec 996 &addr1, &l, false, MEMTXATTRS_UNSPECIFIED);
c3b03e58 997 if (memory_region_is_ram(mr)) {
0c3e702a
MC		 998 target_ulong *pte_pa =
999 qemu_map_ram_ptr(mr->ram_block, addr1);
1000#if TCG_OVERSIZED_GUEST
1001 /* MTTCG is not enabled on oversized TCG guests so
1002 * page table updates do not need to be atomic */
1003 *pte_pa = pte = updated_pte;
1004#else
1005 target_ulong old_pte =
d73415a3 1006 qatomic_cmpxchg(pte_pa, pte, updated_pte);
0c3e702a
MC		 1007 if (old_pte != pte) {
1008 goto restart;
1009 } else {
1010 pte = updated_pte;
1011 }
1012#endif
1013 } else {
1014 /* misconfigured PTE in ROM (AD bits are not preset) or
1015 * PTE is in IO space and can't be updated atomically */
1016 return TRANSLATE_FAIL;
1017 }
1018 }
1019
1020 /* for superpage mappings, make a fake leaf PTE for the TLB's
1021 benefit. */
1022 target_ulong vpn = addr >> PGSHIFT;
2bacb224
WL		 1023
1024 if (cpu->cfg.ext_svnapot && (pte & PTE_N)) {
1025 napot_bits = ctzl(ppn) + 1;
1026 if ((i != (levels - 1)) || (napot_bits != 4)) {
1027 return TRANSLATE_FAIL;
1028 }
1029 }
1030
1031 napot_mask = (1 << napot_bits) - 1;
1032 *physical = (((ppn & ~napot_mask) | (vpn & napot_mask) |
1033 (vpn & (((target_ulong)1 << ptshift) - 1))
1034 ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK);
0c3e702a 1035
c3b03e58
MC		 1036 /* set permissions on the TLB entry */
1037 if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
0c3e702a
MC		 1038 *prot |= PAGE_READ;
1039 }
1040 if ((pte & PTE_X)) {
1041 *prot |= PAGE_EXEC;
1042 }
c3b03e58
MC		 1043 /* add write permission on stores or if the page is already dirty,
1044 so that we TLB miss on later writes to update the dirty bit */
0c3e702a
MC		 1045 if ((pte & PTE_W) &&
1046 (access_type == MMU_DATA_STORE || (pte & PTE_D))) {
1047 *prot |= PAGE_WRITE;
1048 }
1049 return TRANSLATE_SUCCESS;
1050 }
1051 }
1052 return TRANSLATE_FAIL;
1053}
1054
1055static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
1448689c 1056 MMUAccessType access_type, bool pmp_violation,
8e2aa21b
AP		 1057 bool first_stage, bool two_stage,
1058 bool two_stage_indirect)
0c3e702a 1059{
3109cd98 1060 CPUState *cs = env_cpu(env);
994b6bb2 1061 int page_fault_exceptions, vm;
419ddf00
AF		 1062 uint64_t stap_mode;
1063
db23e5d9 1064 if (riscv_cpu_mxl(env) == MXL_RV32) {
419ddf00
AF		 1065 stap_mode = SATP32_MODE;
1066 } else {
1067 stap_mode = SATP64_MODE;
1068 }
994b6bb2 1069
1448689c 1070 if (first_stage) {
419ddf00 1071 vm = get_field(env->satp, stap_mode);
1448689c 1072 } else {
419ddf00 1073 vm = get_field(env->hgatp, stap_mode);
1448689c 1074 }
419ddf00 1075
994b6bb2
AF		 1076 page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation;
1077
0c3e702a
MC		 1078 switch (access_type) {
1079 case MMU_INST_FETCH:
b2ef6ab9
AF		 1080 if (riscv_cpu_virt_enabled(env) && !first_stage) {
1081 cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
1082 } else {
1083 cs->exception_index = page_fault_exceptions ?
1084 RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT;
1085 }
0c3e702a
MC		 1086 break;
1087 case MMU_DATA_LOAD:
1c1c060a 1088 if (two_stage && !first_stage) {
b2ef6ab9
AF		 1089 cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
1090 } else {
1091 cs->exception_index = page_fault_exceptions ?
1092 RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT;
1093 }
0c3e702a
MC		 1094 break;
1095 case MMU_DATA_STORE:
1c1c060a 1096 if (two_stage && !first_stage) {
b2ef6ab9
AF		 1097 cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
1098 } else {
1099 cs->exception_index = page_fault_exceptions ?
1100 RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
1101 }
0c3e702a
MC		 1102 break;
1103 default:
1104 g_assert_not_reached();
1105 }
1106 env->badaddr = address;
ec352d0c 1107 env->two_stage_lookup = two_stage;
8e2aa21b 1108 env->two_stage_indirect_lookup = two_stage_indirect;
0c3e702a
MC		 1109}
1110
1111hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
1112{
1113 RISCVCPU *cpu = RISCV_CPU(cs);
36a18664 1114 CPURISCVState *env = &cpu->env;
0c3e702a
MC		 1115 hwaddr phys_addr;
1116 int prot;
1117 int mmu_idx = cpu_mmu_index(&cpu->env, false);
1118
33a9a57d 1119 if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx,
11c27c6d 1120 true, riscv_cpu_virt_enabled(env), true)) {
0c3e702a
MC		 1121 return -1;
1122 }
36a18664
AF		 1123
1124 if (riscv_cpu_virt_enabled(env)) {
33a9a57d 1125 if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL,
11c27c6d 1126 0, mmu_idx, false, true, true)) {
36a18664
AF		 1127 return -1;
1128 }
1129 }
1130
9ef82119 1131 return phys_addr & TARGET_PAGE_MASK;
0c3e702a
MC		 1132}
1133
37207e12
PD		 1134void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
1135 vaddr addr, unsigned size,
1136 MMUAccessType access_type,
1137 int mmu_idx, MemTxAttrs attrs,
1138 MemTxResult response, uintptr_t retaddr)
cbf58276
MC		 1139{
1140 RISCVCPU *cpu = RISCV_CPU(cs);
1141 CPURISCVState *env = &cpu->env;
1142
37207e12 1143 if (access_type == MMU_DATA_STORE) {
cbf58276 1144 cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
f9e580c1 1145 } else if (access_type == MMU_DATA_LOAD) {
cbf58276 1146 cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
f9e580c1
EB		 1147 } else {
1148 cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
cbf58276
MC		 1149 }
1150
1151 env->badaddr = addr;
ec352d0c
GK		 1152 env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
1153 riscv_cpu_two_stage_lookup(mmu_idx);
8e2aa21b 1154 env->two_stage_indirect_lookup = false;
ac684717 1155 cpu_loop_exit_restore(cs, retaddr);
cbf58276
MC		 1156}
1157
0c3e702a
MC		 1158void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
1159 MMUAccessType access_type, int mmu_idx,
1160 uintptr_t retaddr)
1161{
1162 RISCVCPU *cpu = RISCV_CPU(cs);
1163 CPURISCVState *env = &cpu->env;
1164 switch (access_type) {
1165 case MMU_INST_FETCH:
1166 cs->exception_index = RISCV_EXCP_INST_ADDR_MIS;
1167 break;
1168 case MMU_DATA_LOAD:
1169 cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS;
1170 break;
1171 case MMU_DATA_STORE:
1172 cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS;
1173 break;
1174 default:
1175 g_assert_not_reached();
1176 }
1177 env->badaddr = addr;
ec352d0c
GK		 1178 env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
1179 riscv_cpu_two_stage_lookup(mmu_idx);
8e2aa21b 1180 env->two_stage_indirect_lookup = false;
ac684717 1181 cpu_loop_exit_restore(cs, retaddr);
0c3e702a 1182}
0c3e702a 1183
8a4ca3c1
RH		 1184bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
1185 MMUAccessType access_type, int mmu_idx,
1186 bool probe, uintptr_t retaddr)
0c3e702a
MC		 1187{
1188 RISCVCPU *cpu = RISCV_CPU(cs);
1189 CPURISCVState *env = &cpu->env;
36a18664 1190 vaddr im_address;
0c3e702a 1191 hwaddr pa = 0;
b297129a 1192 int prot, prot2, prot_pmp;
635b0b0e 1193 bool pmp_violation = false;
36a18664 1194 bool first_stage_error = true;
1c1c060a 1195 bool two_stage_lookup = false;
8e2aa21b 1196 bool two_stage_indirect_error = false;
0c3e702a 1197 int ret = TRANSLATE_FAIL;
cc0fdb29 1198 int mode = mmu_idx;
b297129a
JS		 1199 /* default TLB page size */
1200 target_ulong tlb_size = TARGET_PAGE_SIZE;
0c3e702a 1201
36a18664
AF		 1202 env->guest_phys_fault_addr = 0;
1203
8a4ca3c1
RH		 1204 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
1205 __func__, address, access_type, mmu_idx);
1206
90ec1cff
GK		 1207 /* MPRV does not affect the virtual-machine load/store
1208 instructions, HLV, HLVX, and HSV. */
1209 if (riscv_cpu_two_stage_lookup(mmu_idx)) {
1210 mode = get_field(env->hstatus, HSTATUS_SPVP);
1211 } else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
1212 get_field(env->mstatus, MSTATUS_MPRV)) {
1213 mode = get_field(env->mstatus, MSTATUS_MPP);
1214 if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) {
1215 two_stage_lookup = true;
cc0fdb29
HA		 1216 }
1217 }
1218
29b3361b 1219 if (riscv_cpu_virt_enabled(env) ||
1c1c060a
AF		 1220 ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
1221 access_type != MMU_INST_FETCH)) {
36a18664 1222 /* Two stage lookup */
33a9a57d
YJ		 1223 ret = get_physical_address(env, &pa, &prot, address,
1224 &env->guest_phys_fault_addr, access_type,
11c27c6d 1225 mmu_idx, true, true, false);
36a18664 1226
33a9a57d
YJ		 1227 /*
1228 * A G-stage exception may be triggered during two state lookup.
1229 * And the env->guest_phys_fault_addr has already been set in
1230 * get_physical_address().
1231 */
1232 if (ret == TRANSLATE_G_STAGE_FAIL) {
1233 first_stage_error = false;
8e2aa21b 1234 two_stage_indirect_error = true;
33a9a57d
YJ		 1235 access_type = MMU_DATA_LOAD;
1236 }
1237
36a18664
AF		 1238 qemu_log_mask(CPU_LOG_MMU,
1239 "%s 1st-stage address=%" VADDR_PRIx " ret %d physical "
1240 TARGET_FMT_plx " prot %d\n",
1241 __func__, address, ret, pa, prot);
1242
33a9a57d 1243 if (ret == TRANSLATE_SUCCESS) {
36a18664
AF		 1244 /* Second stage lookup */
1245 im_address = pa;
1246
33a9a57d 1247 ret = get_physical_address(env, &pa, &prot2, im_address, NULL,
11c27c6d
JF		 1248 access_type, mmu_idx, false, true,
1249 false);
36a18664
AF		 1250
1251 qemu_log_mask(CPU_LOG_MMU,
1252 "%s 2nd-stage address=%" VADDR_PRIx " ret %d physical "
1253 TARGET_FMT_plx " prot %d\n",
8f67cd6d
AF		 1254 __func__, im_address, ret, pa, prot2);
1255
1256 prot &= prot2;
36a18664 1257
b297129a
JS		 1258 if (ret == TRANSLATE_SUCCESS) {
1259 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
1260 size, access_type, mode);
663e1193
JS		 1261
1262 qemu_log_mask(CPU_LOG_MMU,
1263 "%s PMP address=" TARGET_FMT_plx " ret %d prot"
1264 " %d tlb_size " TARGET_FMT_lu "\n",
1265 __func__, pa, ret, prot_pmp, tlb_size);
1266
b297129a 1267 prot &= prot_pmp;
36a18664
AF		 1268 }
1269
1270 if (ret != TRANSLATE_SUCCESS) {
1271 /*
1272 * Guest physical address translation failed, this is a HS
1273 * level exception
1274 */
1275 first_stage_error = false;
1276 env->guest_phys_fault_addr = (im_address |
1277 (address &
1278 (TARGET_PAGE_SIZE - 1))) >> 2;
1279 }
1280 }
1281 } else {
1282 /* Single stage lookup */
33a9a57d 1283 ret = get_physical_address(env, &pa, &prot, address, NULL,
11c27c6d 1284 access_type, mmu_idx, true, false, false);
36a18664
AF		 1285
1286 qemu_log_mask(CPU_LOG_MMU,
1287 "%s address=%" VADDR_PRIx " ret %d physical "
1288 TARGET_FMT_plx " prot %d\n",
1289 __func__, address, ret, pa, prot);
8a4ca3c1 1290
b297129a
JS		 1291 if (ret == TRANSLATE_SUCCESS) {
1292 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
1293 size, access_type, mode);
663e1193
JS		 1294
1295 qemu_log_mask(CPU_LOG_MMU,
1296 "%s PMP address=" TARGET_FMT_plx " ret %d prot"
1297 " %d tlb_size " TARGET_FMT_lu "\n",
1298 __func__, pa, ret, prot_pmp, tlb_size);
1299
b297129a
JS		 1300 prot &= prot_pmp;
1301 }
1f447aec 1302 }
b297129a 1303
1f447aec 1304 if (ret == TRANSLATE_PMP_FAIL) {
635b0b0e 1305 pmp_violation = true;
0c3e702a 1306 }
36a18664 1307
0c3e702a 1308 if (ret == TRANSLATE_SUCCESS) {
b297129a
JS		 1309 tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
1310 prot, mmu_idx, tlb_size);
8a4ca3c1
RH		 1311 return true;
1312 } else if (probe) {
1313 return false;
1314 } else {
1c1c060a
AF		 1315 raise_mmu_exception(env, address, access_type, pmp_violation,
1316 first_stage_error,
1317 riscv_cpu_virt_enabled(env) ||
8e2aa21b
AP		 1318 riscv_cpu_two_stage_lookup(mmu_idx),
1319 two_stage_indirect_error);
ac684717 1320 cpu_loop_exit_restore(cs, retaddr);
0c3e702a 1321 }
36a18664
AF		 1322
1323 return true;
0c3e702a 1324}
8e2aa21b
AP		 1325
1326static target_ulong riscv_transformed_insn(CPURISCVState *env,
1327 target_ulong insn,
1328 target_ulong taddr)
1329{
1330 target_ulong xinsn = 0;
1331 target_ulong access_rs1 = 0, access_imm = 0, access_size = 0;
1332
1333 /*
1334 * Only Quadrant 0 and Quadrant 2 of RVC instruction space need to
1335 * be uncompressed. The Quadrant 1 of RVC instruction space need
1336 * not be transformed because these instructions won't generate
1337 * any load/store trap.
1338 */
1339
1340 if ((insn & 0x3) != 0x3) {
1341 /* Transform 16bit instruction into 32bit instruction */
1342 switch (GET_C_OP(insn)) {
1343 case OPC_RISC_C_OP_QUAD0: /* Quadrant 0 */
1344 switch (GET_C_FUNC(insn)) {
1345 case OPC_RISC_C_FUNC_FLD_LQ:
1346 if (riscv_cpu_xlen(env) != 128) { /* C.FLD (RV32/64) */
1347 xinsn = OPC_RISC_FLD;
1348 xinsn = SET_RD(xinsn, GET_C_RS2S(insn));
1349 access_rs1 = GET_C_RS1S(insn);
1350 access_imm = GET_C_LD_IMM(insn);
1351 access_size = 8;
1352 }
1353 break;
1354 case OPC_RISC_C_FUNC_LW: /* C.LW */
1355 xinsn = OPC_RISC_LW;
1356 xinsn = SET_RD(xinsn, GET_C_RS2S(insn));
1357 access_rs1 = GET_C_RS1S(insn);
1358 access_imm = GET_C_LW_IMM(insn);
1359 access_size = 4;
1360 break;
1361 case OPC_RISC_C_FUNC_FLW_LD:
1362 if (riscv_cpu_xlen(env) == 32) { /* C.FLW (RV32) */
1363 xinsn = OPC_RISC_FLW;
1364 xinsn = SET_RD(xinsn, GET_C_RS2S(insn));
1365 access_rs1 = GET_C_RS1S(insn);
1366 access_imm = GET_C_LW_IMM(insn);
1367 access_size = 4;
1368 } else { /* C.LD (RV64/RV128) */
1369 xinsn = OPC_RISC_LD;
1370 xinsn = SET_RD(xinsn, GET_C_RS2S(insn));
1371 access_rs1 = GET_C_RS1S(insn);
1372 access_imm = GET_C_LD_IMM(insn);
1373 access_size = 8;
1374 }
1375 break;
1376 case OPC_RISC_C_FUNC_FSD_SQ:
1377 if (riscv_cpu_xlen(env) != 128) { /* C.FSD (RV32/64) */
1378 xinsn = OPC_RISC_FSD;
1379 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn));
1380 access_rs1 = GET_C_RS1S(insn);
1381 access_imm = GET_C_SD_IMM(insn);
1382 access_size = 8;
1383 }
1384 break;
1385 case OPC_RISC_C_FUNC_SW: /* C.SW */
1386 xinsn = OPC_RISC_SW;
1387 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn));
1388 access_rs1 = GET_C_RS1S(insn);
1389 access_imm = GET_C_SW_IMM(insn);
1390 access_size = 4;
1391 break;
1392 case OPC_RISC_C_FUNC_FSW_SD:
1393 if (riscv_cpu_xlen(env) == 32) { /* C.FSW (RV32) */
1394 xinsn = OPC_RISC_FSW;
1395 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn));
1396 access_rs1 = GET_C_RS1S(insn);
1397 access_imm = GET_C_SW_IMM(insn);
1398 access_size = 4;
1399 } else { /* C.SD (RV64/RV128) */
1400 xinsn = OPC_RISC_SD;
1401 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn));
1402 access_rs1 = GET_C_RS1S(insn);
1403 access_imm = GET_C_SD_IMM(insn);
1404 access_size = 8;
1405 }
1406 break;
1407 default:
1408 break;
1409 }
1410 break;
1411 case OPC_RISC_C_OP_QUAD2: /* Quadrant 2 */
1412 switch (GET_C_FUNC(insn)) {
1413 case OPC_RISC_C_FUNC_FLDSP_LQSP:
1414 if (riscv_cpu_xlen(env) != 128) { /* C.FLDSP (RV32/64) */
1415 xinsn = OPC_RISC_FLD;
1416 xinsn = SET_RD(xinsn, GET_C_RD(insn));
1417 access_rs1 = 2;
1418 access_imm = GET_C_LDSP_IMM(insn);
1419 access_size = 8;
1420 }
1421 break;
1422 case OPC_RISC_C_FUNC_LWSP: /* C.LWSP */
1423 xinsn = OPC_RISC_LW;
1424 xinsn = SET_RD(xinsn, GET_C_RD(insn));
1425 access_rs1 = 2;
1426 access_imm = GET_C_LWSP_IMM(insn);
1427 access_size = 4;
1428 break;
1429 case OPC_RISC_C_FUNC_FLWSP_LDSP:
1430 if (riscv_cpu_xlen(env) == 32) { /* C.FLWSP (RV32) */
1431 xinsn = OPC_RISC_FLW;
1432 xinsn = SET_RD(xinsn, GET_C_RD(insn));
1433 access_rs1 = 2;
1434 access_imm = GET_C_LWSP_IMM(insn);
1435 access_size = 4;
1436 } else { /* C.LDSP (RV64/RV128) */
1437 xinsn = OPC_RISC_LD;
1438 xinsn = SET_RD(xinsn, GET_C_RD(insn));
1439 access_rs1 = 2;
1440 access_imm = GET_C_LDSP_IMM(insn);
1441 access_size = 8;
1442 }
1443 break;
1444 case OPC_RISC_C_FUNC_FSDSP_SQSP:
1445 if (riscv_cpu_xlen(env) != 128) { /* C.FSDSP (RV32/64) */
1446 xinsn = OPC_RISC_FSD;
1447 xinsn = SET_RS2(xinsn, GET_C_RS2(insn));
1448 access_rs1 = 2;
1449 access_imm = GET_C_SDSP_IMM(insn);
1450 access_size = 8;
1451 }
1452 break;
1453 case OPC_RISC_C_FUNC_SWSP: /* C.SWSP */
1454 xinsn = OPC_RISC_SW;
1455 xinsn = SET_RS2(xinsn, GET_C_RS2(insn));
1456 access_rs1 = 2;
1457 access_imm = GET_C_SWSP_IMM(insn);
1458 access_size = 4;
1459 break;
1460 case 7:
1461 if (riscv_cpu_xlen(env) == 32) { /* C.FSWSP (RV32) */
1462 xinsn = OPC_RISC_FSW;
1463 xinsn = SET_RS2(xinsn, GET_C_RS2(insn));
1464 access_rs1 = 2;
1465 access_imm = GET_C_SWSP_IMM(insn);
1466 access_size = 4;
1467 } else { /* C.SDSP (RV64/RV128) */
1468 xinsn = OPC_RISC_SD;
1469 xinsn = SET_RS2(xinsn, GET_C_RS2(insn));
1470 access_rs1 = 2;
1471 access_imm = GET_C_SDSP_IMM(insn);
1472 access_size = 8;
1473 }
1474 break;
1475 default:
1476 break;
1477 }
1478 break;
1479 default:
1480 break;
1481 }
1482
1483 /*
1484 * Clear Bit1 of transformed instruction to indicate that
1485 * original insruction was a 16bit instruction
1486 */
1487 xinsn &= ~((target_ulong)0x2);
1488 } else {
1489 /* Transform 32bit (or wider) instructions */
1490 switch (MASK_OP_MAJOR(insn)) {
1491 case OPC_RISC_ATOMIC:
1492 xinsn = insn;
1493 access_rs1 = GET_RS1(insn);
1494 access_size = 1 << GET_FUNCT3(insn);
1495 break;
1496 case OPC_RISC_LOAD:
1497 case OPC_RISC_FP_LOAD:
1498 xinsn = SET_I_IMM(insn, 0);
1499 access_rs1 = GET_RS1(insn);
1500 access_imm = GET_IMM(insn);
1501 access_size = 1 << GET_FUNCT3(insn);
1502 break;
1503 case OPC_RISC_STORE:
1504 case OPC_RISC_FP_STORE:
1505 xinsn = SET_S_IMM(insn, 0);
1506 access_rs1 = GET_RS1(insn);
1507 access_imm = GET_STORE_IMM(insn);
1508 access_size = 1 << GET_FUNCT3(insn);
1509 break;
1510 case OPC_RISC_SYSTEM:
1511 if (MASK_OP_SYSTEM(insn) == OPC_RISC_HLVHSV) {
1512 xinsn = insn;
1513 access_rs1 = GET_RS1(insn);
1514 access_size = 1 << ((GET_FUNCT7(insn) >> 1) & 0x3);
1515 access_size = 1 << access_size;
1516 }
1517 break;
1518 default:
1519 break;
1520 }
1521 }
1522
1523 if (access_size) {
1524 xinsn = SET_RS1(xinsn, (taddr - (env->gpr[access_rs1] + access_imm)) &
1525 (access_size - 1));
1526 }
1527
1528 return xinsn;
1529}
263e2ab2 1530#endif /* !CONFIG_USER_ONLY */
0c3e702a
MC		 1531
1532/*
1533 * Handle Traps
1534 *
1535 * Adapted from Spike's processor_t::take_trap.
1536 *
1537 */
1538void riscv_cpu_do_interrupt(CPUState *cs)
1539{
1540#if !defined(CONFIG_USER_ONLY)
1541
1542 RISCVCPU *cpu = RISCV_CPU(cs);
1543 CPURISCVState *env = &cpu->env;
86d0c457 1544 bool write_gva = false;
284d697c 1545 uint64_t s;
0c3e702a 1546
acbbb94e
MC		 1547 /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide
1548 * so we mask off the MSB and separate into trap type and cause.
1549 */
1550 bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG);
1551 target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK;
d028ac75 1552 uint64_t deleg = async ? env->mideleg : env->medeleg;
acbbb94e 1553 target_ulong tval = 0;
8e2aa21b 1554 target_ulong tinst = 0;
30675539
AF		 1555 target_ulong htval = 0;
1556 target_ulong mtval2 = 0;
acbbb94e 1557
a10b9d93
KP		 1558 if (cause == RISCV_EXCP_SEMIHOST) {
1559 if (env->priv >= PRV_S) {
ed3a06b1 1560 do_common_semihosting(cs);
a10b9d93
KP		 1561 env->pc += 4;
1562 return;
1563 }
1564 cause = RISCV_EXCP_BREAKPOINT;
1565 }
1566
acbbb94e
MC		 1567 if (!async) {
1568 /* set tval to badaddr for traps with address information */
1569 switch (cause) {
ab67a1d0
AF		 1570 case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT:
1571 case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT:
acbbb94e
MC		 1572 case RISCV_EXCP_LOAD_ADDR_MIS:
1573 case RISCV_EXCP_STORE_AMO_ADDR_MIS:
1574 case RISCV_EXCP_LOAD_ACCESS_FAULT:
1575 case RISCV_EXCP_STORE_AMO_ACCESS_FAULT:
acbbb94e
MC		 1576 case RISCV_EXCP_LOAD_PAGE_FAULT:
1577 case RISCV_EXCP_STORE_PAGE_FAULT:
24826da0 1578 write_gva = env->two_stage_lookup;
acbbb94e 1579 tval = env->badaddr;
8e2aa21b
AP		 1580 if (env->two_stage_indirect_lookup) {
1581 /*
1582 * special pseudoinstruction for G-stage fault taken while
1583 * doing VS-stage page table walk.
1584 */
1585 tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000;
1586 } else {
1587 /*
1588 * The "Addr. Offset" field in transformed instruction is
1589 * non-zero only for misaligned access.
1590 */
1591 tinst = riscv_transformed_insn(env, env->bins, tval);
1592 }
1593 break;
1594 case RISCV_EXCP_INST_GUEST_PAGE_FAULT:
1595 case RISCV_EXCP_INST_ADDR_MIS:
1596 case RISCV_EXCP_INST_ACCESS_FAULT:
1597 case RISCV_EXCP_INST_PAGE_FAULT:
1598 write_gva = env->two_stage_lookup;
1599 tval = env->badaddr;
1600 if (env->two_stage_indirect_lookup) {
1601 /*
1602 * special pseudoinstruction for G-stage fault taken while
1603 * doing VS-stage page table walk.
1604 */
1605 tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000;
1606 }
acbbb94e 1607 break;
48eaeb56 1608 case RISCV_EXCP_ILLEGAL_INST:
62cf0245 1609 case RISCV_EXCP_VIRT_INSTRUCTION_FAULT:
48eaeb56
AF		 1610 tval = env->bins;
1611 break;
acbbb94e
MC		 1612 default:
1613 break;
0c3e702a 1614 }
acbbb94e
MC		 1615 /* ecall is dispatched as one cause so translate based on mode */
1616 if (cause == RISCV_EXCP_U_ECALL) {
1617 assert(env->priv <= 3);
5eb9e782
AF		 1618
1619 if (env->priv == PRV_M) {
1620 cause = RISCV_EXCP_M_ECALL;
1621 } else if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) {
1622 cause = RISCV_EXCP_VS_ECALL;
1623 } else if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) {
1624 cause = RISCV_EXCP_S_ECALL;
1625 } else if (env->priv == PRV_U) {
1626 cause = RISCV_EXCP_U_ECALL;
1627 }
0c3e702a
MC		 1628 }
1629 }
1630
c51a3f5d 1631 trace_riscv_trap(env->mhartid, async, cause, env->pc, tval,
69430111
AF		 1632 riscv_cpu_get_trap_name(cause, async));
1633
1634 qemu_log_mask(CPU_LOG_INT,
1635 "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", "
1636 "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n",
1637 __func__, env->mhartid, async, cause, env->pc, tval,
1638 riscv_cpu_get_trap_name(cause, async));
0c3e702a 1639
acbbb94e
MC		 1640 if (env->priv <= PRV_S &&
1641 cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
0c3e702a 1642 /* handle the trap in S-mode */
5eb9e782 1643 if (riscv_has_ext(env, RVH)) {
d028ac75 1644 uint64_t hdeleg = async ? env->hideleg : env->hedeleg;
1c1c060a 1645
50d16087 1646 if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1)) {
84b1c04b 1647 /* Trap to VS mode */
c5969a3a
RK		 1648 /*
1649 * See if we need to adjust cause. Yes if its VS mode interrupt
1650 * no if hypervisor has delegated one of hs mode's interrupt
1651 */
1652 if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT ||
84b1c04b 1653 cause == IRQ_VS_EXT) {
c5969a3a 1654 cause = cause - 1;
84b1c04b 1655 }
86d0c457 1656 write_gva = false;
5eb9e782
AF		 1657 } else if (riscv_cpu_virt_enabled(env)) {
1658 /* Trap into HS mode, from virt */
1659 riscv_cpu_swap_hypervisor_regs(env);
f2d5850f 1660 env->hstatus = set_field(env->hstatus, HSTATUS_SPVP,
ace54453 1661 env->priv);
5eb9e782
AF		 1662 env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
1663 riscv_cpu_virt_enabled(env));
1664
86d0c457 1665
30675539
AF		 1666 htval = env->guest_phys_fault_addr;
1667
5eb9e782 1668 riscv_cpu_set_virt_enabled(env, 0);
5eb9e782
AF		 1669 } else {
1670 /* Trap into HS mode */
ec352d0c 1671 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
30675539 1672 htval = env->guest_phys_fault_addr;
5eb9e782 1673 }
86d0c457 1674 env->hstatus = set_field(env->hstatus, HSTATUS_GVA, write_gva);
5eb9e782
AF		 1675 }
1676
1677 s = env->mstatus;
1a9540d1 1678 s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
0c3e702a
MC		 1679 s = set_field(s, MSTATUS_SPP, env->priv);
1680 s = set_field(s, MSTATUS_SIE, 0);
c7b95171 1681 env->mstatus = s;
16fdb8ff 1682 env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1));
acbbb94e 1683 env->sepc = env->pc;
ac12b601 1684 env->stval = tval;
30675539 1685 env->htval = htval;
8e2aa21b 1686 env->htinst = tinst;
acbbb94e
MC		 1687 env->pc = (env->stvec >> 2 << 2) +
1688 ((async && (env->stvec & 3) == 1) ? cause * 4 : 0);
fb738839 1689 riscv_cpu_set_mode(env, PRV_S);
0c3e702a 1690 } else {
acbbb94e 1691 /* handle the trap in M-mode */
5eb9e782
AF		 1692 if (riscv_has_ext(env, RVH)) {
1693 if (riscv_cpu_virt_enabled(env)) {
1694 riscv_cpu_swap_hypervisor_regs(env);
1695 }
1696 env->mstatus = set_field(env->mstatus, MSTATUS_MPV,
284d697c 1697 riscv_cpu_virt_enabled(env));
9034e90a
AF		 1698 if (riscv_cpu_virt_enabled(env) && tval) {
1699 env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1);
1700 }
5eb9e782 1701
30675539
AF		 1702 mtval2 = env->guest_phys_fault_addr;
1703
5eb9e782
AF		 1704 /* Trapping to M mode, virt is disabled */
1705 riscv_cpu_set_virt_enabled(env, 0);
5eb9e782
AF		 1706 }
1707
1708 s = env->mstatus;
1a9540d1 1709 s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE));
0c3e702a
MC		 1710 s = set_field(s, MSTATUS_MPP, env->priv);
1711 s = set_field(s, MSTATUS_MIE, 0);
c7b95171 1712 env->mstatus = s;
acbbb94e
MC		 1713 env->mcause = cause | ~(((target_ulong)-1) >> async);
1714 env->mepc = env->pc;
ac12b601 1715 env->mtval = tval;
30675539 1716 env->mtval2 = mtval2;
8e2aa21b 1717 env->mtinst = tinst;
acbbb94e
MC		 1718 env->pc = (env->mtvec >> 2 << 2) +
1719 ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);
fb738839 1720 riscv_cpu_set_mode(env, PRV_M);
0c3e702a 1721 }
d9360e96
MC		 1722
1723 /* NOTE: it is not necessary to yield load reservations here. It is only
1724 * necessary for an SC from "another hart" to cause a load reservation
1725 * to be yielded. Refer to the memory consistency model section of the
1726 * RISC-V ISA Specification.
1727 */
1728
ec352d0c 1729 env->two_stage_lookup = false;
8e2aa21b 1730 env->two_stage_indirect_lookup = false;
0c3e702a 1731#endif
330d2ae3 1732 cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */
0c3e702a 1733}
QEMU mirror