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hw/riscv: virt: Remove the redundant ipi-id property
[mirror_qemu.git] / target / riscv / cpu_helper.c
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0c3e702a 1/*
df354dd4 2 * RISC-V CPU helpers for qemu.
0c3e702a
MC		 3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "qemu/osdep.h"
21#include "qemu/log.h"
7ec5d303 22#include "qemu/main-loop.h"
0c3e702a 23#include "cpu.h"
892320fa 24#include "pmu.h"
0c3e702a 25#include "exec/exec-all.h"
8e2aa21b 26#include "instmap.h"
dcb32f1d 27#include "tcg/tcg-op.h"
929f0a7f 28#include "trace.h"
6b5fe137 29#include "semihosting/common-semi.h"
2c9d7471 30#include "sysemu/cpu-timers.h"
892320fa 31#include "cpu_bits.h"
2c9d7471 32#include "debug.h"
0c3e702a
MC		 33
34int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
35{
36#ifdef CONFIG_USER_ONLY
37 return 0;
38#else
39 return env->priv;
40#endif
41}
42
53677acf
RH		 43void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
44 target_ulong *cs_base, uint32_t *pflags)
45{
b4a99d40
FC		 46 CPUState *cs = env_cpu(env);
47 RISCVCPU *cpu = RISCV_CPU(cs);
48
53677acf
RH		 49 uint32_t flags = 0;
50
8c796f1a 51 *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
53677acf
RH		 52 *cs_base = 0;
53
32e579b8 54 if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) {
a689a82b
FC		 55 /*
56 * If env->vl equals to VLMAX, we can use generic vector operation
57 * expanders (GVEC) to accerlate the vector operations.
58 * However, as LMUL could be a fractional number. The maximum
59 * vector size can be operated might be less than 8 bytes,
60 * which is not supported by GVEC. So we set vl_eq_vlmax flag to true
61 * only when maxsz >= 8 bytes.
62 */
53677acf 63 uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);
a689a82b
FC		 64 uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW);
65 uint32_t maxsz = vlmax << sew;
66 bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) &&
67 (maxsz >= 8);
d96a271a 68 flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill);
a689a82b 69 flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew);
53677acf
RH		 70 flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
71 FIELD_EX64(env->vtype, VTYPE, VLMUL));
72 flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
f1eed927 73 flags = FIELD_DP32(flags, TB_FLAGS, VTA,
74 FIELD_EX64(env->vtype, VTYPE, VTA));
355d5584
YTC		 75 flags = FIELD_DP32(flags, TB_FLAGS, VMA,
76 FIELD_EX64(env->vtype, VTYPE, VMA));
53677acf
RH		 77 } else {
78 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
79 }
80
81#ifdef CONFIG_USER_ONLY
82 flags |= TB_FLAGS_MSTATUS_FS;
61b4b69d 83 flags |= TB_FLAGS_MSTATUS_VS;
53677acf
RH		 84#else
85 flags |= cpu_mmu_index(env, 0);
86 if (riscv_cpu_fp_enabled(env)) {
87 flags |= env->mstatus & MSTATUS_FS;
88 }
89
61b4b69d
LZ		 90 if (riscv_cpu_vector_enabled(env)) {
91 flags |= env->mstatus & MSTATUS_VS;
92 }
93
53677acf
RH		 94 if (riscv_has_ext(env, RVH)) {
95 if (env->priv == PRV_M ||
96 (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
97 (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
98 get_field(env->hstatus, HSTATUS_HU))) {
99 flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
100 }
101
102 flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS,
103 get_field(env->mstatus_hs, MSTATUS_FS));
8e1ee1fb
FC		 104
105 flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS,
106 get_field(env->mstatus_hs, MSTATUS_VS));
53677acf 107 }
2c9d7471 108 if (riscv_feature(env, RISCV_FEATURE_DEBUG) && !icount_enabled()) {
577f0286 109 flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled);
2c9d7471 110 }
53677acf
RH		 111#endif
112
440544e1 113 flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
4208dc7e
LZ		 114 if (env->cur_pmmask < (env->xl == MXL_RV32 ? UINT32_MAX : UINT64_MAX)) {
115 flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1);
116 }
117 if (env->cur_pmbase != 0) {
118 flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1);
119 }
92371bd9 120
53677acf
RH		 121 *pflags = flags;
122}
123
40bfa5f6
LZ		 124void riscv_cpu_update_mask(CPURISCVState *env)
125{
126 target_ulong mask = -1, base = 0;
127 /*
128 * TODO: Current RVJ spec does not specify
129 * how the extension interacts with XLEN.
130 */
131#ifndef CONFIG_USER_ONLY
132 if (riscv_has_ext(env, RVJ)) {
133 switch (env->priv) {
134 case PRV_M:
135 if (env->mmte & M_PM_ENABLE) {
136 mask = env->mpmmask;
137 base = env->mpmbase;
138 }
139 break;
140 case PRV_S:
141 if (env->mmte & S_PM_ENABLE) {
142 mask = env->spmmask;
143 base = env->spmbase;
144 }
145 break;
146 case PRV_U:
147 if (env->mmte & U_PM_ENABLE) {
148 mask = env->upmmask;
149 base = env->upmbase;
150 }
151 break;
152 default:
153 g_assert_not_reached();
154 }
155 }
156#endif
157 if (env->xl == MXL_RV32) {
158 env->cur_pmmask = mask & UINT32_MAX;
159 env->cur_pmbase = base & UINT32_MAX;
160 } else {
161 env->cur_pmmask = mask;
162 env->cur_pmbase = base;
163 }
164}
165
0c3e702a 166#ifndef CONFIG_USER_ONLY
43dc93af
AP		 167
168/*
169 * The HS-mode is allowed to configure priority only for the
170 * following VS-mode local interrupts:
171 *
172 * 0 (Reserved interrupt, reads as zero)
173 * 1 Supervisor software interrupt
174 * 4 (Reserved interrupt, reads as zero)
175 * 5 Supervisor timer interrupt
176 * 8 (Reserved interrupt, reads as zero)
177 * 13 (Reserved interrupt)
178 * 14 "
179 * 15 "
180 * 16 "
43577499
AP		 181 * 17 "
182 * 18 "
183 * 19 "
184 * 20 "
185 * 21 "
43dc93af 186 * 22 "
43577499 187 * 23 "
43dc93af
AP		 188 */
189
190static const int hviprio_index2irq[] = {
43577499 191 0, 1, 4, 5, 8, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 };
43dc93af
AP		 192static const int hviprio_index2rdzero[] = {
193 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
194
195int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero)
0c3e702a 196{
43dc93af
AP		 197 if (index < 0 || ARRAY_SIZE(hviprio_index2irq) <= index) {
198 return -EINVAL;
199 }
3ef10a09 200
43dc93af
AP		 201 if (out_irq) {
202 *out_irq = hviprio_index2irq[index];
203 }
3ef10a09 204
43dc93af
AP		 205 if (out_rdzero) {
206 *out_rdzero = hviprio_index2rdzero[index];
207 }
cd032fe7 208
43dc93af
AP		 209 return 0;
210}
3ef10a09 211
43dc93af
AP		 212/*
213 * Default priorities of local interrupts are defined in the
214 * RISC-V Advanced Interrupt Architecture specification.
215 *
216 * ----------------------------------------------------------------
217 * Default |
218 * Priority | Major Interrupt Numbers
219 * ----------------------------------------------------------------
43577499
AP		 220 * Highest | 47, 23, 46, 45, 22, 44,
221 * | 43, 21, 42, 41, 20, 40
43dc93af
AP		 222 * |
223 * | 11 (0b), 3 (03), 7 (07)
224 * | 9 (09), 1 (01), 5 (05)
225 * | 12 (0c)
226 * | 10 (0a), 2 (02), 6 (06)
227 * |
43577499
AP		 228 * | 39, 19, 38, 37, 18, 36,
229 * Lowest | 35, 17, 34, 33, 16, 32
43dc93af
AP		 230 * ----------------------------------------------------------------
231 */
232static const uint8_t default_iprio[64] = {
43577499
AP		 233 /* Custom interrupts 48 to 63 */
234 [63] = IPRIO_MMAXIPRIO,
235 [62] = IPRIO_MMAXIPRIO,
236 [61] = IPRIO_MMAXIPRIO,
237 [60] = IPRIO_MMAXIPRIO,
238 [59] = IPRIO_MMAXIPRIO,
239 [58] = IPRIO_MMAXIPRIO,
240 [57] = IPRIO_MMAXIPRIO,
241 [56] = IPRIO_MMAXIPRIO,
242 [55] = IPRIO_MMAXIPRIO,
243 [54] = IPRIO_MMAXIPRIO,
244 [53] = IPRIO_MMAXIPRIO,
245 [52] = IPRIO_MMAXIPRIO,
246 [51] = IPRIO_MMAXIPRIO,
247 [50] = IPRIO_MMAXIPRIO,
248 [49] = IPRIO_MMAXIPRIO,
249 [48] = IPRIO_MMAXIPRIO,
250
251 /* Custom interrupts 24 to 31 */
252 [31] = IPRIO_MMAXIPRIO,
253 [30] = IPRIO_MMAXIPRIO,
254 [29] = IPRIO_MMAXIPRIO,
255 [28] = IPRIO_MMAXIPRIO,
256 [27] = IPRIO_MMAXIPRIO,
257 [26] = IPRIO_MMAXIPRIO,
258 [25] = IPRIO_MMAXIPRIO,
259 [24] = IPRIO_MMAXIPRIO,
260
261 [47] = IPRIO_DEFAULT_UPPER,
262 [23] = IPRIO_DEFAULT_UPPER + 1,
263 [46] = IPRIO_DEFAULT_UPPER + 2,
264 [45] = IPRIO_DEFAULT_UPPER + 3,
265 [22] = IPRIO_DEFAULT_UPPER + 4,
266 [44] = IPRIO_DEFAULT_UPPER + 5,
267
268 [43] = IPRIO_DEFAULT_UPPER + 6,
269 [21] = IPRIO_DEFAULT_UPPER + 7,
270 [42] = IPRIO_DEFAULT_UPPER + 8,
271 [41] = IPRIO_DEFAULT_UPPER + 9,
272 [20] = IPRIO_DEFAULT_UPPER + 10,
273 [40] = IPRIO_DEFAULT_UPPER + 11,
43dc93af
AP		 274
275 [11] = IPRIO_DEFAULT_M,
276 [3] = IPRIO_DEFAULT_M + 1,
277 [7] = IPRIO_DEFAULT_M + 2,
278
279 [9] = IPRIO_DEFAULT_S,
280 [1] = IPRIO_DEFAULT_S + 1,
281 [5] = IPRIO_DEFAULT_S + 2,
282
283 [12] = IPRIO_DEFAULT_SGEXT,
284
285 [10] = IPRIO_DEFAULT_VS,
286 [2] = IPRIO_DEFAULT_VS + 1,
287 [6] = IPRIO_DEFAULT_VS + 2,
288
43577499
AP		 289 [39] = IPRIO_DEFAULT_LOWER,
290 [19] = IPRIO_DEFAULT_LOWER + 1,
291 [38] = IPRIO_DEFAULT_LOWER + 2,
292 [37] = IPRIO_DEFAULT_LOWER + 3,
293 [18] = IPRIO_DEFAULT_LOWER + 4,
294 [36] = IPRIO_DEFAULT_LOWER + 5,
295
296 [35] = IPRIO_DEFAULT_LOWER + 6,
297 [17] = IPRIO_DEFAULT_LOWER + 7,
298 [34] = IPRIO_DEFAULT_LOWER + 8,
299 [33] = IPRIO_DEFAULT_LOWER + 9,
300 [16] = IPRIO_DEFAULT_LOWER + 10,
301 [32] = IPRIO_DEFAULT_LOWER + 11,
43dc93af
AP		 302};
303
304uint8_t riscv_cpu_default_priority(int irq)
305{
306 if (irq < 0 || irq > 63) {
307 return IPRIO_MMAXIPRIO;
308 }
309
310 return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO;
311};
312
313static int riscv_cpu_pending_to_irq(CPURISCVState *env,
314 int extirq, unsigned int extirq_def_prio,
315 uint64_t pending, uint8_t *iprio)
316{
dc9acc9c 317 RISCVCPU *cpu = env_archcpu(env);
43dc93af
AP		 318 int irq, best_irq = RISCV_EXCP_NONE;
319 unsigned int prio, best_prio = UINT_MAX;
320
321 if (!pending) {
322 return RISCV_EXCP_NONE;
323 }
324
325 irq = ctz64(pending);
dc9acc9c 326 if (!((extirq == IRQ_M_EXT) ? cpu->cfg.ext_smaia : cpu->cfg.ext_ssaia)) {
43dc93af
AP		 327 return irq;
328 }
329
330 pending = pending >> irq;
331 while (pending) {
332 prio = iprio[irq];
333 if (!prio) {
334 if (irq == extirq) {
335 prio = extirq_def_prio;
336 } else {
337 prio = (riscv_cpu_default_priority(irq) < extirq_def_prio) ?
338 1 : IPRIO_MMAXIPRIO;
339 }
340 }
341 if ((pending & 0x1) && (prio <= best_prio)) {
342 best_irq = irq;
343 best_prio = prio;
344 }
345 irq++;
346 pending = pending >> 1;
347 }
348
349 return best_irq;
350}
351
8f42415f 352uint64_t riscv_cpu_all_pending(CPURISCVState *env)
43dc93af
AP		 353{
354 uint32_t gein = get_field(env->hstatus, HSTATUS_VGEIN);
355 uint64_t vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
3ec0fe18 356 uint64_t vstip = (env->vstime_irq) ? MIP_VSTIP : 0;
43dc93af 357
3ec0fe18 358 return (env->mip | vsgein | vstip) & env->mie;
43dc93af
AP		 359}
360
361int riscv_cpu_mirq_pending(CPURISCVState *env)
362{
363 uint64_t irqs = riscv_cpu_all_pending(env) & ~env->mideleg &
364 ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
365
366 return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M,
367 irqs, env->miprio);
368}
369
370int riscv_cpu_sirq_pending(CPURISCVState *env)
371{
372 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg &
373 ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
374
375 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
376 irqs, env->siprio);
377}
378
379int riscv_cpu_vsirq_pending(CPURISCVState *env)
380{
381 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg &
382 (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
383
384 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
385 irqs >> 1, env->hviprio);
386}
387
388static int riscv_cpu_local_irq_pending(CPURISCVState *env)
389{
390 int virq;
391 uint64_t irqs, pending, mie, hsie, vsie;
392
393 /* Determine interrupt enable state of all privilege modes */
394 if (riscv_cpu_virt_enabled(env)) {
395 mie = 1;
396 hsie = 1;
397 vsie = (env->priv < PRV_S) ||
398 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE));
0c3e702a 399 } else {
43dc93af
AP		 400 mie = (env->priv < PRV_M) ||
401 (env->priv == PRV_M && get_field(env->mstatus, MSTATUS_MIE));
402 hsie = (env->priv < PRV_S) ||
403 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE));
404 vsie = 0;
405 }
406
407 /* Determine all pending interrupts */
408 pending = riscv_cpu_all_pending(env);
409
410 /* Check M-mode interrupts */
411 irqs = pending & ~env->mideleg & -mie;
412 if (irqs) {
413 return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M,
414 irqs, env->miprio);
415 }
416
417 /* Check HS-mode interrupts */
418 irqs = pending & env->mideleg & ~env->hideleg & -hsie;
419 if (irqs) {
420 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
421 irqs, env->siprio);
0c3e702a 422 }
43dc93af
AP		 423
424 /* Check VS-mode interrupts */
425 irqs = pending & env->mideleg & env->hideleg & -vsie;
426 if (irqs) {
427 virq = riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
428 irqs >> 1, env->hviprio);
429 return (virq <= 0) ? virq : virq + 1;
430 }
431
432 /* Indicate no pending interrupt */
433 return RISCV_EXCP_NONE;
0c3e702a 434}
0c3e702a
MC		 435
436bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
437{
0c3e702a
MC		 438 if (interrupt_request & CPU_INTERRUPT_HARD) {
439 RISCVCPU *cpu = RISCV_CPU(cs);
440 CPURISCVState *env = &cpu->env;
efbdbc26 441 int interruptno = riscv_cpu_local_irq_pending(env);
0c3e702a
MC		 442 if (interruptno >= 0) {
443 cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno;
444 riscv_cpu_do_interrupt(cs);
445 return true;
446 }
447 }
0c3e702a
MC		 448 return false;
449}
450
b345b480
AF		 451/* Return true is floating point support is currently enabled */
452bool riscv_cpu_fp_enabled(CPURISCVState *env)
453{
454 if (env->mstatus & MSTATUS_FS) {
29409c1d
AF		 455 if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_FS)) {
456 return false;
457 }
b345b480
AF		 458 return true;
459 }
460
461 return false;
462}
463
61b4b69d
LZ		 464/* Return true is vector support is currently enabled */
465bool riscv_cpu_vector_enabled(CPURISCVState *env)
466{
467 if (env->mstatus & MSTATUS_VS) {
468 if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_VS)) {
469 return false;
470 }
471 return true;
472 }
473
474 return false;
475}
476
66e594f2
AF		 477void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
478{
c163b3ba 479 uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM |
284d697c 480 MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE |
61b4b69d 481 MSTATUS64_UXL | MSTATUS_VS;
c163b3ba
WL		 482
483 if (riscv_has_ext(env, RVF)) {
484 mstatus_mask |= MSTATUS_FS;
485 }
66e594f2
AF		 486 bool current_virt = riscv_cpu_virt_enabled(env);
487
488 g_assert(riscv_has_ext(env, RVH));
489
66e594f2
AF		 490 if (current_virt) {
491 /* Current V=1 and we are about to change to V=0 */
492 env->vsstatus = env->mstatus & mstatus_mask;
493 env->mstatus &= ~mstatus_mask;
494 env->mstatus |= env->mstatus_hs;
495
496 env->vstvec = env->stvec;
497 env->stvec = env->stvec_hs;
498
499 env->vsscratch = env->sscratch;
500 env->sscratch = env->sscratch_hs;
501
502 env->vsepc = env->sepc;
503 env->sepc = env->sepc_hs;
504
505 env->vscause = env->scause;
506 env->scause = env->scause_hs;
507
ac12b601
AP		 508 env->vstval = env->stval;
509 env->stval = env->stval_hs;
66e594f2
AF		 510
511 env->vsatp = env->satp;
512 env->satp = env->satp_hs;
513 } else {
514 /* Current V=0 and we are about to change to V=1 */
515 env->mstatus_hs = env->mstatus & mstatus_mask;
516 env->mstatus &= ~mstatus_mask;
517 env->mstatus |= env->vsstatus;
518
519 env->stvec_hs = env->stvec;
520 env->stvec = env->vstvec;
521
522 env->sscratch_hs = env->sscratch;
523 env->sscratch = env->vsscratch;
524
525 env->sepc_hs = env->sepc;
526 env->sepc = env->vsepc;
527
528 env->scause_hs = env->scause;
529 env->scause = env->vscause;
530
ac12b601
AP		 531 env->stval_hs = env->stval;
532 env->stval = env->vstval;
66e594f2
AF		 533
534 env->satp_hs = env->satp;
535 env->satp = env->vsatp;
536 }
537}
538
cd032fe7
AP		 539target_ulong riscv_cpu_get_geilen(CPURISCVState *env)
540{
541 if (!riscv_has_ext(env, RVH)) {
542 return 0;
543 }
544
545 return env->geilen;
546}
547
548void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen)
549{
550 if (!riscv_has_ext(env, RVH)) {
551 return;
552 }
553
554 if (geilen > (TARGET_LONG_BITS - 1)) {
555 return;
556 }
557
558 env->geilen = geilen;
559}
560
ef6bb7b6
AF		 561bool riscv_cpu_virt_enabled(CPURISCVState *env)
562{
563 if (!riscv_has_ext(env, RVH)) {
564 return false;
565 }
566
567 return get_field(env->virt, VIRT_ONOFF);
568}
569
570void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
571{
572 if (!riscv_has_ext(env, RVH)) {
573 return;
574 }
575
eccc5a12
AF		 576 /* Flush the TLB on all virt mode changes. */
577 if (get_field(env->virt, VIRT_ONOFF) != enable) {
578 tlb_flush(env_cpu(env));
579 }
580
ef6bb7b6 581 env->virt = set_field(env->virt, VIRT_ONOFF, enable);
02d9565b
AP		 582
583 if (enable) {
584 /*
585 * The guest external interrupts from an interrupt controller are
586 * delivered only when the Guest/VM is running (i.e. V=1). This means
587 * any guest external interrupt which is triggered while the Guest/VM
588 * is not running (i.e. V=0) will be missed on QEMU resulting in guest
589 * with sluggish response to serial console input and other I/O events.
590 *
591 * To solve this, we check and inject interrupt after setting V=1.
592 */
593 riscv_cpu_update_mip(env_archcpu(env), 0, 0);
594 }
ef6bb7b6
AF		 595}
596
1c1c060a 597bool riscv_cpu_two_stage_lookup(int mmu_idx)
5a894dd7 598{
1c1c060a 599 return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK;
5a894dd7
AF		 600}
601
d028ac75 602int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts)
e3e7039c
MC		 603{
604 CPURISCVState *env = &cpu->env;
605 if (env->miclaim & interrupts) {
606 return -1;
607 } else {
608 env->miclaim |= interrupts;
609 return 0;
610 }
611}
612
d028ac75 613uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value)
df354dd4
MC		 614{
615 CPURISCVState *env = &cpu->env;
0a01f2ee 616 CPUState *cs = CPU(cpu);
3ec0fe18 617 uint64_t gein, vsgein = 0, vstip = 0, old = env->mip;
7ec5d303
AF		 618 bool locked = false;
619
cd032fe7
AP		 620 if (riscv_cpu_virt_enabled(env)) {
621 gein = get_field(env->hstatus, HSTATUS_VGEIN);
622 vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
623 }
624
3ec0fe18
AP		 625 /* No need to update mip for VSTIP */
626 mask = ((mask == MIP_VSTIP) && env->vstime_irq) ? 0 : mask;
627 vstip = env->vstime_irq ? MIP_VSTIP : 0;
628
7ec5d303
AF		 629 if (!qemu_mutex_iothread_locked()) {
630 locked = true;
631 qemu_mutex_lock_iothread();
632 }
df354dd4 633
7ec5d303 634 env->mip = (env->mip & ~mask) | (value & mask);
df354dd4 635
3ec0fe18 636 if (env->mip | vsgein | vstip) {
7ec5d303
AF		 637 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
638 } else {
639 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
640 }
0a01f2ee 641
7ec5d303
AF		 642 if (locked) {
643 qemu_mutex_unlock_iothread();
644 }
df354dd4
MC		 645
646 return old;
647}
648
e2f01f3c
FC		 649void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *),
650 void *arg)
c6957248
AP		 651{
652 env->rdtime_fn = fn;
a47ef6e9 653 env->rdtime_fn_arg = arg;
c6957248
AP		 654}
655
69077dd6
AP		 656void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
657 int (*rmw_fn)(void *arg,
658 target_ulong reg,
659 target_ulong *val,
660 target_ulong new_val,
661 target_ulong write_mask),
662 void *rmw_fn_arg)
663{
664 if (priv <= PRV_M) {
665 env->aia_ireg_rmw_fn[priv] = rmw_fn;
666 env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg;
667 }
668}
669
fb738839 670void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
df354dd4
MC		 671{
672 if (newpriv > PRV_M) {
673 g_assert_not_reached();
674 }
675 if (newpriv == PRV_H) {
676 newpriv = PRV_U;
677 }
5a4ae64c
LZ		 678 if (icount_enabled() && newpriv != env->priv) {
679 riscv_itrigger_update_priv(env);
680 }
df354dd4
MC		 681 /* tlb_flush is unnecessary as mode is contained in mmu_idx */
682 env->priv = newpriv;
440544e1 683 env->xl = cpu_recompute_xl(env);
40bfa5f6 684 riscv_cpu_update_mask(env);
c13b169f
JS		 685
686 /*
687 * Clear the load reservation - otherwise a reservation placed in one
688 * context/process can be used by another, resulting in an SC succeeding
689 * incorrectly. Version 2.2 of the ISA specification explicitly requires
690 * this behaviour, while later revisions say that the kernel "should" use
691 * an SC instruction to force the yielding of a load reservation on a
692 * preemptive context switch. As a result, do both.
693 */
694 env->load_res = -1;
df354dd4
MC		 695}
696
b297129a
JS		 697/*
698 * get_physical_address_pmp - check PMP permission for this physical address
699 *
700 * Match the PMP region and check permission for this physical address and it's
701 * TLB page. Returns 0 if the permission checking was successful
702 *
703 * @env: CPURISCVState
704 * @prot: The returned protection attributes
705 * @tlb_size: TLB page size containing addr. It could be modified after PMP
706 * permission checking. NULL if not set TLB page for addr.
707 * @addr: The physical address to be checked permission
708 * @access_type: The type of MMU access
709 * @mode: Indicates current privilege level.
710 */
711static int get_physical_address_pmp(CPURISCVState *env, int *prot,
712 target_ulong *tlb_size, hwaddr addr,
713 int size, MMUAccessType access_type,
714 int mode)
715{
716 pmp_priv_t pmp_priv;
824cac68 717 int pmp_index = -1;
b297129a
JS		 718
719 if (!riscv_feature(env, RISCV_FEATURE_PMP)) {
720 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
721 return TRANSLATE_SUCCESS;
722 }
723
824cac68
LZ		 724 pmp_index = pmp_hart_has_privs(env, addr, size, 1 << access_type,
725 &pmp_priv, mode);
726 if (pmp_index < 0) {
b297129a
JS		 727 *prot = 0;
728 return TRANSLATE_PMP_FAIL;
729 }
730
731 *prot = pmp_priv_to_page_prot(pmp_priv);
824cac68
LZ		 732 if ((tlb_size != NULL) && pmp_index != MAX_RISCV_PMPS) {
733 target_ulong tlb_sa = addr & ~(TARGET_PAGE_SIZE - 1);
734 target_ulong tlb_ea = tlb_sa + TARGET_PAGE_SIZE - 1;
735
736 *tlb_size = pmp_get_tlb_size(env, pmp_index, tlb_sa, tlb_ea);
b297129a
JS		 737 }
738
739 return TRANSLATE_SUCCESS;
740}
741
0c3e702a
MC		 742/* get_physical_address - get the physical address for this virtual address
743 *
744 * Do a page table walk to obtain the physical address corresponding to a
745 * virtual address. Returns 0 if the translation was successful
746 *
747 * Adapted from Spike's mmu_t::translate and mmu_t::walk
748 *
1448689c
AF		 749 * @env: CPURISCVState
750 * @physical: This will be set to the calculated physical address
751 * @prot: The returned protection attributes
752 * @addr: The virtual address to be translated
33a9a57d
YJ		 753 * @fault_pte_addr: If not NULL, this will be set to fault pte address
754 * when a error occurs on pte address translation.
755 * This will already be shifted to match htval.
1448689c
AF		 756 * @access_type: The type of MMU access
757 * @mmu_idx: Indicates current privilege level
758 * @first_stage: Are we in first stage translation?
759 * Second stage is used for hypervisor guest translation
36a18664 760 * @two_stage: Are we going to perform two stage translation
11c27c6d 761 * @is_debug: Is this access from a debugger or the monitor?
0c3e702a
MC		 762 */
763static int get_physical_address(CPURISCVState *env, hwaddr *physical,
764 int *prot, target_ulong addr,
33a9a57d 765 target_ulong *fault_pte_addr,
1448689c 766 int access_type, int mmu_idx,
11c27c6d
JF		 767 bool first_stage, bool two_stage,
768 bool is_debug)
0c3e702a
MC		 769{
770 /* NOTE: the env->pc value visible here will not be
771 * correct, but the value visible to the exception handler
772 * (riscv_cpu_do_interrupt) is correct */
aacb578f
PD		 773 MemTxResult res;
774 MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
c445593d 775 int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK;
36a18664 776 bool use_background = false;
05e6ca5e
GR		 777 hwaddr ppn;
778 RISCVCPU *cpu = env_archcpu(env);
2bacb224
WL		 779 int napot_bits = 0;
780 target_ulong napot_mask;
0c3e702a 781
36a18664
AF		 782 /*
783 * Check if we should use the background registers for the two
784 * stage translation. We don't need to check if we actually need
785 * two stage translation as that happened before this function
786 * was called. Background registers will be used if the guest has
787 * forced a two stage translation to be on (in HS or M mode).
788 */
db9ab38b 789 if (!riscv_cpu_virt_enabled(env) && two_stage) {
29b3361b
AF		 790 use_background = true;
791 }
792
90ec1cff
GK		 793 /* MPRV does not affect the virtual-machine load/store
794 instructions, HLV, HLVX, and HSV. */
795 if (riscv_cpu_two_stage_lookup(mmu_idx)) {
796 mode = get_field(env->hstatus, HSTATUS_SPVP);
797 } else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
0c3e702a
MC		 798 if (get_field(env->mstatus, MSTATUS_MPRV)) {
799 mode = get_field(env->mstatus, MSTATUS_MPP);
800 }
801 }
802
36a18664
AF		 803 if (first_stage == false) {
804 /* We are in stage 2 translation, this is similar to stage 1. */
805 /* Stage 2 is always taken as U-mode */
806 mode = PRV_U;
807 }
808
0c3e702a
MC		 809 if (mode == PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) {
810 *physical = addr;
811 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
812 return TRANSLATE_SUCCESS;
813 }
814
815 *prot = 0;
816
ddf78132 817 hwaddr base;
36a18664
AF		 818 int levels, ptidxbits, ptesize, vm, sum, mxr, widened;
819
820 if (first_stage == true) {
821 mxr = get_field(env->mstatus, MSTATUS_MXR);
822 } else {
823 mxr = get_field(env->vsstatus, MSTATUS_MXR);
824 }
0c3e702a 825
1a9540d1
AF		 826 if (first_stage == true) {
827 if (use_background) {
db23e5d9 828 if (riscv_cpu_mxl(env) == MXL_RV32) {
419ddf00
AF		 829 base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT;
830 vm = get_field(env->vsatp, SATP32_MODE);
831 } else {
832 base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT;
833 vm = get_field(env->vsatp, SATP64_MODE);
834 }
36a18664 835 } else {
db23e5d9 836 if (riscv_cpu_mxl(env) == MXL_RV32) {
419ddf00
AF		 837 base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
838 vm = get_field(env->satp, SATP32_MODE);
839 } else {
840 base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT;
841 vm = get_field(env->satp, SATP64_MODE);
842 }
0c3e702a 843 }
36a18664 844 widened = 0;
1a9540d1 845 } else {
db23e5d9 846 if (riscv_cpu_mxl(env) == MXL_RV32) {
994b6bb2
AF		 847 base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT;
848 vm = get_field(env->hgatp, SATP32_MODE);
849 } else {
850 base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT;
851 vm = get_field(env->hgatp, SATP64_MODE);
852 }
1a9540d1
AF		 853 widened = 2;
854 }
c63ca4ff 855 /* status.SUM will be ignored if execute on background */
11c27c6d 856 sum = get_field(env->mstatus, MSTATUS_SUM) || use_background || is_debug;
1a9540d1
AF		 857 switch (vm) {
858 case VM_1_10_SV32:
859 levels = 2; ptidxbits = 10; ptesize = 4; break;
860 case VM_1_10_SV39:
861 levels = 3; ptidxbits = 9; ptesize = 8; break;
862 case VM_1_10_SV48:
863 levels = 4; ptidxbits = 9; ptesize = 8; break;
864 case VM_1_10_SV57:
865 levels = 5; ptidxbits = 9; ptesize = 8; break;
866 case VM_1_10_MBARE:
867 *physical = addr;
868 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
869 return TRANSLATE_SUCCESS;
870 default:
871 g_assert_not_reached();
0c3e702a
MC		 872 }
873
3109cd98 874 CPUState *cs = env_cpu(env);
36a18664
AF		 875 int va_bits = PGSHIFT + levels * ptidxbits + widened;
876 target_ulong mask, masked_msbs;
877
878 if (TARGET_LONG_BITS > (va_bits - 1)) {
879 mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1;
880 } else {
881 mask = 0;
882 }
883 masked_msbs = (addr >> (va_bits - 1)) & mask;
884
0c3e702a
MC		 885 if (masked_msbs != 0 && masked_msbs != mask) {
886 return TRANSLATE_FAIL;
887 }
888
889 int ptshift = (levels - 1) * ptidxbits;
890 int i;
891
892#if !TCG_OVERSIZED_GUEST
893restart:
894#endif
895 for (i = 0; i < levels; i++, ptshift -= ptidxbits) {
36a18664
AF		 896 target_ulong idx;
897 if (i == 0) {
898 idx = (addr >> (PGSHIFT + ptshift)) &
899 ((1 << (ptidxbits + widened)) - 1);
900 } else {
901 idx = (addr >> (PGSHIFT + ptshift)) &
0c3e702a 902 ((1 << ptidxbits) - 1);
36a18664 903 }
0c3e702a
MC		 904
905 /* check that physical address of PTE is legal */
36a18664
AF		 906 hwaddr pte_addr;
907
908 if (two_stage && first_stage) {
38472890 909 int vbase_prot;
36a18664
AF		 910 hwaddr vbase;
911
912 /* Do the second stage translation on the base PTE address. */
88914473 913 int vbase_ret = get_physical_address(env, &vbase, &vbase_prot,
33a9a57d 914 base, NULL, MMU_DATA_LOAD,
11c27c6d
JF		 915 mmu_idx, false, true,
916 is_debug);
88914473
AF		 917
918 if (vbase_ret != TRANSLATE_SUCCESS) {
33a9a57d
YJ		 919 if (fault_pte_addr) {
920 *fault_pte_addr = (base + idx * ptesize) >> 2;
921 }
922 return TRANSLATE_G_STAGE_FAIL;
88914473 923 }
36a18664
AF		 924
925 pte_addr = vbase + idx * ptesize;
926 } else {
927 pte_addr = base + idx * ptesize;
928 }
1f447aec 929
b297129a
JS		 930 int pmp_prot;
931 int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr,
932 sizeof(target_ulong),
933 MMU_DATA_LOAD, PRV_S);
934 if (pmp_ret != TRANSLATE_SUCCESS) {
1f447aec
HA		 935 return TRANSLATE_PMP_FAIL;
936 }
aacb578f 937
f08c7ff3 938 target_ulong pte;
db23e5d9 939 if (riscv_cpu_mxl(env) == MXL_RV32) {
f08c7ff3
AF		 940 pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
941 } else {
942 pte = address_space_ldq(cs->as, pte_addr, attrs, &res);
943 }
944
aacb578f
PD		 945 if (res != MEMTX_OK) {
946 return TRANSLATE_FAIL;
947 }
948
05e6ca5e
GR		 949 if (riscv_cpu_sxl(env) == MXL_RV32) {
950 ppn = pte >> PTE_PPN_SHIFT;
951 } else if (cpu->cfg.ext_svpbmt || cpu->cfg.ext_svnapot) {
952 ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT;
953 } else {
954 ppn = pte >> PTE_PPN_SHIFT;
955 if ((pte & ~(target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT) {
956 return TRANSLATE_FAIL;
957 }
958 }
0c3e702a 959
c3b03e58
MC		 960 if (!(pte & PTE_V)) {
961 /* Invalid PTE */
962 return TRANSLATE_FAIL;
bbce8ba8
WL		 963 } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT)) {
964 return TRANSLATE_FAIL;
c3b03e58
MC		 965 } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
966 /* Inner PTE, continue walking */
bbce8ba8 967 if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) {
b6ecc63c
WL		 968 return TRANSLATE_FAIL;
969 }
0c3e702a 970 base = ppn << PGSHIFT;
c3b03e58
MC		 971 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
972 /* Reserved leaf PTE flags: PTE_W */
973 return TRANSLATE_FAIL;
974 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) {
975 /* Reserved leaf PTE flags: PTE_W + PTE_X */
976 return TRANSLATE_FAIL;
977 } else if ((pte & PTE_U) && ((mode != PRV_U) &&
978 (!sum || access_type == MMU_INST_FETCH))) {
979 /* User PTE flags when not U mode and mstatus.SUM is not set,
980 or the access type is an instruction fetch */
981 return TRANSLATE_FAIL;
982 } else if (!(pte & PTE_U) && (mode != PRV_S)) {
983 /* Supervisor PTE flags when not S mode */
984 return TRANSLATE_FAIL;
985 } else if (ppn & ((1ULL << ptshift) - 1)) {
986 /* Misaligned PPN */
987 return TRANSLATE_FAIL;
988 } else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) ||
989 ((pte & PTE_X) && mxr))) {
990 /* Read access check failed */
991 return TRANSLATE_FAIL;
992 } else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) {
993 /* Write access check failed */
994 return TRANSLATE_FAIL;
995 } else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) {
996 /* Fetch access check failed */
997 return TRANSLATE_FAIL;
0c3e702a
MC		 998 } else {
999 /* if necessary, set accessed and dirty bits. */
1000 target_ulong updated_pte = pte | PTE_A |
1001 (access_type == MMU_DATA_STORE ? PTE_D : 0);
1002
1003 /* Page table updates need to be atomic with MTTCG enabled */
1004 if (updated_pte != pte) {
c3b03e58
MC		 1005 /*
1006 * - if accessed or dirty bits need updating, and the PTE is
1007 * in RAM, then we do so atomically with a compare and swap.
1008 * - if the PTE is in IO space or ROM, then it can't be updated
1009 * and we return TRANSLATE_FAIL.
1010 * - if the PTE changed by the time we went to update it, then
1011 * it is no longer valid and we must re-walk the page table.
1012 */
0c3e702a
MC		 1013 MemoryRegion *mr;
1014 hwaddr l = sizeof(target_ulong), addr1;
1015 mr = address_space_translate(cs->as, pte_addr,
bc6b1cec 1016 &addr1, &l, false, MEMTXATTRS_UNSPECIFIED);
c3b03e58 1017 if (memory_region_is_ram(mr)) {
0c3e702a
MC		 1018 target_ulong *pte_pa =
1019 qemu_map_ram_ptr(mr->ram_block, addr1);
1020#if TCG_OVERSIZED_GUEST
1021 /* MTTCG is not enabled on oversized TCG guests so
1022 * page table updates do not need to be atomic */
1023 *pte_pa = pte = updated_pte;
1024#else
1025 target_ulong old_pte =
d73415a3 1026 qatomic_cmpxchg(pte_pa, pte, updated_pte);
0c3e702a
MC		 1027 if (old_pte != pte) {
1028 goto restart;
1029 } else {
1030 pte = updated_pte;
1031 }
1032#endif
1033 } else {
1034 /* misconfigured PTE in ROM (AD bits are not preset) or
1035 * PTE is in IO space and can't be updated atomically */
1036 return TRANSLATE_FAIL;
1037 }
1038 }
1039
1040 /* for superpage mappings, make a fake leaf PTE for the TLB's
1041 benefit. */
1042 target_ulong vpn = addr >> PGSHIFT;
2bacb224
WL		 1043
1044 if (cpu->cfg.ext_svnapot && (pte & PTE_N)) {
1045 napot_bits = ctzl(ppn) + 1;
1046 if ((i != (levels - 1)) || (napot_bits != 4)) {
1047 return TRANSLATE_FAIL;
1048 }
1049 }
1050
1051 napot_mask = (1 << napot_bits) - 1;
1052 *physical = (((ppn & ~napot_mask) | (vpn & napot_mask) |
1053 (vpn & (((target_ulong)1 << ptshift) - 1))
1054 ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK);
0c3e702a 1055
c3b03e58
MC		 1056 /* set permissions on the TLB entry */
1057 if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
0c3e702a
MC		 1058 *prot |= PAGE_READ;
1059 }
1060 if ((pte & PTE_X)) {
1061 *prot |= PAGE_EXEC;
1062 }
c3b03e58
MC		 1063 /* add write permission on stores or if the page is already dirty,
1064 so that we TLB miss on later writes to update the dirty bit */
0c3e702a
MC		 1065 if ((pte & PTE_W) &&
1066 (access_type == MMU_DATA_STORE || (pte & PTE_D))) {
1067 *prot |= PAGE_WRITE;
1068 }
1069 return TRANSLATE_SUCCESS;
1070 }
1071 }
1072 return TRANSLATE_FAIL;
1073}
1074
1075static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
1448689c 1076 MMUAccessType access_type, bool pmp_violation,
8e2aa21b
AP		 1077 bool first_stage, bool two_stage,
1078 bool two_stage_indirect)
0c3e702a 1079{
3109cd98 1080 CPUState *cs = env_cpu(env);
994b6bb2 1081 int page_fault_exceptions, vm;
419ddf00
AF		 1082 uint64_t stap_mode;
1083
db23e5d9 1084 if (riscv_cpu_mxl(env) == MXL_RV32) {
419ddf00
AF		 1085 stap_mode = SATP32_MODE;
1086 } else {
1087 stap_mode = SATP64_MODE;
1088 }
994b6bb2 1089
1448689c 1090 if (first_stage) {
419ddf00 1091 vm = get_field(env->satp, stap_mode);
1448689c 1092 } else {
419ddf00 1093 vm = get_field(env->hgatp, stap_mode);
1448689c 1094 }
419ddf00 1095
994b6bb2
AF		 1096 page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation;
1097
0c3e702a
MC		 1098 switch (access_type) {
1099 case MMU_INST_FETCH:
b2ef6ab9
AF		 1100 if (riscv_cpu_virt_enabled(env) && !first_stage) {
1101 cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
1102 } else {
1103 cs->exception_index = page_fault_exceptions ?
1104 RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT;
1105 }
0c3e702a
MC		 1106 break;
1107 case MMU_DATA_LOAD:
1c1c060a 1108 if (two_stage && !first_stage) {
b2ef6ab9
AF		 1109 cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
1110 } else {
1111 cs->exception_index = page_fault_exceptions ?
1112 RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT;
1113 }
0c3e702a
MC		 1114 break;
1115 case MMU_DATA_STORE:
1c1c060a 1116 if (two_stage && !first_stage) {
b2ef6ab9
AF		 1117 cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
1118 } else {
1119 cs->exception_index = page_fault_exceptions ?
1120 RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
1121 }
0c3e702a
MC		 1122 break;
1123 default:
1124 g_assert_not_reached();
1125 }
1126 env->badaddr = address;
ec352d0c 1127 env->two_stage_lookup = two_stage;
8e2aa21b 1128 env->two_stage_indirect_lookup = two_stage_indirect;
0c3e702a
MC		 1129}
1130
1131hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
1132{
1133 RISCVCPU *cpu = RISCV_CPU(cs);
36a18664 1134 CPURISCVState *env = &cpu->env;
0c3e702a
MC		 1135 hwaddr phys_addr;
1136 int prot;
1137 int mmu_idx = cpu_mmu_index(&cpu->env, false);
1138
33a9a57d 1139 if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx,
11c27c6d 1140 true, riscv_cpu_virt_enabled(env), true)) {
0c3e702a
MC		 1141 return -1;
1142 }
36a18664
AF		 1143
1144 if (riscv_cpu_virt_enabled(env)) {
33a9a57d 1145 if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL,
11c27c6d 1146 0, mmu_idx, false, true, true)) {
36a18664
AF		 1147 return -1;
1148 }
1149 }
1150
9ef82119 1151 return phys_addr & TARGET_PAGE_MASK;
0c3e702a
MC		 1152}
1153
37207e12
PD		 1154void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
1155 vaddr addr, unsigned size,
1156 MMUAccessType access_type,
1157 int mmu_idx, MemTxAttrs attrs,
1158 MemTxResult response, uintptr_t retaddr)
cbf58276
MC		 1159{
1160 RISCVCPU *cpu = RISCV_CPU(cs);
1161 CPURISCVState *env = &cpu->env;
1162
37207e12 1163 if (access_type == MMU_DATA_STORE) {
cbf58276 1164 cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
f9e580c1 1165 } else if (access_type == MMU_DATA_LOAD) {
cbf58276 1166 cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
f9e580c1
EB		 1167 } else {
1168 cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
cbf58276
MC		 1169 }
1170
1171 env->badaddr = addr;
ec352d0c
GK		 1172 env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
1173 riscv_cpu_two_stage_lookup(mmu_idx);
8e2aa21b 1174 env->two_stage_indirect_lookup = false;
ac684717 1175 cpu_loop_exit_restore(cs, retaddr);
cbf58276
MC		 1176}
1177
0c3e702a
MC		 1178void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
1179 MMUAccessType access_type, int mmu_idx,
1180 uintptr_t retaddr)
1181{
1182 RISCVCPU *cpu = RISCV_CPU(cs);
1183 CPURISCVState *env = &cpu->env;
1184 switch (access_type) {
1185 case MMU_INST_FETCH:
1186 cs->exception_index = RISCV_EXCP_INST_ADDR_MIS;
1187 break;
1188 case MMU_DATA_LOAD:
1189 cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS;
1190 break;
1191 case MMU_DATA_STORE:
1192 cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS;
1193 break;
1194 default:
1195 g_assert_not_reached();
1196 }
1197 env->badaddr = addr;
ec352d0c
GK		 1198 env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
1199 riscv_cpu_two_stage_lookup(mmu_idx);
8e2aa21b 1200 env->two_stage_indirect_lookup = false;
ac684717 1201 cpu_loop_exit_restore(cs, retaddr);
0c3e702a 1202}
0c3e702a 1203
892320fa
AP		 1204
1205static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type)
1206{
1207 enum riscv_pmu_event_idx pmu_event_type;
1208
1209 switch (access_type) {
1210 case MMU_INST_FETCH:
1211 pmu_event_type = RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS;
1212 break;
1213 case MMU_DATA_LOAD:
1214 pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS;
1215 break;
1216 case MMU_DATA_STORE:
1217 pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS;
1218 break;
1219 default:
1220 return;
1221 }
1222
1223 riscv_pmu_incr_ctr(cpu, pmu_event_type);
1224}
1225
8a4ca3c1
RH		 1226bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
1227 MMUAccessType access_type, int mmu_idx,
1228 bool probe, uintptr_t retaddr)
0c3e702a
MC		 1229{
1230 RISCVCPU *cpu = RISCV_CPU(cs);
1231 CPURISCVState *env = &cpu->env;
36a18664 1232 vaddr im_address;
0c3e702a 1233 hwaddr pa = 0;
b297129a 1234 int prot, prot2, prot_pmp;
635b0b0e 1235 bool pmp_violation = false;
36a18664 1236 bool first_stage_error = true;
1c1c060a 1237 bool two_stage_lookup = false;
8e2aa21b 1238 bool two_stage_indirect_error = false;
0c3e702a 1239 int ret = TRANSLATE_FAIL;
cc0fdb29 1240 int mode = mmu_idx;
b297129a
JS		 1241 /* default TLB page size */
1242 target_ulong tlb_size = TARGET_PAGE_SIZE;
0c3e702a 1243
36a18664
AF		 1244 env->guest_phys_fault_addr = 0;
1245
8a4ca3c1
RH		 1246 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
1247 __func__, address, access_type, mmu_idx);
1248
90ec1cff
GK		 1249 /* MPRV does not affect the virtual-machine load/store
1250 instructions, HLV, HLVX, and HSV. */
1251 if (riscv_cpu_two_stage_lookup(mmu_idx)) {
1252 mode = get_field(env->hstatus, HSTATUS_SPVP);
1253 } else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
1254 get_field(env->mstatus, MSTATUS_MPRV)) {
1255 mode = get_field(env->mstatus, MSTATUS_MPP);
1256 if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) {
1257 two_stage_lookup = true;
cc0fdb29
HA		 1258 }
1259 }
1260
29b3361b 1261 if (riscv_cpu_virt_enabled(env) ||
1c1c060a
AF		 1262 ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
1263 access_type != MMU_INST_FETCH)) {
36a18664 1264 /* Two stage lookup */
33a9a57d
YJ		 1265 ret = get_physical_address(env, &pa, &prot, address,
1266 &env->guest_phys_fault_addr, access_type,
11c27c6d 1267 mmu_idx, true, true, false);
36a18664 1268
33a9a57d
YJ		 1269 /*
1270 * A G-stage exception may be triggered during two state lookup.
1271 * And the env->guest_phys_fault_addr has already been set in
1272 * get_physical_address().
1273 */
1274 if (ret == TRANSLATE_G_STAGE_FAIL) {
1275 first_stage_error = false;
8e2aa21b 1276 two_stage_indirect_error = true;
33a9a57d
YJ		 1277 access_type = MMU_DATA_LOAD;
1278 }
1279
36a18664
AF		 1280 qemu_log_mask(CPU_LOG_MMU,
1281 "%s 1st-stage address=%" VADDR_PRIx " ret %d physical "
1282 TARGET_FMT_plx " prot %d\n",
1283 __func__, address, ret, pa, prot);
1284
33a9a57d 1285 if (ret == TRANSLATE_SUCCESS) {
36a18664
AF		 1286 /* Second stage lookup */
1287 im_address = pa;
1288
33a9a57d 1289 ret = get_physical_address(env, &pa, &prot2, im_address, NULL,
11c27c6d
JF		 1290 access_type, mmu_idx, false, true,
1291 false);
36a18664
AF		 1292
1293 qemu_log_mask(CPU_LOG_MMU,
1294 "%s 2nd-stage address=%" VADDR_PRIx " ret %d physical "
1295 TARGET_FMT_plx " prot %d\n",
8f67cd6d
AF		 1296 __func__, im_address, ret, pa, prot2);
1297
1298 prot &= prot2;
36a18664 1299
b297129a
JS		 1300 if (ret == TRANSLATE_SUCCESS) {
1301 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
1302 size, access_type, mode);
663e1193
JS		 1303
1304 qemu_log_mask(CPU_LOG_MMU,
1305 "%s PMP address=" TARGET_FMT_plx " ret %d prot"
1306 " %d tlb_size " TARGET_FMT_lu "\n",
1307 __func__, pa, ret, prot_pmp, tlb_size);
1308
b297129a 1309 prot &= prot_pmp;
36a18664
AF		 1310 }
1311
1312 if (ret != TRANSLATE_SUCCESS) {
1313 /*
1314 * Guest physical address translation failed, this is a HS
1315 * level exception
1316 */
1317 first_stage_error = false;
1318 env->guest_phys_fault_addr = (im_address |
1319 (address &
1320 (TARGET_PAGE_SIZE - 1))) >> 2;
1321 }
1322 }
1323 } else {
892320fa 1324 pmu_tlb_fill_incr_ctr(cpu, access_type);
36a18664 1325 /* Single stage lookup */
33a9a57d 1326 ret = get_physical_address(env, &pa, &prot, address, NULL,
11c27c6d 1327 access_type, mmu_idx, true, false, false);
36a18664
AF		 1328
1329 qemu_log_mask(CPU_LOG_MMU,
1330 "%s address=%" VADDR_PRIx " ret %d physical "
1331 TARGET_FMT_plx " prot %d\n",
1332 __func__, address, ret, pa, prot);
8a4ca3c1 1333
b297129a
JS		 1334 if (ret == TRANSLATE_SUCCESS) {
1335 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
1336 size, access_type, mode);
663e1193
JS		 1337
1338 qemu_log_mask(CPU_LOG_MMU,
1339 "%s PMP address=" TARGET_FMT_plx " ret %d prot"
1340 " %d tlb_size " TARGET_FMT_lu "\n",
1341 __func__, pa, ret, prot_pmp, tlb_size);
1342
b297129a
JS		 1343 prot &= prot_pmp;
1344 }
1f447aec 1345 }
b297129a 1346
1f447aec 1347 if (ret == TRANSLATE_PMP_FAIL) {
635b0b0e 1348 pmp_violation = true;
0c3e702a 1349 }
36a18664 1350
0c3e702a 1351 if (ret == TRANSLATE_SUCCESS) {
b297129a
JS		 1352 tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
1353 prot, mmu_idx, tlb_size);
8a4ca3c1
RH		 1354 return true;
1355 } else if (probe) {
1356 return false;
1357 } else {
1c1c060a
AF		 1358 raise_mmu_exception(env, address, access_type, pmp_violation,
1359 first_stage_error,
1360 riscv_cpu_virt_enabled(env) ||
8e2aa21b
AP		 1361 riscv_cpu_two_stage_lookup(mmu_idx),
1362 two_stage_indirect_error);
ac684717 1363 cpu_loop_exit_restore(cs, retaddr);
0c3e702a 1364 }
36a18664
AF		 1365
1366 return true;
0c3e702a 1367}
8e2aa21b
AP		 1368
1369static target_ulong riscv_transformed_insn(CPURISCVState *env,
1370 target_ulong insn,
1371 target_ulong taddr)
1372{
1373 target_ulong xinsn = 0;
1374 target_ulong access_rs1 = 0, access_imm = 0, access_size = 0;
1375
1376 /*
1377 * Only Quadrant 0 and Quadrant 2 of RVC instruction space need to
1378 * be uncompressed. The Quadrant 1 of RVC instruction space need
1379 * not be transformed because these instructions won't generate
1380 * any load/store trap.
1381 */
1382
1383 if ((insn & 0x3) != 0x3) {
1384 /* Transform 16bit instruction into 32bit instruction */
1385 switch (GET_C_OP(insn)) {
1386 case OPC_RISC_C_OP_QUAD0: /* Quadrant 0 */
1387 switch (GET_C_FUNC(insn)) {
1388 case OPC_RISC_C_FUNC_FLD_LQ:
1389 if (riscv_cpu_xlen(env) != 128) { /* C.FLD (RV32/64) */
1390 xinsn = OPC_RISC_FLD;
1391 xinsn = SET_RD(xinsn, GET_C_RS2S(insn));
1392 access_rs1 = GET_C_RS1S(insn);
1393 access_imm = GET_C_LD_IMM(insn);
1394 access_size = 8;
1395 }
1396 break;
1397 case OPC_RISC_C_FUNC_LW: /* C.LW */
1398 xinsn = OPC_RISC_LW;
1399 xinsn = SET_RD(xinsn, GET_C_RS2S(insn));
1400 access_rs1 = GET_C_RS1S(insn);
1401 access_imm = GET_C_LW_IMM(insn);
1402 access_size = 4;
1403 break;
1404 case OPC_RISC_C_FUNC_FLW_LD:
1405 if (riscv_cpu_xlen(env) == 32) { /* C.FLW (RV32) */
1406 xinsn = OPC_RISC_FLW;
1407 xinsn = SET_RD(xinsn, GET_C_RS2S(insn));
1408 access_rs1 = GET_C_RS1S(insn);
1409 access_imm = GET_C_LW_IMM(insn);
1410 access_size = 4;
1411 } else { /* C.LD (RV64/RV128) */
1412 xinsn = OPC_RISC_LD;
1413 xinsn = SET_RD(xinsn, GET_C_RS2S(insn));
1414 access_rs1 = GET_C_RS1S(insn);
1415 access_imm = GET_C_LD_IMM(insn);
1416 access_size = 8;
1417 }
1418 break;
1419 case OPC_RISC_C_FUNC_FSD_SQ:
1420 if (riscv_cpu_xlen(env) != 128) { /* C.FSD (RV32/64) */
1421 xinsn = OPC_RISC_FSD;
1422 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn));
1423 access_rs1 = GET_C_RS1S(insn);
1424 access_imm = GET_C_SD_IMM(insn);
1425 access_size = 8;
1426 }
1427 break;
1428 case OPC_RISC_C_FUNC_SW: /* C.SW */
1429 xinsn = OPC_RISC_SW;
1430 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn));
1431 access_rs1 = GET_C_RS1S(insn);
1432 access_imm = GET_C_SW_IMM(insn);
1433 access_size = 4;
1434 break;
1435 case OPC_RISC_C_FUNC_FSW_SD:
1436 if (riscv_cpu_xlen(env) == 32) { /* C.FSW (RV32) */
1437 xinsn = OPC_RISC_FSW;
1438 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn));
1439 access_rs1 = GET_C_RS1S(insn);
1440 access_imm = GET_C_SW_IMM(insn);
1441 access_size = 4;
1442 } else { /* C.SD (RV64/RV128) */
1443 xinsn = OPC_RISC_SD;
1444 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn));
1445 access_rs1 = GET_C_RS1S(insn);
1446 access_imm = GET_C_SD_IMM(insn);
1447 access_size = 8;
1448 }
1449 break;
1450 default:
1451 break;
1452 }
1453 break;
1454 case OPC_RISC_C_OP_QUAD2: /* Quadrant 2 */
1455 switch (GET_C_FUNC(insn)) {
1456 case OPC_RISC_C_FUNC_FLDSP_LQSP:
1457 if (riscv_cpu_xlen(env) != 128) { /* C.FLDSP (RV32/64) */
1458 xinsn = OPC_RISC_FLD;
1459 xinsn = SET_RD(xinsn, GET_C_RD(insn));
1460 access_rs1 = 2;
1461 access_imm = GET_C_LDSP_IMM(insn);
1462 access_size = 8;
1463 }
1464 break;
1465 case OPC_RISC_C_FUNC_LWSP: /* C.LWSP */
1466 xinsn = OPC_RISC_LW;
1467 xinsn = SET_RD(xinsn, GET_C_RD(insn));
1468 access_rs1 = 2;
1469 access_imm = GET_C_LWSP_IMM(insn);
1470 access_size = 4;
1471 break;
1472 case OPC_RISC_C_FUNC_FLWSP_LDSP:
1473 if (riscv_cpu_xlen(env) == 32) { /* C.FLWSP (RV32) */
1474 xinsn = OPC_RISC_FLW;
1475 xinsn = SET_RD(xinsn, GET_C_RD(insn));
1476 access_rs1 = 2;
1477 access_imm = GET_C_LWSP_IMM(insn);
1478 access_size = 4;
1479 } else { /* C.LDSP (RV64/RV128) */
1480 xinsn = OPC_RISC_LD;
1481 xinsn = SET_RD(xinsn, GET_C_RD(insn));
1482 access_rs1 = 2;
1483 access_imm = GET_C_LDSP_IMM(insn);
1484 access_size = 8;
1485 }
1486 break;
1487 case OPC_RISC_C_FUNC_FSDSP_SQSP:
1488 if (riscv_cpu_xlen(env) != 128) { /* C.FSDSP (RV32/64) */
1489 xinsn = OPC_RISC_FSD;
1490 xinsn = SET_RS2(xinsn, GET_C_RS2(insn));
1491 access_rs1 = 2;
1492 access_imm = GET_C_SDSP_IMM(insn);
1493 access_size = 8;
1494 }
1495 break;
1496 case OPC_RISC_C_FUNC_SWSP: /* C.SWSP */
1497 xinsn = OPC_RISC_SW;
1498 xinsn = SET_RS2(xinsn, GET_C_RS2(insn));
1499 access_rs1 = 2;
1500 access_imm = GET_C_SWSP_IMM(insn);
1501 access_size = 4;
1502 break;
1503 case 7:
1504 if (riscv_cpu_xlen(env) == 32) { /* C.FSWSP (RV32) */
1505 xinsn = OPC_RISC_FSW;
1506 xinsn = SET_RS2(xinsn, GET_C_RS2(insn));
1507 access_rs1 = 2;
1508 access_imm = GET_C_SWSP_IMM(insn);
1509 access_size = 4;
1510 } else { /* C.SDSP (RV64/RV128) */
1511 xinsn = OPC_RISC_SD;
1512 xinsn = SET_RS2(xinsn, GET_C_RS2(insn));
1513 access_rs1 = 2;
1514 access_imm = GET_C_SDSP_IMM(insn);
1515 access_size = 8;
1516 }
1517 break;
1518 default:
1519 break;
1520 }
1521 break;
1522 default:
1523 break;
1524 }
1525
1526 /*
1527 * Clear Bit1 of transformed instruction to indicate that
1528 * original insruction was a 16bit instruction
1529 */
1530 xinsn &= ~((target_ulong)0x2);
1531 } else {
1532 /* Transform 32bit (or wider) instructions */
1533 switch (MASK_OP_MAJOR(insn)) {
1534 case OPC_RISC_ATOMIC:
1535 xinsn = insn;
1536 access_rs1 = GET_RS1(insn);
1537 access_size = 1 << GET_FUNCT3(insn);
1538 break;
1539 case OPC_RISC_LOAD:
1540 case OPC_RISC_FP_LOAD:
1541 xinsn = SET_I_IMM(insn, 0);
1542 access_rs1 = GET_RS1(insn);
1543 access_imm = GET_IMM(insn);
1544 access_size = 1 << GET_FUNCT3(insn);
1545 break;
1546 case OPC_RISC_STORE:
1547 case OPC_RISC_FP_STORE:
1548 xinsn = SET_S_IMM(insn, 0);
1549 access_rs1 = GET_RS1(insn);
1550 access_imm = GET_STORE_IMM(insn);
1551 access_size = 1 << GET_FUNCT3(insn);
1552 break;
1553 case OPC_RISC_SYSTEM:
1554 if (MASK_OP_SYSTEM(insn) == OPC_RISC_HLVHSV) {
1555 xinsn = insn;
1556 access_rs1 = GET_RS1(insn);
1557 access_size = 1 << ((GET_FUNCT7(insn) >> 1) & 0x3);
1558 access_size = 1 << access_size;
1559 }
1560 break;
1561 default:
1562 break;
1563 }
1564 }
1565
1566 if (access_size) {
1567 xinsn = SET_RS1(xinsn, (taddr - (env->gpr[access_rs1] + access_imm)) &
1568 (access_size - 1));
1569 }
1570
1571 return xinsn;
1572}
263e2ab2 1573#endif /* !CONFIG_USER_ONLY */
0c3e702a
MC		 1574
1575/*
1576 * Handle Traps
1577 *
1578 * Adapted from Spike's processor_t::take_trap.
1579 *
1580 */
1581void riscv_cpu_do_interrupt(CPUState *cs)
1582{
1583#if !defined(CONFIG_USER_ONLY)
1584
1585 RISCVCPU *cpu = RISCV_CPU(cs);
1586 CPURISCVState *env = &cpu->env;
86d0c457 1587 bool write_gva = false;
284d697c 1588 uint64_t s;
0c3e702a 1589
acbbb94e
MC		 1590 /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide
1591 * so we mask off the MSB and separate into trap type and cause.
1592 */
1593 bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG);
1594 target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK;
d028ac75 1595 uint64_t deleg = async ? env->mideleg : env->medeleg;
acbbb94e 1596 target_ulong tval = 0;
8e2aa21b 1597 target_ulong tinst = 0;
30675539
AF		 1598 target_ulong htval = 0;
1599 target_ulong mtval2 = 0;
acbbb94e 1600
a10b9d93 1601 if (cause == RISCV_EXCP_SEMIHOST) {
7d7fb116
PM		 1602 do_common_semihosting(cs);
1603 env->pc += 4;
1604 return;
a10b9d93
KP		 1605 }
1606
acbbb94e
MC		 1607 if (!async) {
1608 /* set tval to badaddr for traps with address information */
1609 switch (cause) {
ab67a1d0
AF		 1610 case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT:
1611 case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT:
acbbb94e
MC		 1612 case RISCV_EXCP_LOAD_ADDR_MIS:
1613 case RISCV_EXCP_STORE_AMO_ADDR_MIS:
1614 case RISCV_EXCP_LOAD_ACCESS_FAULT:
1615 case RISCV_EXCP_STORE_AMO_ACCESS_FAULT:
acbbb94e
MC		 1616 case RISCV_EXCP_LOAD_PAGE_FAULT:
1617 case RISCV_EXCP_STORE_PAGE_FAULT:
24826da0 1618 write_gva = env->two_stage_lookup;
acbbb94e 1619 tval = env->badaddr;
8e2aa21b
AP		 1620 if (env->two_stage_indirect_lookup) {
1621 /*
1622 * special pseudoinstruction for G-stage fault taken while
1623 * doing VS-stage page table walk.
1624 */
1625 tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000;
1626 } else {
1627 /*
1628 * The "Addr. Offset" field in transformed instruction is
1629 * non-zero only for misaligned access.
1630 */
1631 tinst = riscv_transformed_insn(env, env->bins, tval);
1632 }
1633 break;
1634 case RISCV_EXCP_INST_GUEST_PAGE_FAULT:
1635 case RISCV_EXCP_INST_ADDR_MIS:
1636 case RISCV_EXCP_INST_ACCESS_FAULT:
1637 case RISCV_EXCP_INST_PAGE_FAULT:
1638 write_gva = env->two_stage_lookup;
1639 tval = env->badaddr;
1640 if (env->two_stage_indirect_lookup) {
1641 /*
1642 * special pseudoinstruction for G-stage fault taken while
1643 * doing VS-stage page table walk.
1644 */
1645 tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000;
1646 }
acbbb94e 1647 break;
48eaeb56 1648 case RISCV_EXCP_ILLEGAL_INST:
62cf0245 1649 case RISCV_EXCP_VIRT_INSTRUCTION_FAULT:
48eaeb56
AF		 1650 tval = env->bins;
1651 break;
acbbb94e
MC		 1652 default:
1653 break;
0c3e702a 1654 }
acbbb94e
MC		 1655 /* ecall is dispatched as one cause so translate based on mode */
1656 if (cause == RISCV_EXCP_U_ECALL) {
1657 assert(env->priv <= 3);
5eb9e782
AF		 1658
1659 if (env->priv == PRV_M) {
1660 cause = RISCV_EXCP_M_ECALL;
1661 } else if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) {
1662 cause = RISCV_EXCP_VS_ECALL;
1663 } else if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) {
1664 cause = RISCV_EXCP_S_ECALL;
1665 } else if (env->priv == PRV_U) {
1666 cause = RISCV_EXCP_U_ECALL;
1667 }
0c3e702a
MC		 1668 }
1669 }
1670
c51a3f5d 1671 trace_riscv_trap(env->mhartid, async, cause, env->pc, tval,
69430111
AF		 1672 riscv_cpu_get_trap_name(cause, async));
1673
1674 qemu_log_mask(CPU_LOG_INT,
1675 "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", "
1676 "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n",
1677 __func__, env->mhartid, async, cause, env->pc, tval,
1678 riscv_cpu_get_trap_name(cause, async));
0c3e702a 1679
acbbb94e
MC		 1680 if (env->priv <= PRV_S &&
1681 cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
0c3e702a 1682 /* handle the trap in S-mode */
5eb9e782 1683 if (riscv_has_ext(env, RVH)) {
d028ac75 1684 uint64_t hdeleg = async ? env->hideleg : env->hedeleg;
1c1c060a 1685
50d16087 1686 if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1)) {
84b1c04b 1687 /* Trap to VS mode */
c5969a3a
RK		 1688 /*
1689 * See if we need to adjust cause. Yes if its VS mode interrupt
1690 * no if hypervisor has delegated one of hs mode's interrupt
1691 */
1692 if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT ||
84b1c04b 1693 cause == IRQ_VS_EXT) {
c5969a3a 1694 cause = cause - 1;
84b1c04b 1695 }
86d0c457 1696 write_gva = false;
5eb9e782
AF		 1697 } else if (riscv_cpu_virt_enabled(env)) {
1698 /* Trap into HS mode, from virt */
1699 riscv_cpu_swap_hypervisor_regs(env);
f2d5850f 1700 env->hstatus = set_field(env->hstatus, HSTATUS_SPVP,
ace54453 1701 env->priv);
5eb9e782
AF		 1702 env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
1703 riscv_cpu_virt_enabled(env));
1704
86d0c457 1705
30675539
AF		 1706 htval = env->guest_phys_fault_addr;
1707
5eb9e782 1708 riscv_cpu_set_virt_enabled(env, 0);
5eb9e782
AF		 1709 } else {
1710 /* Trap into HS mode */
ec352d0c 1711 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
30675539 1712 htval = env->guest_phys_fault_addr;
5eb9e782 1713 }
86d0c457 1714 env->hstatus = set_field(env->hstatus, HSTATUS_GVA, write_gva);
5eb9e782
AF		 1715 }
1716
1717 s = env->mstatus;
1a9540d1 1718 s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
0c3e702a
MC		 1719 s = set_field(s, MSTATUS_SPP, env->priv);
1720 s = set_field(s, MSTATUS_SIE, 0);
c7b95171 1721 env->mstatus = s;
16fdb8ff 1722 env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1));
acbbb94e 1723 env->sepc = env->pc;
ac12b601 1724 env->stval = tval;
30675539 1725 env->htval = htval;
8e2aa21b 1726 env->htinst = tinst;
acbbb94e
MC		 1727 env->pc = (env->stvec >> 2 << 2) +
1728 ((async && (env->stvec & 3) == 1) ? cause * 4 : 0);
fb738839 1729 riscv_cpu_set_mode(env, PRV_S);
0c3e702a 1730 } else {
acbbb94e 1731 /* handle the trap in M-mode */
5eb9e782
AF		 1732 if (riscv_has_ext(env, RVH)) {
1733 if (riscv_cpu_virt_enabled(env)) {
1734 riscv_cpu_swap_hypervisor_regs(env);
1735 }
1736 env->mstatus = set_field(env->mstatus, MSTATUS_MPV,
284d697c 1737 riscv_cpu_virt_enabled(env));
9034e90a
AF		 1738 if (riscv_cpu_virt_enabled(env) && tval) {
1739 env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1);
1740 }
5eb9e782 1741
30675539
AF		 1742 mtval2 = env->guest_phys_fault_addr;
1743
5eb9e782
AF		 1744 /* Trapping to M mode, virt is disabled */
1745 riscv_cpu_set_virt_enabled(env, 0);
5eb9e782
AF		 1746 }
1747
1748 s = env->mstatus;
1a9540d1 1749 s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE));
0c3e702a
MC		 1750 s = set_field(s, MSTATUS_MPP, env->priv);
1751 s = set_field(s, MSTATUS_MIE, 0);
c7b95171 1752 env->mstatus = s;
acbbb94e
MC		 1753 env->mcause = cause | ~(((target_ulong)-1) >> async);
1754 env->mepc = env->pc;
ac12b601 1755 env->mtval = tval;
30675539 1756 env->mtval2 = mtval2;
8e2aa21b 1757 env->mtinst = tinst;
acbbb94e
MC		 1758 env->pc = (env->mtvec >> 2 << 2) +
1759 ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);
fb738839 1760 riscv_cpu_set_mode(env, PRV_M);
0c3e702a 1761 }
d9360e96
MC		 1762
1763 /* NOTE: it is not necessary to yield load reservations here. It is only
1764 * necessary for an SC from "another hart" to cause a load reservation
1765 * to be yielded. Refer to the memory consistency model section of the
1766 * RISC-V ISA Specification.
1767 */
1768
ec352d0c 1769 env->two_stage_lookup = false;
8e2aa21b 1770 env->two_stage_indirect_lookup = false;
0c3e702a 1771#endif
330d2ae3 1772 cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */
0c3e702a 1773}
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