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0c3e702a | 1 | /* |
df354dd4 | 2 | * RISC-V CPU helpers for qemu. |
0c3e702a MC |
3 | * |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
21 | #include "qemu/log.h" | |
7ec5d303 | 22 | #include "qemu/main-loop.h" |
0c3e702a MC |
23 | #include "cpu.h" |
24 | #include "exec/exec-all.h" | |
dcb32f1d | 25 | #include "tcg/tcg-op.h" |
929f0a7f | 26 | #include "trace.h" |
6b5fe137 | 27 | #include "semihosting/common-semi.h" |
0c3e702a MC |
28 | |
29 | int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) | |
30 | { | |
31 | #ifdef CONFIG_USER_ONLY | |
32 | return 0; | |
33 | #else | |
34 | return env->priv; | |
35 | #endif | |
36 | } | |
37 | ||
92371bd9 RH |
38 | static RISCVMXL cpu_get_xl(CPURISCVState *env) |
39 | { | |
40 | #if defined(TARGET_RISCV32) | |
41 | return MXL_RV32; | |
42 | #elif defined(CONFIG_USER_ONLY) | |
43 | return MXL_RV64; | |
44 | #else | |
45 | RISCVMXL xl = riscv_cpu_mxl(env); | |
46 | ||
47 | /* | |
48 | * When emulating a 32-bit-only cpu, use RV32. | |
49 | * When emulating a 64-bit cpu, and MXL has been reduced to RV32, | |
50 | * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened | |
51 | * back to RV64 for lower privs. | |
52 | */ | |
53 | if (xl != MXL_RV32) { | |
54 | switch (env->priv) { | |
55 | case PRV_M: | |
56 | break; | |
57 | case PRV_U: | |
58 | xl = get_field(env->mstatus, MSTATUS64_UXL); | |
59 | break; | |
60 | default: /* PRV_S | PRV_H */ | |
61 | xl = get_field(env->mstatus, MSTATUS64_SXL); | |
62 | break; | |
63 | } | |
64 | } | |
65 | return xl; | |
66 | #endif | |
67 | } | |
68 | ||
53677acf RH |
69 | void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, |
70 | target_ulong *cs_base, uint32_t *pflags) | |
71 | { | |
72 | uint32_t flags = 0; | |
73 | ||
74 | *pc = env->pc; | |
75 | *cs_base = 0; | |
76 | ||
77 | if (riscv_has_ext(env, RVV)) { | |
78 | uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype); | |
79 | bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl); | |
80 | flags = FIELD_DP32(flags, TB_FLAGS, VILL, | |
81 | FIELD_EX64(env->vtype, VTYPE, VILL)); | |
82 | flags = FIELD_DP32(flags, TB_FLAGS, SEW, | |
83 | FIELD_EX64(env->vtype, VTYPE, VSEW)); | |
84 | flags = FIELD_DP32(flags, TB_FLAGS, LMUL, | |
85 | FIELD_EX64(env->vtype, VTYPE, VLMUL)); | |
86 | flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); | |
87 | } else { | |
88 | flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); | |
89 | } | |
90 | ||
91 | #ifdef CONFIG_USER_ONLY | |
92 | flags |= TB_FLAGS_MSTATUS_FS; | |
93 | #else | |
94 | flags |= cpu_mmu_index(env, 0); | |
95 | if (riscv_cpu_fp_enabled(env)) { | |
96 | flags |= env->mstatus & MSTATUS_FS; | |
97 | } | |
98 | ||
99 | if (riscv_has_ext(env, RVH)) { | |
100 | if (env->priv == PRV_M || | |
101 | (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || | |
102 | (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && | |
103 | get_field(env->hstatus, HSTATUS_HU))) { | |
104 | flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); | |
105 | } | |
106 | ||
107 | flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, | |
108 | get_field(env->mstatus_hs, MSTATUS_FS)); | |
109 | } | |
0774a7a1 AP |
110 | if (riscv_has_ext(env, RVJ)) { |
111 | int priv = flags & TB_FLAGS_PRIV_MMU_MASK; | |
112 | bool pm_enabled = false; | |
113 | switch (priv) { | |
114 | case PRV_U: | |
115 | pm_enabled = env->mmte & U_PM_ENABLE; | |
116 | break; | |
117 | case PRV_S: | |
118 | pm_enabled = env->mmte & S_PM_ENABLE; | |
119 | break; | |
120 | case PRV_M: | |
121 | pm_enabled = env->mmte & M_PM_ENABLE; | |
122 | break; | |
123 | default: | |
124 | g_assert_not_reached(); | |
125 | } | |
126 | flags = FIELD_DP32(flags, TB_FLAGS, PM_ENABLED, pm_enabled); | |
127 | } | |
53677acf RH |
128 | #endif |
129 | ||
92371bd9 RH |
130 | flags = FIELD_DP32(flags, TB_FLAGS, XL, cpu_get_xl(env)); |
131 | ||
53677acf RH |
132 | *pflags = flags; |
133 | } | |
134 | ||
0c3e702a | 135 | #ifndef CONFIG_USER_ONLY |
efbdbc26 | 136 | static int riscv_cpu_local_irq_pending(CPURISCVState *env) |
0c3e702a | 137 | { |
487a9955 | 138 | target_ulong virt_enabled = riscv_cpu_virt_enabled(env); |
3ef10a09 | 139 | |
efbdbc26 MC |
140 | target_ulong mstatus_mie = get_field(env->mstatus, MSTATUS_MIE); |
141 | target_ulong mstatus_sie = get_field(env->mstatus, MSTATUS_SIE); | |
3ef10a09 | 142 | |
487a9955 | 143 | target_ulong pending = env->mip & env->mie; |
3ef10a09 AF |
144 | |
145 | target_ulong mie = env->priv < PRV_M || | |
146 | (env->priv == PRV_M && mstatus_mie); | |
147 | target_ulong sie = env->priv < PRV_S || | |
148 | (env->priv == PRV_S && mstatus_sie); | |
487a9955 JM |
149 | target_ulong hsie = virt_enabled || sie; |
150 | target_ulong vsie = virt_enabled && sie; | |
3ef10a09 | 151 | |
487a9955 JM |
152 | target_ulong irqs = |
153 | (pending & ~env->mideleg & -mie) | | |
154 | (pending & env->mideleg & ~env->hideleg & -hsie) | | |
155 | (pending & env->mideleg & env->hideleg & -vsie); | |
0c3e702a | 156 | |
efbdbc26 MC |
157 | if (irqs) { |
158 | return ctz64(irqs); /* since non-zero */ | |
0c3e702a | 159 | } else { |
330d2ae3 | 160 | return RISCV_EXCP_NONE; /* indicates no pending interrupt */ |
0c3e702a MC |
161 | } |
162 | } | |
0c3e702a MC |
163 | |
164 | bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) | |
165 | { | |
0c3e702a MC |
166 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
167 | RISCVCPU *cpu = RISCV_CPU(cs); | |
168 | CPURISCVState *env = &cpu->env; | |
efbdbc26 | 169 | int interruptno = riscv_cpu_local_irq_pending(env); |
0c3e702a MC |
170 | if (interruptno >= 0) { |
171 | cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno; | |
172 | riscv_cpu_do_interrupt(cs); | |
173 | return true; | |
174 | } | |
175 | } | |
0c3e702a MC |
176 | return false; |
177 | } | |
178 | ||
b345b480 AF |
179 | /* Return true is floating point support is currently enabled */ |
180 | bool riscv_cpu_fp_enabled(CPURISCVState *env) | |
181 | { | |
182 | if (env->mstatus & MSTATUS_FS) { | |
29409c1d AF |
183 | if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_FS)) { |
184 | return false; | |
185 | } | |
b345b480 AF |
186 | return true; |
187 | } | |
188 | ||
189 | return false; | |
190 | } | |
191 | ||
66e594f2 AF |
192 | void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) |
193 | { | |
284d697c YJ |
194 | uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | |
195 | MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | | |
b550f894 | 196 | MSTATUS64_UXL; |
66e594f2 AF |
197 | bool current_virt = riscv_cpu_virt_enabled(env); |
198 | ||
199 | g_assert(riscv_has_ext(env, RVH)); | |
200 | ||
66e594f2 AF |
201 | if (current_virt) { |
202 | /* Current V=1 and we are about to change to V=0 */ | |
203 | env->vsstatus = env->mstatus & mstatus_mask; | |
204 | env->mstatus &= ~mstatus_mask; | |
205 | env->mstatus |= env->mstatus_hs; | |
206 | ||
207 | env->vstvec = env->stvec; | |
208 | env->stvec = env->stvec_hs; | |
209 | ||
210 | env->vsscratch = env->sscratch; | |
211 | env->sscratch = env->sscratch_hs; | |
212 | ||
213 | env->vsepc = env->sepc; | |
214 | env->sepc = env->sepc_hs; | |
215 | ||
216 | env->vscause = env->scause; | |
217 | env->scause = env->scause_hs; | |
218 | ||
ac12b601 AP |
219 | env->vstval = env->stval; |
220 | env->stval = env->stval_hs; | |
66e594f2 AF |
221 | |
222 | env->vsatp = env->satp; | |
223 | env->satp = env->satp_hs; | |
224 | } else { | |
225 | /* Current V=0 and we are about to change to V=1 */ | |
226 | env->mstatus_hs = env->mstatus & mstatus_mask; | |
227 | env->mstatus &= ~mstatus_mask; | |
228 | env->mstatus |= env->vsstatus; | |
229 | ||
230 | env->stvec_hs = env->stvec; | |
231 | env->stvec = env->vstvec; | |
232 | ||
233 | env->sscratch_hs = env->sscratch; | |
234 | env->sscratch = env->vsscratch; | |
235 | ||
236 | env->sepc_hs = env->sepc; | |
237 | env->sepc = env->vsepc; | |
238 | ||
239 | env->scause_hs = env->scause; | |
240 | env->scause = env->vscause; | |
241 | ||
ac12b601 AP |
242 | env->stval_hs = env->stval; |
243 | env->stval = env->vstval; | |
66e594f2 AF |
244 | |
245 | env->satp_hs = env->satp; | |
246 | env->satp = env->vsatp; | |
247 | } | |
248 | } | |
249 | ||
ef6bb7b6 AF |
250 | bool riscv_cpu_virt_enabled(CPURISCVState *env) |
251 | { | |
252 | if (!riscv_has_ext(env, RVH)) { | |
253 | return false; | |
254 | } | |
255 | ||
256 | return get_field(env->virt, VIRT_ONOFF); | |
257 | } | |
258 | ||
259 | void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) | |
260 | { | |
261 | if (!riscv_has_ext(env, RVH)) { | |
262 | return; | |
263 | } | |
264 | ||
eccc5a12 AF |
265 | /* Flush the TLB on all virt mode changes. */ |
266 | if (get_field(env->virt, VIRT_ONOFF) != enable) { | |
267 | tlb_flush(env_cpu(env)); | |
268 | } | |
269 | ||
ef6bb7b6 AF |
270 | env->virt = set_field(env->virt, VIRT_ONOFF, enable); |
271 | } | |
272 | ||
1c1c060a | 273 | bool riscv_cpu_two_stage_lookup(int mmu_idx) |
5a894dd7 | 274 | { |
1c1c060a | 275 | return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK; |
5a894dd7 AF |
276 | } |
277 | ||
e3e7039c MC |
278 | int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) |
279 | { | |
280 | CPURISCVState *env = &cpu->env; | |
281 | if (env->miclaim & interrupts) { | |
282 | return -1; | |
283 | } else { | |
284 | env->miclaim |= interrupts; | |
285 | return 0; | |
286 | } | |
287 | } | |
288 | ||
df354dd4 MC |
289 | uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value) |
290 | { | |
291 | CPURISCVState *env = &cpu->env; | |
0a01f2ee | 292 | CPUState *cs = CPU(cpu); |
7ec5d303 AF |
293 | uint32_t old = env->mip; |
294 | bool locked = false; | |
295 | ||
296 | if (!qemu_mutex_iothread_locked()) { | |
297 | locked = true; | |
298 | qemu_mutex_lock_iothread(); | |
299 | } | |
df354dd4 | 300 | |
7ec5d303 | 301 | env->mip = (env->mip & ~mask) | (value & mask); |
df354dd4 | 302 | |
7ec5d303 AF |
303 | if (env->mip) { |
304 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); | |
305 | } else { | |
306 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); | |
307 | } | |
0a01f2ee | 308 | |
7ec5d303 AF |
309 | if (locked) { |
310 | qemu_mutex_unlock_iothread(); | |
311 | } | |
df354dd4 MC |
312 | |
313 | return old; | |
314 | } | |
315 | ||
a47ef6e9 BM |
316 | void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), |
317 | uint32_t arg) | |
c6957248 AP |
318 | { |
319 | env->rdtime_fn = fn; | |
a47ef6e9 | 320 | env->rdtime_fn_arg = arg; |
c6957248 AP |
321 | } |
322 | ||
fb738839 | 323 | void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) |
df354dd4 MC |
324 | { |
325 | if (newpriv > PRV_M) { | |
326 | g_assert_not_reached(); | |
327 | } | |
328 | if (newpriv == PRV_H) { | |
329 | newpriv = PRV_U; | |
330 | } | |
331 | /* tlb_flush is unnecessary as mode is contained in mmu_idx */ | |
332 | env->priv = newpriv; | |
c13b169f JS |
333 | |
334 | /* | |
335 | * Clear the load reservation - otherwise a reservation placed in one | |
336 | * context/process can be used by another, resulting in an SC succeeding | |
337 | * incorrectly. Version 2.2 of the ISA specification explicitly requires | |
338 | * this behaviour, while later revisions say that the kernel "should" use | |
339 | * an SC instruction to force the yielding of a load reservation on a | |
340 | * preemptive context switch. As a result, do both. | |
341 | */ | |
342 | env->load_res = -1; | |
df354dd4 MC |
343 | } |
344 | ||
b297129a JS |
345 | /* |
346 | * get_physical_address_pmp - check PMP permission for this physical address | |
347 | * | |
348 | * Match the PMP region and check permission for this physical address and it's | |
349 | * TLB page. Returns 0 if the permission checking was successful | |
350 | * | |
351 | * @env: CPURISCVState | |
352 | * @prot: The returned protection attributes | |
353 | * @tlb_size: TLB page size containing addr. It could be modified after PMP | |
354 | * permission checking. NULL if not set TLB page for addr. | |
355 | * @addr: The physical address to be checked permission | |
356 | * @access_type: The type of MMU access | |
357 | * @mode: Indicates current privilege level. | |
358 | */ | |
359 | static int get_physical_address_pmp(CPURISCVState *env, int *prot, | |
360 | target_ulong *tlb_size, hwaddr addr, | |
361 | int size, MMUAccessType access_type, | |
362 | int mode) | |
363 | { | |
364 | pmp_priv_t pmp_priv; | |
365 | target_ulong tlb_size_pmp = 0; | |
366 | ||
367 | if (!riscv_feature(env, RISCV_FEATURE_PMP)) { | |
368 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
369 | return TRANSLATE_SUCCESS; | |
370 | } | |
371 | ||
372 | if (!pmp_hart_has_privs(env, addr, size, 1 << access_type, &pmp_priv, | |
373 | mode)) { | |
374 | *prot = 0; | |
375 | return TRANSLATE_PMP_FAIL; | |
376 | } | |
377 | ||
378 | *prot = pmp_priv_to_page_prot(pmp_priv); | |
379 | if (tlb_size != NULL) { | |
380 | if (pmp_is_range_in_tlb(env, addr & ~(*tlb_size - 1), &tlb_size_pmp)) { | |
381 | *tlb_size = tlb_size_pmp; | |
382 | } | |
383 | } | |
384 | ||
385 | return TRANSLATE_SUCCESS; | |
386 | } | |
387 | ||
0c3e702a MC |
388 | /* get_physical_address - get the physical address for this virtual address |
389 | * | |
390 | * Do a page table walk to obtain the physical address corresponding to a | |
391 | * virtual address. Returns 0 if the translation was successful | |
392 | * | |
393 | * Adapted from Spike's mmu_t::translate and mmu_t::walk | |
394 | * | |
1448689c AF |
395 | * @env: CPURISCVState |
396 | * @physical: This will be set to the calculated physical address | |
397 | * @prot: The returned protection attributes | |
398 | * @addr: The virtual address to be translated | |
33a9a57d YJ |
399 | * @fault_pte_addr: If not NULL, this will be set to fault pte address |
400 | * when a error occurs on pte address translation. | |
401 | * This will already be shifted to match htval. | |
1448689c AF |
402 | * @access_type: The type of MMU access |
403 | * @mmu_idx: Indicates current privilege level | |
404 | * @first_stage: Are we in first stage translation? | |
405 | * Second stage is used for hypervisor guest translation | |
36a18664 | 406 | * @two_stage: Are we going to perform two stage translation |
11c27c6d | 407 | * @is_debug: Is this access from a debugger or the monitor? |
0c3e702a MC |
408 | */ |
409 | static int get_physical_address(CPURISCVState *env, hwaddr *physical, | |
410 | int *prot, target_ulong addr, | |
33a9a57d | 411 | target_ulong *fault_pte_addr, |
1448689c | 412 | int access_type, int mmu_idx, |
11c27c6d JF |
413 | bool first_stage, bool two_stage, |
414 | bool is_debug) | |
0c3e702a MC |
415 | { |
416 | /* NOTE: the env->pc value visible here will not be | |
417 | * correct, but the value visible to the exception handler | |
418 | * (riscv_cpu_do_interrupt) is correct */ | |
aacb578f PD |
419 | MemTxResult res; |
420 | MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; | |
c445593d | 421 | int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK; |
36a18664 | 422 | bool use_background = false; |
0c3e702a | 423 | |
36a18664 AF |
424 | /* |
425 | * Check if we should use the background registers for the two | |
426 | * stage translation. We don't need to check if we actually need | |
427 | * two stage translation as that happened before this function | |
428 | * was called. Background registers will be used if the guest has | |
429 | * forced a two stage translation to be on (in HS or M mode). | |
430 | */ | |
db9ab38b | 431 | if (!riscv_cpu_virt_enabled(env) && two_stage) { |
29b3361b AF |
432 | use_background = true; |
433 | } | |
434 | ||
90ec1cff GK |
435 | /* MPRV does not affect the virtual-machine load/store |
436 | instructions, HLV, HLVX, and HSV. */ | |
437 | if (riscv_cpu_two_stage_lookup(mmu_idx)) { | |
438 | mode = get_field(env->hstatus, HSTATUS_SPVP); | |
439 | } else if (mode == PRV_M && access_type != MMU_INST_FETCH) { | |
0c3e702a MC |
440 | if (get_field(env->mstatus, MSTATUS_MPRV)) { |
441 | mode = get_field(env->mstatus, MSTATUS_MPP); | |
442 | } | |
443 | } | |
444 | ||
36a18664 AF |
445 | if (first_stage == false) { |
446 | /* We are in stage 2 translation, this is similar to stage 1. */ | |
447 | /* Stage 2 is always taken as U-mode */ | |
448 | mode = PRV_U; | |
449 | } | |
450 | ||
0c3e702a MC |
451 | if (mode == PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) { |
452 | *physical = addr; | |
453 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
454 | return TRANSLATE_SUCCESS; | |
455 | } | |
456 | ||
457 | *prot = 0; | |
458 | ||
ddf78132 | 459 | hwaddr base; |
36a18664 AF |
460 | int levels, ptidxbits, ptesize, vm, sum, mxr, widened; |
461 | ||
462 | if (first_stage == true) { | |
463 | mxr = get_field(env->mstatus, MSTATUS_MXR); | |
464 | } else { | |
465 | mxr = get_field(env->vsstatus, MSTATUS_MXR); | |
466 | } | |
0c3e702a | 467 | |
1a9540d1 AF |
468 | if (first_stage == true) { |
469 | if (use_background) { | |
db23e5d9 | 470 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
419ddf00 AF |
471 | base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT; |
472 | vm = get_field(env->vsatp, SATP32_MODE); | |
473 | } else { | |
474 | base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT; | |
475 | vm = get_field(env->vsatp, SATP64_MODE); | |
476 | } | |
36a18664 | 477 | } else { |
db23e5d9 | 478 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
419ddf00 AF |
479 | base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; |
480 | vm = get_field(env->satp, SATP32_MODE); | |
481 | } else { | |
482 | base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT; | |
483 | vm = get_field(env->satp, SATP64_MODE); | |
484 | } | |
0c3e702a | 485 | } |
36a18664 | 486 | widened = 0; |
1a9540d1 | 487 | } else { |
db23e5d9 | 488 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
994b6bb2 AF |
489 | base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT; |
490 | vm = get_field(env->hgatp, SATP32_MODE); | |
491 | } else { | |
492 | base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT; | |
493 | vm = get_field(env->hgatp, SATP64_MODE); | |
494 | } | |
1a9540d1 AF |
495 | widened = 2; |
496 | } | |
c63ca4ff | 497 | /* status.SUM will be ignored if execute on background */ |
11c27c6d | 498 | sum = get_field(env->mstatus, MSTATUS_SUM) || use_background || is_debug; |
1a9540d1 AF |
499 | switch (vm) { |
500 | case VM_1_10_SV32: | |
501 | levels = 2; ptidxbits = 10; ptesize = 4; break; | |
502 | case VM_1_10_SV39: | |
503 | levels = 3; ptidxbits = 9; ptesize = 8; break; | |
504 | case VM_1_10_SV48: | |
505 | levels = 4; ptidxbits = 9; ptesize = 8; break; | |
506 | case VM_1_10_SV57: | |
507 | levels = 5; ptidxbits = 9; ptesize = 8; break; | |
508 | case VM_1_10_MBARE: | |
509 | *physical = addr; | |
510 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
511 | return TRANSLATE_SUCCESS; | |
512 | default: | |
513 | g_assert_not_reached(); | |
0c3e702a MC |
514 | } |
515 | ||
3109cd98 | 516 | CPUState *cs = env_cpu(env); |
36a18664 AF |
517 | int va_bits = PGSHIFT + levels * ptidxbits + widened; |
518 | target_ulong mask, masked_msbs; | |
519 | ||
520 | if (TARGET_LONG_BITS > (va_bits - 1)) { | |
521 | mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; | |
522 | } else { | |
523 | mask = 0; | |
524 | } | |
525 | masked_msbs = (addr >> (va_bits - 1)) & mask; | |
526 | ||
0c3e702a MC |
527 | if (masked_msbs != 0 && masked_msbs != mask) { |
528 | return TRANSLATE_FAIL; | |
529 | } | |
530 | ||
531 | int ptshift = (levels - 1) * ptidxbits; | |
532 | int i; | |
533 | ||
534 | #if !TCG_OVERSIZED_GUEST | |
535 | restart: | |
536 | #endif | |
537 | for (i = 0; i < levels; i++, ptshift -= ptidxbits) { | |
36a18664 AF |
538 | target_ulong idx; |
539 | if (i == 0) { | |
540 | idx = (addr >> (PGSHIFT + ptshift)) & | |
541 | ((1 << (ptidxbits + widened)) - 1); | |
542 | } else { | |
543 | idx = (addr >> (PGSHIFT + ptshift)) & | |
0c3e702a | 544 | ((1 << ptidxbits) - 1); |
36a18664 | 545 | } |
0c3e702a MC |
546 | |
547 | /* check that physical address of PTE is legal */ | |
36a18664 AF |
548 | hwaddr pte_addr; |
549 | ||
550 | if (two_stage && first_stage) { | |
38472890 | 551 | int vbase_prot; |
36a18664 AF |
552 | hwaddr vbase; |
553 | ||
554 | /* Do the second stage translation on the base PTE address. */ | |
88914473 | 555 | int vbase_ret = get_physical_address(env, &vbase, &vbase_prot, |
33a9a57d | 556 | base, NULL, MMU_DATA_LOAD, |
11c27c6d JF |
557 | mmu_idx, false, true, |
558 | is_debug); | |
88914473 AF |
559 | |
560 | if (vbase_ret != TRANSLATE_SUCCESS) { | |
33a9a57d YJ |
561 | if (fault_pte_addr) { |
562 | *fault_pte_addr = (base + idx * ptesize) >> 2; | |
563 | } | |
564 | return TRANSLATE_G_STAGE_FAIL; | |
88914473 | 565 | } |
36a18664 AF |
566 | |
567 | pte_addr = vbase + idx * ptesize; | |
568 | } else { | |
569 | pte_addr = base + idx * ptesize; | |
570 | } | |
1f447aec | 571 | |
b297129a JS |
572 | int pmp_prot; |
573 | int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr, | |
574 | sizeof(target_ulong), | |
575 | MMU_DATA_LOAD, PRV_S); | |
576 | if (pmp_ret != TRANSLATE_SUCCESS) { | |
1f447aec HA |
577 | return TRANSLATE_PMP_FAIL; |
578 | } | |
aacb578f | 579 | |
f08c7ff3 | 580 | target_ulong pte; |
db23e5d9 | 581 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
f08c7ff3 AF |
582 | pte = address_space_ldl(cs->as, pte_addr, attrs, &res); |
583 | } else { | |
584 | pte = address_space_ldq(cs->as, pte_addr, attrs, &res); | |
585 | } | |
586 | ||
aacb578f PD |
587 | if (res != MEMTX_OK) { |
588 | return TRANSLATE_FAIL; | |
589 | } | |
590 | ||
ddf78132 | 591 | hwaddr ppn = pte >> PTE_PPN_SHIFT; |
0c3e702a | 592 | |
c3b03e58 MC |
593 | if (!(pte & PTE_V)) { |
594 | /* Invalid PTE */ | |
595 | return TRANSLATE_FAIL; | |
596 | } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { | |
597 | /* Inner PTE, continue walking */ | |
0c3e702a | 598 | base = ppn << PGSHIFT; |
c3b03e58 MC |
599 | } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) { |
600 | /* Reserved leaf PTE flags: PTE_W */ | |
601 | return TRANSLATE_FAIL; | |
602 | } else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) { | |
603 | /* Reserved leaf PTE flags: PTE_W + PTE_X */ | |
604 | return TRANSLATE_FAIL; | |
605 | } else if ((pte & PTE_U) && ((mode != PRV_U) && | |
606 | (!sum || access_type == MMU_INST_FETCH))) { | |
607 | /* User PTE flags when not U mode and mstatus.SUM is not set, | |
608 | or the access type is an instruction fetch */ | |
609 | return TRANSLATE_FAIL; | |
610 | } else if (!(pte & PTE_U) && (mode != PRV_S)) { | |
611 | /* Supervisor PTE flags when not S mode */ | |
612 | return TRANSLATE_FAIL; | |
613 | } else if (ppn & ((1ULL << ptshift) - 1)) { | |
614 | /* Misaligned PPN */ | |
615 | return TRANSLATE_FAIL; | |
616 | } else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) || | |
617 | ((pte & PTE_X) && mxr))) { | |
618 | /* Read access check failed */ | |
619 | return TRANSLATE_FAIL; | |
620 | } else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) { | |
621 | /* Write access check failed */ | |
622 | return TRANSLATE_FAIL; | |
623 | } else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) { | |
624 | /* Fetch access check failed */ | |
625 | return TRANSLATE_FAIL; | |
0c3e702a MC |
626 | } else { |
627 | /* if necessary, set accessed and dirty bits. */ | |
628 | target_ulong updated_pte = pte | PTE_A | | |
629 | (access_type == MMU_DATA_STORE ? PTE_D : 0); | |
630 | ||
631 | /* Page table updates need to be atomic with MTTCG enabled */ | |
632 | if (updated_pte != pte) { | |
c3b03e58 MC |
633 | /* |
634 | * - if accessed or dirty bits need updating, and the PTE is | |
635 | * in RAM, then we do so atomically with a compare and swap. | |
636 | * - if the PTE is in IO space or ROM, then it can't be updated | |
637 | * and we return TRANSLATE_FAIL. | |
638 | * - if the PTE changed by the time we went to update it, then | |
639 | * it is no longer valid and we must re-walk the page table. | |
640 | */ | |
0c3e702a MC |
641 | MemoryRegion *mr; |
642 | hwaddr l = sizeof(target_ulong), addr1; | |
643 | mr = address_space_translate(cs->as, pte_addr, | |
bc6b1cec | 644 | &addr1, &l, false, MEMTXATTRS_UNSPECIFIED); |
c3b03e58 | 645 | if (memory_region_is_ram(mr)) { |
0c3e702a MC |
646 | target_ulong *pte_pa = |
647 | qemu_map_ram_ptr(mr->ram_block, addr1); | |
648 | #if TCG_OVERSIZED_GUEST | |
649 | /* MTTCG is not enabled on oversized TCG guests so | |
650 | * page table updates do not need to be atomic */ | |
651 | *pte_pa = pte = updated_pte; | |
652 | #else | |
653 | target_ulong old_pte = | |
d73415a3 | 654 | qatomic_cmpxchg(pte_pa, pte, updated_pte); |
0c3e702a MC |
655 | if (old_pte != pte) { |
656 | goto restart; | |
657 | } else { | |
658 | pte = updated_pte; | |
659 | } | |
660 | #endif | |
661 | } else { | |
662 | /* misconfigured PTE in ROM (AD bits are not preset) or | |
663 | * PTE is in IO space and can't be updated atomically */ | |
664 | return TRANSLATE_FAIL; | |
665 | } | |
666 | } | |
667 | ||
668 | /* for superpage mappings, make a fake leaf PTE for the TLB's | |
669 | benefit. */ | |
670 | target_ulong vpn = addr >> PGSHIFT; | |
9ef82119 ZL |
671 | *physical = ((ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT) | |
672 | (addr & ~TARGET_PAGE_MASK); | |
0c3e702a | 673 | |
c3b03e58 MC |
674 | /* set permissions on the TLB entry */ |
675 | if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { | |
0c3e702a MC |
676 | *prot |= PAGE_READ; |
677 | } | |
678 | if ((pte & PTE_X)) { | |
679 | *prot |= PAGE_EXEC; | |
680 | } | |
c3b03e58 MC |
681 | /* add write permission on stores or if the page is already dirty, |
682 | so that we TLB miss on later writes to update the dirty bit */ | |
0c3e702a MC |
683 | if ((pte & PTE_W) && |
684 | (access_type == MMU_DATA_STORE || (pte & PTE_D))) { | |
685 | *prot |= PAGE_WRITE; | |
686 | } | |
687 | return TRANSLATE_SUCCESS; | |
688 | } | |
689 | } | |
690 | return TRANSLATE_FAIL; | |
691 | } | |
692 | ||
693 | static void raise_mmu_exception(CPURISCVState *env, target_ulong address, | |
1448689c | 694 | MMUAccessType access_type, bool pmp_violation, |
1c1c060a | 695 | bool first_stage, bool two_stage) |
0c3e702a | 696 | { |
3109cd98 | 697 | CPUState *cs = env_cpu(env); |
994b6bb2 | 698 | int page_fault_exceptions, vm; |
419ddf00 AF |
699 | uint64_t stap_mode; |
700 | ||
db23e5d9 | 701 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
419ddf00 AF |
702 | stap_mode = SATP32_MODE; |
703 | } else { | |
704 | stap_mode = SATP64_MODE; | |
705 | } | |
994b6bb2 | 706 | |
1448689c | 707 | if (first_stage) { |
419ddf00 | 708 | vm = get_field(env->satp, stap_mode); |
1448689c | 709 | } else { |
419ddf00 | 710 | vm = get_field(env->hgatp, stap_mode); |
1448689c | 711 | } |
419ddf00 | 712 | |
994b6bb2 AF |
713 | page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation; |
714 | ||
0c3e702a MC |
715 | switch (access_type) { |
716 | case MMU_INST_FETCH: | |
b2ef6ab9 AF |
717 | if (riscv_cpu_virt_enabled(env) && !first_stage) { |
718 | cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT; | |
719 | } else { | |
720 | cs->exception_index = page_fault_exceptions ? | |
721 | RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT; | |
722 | } | |
0c3e702a MC |
723 | break; |
724 | case MMU_DATA_LOAD: | |
1c1c060a | 725 | if (two_stage && !first_stage) { |
b2ef6ab9 AF |
726 | cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; |
727 | } else { | |
728 | cs->exception_index = page_fault_exceptions ? | |
729 | RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT; | |
730 | } | |
0c3e702a MC |
731 | break; |
732 | case MMU_DATA_STORE: | |
1c1c060a | 733 | if (two_stage && !first_stage) { |
b2ef6ab9 AF |
734 | cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT; |
735 | } else { | |
736 | cs->exception_index = page_fault_exceptions ? | |
737 | RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_FAULT; | |
738 | } | |
0c3e702a MC |
739 | break; |
740 | default: | |
741 | g_assert_not_reached(); | |
742 | } | |
743 | env->badaddr = address; | |
ec352d0c | 744 | env->two_stage_lookup = two_stage; |
0c3e702a MC |
745 | } |
746 | ||
747 | hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) | |
748 | { | |
749 | RISCVCPU *cpu = RISCV_CPU(cs); | |
36a18664 | 750 | CPURISCVState *env = &cpu->env; |
0c3e702a MC |
751 | hwaddr phys_addr; |
752 | int prot; | |
753 | int mmu_idx = cpu_mmu_index(&cpu->env, false); | |
754 | ||
33a9a57d | 755 | if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx, |
11c27c6d | 756 | true, riscv_cpu_virt_enabled(env), true)) { |
0c3e702a MC |
757 | return -1; |
758 | } | |
36a18664 AF |
759 | |
760 | if (riscv_cpu_virt_enabled(env)) { | |
33a9a57d | 761 | if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL, |
11c27c6d | 762 | 0, mmu_idx, false, true, true)) { |
36a18664 AF |
763 | return -1; |
764 | } | |
765 | } | |
766 | ||
9ef82119 | 767 | return phys_addr & TARGET_PAGE_MASK; |
0c3e702a MC |
768 | } |
769 | ||
37207e12 PD |
770 | void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, |
771 | vaddr addr, unsigned size, | |
772 | MMUAccessType access_type, | |
773 | int mmu_idx, MemTxAttrs attrs, | |
774 | MemTxResult response, uintptr_t retaddr) | |
cbf58276 MC |
775 | { |
776 | RISCVCPU *cpu = RISCV_CPU(cs); | |
777 | CPURISCVState *env = &cpu->env; | |
778 | ||
37207e12 | 779 | if (access_type == MMU_DATA_STORE) { |
cbf58276 | 780 | cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; |
f9e580c1 | 781 | } else if (access_type == MMU_DATA_LOAD) { |
cbf58276 | 782 | cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; |
f9e580c1 EB |
783 | } else { |
784 | cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT; | |
cbf58276 MC |
785 | } |
786 | ||
787 | env->badaddr = addr; | |
ec352d0c GK |
788 | env->two_stage_lookup = riscv_cpu_virt_enabled(env) || |
789 | riscv_cpu_two_stage_lookup(mmu_idx); | |
37207e12 | 790 | riscv_raise_exception(&cpu->env, cs->exception_index, retaddr); |
cbf58276 MC |
791 | } |
792 | ||
0c3e702a MC |
793 | void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, |
794 | MMUAccessType access_type, int mmu_idx, | |
795 | uintptr_t retaddr) | |
796 | { | |
797 | RISCVCPU *cpu = RISCV_CPU(cs); | |
798 | CPURISCVState *env = &cpu->env; | |
799 | switch (access_type) { | |
800 | case MMU_INST_FETCH: | |
801 | cs->exception_index = RISCV_EXCP_INST_ADDR_MIS; | |
802 | break; | |
803 | case MMU_DATA_LOAD: | |
804 | cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS; | |
805 | break; | |
806 | case MMU_DATA_STORE: | |
807 | cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS; | |
808 | break; | |
809 | default: | |
810 | g_assert_not_reached(); | |
811 | } | |
812 | env->badaddr = addr; | |
ec352d0c GK |
813 | env->two_stage_lookup = riscv_cpu_virt_enabled(env) || |
814 | riscv_cpu_two_stage_lookup(mmu_idx); | |
fb738839 | 815 | riscv_raise_exception(env, cs->exception_index, retaddr); |
0c3e702a | 816 | } |
cbc183d2 | 817 | #endif /* !CONFIG_USER_ONLY */ |
0c3e702a | 818 | |
8a4ca3c1 RH |
819 | bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
820 | MMUAccessType access_type, int mmu_idx, | |
821 | bool probe, uintptr_t retaddr) | |
0c3e702a MC |
822 | { |
823 | RISCVCPU *cpu = RISCV_CPU(cs); | |
824 | CPURISCVState *env = &cpu->env; | |
2921343b | 825 | #ifndef CONFIG_USER_ONLY |
36a18664 | 826 | vaddr im_address; |
0c3e702a | 827 | hwaddr pa = 0; |
b297129a | 828 | int prot, prot2, prot_pmp; |
635b0b0e | 829 | bool pmp_violation = false; |
36a18664 | 830 | bool first_stage_error = true; |
1c1c060a | 831 | bool two_stage_lookup = false; |
0c3e702a | 832 | int ret = TRANSLATE_FAIL; |
cc0fdb29 | 833 | int mode = mmu_idx; |
b297129a JS |
834 | /* default TLB page size */ |
835 | target_ulong tlb_size = TARGET_PAGE_SIZE; | |
0c3e702a | 836 | |
36a18664 AF |
837 | env->guest_phys_fault_addr = 0; |
838 | ||
8a4ca3c1 RH |
839 | qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", |
840 | __func__, address, access_type, mmu_idx); | |
841 | ||
90ec1cff GK |
842 | /* MPRV does not affect the virtual-machine load/store |
843 | instructions, HLV, HLVX, and HSV. */ | |
844 | if (riscv_cpu_two_stage_lookup(mmu_idx)) { | |
845 | mode = get_field(env->hstatus, HSTATUS_SPVP); | |
846 | } else if (mode == PRV_M && access_type != MMU_INST_FETCH && | |
847 | get_field(env->mstatus, MSTATUS_MPRV)) { | |
848 | mode = get_field(env->mstatus, MSTATUS_MPP); | |
849 | if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) { | |
850 | two_stage_lookup = true; | |
cc0fdb29 HA |
851 | } |
852 | } | |
853 | ||
29b3361b | 854 | if (riscv_cpu_virt_enabled(env) || |
1c1c060a AF |
855 | ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) && |
856 | access_type != MMU_INST_FETCH)) { | |
36a18664 | 857 | /* Two stage lookup */ |
33a9a57d YJ |
858 | ret = get_physical_address(env, &pa, &prot, address, |
859 | &env->guest_phys_fault_addr, access_type, | |
11c27c6d | 860 | mmu_idx, true, true, false); |
36a18664 | 861 | |
33a9a57d YJ |
862 | /* |
863 | * A G-stage exception may be triggered during two state lookup. | |
864 | * And the env->guest_phys_fault_addr has already been set in | |
865 | * get_physical_address(). | |
866 | */ | |
867 | if (ret == TRANSLATE_G_STAGE_FAIL) { | |
868 | first_stage_error = false; | |
869 | access_type = MMU_DATA_LOAD; | |
870 | } | |
871 | ||
36a18664 AF |
872 | qemu_log_mask(CPU_LOG_MMU, |
873 | "%s 1st-stage address=%" VADDR_PRIx " ret %d physical " | |
874 | TARGET_FMT_plx " prot %d\n", | |
875 | __func__, address, ret, pa, prot); | |
876 | ||
33a9a57d | 877 | if (ret == TRANSLATE_SUCCESS) { |
36a18664 AF |
878 | /* Second stage lookup */ |
879 | im_address = pa; | |
880 | ||
33a9a57d | 881 | ret = get_physical_address(env, &pa, &prot2, im_address, NULL, |
11c27c6d JF |
882 | access_type, mmu_idx, false, true, |
883 | false); | |
36a18664 AF |
884 | |
885 | qemu_log_mask(CPU_LOG_MMU, | |
886 | "%s 2nd-stage address=%" VADDR_PRIx " ret %d physical " | |
887 | TARGET_FMT_plx " prot %d\n", | |
8f67cd6d AF |
888 | __func__, im_address, ret, pa, prot2); |
889 | ||
890 | prot &= prot2; | |
36a18664 | 891 | |
b297129a JS |
892 | if (ret == TRANSLATE_SUCCESS) { |
893 | ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, | |
894 | size, access_type, mode); | |
663e1193 JS |
895 | |
896 | qemu_log_mask(CPU_LOG_MMU, | |
897 | "%s PMP address=" TARGET_FMT_plx " ret %d prot" | |
898 | " %d tlb_size " TARGET_FMT_lu "\n", | |
899 | __func__, pa, ret, prot_pmp, tlb_size); | |
900 | ||
b297129a | 901 | prot &= prot_pmp; |
36a18664 AF |
902 | } |
903 | ||
904 | if (ret != TRANSLATE_SUCCESS) { | |
905 | /* | |
906 | * Guest physical address translation failed, this is a HS | |
907 | * level exception | |
908 | */ | |
909 | first_stage_error = false; | |
910 | env->guest_phys_fault_addr = (im_address | | |
911 | (address & | |
912 | (TARGET_PAGE_SIZE - 1))) >> 2; | |
913 | } | |
914 | } | |
915 | } else { | |
916 | /* Single stage lookup */ | |
33a9a57d | 917 | ret = get_physical_address(env, &pa, &prot, address, NULL, |
11c27c6d | 918 | access_type, mmu_idx, true, false, false); |
36a18664 AF |
919 | |
920 | qemu_log_mask(CPU_LOG_MMU, | |
921 | "%s address=%" VADDR_PRIx " ret %d physical " | |
922 | TARGET_FMT_plx " prot %d\n", | |
923 | __func__, address, ret, pa, prot); | |
8a4ca3c1 | 924 | |
b297129a JS |
925 | if (ret == TRANSLATE_SUCCESS) { |
926 | ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, | |
927 | size, access_type, mode); | |
663e1193 JS |
928 | |
929 | qemu_log_mask(CPU_LOG_MMU, | |
930 | "%s PMP address=" TARGET_FMT_plx " ret %d prot" | |
931 | " %d tlb_size " TARGET_FMT_lu "\n", | |
932 | __func__, pa, ret, prot_pmp, tlb_size); | |
933 | ||
b297129a JS |
934 | prot &= prot_pmp; |
935 | } | |
1f447aec | 936 | } |
b297129a | 937 | |
1f447aec | 938 | if (ret == TRANSLATE_PMP_FAIL) { |
635b0b0e | 939 | pmp_violation = true; |
0c3e702a | 940 | } |
36a18664 | 941 | |
0c3e702a | 942 | if (ret == TRANSLATE_SUCCESS) { |
b297129a JS |
943 | tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1), |
944 | prot, mmu_idx, tlb_size); | |
8a4ca3c1 RH |
945 | return true; |
946 | } else if (probe) { | |
947 | return false; | |
948 | } else { | |
1c1c060a AF |
949 | raise_mmu_exception(env, address, access_type, pmp_violation, |
950 | first_stage_error, | |
951 | riscv_cpu_virt_enabled(env) || | |
952 | riscv_cpu_two_stage_lookup(mmu_idx)); | |
8a4ca3c1 | 953 | riscv_raise_exception(env, cs->exception_index, retaddr); |
0c3e702a | 954 | } |
36a18664 AF |
955 | |
956 | return true; | |
957 | ||
0c3e702a | 958 | #else |
8a4ca3c1 | 959 | switch (access_type) { |
0c3e702a MC |
960 | case MMU_INST_FETCH: |
961 | cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT; | |
962 | break; | |
963 | case MMU_DATA_LOAD: | |
964 | cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT; | |
965 | break; | |
966 | case MMU_DATA_STORE: | |
967 | cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT; | |
968 | break; | |
2921343b GM |
969 | default: |
970 | g_assert_not_reached(); | |
0c3e702a | 971 | } |
2921343b | 972 | env->badaddr = address; |
8a4ca3c1 | 973 | cpu_loop_exit_restore(cs, retaddr); |
0c3e702a | 974 | #endif |
0c3e702a MC |
975 | } |
976 | ||
977 | /* | |
978 | * Handle Traps | |
979 | * | |
980 | * Adapted from Spike's processor_t::take_trap. | |
981 | * | |
982 | */ | |
983 | void riscv_cpu_do_interrupt(CPUState *cs) | |
984 | { | |
985 | #if !defined(CONFIG_USER_ONLY) | |
986 | ||
987 | RISCVCPU *cpu = RISCV_CPU(cs); | |
988 | CPURISCVState *env = &cpu->env; | |
284d697c | 989 | uint64_t s; |
0c3e702a | 990 | |
acbbb94e MC |
991 | /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide |
992 | * so we mask off the MSB and separate into trap type and cause. | |
993 | */ | |
994 | bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG); | |
995 | target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; | |
996 | target_ulong deleg = async ? env->mideleg : env->medeleg; | |
4aeb9e26 | 997 | bool write_tval = false; |
acbbb94e | 998 | target_ulong tval = 0; |
30675539 AF |
999 | target_ulong htval = 0; |
1000 | target_ulong mtval2 = 0; | |
acbbb94e | 1001 | |
a10b9d93 KP |
1002 | if (cause == RISCV_EXCP_SEMIHOST) { |
1003 | if (env->priv >= PRV_S) { | |
1004 | env->gpr[xA0] = do_common_semihosting(cs); | |
1005 | env->pc += 4; | |
1006 | return; | |
1007 | } | |
1008 | cause = RISCV_EXCP_BREAKPOINT; | |
1009 | } | |
1010 | ||
acbbb94e MC |
1011 | if (!async) { |
1012 | /* set tval to badaddr for traps with address information */ | |
1013 | switch (cause) { | |
ab67a1d0 AF |
1014 | case RISCV_EXCP_INST_GUEST_PAGE_FAULT: |
1015 | case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: | |
1016 | case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: | |
acbbb94e MC |
1017 | case RISCV_EXCP_INST_ADDR_MIS: |
1018 | case RISCV_EXCP_INST_ACCESS_FAULT: | |
1019 | case RISCV_EXCP_LOAD_ADDR_MIS: | |
1020 | case RISCV_EXCP_STORE_AMO_ADDR_MIS: | |
1021 | case RISCV_EXCP_LOAD_ACCESS_FAULT: | |
1022 | case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: | |
1023 | case RISCV_EXCP_INST_PAGE_FAULT: | |
1024 | case RISCV_EXCP_LOAD_PAGE_FAULT: | |
1025 | case RISCV_EXCP_STORE_PAGE_FAULT: | |
4aeb9e26 | 1026 | write_tval = true; |
acbbb94e MC |
1027 | tval = env->badaddr; |
1028 | break; | |
1029 | default: | |
1030 | break; | |
0c3e702a | 1031 | } |
acbbb94e MC |
1032 | /* ecall is dispatched as one cause so translate based on mode */ |
1033 | if (cause == RISCV_EXCP_U_ECALL) { | |
1034 | assert(env->priv <= 3); | |
5eb9e782 AF |
1035 | |
1036 | if (env->priv == PRV_M) { | |
1037 | cause = RISCV_EXCP_M_ECALL; | |
1038 | } else if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) { | |
1039 | cause = RISCV_EXCP_VS_ECALL; | |
1040 | } else if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) { | |
1041 | cause = RISCV_EXCP_S_ECALL; | |
1042 | } else if (env->priv == PRV_U) { | |
1043 | cause = RISCV_EXCP_U_ECALL; | |
1044 | } | |
0c3e702a MC |
1045 | } |
1046 | } | |
1047 | ||
c51a3f5d | 1048 | trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, |
69430111 AF |
1049 | riscv_cpu_get_trap_name(cause, async)); |
1050 | ||
1051 | qemu_log_mask(CPU_LOG_INT, | |
1052 | "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", " | |
1053 | "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n", | |
1054 | __func__, env->mhartid, async, cause, env->pc, tval, | |
1055 | riscv_cpu_get_trap_name(cause, async)); | |
0c3e702a | 1056 | |
acbbb94e MC |
1057 | if (env->priv <= PRV_S && |
1058 | cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { | |
0c3e702a | 1059 | /* handle the trap in S-mode */ |
5eb9e782 AF |
1060 | if (riscv_has_ext(env, RVH)) { |
1061 | target_ulong hdeleg = async ? env->hideleg : env->hedeleg; | |
1c1c060a | 1062 | |
ec352d0c | 1063 | if (env->two_stage_lookup && write_tval) { |
9034e90a AF |
1064 | /* |
1065 | * If we are writing a guest virtual address to stval, set | |
1066 | * this to 1. If we are trapping to VS we will set this to 0 | |
1067 | * later. | |
1068 | */ | |
1069 | env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 1); | |
1070 | } else { | |
1071 | /* For other HS-mode traps, we set this to 0. */ | |
1072 | env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0); | |
1073 | } | |
1074 | ||
50d16087 | 1075 | if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1)) { |
84b1c04b | 1076 | /* Trap to VS mode */ |
c5969a3a RK |
1077 | /* |
1078 | * See if we need to adjust cause. Yes if its VS mode interrupt | |
1079 | * no if hypervisor has delegated one of hs mode's interrupt | |
1080 | */ | |
1081 | if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || | |
84b1c04b | 1082 | cause == IRQ_VS_EXT) { |
c5969a3a | 1083 | cause = cause - 1; |
84b1c04b | 1084 | } |
9034e90a | 1085 | env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0); |
5eb9e782 AF |
1086 | } else if (riscv_cpu_virt_enabled(env)) { |
1087 | /* Trap into HS mode, from virt */ | |
1088 | riscv_cpu_swap_hypervisor_regs(env); | |
f2d5850f | 1089 | env->hstatus = set_field(env->hstatus, HSTATUS_SPVP, |
ace54453 | 1090 | env->priv); |
5eb9e782 AF |
1091 | env->hstatus = set_field(env->hstatus, HSTATUS_SPV, |
1092 | riscv_cpu_virt_enabled(env)); | |
1093 | ||
30675539 AF |
1094 | htval = env->guest_phys_fault_addr; |
1095 | ||
5eb9e782 | 1096 | riscv_cpu_set_virt_enabled(env, 0); |
5eb9e782 AF |
1097 | } else { |
1098 | /* Trap into HS mode */ | |
ec352d0c | 1099 | env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false); |
30675539 | 1100 | htval = env->guest_phys_fault_addr; |
5eb9e782 AF |
1101 | } |
1102 | } | |
1103 | ||
1104 | s = env->mstatus; | |
1a9540d1 | 1105 | s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); |
0c3e702a MC |
1106 | s = set_field(s, MSTATUS_SPP, env->priv); |
1107 | s = set_field(s, MSTATUS_SIE, 0); | |
c7b95171 | 1108 | env->mstatus = s; |
16fdb8ff | 1109 | env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1)); |
acbbb94e | 1110 | env->sepc = env->pc; |
ac12b601 | 1111 | env->stval = tval; |
30675539 | 1112 | env->htval = htval; |
acbbb94e MC |
1113 | env->pc = (env->stvec >> 2 << 2) + |
1114 | ((async && (env->stvec & 3) == 1) ? cause * 4 : 0); | |
fb738839 | 1115 | riscv_cpu_set_mode(env, PRV_S); |
0c3e702a | 1116 | } else { |
acbbb94e | 1117 | /* handle the trap in M-mode */ |
5eb9e782 AF |
1118 | if (riscv_has_ext(env, RVH)) { |
1119 | if (riscv_cpu_virt_enabled(env)) { | |
1120 | riscv_cpu_swap_hypervisor_regs(env); | |
1121 | } | |
1122 | env->mstatus = set_field(env->mstatus, MSTATUS_MPV, | |
284d697c | 1123 | riscv_cpu_virt_enabled(env)); |
9034e90a AF |
1124 | if (riscv_cpu_virt_enabled(env) && tval) { |
1125 | env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1); | |
1126 | } | |
5eb9e782 | 1127 | |
30675539 AF |
1128 | mtval2 = env->guest_phys_fault_addr; |
1129 | ||
5eb9e782 AF |
1130 | /* Trapping to M mode, virt is disabled */ |
1131 | riscv_cpu_set_virt_enabled(env, 0); | |
5eb9e782 AF |
1132 | } |
1133 | ||
1134 | s = env->mstatus; | |
1a9540d1 | 1135 | s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); |
0c3e702a MC |
1136 | s = set_field(s, MSTATUS_MPP, env->priv); |
1137 | s = set_field(s, MSTATUS_MIE, 0); | |
c7b95171 | 1138 | env->mstatus = s; |
acbbb94e MC |
1139 | env->mcause = cause | ~(((target_ulong)-1) >> async); |
1140 | env->mepc = env->pc; | |
ac12b601 | 1141 | env->mtval = tval; |
30675539 | 1142 | env->mtval2 = mtval2; |
acbbb94e MC |
1143 | env->pc = (env->mtvec >> 2 << 2) + |
1144 | ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); | |
fb738839 | 1145 | riscv_cpu_set_mode(env, PRV_M); |
0c3e702a | 1146 | } |
d9360e96 MC |
1147 | |
1148 | /* NOTE: it is not necessary to yield load reservations here. It is only | |
1149 | * necessary for an SC from "another hart" to cause a load reservation | |
1150 | * to be yielded. Refer to the memory consistency model section of the | |
1151 | * RISC-V ISA Specification. | |
1152 | */ | |
1153 | ||
ec352d0c | 1154 | env->two_stage_lookup = false; |
0c3e702a | 1155 | #endif |
330d2ae3 | 1156 | cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */ |
0c3e702a | 1157 | } |