]> git.proxmox.com Git - mirror_qemu.git/blame - target/riscv/cpu_helper.c
projects / mirror_qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
target/riscv: Separate priv from mmu_idx
[mirror_qemu.git] / target / riscv / cpu_helper.c
CommitLineData
0c3e702a 1/*
df354dd4 2 * RISC-V CPU helpers for qemu.
0c3e702a
MC		 3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "qemu/osdep.h"
21#include "qemu/log.h"
7ec5d303 22#include "qemu/main-loop.h"
0c3e702a 23#include "cpu.h"
892320fa 24#include "pmu.h"
0c3e702a 25#include "exec/exec-all.h"
8e2aa21b 26#include "instmap.h"
dcb32f1d 27#include "tcg/tcg-op.h"
929f0a7f 28#include "trace.h"
6b5fe137 29#include "semihosting/common-semi.h"
2c9d7471 30#include "sysemu/cpu-timers.h"
892320fa 31#include "cpu_bits.h"
2c9d7471 32#include "debug.h"
0c3e702a
MC		 33
34int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
35{
36#ifdef CONFIG_USER_ONLY
37 return 0;
38#else
39 return env->priv;
40#endif
41}
42
53677acf
RH		 43void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
44 target_ulong *cs_base, uint32_t *pflags)
45{
b4a99d40
FC		 46 CPUState *cs = env_cpu(env);
47 RISCVCPU *cpu = RISCV_CPU(cs);
25f3ddff 48 RISCVExtStatus fs, vs;
53677acf
RH		 49 uint32_t flags = 0;
50
8c796f1a 51 *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
53677acf
RH		 52 *cs_base = 0;
53
3f4a5a53 54 if (cpu->cfg.ext_zve32f) {
a689a82b
FC		 55 /*
56 * If env->vl equals to VLMAX, we can use generic vector operation
57 * expanders (GVEC) to accerlate the vector operations.
58 * However, as LMUL could be a fractional number. The maximum
59 * vector size can be operated might be less than 8 bytes,
60 * which is not supported by GVEC. So we set vl_eq_vlmax flag to true
61 * only when maxsz >= 8 bytes.
62 */
718942ae 63 uint32_t vlmax = vext_get_vlmax(cpu, env->vtype);
a689a82b
FC		 64 uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW);
65 uint32_t maxsz = vlmax << sew;
66 bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) &&
67 (maxsz >= 8);
d96a271a 68 flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill);
a689a82b 69 flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew);
53677acf 70 flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
c45eff30 71 FIELD_EX64(env->vtype, VTYPE, VLMUL));
53677acf 72 flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
f1eed927 73 flags = FIELD_DP32(flags, TB_FLAGS, VTA,
c45eff30 74 FIELD_EX64(env->vtype, VTYPE, VTA));
355d5584 75 flags = FIELD_DP32(flags, TB_FLAGS, VMA,
c45eff30 76 FIELD_EX64(env->vtype, VTYPE, VMA));
4acaa133 77 flags = FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart == 0);
53677acf
RH		 78 } else {
79 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
80 }
81
82#ifdef CONFIG_USER_ONLY
25f3ddff
RH		 83 fs = EXT_STATUS_DIRTY;
84 vs = EXT_STATUS_DIRTY;
53677acf 85#else
47debc72
FW		 86 flags = FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv);
87
53677acf 88 flags |= cpu_mmu_index(env, 0);
25f3ddff
RH		 89 fs = get_field(env->mstatus, MSTATUS_FS);
90 vs = get_field(env->mstatus, MSTATUS_VS);
61b4b69d 91
53677acf
RH		 92 if (riscv_has_ext(env, RVH)) {
93 if (env->priv == PRV_M ||
38256529
WL		 94 (env->priv == PRV_S && !env->virt_enabled) ||
95 (env->priv == PRV_U && !env->virt_enabled &&
c45eff30 96 get_field(env->hstatus, HSTATUS_HU))) {
53677acf
RH		 97 flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
98 }
99
25f3ddff
RH		 100 if (env->virt_enabled) {
101 flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1);
102 /*
103 * Merge DISABLED and !DIRTY states using MIN.
104 * We will set both fields when dirtying.
105 */
106 fs = MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS));
107 vs = MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS));
108 }
53677acf 109 }
cdfb2905 110 if (cpu->cfg.debug && !icount_enabled()) {
577f0286 111 flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled);
2c9d7471 112 }
53677acf
RH		 113#endif
114
25f3ddff
RH		 115 flags = FIELD_DP32(flags, TB_FLAGS, FS, fs);
116 flags = FIELD_DP32(flags, TB_FLAGS, VS, vs);
440544e1 117 flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
4208dc7e
LZ		 118 if (env->cur_pmmask < (env->xl == MXL_RV32 ? UINT32_MAX : UINT64_MAX)) {
119 flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1);
120 }
121 if (env->cur_pmbase != 0) {
122 flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1);
123 }
92371bd9 124
53677acf
RH		 125 *pflags = flags;
126}
127
40bfa5f6
LZ		 128void riscv_cpu_update_mask(CPURISCVState *env)
129{
130 target_ulong mask = -1, base = 0;
131 /*
132 * TODO: Current RVJ spec does not specify
133 * how the extension interacts with XLEN.
134 */
135#ifndef CONFIG_USER_ONLY
136 if (riscv_has_ext(env, RVJ)) {
137 switch (env->priv) {
138 case PRV_M:
139 if (env->mmte & M_PM_ENABLE) {
140 mask = env->mpmmask;
141 base = env->mpmbase;
142 }
143 break;
144 case PRV_S:
145 if (env->mmte & S_PM_ENABLE) {
146 mask = env->spmmask;
147 base = env->spmbase;
148 }
149 break;
150 case PRV_U:
151 if (env->mmte & U_PM_ENABLE) {
152 mask = env->upmmask;
153 base = env->upmbase;
154 }
155 break;
156 default:
157 g_assert_not_reached();
158 }
159 }
160#endif
161 if (env->xl == MXL_RV32) {
162 env->cur_pmmask = mask & UINT32_MAX;
163 env->cur_pmbase = base & UINT32_MAX;
164 } else {
165 env->cur_pmmask = mask;
166 env->cur_pmbase = base;
167 }
168}
169
0c3e702a 170#ifndef CONFIG_USER_ONLY
43dc93af
AP		 171
172/*
173 * The HS-mode is allowed to configure priority only for the
174 * following VS-mode local interrupts:
175 *
176 * 0 (Reserved interrupt, reads as zero)
177 * 1 Supervisor software interrupt
178 * 4 (Reserved interrupt, reads as zero)
179 * 5 Supervisor timer interrupt
180 * 8 (Reserved interrupt, reads as zero)
181 * 13 (Reserved interrupt)
182 * 14 "
183 * 15 "
184 * 16 "
43577499
AP		 185 * 17 "
186 * 18 "
187 * 19 "
188 * 20 "
189 * 21 "
43dc93af 190 * 22 "
43577499 191 * 23 "
43dc93af
AP		 192 */
193
194static const int hviprio_index2irq[] = {
43577499 195 0, 1, 4, 5, 8, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 };
43dc93af
AP		 196static const int hviprio_index2rdzero[] = {
197 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
198
199int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero)
0c3e702a 200{
43dc93af
AP		 201 if (index < 0 || ARRAY_SIZE(hviprio_index2irq) <= index) {
202 return -EINVAL;
203 }
3ef10a09 204
43dc93af
AP		 205 if (out_irq) {
206 *out_irq = hviprio_index2irq[index];
207 }
3ef10a09 208
43dc93af
AP		 209 if (out_rdzero) {
210 *out_rdzero = hviprio_index2rdzero[index];
211 }
cd032fe7 212
43dc93af
AP		 213 return 0;
214}
3ef10a09 215
43dc93af
AP		 216/*
217 * Default priorities of local interrupts are defined in the
218 * RISC-V Advanced Interrupt Architecture specification.
219 *
220 * ----------------------------------------------------------------
221 * Default |
222 * Priority | Major Interrupt Numbers
223 * ----------------------------------------------------------------
43577499
AP		 224 * Highest | 47, 23, 46, 45, 22, 44,
225 * | 43, 21, 42, 41, 20, 40
43dc93af
AP		 226 * |
227 * | 11 (0b), 3 (03), 7 (07)
228 * | 9 (09), 1 (01), 5 (05)
229 * | 12 (0c)
230 * | 10 (0a), 2 (02), 6 (06)
231 * |
43577499
AP		 232 * | 39, 19, 38, 37, 18, 36,
233 * Lowest | 35, 17, 34, 33, 16, 32
43dc93af
AP		 234 * ----------------------------------------------------------------
235 */
236static const uint8_t default_iprio[64] = {
c45eff30
WL		 237 /* Custom interrupts 48 to 63 */
238 [63] = IPRIO_MMAXIPRIO,
239 [62] = IPRIO_MMAXIPRIO,
240 [61] = IPRIO_MMAXIPRIO,
241 [60] = IPRIO_MMAXIPRIO,
242 [59] = IPRIO_MMAXIPRIO,
243 [58] = IPRIO_MMAXIPRIO,
244 [57] = IPRIO_MMAXIPRIO,
245 [56] = IPRIO_MMAXIPRIO,
246 [55] = IPRIO_MMAXIPRIO,
247 [54] = IPRIO_MMAXIPRIO,
248 [53] = IPRIO_MMAXIPRIO,
249 [52] = IPRIO_MMAXIPRIO,
250 [51] = IPRIO_MMAXIPRIO,
251 [50] = IPRIO_MMAXIPRIO,
252 [49] = IPRIO_MMAXIPRIO,
253 [48] = IPRIO_MMAXIPRIO,
254
255 /* Custom interrupts 24 to 31 */
256 [31] = IPRIO_MMAXIPRIO,
257 [30] = IPRIO_MMAXIPRIO,
258 [29] = IPRIO_MMAXIPRIO,
259 [28] = IPRIO_MMAXIPRIO,
260 [27] = IPRIO_MMAXIPRIO,
261 [26] = IPRIO_MMAXIPRIO,
262 [25] = IPRIO_MMAXIPRIO,
263 [24] = IPRIO_MMAXIPRIO,
264
265 [47] = IPRIO_DEFAULT_UPPER,
266 [23] = IPRIO_DEFAULT_UPPER + 1,
267 [46] = IPRIO_DEFAULT_UPPER + 2,
268 [45] = IPRIO_DEFAULT_UPPER + 3,
269 [22] = IPRIO_DEFAULT_UPPER + 4,
270 [44] = IPRIO_DEFAULT_UPPER + 5,
271
272 [43] = IPRIO_DEFAULT_UPPER + 6,
273 [21] = IPRIO_DEFAULT_UPPER + 7,
274 [42] = IPRIO_DEFAULT_UPPER + 8,
275 [41] = IPRIO_DEFAULT_UPPER + 9,
276 [20] = IPRIO_DEFAULT_UPPER + 10,
277 [40] = IPRIO_DEFAULT_UPPER + 11,
278
279 [11] = IPRIO_DEFAULT_M,
280 [3] = IPRIO_DEFAULT_M + 1,
281 [7] = IPRIO_DEFAULT_M + 2,
282
283 [9] = IPRIO_DEFAULT_S,
284 [1] = IPRIO_DEFAULT_S + 1,
285 [5] = IPRIO_DEFAULT_S + 2,
286
287 [12] = IPRIO_DEFAULT_SGEXT,
288
289 [10] = IPRIO_DEFAULT_VS,
290 [2] = IPRIO_DEFAULT_VS + 1,
291 [6] = IPRIO_DEFAULT_VS + 2,
292
293 [39] = IPRIO_DEFAULT_LOWER,
294 [19] = IPRIO_DEFAULT_LOWER + 1,
295 [38] = IPRIO_DEFAULT_LOWER + 2,
296 [37] = IPRIO_DEFAULT_LOWER + 3,
297 [18] = IPRIO_DEFAULT_LOWER + 4,
298 [36] = IPRIO_DEFAULT_LOWER + 5,
299
300 [35] = IPRIO_DEFAULT_LOWER + 6,
301 [17] = IPRIO_DEFAULT_LOWER + 7,
302 [34] = IPRIO_DEFAULT_LOWER + 8,
303 [33] = IPRIO_DEFAULT_LOWER + 9,
304 [16] = IPRIO_DEFAULT_LOWER + 10,
305 [32] = IPRIO_DEFAULT_LOWER + 11,
43dc93af
AP		 306};
307
308uint8_t riscv_cpu_default_priority(int irq)
309{
310 if (irq < 0 || irq > 63) {
311 return IPRIO_MMAXIPRIO;
312 }
313
314 return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO;
315};
316
317static int riscv_cpu_pending_to_irq(CPURISCVState *env,
318 int extirq, unsigned int extirq_def_prio,
319 uint64_t pending, uint8_t *iprio)
320{
321 int irq, best_irq = RISCV_EXCP_NONE;
322 unsigned int prio, best_prio = UINT_MAX;
323
324 if (!pending) {
325 return RISCV_EXCP_NONE;
326 }
327
328 irq = ctz64(pending);
9c33e08b
WL		 329 if (!((extirq == IRQ_M_EXT) ? riscv_cpu_cfg(env)->ext_smaia :
330 riscv_cpu_cfg(env)->ext_ssaia)) {
43dc93af
AP		 331 return irq;
332 }
333
334 pending = pending >> irq;
335 while (pending) {
336 prio = iprio[irq];
337 if (!prio) {
338 if (irq == extirq) {
339 prio = extirq_def_prio;
340 } else {
341 prio = (riscv_cpu_default_priority(irq) < extirq_def_prio) ?
342 1 : IPRIO_MMAXIPRIO;
343 }
344 }
345 if ((pending & 0x1) && (prio <= best_prio)) {
346 best_irq = irq;
347 best_prio = prio;
348 }
349 irq++;
350 pending = pending >> 1;
351 }
352
353 return best_irq;
354}
355
8f42415f 356uint64_t riscv_cpu_all_pending(CPURISCVState *env)
43dc93af
AP		 357{
358 uint32_t gein = get_field(env->hstatus, HSTATUS_VGEIN);
359 uint64_t vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
3ec0fe18 360 uint64_t vstip = (env->vstime_irq) ? MIP_VSTIP : 0;
43dc93af 361
3ec0fe18 362 return (env->mip | vsgein | vstip) & env->mie;
43dc93af
AP		 363}
364
365int riscv_cpu_mirq_pending(CPURISCVState *env)
366{
367 uint64_t irqs = riscv_cpu_all_pending(env) & ~env->mideleg &
368 ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
369
370 return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M,
371 irqs, env->miprio);
372}
373
374int riscv_cpu_sirq_pending(CPURISCVState *env)
375{
376 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg &
377 ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
378
379 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
380 irqs, env->siprio);
381}
382
383int riscv_cpu_vsirq_pending(CPURISCVState *env)
384{
385 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg &
386 (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
387
388 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
389 irqs >> 1, env->hviprio);
390}
391
392static int riscv_cpu_local_irq_pending(CPURISCVState *env)
393{
394 int virq;
395 uint64_t irqs, pending, mie, hsie, vsie;
396
397 /* Determine interrupt enable state of all privilege modes */
38256529 398 if (env->virt_enabled) {
43dc93af
AP		 399 mie = 1;
400 hsie = 1;
401 vsie = (env->priv < PRV_S) ||
402 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE));
0c3e702a 403 } else {
43dc93af
AP		 404 mie = (env->priv < PRV_M) ||
405 (env->priv == PRV_M && get_field(env->mstatus, MSTATUS_MIE));
406 hsie = (env->priv < PRV_S) ||
407 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE));
408 vsie = 0;
409 }
410
411 /* Determine all pending interrupts */
412 pending = riscv_cpu_all_pending(env);
413
414 /* Check M-mode interrupts */
415 irqs = pending & ~env->mideleg & -mie;
416 if (irqs) {
417 return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M,
418 irqs, env->miprio);
419 }
420
421 /* Check HS-mode interrupts */
422 irqs = pending & env->mideleg & ~env->hideleg & -hsie;
423 if (irqs) {
424 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
425 irqs, env->siprio);
0c3e702a 426 }
43dc93af
AP		 427
428 /* Check VS-mode interrupts */
429 irqs = pending & env->mideleg & env->hideleg & -vsie;
430 if (irqs) {
431 virq = riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
432 irqs >> 1, env->hviprio);
433 return (virq <= 0) ? virq : virq + 1;
434 }
435
436 /* Indicate no pending interrupt */
437 return RISCV_EXCP_NONE;
0c3e702a 438}
0c3e702a
MC		 439
440bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
441{
0c3e702a
MC		 442 if (interrupt_request & CPU_INTERRUPT_HARD) {
443 RISCVCPU *cpu = RISCV_CPU(cs);
444 CPURISCVState *env = &cpu->env;
efbdbc26 445 int interruptno = riscv_cpu_local_irq_pending(env);
0c3e702a
MC		 446 if (interruptno >= 0) {
447 cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno;
448 riscv_cpu_do_interrupt(cs);
449 return true;
450 }
451 }
0c3e702a
MC		 452 return false;
453}
454
b345b480
AF		 455/* Return true is floating point support is currently enabled */
456bool riscv_cpu_fp_enabled(CPURISCVState *env)
457{
458 if (env->mstatus & MSTATUS_FS) {
38256529 459 if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_FS)) {
29409c1d
AF		 460 return false;
461 }
b345b480
AF		 462 return true;
463 }
464
465 return false;
466}
467
61b4b69d
LZ		 468/* Return true is vector support is currently enabled */
469bool riscv_cpu_vector_enabled(CPURISCVState *env)
470{
471 if (env->mstatus & MSTATUS_VS) {
38256529 472 if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_VS)) {
61b4b69d
LZ		 473 return false;
474 }
475 return true;
476 }
477
478 return false;
479}
480
66e594f2
AF		 481void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
482{
c163b3ba 483 uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM |
284d697c 484 MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE |
61b4b69d 485 MSTATUS64_UXL | MSTATUS_VS;
c163b3ba
WL		 486
487 if (riscv_has_ext(env, RVF)) {
488 mstatus_mask |= MSTATUS_FS;
489 }
38256529 490 bool current_virt = env->virt_enabled;
66e594f2
AF		 491
492 g_assert(riscv_has_ext(env, RVH));
493
66e594f2
AF		 494 if (current_virt) {
495 /* Current V=1 and we are about to change to V=0 */
496 env->vsstatus = env->mstatus & mstatus_mask;
497 env->mstatus &= ~mstatus_mask;
498 env->mstatus |= env->mstatus_hs;
499
500 env->vstvec = env->stvec;
501 env->stvec = env->stvec_hs;
502
503 env->vsscratch = env->sscratch;
504 env->sscratch = env->sscratch_hs;
505
506 env->vsepc = env->sepc;
507 env->sepc = env->sepc_hs;
508
509 env->vscause = env->scause;
510 env->scause = env->scause_hs;
511
ac12b601
AP		 512 env->vstval = env->stval;
513 env->stval = env->stval_hs;
66e594f2
AF		 514
515 env->vsatp = env->satp;
516 env->satp = env->satp_hs;
517 } else {
518 /* Current V=0 and we are about to change to V=1 */
519 env->mstatus_hs = env->mstatus & mstatus_mask;
520 env->mstatus &= ~mstatus_mask;
521 env->mstatus |= env->vsstatus;
522
523 env->stvec_hs = env->stvec;
524 env->stvec = env->vstvec;
525
526 env->sscratch_hs = env->sscratch;
527 env->sscratch = env->vsscratch;
528
529 env->sepc_hs = env->sepc;
530 env->sepc = env->vsepc;
531
532 env->scause_hs = env->scause;
533 env->scause = env->vscause;
534
ac12b601
AP		 535 env->stval_hs = env->stval;
536 env->stval = env->vstval;
66e594f2
AF		 537
538 env->satp_hs = env->satp;
539 env->satp = env->vsatp;
540 }
541}
542
cd032fe7
AP		 543target_ulong riscv_cpu_get_geilen(CPURISCVState *env)
544{
545 if (!riscv_has_ext(env, RVH)) {
546 return 0;
547 }
548
549 return env->geilen;
550}
551
552void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen)
553{
554 if (!riscv_has_ext(env, RVH)) {
555 return;
556 }
557
558 if (geilen > (TARGET_LONG_BITS - 1)) {
559 return;
560 }
561
562 env->geilen = geilen;
563}
564
c43732f5 565/* This function can only be called to set virt when RVH is enabled */
ef6bb7b6
AF		 566void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
567{
eccc5a12 568 /* Flush the TLB on all virt mode changes. */
b3c5077b 569 if (env->virt_enabled != enable) {
eccc5a12
AF		 570 tlb_flush(env_cpu(env));
571 }
572
b3c5077b 573 env->virt_enabled = enable;
02d9565b
AP		 574
575 if (enable) {
576 /*
577 * The guest external interrupts from an interrupt controller are
578 * delivered only when the Guest/VM is running (i.e. V=1). This means
579 * any guest external interrupt which is triggered while the Guest/VM
580 * is not running (i.e. V=0) will be missed on QEMU resulting in guest
581 * with sluggish response to serial console input and other I/O events.
582 *
583 * To solve this, we check and inject interrupt after setting V=1.
584 */
bbb9fc25 585 riscv_cpu_update_mip(env, 0, 0);
02d9565b 586 }
ef6bb7b6
AF		 587}
588
1c1c060a 589bool riscv_cpu_two_stage_lookup(int mmu_idx)
5a894dd7 590{
1c1c060a 591 return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK;
5a894dd7
AF		 592}
593
d028ac75 594int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts)
e3e7039c
MC		 595{
596 CPURISCVState *env = &cpu->env;
597 if (env->miclaim & interrupts) {
598 return -1;
599 } else {
600 env->miclaim |= interrupts;
601 return 0;
602 }
603}
604
bbb9fc25
WL		 605uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask,
606 uint64_t value)
df354dd4 607{
bbb9fc25 608 CPUState *cs = env_cpu(env);
3ec0fe18 609 uint64_t gein, vsgein = 0, vstip = 0, old = env->mip;
7ec5d303 610
38256529 611 if (env->virt_enabled) {
cd032fe7
AP		 612 gein = get_field(env->hstatus, HSTATUS_VGEIN);
613 vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
614 }
615
3ec0fe18
AP		 616 vstip = env->vstime_irq ? MIP_VSTIP : 0;
617
b3eb5b86 618 QEMU_IOTHREAD_LOCK_GUARD();
df354dd4 619
7ec5d303 620 env->mip = (env->mip & ~mask) | (value & mask);
df354dd4 621
3ec0fe18 622 if (env->mip | vsgein | vstip) {
7ec5d303
AF		 623 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
624 } else {
625 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
626 }
0a01f2ee 627
df354dd4
MC		 628 return old;
629}
630
e2f01f3c
FC		 631void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *),
632 void *arg)
c6957248
AP		 633{
634 env->rdtime_fn = fn;
a47ef6e9 635 env->rdtime_fn_arg = arg;
c6957248
AP		 636}
637
69077dd6
AP		 638void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
639 int (*rmw_fn)(void *arg,
640 target_ulong reg,
641 target_ulong *val,
642 target_ulong new_val,
643 target_ulong write_mask),
644 void *rmw_fn_arg)
645{
646 if (priv <= PRV_M) {
647 env->aia_ireg_rmw_fn[priv] = rmw_fn;
648 env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg;
649 }
650}
651
fb738839 652void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
df354dd4 653{
0c98ccef
WL		 654 g_assert(newpriv <= PRV_M && newpriv != PRV_RESERVED);
655
5a4ae64c
LZ		 656 if (icount_enabled() && newpriv != env->priv) {
657 riscv_itrigger_update_priv(env);
658 }
df354dd4
MC		 659 /* tlb_flush is unnecessary as mode is contained in mmu_idx */
660 env->priv = newpriv;
440544e1 661 env->xl = cpu_recompute_xl(env);
40bfa5f6 662 riscv_cpu_update_mask(env);
c13b169f
JS		 663
664 /*
665 * Clear the load reservation - otherwise a reservation placed in one
666 * context/process can be used by another, resulting in an SC succeeding
667 * incorrectly. Version 2.2 of the ISA specification explicitly requires
668 * this behaviour, while later revisions say that the kernel "should" use
669 * an SC instruction to force the yielding of a load reservation on a
670 * preemptive context switch. As a result, do both.
671 */
672 env->load_res = -1;
df354dd4
MC		 673}
674
b297129a
JS		 675/*
676 * get_physical_address_pmp - check PMP permission for this physical address
677 *
678 * Match the PMP region and check permission for this physical address and it's
679 * TLB page. Returns 0 if the permission checking was successful
680 *
681 * @env: CPURISCVState
682 * @prot: The returned protection attributes
683 * @tlb_size: TLB page size containing addr. It could be modified after PMP
684 * permission checking. NULL if not set TLB page for addr.
685 * @addr: The physical address to be checked permission
686 * @access_type: The type of MMU access
687 * @mode: Indicates current privilege level.
688 */
689static int get_physical_address_pmp(CPURISCVState *env, int *prot,
690 target_ulong *tlb_size, hwaddr addr,
691 int size, MMUAccessType access_type,
692 int mode)
693{
694 pmp_priv_t pmp_priv;
824cac68 695 int pmp_index = -1;
b297129a 696
3fe40ef5 697 if (!riscv_cpu_cfg(env)->pmp) {
b297129a
JS		 698 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
699 return TRANSLATE_SUCCESS;
700 }
701
824cac68
LZ		 702 pmp_index = pmp_hart_has_privs(env, addr, size, 1 << access_type,
703 &pmp_priv, mode);
704 if (pmp_index < 0) {
b297129a
JS		 705 *prot = 0;
706 return TRANSLATE_PMP_FAIL;
707 }
708
709 *prot = pmp_priv_to_page_prot(pmp_priv);
824cac68
LZ		 710 if ((tlb_size != NULL) && pmp_index != MAX_RISCV_PMPS) {
711 target_ulong tlb_sa = addr & ~(TARGET_PAGE_SIZE - 1);
712 target_ulong tlb_ea = tlb_sa + TARGET_PAGE_SIZE - 1;
713
714 *tlb_size = pmp_get_tlb_size(env, pmp_index, tlb_sa, tlb_ea);
b297129a
JS		 715 }
716
717 return TRANSLATE_SUCCESS;
718}
719
3b57254d
WL		 720/*
721 * get_physical_address - get the physical address for this virtual address
0c3e702a
MC		 722 *
723 * Do a page table walk to obtain the physical address corresponding to a
724 * virtual address. Returns 0 if the translation was successful
725 *
726 * Adapted from Spike's mmu_t::translate and mmu_t::walk
727 *
1448689c
AF		 728 * @env: CPURISCVState
729 * @physical: This will be set to the calculated physical address
730 * @prot: The returned protection attributes
77dff650 731 * @addr: The virtual address or guest physical address to be translated
33a9a57d
YJ		 732 * @fault_pte_addr: If not NULL, this will be set to fault pte address
733 * when a error occurs on pte address translation.
734 * This will already be shifted to match htval.
1448689c
AF		 735 * @access_type: The type of MMU access
736 * @mmu_idx: Indicates current privilege level
737 * @first_stage: Are we in first stage translation?
738 * Second stage is used for hypervisor guest translation
36a18664 739 * @two_stage: Are we going to perform two stage translation
11c27c6d 740 * @is_debug: Is this access from a debugger or the monitor?
0c3e702a
MC		 741 */
742static int get_physical_address(CPURISCVState *env, hwaddr *physical,
77dff650 743 int *prot, vaddr addr,
33a9a57d 744 target_ulong *fault_pte_addr,
1448689c 745 int access_type, int mmu_idx,
11c27c6d
JF		 746 bool first_stage, bool two_stage,
747 bool is_debug)
0c3e702a 748{
3b57254d
WL		 749 /*
750 * NOTE: the env->pc value visible here will not be
0c3e702a 751 * correct, but the value visible to the exception handler
3b57254d
WL		 752 * (riscv_cpu_do_interrupt) is correct
753 */
aacb578f
PD		 754 MemTxResult res;
755 MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
47debc72 756 int mode = env->priv;
36a18664 757 bool use_background = false;
05e6ca5e 758 hwaddr ppn;
2bacb224
WL		 759 int napot_bits = 0;
760 target_ulong napot_mask;
0c3e702a 761
36a18664
AF		 762 /*
763 * Check if we should use the background registers for the two
764 * stage translation. We don't need to check if we actually need
765 * two stage translation as that happened before this function
766 * was called. Background registers will be used if the guest has
767 * forced a two stage translation to be on (in HS or M mode).
768 */
38256529 769 if (!env->virt_enabled && two_stage) {
29b3361b
AF		 770 use_background = true;
771 }
772
3b57254d
WL		 773 /*
774 * MPRV does not affect the virtual-machine load/store
775 * instructions, HLV, HLVX, and HSV.
776 */
90ec1cff
GK		 777 if (riscv_cpu_two_stage_lookup(mmu_idx)) {
778 mode = get_field(env->hstatus, HSTATUS_SPVP);
779 } else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
0c3e702a
MC		 780 if (get_field(env->mstatus, MSTATUS_MPRV)) {
781 mode = get_field(env->mstatus, MSTATUS_MPP);
782 }
783 }
784
36a18664 785 if (first_stage == false) {
3b57254d
WL		 786 /*
787 * We are in stage 2 translation, this is similar to stage 1.
788 * Stage 2 is always taken as U-mode
789 */
36a18664
AF		 790 mode = PRV_U;
791 }
792
dcf654a3 793 if (mode == PRV_M || !riscv_cpu_cfg(env)->mmu) {
0c3e702a
MC		 794 *physical = addr;
795 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
796 return TRANSLATE_SUCCESS;
797 }
798
799 *prot = 0;
800
ddf78132 801 hwaddr base;
36a18664
AF		 802 int levels, ptidxbits, ptesize, vm, sum, mxr, widened;
803
804 if (first_stage == true) {
805 mxr = get_field(env->mstatus, MSTATUS_MXR);
806 } else {
807 mxr = get_field(env->vsstatus, MSTATUS_MXR);
808 }
0c3e702a 809
1a9540d1
AF		 810 if (first_stage == true) {
811 if (use_background) {
db23e5d9 812 if (riscv_cpu_mxl(env) == MXL_RV32) {
419ddf00
AF		 813 base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT;
814 vm = get_field(env->vsatp, SATP32_MODE);
815 } else {
816 base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT;
817 vm = get_field(env->vsatp, SATP64_MODE);
818 }
36a18664 819 } else {
db23e5d9 820 if (riscv_cpu_mxl(env) == MXL_RV32) {
419ddf00
AF		 821 base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
822 vm = get_field(env->satp, SATP32_MODE);
823 } else {
824 base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT;
825 vm = get_field(env->satp, SATP64_MODE);
826 }
0c3e702a 827 }
36a18664 828 widened = 0;
1a9540d1 829 } else {
db23e5d9 830 if (riscv_cpu_mxl(env) == MXL_RV32) {
994b6bb2
AF		 831 base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT;
832 vm = get_field(env->hgatp, SATP32_MODE);
833 } else {
834 base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT;
835 vm = get_field(env->hgatp, SATP64_MODE);
836 }
1a9540d1
AF		 837 widened = 2;
838 }
c63ca4ff 839 /* status.SUM will be ignored if execute on background */
11c27c6d 840 sum = get_field(env->mstatus, MSTATUS_SUM) || use_background || is_debug;
1a9540d1
AF		 841 switch (vm) {
842 case VM_1_10_SV32:
843 levels = 2; ptidxbits = 10; ptesize = 4; break;
844 case VM_1_10_SV39:
845 levels = 3; ptidxbits = 9; ptesize = 8; break;
846 case VM_1_10_SV48:
847 levels = 4; ptidxbits = 9; ptesize = 8; break;
848 case VM_1_10_SV57:
849 levels = 5; ptidxbits = 9; ptesize = 8; break;
850 case VM_1_10_MBARE:
851 *physical = addr;
852 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
853 return TRANSLATE_SUCCESS;
854 default:
855 g_assert_not_reached();
0c3e702a
MC		 856 }
857
3109cd98 858 CPUState *cs = env_cpu(env);
36a18664
AF		 859 int va_bits = PGSHIFT + levels * ptidxbits + widened;
860 target_ulong mask, masked_msbs;
861
862 if (TARGET_LONG_BITS > (va_bits - 1)) {
863 mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1;
864 } else {
865 mask = 0;
866 }
867 masked_msbs = (addr >> (va_bits - 1)) & mask;
868
0c3e702a
MC		 869 if (masked_msbs != 0 && masked_msbs != mask) {
870 return TRANSLATE_FAIL;
871 }
872
873 int ptshift = (levels - 1) * ptidxbits;
874 int i;
875
876#if !TCG_OVERSIZED_GUEST
877restart:
878#endif
879 for (i = 0; i < levels; i++, ptshift -= ptidxbits) {
36a18664
AF		 880 target_ulong idx;
881 if (i == 0) {
882 idx = (addr >> (PGSHIFT + ptshift)) &
883 ((1 << (ptidxbits + widened)) - 1);
884 } else {
885 idx = (addr >> (PGSHIFT + ptshift)) &
0c3e702a 886 ((1 << ptidxbits) - 1);
36a18664 887 }
0c3e702a
MC		 888
889 /* check that physical address of PTE is legal */
36a18664
AF		 890 hwaddr pte_addr;
891
892 if (two_stage && first_stage) {
38472890 893 int vbase_prot;
36a18664
AF		 894 hwaddr vbase;
895
896 /* Do the second stage translation on the base PTE address. */
88914473 897 int vbase_ret = get_physical_address(env, &vbase, &vbase_prot,
33a9a57d 898 base, NULL, MMU_DATA_LOAD,
11c27c6d
JF		 899 mmu_idx, false, true,
900 is_debug);
88914473
AF		 901
902 if (vbase_ret != TRANSLATE_SUCCESS) {
33a9a57d
YJ		 903 if (fault_pte_addr) {
904 *fault_pte_addr = (base + idx * ptesize) >> 2;
905 }
906 return TRANSLATE_G_STAGE_FAIL;
88914473 907 }
36a18664
AF		 908
909 pte_addr = vbase + idx * ptesize;
910 } else {
911 pte_addr = base + idx * ptesize;
912 }
1f447aec 913
b297129a
JS		 914 int pmp_prot;
915 int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr,
916 sizeof(target_ulong),
917 MMU_DATA_LOAD, PRV_S);
918 if (pmp_ret != TRANSLATE_SUCCESS) {
1f447aec
HA		 919 return TRANSLATE_PMP_FAIL;
920 }
aacb578f 921
f08c7ff3 922 target_ulong pte;
db23e5d9 923 if (riscv_cpu_mxl(env) == MXL_RV32) {
f08c7ff3
AF		 924 pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
925 } else {
926 pte = address_space_ldq(cs->as, pte_addr, attrs, &res);
927 }
928
aacb578f
PD		 929 if (res != MEMTX_OK) {
930 return TRANSLATE_FAIL;
931 }
932
7a6613da 933 bool pbmte = env->menvcfg & MENVCFG_PBMTE;
0af3f115 934 bool hade = env->menvcfg & MENVCFG_HADE;
7a6613da 935
38256529 936 if (first_stage && two_stage && env->virt_enabled) {
7a6613da 937 pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
0af3f115 938 hade = hade && (env->henvcfg & HENVCFG_HADE);
7a6613da
WL		 939 }
940
05e6ca5e
GR		 941 if (riscv_cpu_sxl(env) == MXL_RV32) {
942 ppn = pte >> PTE_PPN_SHIFT;
9c33e08b 943 } else if (pbmte || riscv_cpu_cfg(env)->ext_svnapot) {
05e6ca5e
GR		 944 ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT;
945 } else {
946 ppn = pte >> PTE_PPN_SHIFT;
947 if ((pte & ~(target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT) {
948 return TRANSLATE_FAIL;
949 }
950 }
0c3e702a 951
c3b03e58
MC		 952 if (!(pte & PTE_V)) {
953 /* Invalid PTE */
954 return TRANSLATE_FAIL;
7a6613da 955 } else if (!pbmte && (pte & PTE_PBMT)) {
bbce8ba8 956 return TRANSLATE_FAIL;
c3b03e58
MC		 957 } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
958 /* Inner PTE, continue walking */
bbce8ba8 959 if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) {
b6ecc63c
WL		 960 return TRANSLATE_FAIL;
961 }
0c3e702a 962 base = ppn << PGSHIFT;
c3b03e58
MC		 963 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
964 /* Reserved leaf PTE flags: PTE_W */
965 return TRANSLATE_FAIL;
966 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) {
967 /* Reserved leaf PTE flags: PTE_W + PTE_X */
968 return TRANSLATE_FAIL;
969 } else if ((pte & PTE_U) && ((mode != PRV_U) &&
970 (!sum || access_type == MMU_INST_FETCH))) {
971 /* User PTE flags when not U mode and mstatus.SUM is not set,
972 or the access type is an instruction fetch */
973 return TRANSLATE_FAIL;
974 } else if (!(pte & PTE_U) && (mode != PRV_S)) {
975 /* Supervisor PTE flags when not S mode */
976 return TRANSLATE_FAIL;
977 } else if (ppn & ((1ULL << ptshift) - 1)) {
978 /* Misaligned PPN */
979 return TRANSLATE_FAIL;
980 } else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) ||
981 ((pte & PTE_X) && mxr))) {
982 /* Read access check failed */
983 return TRANSLATE_FAIL;
984 } else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) {
985 /* Write access check failed */
986 return TRANSLATE_FAIL;
987 } else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) {
988 /* Fetch access check failed */
989 return TRANSLATE_FAIL;
0c3e702a
MC		 990 } else {
991 /* if necessary, set accessed and dirty bits. */
992 target_ulong updated_pte = pte | PTE_A |
993 (access_type == MMU_DATA_STORE ? PTE_D : 0);
994
995 /* Page table updates need to be atomic with MTTCG enabled */
996 if (updated_pte != pte) {
0af3f115
WL		 997 if (!hade) {
998 return TRANSLATE_FAIL;
999 }
1000
c3b03e58
MC		 1001 /*
1002 * - if accessed or dirty bits need updating, and the PTE is
1003 * in RAM, then we do so atomically with a compare and swap.
1004 * - if the PTE is in IO space or ROM, then it can't be updated
1005 * and we return TRANSLATE_FAIL.
1006 * - if the PTE changed by the time we went to update it, then
1007 * it is no longer valid and we must re-walk the page table.
1008 */
0c3e702a
MC		 1009 MemoryRegion *mr;
1010 hwaddr l = sizeof(target_ulong), addr1;
c45eff30
WL		 1011 mr = address_space_translate(cs->as, pte_addr, &addr1, &l,
1012 false, MEMTXATTRS_UNSPECIFIED);
c3b03e58 1013 if (memory_region_is_ram(mr)) {
0c3e702a
MC		 1014 target_ulong *pte_pa =
1015 qemu_map_ram_ptr(mr->ram_block, addr1);
1016#if TCG_OVERSIZED_GUEST
3b57254d
WL		 1017 /*
1018 * MTTCG is not enabled on oversized TCG guests so
1019 * page table updates do not need to be atomic
1020 */
0c3e702a
MC		 1021 *pte_pa = pte = updated_pte;
1022#else
1023 target_ulong old_pte =
d73415a3 1024 qatomic_cmpxchg(pte_pa, pte, updated_pte);
0c3e702a
MC		 1025 if (old_pte != pte) {
1026 goto restart;
1027 } else {
1028 pte = updated_pte;
1029 }
1030#endif
1031 } else {
3b57254d
WL		 1032 /*
1033 * misconfigured PTE in ROM (AD bits are not preset) or
1034 * PTE is in IO space and can't be updated atomically
1035 */
0c3e702a
MC		 1036 return TRANSLATE_FAIL;
1037 }
1038 }
1039
3b57254d
WL		 1040 /*
1041 * for superpage mappings, make a fake leaf PTE for the TLB's
1042 * benefit.
1043 */
0c3e702a 1044 target_ulong vpn = addr >> PGSHIFT;
2bacb224 1045
9c33e08b 1046 if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) {
2bacb224
WL		 1047 napot_bits = ctzl(ppn) + 1;
1048 if ((i != (levels - 1)) || (napot_bits != 4)) {
1049 return TRANSLATE_FAIL;
1050 }
1051 }
1052
1053 napot_mask = (1 << napot_bits) - 1;
1054 *physical = (((ppn & ~napot_mask) | (vpn & napot_mask) |
1055 (vpn & (((target_ulong)1 << ptshift) - 1))
1056 ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK);
0c3e702a 1057
c3b03e58
MC		 1058 /* set permissions on the TLB entry */
1059 if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
0c3e702a
MC		 1060 *prot |= PAGE_READ;
1061 }
628f0ec1 1062 if (pte & PTE_X) {
0c3e702a
MC		 1063 *prot |= PAGE_EXEC;
1064 }
3b57254d
WL		 1065 /*
1066 * add write permission on stores or if the page is already dirty,
1067 * so that we TLB miss on later writes to update the dirty bit
1068 */
0c3e702a 1069 if ((pte & PTE_W) &&
c45eff30 1070 (access_type == MMU_DATA_STORE || (pte & PTE_D))) {
0c3e702a
MC		 1071 *prot |= PAGE_WRITE;
1072 }
1073 return TRANSLATE_SUCCESS;
1074 }
1075 }
1076 return TRANSLATE_FAIL;
1077}
1078
1079static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
1448689c 1080 MMUAccessType access_type, bool pmp_violation,
8e2aa21b
AP		 1081 bool first_stage, bool two_stage,
1082 bool two_stage_indirect)
0c3e702a 1083{
3109cd98 1084 CPUState *cs = env_cpu(env);
994b6bb2 1085 int page_fault_exceptions, vm;
419ddf00
AF		 1086 uint64_t stap_mode;
1087
db23e5d9 1088 if (riscv_cpu_mxl(env) == MXL_RV32) {
419ddf00
AF		 1089 stap_mode = SATP32_MODE;
1090 } else {
1091 stap_mode = SATP64_MODE;
1092 }
994b6bb2 1093
1448689c 1094 if (first_stage) {
419ddf00 1095 vm = get_field(env->satp, stap_mode);
1448689c 1096 } else {
419ddf00 1097 vm = get_field(env->hgatp, stap_mode);
1448689c 1098 }
419ddf00 1099
994b6bb2
AF		 1100 page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation;
1101
0c3e702a
MC		 1102 switch (access_type) {
1103 case MMU_INST_FETCH:
38256529 1104 if (env->virt_enabled && !first_stage) {
b2ef6ab9
AF		 1105 cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
1106 } else {
1107 cs->exception_index = page_fault_exceptions ?
1108 RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT;
1109 }
0c3e702a
MC		 1110 break;
1111 case MMU_DATA_LOAD:
1c1c060a 1112 if (two_stage && !first_stage) {
b2ef6ab9
AF		 1113 cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
1114 } else {
1115 cs->exception_index = page_fault_exceptions ?
1116 RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT;
1117 }
0c3e702a
MC		 1118 break;
1119 case MMU_DATA_STORE:
1c1c060a 1120 if (two_stage && !first_stage) {
b2ef6ab9
AF		 1121 cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
1122 } else {
1123 cs->exception_index = page_fault_exceptions ?
246f8796
WL		 1124 RISCV_EXCP_STORE_PAGE_FAULT :
1125 RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
b2ef6ab9 1126 }
0c3e702a
MC		 1127 break;
1128 default:
1129 g_assert_not_reached();
1130 }
1131 env->badaddr = address;
ec352d0c 1132 env->two_stage_lookup = two_stage;
8e2aa21b 1133 env->two_stage_indirect_lookup = two_stage_indirect;
0c3e702a
MC		 1134}
1135
1136hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
1137{
1138 RISCVCPU *cpu = RISCV_CPU(cs);
36a18664 1139 CPURISCVState *env = &cpu->env;
0c3e702a
MC		 1140 hwaddr phys_addr;
1141 int prot;
1142 int mmu_idx = cpu_mmu_index(&cpu->env, false);
1143
33a9a57d 1144 if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx,
38256529 1145 true, env->virt_enabled, true)) {
0c3e702a
MC		 1146 return -1;
1147 }
36a18664 1148
38256529 1149 if (env->virt_enabled) {
33a9a57d 1150 if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL,
11c27c6d 1151 0, mmu_idx, false, true, true)) {
36a18664
AF		 1152 return -1;
1153 }
1154 }
1155
9ef82119 1156 return phys_addr & TARGET_PAGE_MASK;
0c3e702a
MC		 1157}
1158
37207e12
PD		 1159void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
1160 vaddr addr, unsigned size,
1161 MMUAccessType access_type,
1162 int mmu_idx, MemTxAttrs attrs,
1163 MemTxResult response, uintptr_t retaddr)
cbf58276
MC		 1164{
1165 RISCVCPU *cpu = RISCV_CPU(cs);
1166 CPURISCVState *env = &cpu->env;
1167
37207e12 1168 if (access_type == MMU_DATA_STORE) {
cbf58276 1169 cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
f9e580c1 1170 } else if (access_type == MMU_DATA_LOAD) {
cbf58276 1171 cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
f9e580c1
EB		 1172 } else {
1173 cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
cbf58276
MC		 1174 }
1175
1176 env->badaddr = addr;
38256529 1177 env->two_stage_lookup = env->virt_enabled ||
ec352d0c 1178 riscv_cpu_two_stage_lookup(mmu_idx);
8e2aa21b 1179 env->two_stage_indirect_lookup = false;
ac684717 1180 cpu_loop_exit_restore(cs, retaddr);
cbf58276
MC		 1181}
1182
0c3e702a
MC		 1183void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
1184 MMUAccessType access_type, int mmu_idx,
1185 uintptr_t retaddr)
1186{
1187 RISCVCPU *cpu = RISCV_CPU(cs);
1188 CPURISCVState *env = &cpu->env;
1189 switch (access_type) {
1190 case MMU_INST_FETCH:
1191 cs->exception_index = RISCV_EXCP_INST_ADDR_MIS;
1192 break;
1193 case MMU_DATA_LOAD:
1194 cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS;
1195 break;
1196 case MMU_DATA_STORE:
1197 cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS;
1198 break;
1199 default:
1200 g_assert_not_reached();
1201 }
1202 env->badaddr = addr;
38256529 1203 env->two_stage_lookup = env->virt_enabled ||
ec352d0c 1204 riscv_cpu_two_stage_lookup(mmu_idx);
8e2aa21b 1205 env->two_stage_indirect_lookup = false;
ac684717 1206 cpu_loop_exit_restore(cs, retaddr);
0c3e702a 1207}
0c3e702a 1208
892320fa
AP		 1209
1210static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type)
1211{
1212 enum riscv_pmu_event_idx pmu_event_type;
1213
1214 switch (access_type) {
1215 case MMU_INST_FETCH:
1216 pmu_event_type = RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS;
1217 break;
1218 case MMU_DATA_LOAD:
1219 pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS;
1220 break;
1221 case MMU_DATA_STORE:
1222 pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS;
1223 break;
1224 default:
1225 return;
1226 }
1227
1228 riscv_pmu_incr_ctr(cpu, pmu_event_type);
1229}
1230
8a4ca3c1
RH		 1231bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
1232 MMUAccessType access_type, int mmu_idx,
1233 bool probe, uintptr_t retaddr)
0c3e702a
MC		 1234{
1235 RISCVCPU *cpu = RISCV_CPU(cs);
1236 CPURISCVState *env = &cpu->env;
36a18664 1237 vaddr im_address;
0c3e702a 1238 hwaddr pa = 0;
b297129a 1239 int prot, prot2, prot_pmp;
635b0b0e 1240 bool pmp_violation = false;
36a18664 1241 bool first_stage_error = true;
1c1c060a 1242 bool two_stage_lookup = false;
8e2aa21b 1243 bool two_stage_indirect_error = false;
0c3e702a 1244 int ret = TRANSLATE_FAIL;
cc0fdb29 1245 int mode = mmu_idx;
b297129a
JS		 1246 /* default TLB page size */
1247 target_ulong tlb_size = TARGET_PAGE_SIZE;
0c3e702a 1248
36a18664
AF		 1249 env->guest_phys_fault_addr = 0;
1250
8a4ca3c1
RH		 1251 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
1252 __func__, address, access_type, mmu_idx);
1253
3b57254d
WL		 1254 /*
1255 * MPRV does not affect the virtual-machine load/store
1256 * instructions, HLV, HLVX, and HSV.
1257 */
90ec1cff
GK		 1258 if (riscv_cpu_two_stage_lookup(mmu_idx)) {
1259 mode = get_field(env->hstatus, HSTATUS_SPVP);
1260 } else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
1261 get_field(env->mstatus, MSTATUS_MPRV)) {
1262 mode = get_field(env->mstatus, MSTATUS_MPP);
1263 if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) {
1264 two_stage_lookup = true;
cc0fdb29
HA		 1265 }
1266 }
1267
eacd03cb 1268 pmu_tlb_fill_incr_ctr(cpu, access_type);
38256529 1269 if (env->virt_enabled ||
1c1c060a
AF		 1270 ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
1271 access_type != MMU_INST_FETCH)) {
36a18664 1272 /* Two stage lookup */
33a9a57d
YJ		 1273 ret = get_physical_address(env, &pa, &prot, address,
1274 &env->guest_phys_fault_addr, access_type,
11c27c6d 1275 mmu_idx, true, true, false);
36a18664 1276
33a9a57d
YJ		 1277 /*
1278 * A G-stage exception may be triggered during two state lookup.
1279 * And the env->guest_phys_fault_addr has already been set in
1280 * get_physical_address().
1281 */
1282 if (ret == TRANSLATE_G_STAGE_FAIL) {
1283 first_stage_error = false;
8e2aa21b 1284 two_stage_indirect_error = true;
33a9a57d
YJ		 1285 access_type = MMU_DATA_LOAD;
1286 }
1287
36a18664
AF		 1288 qemu_log_mask(CPU_LOG_MMU,
1289 "%s 1st-stage address=%" VADDR_PRIx " ret %d physical "
883f2c59 1290 HWADDR_FMT_plx " prot %d\n",
36a18664
AF		 1291 __func__, address, ret, pa, prot);
1292
33a9a57d 1293 if (ret == TRANSLATE_SUCCESS) {
36a18664
AF		 1294 /* Second stage lookup */
1295 im_address = pa;
1296
33a9a57d 1297 ret = get_physical_address(env, &pa, &prot2, im_address, NULL,
11c27c6d
JF		 1298 access_type, mmu_idx, false, true,
1299 false);
36a18664
AF		 1300
1301 qemu_log_mask(CPU_LOG_MMU,
c45eff30
WL		 1302 "%s 2nd-stage address=%" VADDR_PRIx
1303 " ret %d physical "
1304 HWADDR_FMT_plx " prot %d\n",
1305 __func__, im_address, ret, pa, prot2);
8f67cd6d
AF		 1306
1307 prot &= prot2;
36a18664 1308
b297129a
JS		 1309 if (ret == TRANSLATE_SUCCESS) {
1310 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
1311 size, access_type, mode);
663e1193
JS		 1312
1313 qemu_log_mask(CPU_LOG_MMU,
883f2c59 1314 "%s PMP address=" HWADDR_FMT_plx " ret %d prot"
663e1193
JS		 1315 " %d tlb_size " TARGET_FMT_lu "\n",
1316 __func__, pa, ret, prot_pmp, tlb_size);
1317
b297129a 1318 prot &= prot_pmp;
36a18664
AF		 1319 }
1320
1321 if (ret != TRANSLATE_SUCCESS) {
1322 /*
1323 * Guest physical address translation failed, this is a HS
1324 * level exception
1325 */
1326 first_stage_error = false;
1327 env->guest_phys_fault_addr = (im_address |
1328 (address &
1329 (TARGET_PAGE_SIZE - 1))) >> 2;
1330 }
1331 }
1332 } else {
1333 /* Single stage lookup */
33a9a57d 1334 ret = get_physical_address(env, &pa, &prot, address, NULL,
11c27c6d 1335 access_type, mmu_idx, true, false, false);
36a18664
AF		 1336
1337 qemu_log_mask(CPU_LOG_MMU,
1338 "%s address=%" VADDR_PRIx " ret %d physical "
883f2c59 1339 HWADDR_FMT_plx " prot %d\n",
36a18664 1340 __func__, address, ret, pa, prot);
8a4ca3c1 1341
b297129a
JS		 1342 if (ret == TRANSLATE_SUCCESS) {
1343 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
1344 size, access_type, mode);
663e1193
JS		 1345
1346 qemu_log_mask(CPU_LOG_MMU,
883f2c59 1347 "%s PMP address=" HWADDR_FMT_plx " ret %d prot"
663e1193
JS		 1348 " %d tlb_size " TARGET_FMT_lu "\n",
1349 __func__, pa, ret, prot_pmp, tlb_size);
1350
b297129a
JS		 1351 prot &= prot_pmp;
1352 }
1f447aec 1353 }
b297129a 1354
1f447aec 1355 if (ret == TRANSLATE_PMP_FAIL) {
635b0b0e 1356 pmp_violation = true;
0c3e702a 1357 }
36a18664 1358
0c3e702a 1359 if (ret == TRANSLATE_SUCCESS) {
b297129a
JS		 1360 tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
1361 prot, mmu_idx, tlb_size);
8a4ca3c1
RH		 1362 return true;
1363 } else if (probe) {
1364 return false;
1365 } else {
1c1c060a
AF		 1366 raise_mmu_exception(env, address, access_type, pmp_violation,
1367 first_stage_error,
38256529 1368 env->virt_enabled ||
8e2aa21b
AP		 1369 riscv_cpu_two_stage_lookup(mmu_idx),
1370 two_stage_indirect_error);
ac684717 1371 cpu_loop_exit_restore(cs, retaddr);
0c3e702a 1372 }
36a18664
AF		 1373
1374 return true;
0c3e702a 1375}
8e2aa21b
AP		 1376
1377static target_ulong riscv_transformed_insn(CPURISCVState *env,
1378 target_ulong insn,
1379 target_ulong taddr)
1380{
1381 target_ulong xinsn = 0;
1382 target_ulong access_rs1 = 0, access_imm = 0, access_size = 0;
1383
1384 /*
1385 * Only Quadrant 0 and Quadrant 2 of RVC instruction space need to
1386 * be uncompressed. The Quadrant 1 of RVC instruction space need
1387 * not be transformed because these instructions won't generate
1388 * any load/store trap.
1389 */
1390
1391 if ((insn & 0x3) != 0x3) {
1392 /* Transform 16bit instruction into 32bit instruction */
1393 switch (GET_C_OP(insn)) {
1394 case OPC_RISC_C_OP_QUAD0: /* Quadrant 0 */
1395 switch (GET_C_FUNC(insn)) {
1396 case OPC_RISC_C_FUNC_FLD_LQ:
1397 if (riscv_cpu_xlen(env) != 128) { /* C.FLD (RV32/64) */
1398 xinsn = OPC_RISC_FLD;
1399 xinsn = SET_RD(xinsn, GET_C_RS2S(insn));
1400 access_rs1 = GET_C_RS1S(insn);
1401 access_imm = GET_C_LD_IMM(insn);
1402 access_size = 8;
1403 }
1404 break;
1405 case OPC_RISC_C_FUNC_LW: /* C.LW */
1406 xinsn = OPC_RISC_LW;
1407 xinsn = SET_RD(xinsn, GET_C_RS2S(insn));
1408 access_rs1 = GET_C_RS1S(insn);
1409 access_imm = GET_C_LW_IMM(insn);
1410 access_size = 4;
1411 break;
1412 case OPC_RISC_C_FUNC_FLW_LD:
1413 if (riscv_cpu_xlen(env) == 32) { /* C.FLW (RV32) */
1414 xinsn = OPC_RISC_FLW;
1415 xinsn = SET_RD(xinsn, GET_C_RS2S(insn));
1416 access_rs1 = GET_C_RS1S(insn);
1417 access_imm = GET_C_LW_IMM(insn);
1418 access_size = 4;
1419 } else { /* C.LD (RV64/RV128) */
1420 xinsn = OPC_RISC_LD;
1421 xinsn = SET_RD(xinsn, GET_C_RS2S(insn));
1422 access_rs1 = GET_C_RS1S(insn);
1423 access_imm = GET_C_LD_IMM(insn);
1424 access_size = 8;
1425 }
1426 break;
1427 case OPC_RISC_C_FUNC_FSD_SQ:
1428 if (riscv_cpu_xlen(env) != 128) { /* C.FSD (RV32/64) */
1429 xinsn = OPC_RISC_FSD;
1430 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn));
1431 access_rs1 = GET_C_RS1S(insn);
1432 access_imm = GET_C_SD_IMM(insn);
1433 access_size = 8;
1434 }
1435 break;
1436 case OPC_RISC_C_FUNC_SW: /* C.SW */
1437 xinsn = OPC_RISC_SW;
1438 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn));
1439 access_rs1 = GET_C_RS1S(insn);
1440 access_imm = GET_C_SW_IMM(insn);
1441 access_size = 4;
1442 break;
1443 case OPC_RISC_C_FUNC_FSW_SD:
1444 if (riscv_cpu_xlen(env) == 32) { /* C.FSW (RV32) */
1445 xinsn = OPC_RISC_FSW;
1446 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn));
1447 access_rs1 = GET_C_RS1S(insn);
1448 access_imm = GET_C_SW_IMM(insn);
1449 access_size = 4;
1450 } else { /* C.SD (RV64/RV128) */
1451 xinsn = OPC_RISC_SD;
1452 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn));
1453 access_rs1 = GET_C_RS1S(insn);
1454 access_imm = GET_C_SD_IMM(insn);
1455 access_size = 8;
1456 }
1457 break;
1458 default:
1459 break;
1460 }
1461 break;
1462 case OPC_RISC_C_OP_QUAD2: /* Quadrant 2 */
1463 switch (GET_C_FUNC(insn)) {
1464 case OPC_RISC_C_FUNC_FLDSP_LQSP:
1465 if (riscv_cpu_xlen(env) != 128) { /* C.FLDSP (RV32/64) */
1466 xinsn = OPC_RISC_FLD;
1467 xinsn = SET_RD(xinsn, GET_C_RD(insn));
1468 access_rs1 = 2;
1469 access_imm = GET_C_LDSP_IMM(insn);
1470 access_size = 8;
1471 }
1472 break;
1473 case OPC_RISC_C_FUNC_LWSP: /* C.LWSP */
1474 xinsn = OPC_RISC_LW;
1475 xinsn = SET_RD(xinsn, GET_C_RD(insn));
1476 access_rs1 = 2;
1477 access_imm = GET_C_LWSP_IMM(insn);
1478 access_size = 4;
1479 break;
1480 case OPC_RISC_C_FUNC_FLWSP_LDSP:
1481 if (riscv_cpu_xlen(env) == 32) { /* C.FLWSP (RV32) */
1482 xinsn = OPC_RISC_FLW;
1483 xinsn = SET_RD(xinsn, GET_C_RD(insn));
1484 access_rs1 = 2;
1485 access_imm = GET_C_LWSP_IMM(insn);
1486 access_size = 4;
1487 } else { /* C.LDSP (RV64/RV128) */
1488 xinsn = OPC_RISC_LD;
1489 xinsn = SET_RD(xinsn, GET_C_RD(insn));
1490 access_rs1 = 2;
1491 access_imm = GET_C_LDSP_IMM(insn);
1492 access_size = 8;
1493 }
1494 break;
1495 case OPC_RISC_C_FUNC_FSDSP_SQSP:
1496 if (riscv_cpu_xlen(env) != 128) { /* C.FSDSP (RV32/64) */
1497 xinsn = OPC_RISC_FSD;
1498 xinsn = SET_RS2(xinsn, GET_C_RS2(insn));
1499 access_rs1 = 2;
1500 access_imm = GET_C_SDSP_IMM(insn);
1501 access_size = 8;
1502 }
1503 break;
1504 case OPC_RISC_C_FUNC_SWSP: /* C.SWSP */
1505 xinsn = OPC_RISC_SW;
1506 xinsn = SET_RS2(xinsn, GET_C_RS2(insn));
1507 access_rs1 = 2;
1508 access_imm = GET_C_SWSP_IMM(insn);
1509 access_size = 4;
1510 break;
1511 case 7:
1512 if (riscv_cpu_xlen(env) == 32) { /* C.FSWSP (RV32) */
1513 xinsn = OPC_RISC_FSW;
1514 xinsn = SET_RS2(xinsn, GET_C_RS2(insn));
1515 access_rs1 = 2;
1516 access_imm = GET_C_SWSP_IMM(insn);
1517 access_size = 4;
1518 } else { /* C.SDSP (RV64/RV128) */
1519 xinsn = OPC_RISC_SD;
1520 xinsn = SET_RS2(xinsn, GET_C_RS2(insn));
1521 access_rs1 = 2;
1522 access_imm = GET_C_SDSP_IMM(insn);
1523 access_size = 8;
1524 }
1525 break;
1526 default:
1527 break;
1528 }
1529 break;
1530 default:
1531 break;
1532 }
1533
1534 /*
1535 * Clear Bit1 of transformed instruction to indicate that
1536 * original insruction was a 16bit instruction
1537 */
1538 xinsn &= ~((target_ulong)0x2);
1539 } else {
1540 /* Transform 32bit (or wider) instructions */
1541 switch (MASK_OP_MAJOR(insn)) {
1542 case OPC_RISC_ATOMIC:
1543 xinsn = insn;
1544 access_rs1 = GET_RS1(insn);
1545 access_size = 1 << GET_FUNCT3(insn);
1546 break;
1547 case OPC_RISC_LOAD:
1548 case OPC_RISC_FP_LOAD:
1549 xinsn = SET_I_IMM(insn, 0);
1550 access_rs1 = GET_RS1(insn);
1551 access_imm = GET_IMM(insn);
1552 access_size = 1 << GET_FUNCT3(insn);
1553 break;
1554 case OPC_RISC_STORE:
1555 case OPC_RISC_FP_STORE:
1556 xinsn = SET_S_IMM(insn, 0);
1557 access_rs1 = GET_RS1(insn);
1558 access_imm = GET_STORE_IMM(insn);
1559 access_size = 1 << GET_FUNCT3(insn);
1560 break;
1561 case OPC_RISC_SYSTEM:
1562 if (MASK_OP_SYSTEM(insn) == OPC_RISC_HLVHSV) {
1563 xinsn = insn;
1564 access_rs1 = GET_RS1(insn);
1565 access_size = 1 << ((GET_FUNCT7(insn) >> 1) & 0x3);
1566 access_size = 1 << access_size;
1567 }
1568 break;
1569 default:
1570 break;
1571 }
1572 }
1573
1574 if (access_size) {
1575 xinsn = SET_RS1(xinsn, (taddr - (env->gpr[access_rs1] + access_imm)) &
1576 (access_size - 1));
1577 }
1578
1579 return xinsn;
1580}
263e2ab2 1581#endif /* !CONFIG_USER_ONLY */
0c3e702a
MC		 1582
1583/*
1584 * Handle Traps
1585 *
1586 * Adapted from Spike's processor_t::take_trap.
1587 *
1588 */
1589void riscv_cpu_do_interrupt(CPUState *cs)
1590{
1591#if !defined(CONFIG_USER_ONLY)
1592
1593 RISCVCPU *cpu = RISCV_CPU(cs);
1594 CPURISCVState *env = &cpu->env;
86d0c457 1595 bool write_gva = false;
284d697c 1596 uint64_t s;
0c3e702a 1597
3b57254d
WL		 1598 /*
1599 * cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide
acbbb94e
MC		 1600 * so we mask off the MSB and separate into trap type and cause.
1601 */
1602 bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG);
1603 target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK;
d028ac75 1604 uint64_t deleg = async ? env->mideleg : env->medeleg;
acbbb94e 1605 target_ulong tval = 0;
8e2aa21b 1606 target_ulong tinst = 0;
30675539
AF		 1607 target_ulong htval = 0;
1608 target_ulong mtval2 = 0;
acbbb94e 1609
a10b9d93 1610 if (cause == RISCV_EXCP_SEMIHOST) {
7d7fb116
PM		 1611 do_common_semihosting(cs);
1612 env->pc += 4;
1613 return;
a10b9d93
KP		 1614 }
1615
acbbb94e
MC		 1616 if (!async) {
1617 /* set tval to badaddr for traps with address information */
1618 switch (cause) {
ab67a1d0
AF		 1619 case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT:
1620 case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT:
acbbb94e
MC		 1621 case RISCV_EXCP_LOAD_ADDR_MIS:
1622 case RISCV_EXCP_STORE_AMO_ADDR_MIS:
1623 case RISCV_EXCP_LOAD_ACCESS_FAULT:
1624 case RISCV_EXCP_STORE_AMO_ACCESS_FAULT:
acbbb94e
MC		 1625 case RISCV_EXCP_LOAD_PAGE_FAULT:
1626 case RISCV_EXCP_STORE_PAGE_FAULT:
24826da0 1627 write_gva = env->two_stage_lookup;
acbbb94e 1628 tval = env->badaddr;
8e2aa21b
AP		 1629 if (env->two_stage_indirect_lookup) {
1630 /*
1631 * special pseudoinstruction for G-stage fault taken while
1632 * doing VS-stage page table walk.
1633 */
1634 tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000;
1635 } else {
1636 /*
1637 * The "Addr. Offset" field in transformed instruction is
1638 * non-zero only for misaligned access.
1639 */
1640 tinst = riscv_transformed_insn(env, env->bins, tval);
1641 }
1642 break;
1643 case RISCV_EXCP_INST_GUEST_PAGE_FAULT:
1644 case RISCV_EXCP_INST_ADDR_MIS:
1645 case RISCV_EXCP_INST_ACCESS_FAULT:
1646 case RISCV_EXCP_INST_PAGE_FAULT:
1647 write_gva = env->two_stage_lookup;
1648 tval = env->badaddr;
1649 if (env->two_stage_indirect_lookup) {
1650 /*
1651 * special pseudoinstruction for G-stage fault taken while
1652 * doing VS-stage page table walk.
1653 */
1654 tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000;
1655 }
acbbb94e 1656 break;
48eaeb56 1657 case RISCV_EXCP_ILLEGAL_INST:
62cf0245 1658 case RISCV_EXCP_VIRT_INSTRUCTION_FAULT:
48eaeb56
AF		 1659 tval = env->bins;
1660 break;
26934f9a
SM		 1661 case RISCV_EXCP_BREAKPOINT:
1662 if (cs->watchpoint_hit) {
1663 tval = cs->watchpoint_hit->hitaddr;
1664 cs->watchpoint_hit = NULL;
1665 }
1666 break;
acbbb94e
MC		 1667 default:
1668 break;
0c3e702a 1669 }
acbbb94e
MC		 1670 /* ecall is dispatched as one cause so translate based on mode */
1671 if (cause == RISCV_EXCP_U_ECALL) {
1672 assert(env->priv <= 3);
5eb9e782
AF		 1673
1674 if (env->priv == PRV_M) {
1675 cause = RISCV_EXCP_M_ECALL;
38256529 1676 } else if (env->priv == PRV_S && env->virt_enabled) {
5eb9e782 1677 cause = RISCV_EXCP_VS_ECALL;
38256529 1678 } else if (env->priv == PRV_S && !env->virt_enabled) {
5eb9e782
AF		 1679 cause = RISCV_EXCP_S_ECALL;
1680 } else if (env->priv == PRV_U) {
1681 cause = RISCV_EXCP_U_ECALL;
1682 }
0c3e702a
MC		 1683 }
1684 }
1685
c51a3f5d 1686 trace_riscv_trap(env->mhartid, async, cause, env->pc, tval,
69430111
AF		 1687 riscv_cpu_get_trap_name(cause, async));
1688
1689 qemu_log_mask(CPU_LOG_INT,
1690 "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", "
1691 "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n",
1692 __func__, env->mhartid, async, cause, env->pc, tval,
1693 riscv_cpu_get_trap_name(cause, async));
0c3e702a 1694
acbbb94e
MC		 1695 if (env->priv <= PRV_S &&
1696 cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
0c3e702a 1697 /* handle the trap in S-mode */
5eb9e782 1698 if (riscv_has_ext(env, RVH)) {
d028ac75 1699 uint64_t hdeleg = async ? env->hideleg : env->hedeleg;
1c1c060a 1700
38256529 1701 if (env->virt_enabled && ((hdeleg >> cause) & 1)) {
84b1c04b 1702 /* Trap to VS mode */
c5969a3a
RK		 1703 /*
1704 * See if we need to adjust cause. Yes if its VS mode interrupt
1705 * no if hypervisor has delegated one of hs mode's interrupt
1706 */
1707 if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT ||
84b1c04b 1708 cause == IRQ_VS_EXT) {
c5969a3a 1709 cause = cause - 1;
84b1c04b 1710 }
86d0c457 1711 write_gva = false;
38256529 1712 } else if (env->virt_enabled) {
5eb9e782
AF		 1713 /* Trap into HS mode, from virt */
1714 riscv_cpu_swap_hypervisor_regs(env);
f2d5850f 1715 env->hstatus = set_field(env->hstatus, HSTATUS_SPVP,
ace54453 1716 env->priv);
2136b6c3 1717 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, true);
86d0c457 1718
30675539
AF		 1719 htval = env->guest_phys_fault_addr;
1720
5eb9e782 1721 riscv_cpu_set_virt_enabled(env, 0);
5eb9e782
AF		 1722 } else {
1723 /* Trap into HS mode */
ec352d0c 1724 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
30675539 1725 htval = env->guest_phys_fault_addr;
5eb9e782 1726 }
86d0c457 1727 env->hstatus = set_field(env->hstatus, HSTATUS_GVA, write_gva);
5eb9e782
AF		 1728 }
1729
1730 s = env->mstatus;
1a9540d1 1731 s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
0c3e702a
MC		 1732 s = set_field(s, MSTATUS_SPP, env->priv);
1733 s = set_field(s, MSTATUS_SIE, 0);
c7b95171 1734 env->mstatus = s;
16fdb8ff 1735 env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1));
acbbb94e 1736 env->sepc = env->pc;
ac12b601 1737 env->stval = tval;
30675539 1738 env->htval = htval;
8e2aa21b 1739 env->htinst = tinst;
acbbb94e 1740 env->pc = (env->stvec >> 2 << 2) +
c45eff30 1741 ((async && (env->stvec & 3) == 1) ? cause * 4 : 0);
fb738839 1742 riscv_cpu_set_mode(env, PRV_S);
0c3e702a 1743 } else {
acbbb94e 1744 /* handle the trap in M-mode */
5eb9e782 1745 if (riscv_has_ext(env, RVH)) {
38256529 1746 if (env->virt_enabled) {
5eb9e782
AF		 1747 riscv_cpu_swap_hypervisor_regs(env);
1748 }
1749 env->mstatus = set_field(env->mstatus, MSTATUS_MPV,
38256529
WL		 1750 env->virt_enabled);
1751 if (env->virt_enabled && tval) {
9034e90a
AF		 1752 env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1);
1753 }
5eb9e782 1754
30675539
AF		 1755 mtval2 = env->guest_phys_fault_addr;
1756
5eb9e782
AF		 1757 /* Trapping to M mode, virt is disabled */
1758 riscv_cpu_set_virt_enabled(env, 0);
5eb9e782
AF		 1759 }
1760
1761 s = env->mstatus;
1a9540d1 1762 s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE));
0c3e702a
MC		 1763 s = set_field(s, MSTATUS_MPP, env->priv);
1764 s = set_field(s, MSTATUS_MIE, 0);
c7b95171 1765 env->mstatus = s;
acbbb94e
MC		 1766 env->mcause = cause | ~(((target_ulong)-1) >> async);
1767 env->mepc = env->pc;
ac12b601 1768 env->mtval = tval;
30675539 1769 env->mtval2 = mtval2;
8e2aa21b 1770 env->mtinst = tinst;
acbbb94e 1771 env->pc = (env->mtvec >> 2 << 2) +
c45eff30 1772 ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);
fb738839 1773 riscv_cpu_set_mode(env, PRV_M);
0c3e702a 1774 }
d9360e96 1775
3b57254d
WL		 1776 /*
1777 * NOTE: it is not necessary to yield load reservations here. It is only
d9360e96
MC		 1778 * necessary for an SC from "another hart" to cause a load reservation
1779 * to be yielded. Refer to the memory consistency model section of the
1780 * RISC-V ISA Specification.
1781 */
1782
ec352d0c 1783 env->two_stage_lookup = false;
8e2aa21b 1784 env->two_stage_indirect_lookup = false;
0c3e702a 1785#endif
330d2ae3 1786 cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */
0c3e702a 1787}
QEMU mirror