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0c3e702a | 1 | /* |
df354dd4 | 2 | * RISC-V CPU helpers for qemu. |
0c3e702a MC |
3 | * |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
21 | #include "qemu/log.h" | |
7ec5d303 | 22 | #include "qemu/main-loop.h" |
0c3e702a | 23 | #include "cpu.h" |
c8f8a995 | 24 | #include "internals.h" |
892320fa | 25 | #include "pmu.h" |
0c3e702a | 26 | #include "exec/exec-all.h" |
8e2aa21b | 27 | #include "instmap.h" |
dcb32f1d | 28 | #include "tcg/tcg-op.h" |
929f0a7f | 29 | #include "trace.h" |
6b5fe137 | 30 | #include "semihosting/common-semi.h" |
2c9d7471 | 31 | #include "sysemu/cpu-timers.h" |
892320fa | 32 | #include "cpu_bits.h" |
2c9d7471 | 33 | #include "debug.h" |
70f168f8 | 34 | #include "tcg/oversized-guest.h" |
0c3e702a MC |
35 | |
36 | int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) | |
37 | { | |
38 | #ifdef CONFIG_USER_ONLY | |
39 | return 0; | |
40 | #else | |
696bacde RH |
41 | bool virt = env->virt_enabled; |
42 | int mode = env->priv; | |
c8f8a995 FW |
43 | |
44 | /* All priv -> mmu_idx mapping are here */ | |
696bacde | 45 | if (!ifetch) { |
eaecd473 RH |
46 | uint64_t status = env->mstatus; |
47 | ||
48 | if (mode == PRV_M && get_field(status, MSTATUS_MPRV)) { | |
696bacde | 49 | mode = get_field(env->mstatus, MSTATUS_MPP); |
869d76f2 WL |
50 | virt = get_field(env->mstatus, MSTATUS_MPV) && |
51 | (mode != PRV_M); | |
eaecd473 RH |
52 | if (virt) { |
53 | status = env->vsstatus; | |
54 | } | |
696bacde | 55 | } |
eaecd473 | 56 | if (mode == PRV_S && get_field(status, MSTATUS_SUM)) { |
696bacde RH |
57 | mode = MMUIdx_S_SUM; |
58 | } | |
c8f8a995 | 59 | } |
696bacde RH |
60 | |
61 | return mode | (virt ? MMU_2STAGE_BIT : 0); | |
0c3e702a MC |
62 | #endif |
63 | } | |
64 | ||
bb5de525 AJ |
65 | void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, |
66 | uint64_t *cs_base, uint32_t *pflags) | |
53677acf | 67 | { |
614c9466 | 68 | RISCVCPU *cpu = env_archcpu(env); |
25f3ddff | 69 | RISCVExtStatus fs, vs; |
53677acf RH |
70 | uint32_t flags = 0; |
71 | ||
8c796f1a | 72 | *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc; |
53677acf RH |
73 | *cs_base = 0; |
74 | ||
3f4a5a53 | 75 | if (cpu->cfg.ext_zve32f) { |
a689a82b FC |
76 | /* |
77 | * If env->vl equals to VLMAX, we can use generic vector operation | |
78 | * expanders (GVEC) to accerlate the vector operations. | |
79 | * However, as LMUL could be a fractional number. The maximum | |
80 | * vector size can be operated might be less than 8 bytes, | |
81 | * which is not supported by GVEC. So we set vl_eq_vlmax flag to true | |
82 | * only when maxsz >= 8 bytes. | |
83 | */ | |
718942ae | 84 | uint32_t vlmax = vext_get_vlmax(cpu, env->vtype); |
a689a82b FC |
85 | uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW); |
86 | uint32_t maxsz = vlmax << sew; | |
87 | bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) && | |
88 | (maxsz >= 8); | |
d96a271a | 89 | flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); |
a689a82b | 90 | flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew); |
53677acf | 91 | flags = FIELD_DP32(flags, TB_FLAGS, LMUL, |
c45eff30 | 92 | FIELD_EX64(env->vtype, VTYPE, VLMUL)); |
53677acf | 93 | flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); |
f1eed927 | 94 | flags = FIELD_DP32(flags, TB_FLAGS, VTA, |
c45eff30 | 95 | FIELD_EX64(env->vtype, VTYPE, VTA)); |
355d5584 | 96 | flags = FIELD_DP32(flags, TB_FLAGS, VMA, |
c45eff30 | 97 | FIELD_EX64(env->vtype, VTYPE, VMA)); |
4acaa133 | 98 | flags = FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart == 0); |
53677acf RH |
99 | } else { |
100 | flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); | |
101 | } | |
102 | ||
103 | #ifdef CONFIG_USER_ONLY | |
25f3ddff RH |
104 | fs = EXT_STATUS_DIRTY; |
105 | vs = EXT_STATUS_DIRTY; | |
53677acf | 106 | #else |
47debc72 FW |
107 | flags = FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv); |
108 | ||
53677acf | 109 | flags |= cpu_mmu_index(env, 0); |
25f3ddff RH |
110 | fs = get_field(env->mstatus, MSTATUS_FS); |
111 | vs = get_field(env->mstatus, MSTATUS_VS); | |
61b4b69d | 112 | |
0f58cbbe RH |
113 | if (env->virt_enabled) { |
114 | flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1); | |
115 | /* | |
116 | * Merge DISABLED and !DIRTY states using MIN. | |
117 | * We will set both fields when dirtying. | |
118 | */ | |
119 | fs = MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS)); | |
120 | vs = MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS)); | |
53677acf | 121 | } |
0f58cbbe | 122 | |
e0b343b5 MC |
123 | /* With Zfinx, floating point is enabled/disabled by Smstateen. */ |
124 | if (!riscv_has_ext(env, RVF)) { | |
125 | fs = (smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR) == RISCV_EXCP_NONE) | |
126 | ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED; | |
127 | } | |
128 | ||
cdfb2905 | 129 | if (cpu->cfg.debug && !icount_enabled()) { |
577f0286 | 130 | flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled); |
2c9d7471 | 131 | } |
53677acf RH |
132 | #endif |
133 | ||
25f3ddff RH |
134 | flags = FIELD_DP32(flags, TB_FLAGS, FS, fs); |
135 | flags = FIELD_DP32(flags, TB_FLAGS, VS, vs); | |
440544e1 | 136 | flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl); |
3a610f54 | 137 | flags = FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env)); |
b83e4f1d | 138 | if (env->cur_pmmask != 0) { |
4208dc7e LZ |
139 | flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); |
140 | } | |
141 | if (env->cur_pmbase != 0) { | |
142 | flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1); | |
143 | } | |
92371bd9 | 144 | |
53677acf RH |
145 | *pflags = flags; |
146 | } | |
147 | ||
40bfa5f6 LZ |
148 | void riscv_cpu_update_mask(CPURISCVState *env) |
149 | { | |
b83e4f1d | 150 | target_ulong mask = 0, base = 0; |
ef1ba32a | 151 | RISCVMXL xl = env->xl; |
40bfa5f6 LZ |
152 | /* |
153 | * TODO: Current RVJ spec does not specify | |
154 | * how the extension interacts with XLEN. | |
155 | */ | |
156 | #ifndef CONFIG_USER_ONLY | |
ef1ba32a WL |
157 | int mode = cpu_address_mode(env); |
158 | xl = cpu_get_xl(env, mode); | |
40bfa5f6 | 159 | if (riscv_has_ext(env, RVJ)) { |
ef1ba32a | 160 | switch (mode) { |
40bfa5f6 LZ |
161 | case PRV_M: |
162 | if (env->mmte & M_PM_ENABLE) { | |
163 | mask = env->mpmmask; | |
164 | base = env->mpmbase; | |
165 | } | |
166 | break; | |
167 | case PRV_S: | |
168 | if (env->mmte & S_PM_ENABLE) { | |
169 | mask = env->spmmask; | |
170 | base = env->spmbase; | |
171 | } | |
172 | break; | |
173 | case PRV_U: | |
174 | if (env->mmte & U_PM_ENABLE) { | |
175 | mask = env->upmmask; | |
176 | base = env->upmbase; | |
177 | } | |
178 | break; | |
179 | default: | |
180 | g_assert_not_reached(); | |
181 | } | |
182 | } | |
183 | #endif | |
ef1ba32a | 184 | if (xl == MXL_RV32) { |
40bfa5f6 LZ |
185 | env->cur_pmmask = mask & UINT32_MAX; |
186 | env->cur_pmbase = base & UINT32_MAX; | |
187 | } else { | |
188 | env->cur_pmmask = mask; | |
189 | env->cur_pmbase = base; | |
190 | } | |
191 | } | |
192 | ||
0c3e702a | 193 | #ifndef CONFIG_USER_ONLY |
43dc93af AP |
194 | |
195 | /* | |
196 | * The HS-mode is allowed to configure priority only for the | |
197 | * following VS-mode local interrupts: | |
198 | * | |
199 | * 0 (Reserved interrupt, reads as zero) | |
200 | * 1 Supervisor software interrupt | |
201 | * 4 (Reserved interrupt, reads as zero) | |
202 | * 5 Supervisor timer interrupt | |
203 | * 8 (Reserved interrupt, reads as zero) | |
204 | * 13 (Reserved interrupt) | |
205 | * 14 " | |
206 | * 15 " | |
207 | * 16 " | |
43577499 AP |
208 | * 17 " |
209 | * 18 " | |
210 | * 19 " | |
211 | * 20 " | |
212 | * 21 " | |
43dc93af | 213 | * 22 " |
43577499 | 214 | * 23 " |
43dc93af AP |
215 | */ |
216 | ||
217 | static const int hviprio_index2irq[] = { | |
43577499 | 218 | 0, 1, 4, 5, 8, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 }; |
43dc93af AP |
219 | static const int hviprio_index2rdzero[] = { |
220 | 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; | |
221 | ||
222 | int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero) | |
0c3e702a | 223 | { |
43dc93af AP |
224 | if (index < 0 || ARRAY_SIZE(hviprio_index2irq) <= index) { |
225 | return -EINVAL; | |
226 | } | |
3ef10a09 | 227 | |
43dc93af AP |
228 | if (out_irq) { |
229 | *out_irq = hviprio_index2irq[index]; | |
230 | } | |
3ef10a09 | 231 | |
43dc93af AP |
232 | if (out_rdzero) { |
233 | *out_rdzero = hviprio_index2rdzero[index]; | |
234 | } | |
cd032fe7 | 235 | |
43dc93af AP |
236 | return 0; |
237 | } | |
3ef10a09 | 238 | |
43dc93af AP |
239 | /* |
240 | * Default priorities of local interrupts are defined in the | |
241 | * RISC-V Advanced Interrupt Architecture specification. | |
242 | * | |
243 | * ---------------------------------------------------------------- | |
244 | * Default | | |
245 | * Priority | Major Interrupt Numbers | |
246 | * ---------------------------------------------------------------- | |
43577499 AP |
247 | * Highest | 47, 23, 46, 45, 22, 44, |
248 | * | 43, 21, 42, 41, 20, 40 | |
43dc93af AP |
249 | * | |
250 | * | 11 (0b), 3 (03), 7 (07) | |
251 | * | 9 (09), 1 (01), 5 (05) | |
252 | * | 12 (0c) | |
253 | * | 10 (0a), 2 (02), 6 (06) | |
254 | * | | |
43577499 AP |
255 | * | 39, 19, 38, 37, 18, 36, |
256 | * Lowest | 35, 17, 34, 33, 16, 32 | |
43dc93af AP |
257 | * ---------------------------------------------------------------- |
258 | */ | |
259 | static const uint8_t default_iprio[64] = { | |
c45eff30 WL |
260 | /* Custom interrupts 48 to 63 */ |
261 | [63] = IPRIO_MMAXIPRIO, | |
262 | [62] = IPRIO_MMAXIPRIO, | |
263 | [61] = IPRIO_MMAXIPRIO, | |
264 | [60] = IPRIO_MMAXIPRIO, | |
265 | [59] = IPRIO_MMAXIPRIO, | |
266 | [58] = IPRIO_MMAXIPRIO, | |
267 | [57] = IPRIO_MMAXIPRIO, | |
268 | [56] = IPRIO_MMAXIPRIO, | |
269 | [55] = IPRIO_MMAXIPRIO, | |
270 | [54] = IPRIO_MMAXIPRIO, | |
271 | [53] = IPRIO_MMAXIPRIO, | |
272 | [52] = IPRIO_MMAXIPRIO, | |
273 | [51] = IPRIO_MMAXIPRIO, | |
274 | [50] = IPRIO_MMAXIPRIO, | |
275 | [49] = IPRIO_MMAXIPRIO, | |
276 | [48] = IPRIO_MMAXIPRIO, | |
277 | ||
278 | /* Custom interrupts 24 to 31 */ | |
279 | [31] = IPRIO_MMAXIPRIO, | |
280 | [30] = IPRIO_MMAXIPRIO, | |
281 | [29] = IPRIO_MMAXIPRIO, | |
282 | [28] = IPRIO_MMAXIPRIO, | |
283 | [27] = IPRIO_MMAXIPRIO, | |
284 | [26] = IPRIO_MMAXIPRIO, | |
285 | [25] = IPRIO_MMAXIPRIO, | |
286 | [24] = IPRIO_MMAXIPRIO, | |
287 | ||
288 | [47] = IPRIO_DEFAULT_UPPER, | |
289 | [23] = IPRIO_DEFAULT_UPPER + 1, | |
290 | [46] = IPRIO_DEFAULT_UPPER + 2, | |
291 | [45] = IPRIO_DEFAULT_UPPER + 3, | |
292 | [22] = IPRIO_DEFAULT_UPPER + 4, | |
293 | [44] = IPRIO_DEFAULT_UPPER + 5, | |
294 | ||
295 | [43] = IPRIO_DEFAULT_UPPER + 6, | |
296 | [21] = IPRIO_DEFAULT_UPPER + 7, | |
297 | [42] = IPRIO_DEFAULT_UPPER + 8, | |
298 | [41] = IPRIO_DEFAULT_UPPER + 9, | |
299 | [20] = IPRIO_DEFAULT_UPPER + 10, | |
300 | [40] = IPRIO_DEFAULT_UPPER + 11, | |
301 | ||
302 | [11] = IPRIO_DEFAULT_M, | |
303 | [3] = IPRIO_DEFAULT_M + 1, | |
304 | [7] = IPRIO_DEFAULT_M + 2, | |
305 | ||
306 | [9] = IPRIO_DEFAULT_S, | |
307 | [1] = IPRIO_DEFAULT_S + 1, | |
308 | [5] = IPRIO_DEFAULT_S + 2, | |
309 | ||
310 | [12] = IPRIO_DEFAULT_SGEXT, | |
311 | ||
312 | [10] = IPRIO_DEFAULT_VS, | |
313 | [2] = IPRIO_DEFAULT_VS + 1, | |
314 | [6] = IPRIO_DEFAULT_VS + 2, | |
315 | ||
316 | [39] = IPRIO_DEFAULT_LOWER, | |
317 | [19] = IPRIO_DEFAULT_LOWER + 1, | |
318 | [38] = IPRIO_DEFAULT_LOWER + 2, | |
319 | [37] = IPRIO_DEFAULT_LOWER + 3, | |
320 | [18] = IPRIO_DEFAULT_LOWER + 4, | |
321 | [36] = IPRIO_DEFAULT_LOWER + 5, | |
322 | ||
323 | [35] = IPRIO_DEFAULT_LOWER + 6, | |
324 | [17] = IPRIO_DEFAULT_LOWER + 7, | |
325 | [34] = IPRIO_DEFAULT_LOWER + 8, | |
326 | [33] = IPRIO_DEFAULT_LOWER + 9, | |
327 | [16] = IPRIO_DEFAULT_LOWER + 10, | |
328 | [32] = IPRIO_DEFAULT_LOWER + 11, | |
43dc93af AP |
329 | }; |
330 | ||
331 | uint8_t riscv_cpu_default_priority(int irq) | |
332 | { | |
333 | if (irq < 0 || irq > 63) { | |
334 | return IPRIO_MMAXIPRIO; | |
335 | } | |
336 | ||
337 | return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO; | |
338 | }; | |
339 | ||
340 | static int riscv_cpu_pending_to_irq(CPURISCVState *env, | |
341 | int extirq, unsigned int extirq_def_prio, | |
342 | uint64_t pending, uint8_t *iprio) | |
343 | { | |
344 | int irq, best_irq = RISCV_EXCP_NONE; | |
345 | unsigned int prio, best_prio = UINT_MAX; | |
346 | ||
347 | if (!pending) { | |
348 | return RISCV_EXCP_NONE; | |
349 | } | |
350 | ||
351 | irq = ctz64(pending); | |
9c33e08b WL |
352 | if (!((extirq == IRQ_M_EXT) ? riscv_cpu_cfg(env)->ext_smaia : |
353 | riscv_cpu_cfg(env)->ext_ssaia)) { | |
43dc93af AP |
354 | return irq; |
355 | } | |
356 | ||
357 | pending = pending >> irq; | |
358 | while (pending) { | |
359 | prio = iprio[irq]; | |
360 | if (!prio) { | |
361 | if (irq == extirq) { | |
362 | prio = extirq_def_prio; | |
363 | } else { | |
364 | prio = (riscv_cpu_default_priority(irq) < extirq_def_prio) ? | |
365 | 1 : IPRIO_MMAXIPRIO; | |
366 | } | |
367 | } | |
368 | if ((pending & 0x1) && (prio <= best_prio)) { | |
369 | best_irq = irq; | |
370 | best_prio = prio; | |
371 | } | |
372 | irq++; | |
373 | pending = pending >> 1; | |
374 | } | |
375 | ||
376 | return best_irq; | |
377 | } | |
378 | ||
1697837e | 379 | /* |
40336d5b RK |
380 | * Doesn't report interrupts inserted using mvip from M-mode firmware or |
381 | * using hvip bits 13:63 from HS-mode. Those are returned in | |
382 | * riscv_cpu_sirq_pending() and riscv_cpu_vsirq_pending(). | |
1697837e | 383 | */ |
8f42415f | 384 | uint64_t riscv_cpu_all_pending(CPURISCVState *env) |
43dc93af AP |
385 | { |
386 | uint32_t gein = get_field(env->hstatus, HSTATUS_VGEIN); | |
387 | uint64_t vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; | |
3ec0fe18 | 388 | uint64_t vstip = (env->vstime_irq) ? MIP_VSTIP : 0; |
43dc93af | 389 | |
3ec0fe18 | 390 | return (env->mip | vsgein | vstip) & env->mie; |
43dc93af AP |
391 | } |
392 | ||
393 | int riscv_cpu_mirq_pending(CPURISCVState *env) | |
394 | { | |
395 | uint64_t irqs = riscv_cpu_all_pending(env) & ~env->mideleg & | |
396 | ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); | |
397 | ||
398 | return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, | |
399 | irqs, env->miprio); | |
400 | } | |
401 | ||
402 | int riscv_cpu_sirq_pending(CPURISCVState *env) | |
403 | { | |
404 | uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & | |
405 | ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); | |
1697837e | 406 | uint64_t irqs_f = env->mvip & env->mvien & ~env->mideleg & env->sie; |
43dc93af AP |
407 | |
408 | return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, | |
1697837e | 409 | irqs | irqs_f, env->siprio); |
43dc93af AP |
410 | } |
411 | ||
412 | int riscv_cpu_vsirq_pending(CPURISCVState *env) | |
413 | { | |
40336d5b RK |
414 | uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & env->hideleg; |
415 | uint64_t irqs_f_vs = env->hvip & env->hvien & ~env->hideleg & env->vsie; | |
416 | uint64_t vsbits; | |
417 | ||
418 | /* Bring VS-level bits to correct position */ | |
419 | vsbits = irqs & VS_MODE_INTERRUPTS; | |
420 | irqs &= ~VS_MODE_INTERRUPTS; | |
421 | irqs |= vsbits >> 1; | |
43dc93af AP |
422 | |
423 | return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, | |
40336d5b | 424 | (irqs | irqs_f_vs), env->hviprio); |
43dc93af AP |
425 | } |
426 | ||
427 | static int riscv_cpu_local_irq_pending(CPURISCVState *env) | |
428 | { | |
40336d5b RK |
429 | uint64_t irqs, pending, mie, hsie, vsie, irqs_f, irqs_f_vs; |
430 | uint64_t vsbits, irq_delegated; | |
43dc93af | 431 | int virq; |
43dc93af AP |
432 | |
433 | /* Determine interrupt enable state of all privilege modes */ | |
38256529 | 434 | if (env->virt_enabled) { |
43dc93af AP |
435 | mie = 1; |
436 | hsie = 1; | |
437 | vsie = (env->priv < PRV_S) || | |
438 | (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE)); | |
0c3e702a | 439 | } else { |
43dc93af AP |
440 | mie = (env->priv < PRV_M) || |
441 | (env->priv == PRV_M && get_field(env->mstatus, MSTATUS_MIE)); | |
442 | hsie = (env->priv < PRV_S) || | |
443 | (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE)); | |
444 | vsie = 0; | |
445 | } | |
446 | ||
447 | /* Determine all pending interrupts */ | |
448 | pending = riscv_cpu_all_pending(env); | |
449 | ||
450 | /* Check M-mode interrupts */ | |
451 | irqs = pending & ~env->mideleg & -mie; | |
452 | if (irqs) { | |
453 | return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, | |
454 | irqs, env->miprio); | |
455 | } | |
456 | ||
1697837e RK |
457 | /* Check for virtual S-mode interrupts. */ |
458 | irqs_f = env->mvip & (env->mvien & ~env->mideleg) & env->sie; | |
459 | ||
43dc93af | 460 | /* Check HS-mode interrupts */ |
1697837e | 461 | irqs = ((pending & env->mideleg & ~env->hideleg) | irqs_f) & -hsie; |
43dc93af AP |
462 | if (irqs) { |
463 | return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, | |
464 | irqs, env->siprio); | |
0c3e702a | 465 | } |
43dc93af | 466 | |
40336d5b RK |
467 | /* Check for virtual VS-mode interrupts. */ |
468 | irqs_f_vs = env->hvip & env->hvien & ~env->hideleg & env->vsie; | |
469 | ||
43dc93af | 470 | /* Check VS-mode interrupts */ |
40336d5b RK |
471 | irq_delegated = pending & env->mideleg & env->hideleg; |
472 | ||
473 | /* Bring VS-level bits to correct position */ | |
474 | vsbits = irq_delegated & VS_MODE_INTERRUPTS; | |
475 | irq_delegated &= ~VS_MODE_INTERRUPTS; | |
476 | irq_delegated |= vsbits >> 1; | |
477 | ||
478 | irqs = (irq_delegated | irqs_f_vs) & -vsie; | |
43dc93af AP |
479 | if (irqs) { |
480 | virq = riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, | |
40336d5b RK |
481 | irqs, env->hviprio); |
482 | if (virq <= 0 || (virq > 12 && virq <= 63)) { | |
483 | return virq; | |
484 | } else { | |
485 | return virq + 1; | |
486 | } | |
43dc93af AP |
487 | } |
488 | ||
489 | /* Indicate no pending interrupt */ | |
490 | return RISCV_EXCP_NONE; | |
0c3e702a | 491 | } |
0c3e702a MC |
492 | |
493 | bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) | |
494 | { | |
0c3e702a MC |
495 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
496 | RISCVCPU *cpu = RISCV_CPU(cs); | |
497 | CPURISCVState *env = &cpu->env; | |
efbdbc26 | 498 | int interruptno = riscv_cpu_local_irq_pending(env); |
0c3e702a MC |
499 | if (interruptno >= 0) { |
500 | cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno; | |
501 | riscv_cpu_do_interrupt(cs); | |
502 | return true; | |
503 | } | |
504 | } | |
0c3e702a MC |
505 | return false; |
506 | } | |
507 | ||
b345b480 AF |
508 | /* Return true is floating point support is currently enabled */ |
509 | bool riscv_cpu_fp_enabled(CPURISCVState *env) | |
510 | { | |
511 | if (env->mstatus & MSTATUS_FS) { | |
38256529 | 512 | if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_FS)) { |
29409c1d AF |
513 | return false; |
514 | } | |
b345b480 AF |
515 | return true; |
516 | } | |
517 | ||
518 | return false; | |
519 | } | |
520 | ||
61b4b69d LZ |
521 | /* Return true is vector support is currently enabled */ |
522 | bool riscv_cpu_vector_enabled(CPURISCVState *env) | |
523 | { | |
524 | if (env->mstatus & MSTATUS_VS) { | |
38256529 | 525 | if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_VS)) { |
61b4b69d LZ |
526 | return false; |
527 | } | |
528 | return true; | |
529 | } | |
530 | ||
531 | return false; | |
532 | } | |
533 | ||
66e594f2 AF |
534 | void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) |
535 | { | |
c163b3ba | 536 | uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | |
284d697c | 537 | MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | |
61b4b69d | 538 | MSTATUS64_UXL | MSTATUS_VS; |
c163b3ba WL |
539 | |
540 | if (riscv_has_ext(env, RVF)) { | |
541 | mstatus_mask |= MSTATUS_FS; | |
542 | } | |
38256529 | 543 | bool current_virt = env->virt_enabled; |
66e594f2 AF |
544 | |
545 | g_assert(riscv_has_ext(env, RVH)); | |
546 | ||
66e594f2 AF |
547 | if (current_virt) { |
548 | /* Current V=1 and we are about to change to V=0 */ | |
549 | env->vsstatus = env->mstatus & mstatus_mask; | |
550 | env->mstatus &= ~mstatus_mask; | |
551 | env->mstatus |= env->mstatus_hs; | |
552 | ||
553 | env->vstvec = env->stvec; | |
554 | env->stvec = env->stvec_hs; | |
555 | ||
556 | env->vsscratch = env->sscratch; | |
557 | env->sscratch = env->sscratch_hs; | |
558 | ||
559 | env->vsepc = env->sepc; | |
560 | env->sepc = env->sepc_hs; | |
561 | ||
562 | env->vscause = env->scause; | |
563 | env->scause = env->scause_hs; | |
564 | ||
ac12b601 AP |
565 | env->vstval = env->stval; |
566 | env->stval = env->stval_hs; | |
66e594f2 AF |
567 | |
568 | env->vsatp = env->satp; | |
569 | env->satp = env->satp_hs; | |
570 | } else { | |
571 | /* Current V=0 and we are about to change to V=1 */ | |
572 | env->mstatus_hs = env->mstatus & mstatus_mask; | |
573 | env->mstatus &= ~mstatus_mask; | |
574 | env->mstatus |= env->vsstatus; | |
575 | ||
576 | env->stvec_hs = env->stvec; | |
577 | env->stvec = env->vstvec; | |
578 | ||
579 | env->sscratch_hs = env->sscratch; | |
580 | env->sscratch = env->vsscratch; | |
581 | ||
582 | env->sepc_hs = env->sepc; | |
583 | env->sepc = env->vsepc; | |
584 | ||
585 | env->scause_hs = env->scause; | |
586 | env->scause = env->vscause; | |
587 | ||
ac12b601 AP |
588 | env->stval_hs = env->stval; |
589 | env->stval = env->vstval; | |
66e594f2 AF |
590 | |
591 | env->satp_hs = env->satp; | |
592 | env->satp = env->vsatp; | |
593 | } | |
594 | } | |
595 | ||
cd032fe7 AP |
596 | target_ulong riscv_cpu_get_geilen(CPURISCVState *env) |
597 | { | |
598 | if (!riscv_has_ext(env, RVH)) { | |
599 | return 0; | |
600 | } | |
601 | ||
602 | return env->geilen; | |
603 | } | |
604 | ||
605 | void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen) | |
606 | { | |
607 | if (!riscv_has_ext(env, RVH)) { | |
608 | return; | |
609 | } | |
610 | ||
611 | if (geilen > (TARGET_LONG_BITS - 1)) { | |
612 | return; | |
613 | } | |
614 | ||
615 | env->geilen = geilen; | |
616 | } | |
617 | ||
c43732f5 | 618 | /* This function can only be called to set virt when RVH is enabled */ |
ef6bb7b6 AF |
619 | void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) |
620 | { | |
eccc5a12 | 621 | /* Flush the TLB on all virt mode changes. */ |
b3c5077b | 622 | if (env->virt_enabled != enable) { |
eccc5a12 AF |
623 | tlb_flush(env_cpu(env)); |
624 | } | |
625 | ||
b3c5077b | 626 | env->virt_enabled = enable; |
02d9565b AP |
627 | |
628 | if (enable) { | |
629 | /* | |
630 | * The guest external interrupts from an interrupt controller are | |
631 | * delivered only when the Guest/VM is running (i.e. V=1). This means | |
632 | * any guest external interrupt which is triggered while the Guest/VM | |
633 | * is not running (i.e. V=0) will be missed on QEMU resulting in guest | |
634 | * with sluggish response to serial console input and other I/O events. | |
635 | * | |
636 | * To solve this, we check and inject interrupt after setting V=1. | |
637 | */ | |
bbb9fc25 | 638 | riscv_cpu_update_mip(env, 0, 0); |
02d9565b | 639 | } |
ef6bb7b6 AF |
640 | } |
641 | ||
d028ac75 | 642 | int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts) |
e3e7039c MC |
643 | { |
644 | CPURISCVState *env = &cpu->env; | |
645 | if (env->miclaim & interrupts) { | |
646 | return -1; | |
647 | } else { | |
648 | env->miclaim |= interrupts; | |
649 | return 0; | |
650 | } | |
651 | } | |
652 | ||
1ebad505 | 653 | void riscv_cpu_interrupt(CPURISCVState *env) |
df354dd4 | 654 | { |
1697837e | 655 | uint64_t gein, vsgein = 0, vstip = 0, irqf = 0; |
bbb9fc25 | 656 | CPUState *cs = env_cpu(env); |
1ebad505 RK |
657 | |
658 | QEMU_IOTHREAD_LOCK_GUARD(); | |
7ec5d303 | 659 | |
38256529 | 660 | if (env->virt_enabled) { |
cd032fe7 AP |
661 | gein = get_field(env->hstatus, HSTATUS_VGEIN); |
662 | vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; | |
40336d5b | 663 | irqf = env->hvien & env->hvip & env->vsie; |
1697837e RK |
664 | } else { |
665 | irqf = env->mvien & env->mvip & env->sie; | |
cd032fe7 AP |
666 | } |
667 | ||
3ec0fe18 AP |
668 | vstip = env->vstime_irq ? MIP_VSTIP : 0; |
669 | ||
1697837e | 670 | if (env->mip | vsgein | vstip | irqf) { |
7ec5d303 AF |
671 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
672 | } else { | |
673 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); | |
674 | } | |
1ebad505 RK |
675 | } |
676 | ||
677 | uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, uint64_t value) | |
678 | { | |
679 | uint64_t old = env->mip; | |
680 | ||
681 | /* No need to update mip for VSTIP */ | |
682 | mask = ((mask == MIP_VSTIP) && env->vstime_irq) ? 0 : mask; | |
683 | ||
684 | QEMU_IOTHREAD_LOCK_GUARD(); | |
685 | ||
686 | env->mip = (env->mip & ~mask) | (value & mask); | |
687 | ||
688 | riscv_cpu_interrupt(env); | |
0a01f2ee | 689 | |
df354dd4 MC |
690 | return old; |
691 | } | |
692 | ||
e2f01f3c FC |
693 | void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), |
694 | void *arg) | |
c6957248 AP |
695 | { |
696 | env->rdtime_fn = fn; | |
a47ef6e9 | 697 | env->rdtime_fn_arg = arg; |
c6957248 AP |
698 | } |
699 | ||
69077dd6 AP |
700 | void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, |
701 | int (*rmw_fn)(void *arg, | |
702 | target_ulong reg, | |
703 | target_ulong *val, | |
704 | target_ulong new_val, | |
705 | target_ulong write_mask), | |
706 | void *rmw_fn_arg) | |
707 | { | |
708 | if (priv <= PRV_M) { | |
709 | env->aia_ireg_rmw_fn[priv] = rmw_fn; | |
710 | env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg; | |
711 | } | |
712 | } | |
713 | ||
fb738839 | 714 | void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) |
df354dd4 | 715 | { |
0c98ccef WL |
716 | g_assert(newpriv <= PRV_M && newpriv != PRV_RESERVED); |
717 | ||
5a4ae64c LZ |
718 | if (icount_enabled() && newpriv != env->priv) { |
719 | riscv_itrigger_update_priv(env); | |
720 | } | |
df354dd4 MC |
721 | /* tlb_flush is unnecessary as mode is contained in mmu_idx */ |
722 | env->priv = newpriv; | |
440544e1 | 723 | env->xl = cpu_recompute_xl(env); |
40bfa5f6 | 724 | riscv_cpu_update_mask(env); |
c13b169f JS |
725 | |
726 | /* | |
727 | * Clear the load reservation - otherwise a reservation placed in one | |
728 | * context/process can be used by another, resulting in an SC succeeding | |
729 | * incorrectly. Version 2.2 of the ISA specification explicitly requires | |
730 | * this behaviour, while later revisions say that the kernel "should" use | |
731 | * an SC instruction to force the yielding of a load reservation on a | |
732 | * preemptive context switch. As a result, do both. | |
733 | */ | |
734 | env->load_res = -1; | |
df354dd4 MC |
735 | } |
736 | ||
b297129a JS |
737 | /* |
738 | * get_physical_address_pmp - check PMP permission for this physical address | |
739 | * | |
740 | * Match the PMP region and check permission for this physical address and it's | |
741 | * TLB page. Returns 0 if the permission checking was successful | |
742 | * | |
743 | * @env: CPURISCVState | |
744 | * @prot: The returned protection attributes | |
b297129a JS |
745 | * @addr: The physical address to be checked permission |
746 | * @access_type: The type of MMU access | |
747 | * @mode: Indicates current privilege level. | |
748 | */ | |
bfc7ee12 | 749 | static int get_physical_address_pmp(CPURISCVState *env, int *prot, hwaddr addr, |
b297129a JS |
750 | int size, MMUAccessType access_type, |
751 | int mode) | |
752 | { | |
753 | pmp_priv_t pmp_priv; | |
e9c39713 | 754 | bool pmp_has_privs; |
b297129a | 755 | |
3fe40ef5 | 756 | if (!riscv_cpu_cfg(env)->pmp) { |
b297129a JS |
757 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
758 | return TRANSLATE_SUCCESS; | |
759 | } | |
760 | ||
e9c39713 WL |
761 | pmp_has_privs = pmp_hart_has_privs(env, addr, size, 1 << access_type, |
762 | &pmp_priv, mode); | |
763 | if (!pmp_has_privs) { | |
b297129a JS |
764 | *prot = 0; |
765 | return TRANSLATE_PMP_FAIL; | |
766 | } | |
767 | ||
768 | *prot = pmp_priv_to_page_prot(pmp_priv); | |
b297129a JS |
769 | |
770 | return TRANSLATE_SUCCESS; | |
771 | } | |
772 | ||
3b57254d WL |
773 | /* |
774 | * get_physical_address - get the physical address for this virtual address | |
0c3e702a MC |
775 | * |
776 | * Do a page table walk to obtain the physical address corresponding to a | |
777 | * virtual address. Returns 0 if the translation was successful | |
778 | * | |
779 | * Adapted from Spike's mmu_t::translate and mmu_t::walk | |
780 | * | |
1448689c AF |
781 | * @env: CPURISCVState |
782 | * @physical: This will be set to the calculated physical address | |
783 | * @prot: The returned protection attributes | |
77dff650 | 784 | * @addr: The virtual address or guest physical address to be translated |
33a9a57d YJ |
785 | * @fault_pte_addr: If not NULL, this will be set to fault pte address |
786 | * when a error occurs on pte address translation. | |
787 | * This will already be shifted to match htval. | |
1448689c AF |
788 | * @access_type: The type of MMU access |
789 | * @mmu_idx: Indicates current privilege level | |
790 | * @first_stage: Are we in first stage translation? | |
791 | * Second stage is used for hypervisor guest translation | |
36a18664 | 792 | * @two_stage: Are we going to perform two stage translation |
11c27c6d | 793 | * @is_debug: Is this access from a debugger or the monitor? |
0c3e702a MC |
794 | */ |
795 | static int get_physical_address(CPURISCVState *env, hwaddr *physical, | |
e1dd1507 | 796 | int *ret_prot, vaddr addr, |
33a9a57d | 797 | target_ulong *fault_pte_addr, |
1448689c | 798 | int access_type, int mmu_idx, |
11c27c6d JF |
799 | bool first_stage, bool two_stage, |
800 | bool is_debug) | |
0c3e702a | 801 | { |
3b57254d WL |
802 | /* |
803 | * NOTE: the env->pc value visible here will not be | |
0c3e702a | 804 | * correct, but the value visible to the exception handler |
3b57254d WL |
805 | * (riscv_cpu_do_interrupt) is correct |
806 | */ | |
aacb578f PD |
807 | MemTxResult res; |
808 | MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; | |
340b5805 | 809 | int mode = mmuidx_priv(mmu_idx); |
36a18664 | 810 | bool use_background = false; |
05e6ca5e | 811 | hwaddr ppn; |
2bacb224 WL |
812 | int napot_bits = 0; |
813 | target_ulong napot_mask; | |
0c3e702a | 814 | |
36a18664 AF |
815 | /* |
816 | * Check if we should use the background registers for the two | |
817 | * stage translation. We don't need to check if we actually need | |
818 | * two stage translation as that happened before this function | |
819 | * was called. Background registers will be used if the guest has | |
820 | * forced a two stage translation to be on (in HS or M mode). | |
821 | */ | |
38256529 | 822 | if (!env->virt_enabled && two_stage) { |
29b3361b AF |
823 | use_background = true; |
824 | } | |
825 | ||
dcf654a3 | 826 | if (mode == PRV_M || !riscv_cpu_cfg(env)->mmu) { |
0c3e702a | 827 | *physical = addr; |
e1dd1507 | 828 | *ret_prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
0c3e702a MC |
829 | return TRANSLATE_SUCCESS; |
830 | } | |
831 | ||
e1dd1507 | 832 | *ret_prot = 0; |
0c3e702a | 833 | |
ddf78132 | 834 | hwaddr base; |
38303e8a | 835 | int levels, ptidxbits, ptesize, vm, widened; |
0c3e702a | 836 | |
1a9540d1 AF |
837 | if (first_stage == true) { |
838 | if (use_background) { | |
db23e5d9 | 839 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
419ddf00 AF |
840 | base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT; |
841 | vm = get_field(env->vsatp, SATP32_MODE); | |
842 | } else { | |
843 | base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT; | |
844 | vm = get_field(env->vsatp, SATP64_MODE); | |
845 | } | |
36a18664 | 846 | } else { |
db23e5d9 | 847 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
419ddf00 AF |
848 | base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; |
849 | vm = get_field(env->satp, SATP32_MODE); | |
850 | } else { | |
851 | base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT; | |
852 | vm = get_field(env->satp, SATP64_MODE); | |
853 | } | |
0c3e702a | 854 | } |
36a18664 | 855 | widened = 0; |
1a9540d1 | 856 | } else { |
db23e5d9 | 857 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
994b6bb2 AF |
858 | base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT; |
859 | vm = get_field(env->hgatp, SATP32_MODE); | |
860 | } else { | |
861 | base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT; | |
862 | vm = get_field(env->hgatp, SATP64_MODE); | |
863 | } | |
1a9540d1 AF |
864 | widened = 2; |
865 | } | |
38303e8a | 866 | |
1a9540d1 AF |
867 | switch (vm) { |
868 | case VM_1_10_SV32: | |
869 | levels = 2; ptidxbits = 10; ptesize = 4; break; | |
870 | case VM_1_10_SV39: | |
871 | levels = 3; ptidxbits = 9; ptesize = 8; break; | |
872 | case VM_1_10_SV48: | |
873 | levels = 4; ptidxbits = 9; ptesize = 8; break; | |
874 | case VM_1_10_SV57: | |
875 | levels = 5; ptidxbits = 9; ptesize = 8; break; | |
876 | case VM_1_10_MBARE: | |
877 | *physical = addr; | |
e1dd1507 | 878 | *ret_prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
1a9540d1 AF |
879 | return TRANSLATE_SUCCESS; |
880 | default: | |
881 | g_assert_not_reached(); | |
0c3e702a MC |
882 | } |
883 | ||
3109cd98 | 884 | CPUState *cs = env_cpu(env); |
36a18664 | 885 | int va_bits = PGSHIFT + levels * ptidxbits + widened; |
36a18664 | 886 | |
7bf14a2f IR |
887 | if (first_stage == true) { |
888 | target_ulong mask, masked_msbs; | |
36a18664 | 889 | |
7bf14a2f IR |
890 | if (TARGET_LONG_BITS > (va_bits - 1)) { |
891 | mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; | |
892 | } else { | |
893 | mask = 0; | |
894 | } | |
895 | masked_msbs = (addr >> (va_bits - 1)) & mask; | |
896 | ||
897 | if (masked_msbs != 0 && masked_msbs != mask) { | |
898 | return TRANSLATE_FAIL; | |
899 | } | |
900 | } else { | |
901 | if (vm != VM_1_10_SV32 && addr >> va_bits != 0) { | |
902 | return TRANSLATE_FAIL; | |
903 | } | |
0c3e702a MC |
904 | } |
905 | ||
8d6a00cd | 906 | bool pbmte = env->menvcfg & MENVCFG_PBMTE; |
ed67d637 | 907 | bool adue = env->menvcfg & MENVCFG_ADUE; |
8d6a00cd RH |
908 | |
909 | if (first_stage && two_stage && env->virt_enabled) { | |
910 | pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE); | |
ed67d637 | 911 | adue = adue && (env->henvcfg & HENVCFG_ADUE); |
8d6a00cd RH |
912 | } |
913 | ||
0c3e702a | 914 | int ptshift = (levels - 1) * ptidxbits; |
59688aa0 RH |
915 | target_ulong pte; |
916 | hwaddr pte_addr; | |
0c3e702a MC |
917 | int i; |
918 | ||
919 | #if !TCG_OVERSIZED_GUEST | |
920 | restart: | |
921 | #endif | |
922 | for (i = 0; i < levels; i++, ptshift -= ptidxbits) { | |
36a18664 AF |
923 | target_ulong idx; |
924 | if (i == 0) { | |
925 | idx = (addr >> (PGSHIFT + ptshift)) & | |
926 | ((1 << (ptidxbits + widened)) - 1); | |
927 | } else { | |
928 | idx = (addr >> (PGSHIFT + ptshift)) & | |
0c3e702a | 929 | ((1 << ptidxbits) - 1); |
36a18664 | 930 | } |
0c3e702a MC |
931 | |
932 | /* check that physical address of PTE is legal */ | |
36a18664 AF |
933 | |
934 | if (two_stage && first_stage) { | |
38472890 | 935 | int vbase_prot; |
36a18664 AF |
936 | hwaddr vbase; |
937 | ||
938 | /* Do the second stage translation on the base PTE address. */ | |
88914473 | 939 | int vbase_ret = get_physical_address(env, &vbase, &vbase_prot, |
33a9a57d | 940 | base, NULL, MMU_DATA_LOAD, |
a427c836 | 941 | MMUIdx_U, false, true, |
11c27c6d | 942 | is_debug); |
88914473 AF |
943 | |
944 | if (vbase_ret != TRANSLATE_SUCCESS) { | |
33a9a57d YJ |
945 | if (fault_pte_addr) { |
946 | *fault_pte_addr = (base + idx * ptesize) >> 2; | |
947 | } | |
948 | return TRANSLATE_G_STAGE_FAIL; | |
88914473 | 949 | } |
36a18664 AF |
950 | |
951 | pte_addr = vbase + idx * ptesize; | |
952 | } else { | |
953 | pte_addr = base + idx * ptesize; | |
954 | } | |
1f447aec | 955 | |
b297129a | 956 | int pmp_prot; |
bfc7ee12 | 957 | int pmp_ret = get_physical_address_pmp(env, &pmp_prot, pte_addr, |
b297129a JS |
958 | sizeof(target_ulong), |
959 | MMU_DATA_LOAD, PRV_S); | |
960 | if (pmp_ret != TRANSLATE_SUCCESS) { | |
1f447aec HA |
961 | return TRANSLATE_PMP_FAIL; |
962 | } | |
aacb578f | 963 | |
db23e5d9 | 964 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
f08c7ff3 AF |
965 | pte = address_space_ldl(cs->as, pte_addr, attrs, &res); |
966 | } else { | |
967 | pte = address_space_ldq(cs->as, pte_addr, attrs, &res); | |
968 | } | |
969 | ||
aacb578f PD |
970 | if (res != MEMTX_OK) { |
971 | return TRANSLATE_FAIL; | |
972 | } | |
973 | ||
05e6ca5e GR |
974 | if (riscv_cpu_sxl(env) == MXL_RV32) { |
975 | ppn = pte >> PTE_PPN_SHIFT; | |
05e6ca5e | 976 | } else { |
190e9f8e AG |
977 | if (pte & PTE_RESERVED) { |
978 | return TRANSLATE_FAIL; | |
979 | } | |
980 | ||
981 | if (!pbmte && (pte & PTE_PBMT)) { | |
05e6ca5e GR |
982 | return TRANSLATE_FAIL; |
983 | } | |
190e9f8e AG |
984 | |
985 | if (!riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { | |
986 | return TRANSLATE_FAIL; | |
987 | } | |
988 | ||
989 | ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT; | |
05e6ca5e | 990 | } |
0c3e702a | 991 | |
c3b03e58 MC |
992 | if (!(pte & PTE_V)) { |
993 | /* Invalid PTE */ | |
994 | return TRANSLATE_FAIL; | |
59688aa0 RH |
995 | } |
996 | if (pte & (PTE_R | PTE_W | PTE_X)) { | |
997 | goto leaf; | |
998 | } | |
999 | ||
1000 | /* Inner PTE, continue walking */ | |
1001 | if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) { | |
c3b03e58 | 1002 | return TRANSLATE_FAIL; |
59688aa0 RH |
1003 | } |
1004 | base = ppn << PGSHIFT; | |
1005 | } | |
1006 | ||
1007 | /* No leaf pte at any translation level. */ | |
1008 | return TRANSLATE_FAIL; | |
1009 | ||
1010 | leaf: | |
1011 | if (ppn & ((1ULL << ptshift) - 1)) { | |
1012 | /* Misaligned PPN */ | |
1013 | return TRANSLATE_FAIL; | |
1014 | } | |
1015 | if (!pbmte && (pte & PTE_PBMT)) { | |
1016 | /* Reserved without Svpbmt. */ | |
1017 | return TRANSLATE_FAIL; | |
1018 | } | |
a9d2e3ed RH |
1019 | |
1020 | /* Check for reserved combinations of RWX flags. */ | |
1021 | switch (pte & (PTE_R | PTE_W | PTE_X)) { | |
1022 | case PTE_W: | |
1023 | case PTE_W | PTE_X: | |
59688aa0 RH |
1024 | return TRANSLATE_FAIL; |
1025 | } | |
a9d2e3ed | 1026 | |
e1dd1507 RH |
1027 | int prot = 0; |
1028 | if (pte & PTE_R) { | |
1029 | prot |= PAGE_READ; | |
1030 | } | |
1031 | if (pte & PTE_W) { | |
1032 | prot |= PAGE_WRITE; | |
1033 | } | |
1034 | if (pte & PTE_X) { | |
1035 | bool mxr; | |
1036 | ||
1037 | if (first_stage == true) { | |
1038 | mxr = get_field(env->mstatus, MSTATUS_MXR); | |
1039 | } else { | |
1040 | mxr = get_field(env->vsstatus, MSTATUS_MXR); | |
1041 | } | |
1042 | if (mxr) { | |
1043 | prot |= PAGE_READ; | |
1044 | } | |
1045 | prot |= PAGE_EXEC; | |
1046 | } | |
1047 | ||
38303e8a RH |
1048 | if (pte & PTE_U) { |
1049 | if (mode != PRV_U) { | |
1050 | if (!mmuidx_sum(mmu_idx)) { | |
1051 | return TRANSLATE_FAIL; | |
1052 | } | |
1053 | /* SUM allows only read+write, not execute. */ | |
1054 | prot &= PAGE_READ | PAGE_WRITE; | |
1055 | } | |
1056 | } else if (mode != PRV_S) { | |
59688aa0 RH |
1057 | /* Supervisor PTE flags when not S mode */ |
1058 | return TRANSLATE_FAIL; | |
1059 | } | |
e1dd1507 RH |
1060 | |
1061 | if (!((prot >> access_type) & 1)) { | |
1062 | /* Access check failed */ | |
59688aa0 RH |
1063 | return TRANSLATE_FAIL; |
1064 | } | |
1065 | ||
1066 | /* If necessary, set accessed and dirty bits. */ | |
1067 | target_ulong updated_pte = pte | PTE_A | | |
0c3e702a MC |
1068 | (access_type == MMU_DATA_STORE ? PTE_D : 0); |
1069 | ||
59688aa0 | 1070 | /* Page table updates need to be atomic with MTTCG enabled */ |
0a19bf5e | 1071 | if (updated_pte != pte && !is_debug) { |
ed67d637 | 1072 | if (!adue) { |
59688aa0 RH |
1073 | return TRANSLATE_FAIL; |
1074 | } | |
0af3f115 | 1075 | |
59688aa0 RH |
1076 | /* |
1077 | * - if accessed or dirty bits need updating, and the PTE is | |
1078 | * in RAM, then we do so atomically with a compare and swap. | |
1079 | * - if the PTE is in IO space or ROM, then it can't be updated | |
1080 | * and we return TRANSLATE_FAIL. | |
1081 | * - if the PTE changed by the time we went to update it, then | |
1082 | * it is no longer valid and we must re-walk the page table. | |
1083 | */ | |
1084 | MemoryRegion *mr; | |
1085 | hwaddr l = sizeof(target_ulong), addr1; | |
1086 | mr = address_space_translate(cs->as, pte_addr, &addr1, &l, | |
1087 | false, MEMTXATTRS_UNSPECIFIED); | |
1088 | if (memory_region_is_ram(mr)) { | |
1089 | target_ulong *pte_pa = qemu_map_ram_ptr(mr->ram_block, addr1); | |
0c3e702a | 1090 | #if TCG_OVERSIZED_GUEST |
59688aa0 RH |
1091 | /* |
1092 | * MTTCG is not enabled on oversized TCG guests so | |
1093 | * page table updates do not need to be atomic | |
1094 | */ | |
1095 | *pte_pa = pte = updated_pte; | |
0c3e702a | 1096 | #else |
59688aa0 RH |
1097 | target_ulong old_pte = qatomic_cmpxchg(pte_pa, pte, updated_pte); |
1098 | if (old_pte != pte) { | |
1099 | goto restart; | |
0c3e702a | 1100 | } |
59688aa0 RH |
1101 | pte = updated_pte; |
1102 | #endif | |
1103 | } else { | |
3b57254d | 1104 | /* |
59688aa0 RH |
1105 | * Misconfigured PTE in ROM (AD bits are not preset) or |
1106 | * PTE is in IO space and can't be updated atomically. | |
3b57254d | 1107 | */ |
59688aa0 RH |
1108 | return TRANSLATE_FAIL; |
1109 | } | |
1110 | } | |
2bacb224 | 1111 | |
59688aa0 RH |
1112 | /* For superpage mappings, make a fake leaf PTE for the TLB's benefit. */ |
1113 | target_ulong vpn = addr >> PGSHIFT; | |
0c3e702a | 1114 | |
59688aa0 RH |
1115 | if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { |
1116 | napot_bits = ctzl(ppn) + 1; | |
1117 | if ((i != (levels - 1)) || (napot_bits != 4)) { | |
1118 | return TRANSLATE_FAIL; | |
0c3e702a MC |
1119 | } |
1120 | } | |
59688aa0 RH |
1121 | |
1122 | napot_mask = (1 << napot_bits) - 1; | |
1123 | *physical = (((ppn & ~napot_mask) | (vpn & napot_mask) | | |
1124 | (vpn & (((target_ulong)1 << ptshift) - 1)) | |
1125 | ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK); | |
1126 | ||
59688aa0 | 1127 | /* |
e1dd1507 RH |
1128 | * Remove write permission unless this is a store, or the page is |
1129 | * already dirty, so that we TLB miss on later writes to update | |
1130 | * the dirty bit. | |
59688aa0 | 1131 | */ |
e1dd1507 RH |
1132 | if (access_type != MMU_DATA_STORE && !(pte & PTE_D)) { |
1133 | prot &= ~PAGE_WRITE; | |
59688aa0 | 1134 | } |
e1dd1507 RH |
1135 | *ret_prot = prot; |
1136 | ||
59688aa0 | 1137 | return TRANSLATE_SUCCESS; |
0c3e702a MC |
1138 | } |
1139 | ||
1140 | static void raise_mmu_exception(CPURISCVState *env, target_ulong address, | |
1448689c | 1141 | MMUAccessType access_type, bool pmp_violation, |
8e2aa21b AP |
1142 | bool first_stage, bool two_stage, |
1143 | bool two_stage_indirect) | |
0c3e702a | 1144 | { |
3109cd98 | 1145 | CPUState *cs = env_cpu(env); |
994b6bb2 | 1146 | |
0c3e702a MC |
1147 | switch (access_type) { |
1148 | case MMU_INST_FETCH: | |
38256529 | 1149 | if (env->virt_enabled && !first_stage) { |
b2ef6ab9 AF |
1150 | cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT; |
1151 | } else { | |
82d53adf IK |
1152 | cs->exception_index = pmp_violation ? |
1153 | RISCV_EXCP_INST_ACCESS_FAULT : RISCV_EXCP_INST_PAGE_FAULT; | |
b2ef6ab9 | 1154 | } |
0c3e702a MC |
1155 | break; |
1156 | case MMU_DATA_LOAD: | |
1c1c060a | 1157 | if (two_stage && !first_stage) { |
b2ef6ab9 AF |
1158 | cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; |
1159 | } else { | |
82d53adf IK |
1160 | cs->exception_index = pmp_violation ? |
1161 | RISCV_EXCP_LOAD_ACCESS_FAULT : RISCV_EXCP_LOAD_PAGE_FAULT; | |
b2ef6ab9 | 1162 | } |
0c3e702a MC |
1163 | break; |
1164 | case MMU_DATA_STORE: | |
1c1c060a | 1165 | if (two_stage && !first_stage) { |
b2ef6ab9 AF |
1166 | cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT; |
1167 | } else { | |
82d53adf IK |
1168 | cs->exception_index = pmp_violation ? |
1169 | RISCV_EXCP_STORE_AMO_ACCESS_FAULT : | |
1170 | RISCV_EXCP_STORE_PAGE_FAULT; | |
b2ef6ab9 | 1171 | } |
0c3e702a MC |
1172 | break; |
1173 | default: | |
1174 | g_assert_not_reached(); | |
1175 | } | |
1176 | env->badaddr = address; | |
ec352d0c | 1177 | env->two_stage_lookup = two_stage; |
8e2aa21b | 1178 | env->two_stage_indirect_lookup = two_stage_indirect; |
0c3e702a MC |
1179 | } |
1180 | ||
1181 | hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) | |
1182 | { | |
1183 | RISCVCPU *cpu = RISCV_CPU(cs); | |
36a18664 | 1184 | CPURISCVState *env = &cpu->env; |
0c3e702a MC |
1185 | hwaddr phys_addr; |
1186 | int prot; | |
1187 | int mmu_idx = cpu_mmu_index(&cpu->env, false); | |
1188 | ||
33a9a57d | 1189 | if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx, |
38256529 | 1190 | true, env->virt_enabled, true)) { |
0c3e702a MC |
1191 | return -1; |
1192 | } | |
36a18664 | 1193 | |
38256529 | 1194 | if (env->virt_enabled) { |
33a9a57d | 1195 | if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL, |
11c27c6d | 1196 | 0, mmu_idx, false, true, true)) { |
36a18664 AF |
1197 | return -1; |
1198 | } | |
1199 | } | |
1200 | ||
9ef82119 | 1201 | return phys_addr & TARGET_PAGE_MASK; |
0c3e702a MC |
1202 | } |
1203 | ||
37207e12 PD |
1204 | void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, |
1205 | vaddr addr, unsigned size, | |
1206 | MMUAccessType access_type, | |
1207 | int mmu_idx, MemTxAttrs attrs, | |
1208 | MemTxResult response, uintptr_t retaddr) | |
cbf58276 MC |
1209 | { |
1210 | RISCVCPU *cpu = RISCV_CPU(cs); | |
1211 | CPURISCVState *env = &cpu->env; | |
1212 | ||
37207e12 | 1213 | if (access_type == MMU_DATA_STORE) { |
cbf58276 | 1214 | cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; |
f9e580c1 | 1215 | } else if (access_type == MMU_DATA_LOAD) { |
cbf58276 | 1216 | cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; |
f9e580c1 EB |
1217 | } else { |
1218 | cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT; | |
cbf58276 MC |
1219 | } |
1220 | ||
1221 | env->badaddr = addr; | |
696bacde | 1222 | env->two_stage_lookup = mmuidx_2stage(mmu_idx); |
8e2aa21b | 1223 | env->two_stage_indirect_lookup = false; |
ac684717 | 1224 | cpu_loop_exit_restore(cs, retaddr); |
cbf58276 MC |
1225 | } |
1226 | ||
0c3e702a MC |
1227 | void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, |
1228 | MMUAccessType access_type, int mmu_idx, | |
1229 | uintptr_t retaddr) | |
1230 | { | |
1231 | RISCVCPU *cpu = RISCV_CPU(cs); | |
1232 | CPURISCVState *env = &cpu->env; | |
1233 | switch (access_type) { | |
1234 | case MMU_INST_FETCH: | |
1235 | cs->exception_index = RISCV_EXCP_INST_ADDR_MIS; | |
1236 | break; | |
1237 | case MMU_DATA_LOAD: | |
1238 | cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS; | |
1239 | break; | |
1240 | case MMU_DATA_STORE: | |
1241 | cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS; | |
1242 | break; | |
1243 | default: | |
1244 | g_assert_not_reached(); | |
1245 | } | |
1246 | env->badaddr = addr; | |
696bacde | 1247 | env->two_stage_lookup = mmuidx_2stage(mmu_idx); |
8e2aa21b | 1248 | env->two_stage_indirect_lookup = false; |
ac684717 | 1249 | cpu_loop_exit_restore(cs, retaddr); |
0c3e702a | 1250 | } |
0c3e702a | 1251 | |
892320fa AP |
1252 | |
1253 | static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type) | |
1254 | { | |
1255 | enum riscv_pmu_event_idx pmu_event_type; | |
1256 | ||
1257 | switch (access_type) { | |
1258 | case MMU_INST_FETCH: | |
1259 | pmu_event_type = RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS; | |
1260 | break; | |
1261 | case MMU_DATA_LOAD: | |
1262 | pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS; | |
1263 | break; | |
1264 | case MMU_DATA_STORE: | |
1265 | pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS; | |
1266 | break; | |
1267 | default: | |
1268 | return; | |
1269 | } | |
1270 | ||
1271 | riscv_pmu_incr_ctr(cpu, pmu_event_type); | |
1272 | } | |
1273 | ||
8a4ca3c1 RH |
1274 | bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
1275 | MMUAccessType access_type, int mmu_idx, | |
1276 | bool probe, uintptr_t retaddr) | |
0c3e702a MC |
1277 | { |
1278 | RISCVCPU *cpu = RISCV_CPU(cs); | |
1279 | CPURISCVState *env = &cpu->env; | |
36a18664 | 1280 | vaddr im_address; |
0c3e702a | 1281 | hwaddr pa = 0; |
b297129a | 1282 | int prot, prot2, prot_pmp; |
635b0b0e | 1283 | bool pmp_violation = false; |
36a18664 | 1284 | bool first_stage_error = true; |
696bacde | 1285 | bool two_stage_lookup = mmuidx_2stage(mmu_idx); |
8e2aa21b | 1286 | bool two_stage_indirect_error = false; |
0c3e702a | 1287 | int ret = TRANSLATE_FAIL; |
cc0fdb29 | 1288 | int mode = mmu_idx; |
b297129a JS |
1289 | /* default TLB page size */ |
1290 | target_ulong tlb_size = TARGET_PAGE_SIZE; | |
0c3e702a | 1291 | |
36a18664 AF |
1292 | env->guest_phys_fault_addr = 0; |
1293 | ||
8a4ca3c1 RH |
1294 | qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", |
1295 | __func__, address, access_type, mmu_idx); | |
1296 | ||
eacd03cb | 1297 | pmu_tlb_fill_incr_ctr(cpu, access_type); |
696bacde | 1298 | if (two_stage_lookup) { |
36a18664 | 1299 | /* Two stage lookup */ |
33a9a57d YJ |
1300 | ret = get_physical_address(env, &pa, &prot, address, |
1301 | &env->guest_phys_fault_addr, access_type, | |
11c27c6d | 1302 | mmu_idx, true, true, false); |
36a18664 | 1303 | |
33a9a57d YJ |
1304 | /* |
1305 | * A G-stage exception may be triggered during two state lookup. | |
1306 | * And the env->guest_phys_fault_addr has already been set in | |
1307 | * get_physical_address(). | |
1308 | */ | |
1309 | if (ret == TRANSLATE_G_STAGE_FAIL) { | |
1310 | first_stage_error = false; | |
8e2aa21b | 1311 | two_stage_indirect_error = true; |
33a9a57d YJ |
1312 | } |
1313 | ||
36a18664 AF |
1314 | qemu_log_mask(CPU_LOG_MMU, |
1315 | "%s 1st-stage address=%" VADDR_PRIx " ret %d physical " | |
883f2c59 | 1316 | HWADDR_FMT_plx " prot %d\n", |
36a18664 AF |
1317 | __func__, address, ret, pa, prot); |
1318 | ||
33a9a57d | 1319 | if (ret == TRANSLATE_SUCCESS) { |
36a18664 AF |
1320 | /* Second stage lookup */ |
1321 | im_address = pa; | |
1322 | ||
33a9a57d | 1323 | ret = get_physical_address(env, &pa, &prot2, im_address, NULL, |
a427c836 | 1324 | access_type, MMUIdx_U, false, true, |
11c27c6d | 1325 | false); |
36a18664 AF |
1326 | |
1327 | qemu_log_mask(CPU_LOG_MMU, | |
c45eff30 WL |
1328 | "%s 2nd-stage address=%" VADDR_PRIx |
1329 | " ret %d physical " | |
1330 | HWADDR_FMT_plx " prot %d\n", | |
1331 | __func__, im_address, ret, pa, prot2); | |
8f67cd6d AF |
1332 | |
1333 | prot &= prot2; | |
36a18664 | 1334 | |
b297129a | 1335 | if (ret == TRANSLATE_SUCCESS) { |
bfc7ee12 | 1336 | ret = get_physical_address_pmp(env, &prot_pmp, pa, |
b297129a | 1337 | size, access_type, mode); |
bfc7ee12 | 1338 | tlb_size = pmp_get_tlb_size(env, pa); |
663e1193 JS |
1339 | |
1340 | qemu_log_mask(CPU_LOG_MMU, | |
883f2c59 | 1341 | "%s PMP address=" HWADDR_FMT_plx " ret %d prot" |
663e1193 JS |
1342 | " %d tlb_size " TARGET_FMT_lu "\n", |
1343 | __func__, pa, ret, prot_pmp, tlb_size); | |
1344 | ||
b297129a | 1345 | prot &= prot_pmp; |
36a18664 AF |
1346 | } |
1347 | ||
1348 | if (ret != TRANSLATE_SUCCESS) { | |
1349 | /* | |
1350 | * Guest physical address translation failed, this is a HS | |
1351 | * level exception | |
1352 | */ | |
1353 | first_stage_error = false; | |
1354 | env->guest_phys_fault_addr = (im_address | | |
1355 | (address & | |
1356 | (TARGET_PAGE_SIZE - 1))) >> 2; | |
1357 | } | |
1358 | } | |
1359 | } else { | |
1360 | /* Single stage lookup */ | |
33a9a57d | 1361 | ret = get_physical_address(env, &pa, &prot, address, NULL, |
11c27c6d | 1362 | access_type, mmu_idx, true, false, false); |
36a18664 AF |
1363 | |
1364 | qemu_log_mask(CPU_LOG_MMU, | |
1365 | "%s address=%" VADDR_PRIx " ret %d physical " | |
883f2c59 | 1366 | HWADDR_FMT_plx " prot %d\n", |
36a18664 | 1367 | __func__, address, ret, pa, prot); |
8a4ca3c1 | 1368 | |
b297129a | 1369 | if (ret == TRANSLATE_SUCCESS) { |
bfc7ee12 | 1370 | ret = get_physical_address_pmp(env, &prot_pmp, pa, |
b297129a | 1371 | size, access_type, mode); |
bfc7ee12 | 1372 | tlb_size = pmp_get_tlb_size(env, pa); |
663e1193 JS |
1373 | |
1374 | qemu_log_mask(CPU_LOG_MMU, | |
883f2c59 | 1375 | "%s PMP address=" HWADDR_FMT_plx " ret %d prot" |
663e1193 JS |
1376 | " %d tlb_size " TARGET_FMT_lu "\n", |
1377 | __func__, pa, ret, prot_pmp, tlb_size); | |
1378 | ||
b297129a JS |
1379 | prot &= prot_pmp; |
1380 | } | |
1f447aec | 1381 | } |
b297129a | 1382 | |
1f447aec | 1383 | if (ret == TRANSLATE_PMP_FAIL) { |
635b0b0e | 1384 | pmp_violation = true; |
0c3e702a | 1385 | } |
36a18664 | 1386 | |
0c3e702a | 1387 | if (ret == TRANSLATE_SUCCESS) { |
b297129a JS |
1388 | tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1), |
1389 | prot, mmu_idx, tlb_size); | |
8a4ca3c1 RH |
1390 | return true; |
1391 | } else if (probe) { | |
1392 | return false; | |
1393 | } else { | |
1c1c060a | 1394 | raise_mmu_exception(env, address, access_type, pmp_violation, |
696bacde | 1395 | first_stage_error, two_stage_lookup, |
8e2aa21b | 1396 | two_stage_indirect_error); |
ac684717 | 1397 | cpu_loop_exit_restore(cs, retaddr); |
0c3e702a | 1398 | } |
36a18664 AF |
1399 | |
1400 | return true; | |
0c3e702a | 1401 | } |
8e2aa21b AP |
1402 | |
1403 | static target_ulong riscv_transformed_insn(CPURISCVState *env, | |
1404 | target_ulong insn, | |
1405 | target_ulong taddr) | |
1406 | { | |
1407 | target_ulong xinsn = 0; | |
1408 | target_ulong access_rs1 = 0, access_imm = 0, access_size = 0; | |
1409 | ||
1410 | /* | |
1411 | * Only Quadrant 0 and Quadrant 2 of RVC instruction space need to | |
1412 | * be uncompressed. The Quadrant 1 of RVC instruction space need | |
1413 | * not be transformed because these instructions won't generate | |
1414 | * any load/store trap. | |
1415 | */ | |
1416 | ||
1417 | if ((insn & 0x3) != 0x3) { | |
1418 | /* Transform 16bit instruction into 32bit instruction */ | |
1419 | switch (GET_C_OP(insn)) { | |
1420 | case OPC_RISC_C_OP_QUAD0: /* Quadrant 0 */ | |
1421 | switch (GET_C_FUNC(insn)) { | |
1422 | case OPC_RISC_C_FUNC_FLD_LQ: | |
1423 | if (riscv_cpu_xlen(env) != 128) { /* C.FLD (RV32/64) */ | |
1424 | xinsn = OPC_RISC_FLD; | |
1425 | xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); | |
1426 | access_rs1 = GET_C_RS1S(insn); | |
1427 | access_imm = GET_C_LD_IMM(insn); | |
1428 | access_size = 8; | |
1429 | } | |
1430 | break; | |
1431 | case OPC_RISC_C_FUNC_LW: /* C.LW */ | |
1432 | xinsn = OPC_RISC_LW; | |
1433 | xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); | |
1434 | access_rs1 = GET_C_RS1S(insn); | |
1435 | access_imm = GET_C_LW_IMM(insn); | |
1436 | access_size = 4; | |
1437 | break; | |
1438 | case OPC_RISC_C_FUNC_FLW_LD: | |
1439 | if (riscv_cpu_xlen(env) == 32) { /* C.FLW (RV32) */ | |
1440 | xinsn = OPC_RISC_FLW; | |
1441 | xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); | |
1442 | access_rs1 = GET_C_RS1S(insn); | |
1443 | access_imm = GET_C_LW_IMM(insn); | |
1444 | access_size = 4; | |
1445 | } else { /* C.LD (RV64/RV128) */ | |
1446 | xinsn = OPC_RISC_LD; | |
1447 | xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); | |
1448 | access_rs1 = GET_C_RS1S(insn); | |
1449 | access_imm = GET_C_LD_IMM(insn); | |
1450 | access_size = 8; | |
1451 | } | |
1452 | break; | |
1453 | case OPC_RISC_C_FUNC_FSD_SQ: | |
1454 | if (riscv_cpu_xlen(env) != 128) { /* C.FSD (RV32/64) */ | |
1455 | xinsn = OPC_RISC_FSD; | |
1456 | xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); | |
1457 | access_rs1 = GET_C_RS1S(insn); | |
1458 | access_imm = GET_C_SD_IMM(insn); | |
1459 | access_size = 8; | |
1460 | } | |
1461 | break; | |
1462 | case OPC_RISC_C_FUNC_SW: /* C.SW */ | |
1463 | xinsn = OPC_RISC_SW; | |
1464 | xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); | |
1465 | access_rs1 = GET_C_RS1S(insn); | |
1466 | access_imm = GET_C_SW_IMM(insn); | |
1467 | access_size = 4; | |
1468 | break; | |
1469 | case OPC_RISC_C_FUNC_FSW_SD: | |
1470 | if (riscv_cpu_xlen(env) == 32) { /* C.FSW (RV32) */ | |
1471 | xinsn = OPC_RISC_FSW; | |
1472 | xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); | |
1473 | access_rs1 = GET_C_RS1S(insn); | |
1474 | access_imm = GET_C_SW_IMM(insn); | |
1475 | access_size = 4; | |
1476 | } else { /* C.SD (RV64/RV128) */ | |
1477 | xinsn = OPC_RISC_SD; | |
1478 | xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); | |
1479 | access_rs1 = GET_C_RS1S(insn); | |
1480 | access_imm = GET_C_SD_IMM(insn); | |
1481 | access_size = 8; | |
1482 | } | |
1483 | break; | |
1484 | default: | |
1485 | break; | |
1486 | } | |
1487 | break; | |
1488 | case OPC_RISC_C_OP_QUAD2: /* Quadrant 2 */ | |
1489 | switch (GET_C_FUNC(insn)) { | |
1490 | case OPC_RISC_C_FUNC_FLDSP_LQSP: | |
1491 | if (riscv_cpu_xlen(env) != 128) { /* C.FLDSP (RV32/64) */ | |
1492 | xinsn = OPC_RISC_FLD; | |
1493 | xinsn = SET_RD(xinsn, GET_C_RD(insn)); | |
1494 | access_rs1 = 2; | |
1495 | access_imm = GET_C_LDSP_IMM(insn); | |
1496 | access_size = 8; | |
1497 | } | |
1498 | break; | |
1499 | case OPC_RISC_C_FUNC_LWSP: /* C.LWSP */ | |
1500 | xinsn = OPC_RISC_LW; | |
1501 | xinsn = SET_RD(xinsn, GET_C_RD(insn)); | |
1502 | access_rs1 = 2; | |
1503 | access_imm = GET_C_LWSP_IMM(insn); | |
1504 | access_size = 4; | |
1505 | break; | |
1506 | case OPC_RISC_C_FUNC_FLWSP_LDSP: | |
1507 | if (riscv_cpu_xlen(env) == 32) { /* C.FLWSP (RV32) */ | |
1508 | xinsn = OPC_RISC_FLW; | |
1509 | xinsn = SET_RD(xinsn, GET_C_RD(insn)); | |
1510 | access_rs1 = 2; | |
1511 | access_imm = GET_C_LWSP_IMM(insn); | |
1512 | access_size = 4; | |
1513 | } else { /* C.LDSP (RV64/RV128) */ | |
1514 | xinsn = OPC_RISC_LD; | |
1515 | xinsn = SET_RD(xinsn, GET_C_RD(insn)); | |
1516 | access_rs1 = 2; | |
1517 | access_imm = GET_C_LDSP_IMM(insn); | |
1518 | access_size = 8; | |
1519 | } | |
1520 | break; | |
1521 | case OPC_RISC_C_FUNC_FSDSP_SQSP: | |
1522 | if (riscv_cpu_xlen(env) != 128) { /* C.FSDSP (RV32/64) */ | |
1523 | xinsn = OPC_RISC_FSD; | |
1524 | xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); | |
1525 | access_rs1 = 2; | |
1526 | access_imm = GET_C_SDSP_IMM(insn); | |
1527 | access_size = 8; | |
1528 | } | |
1529 | break; | |
1530 | case OPC_RISC_C_FUNC_SWSP: /* C.SWSP */ | |
1531 | xinsn = OPC_RISC_SW; | |
1532 | xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); | |
1533 | access_rs1 = 2; | |
1534 | access_imm = GET_C_SWSP_IMM(insn); | |
1535 | access_size = 4; | |
1536 | break; | |
1537 | case 7: | |
1538 | if (riscv_cpu_xlen(env) == 32) { /* C.FSWSP (RV32) */ | |
1539 | xinsn = OPC_RISC_FSW; | |
1540 | xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); | |
1541 | access_rs1 = 2; | |
1542 | access_imm = GET_C_SWSP_IMM(insn); | |
1543 | access_size = 4; | |
1544 | } else { /* C.SDSP (RV64/RV128) */ | |
1545 | xinsn = OPC_RISC_SD; | |
1546 | xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); | |
1547 | access_rs1 = 2; | |
1548 | access_imm = GET_C_SDSP_IMM(insn); | |
1549 | access_size = 8; | |
1550 | } | |
1551 | break; | |
1552 | default: | |
1553 | break; | |
1554 | } | |
1555 | break; | |
1556 | default: | |
1557 | break; | |
1558 | } | |
1559 | ||
1560 | /* | |
1561 | * Clear Bit1 of transformed instruction to indicate that | |
1562 | * original insruction was a 16bit instruction | |
1563 | */ | |
1564 | xinsn &= ~((target_ulong)0x2); | |
1565 | } else { | |
1566 | /* Transform 32bit (or wider) instructions */ | |
1567 | switch (MASK_OP_MAJOR(insn)) { | |
1568 | case OPC_RISC_ATOMIC: | |
1569 | xinsn = insn; | |
1570 | access_rs1 = GET_RS1(insn); | |
1571 | access_size = 1 << GET_FUNCT3(insn); | |
1572 | break; | |
1573 | case OPC_RISC_LOAD: | |
1574 | case OPC_RISC_FP_LOAD: | |
1575 | xinsn = SET_I_IMM(insn, 0); | |
1576 | access_rs1 = GET_RS1(insn); | |
1577 | access_imm = GET_IMM(insn); | |
1578 | access_size = 1 << GET_FUNCT3(insn); | |
1579 | break; | |
1580 | case OPC_RISC_STORE: | |
1581 | case OPC_RISC_FP_STORE: | |
1582 | xinsn = SET_S_IMM(insn, 0); | |
1583 | access_rs1 = GET_RS1(insn); | |
1584 | access_imm = GET_STORE_IMM(insn); | |
1585 | access_size = 1 << GET_FUNCT3(insn); | |
1586 | break; | |
1587 | case OPC_RISC_SYSTEM: | |
1588 | if (MASK_OP_SYSTEM(insn) == OPC_RISC_HLVHSV) { | |
1589 | xinsn = insn; | |
1590 | access_rs1 = GET_RS1(insn); | |
1591 | access_size = 1 << ((GET_FUNCT7(insn) >> 1) & 0x3); | |
1592 | access_size = 1 << access_size; | |
1593 | } | |
1594 | break; | |
1595 | default: | |
1596 | break; | |
1597 | } | |
1598 | } | |
1599 | ||
1600 | if (access_size) { | |
1601 | xinsn = SET_RS1(xinsn, (taddr - (env->gpr[access_rs1] + access_imm)) & | |
1602 | (access_size - 1)); | |
1603 | } | |
1604 | ||
1605 | return xinsn; | |
1606 | } | |
263e2ab2 | 1607 | #endif /* !CONFIG_USER_ONLY */ |
0c3e702a MC |
1608 | |
1609 | /* | |
1610 | * Handle Traps | |
1611 | * | |
1612 | * Adapted from Spike's processor_t::take_trap. | |
1613 | * | |
1614 | */ | |
1615 | void riscv_cpu_do_interrupt(CPUState *cs) | |
1616 | { | |
1617 | #if !defined(CONFIG_USER_ONLY) | |
1618 | ||
1619 | RISCVCPU *cpu = RISCV_CPU(cs); | |
1620 | CPURISCVState *env = &cpu->env; | |
86d0c457 | 1621 | bool write_gva = false; |
284d697c | 1622 | uint64_t s; |
0c3e702a | 1623 | |
3b57254d WL |
1624 | /* |
1625 | * cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide | |
acbbb94e MC |
1626 | * so we mask off the MSB and separate into trap type and cause. |
1627 | */ | |
1628 | bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG); | |
1629 | target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; | |
d028ac75 | 1630 | uint64_t deleg = async ? env->mideleg : env->medeleg; |
1697837e RK |
1631 | bool s_injected = env->mvip & (1 << cause) & env->mvien && |
1632 | !(env->mip & (1 << cause)); | |
40336d5b RK |
1633 | bool vs_injected = env->hvip & (1 << cause) & env->hvien && |
1634 | !(env->mip & (1 << cause)); | |
acbbb94e | 1635 | target_ulong tval = 0; |
8e2aa21b | 1636 | target_ulong tinst = 0; |
30675539 AF |
1637 | target_ulong htval = 0; |
1638 | target_ulong mtval2 = 0; | |
acbbb94e | 1639 | |
acbbb94e MC |
1640 | if (!async) { |
1641 | /* set tval to badaddr for traps with address information */ | |
1642 | switch (cause) { | |
d17bcae5 RK |
1643 | case RISCV_EXCP_SEMIHOST: |
1644 | do_common_semihosting(cs); | |
1645 | env->pc += 4; | |
1646 | return; | |
ab67a1d0 AF |
1647 | case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: |
1648 | case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: | |
acbbb94e MC |
1649 | case RISCV_EXCP_LOAD_ADDR_MIS: |
1650 | case RISCV_EXCP_STORE_AMO_ADDR_MIS: | |
1651 | case RISCV_EXCP_LOAD_ACCESS_FAULT: | |
1652 | case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: | |
acbbb94e MC |
1653 | case RISCV_EXCP_LOAD_PAGE_FAULT: |
1654 | case RISCV_EXCP_STORE_PAGE_FAULT: | |
24826da0 | 1655 | write_gva = env->two_stage_lookup; |
acbbb94e | 1656 | tval = env->badaddr; |
8e2aa21b AP |
1657 | if (env->two_stage_indirect_lookup) { |
1658 | /* | |
1659 | * special pseudoinstruction for G-stage fault taken while | |
1660 | * doing VS-stage page table walk. | |
1661 | */ | |
1662 | tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000; | |
1663 | } else { | |
1664 | /* | |
1665 | * The "Addr. Offset" field in transformed instruction is | |
1666 | * non-zero only for misaligned access. | |
1667 | */ | |
1668 | tinst = riscv_transformed_insn(env, env->bins, tval); | |
1669 | } | |
1670 | break; | |
1671 | case RISCV_EXCP_INST_GUEST_PAGE_FAULT: | |
1672 | case RISCV_EXCP_INST_ADDR_MIS: | |
1673 | case RISCV_EXCP_INST_ACCESS_FAULT: | |
1674 | case RISCV_EXCP_INST_PAGE_FAULT: | |
1675 | write_gva = env->two_stage_lookup; | |
1676 | tval = env->badaddr; | |
1677 | if (env->two_stage_indirect_lookup) { | |
1678 | /* | |
1679 | * special pseudoinstruction for G-stage fault taken while | |
1680 | * doing VS-stage page table walk. | |
1681 | */ | |
1682 | tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000; | |
1683 | } | |
acbbb94e | 1684 | break; |
48eaeb56 | 1685 | case RISCV_EXCP_ILLEGAL_INST: |
62cf0245 | 1686 | case RISCV_EXCP_VIRT_INSTRUCTION_FAULT: |
48eaeb56 AF |
1687 | tval = env->bins; |
1688 | break; | |
26934f9a SM |
1689 | case RISCV_EXCP_BREAKPOINT: |
1690 | if (cs->watchpoint_hit) { | |
1691 | tval = cs->watchpoint_hit->hitaddr; | |
1692 | cs->watchpoint_hit = NULL; | |
1693 | } | |
1694 | break; | |
acbbb94e MC |
1695 | default: |
1696 | break; | |
0c3e702a | 1697 | } |
acbbb94e MC |
1698 | /* ecall is dispatched as one cause so translate based on mode */ |
1699 | if (cause == RISCV_EXCP_U_ECALL) { | |
1700 | assert(env->priv <= 3); | |
5eb9e782 AF |
1701 | |
1702 | if (env->priv == PRV_M) { | |
1703 | cause = RISCV_EXCP_M_ECALL; | |
38256529 | 1704 | } else if (env->priv == PRV_S && env->virt_enabled) { |
5eb9e782 | 1705 | cause = RISCV_EXCP_VS_ECALL; |
38256529 | 1706 | } else if (env->priv == PRV_S && !env->virt_enabled) { |
5eb9e782 AF |
1707 | cause = RISCV_EXCP_S_ECALL; |
1708 | } else if (env->priv == PRV_U) { | |
1709 | cause = RISCV_EXCP_U_ECALL; | |
1710 | } | |
0c3e702a MC |
1711 | } |
1712 | } | |
1713 | ||
c51a3f5d | 1714 | trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, |
69430111 AF |
1715 | riscv_cpu_get_trap_name(cause, async)); |
1716 | ||
1717 | qemu_log_mask(CPU_LOG_INT, | |
1718 | "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", " | |
1719 | "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n", | |
1720 | __func__, env->mhartid, async, cause, env->pc, tval, | |
1721 | riscv_cpu_get_trap_name(cause, async)); | |
0c3e702a | 1722 | |
1697837e | 1723 | if (env->priv <= PRV_S && cause < 64 && |
40336d5b | 1724 | (((deleg >> cause) & 1) || s_injected || vs_injected)) { |
0c3e702a | 1725 | /* handle the trap in S-mode */ |
5eb9e782 | 1726 | if (riscv_has_ext(env, RVH)) { |
d028ac75 | 1727 | uint64_t hdeleg = async ? env->hideleg : env->hedeleg; |
1c1c060a | 1728 | |
40336d5b RK |
1729 | if (env->virt_enabled && |
1730 | (((hdeleg >> cause) & 1) || vs_injected)) { | |
84b1c04b | 1731 | /* Trap to VS mode */ |
c5969a3a RK |
1732 | /* |
1733 | * See if we need to adjust cause. Yes if its VS mode interrupt | |
1734 | * no if hypervisor has delegated one of hs mode's interrupt | |
1735 | */ | |
1736 | if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || | |
84b1c04b | 1737 | cause == IRQ_VS_EXT) { |
c5969a3a | 1738 | cause = cause - 1; |
84b1c04b | 1739 | } |
86d0c457 | 1740 | write_gva = false; |
38256529 | 1741 | } else if (env->virt_enabled) { |
5eb9e782 AF |
1742 | /* Trap into HS mode, from virt */ |
1743 | riscv_cpu_swap_hypervisor_regs(env); | |
f2d5850f | 1744 | env->hstatus = set_field(env->hstatus, HSTATUS_SPVP, |
ace54453 | 1745 | env->priv); |
2136b6c3 | 1746 | env->hstatus = set_field(env->hstatus, HSTATUS_SPV, true); |
86d0c457 | 1747 | |
30675539 AF |
1748 | htval = env->guest_phys_fault_addr; |
1749 | ||
5eb9e782 | 1750 | riscv_cpu_set_virt_enabled(env, 0); |
5eb9e782 AF |
1751 | } else { |
1752 | /* Trap into HS mode */ | |
ec352d0c | 1753 | env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false); |
30675539 | 1754 | htval = env->guest_phys_fault_addr; |
5eb9e782 | 1755 | } |
86d0c457 | 1756 | env->hstatus = set_field(env->hstatus, HSTATUS_GVA, write_gva); |
5eb9e782 AF |
1757 | } |
1758 | ||
1759 | s = env->mstatus; | |
1a9540d1 | 1760 | s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); |
0c3e702a MC |
1761 | s = set_field(s, MSTATUS_SPP, env->priv); |
1762 | s = set_field(s, MSTATUS_SIE, 0); | |
c7b95171 | 1763 | env->mstatus = s; |
16fdb8ff | 1764 | env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1)); |
acbbb94e | 1765 | env->sepc = env->pc; |
ac12b601 | 1766 | env->stval = tval; |
30675539 | 1767 | env->htval = htval; |
8e2aa21b | 1768 | env->htinst = tinst; |
acbbb94e | 1769 | env->pc = (env->stvec >> 2 << 2) + |
c45eff30 | 1770 | ((async && (env->stvec & 3) == 1) ? cause * 4 : 0); |
fb738839 | 1771 | riscv_cpu_set_mode(env, PRV_S); |
0c3e702a | 1772 | } else { |
acbbb94e | 1773 | /* handle the trap in M-mode */ |
5eb9e782 | 1774 | if (riscv_has_ext(env, RVH)) { |
38256529 | 1775 | if (env->virt_enabled) { |
5eb9e782 AF |
1776 | riscv_cpu_swap_hypervisor_regs(env); |
1777 | } | |
1778 | env->mstatus = set_field(env->mstatus, MSTATUS_MPV, | |
38256529 WL |
1779 | env->virt_enabled); |
1780 | if (env->virt_enabled && tval) { | |
9034e90a AF |
1781 | env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1); |
1782 | } | |
5eb9e782 | 1783 | |
30675539 AF |
1784 | mtval2 = env->guest_phys_fault_addr; |
1785 | ||
5eb9e782 AF |
1786 | /* Trapping to M mode, virt is disabled */ |
1787 | riscv_cpu_set_virt_enabled(env, 0); | |
5eb9e782 AF |
1788 | } |
1789 | ||
1790 | s = env->mstatus; | |
1a9540d1 | 1791 | s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); |
0c3e702a MC |
1792 | s = set_field(s, MSTATUS_MPP, env->priv); |
1793 | s = set_field(s, MSTATUS_MIE, 0); | |
c7b95171 | 1794 | env->mstatus = s; |
acbbb94e MC |
1795 | env->mcause = cause | ~(((target_ulong)-1) >> async); |
1796 | env->mepc = env->pc; | |
ac12b601 | 1797 | env->mtval = tval; |
30675539 | 1798 | env->mtval2 = mtval2; |
8e2aa21b | 1799 | env->mtinst = tinst; |
acbbb94e | 1800 | env->pc = (env->mtvec >> 2 << 2) + |
c45eff30 | 1801 | ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); |
fb738839 | 1802 | riscv_cpu_set_mode(env, PRV_M); |
0c3e702a | 1803 | } |
d9360e96 | 1804 | |
3b57254d WL |
1805 | /* |
1806 | * NOTE: it is not necessary to yield load reservations here. It is only | |
d9360e96 MC |
1807 | * necessary for an SC from "another hart" to cause a load reservation |
1808 | * to be yielded. Refer to the memory consistency model section of the | |
1809 | * RISC-V ISA Specification. | |
1810 | */ | |
1811 | ||
ec352d0c | 1812 | env->two_stage_lookup = false; |
8e2aa21b | 1813 | env->two_stage_indirect_lookup = false; |
0c3e702a | 1814 | #endif |
330d2ae3 | 1815 | cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */ |
0c3e702a | 1816 | } |