]>
Commit | Line | Data |
---|---|---|
0c3e702a | 1 | /* |
df354dd4 | 2 | * RISC-V CPU helpers for qemu. |
0c3e702a MC |
3 | * |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
21 | #include "qemu/log.h" | |
7ec5d303 | 22 | #include "qemu/main-loop.h" |
0c3e702a MC |
23 | #include "cpu.h" |
24 | #include "exec/exec-all.h" | |
dcb32f1d | 25 | #include "tcg/tcg-op.h" |
929f0a7f | 26 | #include "trace.h" |
6b5fe137 | 27 | #include "semihosting/common-semi.h" |
0c3e702a MC |
28 | |
29 | int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) | |
30 | { | |
31 | #ifdef CONFIG_USER_ONLY | |
32 | return 0; | |
33 | #else | |
34 | return env->priv; | |
35 | #endif | |
36 | } | |
37 | ||
53677acf RH |
38 | void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, |
39 | target_ulong *cs_base, uint32_t *pflags) | |
40 | { | |
b4a99d40 FC |
41 | CPUState *cs = env_cpu(env); |
42 | RISCVCPU *cpu = RISCV_CPU(cs); | |
43 | ||
53677acf RH |
44 | uint32_t flags = 0; |
45 | ||
8c796f1a | 46 | *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc; |
53677acf RH |
47 | *cs_base = 0; |
48 | ||
32e579b8 | 49 | if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) { |
a689a82b FC |
50 | /* |
51 | * If env->vl equals to VLMAX, we can use generic vector operation | |
52 | * expanders (GVEC) to accerlate the vector operations. | |
53 | * However, as LMUL could be a fractional number. The maximum | |
54 | * vector size can be operated might be less than 8 bytes, | |
55 | * which is not supported by GVEC. So we set vl_eq_vlmax flag to true | |
56 | * only when maxsz >= 8 bytes. | |
57 | */ | |
53677acf | 58 | uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype); |
a689a82b FC |
59 | uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW); |
60 | uint32_t maxsz = vlmax << sew; | |
61 | bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) && | |
62 | (maxsz >= 8); | |
d96a271a | 63 | flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); |
a689a82b | 64 | flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew); |
53677acf RH |
65 | flags = FIELD_DP32(flags, TB_FLAGS, LMUL, |
66 | FIELD_EX64(env->vtype, VTYPE, VLMUL)); | |
67 | flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); | |
68 | } else { | |
69 | flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); | |
70 | } | |
71 | ||
72 | #ifdef CONFIG_USER_ONLY | |
73 | flags |= TB_FLAGS_MSTATUS_FS; | |
61b4b69d | 74 | flags |= TB_FLAGS_MSTATUS_VS; |
53677acf RH |
75 | #else |
76 | flags |= cpu_mmu_index(env, 0); | |
77 | if (riscv_cpu_fp_enabled(env)) { | |
78 | flags |= env->mstatus & MSTATUS_FS; | |
79 | } | |
80 | ||
61b4b69d LZ |
81 | if (riscv_cpu_vector_enabled(env)) { |
82 | flags |= env->mstatus & MSTATUS_VS; | |
83 | } | |
84 | ||
53677acf RH |
85 | if (riscv_has_ext(env, RVH)) { |
86 | if (env->priv == PRV_M || | |
87 | (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || | |
88 | (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && | |
89 | get_field(env->hstatus, HSTATUS_HU))) { | |
90 | flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); | |
91 | } | |
92 | ||
93 | flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, | |
94 | get_field(env->mstatus_hs, MSTATUS_FS)); | |
8e1ee1fb FC |
95 | |
96 | flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS, | |
97 | get_field(env->mstatus_hs, MSTATUS_VS)); | |
53677acf RH |
98 | } |
99 | #endif | |
100 | ||
440544e1 | 101 | flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl); |
4208dc7e LZ |
102 | if (env->cur_pmmask < (env->xl == MXL_RV32 ? UINT32_MAX : UINT64_MAX)) { |
103 | flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); | |
104 | } | |
105 | if (env->cur_pmbase != 0) { | |
106 | flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1); | |
107 | } | |
92371bd9 | 108 | |
53677acf RH |
109 | *pflags = flags; |
110 | } | |
111 | ||
40bfa5f6 LZ |
112 | void riscv_cpu_update_mask(CPURISCVState *env) |
113 | { | |
114 | target_ulong mask = -1, base = 0; | |
115 | /* | |
116 | * TODO: Current RVJ spec does not specify | |
117 | * how the extension interacts with XLEN. | |
118 | */ | |
119 | #ifndef CONFIG_USER_ONLY | |
120 | if (riscv_has_ext(env, RVJ)) { | |
121 | switch (env->priv) { | |
122 | case PRV_M: | |
123 | if (env->mmte & M_PM_ENABLE) { | |
124 | mask = env->mpmmask; | |
125 | base = env->mpmbase; | |
126 | } | |
127 | break; | |
128 | case PRV_S: | |
129 | if (env->mmte & S_PM_ENABLE) { | |
130 | mask = env->spmmask; | |
131 | base = env->spmbase; | |
132 | } | |
133 | break; | |
134 | case PRV_U: | |
135 | if (env->mmte & U_PM_ENABLE) { | |
136 | mask = env->upmmask; | |
137 | base = env->upmbase; | |
138 | } | |
139 | break; | |
140 | default: | |
141 | g_assert_not_reached(); | |
142 | } | |
143 | } | |
144 | #endif | |
145 | if (env->xl == MXL_RV32) { | |
146 | env->cur_pmmask = mask & UINT32_MAX; | |
147 | env->cur_pmbase = base & UINT32_MAX; | |
148 | } else { | |
149 | env->cur_pmmask = mask; | |
150 | env->cur_pmbase = base; | |
151 | } | |
152 | } | |
153 | ||
0c3e702a | 154 | #ifndef CONFIG_USER_ONLY |
43dc93af AP |
155 | |
156 | /* | |
157 | * The HS-mode is allowed to configure priority only for the | |
158 | * following VS-mode local interrupts: | |
159 | * | |
160 | * 0 (Reserved interrupt, reads as zero) | |
161 | * 1 Supervisor software interrupt | |
162 | * 4 (Reserved interrupt, reads as zero) | |
163 | * 5 Supervisor timer interrupt | |
164 | * 8 (Reserved interrupt, reads as zero) | |
165 | * 13 (Reserved interrupt) | |
166 | * 14 " | |
167 | * 15 " | |
168 | * 16 " | |
169 | * 18 Debug/trace interrupt | |
170 | * 20 (Reserved interrupt) | |
171 | * 22 " | |
172 | * 24 " | |
173 | * 26 " | |
174 | * 28 " | |
175 | * 30 (Reserved for standard reporting of bus or system errors) | |
176 | */ | |
177 | ||
178 | static const int hviprio_index2irq[] = { | |
179 | 0, 1, 4, 5, 8, 13, 14, 15, 16, 18, 20, 22, 24, 26, 28, 30 }; | |
180 | static const int hviprio_index2rdzero[] = { | |
181 | 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; | |
182 | ||
183 | int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero) | |
0c3e702a | 184 | { |
43dc93af AP |
185 | if (index < 0 || ARRAY_SIZE(hviprio_index2irq) <= index) { |
186 | return -EINVAL; | |
187 | } | |
3ef10a09 | 188 | |
43dc93af AP |
189 | if (out_irq) { |
190 | *out_irq = hviprio_index2irq[index]; | |
191 | } | |
3ef10a09 | 192 | |
43dc93af AP |
193 | if (out_rdzero) { |
194 | *out_rdzero = hviprio_index2rdzero[index]; | |
195 | } | |
cd032fe7 | 196 | |
43dc93af AP |
197 | return 0; |
198 | } | |
3ef10a09 | 199 | |
43dc93af AP |
200 | /* |
201 | * Default priorities of local interrupts are defined in the | |
202 | * RISC-V Advanced Interrupt Architecture specification. | |
203 | * | |
204 | * ---------------------------------------------------------------- | |
205 | * Default | | |
206 | * Priority | Major Interrupt Numbers | |
207 | * ---------------------------------------------------------------- | |
208 | * Highest | 63 (3f), 62 (3e), 31 (1f), 30 (1e), 61 (3d), 60 (3c), | |
209 | * | 59 (3b), 58 (3a), 29 (1d), 28 (1c), 57 (39), 56 (38), | |
210 | * | 55 (37), 54 (36), 27 (1b), 26 (1a), 53 (35), 52 (34), | |
211 | * | 51 (33), 50 (32), 25 (19), 24 (18), 49 (31), 48 (30) | |
212 | * | | |
213 | * | 11 (0b), 3 (03), 7 (07) | |
214 | * | 9 (09), 1 (01), 5 (05) | |
215 | * | 12 (0c) | |
216 | * | 10 (0a), 2 (02), 6 (06) | |
217 | * | | |
218 | * | 47 (2f), 46 (2e), 23 (17), 22 (16), 45 (2d), 44 (2c), | |
219 | * | 43 (2b), 42 (2a), 21 (15), 20 (14), 41 (29), 40 (28), | |
220 | * | 39 (27), 38 (26), 19 (13), 18 (12), 37 (25), 36 (24), | |
221 | * Lowest | 35 (23), 34 (22), 17 (11), 16 (10), 33 (21), 32 (20) | |
222 | * ---------------------------------------------------------------- | |
223 | */ | |
224 | static const uint8_t default_iprio[64] = { | |
225 | [63] = IPRIO_DEFAULT_UPPER, | |
226 | [62] = IPRIO_DEFAULT_UPPER + 1, | |
227 | [31] = IPRIO_DEFAULT_UPPER + 2, | |
228 | [30] = IPRIO_DEFAULT_UPPER + 3, | |
229 | [61] = IPRIO_DEFAULT_UPPER + 4, | |
230 | [60] = IPRIO_DEFAULT_UPPER + 5, | |
3ef10a09 | 231 | |
43dc93af AP |
232 | [59] = IPRIO_DEFAULT_UPPER + 6, |
233 | [58] = IPRIO_DEFAULT_UPPER + 7, | |
234 | [29] = IPRIO_DEFAULT_UPPER + 8, | |
235 | [28] = IPRIO_DEFAULT_UPPER + 9, | |
236 | [57] = IPRIO_DEFAULT_UPPER + 10, | |
237 | [56] = IPRIO_DEFAULT_UPPER + 11, | |
0c3e702a | 238 | |
43dc93af AP |
239 | [55] = IPRIO_DEFAULT_UPPER + 12, |
240 | [54] = IPRIO_DEFAULT_UPPER + 13, | |
241 | [27] = IPRIO_DEFAULT_UPPER + 14, | |
242 | [26] = IPRIO_DEFAULT_UPPER + 15, | |
243 | [53] = IPRIO_DEFAULT_UPPER + 16, | |
244 | [52] = IPRIO_DEFAULT_UPPER + 17, | |
245 | ||
246 | [51] = IPRIO_DEFAULT_UPPER + 18, | |
247 | [50] = IPRIO_DEFAULT_UPPER + 19, | |
248 | [25] = IPRIO_DEFAULT_UPPER + 20, | |
249 | [24] = IPRIO_DEFAULT_UPPER + 21, | |
250 | [49] = IPRIO_DEFAULT_UPPER + 22, | |
251 | [48] = IPRIO_DEFAULT_UPPER + 23, | |
252 | ||
253 | [11] = IPRIO_DEFAULT_M, | |
254 | [3] = IPRIO_DEFAULT_M + 1, | |
255 | [7] = IPRIO_DEFAULT_M + 2, | |
256 | ||
257 | [9] = IPRIO_DEFAULT_S, | |
258 | [1] = IPRIO_DEFAULT_S + 1, | |
259 | [5] = IPRIO_DEFAULT_S + 2, | |
260 | ||
261 | [12] = IPRIO_DEFAULT_SGEXT, | |
262 | ||
263 | [10] = IPRIO_DEFAULT_VS, | |
264 | [2] = IPRIO_DEFAULT_VS + 1, | |
265 | [6] = IPRIO_DEFAULT_VS + 2, | |
266 | ||
267 | [47] = IPRIO_DEFAULT_LOWER, | |
268 | [46] = IPRIO_DEFAULT_LOWER + 1, | |
269 | [23] = IPRIO_DEFAULT_LOWER + 2, | |
270 | [22] = IPRIO_DEFAULT_LOWER + 3, | |
271 | [45] = IPRIO_DEFAULT_LOWER + 4, | |
272 | [44] = IPRIO_DEFAULT_LOWER + 5, | |
273 | ||
274 | [43] = IPRIO_DEFAULT_LOWER + 6, | |
275 | [42] = IPRIO_DEFAULT_LOWER + 7, | |
276 | [21] = IPRIO_DEFAULT_LOWER + 8, | |
277 | [20] = IPRIO_DEFAULT_LOWER + 9, | |
278 | [41] = IPRIO_DEFAULT_LOWER + 10, | |
279 | [40] = IPRIO_DEFAULT_LOWER + 11, | |
280 | ||
281 | [39] = IPRIO_DEFAULT_LOWER + 12, | |
282 | [38] = IPRIO_DEFAULT_LOWER + 13, | |
283 | [19] = IPRIO_DEFAULT_LOWER + 14, | |
284 | [18] = IPRIO_DEFAULT_LOWER + 15, | |
285 | [37] = IPRIO_DEFAULT_LOWER + 16, | |
286 | [36] = IPRIO_DEFAULT_LOWER + 17, | |
287 | ||
288 | [35] = IPRIO_DEFAULT_LOWER + 18, | |
289 | [34] = IPRIO_DEFAULT_LOWER + 19, | |
290 | [17] = IPRIO_DEFAULT_LOWER + 20, | |
291 | [16] = IPRIO_DEFAULT_LOWER + 21, | |
292 | [33] = IPRIO_DEFAULT_LOWER + 22, | |
293 | [32] = IPRIO_DEFAULT_LOWER + 23, | |
294 | }; | |
295 | ||
296 | uint8_t riscv_cpu_default_priority(int irq) | |
297 | { | |
298 | if (irq < 0 || irq > 63) { | |
299 | return IPRIO_MMAXIPRIO; | |
300 | } | |
301 | ||
302 | return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO; | |
303 | }; | |
304 | ||
305 | static int riscv_cpu_pending_to_irq(CPURISCVState *env, | |
306 | int extirq, unsigned int extirq_def_prio, | |
307 | uint64_t pending, uint8_t *iprio) | |
308 | { | |
309 | int irq, best_irq = RISCV_EXCP_NONE; | |
310 | unsigned int prio, best_prio = UINT_MAX; | |
311 | ||
312 | if (!pending) { | |
313 | return RISCV_EXCP_NONE; | |
314 | } | |
315 | ||
316 | irq = ctz64(pending); | |
317 | if (!riscv_feature(env, RISCV_FEATURE_AIA)) { | |
318 | return irq; | |
319 | } | |
320 | ||
321 | pending = pending >> irq; | |
322 | while (pending) { | |
323 | prio = iprio[irq]; | |
324 | if (!prio) { | |
325 | if (irq == extirq) { | |
326 | prio = extirq_def_prio; | |
327 | } else { | |
328 | prio = (riscv_cpu_default_priority(irq) < extirq_def_prio) ? | |
329 | 1 : IPRIO_MMAXIPRIO; | |
330 | } | |
331 | } | |
332 | if ((pending & 0x1) && (prio <= best_prio)) { | |
333 | best_irq = irq; | |
334 | best_prio = prio; | |
335 | } | |
336 | irq++; | |
337 | pending = pending >> 1; | |
338 | } | |
339 | ||
340 | return best_irq; | |
341 | } | |
342 | ||
343 | static uint64_t riscv_cpu_all_pending(CPURISCVState *env) | |
344 | { | |
345 | uint32_t gein = get_field(env->hstatus, HSTATUS_VGEIN); | |
346 | uint64_t vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; | |
347 | ||
348 | return (env->mip | vsgein) & env->mie; | |
349 | } | |
350 | ||
351 | int riscv_cpu_mirq_pending(CPURISCVState *env) | |
352 | { | |
353 | uint64_t irqs = riscv_cpu_all_pending(env) & ~env->mideleg & | |
354 | ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); | |
355 | ||
356 | return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, | |
357 | irqs, env->miprio); | |
358 | } | |
359 | ||
360 | int riscv_cpu_sirq_pending(CPURISCVState *env) | |
361 | { | |
362 | uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & | |
363 | ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); | |
364 | ||
365 | return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, | |
366 | irqs, env->siprio); | |
367 | } | |
368 | ||
369 | int riscv_cpu_vsirq_pending(CPURISCVState *env) | |
370 | { | |
371 | uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & | |
372 | (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); | |
373 | ||
374 | return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, | |
375 | irqs >> 1, env->hviprio); | |
376 | } | |
377 | ||
378 | static int riscv_cpu_local_irq_pending(CPURISCVState *env) | |
379 | { | |
380 | int virq; | |
381 | uint64_t irqs, pending, mie, hsie, vsie; | |
382 | ||
383 | /* Determine interrupt enable state of all privilege modes */ | |
384 | if (riscv_cpu_virt_enabled(env)) { | |
385 | mie = 1; | |
386 | hsie = 1; | |
387 | vsie = (env->priv < PRV_S) || | |
388 | (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE)); | |
0c3e702a | 389 | } else { |
43dc93af AP |
390 | mie = (env->priv < PRV_M) || |
391 | (env->priv == PRV_M && get_field(env->mstatus, MSTATUS_MIE)); | |
392 | hsie = (env->priv < PRV_S) || | |
393 | (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE)); | |
394 | vsie = 0; | |
395 | } | |
396 | ||
397 | /* Determine all pending interrupts */ | |
398 | pending = riscv_cpu_all_pending(env); | |
399 | ||
400 | /* Check M-mode interrupts */ | |
401 | irqs = pending & ~env->mideleg & -mie; | |
402 | if (irqs) { | |
403 | return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, | |
404 | irqs, env->miprio); | |
405 | } | |
406 | ||
407 | /* Check HS-mode interrupts */ | |
408 | irqs = pending & env->mideleg & ~env->hideleg & -hsie; | |
409 | if (irqs) { | |
410 | return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, | |
411 | irqs, env->siprio); | |
0c3e702a | 412 | } |
43dc93af AP |
413 | |
414 | /* Check VS-mode interrupts */ | |
415 | irqs = pending & env->mideleg & env->hideleg & -vsie; | |
416 | if (irqs) { | |
417 | virq = riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, | |
418 | irqs >> 1, env->hviprio); | |
419 | return (virq <= 0) ? virq : virq + 1; | |
420 | } | |
421 | ||
422 | /* Indicate no pending interrupt */ | |
423 | return RISCV_EXCP_NONE; | |
0c3e702a | 424 | } |
0c3e702a MC |
425 | |
426 | bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) | |
427 | { | |
0c3e702a MC |
428 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
429 | RISCVCPU *cpu = RISCV_CPU(cs); | |
430 | CPURISCVState *env = &cpu->env; | |
efbdbc26 | 431 | int interruptno = riscv_cpu_local_irq_pending(env); |
0c3e702a MC |
432 | if (interruptno >= 0) { |
433 | cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno; | |
434 | riscv_cpu_do_interrupt(cs); | |
435 | return true; | |
436 | } | |
437 | } | |
0c3e702a MC |
438 | return false; |
439 | } | |
440 | ||
b345b480 AF |
441 | /* Return true is floating point support is currently enabled */ |
442 | bool riscv_cpu_fp_enabled(CPURISCVState *env) | |
443 | { | |
444 | if (env->mstatus & MSTATUS_FS) { | |
29409c1d AF |
445 | if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_FS)) { |
446 | return false; | |
447 | } | |
b345b480 AF |
448 | return true; |
449 | } | |
450 | ||
451 | return false; | |
452 | } | |
453 | ||
61b4b69d LZ |
454 | /* Return true is vector support is currently enabled */ |
455 | bool riscv_cpu_vector_enabled(CPURISCVState *env) | |
456 | { | |
457 | if (env->mstatus & MSTATUS_VS) { | |
458 | if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_VS)) { | |
459 | return false; | |
460 | } | |
461 | return true; | |
462 | } | |
463 | ||
464 | return false; | |
465 | } | |
466 | ||
66e594f2 AF |
467 | void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) |
468 | { | |
284d697c YJ |
469 | uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | |
470 | MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | | |
61b4b69d | 471 | MSTATUS64_UXL | MSTATUS_VS; |
66e594f2 AF |
472 | bool current_virt = riscv_cpu_virt_enabled(env); |
473 | ||
474 | g_assert(riscv_has_ext(env, RVH)); | |
475 | ||
66e594f2 AF |
476 | if (current_virt) { |
477 | /* Current V=1 and we are about to change to V=0 */ | |
478 | env->vsstatus = env->mstatus & mstatus_mask; | |
479 | env->mstatus &= ~mstatus_mask; | |
480 | env->mstatus |= env->mstatus_hs; | |
481 | ||
482 | env->vstvec = env->stvec; | |
483 | env->stvec = env->stvec_hs; | |
484 | ||
485 | env->vsscratch = env->sscratch; | |
486 | env->sscratch = env->sscratch_hs; | |
487 | ||
488 | env->vsepc = env->sepc; | |
489 | env->sepc = env->sepc_hs; | |
490 | ||
491 | env->vscause = env->scause; | |
492 | env->scause = env->scause_hs; | |
493 | ||
ac12b601 AP |
494 | env->vstval = env->stval; |
495 | env->stval = env->stval_hs; | |
66e594f2 AF |
496 | |
497 | env->vsatp = env->satp; | |
498 | env->satp = env->satp_hs; | |
499 | } else { | |
500 | /* Current V=0 and we are about to change to V=1 */ | |
501 | env->mstatus_hs = env->mstatus & mstatus_mask; | |
502 | env->mstatus &= ~mstatus_mask; | |
503 | env->mstatus |= env->vsstatus; | |
504 | ||
505 | env->stvec_hs = env->stvec; | |
506 | env->stvec = env->vstvec; | |
507 | ||
508 | env->sscratch_hs = env->sscratch; | |
509 | env->sscratch = env->vsscratch; | |
510 | ||
511 | env->sepc_hs = env->sepc; | |
512 | env->sepc = env->vsepc; | |
513 | ||
514 | env->scause_hs = env->scause; | |
515 | env->scause = env->vscause; | |
516 | ||
ac12b601 AP |
517 | env->stval_hs = env->stval; |
518 | env->stval = env->vstval; | |
66e594f2 AF |
519 | |
520 | env->satp_hs = env->satp; | |
521 | env->satp = env->vsatp; | |
522 | } | |
523 | } | |
524 | ||
cd032fe7 AP |
525 | target_ulong riscv_cpu_get_geilen(CPURISCVState *env) |
526 | { | |
527 | if (!riscv_has_ext(env, RVH)) { | |
528 | return 0; | |
529 | } | |
530 | ||
531 | return env->geilen; | |
532 | } | |
533 | ||
534 | void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen) | |
535 | { | |
536 | if (!riscv_has_ext(env, RVH)) { | |
537 | return; | |
538 | } | |
539 | ||
540 | if (geilen > (TARGET_LONG_BITS - 1)) { | |
541 | return; | |
542 | } | |
543 | ||
544 | env->geilen = geilen; | |
545 | } | |
546 | ||
ef6bb7b6 AF |
547 | bool riscv_cpu_virt_enabled(CPURISCVState *env) |
548 | { | |
549 | if (!riscv_has_ext(env, RVH)) { | |
550 | return false; | |
551 | } | |
552 | ||
553 | return get_field(env->virt, VIRT_ONOFF); | |
554 | } | |
555 | ||
556 | void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) | |
557 | { | |
558 | if (!riscv_has_ext(env, RVH)) { | |
559 | return; | |
560 | } | |
561 | ||
eccc5a12 AF |
562 | /* Flush the TLB on all virt mode changes. */ |
563 | if (get_field(env->virt, VIRT_ONOFF) != enable) { | |
564 | tlb_flush(env_cpu(env)); | |
565 | } | |
566 | ||
ef6bb7b6 | 567 | env->virt = set_field(env->virt, VIRT_ONOFF, enable); |
02d9565b AP |
568 | |
569 | if (enable) { | |
570 | /* | |
571 | * The guest external interrupts from an interrupt controller are | |
572 | * delivered only when the Guest/VM is running (i.e. V=1). This means | |
573 | * any guest external interrupt which is triggered while the Guest/VM | |
574 | * is not running (i.e. V=0) will be missed on QEMU resulting in guest | |
575 | * with sluggish response to serial console input and other I/O events. | |
576 | * | |
577 | * To solve this, we check and inject interrupt after setting V=1. | |
578 | */ | |
579 | riscv_cpu_update_mip(env_archcpu(env), 0, 0); | |
580 | } | |
ef6bb7b6 AF |
581 | } |
582 | ||
1c1c060a | 583 | bool riscv_cpu_two_stage_lookup(int mmu_idx) |
5a894dd7 | 584 | { |
1c1c060a | 585 | return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK; |
5a894dd7 AF |
586 | } |
587 | ||
d028ac75 | 588 | int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts) |
e3e7039c MC |
589 | { |
590 | CPURISCVState *env = &cpu->env; | |
591 | if (env->miclaim & interrupts) { | |
592 | return -1; | |
593 | } else { | |
594 | env->miclaim |= interrupts; | |
595 | return 0; | |
596 | } | |
597 | } | |
598 | ||
d028ac75 | 599 | uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value) |
df354dd4 MC |
600 | { |
601 | CPURISCVState *env = &cpu->env; | |
0a01f2ee | 602 | CPUState *cs = CPU(cpu); |
d028ac75 | 603 | uint64_t gein, vsgein = 0, old = env->mip; |
7ec5d303 AF |
604 | bool locked = false; |
605 | ||
cd032fe7 AP |
606 | if (riscv_cpu_virt_enabled(env)) { |
607 | gein = get_field(env->hstatus, HSTATUS_VGEIN); | |
608 | vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; | |
609 | } | |
610 | ||
7ec5d303 AF |
611 | if (!qemu_mutex_iothread_locked()) { |
612 | locked = true; | |
613 | qemu_mutex_lock_iothread(); | |
614 | } | |
df354dd4 | 615 | |
7ec5d303 | 616 | env->mip = (env->mip & ~mask) | (value & mask); |
df354dd4 | 617 | |
cd032fe7 | 618 | if (env->mip | vsgein) { |
7ec5d303 AF |
619 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
620 | } else { | |
621 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); | |
622 | } | |
0a01f2ee | 623 | |
7ec5d303 AF |
624 | if (locked) { |
625 | qemu_mutex_unlock_iothread(); | |
626 | } | |
df354dd4 MC |
627 | |
628 | return old; | |
629 | } | |
630 | ||
a47ef6e9 BM |
631 | void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), |
632 | uint32_t arg) | |
c6957248 AP |
633 | { |
634 | env->rdtime_fn = fn; | |
a47ef6e9 | 635 | env->rdtime_fn_arg = arg; |
c6957248 AP |
636 | } |
637 | ||
69077dd6 AP |
638 | void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, |
639 | int (*rmw_fn)(void *arg, | |
640 | target_ulong reg, | |
641 | target_ulong *val, | |
642 | target_ulong new_val, | |
643 | target_ulong write_mask), | |
644 | void *rmw_fn_arg) | |
645 | { | |
646 | if (priv <= PRV_M) { | |
647 | env->aia_ireg_rmw_fn[priv] = rmw_fn; | |
648 | env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg; | |
649 | } | |
650 | } | |
651 | ||
fb738839 | 652 | void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) |
df354dd4 MC |
653 | { |
654 | if (newpriv > PRV_M) { | |
655 | g_assert_not_reached(); | |
656 | } | |
657 | if (newpriv == PRV_H) { | |
658 | newpriv = PRV_U; | |
659 | } | |
660 | /* tlb_flush is unnecessary as mode is contained in mmu_idx */ | |
661 | env->priv = newpriv; | |
440544e1 | 662 | env->xl = cpu_recompute_xl(env); |
40bfa5f6 | 663 | riscv_cpu_update_mask(env); |
c13b169f JS |
664 | |
665 | /* | |
666 | * Clear the load reservation - otherwise a reservation placed in one | |
667 | * context/process can be used by another, resulting in an SC succeeding | |
668 | * incorrectly. Version 2.2 of the ISA specification explicitly requires | |
669 | * this behaviour, while later revisions say that the kernel "should" use | |
670 | * an SC instruction to force the yielding of a load reservation on a | |
671 | * preemptive context switch. As a result, do both. | |
672 | */ | |
673 | env->load_res = -1; | |
df354dd4 MC |
674 | } |
675 | ||
b297129a JS |
676 | /* |
677 | * get_physical_address_pmp - check PMP permission for this physical address | |
678 | * | |
679 | * Match the PMP region and check permission for this physical address and it's | |
680 | * TLB page. Returns 0 if the permission checking was successful | |
681 | * | |
682 | * @env: CPURISCVState | |
683 | * @prot: The returned protection attributes | |
684 | * @tlb_size: TLB page size containing addr. It could be modified after PMP | |
685 | * permission checking. NULL if not set TLB page for addr. | |
686 | * @addr: The physical address to be checked permission | |
687 | * @access_type: The type of MMU access | |
688 | * @mode: Indicates current privilege level. | |
689 | */ | |
690 | static int get_physical_address_pmp(CPURISCVState *env, int *prot, | |
691 | target_ulong *tlb_size, hwaddr addr, | |
692 | int size, MMUAccessType access_type, | |
693 | int mode) | |
694 | { | |
695 | pmp_priv_t pmp_priv; | |
696 | target_ulong tlb_size_pmp = 0; | |
697 | ||
698 | if (!riscv_feature(env, RISCV_FEATURE_PMP)) { | |
699 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
700 | return TRANSLATE_SUCCESS; | |
701 | } | |
702 | ||
703 | if (!pmp_hart_has_privs(env, addr, size, 1 << access_type, &pmp_priv, | |
704 | mode)) { | |
705 | *prot = 0; | |
706 | return TRANSLATE_PMP_FAIL; | |
707 | } | |
708 | ||
709 | *prot = pmp_priv_to_page_prot(pmp_priv); | |
710 | if (tlb_size != NULL) { | |
711 | if (pmp_is_range_in_tlb(env, addr & ~(*tlb_size - 1), &tlb_size_pmp)) { | |
712 | *tlb_size = tlb_size_pmp; | |
713 | } | |
714 | } | |
715 | ||
716 | return TRANSLATE_SUCCESS; | |
717 | } | |
718 | ||
0c3e702a MC |
719 | /* get_physical_address - get the physical address for this virtual address |
720 | * | |
721 | * Do a page table walk to obtain the physical address corresponding to a | |
722 | * virtual address. Returns 0 if the translation was successful | |
723 | * | |
724 | * Adapted from Spike's mmu_t::translate and mmu_t::walk | |
725 | * | |
1448689c AF |
726 | * @env: CPURISCVState |
727 | * @physical: This will be set to the calculated physical address | |
728 | * @prot: The returned protection attributes | |
729 | * @addr: The virtual address to be translated | |
33a9a57d YJ |
730 | * @fault_pte_addr: If not NULL, this will be set to fault pte address |
731 | * when a error occurs on pte address translation. | |
732 | * This will already be shifted to match htval. | |
1448689c AF |
733 | * @access_type: The type of MMU access |
734 | * @mmu_idx: Indicates current privilege level | |
735 | * @first_stage: Are we in first stage translation? | |
736 | * Second stage is used for hypervisor guest translation | |
36a18664 | 737 | * @two_stage: Are we going to perform two stage translation |
11c27c6d | 738 | * @is_debug: Is this access from a debugger or the monitor? |
0c3e702a MC |
739 | */ |
740 | static int get_physical_address(CPURISCVState *env, hwaddr *physical, | |
741 | int *prot, target_ulong addr, | |
33a9a57d | 742 | target_ulong *fault_pte_addr, |
1448689c | 743 | int access_type, int mmu_idx, |
11c27c6d JF |
744 | bool first_stage, bool two_stage, |
745 | bool is_debug) | |
0c3e702a MC |
746 | { |
747 | /* NOTE: the env->pc value visible here will not be | |
748 | * correct, but the value visible to the exception handler | |
749 | * (riscv_cpu_do_interrupt) is correct */ | |
aacb578f PD |
750 | MemTxResult res; |
751 | MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; | |
c445593d | 752 | int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK; |
36a18664 | 753 | bool use_background = false; |
0c3e702a | 754 | |
36a18664 AF |
755 | /* |
756 | * Check if we should use the background registers for the two | |
757 | * stage translation. We don't need to check if we actually need | |
758 | * two stage translation as that happened before this function | |
759 | * was called. Background registers will be used if the guest has | |
760 | * forced a two stage translation to be on (in HS or M mode). | |
761 | */ | |
db9ab38b | 762 | if (!riscv_cpu_virt_enabled(env) && two_stage) { |
29b3361b AF |
763 | use_background = true; |
764 | } | |
765 | ||
90ec1cff GK |
766 | /* MPRV does not affect the virtual-machine load/store |
767 | instructions, HLV, HLVX, and HSV. */ | |
768 | if (riscv_cpu_two_stage_lookup(mmu_idx)) { | |
769 | mode = get_field(env->hstatus, HSTATUS_SPVP); | |
770 | } else if (mode == PRV_M && access_type != MMU_INST_FETCH) { | |
0c3e702a MC |
771 | if (get_field(env->mstatus, MSTATUS_MPRV)) { |
772 | mode = get_field(env->mstatus, MSTATUS_MPP); | |
773 | } | |
774 | } | |
775 | ||
36a18664 AF |
776 | if (first_stage == false) { |
777 | /* We are in stage 2 translation, this is similar to stage 1. */ | |
778 | /* Stage 2 is always taken as U-mode */ | |
779 | mode = PRV_U; | |
780 | } | |
781 | ||
0c3e702a MC |
782 | if (mode == PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) { |
783 | *physical = addr; | |
784 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
785 | return TRANSLATE_SUCCESS; | |
786 | } | |
787 | ||
788 | *prot = 0; | |
789 | ||
ddf78132 | 790 | hwaddr base; |
36a18664 AF |
791 | int levels, ptidxbits, ptesize, vm, sum, mxr, widened; |
792 | ||
793 | if (first_stage == true) { | |
794 | mxr = get_field(env->mstatus, MSTATUS_MXR); | |
795 | } else { | |
796 | mxr = get_field(env->vsstatus, MSTATUS_MXR); | |
797 | } | |
0c3e702a | 798 | |
1a9540d1 AF |
799 | if (first_stage == true) { |
800 | if (use_background) { | |
db23e5d9 | 801 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
419ddf00 AF |
802 | base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT; |
803 | vm = get_field(env->vsatp, SATP32_MODE); | |
804 | } else { | |
805 | base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT; | |
806 | vm = get_field(env->vsatp, SATP64_MODE); | |
807 | } | |
36a18664 | 808 | } else { |
db23e5d9 | 809 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
419ddf00 AF |
810 | base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; |
811 | vm = get_field(env->satp, SATP32_MODE); | |
812 | } else { | |
813 | base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT; | |
814 | vm = get_field(env->satp, SATP64_MODE); | |
815 | } | |
0c3e702a | 816 | } |
36a18664 | 817 | widened = 0; |
1a9540d1 | 818 | } else { |
db23e5d9 | 819 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
994b6bb2 AF |
820 | base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT; |
821 | vm = get_field(env->hgatp, SATP32_MODE); | |
822 | } else { | |
823 | base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT; | |
824 | vm = get_field(env->hgatp, SATP64_MODE); | |
825 | } | |
1a9540d1 AF |
826 | widened = 2; |
827 | } | |
c63ca4ff | 828 | /* status.SUM will be ignored if execute on background */ |
11c27c6d | 829 | sum = get_field(env->mstatus, MSTATUS_SUM) || use_background || is_debug; |
1a9540d1 AF |
830 | switch (vm) { |
831 | case VM_1_10_SV32: | |
832 | levels = 2; ptidxbits = 10; ptesize = 4; break; | |
833 | case VM_1_10_SV39: | |
834 | levels = 3; ptidxbits = 9; ptesize = 8; break; | |
835 | case VM_1_10_SV48: | |
836 | levels = 4; ptidxbits = 9; ptesize = 8; break; | |
837 | case VM_1_10_SV57: | |
838 | levels = 5; ptidxbits = 9; ptesize = 8; break; | |
839 | case VM_1_10_MBARE: | |
840 | *physical = addr; | |
841 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
842 | return TRANSLATE_SUCCESS; | |
843 | default: | |
844 | g_assert_not_reached(); | |
0c3e702a MC |
845 | } |
846 | ||
3109cd98 | 847 | CPUState *cs = env_cpu(env); |
36a18664 AF |
848 | int va_bits = PGSHIFT + levels * ptidxbits + widened; |
849 | target_ulong mask, masked_msbs; | |
850 | ||
851 | if (TARGET_LONG_BITS > (va_bits - 1)) { | |
852 | mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; | |
853 | } else { | |
854 | mask = 0; | |
855 | } | |
856 | masked_msbs = (addr >> (va_bits - 1)) & mask; | |
857 | ||
0c3e702a MC |
858 | if (masked_msbs != 0 && masked_msbs != mask) { |
859 | return TRANSLATE_FAIL; | |
860 | } | |
861 | ||
862 | int ptshift = (levels - 1) * ptidxbits; | |
863 | int i; | |
864 | ||
865 | #if !TCG_OVERSIZED_GUEST | |
866 | restart: | |
867 | #endif | |
868 | for (i = 0; i < levels; i++, ptshift -= ptidxbits) { | |
36a18664 AF |
869 | target_ulong idx; |
870 | if (i == 0) { | |
871 | idx = (addr >> (PGSHIFT + ptshift)) & | |
872 | ((1 << (ptidxbits + widened)) - 1); | |
873 | } else { | |
874 | idx = (addr >> (PGSHIFT + ptshift)) & | |
0c3e702a | 875 | ((1 << ptidxbits) - 1); |
36a18664 | 876 | } |
0c3e702a MC |
877 | |
878 | /* check that physical address of PTE is legal */ | |
36a18664 AF |
879 | hwaddr pte_addr; |
880 | ||
881 | if (two_stage && first_stage) { | |
38472890 | 882 | int vbase_prot; |
36a18664 AF |
883 | hwaddr vbase; |
884 | ||
885 | /* Do the second stage translation on the base PTE address. */ | |
88914473 | 886 | int vbase_ret = get_physical_address(env, &vbase, &vbase_prot, |
33a9a57d | 887 | base, NULL, MMU_DATA_LOAD, |
11c27c6d JF |
888 | mmu_idx, false, true, |
889 | is_debug); | |
88914473 AF |
890 | |
891 | if (vbase_ret != TRANSLATE_SUCCESS) { | |
33a9a57d YJ |
892 | if (fault_pte_addr) { |
893 | *fault_pte_addr = (base + idx * ptesize) >> 2; | |
894 | } | |
895 | return TRANSLATE_G_STAGE_FAIL; | |
88914473 | 896 | } |
36a18664 AF |
897 | |
898 | pte_addr = vbase + idx * ptesize; | |
899 | } else { | |
900 | pte_addr = base + idx * ptesize; | |
901 | } | |
1f447aec | 902 | |
b297129a JS |
903 | int pmp_prot; |
904 | int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr, | |
905 | sizeof(target_ulong), | |
906 | MMU_DATA_LOAD, PRV_S); | |
907 | if (pmp_ret != TRANSLATE_SUCCESS) { | |
1f447aec HA |
908 | return TRANSLATE_PMP_FAIL; |
909 | } | |
aacb578f | 910 | |
f08c7ff3 | 911 | target_ulong pte; |
db23e5d9 | 912 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
f08c7ff3 AF |
913 | pte = address_space_ldl(cs->as, pte_addr, attrs, &res); |
914 | } else { | |
915 | pte = address_space_ldq(cs->as, pte_addr, attrs, &res); | |
916 | } | |
917 | ||
aacb578f PD |
918 | if (res != MEMTX_OK) { |
919 | return TRANSLATE_FAIL; | |
920 | } | |
921 | ||
ddf78132 | 922 | hwaddr ppn = pte >> PTE_PPN_SHIFT; |
0c3e702a | 923 | |
c3b03e58 MC |
924 | if (!(pte & PTE_V)) { |
925 | /* Invalid PTE */ | |
926 | return TRANSLATE_FAIL; | |
927 | } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { | |
928 | /* Inner PTE, continue walking */ | |
0c3e702a | 929 | base = ppn << PGSHIFT; |
c3b03e58 MC |
930 | } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) { |
931 | /* Reserved leaf PTE flags: PTE_W */ | |
932 | return TRANSLATE_FAIL; | |
933 | } else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) { | |
934 | /* Reserved leaf PTE flags: PTE_W + PTE_X */ | |
935 | return TRANSLATE_FAIL; | |
936 | } else if ((pte & PTE_U) && ((mode != PRV_U) && | |
937 | (!sum || access_type == MMU_INST_FETCH))) { | |
938 | /* User PTE flags when not U mode and mstatus.SUM is not set, | |
939 | or the access type is an instruction fetch */ | |
940 | return TRANSLATE_FAIL; | |
941 | } else if (!(pte & PTE_U) && (mode != PRV_S)) { | |
942 | /* Supervisor PTE flags when not S mode */ | |
943 | return TRANSLATE_FAIL; | |
944 | } else if (ppn & ((1ULL << ptshift) - 1)) { | |
945 | /* Misaligned PPN */ | |
946 | return TRANSLATE_FAIL; | |
947 | } else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) || | |
948 | ((pte & PTE_X) && mxr))) { | |
949 | /* Read access check failed */ | |
950 | return TRANSLATE_FAIL; | |
951 | } else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) { | |
952 | /* Write access check failed */ | |
953 | return TRANSLATE_FAIL; | |
954 | } else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) { | |
955 | /* Fetch access check failed */ | |
956 | return TRANSLATE_FAIL; | |
0c3e702a MC |
957 | } else { |
958 | /* if necessary, set accessed and dirty bits. */ | |
959 | target_ulong updated_pte = pte | PTE_A | | |
960 | (access_type == MMU_DATA_STORE ? PTE_D : 0); | |
961 | ||
962 | /* Page table updates need to be atomic with MTTCG enabled */ | |
963 | if (updated_pte != pte) { | |
c3b03e58 MC |
964 | /* |
965 | * - if accessed or dirty bits need updating, and the PTE is | |
966 | * in RAM, then we do so atomically with a compare and swap. | |
967 | * - if the PTE is in IO space or ROM, then it can't be updated | |
968 | * and we return TRANSLATE_FAIL. | |
969 | * - if the PTE changed by the time we went to update it, then | |
970 | * it is no longer valid and we must re-walk the page table. | |
971 | */ | |
0c3e702a MC |
972 | MemoryRegion *mr; |
973 | hwaddr l = sizeof(target_ulong), addr1; | |
974 | mr = address_space_translate(cs->as, pte_addr, | |
bc6b1cec | 975 | &addr1, &l, false, MEMTXATTRS_UNSPECIFIED); |
c3b03e58 | 976 | if (memory_region_is_ram(mr)) { |
0c3e702a MC |
977 | target_ulong *pte_pa = |
978 | qemu_map_ram_ptr(mr->ram_block, addr1); | |
979 | #if TCG_OVERSIZED_GUEST | |
980 | /* MTTCG is not enabled on oversized TCG guests so | |
981 | * page table updates do not need to be atomic */ | |
982 | *pte_pa = pte = updated_pte; | |
983 | #else | |
984 | target_ulong old_pte = | |
d73415a3 | 985 | qatomic_cmpxchg(pte_pa, pte, updated_pte); |
0c3e702a MC |
986 | if (old_pte != pte) { |
987 | goto restart; | |
988 | } else { | |
989 | pte = updated_pte; | |
990 | } | |
991 | #endif | |
992 | } else { | |
993 | /* misconfigured PTE in ROM (AD bits are not preset) or | |
994 | * PTE is in IO space and can't be updated atomically */ | |
995 | return TRANSLATE_FAIL; | |
996 | } | |
997 | } | |
998 | ||
999 | /* for superpage mappings, make a fake leaf PTE for the TLB's | |
1000 | benefit. */ | |
1001 | target_ulong vpn = addr >> PGSHIFT; | |
9ef82119 ZL |
1002 | *physical = ((ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT) | |
1003 | (addr & ~TARGET_PAGE_MASK); | |
0c3e702a | 1004 | |
c3b03e58 MC |
1005 | /* set permissions on the TLB entry */ |
1006 | if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { | |
0c3e702a MC |
1007 | *prot |= PAGE_READ; |
1008 | } | |
1009 | if ((pte & PTE_X)) { | |
1010 | *prot |= PAGE_EXEC; | |
1011 | } | |
c3b03e58 MC |
1012 | /* add write permission on stores or if the page is already dirty, |
1013 | so that we TLB miss on later writes to update the dirty bit */ | |
0c3e702a MC |
1014 | if ((pte & PTE_W) && |
1015 | (access_type == MMU_DATA_STORE || (pte & PTE_D))) { | |
1016 | *prot |= PAGE_WRITE; | |
1017 | } | |
1018 | return TRANSLATE_SUCCESS; | |
1019 | } | |
1020 | } | |
1021 | return TRANSLATE_FAIL; | |
1022 | } | |
1023 | ||
1024 | static void raise_mmu_exception(CPURISCVState *env, target_ulong address, | |
1448689c | 1025 | MMUAccessType access_type, bool pmp_violation, |
1c1c060a | 1026 | bool first_stage, bool two_stage) |
0c3e702a | 1027 | { |
3109cd98 | 1028 | CPUState *cs = env_cpu(env); |
994b6bb2 | 1029 | int page_fault_exceptions, vm; |
419ddf00 AF |
1030 | uint64_t stap_mode; |
1031 | ||
db23e5d9 | 1032 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
419ddf00 AF |
1033 | stap_mode = SATP32_MODE; |
1034 | } else { | |
1035 | stap_mode = SATP64_MODE; | |
1036 | } | |
994b6bb2 | 1037 | |
1448689c | 1038 | if (first_stage) { |
419ddf00 | 1039 | vm = get_field(env->satp, stap_mode); |
1448689c | 1040 | } else { |
419ddf00 | 1041 | vm = get_field(env->hgatp, stap_mode); |
1448689c | 1042 | } |
419ddf00 | 1043 | |
994b6bb2 AF |
1044 | page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation; |
1045 | ||
0c3e702a MC |
1046 | switch (access_type) { |
1047 | case MMU_INST_FETCH: | |
b2ef6ab9 AF |
1048 | if (riscv_cpu_virt_enabled(env) && !first_stage) { |
1049 | cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT; | |
1050 | } else { | |
1051 | cs->exception_index = page_fault_exceptions ? | |
1052 | RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT; | |
1053 | } | |
0c3e702a MC |
1054 | break; |
1055 | case MMU_DATA_LOAD: | |
1c1c060a | 1056 | if (two_stage && !first_stage) { |
b2ef6ab9 AF |
1057 | cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; |
1058 | } else { | |
1059 | cs->exception_index = page_fault_exceptions ? | |
1060 | RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT; | |
1061 | } | |
0c3e702a MC |
1062 | break; |
1063 | case MMU_DATA_STORE: | |
1c1c060a | 1064 | if (two_stage && !first_stage) { |
b2ef6ab9 AF |
1065 | cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT; |
1066 | } else { | |
1067 | cs->exception_index = page_fault_exceptions ? | |
1068 | RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_FAULT; | |
1069 | } | |
0c3e702a MC |
1070 | break; |
1071 | default: | |
1072 | g_assert_not_reached(); | |
1073 | } | |
1074 | env->badaddr = address; | |
ec352d0c | 1075 | env->two_stage_lookup = two_stage; |
0c3e702a MC |
1076 | } |
1077 | ||
1078 | hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) | |
1079 | { | |
1080 | RISCVCPU *cpu = RISCV_CPU(cs); | |
36a18664 | 1081 | CPURISCVState *env = &cpu->env; |
0c3e702a MC |
1082 | hwaddr phys_addr; |
1083 | int prot; | |
1084 | int mmu_idx = cpu_mmu_index(&cpu->env, false); | |
1085 | ||
33a9a57d | 1086 | if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx, |
11c27c6d | 1087 | true, riscv_cpu_virt_enabled(env), true)) { |
0c3e702a MC |
1088 | return -1; |
1089 | } | |
36a18664 AF |
1090 | |
1091 | if (riscv_cpu_virt_enabled(env)) { | |
33a9a57d | 1092 | if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL, |
11c27c6d | 1093 | 0, mmu_idx, false, true, true)) { |
36a18664 AF |
1094 | return -1; |
1095 | } | |
1096 | } | |
1097 | ||
9ef82119 | 1098 | return phys_addr & TARGET_PAGE_MASK; |
0c3e702a MC |
1099 | } |
1100 | ||
37207e12 PD |
1101 | void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, |
1102 | vaddr addr, unsigned size, | |
1103 | MMUAccessType access_type, | |
1104 | int mmu_idx, MemTxAttrs attrs, | |
1105 | MemTxResult response, uintptr_t retaddr) | |
cbf58276 MC |
1106 | { |
1107 | RISCVCPU *cpu = RISCV_CPU(cs); | |
1108 | CPURISCVState *env = &cpu->env; | |
1109 | ||
37207e12 | 1110 | if (access_type == MMU_DATA_STORE) { |
cbf58276 | 1111 | cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; |
f9e580c1 | 1112 | } else if (access_type == MMU_DATA_LOAD) { |
cbf58276 | 1113 | cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; |
f9e580c1 EB |
1114 | } else { |
1115 | cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT; | |
cbf58276 MC |
1116 | } |
1117 | ||
1118 | env->badaddr = addr; | |
ec352d0c GK |
1119 | env->two_stage_lookup = riscv_cpu_virt_enabled(env) || |
1120 | riscv_cpu_two_stage_lookup(mmu_idx); | |
37207e12 | 1121 | riscv_raise_exception(&cpu->env, cs->exception_index, retaddr); |
cbf58276 MC |
1122 | } |
1123 | ||
0c3e702a MC |
1124 | void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, |
1125 | MMUAccessType access_type, int mmu_idx, | |
1126 | uintptr_t retaddr) | |
1127 | { | |
1128 | RISCVCPU *cpu = RISCV_CPU(cs); | |
1129 | CPURISCVState *env = &cpu->env; | |
1130 | switch (access_type) { | |
1131 | case MMU_INST_FETCH: | |
1132 | cs->exception_index = RISCV_EXCP_INST_ADDR_MIS; | |
1133 | break; | |
1134 | case MMU_DATA_LOAD: | |
1135 | cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS; | |
1136 | break; | |
1137 | case MMU_DATA_STORE: | |
1138 | cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS; | |
1139 | break; | |
1140 | default: | |
1141 | g_assert_not_reached(); | |
1142 | } | |
1143 | env->badaddr = addr; | |
ec352d0c GK |
1144 | env->two_stage_lookup = riscv_cpu_virt_enabled(env) || |
1145 | riscv_cpu_two_stage_lookup(mmu_idx); | |
fb738839 | 1146 | riscv_raise_exception(env, cs->exception_index, retaddr); |
0c3e702a | 1147 | } |
0c3e702a | 1148 | |
8a4ca3c1 RH |
1149 | bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
1150 | MMUAccessType access_type, int mmu_idx, | |
1151 | bool probe, uintptr_t retaddr) | |
0c3e702a MC |
1152 | { |
1153 | RISCVCPU *cpu = RISCV_CPU(cs); | |
1154 | CPURISCVState *env = &cpu->env; | |
36a18664 | 1155 | vaddr im_address; |
0c3e702a | 1156 | hwaddr pa = 0; |
b297129a | 1157 | int prot, prot2, prot_pmp; |
635b0b0e | 1158 | bool pmp_violation = false; |
36a18664 | 1159 | bool first_stage_error = true; |
1c1c060a | 1160 | bool two_stage_lookup = false; |
0c3e702a | 1161 | int ret = TRANSLATE_FAIL; |
cc0fdb29 | 1162 | int mode = mmu_idx; |
b297129a JS |
1163 | /* default TLB page size */ |
1164 | target_ulong tlb_size = TARGET_PAGE_SIZE; | |
0c3e702a | 1165 | |
36a18664 AF |
1166 | env->guest_phys_fault_addr = 0; |
1167 | ||
8a4ca3c1 RH |
1168 | qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", |
1169 | __func__, address, access_type, mmu_idx); | |
1170 | ||
90ec1cff GK |
1171 | /* MPRV does not affect the virtual-machine load/store |
1172 | instructions, HLV, HLVX, and HSV. */ | |
1173 | if (riscv_cpu_two_stage_lookup(mmu_idx)) { | |
1174 | mode = get_field(env->hstatus, HSTATUS_SPVP); | |
1175 | } else if (mode == PRV_M && access_type != MMU_INST_FETCH && | |
1176 | get_field(env->mstatus, MSTATUS_MPRV)) { | |
1177 | mode = get_field(env->mstatus, MSTATUS_MPP); | |
1178 | if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) { | |
1179 | two_stage_lookup = true; | |
cc0fdb29 HA |
1180 | } |
1181 | } | |
1182 | ||
29b3361b | 1183 | if (riscv_cpu_virt_enabled(env) || |
1c1c060a AF |
1184 | ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) && |
1185 | access_type != MMU_INST_FETCH)) { | |
36a18664 | 1186 | /* Two stage lookup */ |
33a9a57d YJ |
1187 | ret = get_physical_address(env, &pa, &prot, address, |
1188 | &env->guest_phys_fault_addr, access_type, | |
11c27c6d | 1189 | mmu_idx, true, true, false); |
36a18664 | 1190 | |
33a9a57d YJ |
1191 | /* |
1192 | * A G-stage exception may be triggered during two state lookup. | |
1193 | * And the env->guest_phys_fault_addr has already been set in | |
1194 | * get_physical_address(). | |
1195 | */ | |
1196 | if (ret == TRANSLATE_G_STAGE_FAIL) { | |
1197 | first_stage_error = false; | |
1198 | access_type = MMU_DATA_LOAD; | |
1199 | } | |
1200 | ||
36a18664 AF |
1201 | qemu_log_mask(CPU_LOG_MMU, |
1202 | "%s 1st-stage address=%" VADDR_PRIx " ret %d physical " | |
1203 | TARGET_FMT_plx " prot %d\n", | |
1204 | __func__, address, ret, pa, prot); | |
1205 | ||
33a9a57d | 1206 | if (ret == TRANSLATE_SUCCESS) { |
36a18664 AF |
1207 | /* Second stage lookup */ |
1208 | im_address = pa; | |
1209 | ||
33a9a57d | 1210 | ret = get_physical_address(env, &pa, &prot2, im_address, NULL, |
11c27c6d JF |
1211 | access_type, mmu_idx, false, true, |
1212 | false); | |
36a18664 AF |
1213 | |
1214 | qemu_log_mask(CPU_LOG_MMU, | |
1215 | "%s 2nd-stage address=%" VADDR_PRIx " ret %d physical " | |
1216 | TARGET_FMT_plx " prot %d\n", | |
8f67cd6d AF |
1217 | __func__, im_address, ret, pa, prot2); |
1218 | ||
1219 | prot &= prot2; | |
36a18664 | 1220 | |
b297129a JS |
1221 | if (ret == TRANSLATE_SUCCESS) { |
1222 | ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, | |
1223 | size, access_type, mode); | |
663e1193 JS |
1224 | |
1225 | qemu_log_mask(CPU_LOG_MMU, | |
1226 | "%s PMP address=" TARGET_FMT_plx " ret %d prot" | |
1227 | " %d tlb_size " TARGET_FMT_lu "\n", | |
1228 | __func__, pa, ret, prot_pmp, tlb_size); | |
1229 | ||
b297129a | 1230 | prot &= prot_pmp; |
36a18664 AF |
1231 | } |
1232 | ||
1233 | if (ret != TRANSLATE_SUCCESS) { | |
1234 | /* | |
1235 | * Guest physical address translation failed, this is a HS | |
1236 | * level exception | |
1237 | */ | |
1238 | first_stage_error = false; | |
1239 | env->guest_phys_fault_addr = (im_address | | |
1240 | (address & | |
1241 | (TARGET_PAGE_SIZE - 1))) >> 2; | |
1242 | } | |
1243 | } | |
1244 | } else { | |
1245 | /* Single stage lookup */ | |
33a9a57d | 1246 | ret = get_physical_address(env, &pa, &prot, address, NULL, |
11c27c6d | 1247 | access_type, mmu_idx, true, false, false); |
36a18664 AF |
1248 | |
1249 | qemu_log_mask(CPU_LOG_MMU, | |
1250 | "%s address=%" VADDR_PRIx " ret %d physical " | |
1251 | TARGET_FMT_plx " prot %d\n", | |
1252 | __func__, address, ret, pa, prot); | |
8a4ca3c1 | 1253 | |
b297129a JS |
1254 | if (ret == TRANSLATE_SUCCESS) { |
1255 | ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, | |
1256 | size, access_type, mode); | |
663e1193 JS |
1257 | |
1258 | qemu_log_mask(CPU_LOG_MMU, | |
1259 | "%s PMP address=" TARGET_FMT_plx " ret %d prot" | |
1260 | " %d tlb_size " TARGET_FMT_lu "\n", | |
1261 | __func__, pa, ret, prot_pmp, tlb_size); | |
1262 | ||
b297129a JS |
1263 | prot &= prot_pmp; |
1264 | } | |
1f447aec | 1265 | } |
b297129a | 1266 | |
1f447aec | 1267 | if (ret == TRANSLATE_PMP_FAIL) { |
635b0b0e | 1268 | pmp_violation = true; |
0c3e702a | 1269 | } |
36a18664 | 1270 | |
0c3e702a | 1271 | if (ret == TRANSLATE_SUCCESS) { |
b297129a JS |
1272 | tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1), |
1273 | prot, mmu_idx, tlb_size); | |
8a4ca3c1 RH |
1274 | return true; |
1275 | } else if (probe) { | |
1276 | return false; | |
1277 | } else { | |
1c1c060a AF |
1278 | raise_mmu_exception(env, address, access_type, pmp_violation, |
1279 | first_stage_error, | |
1280 | riscv_cpu_virt_enabled(env) || | |
1281 | riscv_cpu_two_stage_lookup(mmu_idx)); | |
8a4ca3c1 | 1282 | riscv_raise_exception(env, cs->exception_index, retaddr); |
0c3e702a | 1283 | } |
36a18664 AF |
1284 | |
1285 | return true; | |
0c3e702a | 1286 | } |
263e2ab2 | 1287 | #endif /* !CONFIG_USER_ONLY */ |
0c3e702a MC |
1288 | |
1289 | /* | |
1290 | * Handle Traps | |
1291 | * | |
1292 | * Adapted from Spike's processor_t::take_trap. | |
1293 | * | |
1294 | */ | |
1295 | void riscv_cpu_do_interrupt(CPUState *cs) | |
1296 | { | |
1297 | #if !defined(CONFIG_USER_ONLY) | |
1298 | ||
1299 | RISCVCPU *cpu = RISCV_CPU(cs); | |
1300 | CPURISCVState *env = &cpu->env; | |
86d0c457 | 1301 | bool write_gva = false; |
284d697c | 1302 | uint64_t s; |
0c3e702a | 1303 | |
acbbb94e MC |
1304 | /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide |
1305 | * so we mask off the MSB and separate into trap type and cause. | |
1306 | */ | |
1307 | bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG); | |
1308 | target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; | |
d028ac75 | 1309 | uint64_t deleg = async ? env->mideleg : env->medeleg; |
acbbb94e | 1310 | target_ulong tval = 0; |
30675539 AF |
1311 | target_ulong htval = 0; |
1312 | target_ulong mtval2 = 0; | |
acbbb94e | 1313 | |
a10b9d93 KP |
1314 | if (cause == RISCV_EXCP_SEMIHOST) { |
1315 | if (env->priv >= PRV_S) { | |
1316 | env->gpr[xA0] = do_common_semihosting(cs); | |
1317 | env->pc += 4; | |
1318 | return; | |
1319 | } | |
1320 | cause = RISCV_EXCP_BREAKPOINT; | |
1321 | } | |
1322 | ||
acbbb94e MC |
1323 | if (!async) { |
1324 | /* set tval to badaddr for traps with address information */ | |
1325 | switch (cause) { | |
ab67a1d0 AF |
1326 | case RISCV_EXCP_INST_GUEST_PAGE_FAULT: |
1327 | case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: | |
1328 | case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: | |
acbbb94e MC |
1329 | case RISCV_EXCP_INST_ADDR_MIS: |
1330 | case RISCV_EXCP_INST_ACCESS_FAULT: | |
1331 | case RISCV_EXCP_LOAD_ADDR_MIS: | |
1332 | case RISCV_EXCP_STORE_AMO_ADDR_MIS: | |
1333 | case RISCV_EXCP_LOAD_ACCESS_FAULT: | |
1334 | case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: | |
1335 | case RISCV_EXCP_INST_PAGE_FAULT: | |
1336 | case RISCV_EXCP_LOAD_PAGE_FAULT: | |
1337 | case RISCV_EXCP_STORE_PAGE_FAULT: | |
86d0c457 | 1338 | write_gva = true; |
acbbb94e MC |
1339 | tval = env->badaddr; |
1340 | break; | |
48eaeb56 AF |
1341 | case RISCV_EXCP_ILLEGAL_INST: |
1342 | tval = env->bins; | |
1343 | break; | |
acbbb94e MC |
1344 | default: |
1345 | break; | |
0c3e702a | 1346 | } |
acbbb94e MC |
1347 | /* ecall is dispatched as one cause so translate based on mode */ |
1348 | if (cause == RISCV_EXCP_U_ECALL) { | |
1349 | assert(env->priv <= 3); | |
5eb9e782 AF |
1350 | |
1351 | if (env->priv == PRV_M) { | |
1352 | cause = RISCV_EXCP_M_ECALL; | |
1353 | } else if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) { | |
1354 | cause = RISCV_EXCP_VS_ECALL; | |
1355 | } else if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) { | |
1356 | cause = RISCV_EXCP_S_ECALL; | |
1357 | } else if (env->priv == PRV_U) { | |
1358 | cause = RISCV_EXCP_U_ECALL; | |
1359 | } | |
0c3e702a MC |
1360 | } |
1361 | } | |
1362 | ||
c51a3f5d | 1363 | trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, |
69430111 AF |
1364 | riscv_cpu_get_trap_name(cause, async)); |
1365 | ||
1366 | qemu_log_mask(CPU_LOG_INT, | |
1367 | "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", " | |
1368 | "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n", | |
1369 | __func__, env->mhartid, async, cause, env->pc, tval, | |
1370 | riscv_cpu_get_trap_name(cause, async)); | |
0c3e702a | 1371 | |
acbbb94e MC |
1372 | if (env->priv <= PRV_S && |
1373 | cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { | |
0c3e702a | 1374 | /* handle the trap in S-mode */ |
5eb9e782 | 1375 | if (riscv_has_ext(env, RVH)) { |
d028ac75 | 1376 | uint64_t hdeleg = async ? env->hideleg : env->hedeleg; |
1c1c060a | 1377 | |
50d16087 | 1378 | if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1)) { |
84b1c04b | 1379 | /* Trap to VS mode */ |
c5969a3a RK |
1380 | /* |
1381 | * See if we need to adjust cause. Yes if its VS mode interrupt | |
1382 | * no if hypervisor has delegated one of hs mode's interrupt | |
1383 | */ | |
1384 | if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || | |
84b1c04b | 1385 | cause == IRQ_VS_EXT) { |
c5969a3a | 1386 | cause = cause - 1; |
84b1c04b | 1387 | } |
86d0c457 | 1388 | write_gva = false; |
5eb9e782 AF |
1389 | } else if (riscv_cpu_virt_enabled(env)) { |
1390 | /* Trap into HS mode, from virt */ | |
1391 | riscv_cpu_swap_hypervisor_regs(env); | |
f2d5850f | 1392 | env->hstatus = set_field(env->hstatus, HSTATUS_SPVP, |
ace54453 | 1393 | env->priv); |
5eb9e782 AF |
1394 | env->hstatus = set_field(env->hstatus, HSTATUS_SPV, |
1395 | riscv_cpu_virt_enabled(env)); | |
1396 | ||
86d0c457 | 1397 | |
30675539 AF |
1398 | htval = env->guest_phys_fault_addr; |
1399 | ||
5eb9e782 | 1400 | riscv_cpu_set_virt_enabled(env, 0); |
5eb9e782 AF |
1401 | } else { |
1402 | /* Trap into HS mode */ | |
ec352d0c | 1403 | env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false); |
30675539 | 1404 | htval = env->guest_phys_fault_addr; |
86d0c457 | 1405 | write_gva = false; |
5eb9e782 | 1406 | } |
86d0c457 | 1407 | env->hstatus = set_field(env->hstatus, HSTATUS_GVA, write_gva); |
5eb9e782 AF |
1408 | } |
1409 | ||
1410 | s = env->mstatus; | |
1a9540d1 | 1411 | s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); |
0c3e702a MC |
1412 | s = set_field(s, MSTATUS_SPP, env->priv); |
1413 | s = set_field(s, MSTATUS_SIE, 0); | |
c7b95171 | 1414 | env->mstatus = s; |
16fdb8ff | 1415 | env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1)); |
acbbb94e | 1416 | env->sepc = env->pc; |
ac12b601 | 1417 | env->stval = tval; |
30675539 | 1418 | env->htval = htval; |
acbbb94e MC |
1419 | env->pc = (env->stvec >> 2 << 2) + |
1420 | ((async && (env->stvec & 3) == 1) ? cause * 4 : 0); | |
fb738839 | 1421 | riscv_cpu_set_mode(env, PRV_S); |
0c3e702a | 1422 | } else { |
acbbb94e | 1423 | /* handle the trap in M-mode */ |
5eb9e782 AF |
1424 | if (riscv_has_ext(env, RVH)) { |
1425 | if (riscv_cpu_virt_enabled(env)) { | |
1426 | riscv_cpu_swap_hypervisor_regs(env); | |
1427 | } | |
1428 | env->mstatus = set_field(env->mstatus, MSTATUS_MPV, | |
284d697c | 1429 | riscv_cpu_virt_enabled(env)); |
9034e90a AF |
1430 | if (riscv_cpu_virt_enabled(env) && tval) { |
1431 | env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1); | |
1432 | } | |
5eb9e782 | 1433 | |
30675539 AF |
1434 | mtval2 = env->guest_phys_fault_addr; |
1435 | ||
5eb9e782 AF |
1436 | /* Trapping to M mode, virt is disabled */ |
1437 | riscv_cpu_set_virt_enabled(env, 0); | |
5eb9e782 AF |
1438 | } |
1439 | ||
1440 | s = env->mstatus; | |
1a9540d1 | 1441 | s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); |
0c3e702a MC |
1442 | s = set_field(s, MSTATUS_MPP, env->priv); |
1443 | s = set_field(s, MSTATUS_MIE, 0); | |
c7b95171 | 1444 | env->mstatus = s; |
acbbb94e MC |
1445 | env->mcause = cause | ~(((target_ulong)-1) >> async); |
1446 | env->mepc = env->pc; | |
ac12b601 | 1447 | env->mtval = tval; |
30675539 | 1448 | env->mtval2 = mtval2; |
acbbb94e MC |
1449 | env->pc = (env->mtvec >> 2 << 2) + |
1450 | ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); | |
fb738839 | 1451 | riscv_cpu_set_mode(env, PRV_M); |
0c3e702a | 1452 | } |
d9360e96 MC |
1453 | |
1454 | /* NOTE: it is not necessary to yield load reservations here. It is only | |
1455 | * necessary for an SC from "another hart" to cause a load reservation | |
1456 | * to be yielded. Refer to the memory consistency model section of the | |
1457 | * RISC-V ISA Specification. | |
1458 | */ | |
1459 | ||
ec352d0c | 1460 | env->two_stage_lookup = false; |
0c3e702a | 1461 | #endif |
330d2ae3 | 1462 | cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */ |
0c3e702a | 1463 | } |