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0c3e702a | 1 | /* |
df354dd4 | 2 | * RISC-V CPU helpers for qemu. |
0c3e702a MC |
3 | * |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
21 | #include "qemu/log.h" | |
7ec5d303 | 22 | #include "qemu/main-loop.h" |
0c3e702a | 23 | #include "cpu.h" |
c8f8a995 | 24 | #include "internals.h" |
892320fa | 25 | #include "pmu.h" |
0c3e702a | 26 | #include "exec/exec-all.h" |
74781c08 | 27 | #include "exec/page-protection.h" |
8e2aa21b | 28 | #include "instmap.h" |
dcb32f1d | 29 | #include "tcg/tcg-op.h" |
929f0a7f | 30 | #include "trace.h" |
6b5fe137 | 31 | #include "semihosting/common-semi.h" |
2c9d7471 | 32 | #include "sysemu/cpu-timers.h" |
892320fa | 33 | #include "cpu_bits.h" |
2c9d7471 | 34 | #include "debug.h" |
70f168f8 | 35 | #include "tcg/oversized-guest.h" |
0c3e702a | 36 | |
7f6f2ebb | 37 | int riscv_env_mmu_index(CPURISCVState *env, bool ifetch) |
0c3e702a MC |
38 | { |
39 | #ifdef CONFIG_USER_ONLY | |
40 | return 0; | |
41 | #else | |
696bacde RH |
42 | bool virt = env->virt_enabled; |
43 | int mode = env->priv; | |
c8f8a995 FW |
44 | |
45 | /* All priv -> mmu_idx mapping are here */ | |
696bacde | 46 | if (!ifetch) { |
eaecd473 RH |
47 | uint64_t status = env->mstatus; |
48 | ||
49 | if (mode == PRV_M && get_field(status, MSTATUS_MPRV)) { | |
696bacde | 50 | mode = get_field(env->mstatus, MSTATUS_MPP); |
869d76f2 WL |
51 | virt = get_field(env->mstatus, MSTATUS_MPV) && |
52 | (mode != PRV_M); | |
eaecd473 RH |
53 | if (virt) { |
54 | status = env->vsstatus; | |
55 | } | |
696bacde | 56 | } |
eaecd473 | 57 | if (mode == PRV_S && get_field(status, MSTATUS_SUM)) { |
696bacde RH |
58 | mode = MMUIdx_S_SUM; |
59 | } | |
c8f8a995 | 60 | } |
696bacde RH |
61 | |
62 | return mode | (virt ? MMU_2STAGE_BIT : 0); | |
0c3e702a MC |
63 | #endif |
64 | } | |
65 | ||
bb5de525 AJ |
66 | void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, |
67 | uint64_t *cs_base, uint32_t *pflags) | |
53677acf | 68 | { |
614c9466 | 69 | RISCVCPU *cpu = env_archcpu(env); |
25f3ddff | 70 | RISCVExtStatus fs, vs; |
53677acf RH |
71 | uint32_t flags = 0; |
72 | ||
8c796f1a | 73 | *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc; |
53677acf RH |
74 | *cs_base = 0; |
75 | ||
3f4a5a53 | 76 | if (cpu->cfg.ext_zve32f) { |
a689a82b FC |
77 | /* |
78 | * If env->vl equals to VLMAX, we can use generic vector operation | |
79 | * expanders (GVEC) to accerlate the vector operations. | |
80 | * However, as LMUL could be a fractional number. The maximum | |
81 | * vector size can be operated might be less than 8 bytes, | |
82 | * which is not supported by GVEC. So we set vl_eq_vlmax flag to true | |
83 | * only when maxsz >= 8 bytes. | |
84 | */ | |
cd21576d DHB |
85 | |
86 | /* lmul encoded as in DisasContext::lmul */ | |
87 | int8_t lmul = sextract32(FIELD_EX64(env->vtype, VTYPE, VLMUL), 0, 3); | |
88 | uint32_t vsew = FIELD_EX64(env->vtype, VTYPE, VSEW); | |
89 | uint32_t vlmax = vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul); | |
90 | uint32_t maxsz = vlmax << vsew; | |
a689a82b FC |
91 | bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) && |
92 | (maxsz >= 8); | |
d96a271a | 93 | flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); |
cd21576d | 94 | flags = FIELD_DP32(flags, TB_FLAGS, SEW, vsew); |
53677acf | 95 | flags = FIELD_DP32(flags, TB_FLAGS, LMUL, |
c45eff30 | 96 | FIELD_EX64(env->vtype, VTYPE, VLMUL)); |
53677acf | 97 | flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); |
f1eed927 | 98 | flags = FIELD_DP32(flags, TB_FLAGS, VTA, |
c45eff30 | 99 | FIELD_EX64(env->vtype, VTYPE, VTA)); |
355d5584 | 100 | flags = FIELD_DP32(flags, TB_FLAGS, VMA, |
c45eff30 | 101 | FIELD_EX64(env->vtype, VTYPE, VMA)); |
4acaa133 | 102 | flags = FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart == 0); |
53677acf RH |
103 | } else { |
104 | flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); | |
105 | } | |
106 | ||
107 | #ifdef CONFIG_USER_ONLY | |
25f3ddff RH |
108 | fs = EXT_STATUS_DIRTY; |
109 | vs = EXT_STATUS_DIRTY; | |
53677acf | 110 | #else |
47debc72 FW |
111 | flags = FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv); |
112 | ||
d9996d09 | 113 | flags |= riscv_env_mmu_index(env, 0); |
25f3ddff RH |
114 | fs = get_field(env->mstatus, MSTATUS_FS); |
115 | vs = get_field(env->mstatus, MSTATUS_VS); | |
61b4b69d | 116 | |
0f58cbbe RH |
117 | if (env->virt_enabled) { |
118 | flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1); | |
119 | /* | |
120 | * Merge DISABLED and !DIRTY states using MIN. | |
121 | * We will set both fields when dirtying. | |
122 | */ | |
123 | fs = MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS)); | |
124 | vs = MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS)); | |
53677acf | 125 | } |
0f58cbbe | 126 | |
e0b343b5 MC |
127 | /* With Zfinx, floating point is enabled/disabled by Smstateen. */ |
128 | if (!riscv_has_ext(env, RVF)) { | |
129 | fs = (smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR) == RISCV_EXCP_NONE) | |
130 | ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED; | |
131 | } | |
132 | ||
cdfb2905 | 133 | if (cpu->cfg.debug && !icount_enabled()) { |
577f0286 | 134 | flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled); |
2c9d7471 | 135 | } |
53677acf RH |
136 | #endif |
137 | ||
25f3ddff RH |
138 | flags = FIELD_DP32(flags, TB_FLAGS, FS, fs); |
139 | flags = FIELD_DP32(flags, TB_FLAGS, VS, vs); | |
440544e1 | 140 | flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl); |
3a610f54 | 141 | flags = FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env)); |
b83e4f1d | 142 | if (env->cur_pmmask != 0) { |
4208dc7e LZ |
143 | flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); |
144 | } | |
145 | if (env->cur_pmbase != 0) { | |
146 | flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1); | |
147 | } | |
92371bd9 | 148 | |
53677acf RH |
149 | *pflags = flags; |
150 | } | |
151 | ||
40bfa5f6 LZ |
152 | void riscv_cpu_update_mask(CPURISCVState *env) |
153 | { | |
b83e4f1d | 154 | target_ulong mask = 0, base = 0; |
ef1ba32a | 155 | RISCVMXL xl = env->xl; |
40bfa5f6 LZ |
156 | /* |
157 | * TODO: Current RVJ spec does not specify | |
158 | * how the extension interacts with XLEN. | |
159 | */ | |
160 | #ifndef CONFIG_USER_ONLY | |
ef1ba32a WL |
161 | int mode = cpu_address_mode(env); |
162 | xl = cpu_get_xl(env, mode); | |
40bfa5f6 | 163 | if (riscv_has_ext(env, RVJ)) { |
ef1ba32a | 164 | switch (mode) { |
40bfa5f6 LZ |
165 | case PRV_M: |
166 | if (env->mmte & M_PM_ENABLE) { | |
167 | mask = env->mpmmask; | |
168 | base = env->mpmbase; | |
169 | } | |
170 | break; | |
171 | case PRV_S: | |
172 | if (env->mmte & S_PM_ENABLE) { | |
173 | mask = env->spmmask; | |
174 | base = env->spmbase; | |
175 | } | |
176 | break; | |
177 | case PRV_U: | |
178 | if (env->mmte & U_PM_ENABLE) { | |
179 | mask = env->upmmask; | |
180 | base = env->upmbase; | |
181 | } | |
182 | break; | |
183 | default: | |
184 | g_assert_not_reached(); | |
185 | } | |
186 | } | |
187 | #endif | |
ef1ba32a | 188 | if (xl == MXL_RV32) { |
40bfa5f6 LZ |
189 | env->cur_pmmask = mask & UINT32_MAX; |
190 | env->cur_pmbase = base & UINT32_MAX; | |
191 | } else { | |
192 | env->cur_pmmask = mask; | |
193 | env->cur_pmbase = base; | |
194 | } | |
195 | } | |
196 | ||
0c3e702a | 197 | #ifndef CONFIG_USER_ONLY |
43dc93af AP |
198 | |
199 | /* | |
200 | * The HS-mode is allowed to configure priority only for the | |
201 | * following VS-mode local interrupts: | |
202 | * | |
203 | * 0 (Reserved interrupt, reads as zero) | |
204 | * 1 Supervisor software interrupt | |
205 | * 4 (Reserved interrupt, reads as zero) | |
206 | * 5 Supervisor timer interrupt | |
207 | * 8 (Reserved interrupt, reads as zero) | |
208 | * 13 (Reserved interrupt) | |
209 | * 14 " | |
210 | * 15 " | |
211 | * 16 " | |
43577499 AP |
212 | * 17 " |
213 | * 18 " | |
214 | * 19 " | |
215 | * 20 " | |
216 | * 21 " | |
43dc93af | 217 | * 22 " |
43577499 | 218 | * 23 " |
43dc93af AP |
219 | */ |
220 | ||
221 | static const int hviprio_index2irq[] = { | |
43577499 | 222 | 0, 1, 4, 5, 8, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 }; |
43dc93af AP |
223 | static const int hviprio_index2rdzero[] = { |
224 | 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; | |
225 | ||
226 | int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero) | |
0c3e702a | 227 | { |
43dc93af AP |
228 | if (index < 0 || ARRAY_SIZE(hviprio_index2irq) <= index) { |
229 | return -EINVAL; | |
230 | } | |
3ef10a09 | 231 | |
43dc93af AP |
232 | if (out_irq) { |
233 | *out_irq = hviprio_index2irq[index]; | |
234 | } | |
3ef10a09 | 235 | |
43dc93af AP |
236 | if (out_rdzero) { |
237 | *out_rdzero = hviprio_index2rdzero[index]; | |
238 | } | |
cd032fe7 | 239 | |
43dc93af AP |
240 | return 0; |
241 | } | |
3ef10a09 | 242 | |
43dc93af AP |
243 | /* |
244 | * Default priorities of local interrupts are defined in the | |
245 | * RISC-V Advanced Interrupt Architecture specification. | |
246 | * | |
247 | * ---------------------------------------------------------------- | |
248 | * Default | | |
249 | * Priority | Major Interrupt Numbers | |
250 | * ---------------------------------------------------------------- | |
43577499 AP |
251 | * Highest | 47, 23, 46, 45, 22, 44, |
252 | * | 43, 21, 42, 41, 20, 40 | |
43dc93af AP |
253 | * | |
254 | * | 11 (0b), 3 (03), 7 (07) | |
255 | * | 9 (09), 1 (01), 5 (05) | |
256 | * | 12 (0c) | |
257 | * | 10 (0a), 2 (02), 6 (06) | |
258 | * | | |
43577499 AP |
259 | * | 39, 19, 38, 37, 18, 36, |
260 | * Lowest | 35, 17, 34, 33, 16, 32 | |
43dc93af AP |
261 | * ---------------------------------------------------------------- |
262 | */ | |
263 | static const uint8_t default_iprio[64] = { | |
c45eff30 WL |
264 | /* Custom interrupts 48 to 63 */ |
265 | [63] = IPRIO_MMAXIPRIO, | |
266 | [62] = IPRIO_MMAXIPRIO, | |
267 | [61] = IPRIO_MMAXIPRIO, | |
268 | [60] = IPRIO_MMAXIPRIO, | |
269 | [59] = IPRIO_MMAXIPRIO, | |
270 | [58] = IPRIO_MMAXIPRIO, | |
271 | [57] = IPRIO_MMAXIPRIO, | |
272 | [56] = IPRIO_MMAXIPRIO, | |
273 | [55] = IPRIO_MMAXIPRIO, | |
274 | [54] = IPRIO_MMAXIPRIO, | |
275 | [53] = IPRIO_MMAXIPRIO, | |
276 | [52] = IPRIO_MMAXIPRIO, | |
277 | [51] = IPRIO_MMAXIPRIO, | |
278 | [50] = IPRIO_MMAXIPRIO, | |
279 | [49] = IPRIO_MMAXIPRIO, | |
280 | [48] = IPRIO_MMAXIPRIO, | |
281 | ||
282 | /* Custom interrupts 24 to 31 */ | |
283 | [31] = IPRIO_MMAXIPRIO, | |
284 | [30] = IPRIO_MMAXIPRIO, | |
285 | [29] = IPRIO_MMAXIPRIO, | |
286 | [28] = IPRIO_MMAXIPRIO, | |
287 | [27] = IPRIO_MMAXIPRIO, | |
288 | [26] = IPRIO_MMAXIPRIO, | |
289 | [25] = IPRIO_MMAXIPRIO, | |
290 | [24] = IPRIO_MMAXIPRIO, | |
291 | ||
292 | [47] = IPRIO_DEFAULT_UPPER, | |
293 | [23] = IPRIO_DEFAULT_UPPER + 1, | |
294 | [46] = IPRIO_DEFAULT_UPPER + 2, | |
295 | [45] = IPRIO_DEFAULT_UPPER + 3, | |
296 | [22] = IPRIO_DEFAULT_UPPER + 4, | |
297 | [44] = IPRIO_DEFAULT_UPPER + 5, | |
298 | ||
299 | [43] = IPRIO_DEFAULT_UPPER + 6, | |
300 | [21] = IPRIO_DEFAULT_UPPER + 7, | |
301 | [42] = IPRIO_DEFAULT_UPPER + 8, | |
302 | [41] = IPRIO_DEFAULT_UPPER + 9, | |
303 | [20] = IPRIO_DEFAULT_UPPER + 10, | |
304 | [40] = IPRIO_DEFAULT_UPPER + 11, | |
305 | ||
306 | [11] = IPRIO_DEFAULT_M, | |
307 | [3] = IPRIO_DEFAULT_M + 1, | |
308 | [7] = IPRIO_DEFAULT_M + 2, | |
309 | ||
310 | [9] = IPRIO_DEFAULT_S, | |
311 | [1] = IPRIO_DEFAULT_S + 1, | |
312 | [5] = IPRIO_DEFAULT_S + 2, | |
313 | ||
314 | [12] = IPRIO_DEFAULT_SGEXT, | |
315 | ||
316 | [10] = IPRIO_DEFAULT_VS, | |
317 | [2] = IPRIO_DEFAULT_VS + 1, | |
318 | [6] = IPRIO_DEFAULT_VS + 2, | |
319 | ||
320 | [39] = IPRIO_DEFAULT_LOWER, | |
321 | [19] = IPRIO_DEFAULT_LOWER + 1, | |
322 | [38] = IPRIO_DEFAULT_LOWER + 2, | |
323 | [37] = IPRIO_DEFAULT_LOWER + 3, | |
324 | [18] = IPRIO_DEFAULT_LOWER + 4, | |
325 | [36] = IPRIO_DEFAULT_LOWER + 5, | |
326 | ||
327 | [35] = IPRIO_DEFAULT_LOWER + 6, | |
328 | [17] = IPRIO_DEFAULT_LOWER + 7, | |
329 | [34] = IPRIO_DEFAULT_LOWER + 8, | |
330 | [33] = IPRIO_DEFAULT_LOWER + 9, | |
331 | [16] = IPRIO_DEFAULT_LOWER + 10, | |
332 | [32] = IPRIO_DEFAULT_LOWER + 11, | |
43dc93af AP |
333 | }; |
334 | ||
335 | uint8_t riscv_cpu_default_priority(int irq) | |
336 | { | |
337 | if (irq < 0 || irq > 63) { | |
338 | return IPRIO_MMAXIPRIO; | |
339 | } | |
340 | ||
341 | return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO; | |
342 | }; | |
343 | ||
344 | static int riscv_cpu_pending_to_irq(CPURISCVState *env, | |
345 | int extirq, unsigned int extirq_def_prio, | |
346 | uint64_t pending, uint8_t *iprio) | |
347 | { | |
348 | int irq, best_irq = RISCV_EXCP_NONE; | |
349 | unsigned int prio, best_prio = UINT_MAX; | |
350 | ||
351 | if (!pending) { | |
352 | return RISCV_EXCP_NONE; | |
353 | } | |
354 | ||
355 | irq = ctz64(pending); | |
9c33e08b WL |
356 | if (!((extirq == IRQ_M_EXT) ? riscv_cpu_cfg(env)->ext_smaia : |
357 | riscv_cpu_cfg(env)->ext_ssaia)) { | |
43dc93af AP |
358 | return irq; |
359 | } | |
360 | ||
361 | pending = pending >> irq; | |
362 | while (pending) { | |
363 | prio = iprio[irq]; | |
364 | if (!prio) { | |
365 | if (irq == extirq) { | |
366 | prio = extirq_def_prio; | |
367 | } else { | |
368 | prio = (riscv_cpu_default_priority(irq) < extirq_def_prio) ? | |
369 | 1 : IPRIO_MMAXIPRIO; | |
370 | } | |
371 | } | |
372 | if ((pending & 0x1) && (prio <= best_prio)) { | |
373 | best_irq = irq; | |
374 | best_prio = prio; | |
375 | } | |
376 | irq++; | |
377 | pending = pending >> 1; | |
378 | } | |
379 | ||
380 | return best_irq; | |
381 | } | |
382 | ||
1697837e | 383 | /* |
40336d5b RK |
384 | * Doesn't report interrupts inserted using mvip from M-mode firmware or |
385 | * using hvip bits 13:63 from HS-mode. Those are returned in | |
386 | * riscv_cpu_sirq_pending() and riscv_cpu_vsirq_pending(). | |
1697837e | 387 | */ |
8f42415f | 388 | uint64_t riscv_cpu_all_pending(CPURISCVState *env) |
43dc93af AP |
389 | { |
390 | uint32_t gein = get_field(env->hstatus, HSTATUS_VGEIN); | |
391 | uint64_t vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; | |
3ec0fe18 | 392 | uint64_t vstip = (env->vstime_irq) ? MIP_VSTIP : 0; |
43dc93af | 393 | |
3ec0fe18 | 394 | return (env->mip | vsgein | vstip) & env->mie; |
43dc93af AP |
395 | } |
396 | ||
397 | int riscv_cpu_mirq_pending(CPURISCVState *env) | |
398 | { | |
399 | uint64_t irqs = riscv_cpu_all_pending(env) & ~env->mideleg & | |
400 | ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); | |
401 | ||
402 | return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, | |
403 | irqs, env->miprio); | |
404 | } | |
405 | ||
406 | int riscv_cpu_sirq_pending(CPURISCVState *env) | |
407 | { | |
408 | uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & | |
409 | ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); | |
1697837e | 410 | uint64_t irqs_f = env->mvip & env->mvien & ~env->mideleg & env->sie; |
43dc93af AP |
411 | |
412 | return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, | |
1697837e | 413 | irqs | irqs_f, env->siprio); |
43dc93af AP |
414 | } |
415 | ||
416 | int riscv_cpu_vsirq_pending(CPURISCVState *env) | |
417 | { | |
40336d5b RK |
418 | uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & env->hideleg; |
419 | uint64_t irqs_f_vs = env->hvip & env->hvien & ~env->hideleg & env->vsie; | |
420 | uint64_t vsbits; | |
421 | ||
422 | /* Bring VS-level bits to correct position */ | |
423 | vsbits = irqs & VS_MODE_INTERRUPTS; | |
424 | irqs &= ~VS_MODE_INTERRUPTS; | |
425 | irqs |= vsbits >> 1; | |
43dc93af AP |
426 | |
427 | return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, | |
40336d5b | 428 | (irqs | irqs_f_vs), env->hviprio); |
43dc93af AP |
429 | } |
430 | ||
431 | static int riscv_cpu_local_irq_pending(CPURISCVState *env) | |
432 | { | |
40336d5b RK |
433 | uint64_t irqs, pending, mie, hsie, vsie, irqs_f, irqs_f_vs; |
434 | uint64_t vsbits, irq_delegated; | |
43dc93af | 435 | int virq; |
43dc93af AP |
436 | |
437 | /* Determine interrupt enable state of all privilege modes */ | |
38256529 | 438 | if (env->virt_enabled) { |
43dc93af AP |
439 | mie = 1; |
440 | hsie = 1; | |
441 | vsie = (env->priv < PRV_S) || | |
442 | (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE)); | |
0c3e702a | 443 | } else { |
43dc93af AP |
444 | mie = (env->priv < PRV_M) || |
445 | (env->priv == PRV_M && get_field(env->mstatus, MSTATUS_MIE)); | |
446 | hsie = (env->priv < PRV_S) || | |
447 | (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE)); | |
448 | vsie = 0; | |
449 | } | |
450 | ||
451 | /* Determine all pending interrupts */ | |
452 | pending = riscv_cpu_all_pending(env); | |
453 | ||
454 | /* Check M-mode interrupts */ | |
455 | irqs = pending & ~env->mideleg & -mie; | |
456 | if (irqs) { | |
457 | return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, | |
458 | irqs, env->miprio); | |
459 | } | |
460 | ||
1697837e RK |
461 | /* Check for virtual S-mode interrupts. */ |
462 | irqs_f = env->mvip & (env->mvien & ~env->mideleg) & env->sie; | |
463 | ||
43dc93af | 464 | /* Check HS-mode interrupts */ |
1697837e | 465 | irqs = ((pending & env->mideleg & ~env->hideleg) | irqs_f) & -hsie; |
43dc93af AP |
466 | if (irqs) { |
467 | return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, | |
468 | irqs, env->siprio); | |
0c3e702a | 469 | } |
43dc93af | 470 | |
40336d5b RK |
471 | /* Check for virtual VS-mode interrupts. */ |
472 | irqs_f_vs = env->hvip & env->hvien & ~env->hideleg & env->vsie; | |
473 | ||
43dc93af | 474 | /* Check VS-mode interrupts */ |
40336d5b RK |
475 | irq_delegated = pending & env->mideleg & env->hideleg; |
476 | ||
477 | /* Bring VS-level bits to correct position */ | |
478 | vsbits = irq_delegated & VS_MODE_INTERRUPTS; | |
479 | irq_delegated &= ~VS_MODE_INTERRUPTS; | |
480 | irq_delegated |= vsbits >> 1; | |
481 | ||
482 | irqs = (irq_delegated | irqs_f_vs) & -vsie; | |
43dc93af AP |
483 | if (irqs) { |
484 | virq = riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, | |
40336d5b RK |
485 | irqs, env->hviprio); |
486 | if (virq <= 0 || (virq > 12 && virq <= 63)) { | |
487 | return virq; | |
488 | } else { | |
489 | return virq + 1; | |
490 | } | |
43dc93af AP |
491 | } |
492 | ||
493 | /* Indicate no pending interrupt */ | |
494 | return RISCV_EXCP_NONE; | |
0c3e702a | 495 | } |
0c3e702a MC |
496 | |
497 | bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) | |
498 | { | |
0c3e702a MC |
499 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
500 | RISCVCPU *cpu = RISCV_CPU(cs); | |
501 | CPURISCVState *env = &cpu->env; | |
efbdbc26 | 502 | int interruptno = riscv_cpu_local_irq_pending(env); |
0c3e702a MC |
503 | if (interruptno >= 0) { |
504 | cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno; | |
505 | riscv_cpu_do_interrupt(cs); | |
506 | return true; | |
507 | } | |
508 | } | |
0c3e702a MC |
509 | return false; |
510 | } | |
511 | ||
b345b480 AF |
512 | /* Return true is floating point support is currently enabled */ |
513 | bool riscv_cpu_fp_enabled(CPURISCVState *env) | |
514 | { | |
515 | if (env->mstatus & MSTATUS_FS) { | |
38256529 | 516 | if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_FS)) { |
29409c1d AF |
517 | return false; |
518 | } | |
b345b480 AF |
519 | return true; |
520 | } | |
521 | ||
522 | return false; | |
523 | } | |
524 | ||
61b4b69d LZ |
525 | /* Return true is vector support is currently enabled */ |
526 | bool riscv_cpu_vector_enabled(CPURISCVState *env) | |
527 | { | |
528 | if (env->mstatus & MSTATUS_VS) { | |
38256529 | 529 | if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_VS)) { |
61b4b69d LZ |
530 | return false; |
531 | } | |
532 | return true; | |
533 | } | |
534 | ||
535 | return false; | |
536 | } | |
537 | ||
66e594f2 AF |
538 | void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) |
539 | { | |
c163b3ba | 540 | uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | |
284d697c | 541 | MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | |
61b4b69d | 542 | MSTATUS64_UXL | MSTATUS_VS; |
c163b3ba WL |
543 | |
544 | if (riscv_has_ext(env, RVF)) { | |
545 | mstatus_mask |= MSTATUS_FS; | |
546 | } | |
38256529 | 547 | bool current_virt = env->virt_enabled; |
66e594f2 AF |
548 | |
549 | g_assert(riscv_has_ext(env, RVH)); | |
550 | ||
66e594f2 AF |
551 | if (current_virt) { |
552 | /* Current V=1 and we are about to change to V=0 */ | |
553 | env->vsstatus = env->mstatus & mstatus_mask; | |
554 | env->mstatus &= ~mstatus_mask; | |
555 | env->mstatus |= env->mstatus_hs; | |
556 | ||
557 | env->vstvec = env->stvec; | |
558 | env->stvec = env->stvec_hs; | |
559 | ||
560 | env->vsscratch = env->sscratch; | |
561 | env->sscratch = env->sscratch_hs; | |
562 | ||
563 | env->vsepc = env->sepc; | |
564 | env->sepc = env->sepc_hs; | |
565 | ||
566 | env->vscause = env->scause; | |
567 | env->scause = env->scause_hs; | |
568 | ||
ac12b601 AP |
569 | env->vstval = env->stval; |
570 | env->stval = env->stval_hs; | |
66e594f2 AF |
571 | |
572 | env->vsatp = env->satp; | |
573 | env->satp = env->satp_hs; | |
574 | } else { | |
575 | /* Current V=0 and we are about to change to V=1 */ | |
576 | env->mstatus_hs = env->mstatus & mstatus_mask; | |
577 | env->mstatus &= ~mstatus_mask; | |
578 | env->mstatus |= env->vsstatus; | |
579 | ||
580 | env->stvec_hs = env->stvec; | |
581 | env->stvec = env->vstvec; | |
582 | ||
583 | env->sscratch_hs = env->sscratch; | |
584 | env->sscratch = env->vsscratch; | |
585 | ||
586 | env->sepc_hs = env->sepc; | |
587 | env->sepc = env->vsepc; | |
588 | ||
589 | env->scause_hs = env->scause; | |
590 | env->scause = env->vscause; | |
591 | ||
ac12b601 AP |
592 | env->stval_hs = env->stval; |
593 | env->stval = env->vstval; | |
66e594f2 AF |
594 | |
595 | env->satp_hs = env->satp; | |
596 | env->satp = env->vsatp; | |
597 | } | |
598 | } | |
599 | ||
cd032fe7 AP |
600 | target_ulong riscv_cpu_get_geilen(CPURISCVState *env) |
601 | { | |
602 | if (!riscv_has_ext(env, RVH)) { | |
603 | return 0; | |
604 | } | |
605 | ||
606 | return env->geilen; | |
607 | } | |
608 | ||
609 | void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen) | |
610 | { | |
611 | if (!riscv_has_ext(env, RVH)) { | |
612 | return; | |
613 | } | |
614 | ||
615 | if (geilen > (TARGET_LONG_BITS - 1)) { | |
616 | return; | |
617 | } | |
618 | ||
619 | env->geilen = geilen; | |
620 | } | |
621 | ||
c43732f5 | 622 | /* This function can only be called to set virt when RVH is enabled */ |
ef6bb7b6 AF |
623 | void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) |
624 | { | |
eccc5a12 | 625 | /* Flush the TLB on all virt mode changes. */ |
b3c5077b | 626 | if (env->virt_enabled != enable) { |
eccc5a12 AF |
627 | tlb_flush(env_cpu(env)); |
628 | } | |
629 | ||
b3c5077b | 630 | env->virt_enabled = enable; |
02d9565b AP |
631 | |
632 | if (enable) { | |
633 | /* | |
634 | * The guest external interrupts from an interrupt controller are | |
635 | * delivered only when the Guest/VM is running (i.e. V=1). This means | |
636 | * any guest external interrupt which is triggered while the Guest/VM | |
637 | * is not running (i.e. V=0) will be missed on QEMU resulting in guest | |
638 | * with sluggish response to serial console input and other I/O events. | |
639 | * | |
640 | * To solve this, we check and inject interrupt after setting V=1. | |
641 | */ | |
bbb9fc25 | 642 | riscv_cpu_update_mip(env, 0, 0); |
02d9565b | 643 | } |
ef6bb7b6 AF |
644 | } |
645 | ||
d028ac75 | 646 | int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts) |
e3e7039c MC |
647 | { |
648 | CPURISCVState *env = &cpu->env; | |
649 | if (env->miclaim & interrupts) { | |
650 | return -1; | |
651 | } else { | |
652 | env->miclaim |= interrupts; | |
653 | return 0; | |
654 | } | |
655 | } | |
656 | ||
1ebad505 | 657 | void riscv_cpu_interrupt(CPURISCVState *env) |
df354dd4 | 658 | { |
1697837e | 659 | uint64_t gein, vsgein = 0, vstip = 0, irqf = 0; |
bbb9fc25 | 660 | CPUState *cs = env_cpu(env); |
1ebad505 | 661 | |
32ead8e6 | 662 | BQL_LOCK_GUARD(); |
7ec5d303 | 663 | |
38256529 | 664 | if (env->virt_enabled) { |
cd032fe7 AP |
665 | gein = get_field(env->hstatus, HSTATUS_VGEIN); |
666 | vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; | |
40336d5b | 667 | irqf = env->hvien & env->hvip & env->vsie; |
1697837e RK |
668 | } else { |
669 | irqf = env->mvien & env->mvip & env->sie; | |
cd032fe7 AP |
670 | } |
671 | ||
3ec0fe18 AP |
672 | vstip = env->vstime_irq ? MIP_VSTIP : 0; |
673 | ||
1697837e | 674 | if (env->mip | vsgein | vstip | irqf) { |
7ec5d303 AF |
675 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
676 | } else { | |
677 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); | |
678 | } | |
1ebad505 RK |
679 | } |
680 | ||
681 | uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, uint64_t value) | |
682 | { | |
683 | uint64_t old = env->mip; | |
684 | ||
685 | /* No need to update mip for VSTIP */ | |
686 | mask = ((mask == MIP_VSTIP) && env->vstime_irq) ? 0 : mask; | |
687 | ||
32ead8e6 | 688 | BQL_LOCK_GUARD(); |
1ebad505 RK |
689 | |
690 | env->mip = (env->mip & ~mask) | (value & mask); | |
691 | ||
692 | riscv_cpu_interrupt(env); | |
0a01f2ee | 693 | |
df354dd4 MC |
694 | return old; |
695 | } | |
696 | ||
e2f01f3c FC |
697 | void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), |
698 | void *arg) | |
c6957248 AP |
699 | { |
700 | env->rdtime_fn = fn; | |
a47ef6e9 | 701 | env->rdtime_fn_arg = arg; |
c6957248 AP |
702 | } |
703 | ||
69077dd6 AP |
704 | void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, |
705 | int (*rmw_fn)(void *arg, | |
706 | target_ulong reg, | |
707 | target_ulong *val, | |
708 | target_ulong new_val, | |
709 | target_ulong write_mask), | |
710 | void *rmw_fn_arg) | |
711 | { | |
712 | if (priv <= PRV_M) { | |
713 | env->aia_ireg_rmw_fn[priv] = rmw_fn; | |
714 | env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg; | |
715 | } | |
716 | } | |
717 | ||
fb738839 | 718 | void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) |
df354dd4 | 719 | { |
0c98ccef WL |
720 | g_assert(newpriv <= PRV_M && newpriv != PRV_RESERVED); |
721 | ||
5a4ae64c LZ |
722 | if (icount_enabled() && newpriv != env->priv) { |
723 | riscv_itrigger_update_priv(env); | |
724 | } | |
df354dd4 MC |
725 | /* tlb_flush is unnecessary as mode is contained in mmu_idx */ |
726 | env->priv = newpriv; | |
440544e1 | 727 | env->xl = cpu_recompute_xl(env); |
40bfa5f6 | 728 | riscv_cpu_update_mask(env); |
c13b169f JS |
729 | |
730 | /* | |
731 | * Clear the load reservation - otherwise a reservation placed in one | |
732 | * context/process can be used by another, resulting in an SC succeeding | |
733 | * incorrectly. Version 2.2 of the ISA specification explicitly requires | |
734 | * this behaviour, while later revisions say that the kernel "should" use | |
735 | * an SC instruction to force the yielding of a load reservation on a | |
736 | * preemptive context switch. As a result, do both. | |
737 | */ | |
738 | env->load_res = -1; | |
df354dd4 MC |
739 | } |
740 | ||
b297129a JS |
741 | /* |
742 | * get_physical_address_pmp - check PMP permission for this physical address | |
743 | * | |
744 | * Match the PMP region and check permission for this physical address and it's | |
745 | * TLB page. Returns 0 if the permission checking was successful | |
746 | * | |
747 | * @env: CPURISCVState | |
748 | * @prot: The returned protection attributes | |
b297129a JS |
749 | * @addr: The physical address to be checked permission |
750 | * @access_type: The type of MMU access | |
751 | * @mode: Indicates current privilege level. | |
752 | */ | |
bfc7ee12 | 753 | static int get_physical_address_pmp(CPURISCVState *env, int *prot, hwaddr addr, |
b297129a JS |
754 | int size, MMUAccessType access_type, |
755 | int mode) | |
756 | { | |
757 | pmp_priv_t pmp_priv; | |
e9c39713 | 758 | bool pmp_has_privs; |
b297129a | 759 | |
3fe40ef5 | 760 | if (!riscv_cpu_cfg(env)->pmp) { |
b297129a JS |
761 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
762 | return TRANSLATE_SUCCESS; | |
763 | } | |
764 | ||
e9c39713 WL |
765 | pmp_has_privs = pmp_hart_has_privs(env, addr, size, 1 << access_type, |
766 | &pmp_priv, mode); | |
767 | if (!pmp_has_privs) { | |
b297129a JS |
768 | *prot = 0; |
769 | return TRANSLATE_PMP_FAIL; | |
770 | } | |
771 | ||
772 | *prot = pmp_priv_to_page_prot(pmp_priv); | |
b297129a JS |
773 | |
774 | return TRANSLATE_SUCCESS; | |
775 | } | |
776 | ||
3b57254d WL |
777 | /* |
778 | * get_physical_address - get the physical address for this virtual address | |
0c3e702a MC |
779 | * |
780 | * Do a page table walk to obtain the physical address corresponding to a | |
781 | * virtual address. Returns 0 if the translation was successful | |
782 | * | |
783 | * Adapted from Spike's mmu_t::translate and mmu_t::walk | |
784 | * | |
1448689c AF |
785 | * @env: CPURISCVState |
786 | * @physical: This will be set to the calculated physical address | |
787 | * @prot: The returned protection attributes | |
77dff650 | 788 | * @addr: The virtual address or guest physical address to be translated |
33a9a57d YJ |
789 | * @fault_pte_addr: If not NULL, this will be set to fault pte address |
790 | * when a error occurs on pte address translation. | |
791 | * This will already be shifted to match htval. | |
1448689c AF |
792 | * @access_type: The type of MMU access |
793 | * @mmu_idx: Indicates current privilege level | |
794 | * @first_stage: Are we in first stage translation? | |
795 | * Second stage is used for hypervisor guest translation | |
36a18664 | 796 | * @two_stage: Are we going to perform two stage translation |
11c27c6d | 797 | * @is_debug: Is this access from a debugger or the monitor? |
0c3e702a MC |
798 | */ |
799 | static int get_physical_address(CPURISCVState *env, hwaddr *physical, | |
e1dd1507 | 800 | int *ret_prot, vaddr addr, |
33a9a57d | 801 | target_ulong *fault_pte_addr, |
1448689c | 802 | int access_type, int mmu_idx, |
11c27c6d JF |
803 | bool first_stage, bool two_stage, |
804 | bool is_debug) | |
0c3e702a | 805 | { |
3b57254d WL |
806 | /* |
807 | * NOTE: the env->pc value visible here will not be | |
0c3e702a | 808 | * correct, but the value visible to the exception handler |
3b57254d WL |
809 | * (riscv_cpu_do_interrupt) is correct |
810 | */ | |
aacb578f PD |
811 | MemTxResult res; |
812 | MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; | |
340b5805 | 813 | int mode = mmuidx_priv(mmu_idx); |
36a18664 | 814 | bool use_background = false; |
05e6ca5e | 815 | hwaddr ppn; |
2bacb224 WL |
816 | int napot_bits = 0; |
817 | target_ulong napot_mask; | |
0c3e702a | 818 | |
36a18664 AF |
819 | /* |
820 | * Check if we should use the background registers for the two | |
821 | * stage translation. We don't need to check if we actually need | |
822 | * two stage translation as that happened before this function | |
823 | * was called. Background registers will be used if the guest has | |
824 | * forced a two stage translation to be on (in HS or M mode). | |
825 | */ | |
38256529 | 826 | if (!env->virt_enabled && two_stage) { |
29b3361b AF |
827 | use_background = true; |
828 | } | |
829 | ||
dcf654a3 | 830 | if (mode == PRV_M || !riscv_cpu_cfg(env)->mmu) { |
0c3e702a | 831 | *physical = addr; |
e1dd1507 | 832 | *ret_prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
0c3e702a MC |
833 | return TRANSLATE_SUCCESS; |
834 | } | |
835 | ||
e1dd1507 | 836 | *ret_prot = 0; |
0c3e702a | 837 | |
ddf78132 | 838 | hwaddr base; |
38303e8a | 839 | int levels, ptidxbits, ptesize, vm, widened; |
0c3e702a | 840 | |
1a9540d1 AF |
841 | if (first_stage == true) { |
842 | if (use_background) { | |
db23e5d9 | 843 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
419ddf00 AF |
844 | base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT; |
845 | vm = get_field(env->vsatp, SATP32_MODE); | |
846 | } else { | |
847 | base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT; | |
848 | vm = get_field(env->vsatp, SATP64_MODE); | |
849 | } | |
36a18664 | 850 | } else { |
db23e5d9 | 851 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
419ddf00 AF |
852 | base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; |
853 | vm = get_field(env->satp, SATP32_MODE); | |
854 | } else { | |
855 | base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT; | |
856 | vm = get_field(env->satp, SATP64_MODE); | |
857 | } | |
0c3e702a | 858 | } |
36a18664 | 859 | widened = 0; |
1a9540d1 | 860 | } else { |
db23e5d9 | 861 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
994b6bb2 AF |
862 | base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT; |
863 | vm = get_field(env->hgatp, SATP32_MODE); | |
864 | } else { | |
865 | base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT; | |
866 | vm = get_field(env->hgatp, SATP64_MODE); | |
867 | } | |
1a9540d1 AF |
868 | widened = 2; |
869 | } | |
38303e8a | 870 | |
1a9540d1 AF |
871 | switch (vm) { |
872 | case VM_1_10_SV32: | |
873 | levels = 2; ptidxbits = 10; ptesize = 4; break; | |
874 | case VM_1_10_SV39: | |
875 | levels = 3; ptidxbits = 9; ptesize = 8; break; | |
876 | case VM_1_10_SV48: | |
877 | levels = 4; ptidxbits = 9; ptesize = 8; break; | |
878 | case VM_1_10_SV57: | |
879 | levels = 5; ptidxbits = 9; ptesize = 8; break; | |
880 | case VM_1_10_MBARE: | |
881 | *physical = addr; | |
e1dd1507 | 882 | *ret_prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
1a9540d1 AF |
883 | return TRANSLATE_SUCCESS; |
884 | default: | |
885 | g_assert_not_reached(); | |
0c3e702a MC |
886 | } |
887 | ||
3109cd98 | 888 | CPUState *cs = env_cpu(env); |
36a18664 | 889 | int va_bits = PGSHIFT + levels * ptidxbits + widened; |
36a18664 | 890 | |
7bf14a2f IR |
891 | if (first_stage == true) { |
892 | target_ulong mask, masked_msbs; | |
36a18664 | 893 | |
7bf14a2f IR |
894 | if (TARGET_LONG_BITS > (va_bits - 1)) { |
895 | mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; | |
896 | } else { | |
897 | mask = 0; | |
898 | } | |
899 | masked_msbs = (addr >> (va_bits - 1)) & mask; | |
900 | ||
901 | if (masked_msbs != 0 && masked_msbs != mask) { | |
902 | return TRANSLATE_FAIL; | |
903 | } | |
904 | } else { | |
905 | if (vm != VM_1_10_SV32 && addr >> va_bits != 0) { | |
906 | return TRANSLATE_FAIL; | |
907 | } | |
0c3e702a MC |
908 | } |
909 | ||
8d6a00cd | 910 | bool pbmte = env->menvcfg & MENVCFG_PBMTE; |
70d22fd9 AJ |
911 | bool svade = riscv_cpu_cfg(env)->ext_svade; |
912 | bool svadu = riscv_cpu_cfg(env)->ext_svadu; | |
913 | bool adue = svadu ? env->menvcfg & MENVCFG_ADUE : !svade; | |
8d6a00cd RH |
914 | |
915 | if (first_stage && two_stage && env->virt_enabled) { | |
916 | pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE); | |
ed67d637 | 917 | adue = adue && (env->henvcfg & HENVCFG_ADUE); |
8d6a00cd RH |
918 | } |
919 | ||
0c3e702a | 920 | int ptshift = (levels - 1) * ptidxbits; |
59688aa0 RH |
921 | target_ulong pte; |
922 | hwaddr pte_addr; | |
0c3e702a MC |
923 | int i; |
924 | ||
925 | #if !TCG_OVERSIZED_GUEST | |
926 | restart: | |
927 | #endif | |
928 | for (i = 0; i < levels; i++, ptshift -= ptidxbits) { | |
36a18664 AF |
929 | target_ulong idx; |
930 | if (i == 0) { | |
931 | idx = (addr >> (PGSHIFT + ptshift)) & | |
932 | ((1 << (ptidxbits + widened)) - 1); | |
933 | } else { | |
934 | idx = (addr >> (PGSHIFT + ptshift)) & | |
0c3e702a | 935 | ((1 << ptidxbits) - 1); |
36a18664 | 936 | } |
0c3e702a MC |
937 | |
938 | /* check that physical address of PTE is legal */ | |
36a18664 AF |
939 | |
940 | if (two_stage && first_stage) { | |
38472890 | 941 | int vbase_prot; |
36a18664 AF |
942 | hwaddr vbase; |
943 | ||
944 | /* Do the second stage translation on the base PTE address. */ | |
88914473 | 945 | int vbase_ret = get_physical_address(env, &vbase, &vbase_prot, |
33a9a57d | 946 | base, NULL, MMU_DATA_LOAD, |
a427c836 | 947 | MMUIdx_U, false, true, |
11c27c6d | 948 | is_debug); |
88914473 AF |
949 | |
950 | if (vbase_ret != TRANSLATE_SUCCESS) { | |
33a9a57d YJ |
951 | if (fault_pte_addr) { |
952 | *fault_pte_addr = (base + idx * ptesize) >> 2; | |
953 | } | |
954 | return TRANSLATE_G_STAGE_FAIL; | |
88914473 | 955 | } |
36a18664 AF |
956 | |
957 | pte_addr = vbase + idx * ptesize; | |
958 | } else { | |
959 | pte_addr = base + idx * ptesize; | |
960 | } | |
1f447aec | 961 | |
b297129a | 962 | int pmp_prot; |
bfc7ee12 | 963 | int pmp_ret = get_physical_address_pmp(env, &pmp_prot, pte_addr, |
b297129a JS |
964 | sizeof(target_ulong), |
965 | MMU_DATA_LOAD, PRV_S); | |
966 | if (pmp_ret != TRANSLATE_SUCCESS) { | |
1f447aec HA |
967 | return TRANSLATE_PMP_FAIL; |
968 | } | |
aacb578f | 969 | |
db23e5d9 | 970 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
f08c7ff3 AF |
971 | pte = address_space_ldl(cs->as, pte_addr, attrs, &res); |
972 | } else { | |
973 | pte = address_space_ldq(cs->as, pte_addr, attrs, &res); | |
974 | } | |
975 | ||
aacb578f PD |
976 | if (res != MEMTX_OK) { |
977 | return TRANSLATE_FAIL; | |
978 | } | |
979 | ||
05e6ca5e GR |
980 | if (riscv_cpu_sxl(env) == MXL_RV32) { |
981 | ppn = pte >> PTE_PPN_SHIFT; | |
05e6ca5e | 982 | } else { |
190e9f8e AG |
983 | if (pte & PTE_RESERVED) { |
984 | return TRANSLATE_FAIL; | |
985 | } | |
986 | ||
987 | if (!pbmte && (pte & PTE_PBMT)) { | |
05e6ca5e GR |
988 | return TRANSLATE_FAIL; |
989 | } | |
190e9f8e AG |
990 | |
991 | if (!riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { | |
992 | return TRANSLATE_FAIL; | |
993 | } | |
994 | ||
995 | ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT; | |
05e6ca5e | 996 | } |
0c3e702a | 997 | |
c3b03e58 MC |
998 | if (!(pte & PTE_V)) { |
999 | /* Invalid PTE */ | |
1000 | return TRANSLATE_FAIL; | |
59688aa0 RH |
1001 | } |
1002 | if (pte & (PTE_R | PTE_W | PTE_X)) { | |
1003 | goto leaf; | |
1004 | } | |
1005 | ||
1006 | /* Inner PTE, continue walking */ | |
1007 | if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) { | |
c3b03e58 | 1008 | return TRANSLATE_FAIL; |
59688aa0 RH |
1009 | } |
1010 | base = ppn << PGSHIFT; | |
1011 | } | |
1012 | ||
1013 | /* No leaf pte at any translation level. */ | |
1014 | return TRANSLATE_FAIL; | |
1015 | ||
1016 | leaf: | |
1017 | if (ppn & ((1ULL << ptshift) - 1)) { | |
1018 | /* Misaligned PPN */ | |
1019 | return TRANSLATE_FAIL; | |
1020 | } | |
1021 | if (!pbmte && (pte & PTE_PBMT)) { | |
1022 | /* Reserved without Svpbmt. */ | |
1023 | return TRANSLATE_FAIL; | |
1024 | } | |
a9d2e3ed RH |
1025 | |
1026 | /* Check for reserved combinations of RWX flags. */ | |
1027 | switch (pte & (PTE_R | PTE_W | PTE_X)) { | |
1028 | case PTE_W: | |
1029 | case PTE_W | PTE_X: | |
59688aa0 RH |
1030 | return TRANSLATE_FAIL; |
1031 | } | |
a9d2e3ed | 1032 | |
e1dd1507 RH |
1033 | int prot = 0; |
1034 | if (pte & PTE_R) { | |
1035 | prot |= PAGE_READ; | |
1036 | } | |
1037 | if (pte & PTE_W) { | |
1038 | prot |= PAGE_WRITE; | |
1039 | } | |
1040 | if (pte & PTE_X) { | |
6bca4d7d | 1041 | bool mxr = false; |
e1dd1507 | 1042 | |
6bca4d7d IK |
1043 | /* |
1044 | * Use mstatus for first stage or for the second stage without | |
1045 | * virt_enabled (MPRV+MPV) | |
1046 | */ | |
1047 | if (first_stage || !env->virt_enabled) { | |
e1dd1507 | 1048 | mxr = get_field(env->mstatus, MSTATUS_MXR); |
e1dd1507 | 1049 | } |
6bca4d7d IK |
1050 | |
1051 | /* MPRV+MPV case, check VSSTATUS */ | |
1052 | if (first_stage && two_stage && !env->virt_enabled) { | |
1053 | mxr |= get_field(env->vsstatus, MSTATUS_MXR); | |
1054 | } | |
1055 | ||
1056 | /* | |
1057 | * Setting MXR at HS-level overrides both VS-stage and G-stage | |
1058 | * execute-only permissions | |
1059 | */ | |
1060 | if (env->virt_enabled) { | |
1061 | mxr |= get_field(env->mstatus_hs, MSTATUS_MXR); | |
1062 | } | |
1063 | ||
e1dd1507 RH |
1064 | if (mxr) { |
1065 | prot |= PAGE_READ; | |
1066 | } | |
1067 | prot |= PAGE_EXEC; | |
1068 | } | |
1069 | ||
38303e8a RH |
1070 | if (pte & PTE_U) { |
1071 | if (mode != PRV_U) { | |
1072 | if (!mmuidx_sum(mmu_idx)) { | |
1073 | return TRANSLATE_FAIL; | |
1074 | } | |
1075 | /* SUM allows only read+write, not execute. */ | |
1076 | prot &= PAGE_READ | PAGE_WRITE; | |
1077 | } | |
1078 | } else if (mode != PRV_S) { | |
59688aa0 RH |
1079 | /* Supervisor PTE flags when not S mode */ |
1080 | return TRANSLATE_FAIL; | |
1081 | } | |
e1dd1507 RH |
1082 | |
1083 | if (!((prot >> access_type) & 1)) { | |
1084 | /* Access check failed */ | |
59688aa0 RH |
1085 | return TRANSLATE_FAIL; |
1086 | } | |
1087 | ||
70d22fd9 AJ |
1088 | target_ulong updated_pte = pte; |
1089 | ||
1090 | /* | |
1091 | * If ADUE is enabled, set accessed and dirty bits. | |
1092 | * Otherwise raise an exception if necessary. | |
1093 | */ | |
1094 | if (adue) { | |
1095 | updated_pte |= PTE_A | (access_type == MMU_DATA_STORE ? PTE_D : 0); | |
1096 | } else if (!(pte & PTE_A) || | |
1097 | (access_type == MMU_DATA_STORE && !(pte & PTE_D))) { | |
1098 | return TRANSLATE_FAIL; | |
1099 | } | |
0c3e702a | 1100 | |
59688aa0 | 1101 | /* Page table updates need to be atomic with MTTCG enabled */ |
0a19bf5e | 1102 | if (updated_pte != pte && !is_debug) { |
ed67d637 | 1103 | if (!adue) { |
59688aa0 RH |
1104 | return TRANSLATE_FAIL; |
1105 | } | |
0af3f115 | 1106 | |
59688aa0 RH |
1107 | /* |
1108 | * - if accessed or dirty bits need updating, and the PTE is | |
1109 | * in RAM, then we do so atomically with a compare and swap. | |
1110 | * - if the PTE is in IO space or ROM, then it can't be updated | |
1111 | * and we return TRANSLATE_FAIL. | |
1112 | * - if the PTE changed by the time we went to update it, then | |
1113 | * it is no longer valid and we must re-walk the page table. | |
1114 | */ | |
1115 | MemoryRegion *mr; | |
1116 | hwaddr l = sizeof(target_ulong), addr1; | |
1117 | mr = address_space_translate(cs->as, pte_addr, &addr1, &l, | |
1118 | false, MEMTXATTRS_UNSPECIFIED); | |
1119 | if (memory_region_is_ram(mr)) { | |
1120 | target_ulong *pte_pa = qemu_map_ram_ptr(mr->ram_block, addr1); | |
0c3e702a | 1121 | #if TCG_OVERSIZED_GUEST |
59688aa0 RH |
1122 | /* |
1123 | * MTTCG is not enabled on oversized TCG guests so | |
1124 | * page table updates do not need to be atomic | |
1125 | */ | |
1126 | *pte_pa = pte = updated_pte; | |
0c3e702a | 1127 | #else |
59688aa0 RH |
1128 | target_ulong old_pte = qatomic_cmpxchg(pte_pa, pte, updated_pte); |
1129 | if (old_pte != pte) { | |
1130 | goto restart; | |
0c3e702a | 1131 | } |
59688aa0 RH |
1132 | pte = updated_pte; |
1133 | #endif | |
1134 | } else { | |
3b57254d | 1135 | /* |
59688aa0 RH |
1136 | * Misconfigured PTE in ROM (AD bits are not preset) or |
1137 | * PTE is in IO space and can't be updated atomically. | |
3b57254d | 1138 | */ |
59688aa0 RH |
1139 | return TRANSLATE_FAIL; |
1140 | } | |
1141 | } | |
2bacb224 | 1142 | |
59688aa0 RH |
1143 | /* For superpage mappings, make a fake leaf PTE for the TLB's benefit. */ |
1144 | target_ulong vpn = addr >> PGSHIFT; | |
0c3e702a | 1145 | |
59688aa0 RH |
1146 | if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { |
1147 | napot_bits = ctzl(ppn) + 1; | |
1148 | if ((i != (levels - 1)) || (napot_bits != 4)) { | |
1149 | return TRANSLATE_FAIL; | |
0c3e702a MC |
1150 | } |
1151 | } | |
59688aa0 RH |
1152 | |
1153 | napot_mask = (1 << napot_bits) - 1; | |
1154 | *physical = (((ppn & ~napot_mask) | (vpn & napot_mask) | | |
1155 | (vpn & (((target_ulong)1 << ptshift) - 1)) | |
1156 | ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK); | |
1157 | ||
59688aa0 | 1158 | /* |
e1dd1507 RH |
1159 | * Remove write permission unless this is a store, or the page is |
1160 | * already dirty, so that we TLB miss on later writes to update | |
1161 | * the dirty bit. | |
59688aa0 | 1162 | */ |
e1dd1507 RH |
1163 | if (access_type != MMU_DATA_STORE && !(pte & PTE_D)) { |
1164 | prot &= ~PAGE_WRITE; | |
59688aa0 | 1165 | } |
e1dd1507 RH |
1166 | *ret_prot = prot; |
1167 | ||
59688aa0 | 1168 | return TRANSLATE_SUCCESS; |
0c3e702a MC |
1169 | } |
1170 | ||
1171 | static void raise_mmu_exception(CPURISCVState *env, target_ulong address, | |
1448689c | 1172 | MMUAccessType access_type, bool pmp_violation, |
8e2aa21b AP |
1173 | bool first_stage, bool two_stage, |
1174 | bool two_stage_indirect) | |
0c3e702a | 1175 | { |
3109cd98 | 1176 | CPUState *cs = env_cpu(env); |
994b6bb2 | 1177 | |
0c3e702a MC |
1178 | switch (access_type) { |
1179 | case MMU_INST_FETCH: | |
38256529 | 1180 | if (env->virt_enabled && !first_stage) { |
b2ef6ab9 AF |
1181 | cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT; |
1182 | } else { | |
82d53adf IK |
1183 | cs->exception_index = pmp_violation ? |
1184 | RISCV_EXCP_INST_ACCESS_FAULT : RISCV_EXCP_INST_PAGE_FAULT; | |
b2ef6ab9 | 1185 | } |
0c3e702a MC |
1186 | break; |
1187 | case MMU_DATA_LOAD: | |
1c1c060a | 1188 | if (two_stage && !first_stage) { |
b2ef6ab9 AF |
1189 | cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; |
1190 | } else { | |
82d53adf IK |
1191 | cs->exception_index = pmp_violation ? |
1192 | RISCV_EXCP_LOAD_ACCESS_FAULT : RISCV_EXCP_LOAD_PAGE_FAULT; | |
b2ef6ab9 | 1193 | } |
0c3e702a MC |
1194 | break; |
1195 | case MMU_DATA_STORE: | |
1c1c060a | 1196 | if (two_stage && !first_stage) { |
b2ef6ab9 AF |
1197 | cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT; |
1198 | } else { | |
82d53adf IK |
1199 | cs->exception_index = pmp_violation ? |
1200 | RISCV_EXCP_STORE_AMO_ACCESS_FAULT : | |
1201 | RISCV_EXCP_STORE_PAGE_FAULT; | |
b2ef6ab9 | 1202 | } |
0c3e702a MC |
1203 | break; |
1204 | default: | |
1205 | g_assert_not_reached(); | |
1206 | } | |
1207 | env->badaddr = address; | |
ec352d0c | 1208 | env->two_stage_lookup = two_stage; |
8e2aa21b | 1209 | env->two_stage_indirect_lookup = two_stage_indirect; |
0c3e702a MC |
1210 | } |
1211 | ||
1212 | hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) | |
1213 | { | |
1214 | RISCVCPU *cpu = RISCV_CPU(cs); | |
36a18664 | 1215 | CPURISCVState *env = &cpu->env; |
0c3e702a MC |
1216 | hwaddr phys_addr; |
1217 | int prot; | |
d9996d09 | 1218 | int mmu_idx = riscv_env_mmu_index(&cpu->env, false); |
0c3e702a | 1219 | |
33a9a57d | 1220 | if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx, |
38256529 | 1221 | true, env->virt_enabled, true)) { |
0c3e702a MC |
1222 | return -1; |
1223 | } | |
36a18664 | 1224 | |
38256529 | 1225 | if (env->virt_enabled) { |
33a9a57d | 1226 | if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL, |
6979b7b3 | 1227 | 0, MMUIdx_U, false, true, true)) { |
36a18664 AF |
1228 | return -1; |
1229 | } | |
1230 | } | |
1231 | ||
9ef82119 | 1232 | return phys_addr & TARGET_PAGE_MASK; |
0c3e702a MC |
1233 | } |
1234 | ||
37207e12 PD |
1235 | void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, |
1236 | vaddr addr, unsigned size, | |
1237 | MMUAccessType access_type, | |
1238 | int mmu_idx, MemTxAttrs attrs, | |
1239 | MemTxResult response, uintptr_t retaddr) | |
cbf58276 MC |
1240 | { |
1241 | RISCVCPU *cpu = RISCV_CPU(cs); | |
1242 | CPURISCVState *env = &cpu->env; | |
1243 | ||
37207e12 | 1244 | if (access_type == MMU_DATA_STORE) { |
cbf58276 | 1245 | cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; |
f9e580c1 | 1246 | } else if (access_type == MMU_DATA_LOAD) { |
cbf58276 | 1247 | cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; |
f9e580c1 EB |
1248 | } else { |
1249 | cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT; | |
cbf58276 MC |
1250 | } |
1251 | ||
1252 | env->badaddr = addr; | |
696bacde | 1253 | env->two_stage_lookup = mmuidx_2stage(mmu_idx); |
8e2aa21b | 1254 | env->two_stage_indirect_lookup = false; |
ac684717 | 1255 | cpu_loop_exit_restore(cs, retaddr); |
cbf58276 MC |
1256 | } |
1257 | ||
0c3e702a MC |
1258 | void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, |
1259 | MMUAccessType access_type, int mmu_idx, | |
1260 | uintptr_t retaddr) | |
1261 | { | |
1262 | RISCVCPU *cpu = RISCV_CPU(cs); | |
1263 | CPURISCVState *env = &cpu->env; | |
1264 | switch (access_type) { | |
1265 | case MMU_INST_FETCH: | |
1266 | cs->exception_index = RISCV_EXCP_INST_ADDR_MIS; | |
1267 | break; | |
1268 | case MMU_DATA_LOAD: | |
1269 | cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS; | |
1270 | break; | |
1271 | case MMU_DATA_STORE: | |
1272 | cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS; | |
1273 | break; | |
1274 | default: | |
1275 | g_assert_not_reached(); | |
1276 | } | |
1277 | env->badaddr = addr; | |
696bacde | 1278 | env->two_stage_lookup = mmuidx_2stage(mmu_idx); |
8e2aa21b | 1279 | env->two_stage_indirect_lookup = false; |
ac684717 | 1280 | cpu_loop_exit_restore(cs, retaddr); |
0c3e702a | 1281 | } |
0c3e702a | 1282 | |
892320fa AP |
1283 | |
1284 | static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type) | |
1285 | { | |
1286 | enum riscv_pmu_event_idx pmu_event_type; | |
1287 | ||
1288 | switch (access_type) { | |
1289 | case MMU_INST_FETCH: | |
1290 | pmu_event_type = RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS; | |
1291 | break; | |
1292 | case MMU_DATA_LOAD: | |
1293 | pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS; | |
1294 | break; | |
1295 | case MMU_DATA_STORE: | |
1296 | pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS; | |
1297 | break; | |
1298 | default: | |
1299 | return; | |
1300 | } | |
1301 | ||
1302 | riscv_pmu_incr_ctr(cpu, pmu_event_type); | |
1303 | } | |
1304 | ||
8a4ca3c1 RH |
1305 | bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
1306 | MMUAccessType access_type, int mmu_idx, | |
1307 | bool probe, uintptr_t retaddr) | |
0c3e702a MC |
1308 | { |
1309 | RISCVCPU *cpu = RISCV_CPU(cs); | |
1310 | CPURISCVState *env = &cpu->env; | |
36a18664 | 1311 | vaddr im_address; |
0c3e702a | 1312 | hwaddr pa = 0; |
b297129a | 1313 | int prot, prot2, prot_pmp; |
635b0b0e | 1314 | bool pmp_violation = false; |
36a18664 | 1315 | bool first_stage_error = true; |
696bacde | 1316 | bool two_stage_lookup = mmuidx_2stage(mmu_idx); |
8e2aa21b | 1317 | bool two_stage_indirect_error = false; |
0c3e702a | 1318 | int ret = TRANSLATE_FAIL; |
e06adebb | 1319 | int mode = mmuidx_priv(mmu_idx); |
b297129a JS |
1320 | /* default TLB page size */ |
1321 | target_ulong tlb_size = TARGET_PAGE_SIZE; | |
0c3e702a | 1322 | |
36a18664 AF |
1323 | env->guest_phys_fault_addr = 0; |
1324 | ||
8a4ca3c1 RH |
1325 | qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", |
1326 | __func__, address, access_type, mmu_idx); | |
1327 | ||
eacd03cb | 1328 | pmu_tlb_fill_incr_ctr(cpu, access_type); |
696bacde | 1329 | if (two_stage_lookup) { |
36a18664 | 1330 | /* Two stage lookup */ |
33a9a57d YJ |
1331 | ret = get_physical_address(env, &pa, &prot, address, |
1332 | &env->guest_phys_fault_addr, access_type, | |
11c27c6d | 1333 | mmu_idx, true, true, false); |
36a18664 | 1334 | |
33a9a57d YJ |
1335 | /* |
1336 | * A G-stage exception may be triggered during two state lookup. | |
1337 | * And the env->guest_phys_fault_addr has already been set in | |
1338 | * get_physical_address(). | |
1339 | */ | |
1340 | if (ret == TRANSLATE_G_STAGE_FAIL) { | |
1341 | first_stage_error = false; | |
8e2aa21b | 1342 | two_stage_indirect_error = true; |
33a9a57d YJ |
1343 | } |
1344 | ||
36a18664 AF |
1345 | qemu_log_mask(CPU_LOG_MMU, |
1346 | "%s 1st-stage address=%" VADDR_PRIx " ret %d physical " | |
883f2c59 | 1347 | HWADDR_FMT_plx " prot %d\n", |
36a18664 AF |
1348 | __func__, address, ret, pa, prot); |
1349 | ||
33a9a57d | 1350 | if (ret == TRANSLATE_SUCCESS) { |
36a18664 AF |
1351 | /* Second stage lookup */ |
1352 | im_address = pa; | |
1353 | ||
33a9a57d | 1354 | ret = get_physical_address(env, &pa, &prot2, im_address, NULL, |
a427c836 | 1355 | access_type, MMUIdx_U, false, true, |
11c27c6d | 1356 | false); |
36a18664 AF |
1357 | |
1358 | qemu_log_mask(CPU_LOG_MMU, | |
c45eff30 WL |
1359 | "%s 2nd-stage address=%" VADDR_PRIx |
1360 | " ret %d physical " | |
1361 | HWADDR_FMT_plx " prot %d\n", | |
1362 | __func__, im_address, ret, pa, prot2); | |
8f67cd6d AF |
1363 | |
1364 | prot &= prot2; | |
36a18664 | 1365 | |
b297129a | 1366 | if (ret == TRANSLATE_SUCCESS) { |
bfc7ee12 | 1367 | ret = get_physical_address_pmp(env, &prot_pmp, pa, |
b297129a | 1368 | size, access_type, mode); |
bfc7ee12 | 1369 | tlb_size = pmp_get_tlb_size(env, pa); |
663e1193 JS |
1370 | |
1371 | qemu_log_mask(CPU_LOG_MMU, | |
883f2c59 | 1372 | "%s PMP address=" HWADDR_FMT_plx " ret %d prot" |
663e1193 JS |
1373 | " %d tlb_size " TARGET_FMT_lu "\n", |
1374 | __func__, pa, ret, prot_pmp, tlb_size); | |
1375 | ||
b297129a | 1376 | prot &= prot_pmp; |
36a18664 AF |
1377 | } |
1378 | ||
1379 | if (ret != TRANSLATE_SUCCESS) { | |
1380 | /* | |
1381 | * Guest physical address translation failed, this is a HS | |
1382 | * level exception | |
1383 | */ | |
1384 | first_stage_error = false; | |
1385 | env->guest_phys_fault_addr = (im_address | | |
1386 | (address & | |
1387 | (TARGET_PAGE_SIZE - 1))) >> 2; | |
1388 | } | |
1389 | } | |
1390 | } else { | |
1391 | /* Single stage lookup */ | |
33a9a57d | 1392 | ret = get_physical_address(env, &pa, &prot, address, NULL, |
11c27c6d | 1393 | access_type, mmu_idx, true, false, false); |
36a18664 AF |
1394 | |
1395 | qemu_log_mask(CPU_LOG_MMU, | |
1396 | "%s address=%" VADDR_PRIx " ret %d physical " | |
883f2c59 | 1397 | HWADDR_FMT_plx " prot %d\n", |
36a18664 | 1398 | __func__, address, ret, pa, prot); |
8a4ca3c1 | 1399 | |
b297129a | 1400 | if (ret == TRANSLATE_SUCCESS) { |
bfc7ee12 | 1401 | ret = get_physical_address_pmp(env, &prot_pmp, pa, |
b297129a | 1402 | size, access_type, mode); |
bfc7ee12 | 1403 | tlb_size = pmp_get_tlb_size(env, pa); |
663e1193 JS |
1404 | |
1405 | qemu_log_mask(CPU_LOG_MMU, | |
883f2c59 | 1406 | "%s PMP address=" HWADDR_FMT_plx " ret %d prot" |
663e1193 JS |
1407 | " %d tlb_size " TARGET_FMT_lu "\n", |
1408 | __func__, pa, ret, prot_pmp, tlb_size); | |
1409 | ||
b297129a JS |
1410 | prot &= prot_pmp; |
1411 | } | |
1f447aec | 1412 | } |
b297129a | 1413 | |
1f447aec | 1414 | if (ret == TRANSLATE_PMP_FAIL) { |
635b0b0e | 1415 | pmp_violation = true; |
0c3e702a | 1416 | } |
36a18664 | 1417 | |
0c3e702a | 1418 | if (ret == TRANSLATE_SUCCESS) { |
b297129a JS |
1419 | tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1), |
1420 | prot, mmu_idx, tlb_size); | |
8a4ca3c1 RH |
1421 | return true; |
1422 | } else if (probe) { | |
1423 | return false; | |
1424 | } else { | |
1c1c060a | 1425 | raise_mmu_exception(env, address, access_type, pmp_violation, |
696bacde | 1426 | first_stage_error, two_stage_lookup, |
8e2aa21b | 1427 | two_stage_indirect_error); |
ac684717 | 1428 | cpu_loop_exit_restore(cs, retaddr); |
0c3e702a | 1429 | } |
36a18664 AF |
1430 | |
1431 | return true; | |
0c3e702a | 1432 | } |
8e2aa21b AP |
1433 | |
1434 | static target_ulong riscv_transformed_insn(CPURISCVState *env, | |
1435 | target_ulong insn, | |
1436 | target_ulong taddr) | |
1437 | { | |
1438 | target_ulong xinsn = 0; | |
1439 | target_ulong access_rs1 = 0, access_imm = 0, access_size = 0; | |
1440 | ||
1441 | /* | |
1442 | * Only Quadrant 0 and Quadrant 2 of RVC instruction space need to | |
1443 | * be uncompressed. The Quadrant 1 of RVC instruction space need | |
1444 | * not be transformed because these instructions won't generate | |
1445 | * any load/store trap. | |
1446 | */ | |
1447 | ||
1448 | if ((insn & 0x3) != 0x3) { | |
1449 | /* Transform 16bit instruction into 32bit instruction */ | |
1450 | switch (GET_C_OP(insn)) { | |
1451 | case OPC_RISC_C_OP_QUAD0: /* Quadrant 0 */ | |
1452 | switch (GET_C_FUNC(insn)) { | |
1453 | case OPC_RISC_C_FUNC_FLD_LQ: | |
1454 | if (riscv_cpu_xlen(env) != 128) { /* C.FLD (RV32/64) */ | |
1455 | xinsn = OPC_RISC_FLD; | |
1456 | xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); | |
1457 | access_rs1 = GET_C_RS1S(insn); | |
1458 | access_imm = GET_C_LD_IMM(insn); | |
1459 | access_size = 8; | |
1460 | } | |
1461 | break; | |
1462 | case OPC_RISC_C_FUNC_LW: /* C.LW */ | |
1463 | xinsn = OPC_RISC_LW; | |
1464 | xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); | |
1465 | access_rs1 = GET_C_RS1S(insn); | |
1466 | access_imm = GET_C_LW_IMM(insn); | |
1467 | access_size = 4; | |
1468 | break; | |
1469 | case OPC_RISC_C_FUNC_FLW_LD: | |
1470 | if (riscv_cpu_xlen(env) == 32) { /* C.FLW (RV32) */ | |
1471 | xinsn = OPC_RISC_FLW; | |
1472 | xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); | |
1473 | access_rs1 = GET_C_RS1S(insn); | |
1474 | access_imm = GET_C_LW_IMM(insn); | |
1475 | access_size = 4; | |
1476 | } else { /* C.LD (RV64/RV128) */ | |
1477 | xinsn = OPC_RISC_LD; | |
1478 | xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); | |
1479 | access_rs1 = GET_C_RS1S(insn); | |
1480 | access_imm = GET_C_LD_IMM(insn); | |
1481 | access_size = 8; | |
1482 | } | |
1483 | break; | |
1484 | case OPC_RISC_C_FUNC_FSD_SQ: | |
1485 | if (riscv_cpu_xlen(env) != 128) { /* C.FSD (RV32/64) */ | |
1486 | xinsn = OPC_RISC_FSD; | |
1487 | xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); | |
1488 | access_rs1 = GET_C_RS1S(insn); | |
1489 | access_imm = GET_C_SD_IMM(insn); | |
1490 | access_size = 8; | |
1491 | } | |
1492 | break; | |
1493 | case OPC_RISC_C_FUNC_SW: /* C.SW */ | |
1494 | xinsn = OPC_RISC_SW; | |
1495 | xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); | |
1496 | access_rs1 = GET_C_RS1S(insn); | |
1497 | access_imm = GET_C_SW_IMM(insn); | |
1498 | access_size = 4; | |
1499 | break; | |
1500 | case OPC_RISC_C_FUNC_FSW_SD: | |
1501 | if (riscv_cpu_xlen(env) == 32) { /* C.FSW (RV32) */ | |
1502 | xinsn = OPC_RISC_FSW; | |
1503 | xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); | |
1504 | access_rs1 = GET_C_RS1S(insn); | |
1505 | access_imm = GET_C_SW_IMM(insn); | |
1506 | access_size = 4; | |
1507 | } else { /* C.SD (RV64/RV128) */ | |
1508 | xinsn = OPC_RISC_SD; | |
1509 | xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); | |
1510 | access_rs1 = GET_C_RS1S(insn); | |
1511 | access_imm = GET_C_SD_IMM(insn); | |
1512 | access_size = 8; | |
1513 | } | |
1514 | break; | |
1515 | default: | |
1516 | break; | |
1517 | } | |
1518 | break; | |
1519 | case OPC_RISC_C_OP_QUAD2: /* Quadrant 2 */ | |
1520 | switch (GET_C_FUNC(insn)) { | |
1521 | case OPC_RISC_C_FUNC_FLDSP_LQSP: | |
1522 | if (riscv_cpu_xlen(env) != 128) { /* C.FLDSP (RV32/64) */ | |
1523 | xinsn = OPC_RISC_FLD; | |
1524 | xinsn = SET_RD(xinsn, GET_C_RD(insn)); | |
1525 | access_rs1 = 2; | |
1526 | access_imm = GET_C_LDSP_IMM(insn); | |
1527 | access_size = 8; | |
1528 | } | |
1529 | break; | |
1530 | case OPC_RISC_C_FUNC_LWSP: /* C.LWSP */ | |
1531 | xinsn = OPC_RISC_LW; | |
1532 | xinsn = SET_RD(xinsn, GET_C_RD(insn)); | |
1533 | access_rs1 = 2; | |
1534 | access_imm = GET_C_LWSP_IMM(insn); | |
1535 | access_size = 4; | |
1536 | break; | |
1537 | case OPC_RISC_C_FUNC_FLWSP_LDSP: | |
1538 | if (riscv_cpu_xlen(env) == 32) { /* C.FLWSP (RV32) */ | |
1539 | xinsn = OPC_RISC_FLW; | |
1540 | xinsn = SET_RD(xinsn, GET_C_RD(insn)); | |
1541 | access_rs1 = 2; | |
1542 | access_imm = GET_C_LWSP_IMM(insn); | |
1543 | access_size = 4; | |
1544 | } else { /* C.LDSP (RV64/RV128) */ | |
1545 | xinsn = OPC_RISC_LD; | |
1546 | xinsn = SET_RD(xinsn, GET_C_RD(insn)); | |
1547 | access_rs1 = 2; | |
1548 | access_imm = GET_C_LDSP_IMM(insn); | |
1549 | access_size = 8; | |
1550 | } | |
1551 | break; | |
1552 | case OPC_RISC_C_FUNC_FSDSP_SQSP: | |
1553 | if (riscv_cpu_xlen(env) != 128) { /* C.FSDSP (RV32/64) */ | |
1554 | xinsn = OPC_RISC_FSD; | |
1555 | xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); | |
1556 | access_rs1 = 2; | |
1557 | access_imm = GET_C_SDSP_IMM(insn); | |
1558 | access_size = 8; | |
1559 | } | |
1560 | break; | |
1561 | case OPC_RISC_C_FUNC_SWSP: /* C.SWSP */ | |
1562 | xinsn = OPC_RISC_SW; | |
1563 | xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); | |
1564 | access_rs1 = 2; | |
1565 | access_imm = GET_C_SWSP_IMM(insn); | |
1566 | access_size = 4; | |
1567 | break; | |
1568 | case 7: | |
1569 | if (riscv_cpu_xlen(env) == 32) { /* C.FSWSP (RV32) */ | |
1570 | xinsn = OPC_RISC_FSW; | |
1571 | xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); | |
1572 | access_rs1 = 2; | |
1573 | access_imm = GET_C_SWSP_IMM(insn); | |
1574 | access_size = 4; | |
1575 | } else { /* C.SDSP (RV64/RV128) */ | |
1576 | xinsn = OPC_RISC_SD; | |
1577 | xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); | |
1578 | access_rs1 = 2; | |
1579 | access_imm = GET_C_SDSP_IMM(insn); | |
1580 | access_size = 8; | |
1581 | } | |
1582 | break; | |
1583 | default: | |
1584 | break; | |
1585 | } | |
1586 | break; | |
1587 | default: | |
1588 | break; | |
1589 | } | |
1590 | ||
1591 | /* | |
1592 | * Clear Bit1 of transformed instruction to indicate that | |
1593 | * original insruction was a 16bit instruction | |
1594 | */ | |
1595 | xinsn &= ~((target_ulong)0x2); | |
1596 | } else { | |
1597 | /* Transform 32bit (or wider) instructions */ | |
1598 | switch (MASK_OP_MAJOR(insn)) { | |
1599 | case OPC_RISC_ATOMIC: | |
1600 | xinsn = insn; | |
1601 | access_rs1 = GET_RS1(insn); | |
1602 | access_size = 1 << GET_FUNCT3(insn); | |
1603 | break; | |
1604 | case OPC_RISC_LOAD: | |
1605 | case OPC_RISC_FP_LOAD: | |
1606 | xinsn = SET_I_IMM(insn, 0); | |
1607 | access_rs1 = GET_RS1(insn); | |
1608 | access_imm = GET_IMM(insn); | |
1609 | access_size = 1 << GET_FUNCT3(insn); | |
1610 | break; | |
1611 | case OPC_RISC_STORE: | |
1612 | case OPC_RISC_FP_STORE: | |
1613 | xinsn = SET_S_IMM(insn, 0); | |
1614 | access_rs1 = GET_RS1(insn); | |
1615 | access_imm = GET_STORE_IMM(insn); | |
1616 | access_size = 1 << GET_FUNCT3(insn); | |
1617 | break; | |
1618 | case OPC_RISC_SYSTEM: | |
1619 | if (MASK_OP_SYSTEM(insn) == OPC_RISC_HLVHSV) { | |
1620 | xinsn = insn; | |
1621 | access_rs1 = GET_RS1(insn); | |
1622 | access_size = 1 << ((GET_FUNCT7(insn) >> 1) & 0x3); | |
1623 | access_size = 1 << access_size; | |
1624 | } | |
1625 | break; | |
1626 | default: | |
1627 | break; | |
1628 | } | |
1629 | } | |
1630 | ||
1631 | if (access_size) { | |
1632 | xinsn = SET_RS1(xinsn, (taddr - (env->gpr[access_rs1] + access_imm)) & | |
1633 | (access_size - 1)); | |
1634 | } | |
1635 | ||
1636 | return xinsn; | |
1637 | } | |
263e2ab2 | 1638 | #endif /* !CONFIG_USER_ONLY */ |
0c3e702a MC |
1639 | |
1640 | /* | |
1641 | * Handle Traps | |
1642 | * | |
1643 | * Adapted from Spike's processor_t::take_trap. | |
1644 | * | |
1645 | */ | |
1646 | void riscv_cpu_do_interrupt(CPUState *cs) | |
1647 | { | |
1648 | #if !defined(CONFIG_USER_ONLY) | |
1649 | ||
1650 | RISCVCPU *cpu = RISCV_CPU(cs); | |
1651 | CPURISCVState *env = &cpu->env; | |
86d0c457 | 1652 | bool write_gva = false; |
284d697c | 1653 | uint64_t s; |
0c3e702a | 1654 | |
3b57254d WL |
1655 | /* |
1656 | * cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide | |
acbbb94e MC |
1657 | * so we mask off the MSB and separate into trap type and cause. |
1658 | */ | |
1659 | bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG); | |
1660 | target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; | |
d028ac75 | 1661 | uint64_t deleg = async ? env->mideleg : env->medeleg; |
1697837e RK |
1662 | bool s_injected = env->mvip & (1 << cause) & env->mvien && |
1663 | !(env->mip & (1 << cause)); | |
40336d5b RK |
1664 | bool vs_injected = env->hvip & (1 << cause) & env->hvien && |
1665 | !(env->mip & (1 << cause)); | |
acbbb94e | 1666 | target_ulong tval = 0; |
8e2aa21b | 1667 | target_ulong tinst = 0; |
30675539 AF |
1668 | target_ulong htval = 0; |
1669 | target_ulong mtval2 = 0; | |
acbbb94e | 1670 | |
acbbb94e MC |
1671 | if (!async) { |
1672 | /* set tval to badaddr for traps with address information */ | |
1673 | switch (cause) { | |
d17bcae5 RK |
1674 | case RISCV_EXCP_SEMIHOST: |
1675 | do_common_semihosting(cs); | |
1676 | env->pc += 4; | |
1677 | return; | |
ab67a1d0 AF |
1678 | case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: |
1679 | case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: | |
acbbb94e MC |
1680 | case RISCV_EXCP_LOAD_ADDR_MIS: |
1681 | case RISCV_EXCP_STORE_AMO_ADDR_MIS: | |
1682 | case RISCV_EXCP_LOAD_ACCESS_FAULT: | |
1683 | case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: | |
acbbb94e MC |
1684 | case RISCV_EXCP_LOAD_PAGE_FAULT: |
1685 | case RISCV_EXCP_STORE_PAGE_FAULT: | |
24826da0 | 1686 | write_gva = env->two_stage_lookup; |
acbbb94e | 1687 | tval = env->badaddr; |
8e2aa21b AP |
1688 | if (env->two_stage_indirect_lookup) { |
1689 | /* | |
1690 | * special pseudoinstruction for G-stage fault taken while | |
1691 | * doing VS-stage page table walk. | |
1692 | */ | |
1693 | tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000; | |
1694 | } else { | |
1695 | /* | |
1696 | * The "Addr. Offset" field in transformed instruction is | |
1697 | * non-zero only for misaligned access. | |
1698 | */ | |
1699 | tinst = riscv_transformed_insn(env, env->bins, tval); | |
1700 | } | |
1701 | break; | |
1702 | case RISCV_EXCP_INST_GUEST_PAGE_FAULT: | |
1703 | case RISCV_EXCP_INST_ADDR_MIS: | |
1704 | case RISCV_EXCP_INST_ACCESS_FAULT: | |
1705 | case RISCV_EXCP_INST_PAGE_FAULT: | |
1706 | write_gva = env->two_stage_lookup; | |
1707 | tval = env->badaddr; | |
1708 | if (env->two_stage_indirect_lookup) { | |
1709 | /* | |
1710 | * special pseudoinstruction for G-stage fault taken while | |
1711 | * doing VS-stage page table walk. | |
1712 | */ | |
1713 | tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000; | |
1714 | } | |
acbbb94e | 1715 | break; |
48eaeb56 | 1716 | case RISCV_EXCP_ILLEGAL_INST: |
62cf0245 | 1717 | case RISCV_EXCP_VIRT_INSTRUCTION_FAULT: |
48eaeb56 AF |
1718 | tval = env->bins; |
1719 | break; | |
26934f9a SM |
1720 | case RISCV_EXCP_BREAKPOINT: |
1721 | if (cs->watchpoint_hit) { | |
1722 | tval = cs->watchpoint_hit->hitaddr; | |
1723 | cs->watchpoint_hit = NULL; | |
1724 | } | |
1725 | break; | |
acbbb94e MC |
1726 | default: |
1727 | break; | |
0c3e702a | 1728 | } |
acbbb94e MC |
1729 | /* ecall is dispatched as one cause so translate based on mode */ |
1730 | if (cause == RISCV_EXCP_U_ECALL) { | |
1731 | assert(env->priv <= 3); | |
5eb9e782 AF |
1732 | |
1733 | if (env->priv == PRV_M) { | |
1734 | cause = RISCV_EXCP_M_ECALL; | |
38256529 | 1735 | } else if (env->priv == PRV_S && env->virt_enabled) { |
5eb9e782 | 1736 | cause = RISCV_EXCP_VS_ECALL; |
38256529 | 1737 | } else if (env->priv == PRV_S && !env->virt_enabled) { |
5eb9e782 AF |
1738 | cause = RISCV_EXCP_S_ECALL; |
1739 | } else if (env->priv == PRV_U) { | |
1740 | cause = RISCV_EXCP_U_ECALL; | |
1741 | } | |
0c3e702a MC |
1742 | } |
1743 | } | |
1744 | ||
c51a3f5d | 1745 | trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, |
69430111 AF |
1746 | riscv_cpu_get_trap_name(cause, async)); |
1747 | ||
1748 | qemu_log_mask(CPU_LOG_INT, | |
1749 | "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", " | |
1750 | "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n", | |
1751 | __func__, env->mhartid, async, cause, env->pc, tval, | |
1752 | riscv_cpu_get_trap_name(cause, async)); | |
0c3e702a | 1753 | |
1697837e | 1754 | if (env->priv <= PRV_S && cause < 64 && |
40336d5b | 1755 | (((deleg >> cause) & 1) || s_injected || vs_injected)) { |
0c3e702a | 1756 | /* handle the trap in S-mode */ |
5eb9e782 | 1757 | if (riscv_has_ext(env, RVH)) { |
d028ac75 | 1758 | uint64_t hdeleg = async ? env->hideleg : env->hedeleg; |
1c1c060a | 1759 | |
40336d5b RK |
1760 | if (env->virt_enabled && |
1761 | (((hdeleg >> cause) & 1) || vs_injected)) { | |
84b1c04b | 1762 | /* Trap to VS mode */ |
c5969a3a RK |
1763 | /* |
1764 | * See if we need to adjust cause. Yes if its VS mode interrupt | |
1765 | * no if hypervisor has delegated one of hs mode's interrupt | |
1766 | */ | |
1525d8aa AF |
1767 | if (async && (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || |
1768 | cause == IRQ_VS_EXT)) { | |
c5969a3a | 1769 | cause = cause - 1; |
84b1c04b | 1770 | } |
86d0c457 | 1771 | write_gva = false; |
38256529 | 1772 | } else if (env->virt_enabled) { |
5eb9e782 AF |
1773 | /* Trap into HS mode, from virt */ |
1774 | riscv_cpu_swap_hypervisor_regs(env); | |
f2d5850f | 1775 | env->hstatus = set_field(env->hstatus, HSTATUS_SPVP, |
ace54453 | 1776 | env->priv); |
2136b6c3 | 1777 | env->hstatus = set_field(env->hstatus, HSTATUS_SPV, true); |
86d0c457 | 1778 | |
30675539 AF |
1779 | htval = env->guest_phys_fault_addr; |
1780 | ||
5eb9e782 | 1781 | riscv_cpu_set_virt_enabled(env, 0); |
5eb9e782 AF |
1782 | } else { |
1783 | /* Trap into HS mode */ | |
ec352d0c | 1784 | env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false); |
30675539 | 1785 | htval = env->guest_phys_fault_addr; |
5eb9e782 | 1786 | } |
86d0c457 | 1787 | env->hstatus = set_field(env->hstatus, HSTATUS_GVA, write_gva); |
5eb9e782 AF |
1788 | } |
1789 | ||
1790 | s = env->mstatus; | |
1a9540d1 | 1791 | s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); |
0c3e702a MC |
1792 | s = set_field(s, MSTATUS_SPP, env->priv); |
1793 | s = set_field(s, MSTATUS_SIE, 0); | |
c7b95171 | 1794 | env->mstatus = s; |
16fdb8ff | 1795 | env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1)); |
acbbb94e | 1796 | env->sepc = env->pc; |
ac12b601 | 1797 | env->stval = tval; |
30675539 | 1798 | env->htval = htval; |
8e2aa21b | 1799 | env->htinst = tinst; |
acbbb94e | 1800 | env->pc = (env->stvec >> 2 << 2) + |
c45eff30 | 1801 | ((async && (env->stvec & 3) == 1) ? cause * 4 : 0); |
fb738839 | 1802 | riscv_cpu_set_mode(env, PRV_S); |
0c3e702a | 1803 | } else { |
acbbb94e | 1804 | /* handle the trap in M-mode */ |
5eb9e782 | 1805 | if (riscv_has_ext(env, RVH)) { |
38256529 | 1806 | if (env->virt_enabled) { |
5eb9e782 AF |
1807 | riscv_cpu_swap_hypervisor_regs(env); |
1808 | } | |
1809 | env->mstatus = set_field(env->mstatus, MSTATUS_MPV, | |
38256529 WL |
1810 | env->virt_enabled); |
1811 | if (env->virt_enabled && tval) { | |
9034e90a AF |
1812 | env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1); |
1813 | } | |
5eb9e782 | 1814 | |
30675539 AF |
1815 | mtval2 = env->guest_phys_fault_addr; |
1816 | ||
5eb9e782 AF |
1817 | /* Trapping to M mode, virt is disabled */ |
1818 | riscv_cpu_set_virt_enabled(env, 0); | |
5eb9e782 AF |
1819 | } |
1820 | ||
1821 | s = env->mstatus; | |
1a9540d1 | 1822 | s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); |
0c3e702a MC |
1823 | s = set_field(s, MSTATUS_MPP, env->priv); |
1824 | s = set_field(s, MSTATUS_MIE, 0); | |
c7b95171 | 1825 | env->mstatus = s; |
acbbb94e MC |
1826 | env->mcause = cause | ~(((target_ulong)-1) >> async); |
1827 | env->mepc = env->pc; | |
ac12b601 | 1828 | env->mtval = tval; |
30675539 | 1829 | env->mtval2 = mtval2; |
8e2aa21b | 1830 | env->mtinst = tinst; |
acbbb94e | 1831 | env->pc = (env->mtvec >> 2 << 2) + |
c45eff30 | 1832 | ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); |
fb738839 | 1833 | riscv_cpu_set_mode(env, PRV_M); |
0c3e702a | 1834 | } |
d9360e96 | 1835 | |
3b57254d WL |
1836 | /* |
1837 | * NOTE: it is not necessary to yield load reservations here. It is only | |
d9360e96 MC |
1838 | * necessary for an SC from "another hart" to cause a load reservation |
1839 | * to be yielded. Refer to the memory consistency model section of the | |
1840 | * RISC-V ISA Specification. | |
1841 | */ | |
1842 | ||
ec352d0c | 1843 | env->two_stage_lookup = false; |
8e2aa21b | 1844 | env->two_stage_indirect_lookup = false; |
0c3e702a | 1845 | #endif |
330d2ae3 | 1846 | cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */ |
0c3e702a | 1847 | } |